covered-0.7.10/0000755000076500007650000000000011475644735013262 5ustar trevorwtrevorwcovered-0.7.10/acinclude.m40000644000076500007650000003625511052400242015434 0ustar trevorwtrevorw### covered.m4 -- extra macros for configuring Covered -*- Autoconf -*- ## COVERED_PATH_TCL_CONFIG ## ------------------ ## Try finding tclConfig.sh in common library directories and their ## tcl$x.$y subdirectories. Set shell variable r_cv_path_TCL_CONFIG ## to the entire path of the script if found, and leave it empty ## otherwise. AC_DEFUN([COVERED_PATH_TCL_CONFIG], [AC_MSG_CHECKING([for tclConfig.sh in library (sub)directories]) AC_CACHE_VAL([r_cv_path_TCL_CONFIG], [for ldir in /opt/lib /sw/lib /usr/local/lib /usr/lib /lib /usr/lib64 ; do for dir in \ ${ldir} \ `ls -d ${ldir}/tcl[[8-9]].[[0-9]]* 2>/dev/null | sort -r`; do if test -f ${dir}/tclConfig.sh; then r_cv_path_TCL_CONFIG="${dir}/tclConfig.sh" break 2 fi done done]) if test -n "${r_cv_path_TCL_CONFIG}"; then AC_MSG_RESULT([${r_cv_path_TCL_CONFIG}]) else AC_MSG_RESULT([no]) fi ])# COVERED_PATH_TCL_CONFIG ## COVERED_PATH_TK_CONFIG ## ------------------ ## Try finding tkConfig.sh in common library directories and their ## tk$x.$y subdirectories. Set shell variable r_cv_path_TK_CONFIG ## to the entire path of the script if found, and leave it empty ## otherwise. AC_DEFUN([COVERED_PATH_TK_CONFIG], [AC_MSG_CHECKING([for tkConfig.sh in library (sub)directories]) AC_CACHE_VAL([r_cv_path_TK_CONFIG], [for ldir in /opt/lib /sw/lib /usr/local/lib /usr/lib /lib /usr/lib64 ; do for dir in \ ${ldir} \ `ls -d ${ldir}/tk[[8-9]].[[0-9]]* 2>/dev/null | sort -r`; do if test -f ${dir}/tkConfig.sh; then r_cv_path_TK_CONFIG="${dir}/tkConfig.sh" break 2 fi done done]) if test -n "${r_cv_path_TK_CONFIG}"; then AC_MSG_RESULT([${r_cv_path_TK_CONFIG}]) else AC_MSG_RESULT([no]) fi ])# COVERED_PATH_TK_CONFIG ## COVERED_TCLTK_CONFIG ## --------------- ## Try finding the tclConfig.sh and tkConfig.sh scripts in PATH as well ## as in common library directories and their tcl/tk subdirectories. ## Set shell variables TCL_CONFIG and TK_CONFIG to the entire paths to ## the scripts if found and check that the corresponding Tcl/Tk versions ## are at least 8; if not, set shell variable have_tcltk to 'no'. AC_DEFUN([COVERED_TCLTK_CONFIG], [AC_PATH_PROGS(TCL_CONFIG, [${TCL_CONFIG} tclConfig.sh]) if test -z "${TCL_CONFIG}"; then COVERED_PATH_TCL_CONFIG if test -n "${r_cv_path_TCL_CONFIG}"; then TCL_CONFIG="${r_cv_path_TCL_CONFIG}" fi fi AC_PATH_PROGS(TK_CONFIG, [${TK_CONFIG} tkConfig.sh]) if test -z "${TK_CONFIG}"; then COVERED_PATH_TK_CONFIG if test -n "${r_cv_path_TK_CONFIG}"; then TK_CONFIG="${r_cv_path_TK_CONFIG}" fi fi if test -z "${TCLTK_CPPFLAGS}" \ || test -z "${TCLTK_LIBS}"; then ## Check whether the versions found via the *Config.sh files are at ## least 8; otherwise, issue a warning and turn off Tcl/Tk support. ## Note that in theory a system could have outdated versions of the ## *Config.sh scripts and yet up-to-date installations of Tcl/Tk in ## standard places ... if test -n "${TCL_CONFIG}"; then . ${TCL_CONFIG} if test ${TCL_MAJOR_VERSION} -lt 8; then warn_tcltk_version="Tcl/Tk support requires Tcl version >= 8" AC_MSG_WARN([${warn_tcltk_version}]) have_tcltk=no fi fi if test -n "${TK_CONFIG}" \ && test -z "${warn_tcltk_version}"; then . ${TK_CONFIG} if test ${TK_MAJOR_VERSION} -lt 8; then warn_tcltk_version="Tcl/Tk support requires Tk version >= 8" AC_MSG_WARN([${warn_tcltk_version}]) have_tcltk=no fi fi if test -n "${TCL_CONFIG}" \ && test -n "${TK_CONFIG}" \ && test -z "${warn_tcltk_version}"; then if test ${TCL_MAJOR_VERSION} -ne ${TK_MAJOR_VERSION} \ || test ${TCL_MINOR_VERSION} -ne ${TK_MINOR_VERSION}; then warn_tcltk_version="Tcl and Tk major or minor versions disagree" AC_MSG_WARN([${warn_tcltk_version}]) have_tcltk=no fi fi fi ])# COVERED_TCLTK_CONFIG ## COVERED_HEADER_TCL ## ------------- ## Set shell variable 'r_cv_header_tcl_h' to 'yes' if a recent enough ## 'tcl.h' is found, and to 'no' otherwise. AC_DEFUN([COVERED_HEADER_TCL], [AC_CACHE_CHECK([for tcl.h], [r_cv_header_tcl_h], [AC_EGREP_CPP([yes], [#include #if (TCL_MAJOR_VERSION >= 8) yes #endif ], [r_cv_header_tcl_h=yes], [r_cv_header_tcl_h=no])]) ])# COVERED_HEADER_TCL ## COVERED_HEADER_TK ## ------------- ## Set shell variable 'r_cv_header_tk_h' to 'yes' if a recent enough ## 'tk.h' is found, and to 'no' otherwise. AC_DEFUN([COVERED_HEADER_TK], [AC_CACHE_CHECK([for tk.h], [r_cv_header_tk_h], [AC_EGREP_CPP([yes], [#include #if (TK_MAJOR_VERSION >= 8) yes #endif ], [r_cv_header_tk_h=yes], [r_cv_header_tk_h=no])]) ])# COVERED_HEADER_TK ## COVERED_TCLTK_CPPFLAGS ## ----------------- ## Need to ensure that we can find the tcl.h and tk.h headers, which ## may be in non-standard and/or version-dependent directories, such as ## on FreeBSD systems. ## ## The logic is as follows. If TCLTK_CPPFLAGS was specified, then we ## do not investigate any further. Otherwise, if we still think we ## have Tcl/Tk, then first try via the corresponding *Config.sh file, ## or else try the obvious. AC_DEFUN([COVERED_TCLTK_CPPFLAGS], [AC_REQUIRE([COVERED_TCLTK_CONFIG]) if test -z "${TCLTK_CPPFLAGS}"; then ## We have to do the work. if test "${have_tcltk}" = yes; then ## Part 1. Check for tcl.h. found_tcl_h=no if test -n "${TCL_CONFIG}"; then . ${TCL_CONFIG} ## Look for tcl.h in ## ${TCL_PREFIX}/include/tcl${TCL_VERSION} ## ${TCL_PREFIX}/include ## Also look in ## ${TCL_PREFIX}/include/tcl${TCL_VERSION}/generic ## to deal with current FreeBSD layouts. These also link the real ## thing to the version subdir, but the link cannot be used as it ## fails to include 'tclDecls.h' which is not linked. Hence we ## must look for the real thing first. Argh ... for dir in \ ${TCL_PREFIX}/include/tcl${TCL_VERSION}/generic \ ${TCL_PREFIX}/include/tcl${TCL_VERSION} \ ${TCL_PREFIX}/include; do AC_CHECK_HEADER([${dir}/tcl.h], [TCLTK_CPPFLAGS="-I${dir}" found_tcl_h=yes break]) done fi if test "${found_tcl_h}" = no; then COVERED_HEADER_TCL if test "${r_cv_header_tcl_h}" = yes; then found_tcl_h=yes else have_tcltk=no fi fi fi if test "${have_tcltk}" = yes; then ## Part 2. Check for tk.h. found_tk_h=no if test -n "${TK_CONFIG}"; then . ${TK_CONFIG} ## Look for tk.h in ## ${TK_PREFIX}/include/tk${TK_VERSION} ## ${TK_PREFIX}/include ## Also look in ## ${TK_PREFIX}/include/tcl${TK_VERSION} ## to compensate for Debian madness ... ## Also look in ## ${TK_PREFIX}/include/tk${TK_VERSION}/generic ## to deal with current FreeBSD layouts. See above for details. ## ## As the AC_CHECK_HEADER test tries including the header file and ## tk.h includes tcl.h and X11/Xlib.h, we need to change CPPFLAGS ## for the check. r_save_CPPFLAGS="${CPPFLAGS}" CPPFLAGS="${CPPFLAGS} ${TK_XINCLUDES} ${TCLTK_CPPFLAGS}" for dir in \ ${TK_PREFIX}/include/tk${TK_VERSION}/generic \ ${TK_PREFIX}/include/tk${TK_VERSION} \ ${TK_PREFIX}/include/tcl${TK_VERSION} \ ${TK_PREFIX}/include; do AC_CHECK_HEADER([${dir}/tk.h], [TCLTK_CPPFLAGS="${TCLTK_CPPFLAGS} -I${dir}" found_tk_h=yes break]) done CPPFLAGS="${r_save_CPPFLAGS}" fi if test "${found_tk_h}" = no; then COVERED_HEADER_TK if test "{r_cv_header_tk_h}" = yes; then found_tk_h=yes else have_tcltk=no fi fi fi fi if test "${have_tcltk}" = yes; then if test -n "${TK_XINCLUDES}"; then TCLTK_CPPFLAGS="${TCLTK_CPPFLAGS} ${TK_XINCLUDES}" else TCLTK_CPPFLAGS="${TCLTK_CPPFLAGS} ${X_CFLAGS}" fi fi ])# COVERED_TCLTK_CPPFLAGS ## COVERED_TCLTK_LIBS ## ------------- ## Find the tcl and tk libraries. AC_DEFUN([COVERED_TCLTK_LIBS], [AC_REQUIRE([AC_PATH_XTRA]) AC_REQUIRE([COVERED_TCLTK_CONFIG]) if test -z "${TCLTK_LIBS}"; then ## We have to do the work. if test "${have_tcltk}" = yes; then ## Part 1. Try finding the tcl library. if test -n "${TCL_CONFIG}"; then . ${TCL_CONFIG} TCLTK_LIBS="${TCL_LIB_SPEC}" else AC_CHECK_LIB(tcl, Tcl_CreateInterp, [TCLTK_LIBS=-ltcl], [have_tcltk=no]) fi fi if test "${have_tcltk}" = yes; then ## Part 2. Try finding the tk library. if test -n "${TK_CONFIG}"; then . ${TK_CONFIG} TCLTK_LIBS="${TCLTK_LIBS} ${TK_LIB_SPEC} ${TK_LIBS}" else AC_CHECK_LIB(tk, Tk_Init, , , [${TCLTK_LIBS}]) if test "${ac_cv_lib_tk_Tk_Init}" = no; then ## Grr, simple -ltk does not work. ## But maybe we simply need to add X11 libs. ## Note that we cannot simply repeat the above test with extra ## libs, because AC_CHECK_LIB uses the corresponding cache var ## (ac_cv_lib_tk_Tk_Init in our case) if set. As using unset ## is not portable shell programming according to the Autoconf ## docs, we use Tk_SafeInit in the test with X11 libs added. AC_CHECK_LIB(tk, Tk_SafeInit, [TCLTK_LIBS="${TCLTK_LIBS} -ltk ${X_LIBS}"], [have_tcltk=no], [${TCLTK_LIBS} ${X_LIBS}]) fi fi fi ## Postprocessing for AIX. ## On AIX, the *_LIB_SPEC variables need to contain '-bI:' flags for ## the Tcl export file. These are really flags for ld rather than the ## C/C++ compilers, and hence may need protection via '-Wl,'. ## We have two ways of doing that: ## * Recording whether '-Wl,' is needed for the C or C++ compilers, ## and getting this info into the TCLTK_LIBS make variable ... mess! ## * Protecting all entries in TCLTK_LIBS that do not start with '-l' ## or '-L' with '-Wl,' (hoping that all compilers understand this). ## Easy, hence ... case "${host_os}" in aix*) orig_TCLTK_LIBS="${TCLTK_LIBS}" TCLTK_LIBS= for flag in ${orig_TCLTK_LIBS}; do case "${flag}" in -l*|-L*|-Wl,*) ;; *) flag="-Wl,${flag}" ;; esac TCLTK_LIBS="${TCLTK_LIBS} ${flag}" done ;; esac ## Force evaluation ('-ltcl8.3${TCL_DBGX}' and friends ...). eval "TCLTK_LIBS=\"${TCLTK_LIBS}\"" fi ])# COVERED_TCLTK_LIBS ## COVERED_TCLTK_WORKS ## -------------- ## Check whether compiling and linking code using Tcl/Tk works. ## Set shell variable r_cv_tcltk_works to 'yes' or 'no' accordingly. AC_DEFUN([COVERED_TCLTK_WORKS], [AC_CACHE_CHECK([whether compiling/linking Tcl/Tk code works], [r_cv_tcltk_works], [AC_LANG_PUSH(C) r_save_CPPFLAGS="${CPPFLAGS}" r_save_LIBS="${LIBS}" CPPFLAGS="${CPPFLAGS} ${TCLTK_CPPFLAGS}" LIBS="${LIBS} ${TCLTK_LIBS}" AC_LINK_IFELSE([AC_LANG_PROGRAM( [[#include #include ]], [[static char * p1 = (char *) Tcl_Init; static char * p2 = (char *) Tk_Init; ]])], r_cv_tcltk_works=yes, r_cv_tcltk_works=no) CPPFLAGS="${r_save_CPPFLAGS}" LIBS="${r_save_LIBS}" AC_LANG_POP(C)]) ])# COVERED_TCLTK_WORKS ## COVERED_TCLTK ## ------- AC_DEFUN([COVERED_TCLTK], [if test "${want_tcltk}" = yes; then have_tcltk=yes ## (Note that the subsequent 3 macros assume that have_tcltk has been ## set appropriately.) COVERED_TCLTK_CONFIG COVERED_TCLTK_CPPFLAGS COVERED_TCLTK_LIBS if test "${have_tcltk}" = yes; then COVERED_TCLTK_WORKS have_tcltk=${r_cv_tcltk_works} fi else have_tcltk=no ## Just making sure. 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They are # bogus both because they are the default anyway, and because # using them would break gcc on systems where it needs fixed includes. case $ac_im_incroot in /usr/include) ac_x_includes= ;; *) test -f "$ac_im_incroot/X11/Xos.h" && ac_x_includes=$ac_im_incroot;; esac case $ac_im_usrlibdir in /usr/lib | /usr/lib64 | /lib | /lib64) ;; *) test -d "$ac_im_usrlibdir" && ac_x_libraries=$ac_im_usrlibdir ;; esac fi cd .. rm -f -r conftest.dir fi # Standard set of common directories for X headers. # Check X11 before X11Rn because it is often a symlink to the current release. ac_x_header_dirs=' /usr/X11/include /usr/X11R7/include /usr/X11R6/include /usr/X11R5/include /usr/X11R4/include /usr/include/X11 /usr/include/X11R7 /usr/include/X11R6 /usr/include/X11R5 /usr/include/X11R4 /usr/local/X11/include /usr/local/X11R7/include /usr/local/X11R6/include /usr/local/X11R5/include /usr/local/X11R4/include /usr/local/include/X11 /usr/local/include/X11R7 /usr/local/include/X11R6 /usr/local/include/X11R5 /usr/local/include/X11R4 /usr/X386/include /usr/x386/include /usr/XFree86/include/X11 /usr/include /usr/local/include /usr/unsupported/include /usr/athena/include /usr/local/x11r5/include /usr/lpp/Xamples/include /usr/openwin/include /usr/openwin/share/include' if test "$ac_x_includes" = no; then # Guess where to find include files, by looking for Xlib.h. # First, try using that file with no special directory specified. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ @%:@include _ACEOF if ac_fn_c_try_cpp "$LINENO"; then : # We can compile using X headers with no special include directory. ac_x_includes= else for ac_dir in $ac_x_header_dirs; do if test -r "$ac_dir/X11/Xlib.h"; then ac_x_includes=$ac_dir break fi done fi rm -f conftest.err conftest.$ac_ext fi # $ac_x_includes = no if test "$ac_x_libraries" = no; then # Check for the libraries. # See if we find them without any special options. # Don't add to $LIBS permanently. ac_save_LIBS=$LIBS LIBS="-lX11 $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ @%:@include int main () { XrmInitialize () ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : LIBS=$ac_save_LIBS # We can link X programs with no special library path. ac_x_libraries= else LIBS=$ac_save_LIBS for ac_dir in `$as_echo "$ac_x_includes $ac_x_header_dirs" | sed s/include/lib/g` do # Don't even attempt the hair of trying to link an X program! for ac_extension in a so sl dylib la dll; do if test -r "$ac_dir/libX11.$ac_extension"; then ac_x_libraries=$ac_dir break 2 fi done done fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext fi # $ac_x_libraries = no case $ac_x_includes,$ac_x_libraries in #( no,* | *,no | *\'*) # Didn't find X, or a directory has "'" in its name. ac_cv_have_x="have_x=no";; #( *) # Record where we found X for the cache. ac_cv_have_x="have_x=yes\ ac_x_includes='$ac_x_includes'\ ac_x_libraries='$ac_x_libraries'" esac fi ;; #( *) have_x=yes;; esac eval "$ac_cv_have_x" fi # $with_x != no if test "$have_x" != yes; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $have_x" >&5 $as_echo "$have_x" >&6; } no_x=yes else # If each of the values was on the command line, it overrides each guess. test "x$x_includes" = xNONE && x_includes=$ac_x_includes test "x$x_libraries" = xNONE && x_libraries=$ac_x_libraries # Update the cache value to reflect the command line values. ac_cv_have_x="have_x=yes\ ac_x_includes='$x_includes'\ ac_x_libraries='$x_libraries'" { $as_echo "$as_me:${as_lineno-$LINENO}: result: libraries $x_libraries, headers $x_includes" >&5 $as_echo "libraries $x_libraries, headers $x_includes" >&6; } fi if test "$no_x" = yes; then # Not all programs may use this symbol, but it does not hurt to define it. $as_echo "@%:@define X_DISPLAY_MISSING 1" >>confdefs.h X_CFLAGS= X_PRE_LIBS= X_LIBS= X_EXTRA_LIBS= else if test -n "$x_includes"; then X_CFLAGS="$X_CFLAGS -I$x_includes" fi # It would also be nice to do this for all -L options, not just this one. if test -n "$x_libraries"; then X_LIBS="$X_LIBS -L$x_libraries" # For Solaris; some versions of Sun CC require a space after -R and # others require no space. Words are not sufficient . . . . { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether -R must be followed by a space" >&5 $as_echo_n "checking whether -R must be followed by a space... " >&6; } ac_xsave_LIBS=$LIBS; LIBS="$LIBS -R$x_libraries" ac_xsave_c_werror_flag=$ac_c_werror_flag ac_c_werror_flag=yes cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } X_LIBS="$X_LIBS -R$x_libraries" else LIBS="$ac_xsave_LIBS -R $x_libraries" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } X_LIBS="$X_LIBS -R $x_libraries" else { $as_echo "$as_me:${as_lineno-$LINENO}: result: neither works" >&5 $as_echo "neither works" >&6; } fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext ac_c_werror_flag=$ac_xsave_c_werror_flag LIBS=$ac_xsave_LIBS fi # Check for system-dependent libraries X programs must link with. # Do this before checking for the system-independent R6 libraries # (-lICE), since we may need -lsocket or whatever for X linking. if test "$ISC" = yes; then X_EXTRA_LIBS="$X_EXTRA_LIBS -lnsl_s -linet" else # Martyn Johnson says this is needed for Ultrix, if the X # libraries were built with DECnet support. And Karl Berry says # the Alpha needs dnet_stub (dnet does not exist). ac_xsave_LIBS="$LIBS"; LIBS="$LIBS $X_LIBS -lX11" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char XOpenDisplay (); int main () { return XOpenDisplay (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : else { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dnet_ntoa in -ldnet" >&5 $as_echo_n "checking for dnet_ntoa in -ldnet... " >&6; } if test "${ac_cv_lib_dnet_dnet_ntoa+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldnet $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dnet_ntoa (); int main () { return dnet_ntoa (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_dnet_dnet_ntoa=yes else ac_cv_lib_dnet_dnet_ntoa=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dnet_dnet_ntoa" >&5 $as_echo "$ac_cv_lib_dnet_dnet_ntoa" >&6; } if test "x$ac_cv_lib_dnet_dnet_ntoa" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -ldnet" fi if test $ac_cv_lib_dnet_dnet_ntoa = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dnet_ntoa in -ldnet_stub" >&5 $as_echo_n "checking for dnet_ntoa in -ldnet_stub... " >&6; } if test "${ac_cv_lib_dnet_stub_dnet_ntoa+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldnet_stub $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dnet_ntoa (); int main () { return dnet_ntoa (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_dnet_stub_dnet_ntoa=yes else ac_cv_lib_dnet_stub_dnet_ntoa=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dnet_stub_dnet_ntoa" >&5 $as_echo "$ac_cv_lib_dnet_stub_dnet_ntoa" >&6; } if test "x$ac_cv_lib_dnet_stub_dnet_ntoa" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -ldnet_stub" fi fi fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS="$ac_xsave_LIBS" # msh@cis.ufl.edu says -lnsl (and -lsocket) are needed for his 386/AT, # to get the SysV transport functions. # Chad R. Larson says the Pyramis MIS-ES running DC/OSx (SVR4) # needs -lnsl. # The nsl library prevents programs from opening the X display # on Irix 5.2, according to T.E. Dickey. # The functions gethostbyname, getservbyname, and inet_addr are # in -lbsd on LynxOS 3.0.1/i386, according to Lars Hecking. ac_fn_c_check_func "$LINENO" "gethostbyname" "ac_cv_func_gethostbyname" if test "x$ac_cv_func_gethostbyname" = x""yes; then : fi if test $ac_cv_func_gethostbyname = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for gethostbyname in -lnsl" >&5 $as_echo_n "checking for gethostbyname in -lnsl... " >&6; } if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lnsl $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char gethostbyname (); int main () { return gethostbyname (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_nsl_gethostbyname=yes else ac_cv_lib_nsl_gethostbyname=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_nsl_gethostbyname" >&5 $as_echo "$ac_cv_lib_nsl_gethostbyname" >&6; } if test "x$ac_cv_lib_nsl_gethostbyname" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -lnsl" fi if test $ac_cv_lib_nsl_gethostbyname = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for gethostbyname in -lbsd" >&5 $as_echo_n "checking for gethostbyname in -lbsd... " >&6; } if test "${ac_cv_lib_bsd_gethostbyname+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lbsd $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char gethostbyname (); int main () { return gethostbyname (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_bsd_gethostbyname=yes else ac_cv_lib_bsd_gethostbyname=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_bsd_gethostbyname" >&5 $as_echo "$ac_cv_lib_bsd_gethostbyname" >&6; } if test "x$ac_cv_lib_bsd_gethostbyname" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -lbsd" fi fi fi # lieder@skyler.mavd.honeywell.com says without -lsocket, # socket/setsockopt and other routines are undefined under SCO ODT # 2.0. But -lsocket is broken on IRIX 5.2 (and is not necessary # on later versions), says Simon Leinen: it contains gethostby* # variants that don't use the name server (or something). -lsocket # must be given before -lnsl if both are needed. We assume that # if connect needs -lnsl, so does gethostbyname. ac_fn_c_check_func "$LINENO" "connect" "ac_cv_func_connect" if test "x$ac_cv_func_connect" = x""yes; then : fi if test $ac_cv_func_connect = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for connect in -lsocket" >&5 $as_echo_n "checking for connect in -lsocket... " >&6; } if test "${ac_cv_lib_socket_connect+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lsocket $X_EXTRA_LIBS $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char connect (); int main () { return connect (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_socket_connect=yes else ac_cv_lib_socket_connect=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_socket_connect" >&5 $as_echo "$ac_cv_lib_socket_connect" >&6; } if test "x$ac_cv_lib_socket_connect" = x""yes; then : X_EXTRA_LIBS="-lsocket $X_EXTRA_LIBS" fi fi # Guillermo Gomez says -lposix is necessary on A/UX. ac_fn_c_check_func "$LINENO" "remove" "ac_cv_func_remove" if test "x$ac_cv_func_remove" = x""yes; then : fi if test $ac_cv_func_remove = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for remove in -lposix" >&5 $as_echo_n "checking for remove in -lposix... " >&6; } if test "${ac_cv_lib_posix_remove+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lposix $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char remove (); int main () { return remove (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_posix_remove=yes else ac_cv_lib_posix_remove=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_posix_remove" >&5 $as_echo "$ac_cv_lib_posix_remove" >&6; } if test "x$ac_cv_lib_posix_remove" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -lposix" fi fi # BSDI BSD/OS 2.1 needs -lipc for XOpenDisplay. ac_fn_c_check_func "$LINENO" "shmat" "ac_cv_func_shmat" if test "x$ac_cv_func_shmat" = x""yes; then : fi if test $ac_cv_func_shmat = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for shmat in -lipc" >&5 $as_echo_n "checking for shmat in -lipc... " >&6; } if test "${ac_cv_lib_ipc_shmat+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lipc $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char shmat (); int main () { return shmat (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_ipc_shmat=yes else ac_cv_lib_ipc_shmat=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_ipc_shmat" >&5 $as_echo "$ac_cv_lib_ipc_shmat" >&6; } if test "x$ac_cv_lib_ipc_shmat" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -lipc" fi fi fi # Check for libraries that X11R6 Xt/Xaw programs need. ac_save_LDFLAGS=$LDFLAGS test -n "$x_libraries" && LDFLAGS="$LDFLAGS -L$x_libraries" # SM needs ICE to (dynamically) link under SunOS 4.x (so we have to # check for ICE first), but we must link in the order -lSM -lICE or # we get undefined symbols. So assume we have SM if we have ICE. # These have to be linked with before -lX11, unlike the other # libraries we check for below, so use a different variable. # John Interrante, Karl Berry { $as_echo "$as_me:${as_lineno-$LINENO}: checking for IceConnectionNumber in -lICE" >&5 $as_echo_n "checking for IceConnectionNumber in -lICE... " >&6; } if test "${ac_cv_lib_ICE_IceConnectionNumber+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lICE $X_EXTRA_LIBS $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char IceConnectionNumber (); int main () { return IceConnectionNumber (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_ICE_IceConnectionNumber=yes else ac_cv_lib_ICE_IceConnectionNumber=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_ICE_IceConnectionNumber" >&5 $as_echo "$ac_cv_lib_ICE_IceConnectionNumber" >&6; } if test "x$ac_cv_lib_ICE_IceConnectionNumber" = x""yes; then : X_PRE_LIBS="$X_PRE_LIBS -lSM -lICE" fi LDFLAGS=$ac_save_LDFLAGS fi if test "${want_tcltk}" = yes; then have_tcltk=yes ## (Note that the subsequent 3 macros assume that have_tcltk has been ## set appropriately.) for ac_prog in ${TCL_CONFIG} tclConfig.sh do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if test "${ac_cv_path_TCL_CONFIG+set}" = set; then : $as_echo_n "(cached) " >&6 else case $TCL_CONFIG in [\\/]* | ?:[\\/]*) ac_cv_path_TCL_CONFIG="$TCL_CONFIG" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_path_TCL_CONFIG="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi TCL_CONFIG=$ac_cv_path_TCL_CONFIG if test -n "$TCL_CONFIG"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $TCL_CONFIG" >&5 $as_echo "$TCL_CONFIG" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi test -n "$TCL_CONFIG" && break done if test -z "${TCL_CONFIG}"; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tclConfig.sh in library (sub)directories" >&5 $as_echo_n "checking for tclConfig.sh in library (sub)directories... " >&6; } if test "${r_cv_path_TCL_CONFIG+set}" = set; then : $as_echo_n "(cached) " >&6 else for ldir in /opt/lib /sw/lib /usr/local/lib /usr/lib /lib /usr/lib64 ; do for dir in \ ${ldir} \ `ls -d ${ldir}/tcl[8-9].[0-9]* 2>/dev/null | sort -r`; do if test -f ${dir}/tclConfig.sh; then r_cv_path_TCL_CONFIG="${dir}/tclConfig.sh" break 2 fi done done fi if test -n "${r_cv_path_TCL_CONFIG}"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: ${r_cv_path_TCL_CONFIG}" >&5 $as_echo "${r_cv_path_TCL_CONFIG}" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test -n "${r_cv_path_TCL_CONFIG}"; then TCL_CONFIG="${r_cv_path_TCL_CONFIG}" fi fi for ac_prog in ${TK_CONFIG} tkConfig.sh do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if test "${ac_cv_path_TK_CONFIG+set}" = set; then : $as_echo_n "(cached) " >&6 else case $TK_CONFIG in [\\/]* | ?:[\\/]*) ac_cv_path_TK_CONFIG="$TK_CONFIG" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_path_TK_CONFIG="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi TK_CONFIG=$ac_cv_path_TK_CONFIG if test -n "$TK_CONFIG"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $TK_CONFIG" >&5 $as_echo "$TK_CONFIG" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi test -n "$TK_CONFIG" && break done if test -z "${TK_CONFIG}"; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tkConfig.sh in library (sub)directories" >&5 $as_echo_n "checking for tkConfig.sh in library (sub)directories... " >&6; } if test "${r_cv_path_TK_CONFIG+set}" = set; then : $as_echo_n "(cached) " >&6 else for ldir in /opt/lib /sw/lib /usr/local/lib /usr/lib /lib /usr/lib64 ; do for dir in \ ${ldir} \ `ls -d ${ldir}/tk[8-9].[0-9]* 2>/dev/null | sort -r`; do if test -f ${dir}/tkConfig.sh; then r_cv_path_TK_CONFIG="${dir}/tkConfig.sh" break 2 fi done done fi if test -n "${r_cv_path_TK_CONFIG}"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: ${r_cv_path_TK_CONFIG}" >&5 $as_echo "${r_cv_path_TK_CONFIG}" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test -n "${r_cv_path_TK_CONFIG}"; then TK_CONFIG="${r_cv_path_TK_CONFIG}" fi fi if test -z "${TCLTK_CPPFLAGS}" \ || test -z "${TCLTK_LIBS}"; then ## Check whether the versions found via the *Config.sh files are at ## least 8; otherwise, issue a warning and turn off Tcl/Tk support. ## Note that in theory a system could have outdated versions of the ## *Config.sh scripts and yet up-to-date installations of Tcl/Tk in ## standard places ... if test -n "${TCL_CONFIG}"; then . ${TCL_CONFIG} if test ${TCL_MAJOR_VERSION} -lt 8; then warn_tcltk_version="Tcl/Tk support requires Tcl version >= 8" { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: ${warn_tcltk_version}" >&5 $as_echo "$as_me: WARNING: ${warn_tcltk_version}" >&2;} have_tcltk=no fi fi if test -n "${TK_CONFIG}" \ && test -z "${warn_tcltk_version}"; then . ${TK_CONFIG} if test ${TK_MAJOR_VERSION} -lt 8; then warn_tcltk_version="Tcl/Tk support requires Tk version >= 8" { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: ${warn_tcltk_version}" >&5 $as_echo "$as_me: WARNING: ${warn_tcltk_version}" >&2;} have_tcltk=no fi fi if test -n "${TCL_CONFIG}" \ && test -n "${TK_CONFIG}" \ && test -z "${warn_tcltk_version}"; then if test ${TCL_MAJOR_VERSION} -ne ${TK_MAJOR_VERSION} \ || test ${TCL_MINOR_VERSION} -ne ${TK_MINOR_VERSION}; then warn_tcltk_version="Tcl and Tk major or minor versions disagree" { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: ${warn_tcltk_version}" >&5 $as_echo "$as_me: WARNING: ${warn_tcltk_version}" >&2;} have_tcltk=no fi fi fi if test -z "${TCLTK_CPPFLAGS}"; then ## We have to do the work. if test "${have_tcltk}" = yes; then ## Part 1. Check for tcl.h. found_tcl_h=no if test -n "${TCL_CONFIG}"; then . ${TCL_CONFIG} ## Look for tcl.h in ## ${TCL_PREFIX}/include/tcl${TCL_VERSION} ## ${TCL_PREFIX}/include ## Also look in ## ${TCL_PREFIX}/include/tcl${TCL_VERSION}/generic ## to deal with current FreeBSD layouts. These also link the real ## thing to the version subdir, but the link cannot be used as it ## fails to include 'tclDecls.h' which is not linked. Hence we ## must look for the real thing first. Argh ... for dir in \ ${TCL_PREFIX}/include/tcl${TCL_VERSION}/generic \ ${TCL_PREFIX}/include/tcl${TCL_VERSION} \ ${TCL_PREFIX}/include; do as_ac_Header=`$as_echo "ac_cv_header_${dir}/tcl.h" | $as_tr_sh` ac_fn_c_check_header_mongrel "$LINENO" "${dir}/tcl.h" "$as_ac_Header" "$ac_includes_default" eval as_val=\$$as_ac_Header if test "x$as_val" = x""yes; then : TCLTK_CPPFLAGS="-I${dir}" found_tcl_h=yes break fi done fi if test "${found_tcl_h}" = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tcl.h" >&5 $as_echo_n "checking for tcl.h... " >&6; } if test "${r_cv_header_tcl_h+set}" = set; then : $as_echo_n "(cached) " >&6 else cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include #if (TCL_MAJOR_VERSION >= 8) yes #endif _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "yes" >/dev/null 2>&1; then : r_cv_header_tcl_h=yes else r_cv_header_tcl_h=no fi rm -f conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $r_cv_header_tcl_h" >&5 $as_echo "$r_cv_header_tcl_h" >&6; } if test "${r_cv_header_tcl_h}" = yes; then found_tcl_h=yes else have_tcltk=no fi fi fi if test "${have_tcltk}" = yes; then ## Part 2. Check for tk.h. found_tk_h=no if test -n "${TK_CONFIG}"; then . ${TK_CONFIG} ## Look for tk.h in ## ${TK_PREFIX}/include/tk${TK_VERSION} ## ${TK_PREFIX}/include ## Also look in ## ${TK_PREFIX}/include/tcl${TK_VERSION} ## to compensate for Debian madness ... ## Also look in ## ${TK_PREFIX}/include/tk${TK_VERSION}/generic ## to deal with current FreeBSD layouts. See above for details. ## ## As the AC_CHECK_HEADER test tries including the header file and ## tk.h includes tcl.h and X11/Xlib.h, we need to change CPPFLAGS ## for the check. r_save_CPPFLAGS="${CPPFLAGS}" CPPFLAGS="${CPPFLAGS} ${TK_XINCLUDES} ${TCLTK_CPPFLAGS}" for dir in \ ${TK_PREFIX}/include/tk${TK_VERSION}/generic \ ${TK_PREFIX}/include/tk${TK_VERSION} \ ${TK_PREFIX}/include/tcl${TK_VERSION} \ ${TK_PREFIX}/include; do as_ac_Header=`$as_echo "ac_cv_header_${dir}/tk.h" | $as_tr_sh` ac_fn_c_check_header_mongrel "$LINENO" "${dir}/tk.h" "$as_ac_Header" "$ac_includes_default" eval as_val=\$$as_ac_Header if test "x$as_val" = x""yes; then : TCLTK_CPPFLAGS="${TCLTK_CPPFLAGS} -I${dir}" found_tk_h=yes break fi done CPPFLAGS="${r_save_CPPFLAGS}" fi if test "${found_tk_h}" = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tk.h" >&5 $as_echo_n "checking for tk.h... " >&6; } if test "${r_cv_header_tk_h+set}" = set; then : $as_echo_n "(cached) " >&6 else cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include #if (TK_MAJOR_VERSION >= 8) yes #endif _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "yes" >/dev/null 2>&1; then : r_cv_header_tk_h=yes else r_cv_header_tk_h=no fi rm -f conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $r_cv_header_tk_h" >&5 $as_echo "$r_cv_header_tk_h" >&6; } if test "{r_cv_header_tk_h}" = yes; then found_tk_h=yes else have_tcltk=no fi fi fi fi if test "${have_tcltk}" = yes; then if test -n "${TK_XINCLUDES}"; then TCLTK_CPPFLAGS="${TCLTK_CPPFLAGS} ${TK_XINCLUDES}" else TCLTK_CPPFLAGS="${TCLTK_CPPFLAGS} ${X_CFLAGS}" fi fi if test -z "${TCLTK_LIBS}"; then ## We have to do the work. if test "${have_tcltk}" = yes; then ## Part 1. Try finding the tcl library. if test -n "${TCL_CONFIG}"; then . ${TCL_CONFIG} TCLTK_LIBS="${TCL_LIB_SPEC}" else { $as_echo "$as_me:${as_lineno-$LINENO}: checking for Tcl_CreateInterp in -ltcl" >&5 $as_echo_n "checking for Tcl_CreateInterp in -ltcl... " >&6; } if test "${ac_cv_lib_tcl_Tcl_CreateInterp+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ltcl $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char Tcl_CreateInterp (); int main () { return Tcl_CreateInterp (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_tcl_Tcl_CreateInterp=yes else ac_cv_lib_tcl_Tcl_CreateInterp=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_tcl_Tcl_CreateInterp" >&5 $as_echo "$ac_cv_lib_tcl_Tcl_CreateInterp" >&6; } if test "x$ac_cv_lib_tcl_Tcl_CreateInterp" = x""yes; then : TCLTK_LIBS=-ltcl else have_tcltk=no fi fi fi if test "${have_tcltk}" = yes; then ## Part 2. Try finding the tk library. if test -n "${TK_CONFIG}"; then . ${TK_CONFIG} TCLTK_LIBS="${TCLTK_LIBS} ${TK_LIB_SPEC} ${TK_LIBS}" else { $as_echo "$as_me:${as_lineno-$LINENO}: checking for Tk_Init in -ltk" >&5 $as_echo_n "checking for Tk_Init in -ltk... " >&6; } if test "${ac_cv_lib_tk_Tk_Init+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ltk ${TCLTK_LIBS} $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char Tk_Init (); int main () { return Tk_Init (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_tk_Tk_Init=yes else ac_cv_lib_tk_Tk_Init=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_tk_Tk_Init" >&5 $as_echo "$ac_cv_lib_tk_Tk_Init" >&6; } if test "x$ac_cv_lib_tk_Tk_Init" = x""yes; then : cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBTK 1 _ACEOF LIBS="-ltk $LIBS" fi if test "${ac_cv_lib_tk_Tk_Init}" = no; then ## Grr, simple -ltk does not work. ## But maybe we simply need to add X11 libs. ## Note that we cannot simply repeat the above test with extra ## libs, because AC_CHECK_LIB uses the corresponding cache var ## (ac_cv_lib_tk_Tk_Init in our case) if set. As using unset ## is not portable shell programming according to the Autoconf ## docs, we use Tk_SafeInit in the test with X11 libs added. { $as_echo "$as_me:${as_lineno-$LINENO}: checking for Tk_SafeInit in -ltk" >&5 $as_echo_n "checking for Tk_SafeInit in -ltk... " >&6; } if test "${ac_cv_lib_tk_Tk_SafeInit+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ltk ${TCLTK_LIBS} ${X_LIBS} $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char Tk_SafeInit (); int main () { return Tk_SafeInit (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_tk_Tk_SafeInit=yes else ac_cv_lib_tk_Tk_SafeInit=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_tk_Tk_SafeInit" >&5 $as_echo "$ac_cv_lib_tk_Tk_SafeInit" >&6; } if test "x$ac_cv_lib_tk_Tk_SafeInit" = x""yes; then : TCLTK_LIBS="${TCLTK_LIBS} -ltk ${X_LIBS}" else have_tcltk=no fi fi fi fi ## Postprocessing for AIX. ## On AIX, the *_LIB_SPEC variables need to contain '-bI:' flags for ## the Tcl export file. These are really flags for ld rather than the ## C/C++ compilers, and hence may need protection via '-Wl,'. ## We have two ways of doing that: ## * Recording whether '-Wl,' is needed for the C or C++ compilers, ## and getting this info into the TCLTK_LIBS make variable ... mess! ## * Protecting all entries in TCLTK_LIBS that do not start with '-l' ## or '-L' with '-Wl,' (hoping that all compilers understand this). ## Easy, hence ... case "${host_os}" in aix*) orig_TCLTK_LIBS="${TCLTK_LIBS}" TCLTK_LIBS= for flag in ${orig_TCLTK_LIBS}; do case "${flag}" in -l*|-L*|-Wl,*) ;; *) flag="-Wl,${flag}" ;; esac TCLTK_LIBS="${TCLTK_LIBS} ${flag}" done ;; esac ## Force evaluation ('-ltcl8.3${TCL_DBGX}' and friends ...). eval "TCLTK_LIBS=\"${TCLTK_LIBS}\"" fi if test "${have_tcltk}" = yes; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether compiling/linking Tcl/Tk code works" >&5 $as_echo_n "checking whether compiling/linking Tcl/Tk code works... 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TCLTK_CPPFLAGS= TCLTK_LIBS= fi if test "${have_tcltk}" = yes; then $as_echo "@%:@define HAVE_TCLTK 1" >>confdefs.h use_tcltk=yes else use_tcltk=no fi ## Check for browser for help pages if test -z "${COVERED_BROWSER}"; then for ac_prog in firefox safari netscape mozilla galeon kfmclient opera gnome-moz-remote open do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... 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then warn_browser="I could not determine a browser" { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: ${warn_browser}" >&5 $as_echo "$as_me: WARNING: ${warn_browser}" >&2;} else { $as_echo "$as_me:${as_lineno-$LINENO}: result: using default browser ... ${COVERED_BROWSER}" >&5 $as_echo "using default browser ... ${COVERED_BROWSER}" >&6; } fi cat >>confdefs.h <<_ACEOF @%:@define COVERED_BROWSER "$COVERED_BROWSER" _ACEOF @%:@ Check whether --enable-debug was given. if test "${enable_debug+set}" = set; then : enableval=$enable_debug; DEBUGDEF="-DDEBUG_MODE" fi @%:@ Check whether --enable-profiling was given. if test "${enable_profiling+set}" = set; then : enableval=$enable_profiling; PROFILEDEF="-DPROFILER" fi @%:@ Check whether --enable-test was given. if test "${enable_test+set}" = set; then : enableval=$enable_test; TESTMODEDEF="-DTESTMODE" fi ## Simulators supported @%:@ Check whether --with-iv was given. if test "${with_iv+set}" = set; then : withval=$with_iv; if test "${withval}" = no; then want_iv=no elif test "${withval}" = yes; then want_iv=yes else as_ac_Header=`$as_echo "ac_cv_header_$withval/include/iverilog/vpi_user.h" | $as_tr_sh` ac_fn_c_check_header_mongrel "$LINENO" "$withval/include/iverilog/vpi_user.h" "$as_ac_Header" "$ac_includes_default" eval as_val=\$$as_ac_Header if test "x$as_val" = x""yes; then : want_iv=yes iv_prefix="${withval}" iv_inc_prefix="${withval}/include/iverilog" else as_ac_Header=`$as_echo "ac_cv_header_$withval/include/vpi_user.h" | $as_tr_sh` ac_fn_c_check_header_mongrel "$LINENO" "$withval/include/vpi_user.h" "$as_ac_Header" "$ac_includes_default" eval as_val=\$$as_ac_Header if test "x$as_val" = x""yes; then : want_iv=yes iv_prefix="${withval}" iv_inc_prefix="${withval}/include" else as_ac_Header=`$as_echo "ac_cv_header_$withval/include/verilog/vpi_user.h" | $as_tr_sh` ac_fn_c_check_header_mongrel "$LINENO" "$withval/include/verilog/vpi_user.h" "$as_ac_Header" "$ac_includes_default" eval as_val=\$$as_ac_Header if test "x$as_val" = x""yes; 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They are # bogus both because they are the default anyway, and because # using them would break gcc on systems where it needs fixed includes. case $ac_im_incroot in /usr/include) ac_x_includes= ;; *) test -f "$ac_im_incroot/X11/Xos.h" && ac_x_includes=$ac_im_incroot;; esac case $ac_im_usrlibdir in /usr/lib | /usr/lib64 | /lib | /lib64) ;; *) test -d "$ac_im_usrlibdir" && ac_x_libraries=$ac_im_usrlibdir ;; esac fi cd .. rm -f -r conftest.dir fi # Standard set of common directories for X headers. # Check X11 before X11Rn because it is often a symlink to the current release. ac_x_header_dirs=' /usr/X11/include /usr/X11R7/include /usr/X11R6/include /usr/X11R5/include /usr/X11R4/include /usr/include/X11 /usr/include/X11R7 /usr/include/X11R6 /usr/include/X11R5 /usr/include/X11R4 /usr/local/X11/include /usr/local/X11R7/include /usr/local/X11R6/include /usr/local/X11R5/include /usr/local/X11R4/include /usr/local/include/X11 /usr/local/include/X11R7 /usr/local/include/X11R6 /usr/local/include/X11R5 /usr/local/include/X11R4 /usr/X386/include /usr/x386/include /usr/XFree86/include/X11 /usr/include /usr/local/include /usr/unsupported/include /usr/athena/include /usr/local/x11r5/include /usr/lpp/Xamples/include /usr/openwin/include /usr/openwin/share/include' if test "$ac_x_includes" = no; then # Guess where to find include files, by looking for Xlib.h. # First, try using that file with no special directory specified. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ @%:@include _ACEOF if ac_fn_c_try_cpp "$LINENO"; then : # We can compile using X headers with no special include directory. ac_x_includes= else for ac_dir in $ac_x_header_dirs; do if test -r "$ac_dir/X11/Xlib.h"; then ac_x_includes=$ac_dir break fi done fi rm -f conftest.err conftest.$ac_ext fi # $ac_x_includes = no if test "$ac_x_libraries" = no; then # Check for the libraries. # See if we find them without any special options. # Don't add to $LIBS permanently. ac_save_LIBS=$LIBS LIBS="-lX11 $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ @%:@include int main () { XrmInitialize () ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : LIBS=$ac_save_LIBS # We can link X programs with no special library path. ac_x_libraries= else LIBS=$ac_save_LIBS for ac_dir in `$as_echo "$ac_x_includes $ac_x_header_dirs" | sed s/include/lib/g` do # Don't even attempt the hair of trying to link an X program! for ac_extension in a so sl dylib la dll; do if test -r "$ac_dir/libX11.$ac_extension"; then ac_x_libraries=$ac_dir break 2 fi done done fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext fi # $ac_x_libraries = no case $ac_x_includes,$ac_x_libraries in #( no,* | *,no | *\'*) # Didn't find X, or a directory has "'" in its name. ac_cv_have_x="have_x=no";; #( *) # Record where we found X for the cache. ac_cv_have_x="have_x=yes\ ac_x_includes='$ac_x_includes'\ ac_x_libraries='$ac_x_libraries'" esac fi ;; #( *) have_x=yes;; esac eval "$ac_cv_have_x" fi # $with_x != no if test "$have_x" != yes; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $have_x" >&5 $as_echo "$have_x" >&6; } no_x=yes else # If each of the values was on the command line, it overrides each guess. test "x$x_includes" = xNONE && x_includes=$ac_x_includes test "x$x_libraries" = xNONE && x_libraries=$ac_x_libraries # Update the cache value to reflect the command line values. ac_cv_have_x="have_x=yes\ ac_x_includes='$x_includes'\ ac_x_libraries='$x_libraries'" { $as_echo "$as_me:${as_lineno-$LINENO}: result: libraries $x_libraries, headers $x_includes" >&5 $as_echo "libraries $x_libraries, headers $x_includes" >&6; } fi if test "$no_x" = yes; then # Not all programs may use this symbol, but it does not hurt to define it. $as_echo "@%:@define X_DISPLAY_MISSING 1" >>confdefs.h X_CFLAGS= X_PRE_LIBS= X_LIBS= X_EXTRA_LIBS= else if test -n "$x_includes"; then X_CFLAGS="$X_CFLAGS -I$x_includes" fi # It would also be nice to do this for all -L options, not just this one. if test -n "$x_libraries"; then X_LIBS="$X_LIBS -L$x_libraries" # For Solaris; some versions of Sun CC require a space after -R and # others require no space. Words are not sufficient . . . . { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether -R must be followed by a space" >&5 $as_echo_n "checking whether -R must be followed by a space... " >&6; } ac_xsave_LIBS=$LIBS; LIBS="$LIBS -R$x_libraries" ac_xsave_c_werror_flag=$ac_c_werror_flag ac_c_werror_flag=yes cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } X_LIBS="$X_LIBS -R$x_libraries" else LIBS="$ac_xsave_LIBS -R $x_libraries" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } X_LIBS="$X_LIBS -R $x_libraries" else { $as_echo "$as_me:${as_lineno-$LINENO}: result: neither works" >&5 $as_echo "neither works" >&6; } fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext ac_c_werror_flag=$ac_xsave_c_werror_flag LIBS=$ac_xsave_LIBS fi # Check for system-dependent libraries X programs must link with. # Do this before checking for the system-independent R6 libraries # (-lICE), since we may need -lsocket or whatever for X linking. if test "$ISC" = yes; then X_EXTRA_LIBS="$X_EXTRA_LIBS -lnsl_s -linet" else # Martyn Johnson says this is needed for Ultrix, if the X # libraries were built with DECnet support. And Karl Berry says # the Alpha needs dnet_stub (dnet does not exist). ac_xsave_LIBS="$LIBS"; LIBS="$LIBS $X_LIBS -lX11" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char XOpenDisplay (); int main () { return XOpenDisplay (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : else { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dnet_ntoa in -ldnet" >&5 $as_echo_n "checking for dnet_ntoa in -ldnet... " >&6; } if test "${ac_cv_lib_dnet_dnet_ntoa+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldnet $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dnet_ntoa (); int main () { return dnet_ntoa (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_dnet_dnet_ntoa=yes else ac_cv_lib_dnet_dnet_ntoa=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dnet_dnet_ntoa" >&5 $as_echo "$ac_cv_lib_dnet_dnet_ntoa" >&6; } if test "x$ac_cv_lib_dnet_dnet_ntoa" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -ldnet" fi if test $ac_cv_lib_dnet_dnet_ntoa = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dnet_ntoa in -ldnet_stub" >&5 $as_echo_n "checking for dnet_ntoa in -ldnet_stub... " >&6; } if test "${ac_cv_lib_dnet_stub_dnet_ntoa+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldnet_stub $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dnet_ntoa (); int main () { return dnet_ntoa (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_dnet_stub_dnet_ntoa=yes else ac_cv_lib_dnet_stub_dnet_ntoa=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dnet_stub_dnet_ntoa" >&5 $as_echo "$ac_cv_lib_dnet_stub_dnet_ntoa" >&6; } if test "x$ac_cv_lib_dnet_stub_dnet_ntoa" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -ldnet_stub" fi fi fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS="$ac_xsave_LIBS" # msh@cis.ufl.edu says -lnsl (and -lsocket) are needed for his 386/AT, # to get the SysV transport functions. # Chad R. Larson says the Pyramis MIS-ES running DC/OSx (SVR4) # needs -lnsl. # The nsl library prevents programs from opening the X display # on Irix 5.2, according to T.E. Dickey. # The functions gethostbyname, getservbyname, and inet_addr are # in -lbsd on LynxOS 3.0.1/i386, according to Lars Hecking. ac_fn_c_check_func "$LINENO" "gethostbyname" "ac_cv_func_gethostbyname" if test "x$ac_cv_func_gethostbyname" = x""yes; then : fi if test $ac_cv_func_gethostbyname = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for gethostbyname in -lnsl" >&5 $as_echo_n "checking for gethostbyname in -lnsl... " >&6; } if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lnsl $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char gethostbyname (); int main () { return gethostbyname (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_nsl_gethostbyname=yes else ac_cv_lib_nsl_gethostbyname=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_nsl_gethostbyname" >&5 $as_echo "$ac_cv_lib_nsl_gethostbyname" >&6; } if test "x$ac_cv_lib_nsl_gethostbyname" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -lnsl" fi if test $ac_cv_lib_nsl_gethostbyname = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for gethostbyname in -lbsd" >&5 $as_echo_n "checking for gethostbyname in -lbsd... " >&6; } if test "${ac_cv_lib_bsd_gethostbyname+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lbsd $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char gethostbyname (); int main () { return gethostbyname (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_bsd_gethostbyname=yes else ac_cv_lib_bsd_gethostbyname=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_bsd_gethostbyname" >&5 $as_echo "$ac_cv_lib_bsd_gethostbyname" >&6; } if test "x$ac_cv_lib_bsd_gethostbyname" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -lbsd" fi fi fi # lieder@skyler.mavd.honeywell.com says without -lsocket, # socket/setsockopt and other routines are undefined under SCO ODT # 2.0. But -lsocket is broken on IRIX 5.2 (and is not necessary # on later versions), says Simon Leinen: it contains gethostby* # variants that don't use the name server (or something). -lsocket # must be given before -lnsl if both are needed. We assume that # if connect needs -lnsl, so does gethostbyname. ac_fn_c_check_func "$LINENO" "connect" "ac_cv_func_connect" if test "x$ac_cv_func_connect" = x""yes; then : fi if test $ac_cv_func_connect = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for connect in -lsocket" >&5 $as_echo_n "checking for connect in -lsocket... " >&6; } if test "${ac_cv_lib_socket_connect+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lsocket $X_EXTRA_LIBS $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char connect (); int main () { return connect (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_socket_connect=yes else ac_cv_lib_socket_connect=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_socket_connect" >&5 $as_echo "$ac_cv_lib_socket_connect" >&6; } if test "x$ac_cv_lib_socket_connect" = x""yes; then : X_EXTRA_LIBS="-lsocket $X_EXTRA_LIBS" fi fi # Guillermo Gomez says -lposix is necessary on A/UX. ac_fn_c_check_func "$LINENO" "remove" "ac_cv_func_remove" if test "x$ac_cv_func_remove" = x""yes; then : fi if test $ac_cv_func_remove = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for remove in -lposix" >&5 $as_echo_n "checking for remove in -lposix... " >&6; } if test "${ac_cv_lib_posix_remove+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lposix $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char remove (); int main () { return remove (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_posix_remove=yes else ac_cv_lib_posix_remove=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_posix_remove" >&5 $as_echo "$ac_cv_lib_posix_remove" >&6; } if test "x$ac_cv_lib_posix_remove" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -lposix" fi fi # BSDI BSD/OS 2.1 needs -lipc for XOpenDisplay. ac_fn_c_check_func "$LINENO" "shmat" "ac_cv_func_shmat" if test "x$ac_cv_func_shmat" = x""yes; then : fi if test $ac_cv_func_shmat = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for shmat in -lipc" >&5 $as_echo_n "checking for shmat in -lipc... " >&6; } if test "${ac_cv_lib_ipc_shmat+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lipc $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char shmat (); int main () { return shmat (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_ipc_shmat=yes else ac_cv_lib_ipc_shmat=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_ipc_shmat" >&5 $as_echo "$ac_cv_lib_ipc_shmat" >&6; } if test "x$ac_cv_lib_ipc_shmat" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -lipc" fi fi fi # Check for libraries that X11R6 Xt/Xaw programs need. ac_save_LDFLAGS=$LDFLAGS test -n "$x_libraries" && LDFLAGS="$LDFLAGS -L$x_libraries" # SM needs ICE to (dynamically) link under SunOS 4.x (so we have to # check for ICE first), but we must link in the order -lSM -lICE or # we get undefined symbols. So assume we have SM if we have ICE. # These have to be linked with before -lX11, unlike the other # libraries we check for below, so use a different variable. # John Interrante, Karl Berry { $as_echo "$as_me:${as_lineno-$LINENO}: checking for IceConnectionNumber in -lICE" >&5 $as_echo_n "checking for IceConnectionNumber in -lICE... " >&6; } if test "${ac_cv_lib_ICE_IceConnectionNumber+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lICE $X_EXTRA_LIBS $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char IceConnectionNumber (); int main () { return IceConnectionNumber (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_ICE_IceConnectionNumber=yes else ac_cv_lib_ICE_IceConnectionNumber=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_ICE_IceConnectionNumber" >&5 $as_echo "$ac_cv_lib_ICE_IceConnectionNumber" >&6; } if test "x$ac_cv_lib_ICE_IceConnectionNumber" = x""yes; then : X_PRE_LIBS="$X_PRE_LIBS -lSM -lICE" fi LDFLAGS=$ac_save_LDFLAGS fi if test "${want_tcltk}" = yes; then have_tcltk=yes ## (Note that the subsequent 3 macros assume that have_tcltk has been ## set appropriately.) for ac_prog in ${TCL_CONFIG} tclConfig.sh do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if test "${ac_cv_path_TCL_CONFIG+set}" = set; then : $as_echo_n "(cached) " >&6 else case $TCL_CONFIG in [\\/]* | ?:[\\/]*) ac_cv_path_TCL_CONFIG="$TCL_CONFIG" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_path_TCL_CONFIG="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi TCL_CONFIG=$ac_cv_path_TCL_CONFIG if test -n "$TCL_CONFIG"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $TCL_CONFIG" >&5 $as_echo "$TCL_CONFIG" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi test -n "$TCL_CONFIG" && break done if test -z "${TCL_CONFIG}"; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tclConfig.sh in library (sub)directories" >&5 $as_echo_n "checking for tclConfig.sh in library (sub)directories... " >&6; } if test "${r_cv_path_TCL_CONFIG+set}" = set; then : $as_echo_n "(cached) " >&6 else for ldir in /opt/lib /sw/lib /usr/local/lib /usr/lib /lib /usr/lib64 ; do for dir in \ ${ldir} \ `ls -d ${ldir}/tcl[8-9].[0-9]* 2>/dev/null | sort -r`; do if test -f ${dir}/tclConfig.sh; then r_cv_path_TCL_CONFIG="${dir}/tclConfig.sh" break 2 fi done done fi if test -n "${r_cv_path_TCL_CONFIG}"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: ${r_cv_path_TCL_CONFIG}" >&5 $as_echo "${r_cv_path_TCL_CONFIG}" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test -n "${r_cv_path_TCL_CONFIG}"; then TCL_CONFIG="${r_cv_path_TCL_CONFIG}" fi fi for ac_prog in ${TK_CONFIG} tkConfig.sh do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if test "${ac_cv_path_TK_CONFIG+set}" = set; then : $as_echo_n "(cached) " >&6 else case $TK_CONFIG in [\\/]* | ?:[\\/]*) ac_cv_path_TK_CONFIG="$TK_CONFIG" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_path_TK_CONFIG="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi TK_CONFIG=$ac_cv_path_TK_CONFIG if test -n "$TK_CONFIG"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $TK_CONFIG" >&5 $as_echo "$TK_CONFIG" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi test -n "$TK_CONFIG" && break done if test -z "${TK_CONFIG}"; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tkConfig.sh in library (sub)directories" >&5 $as_echo_n "checking for tkConfig.sh in library (sub)directories... " >&6; } if test "${r_cv_path_TK_CONFIG+set}" = set; then : $as_echo_n "(cached) " >&6 else for ldir in /opt/lib /sw/lib /usr/local/lib /usr/lib /lib /usr/lib64 ; do for dir in \ ${ldir} \ `ls -d ${ldir}/tk[8-9].[0-9]* 2>/dev/null | sort -r`; do if test -f ${dir}/tkConfig.sh; then r_cv_path_TK_CONFIG="${dir}/tkConfig.sh" break 2 fi done done fi if test -n "${r_cv_path_TK_CONFIG}"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: ${r_cv_path_TK_CONFIG}" >&5 $as_echo "${r_cv_path_TK_CONFIG}" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test -n "${r_cv_path_TK_CONFIG}"; then TK_CONFIG="${r_cv_path_TK_CONFIG}" fi fi if test -z "${TCLTK_CPPFLAGS}" \ || test -z "${TCLTK_LIBS}"; then ## Check whether the versions found via the *Config.sh files are at ## least 8; otherwise, issue a warning and turn off Tcl/Tk support. ## Note that in theory a system could have outdated versions of the ## *Config.sh scripts and yet up-to-date installations of Tcl/Tk in ## standard places ... if test -n "${TCL_CONFIG}"; then . ${TCL_CONFIG} if test ${TCL_MAJOR_VERSION} -lt 8; then warn_tcltk_version="Tcl/Tk support requires Tcl version >= 8" { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: ${warn_tcltk_version}" >&5 $as_echo "$as_me: WARNING: ${warn_tcltk_version}" >&2;} have_tcltk=no fi fi if test -n "${TK_CONFIG}" \ && test -z "${warn_tcltk_version}"; then . ${TK_CONFIG} if test ${TK_MAJOR_VERSION} -lt 8; then warn_tcltk_version="Tcl/Tk support requires Tk version >= 8" { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: ${warn_tcltk_version}" >&5 $as_echo "$as_me: WARNING: ${warn_tcltk_version}" >&2;} have_tcltk=no fi fi if test -n "${TCL_CONFIG}" \ && test -n "${TK_CONFIG}" \ && test -z "${warn_tcltk_version}"; then if test ${TCL_MAJOR_VERSION} -ne ${TK_MAJOR_VERSION} \ || test ${TCL_MINOR_VERSION} -ne ${TK_MINOR_VERSION}; then warn_tcltk_version="Tcl and Tk major or minor versions disagree" { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: ${warn_tcltk_version}" >&5 $as_echo "$as_me: WARNING: ${warn_tcltk_version}" >&2;} have_tcltk=no fi fi fi if test -z "${TCLTK_CPPFLAGS}"; then ## We have to do the work. if test "${have_tcltk}" = yes; then ## Part 1. Check for tcl.h. found_tcl_h=no if test -n "${TCL_CONFIG}"; then . ${TCL_CONFIG} ## Look for tcl.h in ## ${TCL_PREFIX}/include/tcl${TCL_VERSION} ## ${TCL_PREFIX}/include ## Also look in ## ${TCL_PREFIX}/include/tcl${TCL_VERSION}/generic ## to deal with current FreeBSD layouts. These also link the real ## thing to the version subdir, but the link cannot be used as it ## fails to include 'tclDecls.h' which is not linked. Hence we ## must look for the real thing first. Argh ... for dir in \ ${TCL_PREFIX}/include/tcl${TCL_VERSION}/generic \ ${TCL_PREFIX}/include/tcl${TCL_VERSION} \ ${TCL_PREFIX}/include; do as_ac_Header=`$as_echo "ac_cv_header_${dir}/tcl.h" | $as_tr_sh` ac_fn_c_check_header_mongrel "$LINENO" "${dir}/tcl.h" "$as_ac_Header" "$ac_includes_default" eval as_val=\$$as_ac_Header if test "x$as_val" = x""yes; then : TCLTK_CPPFLAGS="-I${dir}" found_tcl_h=yes break fi done fi if test "${found_tcl_h}" = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tcl.h" >&5 $as_echo_n "checking for tcl.h... " >&6; } if test "${r_cv_header_tcl_h+set}" = set; then : $as_echo_n "(cached) " >&6 else cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include #if (TCL_MAJOR_VERSION >= 8) yes #endif _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "yes" >/dev/null 2>&1; then : r_cv_header_tcl_h=yes else r_cv_header_tcl_h=no fi rm -f conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $r_cv_header_tcl_h" >&5 $as_echo "$r_cv_header_tcl_h" >&6; } if test "${r_cv_header_tcl_h}" = yes; then found_tcl_h=yes else have_tcltk=no fi fi fi if test "${have_tcltk}" = yes; then ## Part 2. Check for tk.h. found_tk_h=no if test -n "${TK_CONFIG}"; then . ${TK_CONFIG} ## Look for tk.h in ## ${TK_PREFIX}/include/tk${TK_VERSION} ## ${TK_PREFIX}/include ## Also look in ## ${TK_PREFIX}/include/tcl${TK_VERSION} ## to compensate for Debian madness ... ## Also look in ## ${TK_PREFIX}/include/tk${TK_VERSION}/generic ## to deal with current FreeBSD layouts. See above for details. ## ## As the AC_CHECK_HEADER test tries including the header file and ## tk.h includes tcl.h and X11/Xlib.h, we need to change CPPFLAGS ## for the check. r_save_CPPFLAGS="${CPPFLAGS}" CPPFLAGS="${CPPFLAGS} ${TK_XINCLUDES} ${TCLTK_CPPFLAGS}" for dir in \ ${TK_PREFIX}/include/tk${TK_VERSION}/generic \ ${TK_PREFIX}/include/tk${TK_VERSION} \ ${TK_PREFIX}/include/tcl${TK_VERSION} \ ${TK_PREFIX}/include; do as_ac_Header=`$as_echo "ac_cv_header_${dir}/tk.h" | $as_tr_sh` ac_fn_c_check_header_mongrel "$LINENO" "${dir}/tk.h" "$as_ac_Header" "$ac_includes_default" eval as_val=\$$as_ac_Header if test "x$as_val" = x""yes; then : TCLTK_CPPFLAGS="${TCLTK_CPPFLAGS} -I${dir}" found_tk_h=yes break fi done CPPFLAGS="${r_save_CPPFLAGS}" fi if test "${found_tk_h}" = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tk.h" >&5 $as_echo_n "checking for tk.h... " >&6; } if test "${r_cv_header_tk_h+set}" = set; then : $as_echo_n "(cached) " >&6 else cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include #if (TK_MAJOR_VERSION >= 8) yes #endif _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "yes" >/dev/null 2>&1; then : r_cv_header_tk_h=yes else r_cv_header_tk_h=no fi rm -f conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $r_cv_header_tk_h" >&5 $as_echo "$r_cv_header_tk_h" >&6; } if test "{r_cv_header_tk_h}" = yes; then found_tk_h=yes else have_tcltk=no fi fi fi fi if test "${have_tcltk}" = yes; then if test -n "${TK_XINCLUDES}"; then TCLTK_CPPFLAGS="${TCLTK_CPPFLAGS} ${TK_XINCLUDES}" else TCLTK_CPPFLAGS="${TCLTK_CPPFLAGS} ${X_CFLAGS}" fi fi if test -z "${TCLTK_LIBS}"; then ## We have to do the work. if test "${have_tcltk}" = yes; then ## Part 1. Try finding the tcl library. if test -n "${TCL_CONFIG}"; then . ${TCL_CONFIG} TCLTK_LIBS="${TCL_LIB_SPEC}" else { $as_echo "$as_me:${as_lineno-$LINENO}: checking for Tcl_CreateInterp in -ltcl" >&5 $as_echo_n "checking for Tcl_CreateInterp in -ltcl... " >&6; } if test "${ac_cv_lib_tcl_Tcl_CreateInterp+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ltcl $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char Tcl_CreateInterp (); int main () { return Tcl_CreateInterp (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_tcl_Tcl_CreateInterp=yes else ac_cv_lib_tcl_Tcl_CreateInterp=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_tcl_Tcl_CreateInterp" >&5 $as_echo "$ac_cv_lib_tcl_Tcl_CreateInterp" >&6; } if test "x$ac_cv_lib_tcl_Tcl_CreateInterp" = x""yes; then : TCLTK_LIBS=-ltcl else have_tcltk=no fi fi fi if test "${have_tcltk}" = yes; then ## Part 2. Try finding the tk library. if test -n "${TK_CONFIG}"; then . ${TK_CONFIG} TCLTK_LIBS="${TCLTK_LIBS} ${TK_LIB_SPEC} ${TK_LIBS}" else { $as_echo "$as_me:${as_lineno-$LINENO}: checking for Tk_Init in -ltk" >&5 $as_echo_n "checking for Tk_Init in -ltk... " >&6; } if test "${ac_cv_lib_tk_Tk_Init+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ltk ${TCLTK_LIBS} $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char Tk_Init (); int main () { return Tk_Init (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_tk_Tk_Init=yes else ac_cv_lib_tk_Tk_Init=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_tk_Tk_Init" >&5 $as_echo "$ac_cv_lib_tk_Tk_Init" >&6; } if test "x$ac_cv_lib_tk_Tk_Init" = x""yes; then : cat >>confdefs.h <<_ACEOF @%:@define HAVE_LIBTK 1 _ACEOF LIBS="-ltk $LIBS" fi if test "${ac_cv_lib_tk_Tk_Init}" = no; then ## Grr, simple -ltk does not work. ## But maybe we simply need to add X11 libs. ## Note that we cannot simply repeat the above test with extra ## libs, because AC_CHECK_LIB uses the corresponding cache var ## (ac_cv_lib_tk_Tk_Init in our case) if set. As using unset ## is not portable shell programming according to the Autoconf ## docs, we use Tk_SafeInit in the test with X11 libs added. { $as_echo "$as_me:${as_lineno-$LINENO}: checking for Tk_SafeInit in -ltk" >&5 $as_echo_n "checking for Tk_SafeInit in -ltk... " >&6; } if test "${ac_cv_lib_tk_Tk_SafeInit+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ltk ${TCLTK_LIBS} ${X_LIBS} $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char Tk_SafeInit (); int main () { return Tk_SafeInit (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_tk_Tk_SafeInit=yes else ac_cv_lib_tk_Tk_SafeInit=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_tk_Tk_SafeInit" >&5 $as_echo "$ac_cv_lib_tk_Tk_SafeInit" >&6; } if test "x$ac_cv_lib_tk_Tk_SafeInit" = x""yes; then : TCLTK_LIBS="${TCLTK_LIBS} -ltk ${X_LIBS}" else have_tcltk=no fi fi fi fi ## Postprocessing for AIX. ## On AIX, the *_LIB_SPEC variables need to contain '-bI:' flags for ## the Tcl export file. These are really flags for ld rather than the ## C/C++ compilers, and hence may need protection via '-Wl,'. ## We have two ways of doing that: ## * Recording whether '-Wl,' is needed for the C or C++ compilers, ## and getting this info into the TCLTK_LIBS make variable ... mess! ## * Protecting all entries in TCLTK_LIBS that do not start with '-l' ## or '-L' with '-Wl,' (hoping that all compilers understand this). ## Easy, hence ... case "${host_os}" in aix*) orig_TCLTK_LIBS="${TCLTK_LIBS}" TCLTK_LIBS= for flag in ${orig_TCLTK_LIBS}; do case "${flag}" in -l*|-L*|-Wl,*) ;; *) flag="-Wl,${flag}" ;; esac TCLTK_LIBS="${TCLTK_LIBS} ${flag}" done ;; esac ## Force evaluation ('-ltcl8.3${TCL_DBGX}' and friends ...). eval "TCLTK_LIBS=\"${TCLTK_LIBS}\"" fi if test "${have_tcltk}" = yes; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether compiling/linking Tcl/Tk code works" >&5 $as_echo_n "checking whether compiling/linking Tcl/Tk code works... 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TCLTK_CPPFLAGS= TCLTK_LIBS= fi if test "${have_tcltk}" = yes; then $as_echo "@%:@define HAVE_TCLTK 1" >>confdefs.h use_tcltk=yes else use_tcltk=no fi ## Check for browser for help pages if test -z "${COVERED_BROWSER}"; then for ac_prog in firefox safari netscape mozilla galeon kfmclient opera gnome-moz-remote open do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... 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then warn_browser="I could not determine a browser" { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: ${warn_browser}" >&5 $as_echo "$as_me: WARNING: ${warn_browser}" >&2;} else { $as_echo "$as_me:${as_lineno-$LINENO}: result: using default browser ... ${COVERED_BROWSER}" >&5 $as_echo "using default browser ... ${COVERED_BROWSER}" >&6; } fi cat >>confdefs.h <<_ACEOF @%:@define COVERED_BROWSER "$COVERED_BROWSER" _ACEOF @%:@ Check whether --enable-debug was given. if test "${enable_debug+set}" = set; then : enableval=$enable_debug; DEBUGDEF="-DDEBUG_MODE" fi @%:@ Check whether --enable-profiling was given. if test "${enable_profiling+set}" = set; then : enableval=$enable_profiling; PROFILEDEF="-DPROFILER" fi @%:@ Check whether --enable-test was given. if test "${enable_test+set}" = set; then : enableval=$enable_test; TESTMODEDEF="-DTESTMODE" fi ## Simulators supported @%:@ Check whether --with-iv was given. if test "${with_iv+set}" = set; then : withval=$with_iv; if test "${withval}" = no; then want_iv=no elif test "${withval}" = yes; then want_iv=yes else as_ac_Header=`$as_echo "ac_cv_header_$withval/include/iverilog/vpi_user.h" | $as_tr_sh` ac_fn_c_check_header_mongrel "$LINENO" "$withval/include/iverilog/vpi_user.h" "$as_ac_Header" "$ac_includes_default" eval as_val=\$$as_ac_Header if test "x$as_val" = x""yes; then : want_iv=yes iv_prefix="${withval}" iv_inc_prefix="${withval}/include/iverilog" else as_ac_Header=`$as_echo "ac_cv_header_$withval/include/vpi_user.h" | $as_tr_sh` ac_fn_c_check_header_mongrel "$LINENO" "$withval/include/vpi_user.h" "$as_ac_Header" "$ac_includes_default" eval as_val=\$$as_ac_Header if test "x$as_val" = x""yes; then : want_iv=yes iv_prefix="${withval}" iv_inc_prefix="${withval}/include" else as_ac_Header=`$as_echo "ac_cv_header_$withval/include/verilog/vpi_user.h" | $as_tr_sh` ac_fn_c_check_header_mongrel "$LINENO" "$withval/include/verilog/vpi_user.h" "$as_ac_Header" "$ac_includes_default" eval as_val=\$$as_ac_Header if test "x$as_val" = x""yes; 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m4_pattern_allow([^mkdir_p$]) m4trace:configure.in:4: -1- AC_SUBST([AWK]) m4trace:configure.in:4: -1- AC_SUBST_TRACE([AWK]) m4trace:configure.in:4: -1- m4_pattern_allow([^AWK$]) m4trace:configure.in:4: -1- AC_SUBST([SET_MAKE]) m4trace:configure.in:4: -1- AC_SUBST_TRACE([SET_MAKE]) m4trace:configure.in:4: -1- m4_pattern_allow([^SET_MAKE$]) m4trace:configure.in:4: -1- AC_SUBST([am__leading_dot]) m4trace:configure.in:4: -1- AC_SUBST_TRACE([am__leading_dot]) m4trace:configure.in:4: -1- m4_pattern_allow([^am__leading_dot$]) m4trace:configure.in:4: -1- AC_SUBST([AMTAR]) m4trace:configure.in:4: -1- AC_SUBST_TRACE([AMTAR]) m4trace:configure.in:4: -1- m4_pattern_allow([^AMTAR$]) m4trace:configure.in:4: -1- AC_SUBST([am__tar]) m4trace:configure.in:4: -1- AC_SUBST_TRACE([am__tar]) m4trace:configure.in:4: -1- m4_pattern_allow([^am__tar$]) m4trace:configure.in:4: -1- AC_SUBST([am__untar]) m4trace:configure.in:4: -1- AC_SUBST_TRACE([am__untar]) m4trace:configure.in:4: -1- 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m4trace:configure.in:7: -1- AC_SUBST_TRACE([host]) m4trace:configure.in:7: -1- m4_pattern_allow([^host$]) m4trace:configure.in:7: -1- AC_SUBST([host_cpu], [$[1]]) m4trace:configure.in:7: -1- AC_SUBST_TRACE([host_cpu]) m4trace:configure.in:7: -1- m4_pattern_allow([^host_cpu$]) m4trace:configure.in:7: -1- AC_SUBST([host_vendor], [$[2]]) m4trace:configure.in:7: -1- AC_SUBST_TRACE([host_vendor]) m4trace:configure.in:7: -1- m4_pattern_allow([^host_vendor$]) m4trace:configure.in:7: -1- AC_SUBST([host_os]) m4trace:configure.in:7: -1- AC_SUBST_TRACE([host_os]) m4trace:configure.in:7: -1- m4_pattern_allow([^host_os$]) m4trace:configure.in:12: -1- AM_CONDITIONAL([BUILD_CYGWIN], [test x$build_cygwin = xyes]) m4trace:configure.in:12: -1- AC_SUBST([BUILD_CYGWIN_TRUE]) m4trace:configure.in:12: -1- AC_SUBST_TRACE([BUILD_CYGWIN_TRUE]) m4trace:configure.in:12: -1- m4_pattern_allow([^BUILD_CYGWIN_TRUE$]) m4trace:configure.in:12: -1- AC_SUBST([BUILD_CYGWIN_FALSE]) m4trace:configure.in:12: -1- AC_SUBST_TRACE([BUILD_CYGWIN_FALSE]) m4trace:configure.in:12: -1- m4_pattern_allow([^BUILD_CYGWIN_FALSE$]) m4trace:configure.in:12: -1- _AM_SUBST_NOTMAKE([BUILD_CYGWIN_TRUE]) m4trace:configure.in:12: -1- _AM_SUBST_NOTMAKE([BUILD_CYGWIN_FALSE]) m4trace:configure.in:15: -1- AC_SUBST([SET_MAKE]) m4trace:configure.in:15: -1- AC_SUBST_TRACE([SET_MAKE]) m4trace:configure.in:15: -1- m4_pattern_allow([^SET_MAKE$]) m4trace:configure.in:16: -1- AC_SUBST([CC]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([CC]) m4trace:configure.in:16: -1- m4_pattern_allow([^CC$]) m4trace:configure.in:16: -1- AC_SUBST([CFLAGS]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([CFLAGS]) m4trace:configure.in:16: -1- m4_pattern_allow([^CFLAGS$]) m4trace:configure.in:16: -1- AC_SUBST([LDFLAGS]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([LDFLAGS]) m4trace:configure.in:16: -1- m4_pattern_allow([^LDFLAGS$]) m4trace:configure.in:16: -1- AC_SUBST([LIBS]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([LIBS]) m4trace:configure.in:16: -1- m4_pattern_allow([^LIBS$]) m4trace:configure.in:16: -1- AC_SUBST([CPPFLAGS]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([CPPFLAGS]) m4trace:configure.in:16: -1- m4_pattern_allow([^CPPFLAGS$]) m4trace:configure.in:16: -1- AC_SUBST([CC]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([CC]) m4trace:configure.in:16: -1- m4_pattern_allow([^CC$]) m4trace:configure.in:16: -1- AC_SUBST([CC]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([CC]) m4trace:configure.in:16: -1- m4_pattern_allow([^CC$]) m4trace:configure.in:16: -1- AC_SUBST([CC]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([CC]) m4trace:configure.in:16: -1- m4_pattern_allow([^CC$]) m4trace:configure.in:16: -1- AC_SUBST([CC]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([CC]) m4trace:configure.in:16: -1- m4_pattern_allow([^CC$]) m4trace:configure.in:16: -1- AC_SUBST([ac_ct_CC]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([ac_ct_CC]) m4trace:configure.in:16: -1- m4_pattern_allow([^ac_ct_CC$]) m4trace:configure.in:16: -1- AC_SUBST([EXEEXT], [$ac_cv_exeext]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([EXEEXT]) m4trace:configure.in:16: -1- m4_pattern_allow([^EXEEXT$]) m4trace:configure.in:16: -1- AC_SUBST([OBJEXT], [$ac_cv_objext]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([OBJEXT]) m4trace:configure.in:16: -1- m4_pattern_allow([^OBJEXT$]) m4trace:configure.in:16: -1- AC_SUBST([DEPDIR], ["${am__leading_dot}deps"]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([DEPDIR]) m4trace:configure.in:16: -1- m4_pattern_allow([^DEPDIR$]) m4trace:configure.in:16: -1- AC_SUBST([am__include]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([am__include]) m4trace:configure.in:16: -1- m4_pattern_allow([^am__include$]) m4trace:configure.in:16: -1- AC_SUBST([am__quote]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([am__quote]) m4trace:configure.in:16: -1- m4_pattern_allow([^am__quote$]) m4trace:configure.in:16: -1- AM_CONDITIONAL([AMDEP], [test "x$enable_dependency_tracking" != xno]) m4trace:configure.in:16: -1- AC_SUBST([AMDEP_TRUE]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([AMDEP_TRUE]) m4trace:configure.in:16: -1- m4_pattern_allow([^AMDEP_TRUE$]) m4trace:configure.in:16: -1- AC_SUBST([AMDEP_FALSE]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([AMDEP_FALSE]) m4trace:configure.in:16: -1- m4_pattern_allow([^AMDEP_FALSE$]) m4trace:configure.in:16: -1- _AM_SUBST_NOTMAKE([AMDEP_TRUE]) m4trace:configure.in:16: -1- _AM_SUBST_NOTMAKE([AMDEP_FALSE]) m4trace:configure.in:16: -1- AC_SUBST([AMDEPBACKSLASH]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([AMDEPBACKSLASH]) m4trace:configure.in:16: -1- m4_pattern_allow([^AMDEPBACKSLASH$]) m4trace:configure.in:16: -1- _AM_SUBST_NOTMAKE([AMDEPBACKSLASH]) m4trace:configure.in:16: -1- AC_SUBST([CCDEPMODE], [depmode=$am_cv_CC_dependencies_compiler_type]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([CCDEPMODE]) m4trace:configure.in:16: -1- m4_pattern_allow([^CCDEPMODE$]) m4trace:configure.in:16: -1- AM_CONDITIONAL([am__fastdepCC], [ test "x$enable_dependency_tracking" != xno \ && test "$am_cv_CC_dependencies_compiler_type" = gcc3]) m4trace:configure.in:16: -1- AC_SUBST([am__fastdepCC_TRUE]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([am__fastdepCC_TRUE]) m4trace:configure.in:16: -1- m4_pattern_allow([^am__fastdepCC_TRUE$]) m4trace:configure.in:16: -1- AC_SUBST([am__fastdepCC_FALSE]) m4trace:configure.in:16: -1- AC_SUBST_TRACE([am__fastdepCC_FALSE]) m4trace:configure.in:16: -1- m4_pattern_allow([^am__fastdepCC_FALSE$]) m4trace:configure.in:16: -1- _AM_SUBST_NOTMAKE([am__fastdepCC_TRUE]) m4trace:configure.in:16: -1- _AM_SUBST_NOTMAKE([am__fastdepCC_FALSE]) m4trace:configure.in:19: -1- AC_SUBST([SET_MAKE]) m4trace:configure.in:19: -1- AC_SUBST_TRACE([SET_MAKE]) m4trace:configure.in:19: -1- m4_pattern_allow([^SET_MAKE$]) m4trace:configure.in:20: -1- AC_SUBST([RANLIB]) m4trace:configure.in:20: -1- AC_SUBST_TRACE([RANLIB]) m4trace:configure.in:20: -1- m4_pattern_allow([^RANLIB$]) m4trace:configure.in:21: -1- AC_SUBST([YACC]) m4trace:configure.in:21: -1- AC_SUBST_TRACE([YACC]) m4trace:configure.in:21: -1- m4_pattern_allow([^YACC$]) m4trace:configure.in:21: -1- AC_SUBST([YACC]) m4trace:configure.in:21: -1- AC_SUBST_TRACE([YACC]) m4trace:configure.in:21: -1- m4_pattern_allow([^YACC$]) m4trace:configure.in:21: -1- AC_SUBST([YFLAGS]) m4trace:configure.in:21: -1- AC_SUBST_TRACE([YFLAGS]) m4trace:configure.in:21: -1- m4_pattern_allow([^YFLAGS$]) m4trace:configure.in:22: -1- AC_SUBST([LEX]) m4trace:configure.in:22: -1- AC_SUBST_TRACE([LEX]) m4trace:configure.in:22: -1- m4_pattern_allow([^LEX$]) m4trace:configure.in:22: -1- AC_SUBST([LEX_OUTPUT_ROOT], [$ac_cv_prog_lex_root]) m4trace:configure.in:22: -1- AC_SUBST_TRACE([LEX_OUTPUT_ROOT]) m4trace:configure.in:22: -1- m4_pattern_allow([^LEX_OUTPUT_ROOT$]) m4trace:configure.in:22: -1- AC_SUBST([LEXLIB]) m4trace:configure.in:22: -1- AC_SUBST_TRACE([LEXLIB]) m4trace:configure.in:22: -1- m4_pattern_allow([^LEXLIB$]) m4trace:configure.in:22: -1- AC_DEFINE_TRACE_LITERAL([YYTEXT_POINTER]) m4trace:configure.in:22: -1- m4_pattern_allow([^YYTEXT_POINTER$]) m4trace:configure.in:22: -1- AH_OUTPUT([YYTEXT_POINTER], [/* Define to 1 if `lex\' declares `yytext\' as a `char *\' by default, not a `char@<:@@:>@\'. */ @%:@undef YYTEXT_POINTER]) m4trace:configure.in:23: -1- AC_DEFINE_TRACE_LITERAL([_FILE_OFFSET_BITS]) m4trace:configure.in:23: -1- m4_pattern_allow([^_FILE_OFFSET_BITS$]) m4trace:configure.in:23: -1- AH_OUTPUT([_FILE_OFFSET_BITS], [/* Number of bits in a file offset, on hosts where this is settable. */ @%:@undef _FILE_OFFSET_BITS]) m4trace:configure.in:23: -1- AC_DEFINE_TRACE_LITERAL([_LARGE_FILES]) m4trace:configure.in:23: -1- m4_pattern_allow([^_LARGE_FILES$]) m4trace:configure.in:23: -1- AH_OUTPUT([_LARGE_FILES], [/* Define for large files, on AIX-style hosts. */ @%:@undef _LARGE_FILES]) m4trace:configure.in:24: -1- AH_OUTPUT([WORDS_BIGENDIAN], [/* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most 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m4_pattern_allow([^EGREP$]) m4trace:configure.in:24: -1- AC_DEFINE_TRACE_LITERAL([STDC_HEADERS]) m4trace:configure.in:24: -1- m4_pattern_allow([^STDC_HEADERS$]) m4trace:configure.in:24: -1- AH_OUTPUT([STDC_HEADERS], [/* Define to 1 if you have the ANSI C header files. */ @%:@undef STDC_HEADERS]) m4trace:configure.in:24: -1- AH_OUTPUT([HAVE_SYS_TYPES_H], [/* Define to 1 if you have the header file. */ @%:@undef HAVE_SYS_TYPES_H]) m4trace:configure.in:24: -1- AH_OUTPUT([HAVE_SYS_STAT_H], [/* Define to 1 if you have the header file. */ @%:@undef HAVE_SYS_STAT_H]) m4trace:configure.in:24: -1- AH_OUTPUT([HAVE_STDLIB_H], [/* Define to 1 if you have the header file. */ @%:@undef HAVE_STDLIB_H]) m4trace:configure.in:24: -1- AH_OUTPUT([HAVE_STRING_H], [/* Define to 1 if you have the header file. */ @%:@undef HAVE_STRING_H]) m4trace:configure.in:24: -1- AH_OUTPUT([HAVE_MEMORY_H], [/* Define to 1 if you have the header file. */ @%:@undef HAVE_MEMORY_H]) m4trace:configure.in:24: -1- AH_OUTPUT([HAVE_STRINGS_H], [/* Define to 1 if you have the header file. */ @%:@undef HAVE_STRINGS_H]) m4trace:configure.in:24: -1- AH_OUTPUT([HAVE_INTTYPES_H], [/* Define to 1 if you have the header file. */ @%:@undef HAVE_INTTYPES_H]) m4trace:configure.in:24: -1- AH_OUTPUT([HAVE_STDINT_H], [/* Define to 1 if you have the header file. */ @%:@undef HAVE_STDINT_H]) m4trace:configure.in:24: -1- AH_OUTPUT([HAVE_UNISTD_H], [/* Define to 1 if you have the header file. */ @%:@undef HAVE_UNISTD_H]) m4trace:configure.in:24: -1- AC_DEFINE_TRACE_LITERAL([WORDS_BIGENDIAN]) m4trace:configure.in:24: -1- m4_pattern_allow([^WORDS_BIGENDIAN$]) m4trace:configure.in:24: -1- AC_DEFINE_TRACE_LITERAL([AC_APPLE_UNIVERSAL_BUILD]) m4trace:configure.in:24: -1- m4_pattern_allow([^AC_APPLE_UNIVERSAL_BUILD$]) m4trace:configure.in:24: -1- AH_OUTPUT([AC_APPLE_UNIVERSAL_BUILD], [/* Define if building universal (internal helper macro) */ @%:@undef AC_APPLE_UNIVERSAL_BUILD]) m4trace:configure.in:25: -1- AC_SUBST([XGPERF]) m4trace:configure.in:25: -1- AC_SUBST_TRACE([XGPERF]) m4trace:configure.in:25: -1- m4_pattern_allow([^XGPERF$]) m4trace:configure.in:34: -1- AH_OUTPUT([HAVE_LIBZ], [/* Define to 1 if you have the `z\' library (-lz). */ @%:@undef HAVE_LIBZ]) m4trace:configure.in:34: -1- AC_DEFINE_TRACE_LITERAL([HAVE_LIBZ]) m4trace:configure.in:34: -1- m4_pattern_allow([^HAVE_LIBZ$]) m4trace:configure.in:37: -1- _m4_warn([obsolete], [The macro `AC_HELP_STRING' is obsolete. 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There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." help=" Try \`$me --help' for more information." # Parse command line while test $# -gt 0 ; do case $1 in --time-stamp | --time* | -t ) echo "$timestamp" ; exit ;; --version | -v ) echo "$version" ; exit ;; --help | --h* | -h ) echo "$usage"; exit ;; -- ) # Stop option processing shift; break ;; - ) # Use stdin as input. break ;; -* ) echo "$me: invalid option $1$help" >&2 exit 1 ;; * ) break ;; esac done if test $# != 0; then echo "$me: too many arguments$help" >&2 exit 1 fi trap 'exit 1' 1 2 15 # CC_FOR_BUILD -- compiler used by this script. Note that the use of a # compiler to aid in system detection is discouraged as it requires # temporary files to be created and, as you can see below, it is a # headache to deal with in a portable fashion. # Historically, `CC_FOR_BUILD' used to be named `HOST_CC'. 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The system name ranges from "MiNT" over "FreeMiNT" # to the lowercase version "mint" (or "freemint"). Finally # the system name "TOS" denotes a system which is actually not # MiNT. But MiNT is downward compatible to TOS, so this should # be no problem. atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit ;; atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit ;; *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit ;; milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) echo m68k-milan-mint${UNAME_RELEASE} exit ;; hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) echo m68k-hades-mint${UNAME_RELEASE} exit ;; *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) echo m68k-unknown-mint${UNAME_RELEASE} exit ;; m68k:machten:*:*) echo m68k-apple-machten${UNAME_RELEASE} exit ;; powerpc:machten:*:*) echo powerpc-apple-machten${UNAME_RELEASE} exit ;; RISC*:Mach:*:*) echo mips-dec-mach_bsd4.3 exit ;; RISC*:ULTRIX:*:*) echo mips-dec-ultrix${UNAME_RELEASE} exit ;; VAX*:ULTRIX*:*:*) echo vax-dec-ultrix${UNAME_RELEASE} exit ;; 2020:CLIX:*:* | 2430:CLIX:*:*) echo clipper-intergraph-clix${UNAME_RELEASE} exit ;; mips:*:*:UMIPS | mips:*:*:RISCos) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #ifdef __cplusplus #include /* for printf() prototype */ int main (int argc, char *argv[]) { #else int main (argc, argv) int argc; char *argv[]; { #endif #if defined (host_mips) && defined (MIPSEB) #if defined (SYSTYPE_SYSV) printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0); #endif #if defined (SYSTYPE_SVR4) printf ("mips-mips-riscos%ssvr4\n", argv[1]); exit (0); #endif #if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD) printf ("mips-mips-riscos%sbsd\n", argv[1]); exit (0); #endif #endif exit (-1); } EOF $CC_FOR_BUILD -o $dummy $dummy.c && dummyarg=`echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` && SYSTEM_NAME=`$dummy $dummyarg` && { echo "$SYSTEM_NAME"; exit; } echo mips-mips-riscos${UNAME_RELEASE} exit ;; Motorola:PowerMAX_OS:*:*) echo powerpc-motorola-powermax exit ;; Motorola:*:4.3:PL8-*) echo powerpc-harris-powermax exit ;; Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*) echo powerpc-harris-powermax exit ;; Night_Hawk:Power_UNIX:*:*) echo powerpc-harris-powerunix exit ;; m88k:CX/UX:7*:*) echo m88k-harris-cxux7 exit ;; m88k:*:4*:R4*) echo m88k-motorola-sysv4 exit ;; m88k:*:3*:R3*) echo m88k-motorola-sysv3 exit ;; AViiON:dgux:*:*) # DG/UX returns AViiON for all architectures UNAME_PROCESSOR=`/usr/bin/uname -p` if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ] then if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \ [ ${TARGET_BINARY_INTERFACE}x = x ] then echo m88k-dg-dgux${UNAME_RELEASE} else echo m88k-dg-dguxbcs${UNAME_RELEASE} fi else echo i586-dg-dgux${UNAME_RELEASE} fi exit ;; M88*:DolphinOS:*:*) # DolphinOS (SVR3) echo m88k-dolphin-sysv3 exit ;; M88*:*:R3*:*) # Delta 88k system running SVR3 echo m88k-motorola-sysv3 exit ;; XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) echo m88k-tektronix-sysv3 exit ;; Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) echo m68k-tektronix-bsd exit ;; *:IRIX*:*:*) echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'` exit ;; ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id exit ;; # Note that: echo "'`uname -s`'" gives 'AIX ' i*86:AIX:*:*) echo i386-ibm-aix exit ;; ia64:AIX:*:*) if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` else IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${UNAME_MACHINE}-ibm-aix${IBM_REV} exit ;; *:AIX:2:3) if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include main() { if (!__power_pc()) exit(1); puts("powerpc-ibm-aix3.2.5"); exit(0); } EOF if $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` then echo "$SYSTEM_NAME" else echo rs6000-ibm-aix3.2.5 fi elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then echo rs6000-ibm-aix3.2.4 else echo rs6000-ibm-aix3.2 fi exit ;; *:AIX:*:[456]) IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then IBM_ARCH=rs6000 else IBM_ARCH=powerpc fi if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` else IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${IBM_ARCH}-ibm-aix${IBM_REV} exit ;; *:AIX:*:*) echo rs6000-ibm-aix exit ;; ibmrt:4.4BSD:*|romp-ibm:BSD:*) echo romp-ibm-bsd4.4 exit ;; ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to exit ;; # report: romp-ibm BSD 4.3 *:BOSX:*:*) echo rs6000-bull-bosx exit ;; DPX/2?00:B.O.S.:*:*) echo m68k-bull-sysv3 exit ;; 9000/[34]??:4.3bsd:1.*:*) echo m68k-hp-bsd exit ;; hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) echo m68k-hp-bsd4.4 exit ;; 9000/[34678]??:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` case "${UNAME_MACHINE}" in 9000/31? ) HP_ARCH=m68000 ;; 9000/[34]?? ) HP_ARCH=m68k ;; 9000/[678][0-9][0-9]) if [ -x /usr/bin/getconf ]; then sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` case "${sc_cpu_version}" in 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 532) # CPU_PA_RISC2_0 case "${sc_kernel_bits}" in 32) HP_ARCH="hppa2.0n" ;; 64) HP_ARCH="hppa2.0w" ;; '') HP_ARCH="hppa2.0" ;; # HP-UX 10.20 esac ;; esac fi if [ "${HP_ARCH}" = "" ]; then eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #define _HPUX_SOURCE #include #include int main () { #if defined(_SC_KERNEL_BITS) long bits = sysconf(_SC_KERNEL_BITS); #endif long cpu = sysconf (_SC_CPU_VERSION); switch (cpu) { case CPU_PA_RISC1_0: puts ("hppa1.0"); break; case CPU_PA_RISC1_1: puts ("hppa1.1"); break; case CPU_PA_RISC2_0: #if defined(_SC_KERNEL_BITS) switch (bits) { case 64: puts ("hppa2.0w"); break; case 32: puts ("hppa2.0n"); break; default: puts ("hppa2.0"); break; } break; #else /* !defined(_SC_KERNEL_BITS) */ puts ("hppa2.0"); break; #endif default: puts ("hppa1.0"); break; } exit (0); } EOF (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` test -z "$HP_ARCH" && HP_ARCH=hppa fi ;; esac if [ ${HP_ARCH} = "hppa2.0w" ] then eval $set_cc_for_build # hppa2.0w-hp-hpux* has a 64-bit kernel and a compiler generating # 32-bit code. hppa64-hp-hpux* has the same kernel and a compiler # generating 64-bit code. GNU and HP use different nomenclature: # # $ CC_FOR_BUILD=cc ./config.guess # => hppa2.0w-hp-hpux11.23 # $ CC_FOR_BUILD="cc +DA2.0w" ./config.guess # => hppa64-hp-hpux11.23 if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | grep __LP64__ >/dev/null then HP_ARCH="hppa2.0w" else HP_ARCH="hppa64" fi fi echo ${HP_ARCH}-hp-hpux${HPUX_REV} exit ;; ia64:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` echo ia64-hp-hpux${HPUX_REV} exit ;; 3050*:HI-UX:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include int main () { long cpu = sysconf (_SC_CPU_VERSION); /* The order matters, because CPU_IS_HP_MC68K erroneously returns true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct results, however. */ if (CPU_IS_PA_RISC (cpu)) { switch (cpu) { case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; default: puts ("hppa-hitachi-hiuxwe2"); break; } } else if (CPU_IS_HP_MC68K (cpu)) puts ("m68k-hitachi-hiuxwe2"); else puts ("unknown-hitachi-hiuxwe2"); exit (0); } EOF $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` && { echo "$SYSTEM_NAME"; exit; } echo unknown-hitachi-hiuxwe2 exit ;; 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) echo hppa1.1-hp-bsd exit ;; 9000/8??:4.3bsd:*:*) echo hppa1.0-hp-bsd exit ;; *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) echo hppa1.0-hp-mpeix exit ;; hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) echo hppa1.1-hp-osf exit ;; hp8??:OSF1:*:*) echo hppa1.0-hp-osf exit ;; i*86:OSF1:*:*) if [ -x /usr/sbin/sysversion ] ; then echo ${UNAME_MACHINE}-unknown-osf1mk else echo ${UNAME_MACHINE}-unknown-osf1 fi exit ;; parisc*:Lites*:*:*) echo hppa1.1-hp-lites exit ;; C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) echo c1-convex-bsd exit ;; C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi exit ;; C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) echo c34-convex-bsd exit ;; C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) echo c38-convex-bsd exit ;; C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) echo c4-convex-bsd exit ;; CRAY*Y-MP:*:*:*) echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; CRAY*[A-Z]90:*:*:*) echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \ | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ -e 's/\.[^.]*$/.X/' exit ;; CRAY*TS:*:*:*) echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; CRAY*T3E:*:*:*) echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; CRAY*SV1:*:*:*) echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; *:UNICOS/mp:*:*) echo craynv-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" exit ;; 5000:UNIX_System_V:4.*:*) FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'` echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" exit ;; i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} exit ;; sparc*:BSD/OS:*:*) echo sparc-unknown-bsdi${UNAME_RELEASE} exit ;; *:BSD/OS:*:*) echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} exit ;; *:FreeBSD:*:*) case ${UNAME_MACHINE} in pc98) echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; amd64) echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; *) echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; esac exit ;; i*:CYGWIN*:*) echo ${UNAME_MACHINE}-pc-cygwin exit ;; *:MINGW*:*) echo ${UNAME_MACHINE}-pc-mingw32 exit ;; i*:windows32*:*) # uname -m includes "-pc" on this system. echo ${UNAME_MACHINE}-mingw32 exit ;; i*:PW*:*) echo ${UNAME_MACHINE}-pc-pw32 exit ;; *:Interix*:[3456]*) case ${UNAME_MACHINE} in x86) echo i586-pc-interix${UNAME_RELEASE} exit ;; EM64T | authenticamd | genuineintel) echo x86_64-unknown-interix${UNAME_RELEASE} exit ;; IA64) echo ia64-unknown-interix${UNAME_RELEASE} exit ;; esac ;; [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) echo i${UNAME_MACHINE}-pc-mks exit ;; i*:Windows_NT*:* | Pentium*:Windows_NT*:*) # How do we know it's Interix rather than the generic POSIX subsystem? # It also conflicts with pre-2.0 versions of AT&T UWIN. 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avr32*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; cris:Linux:*:*) echo cris-axis-linux-gnu exit ;; crisv32:Linux:*:*) echo crisv32-axis-linux-gnu exit ;; frv:Linux:*:*) echo frv-unknown-linux-gnu exit ;; ia64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; m32r*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; m68*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; mips:Linux:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #undef CPU #undef mips #undef mipsel #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) CPU=mipsel #else #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) CPU=mips #else CPU= #endif #endif EOF eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' /^CPU/{ s: ::g p }'`" test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } ;; mips64:Linux:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #undef CPU #undef mips64 #undef mips64el #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) CPU=mips64el #else #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) CPU=mips64 #else CPU= #endif #endif EOF eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' /^CPU/{ s: ::g p }'`" test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } ;; or32:Linux:*:*) echo or32-unknown-linux-gnu exit ;; ppc:Linux:*:*) echo powerpc-unknown-linux-gnu exit ;; ppc64:Linux:*:*) echo powerpc64-unknown-linux-gnu exit ;; alpha:Linux:*:*) case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in EV5) UNAME_MACHINE=alphaev5 ;; EV56) UNAME_MACHINE=alphaev56 ;; PCA56) UNAME_MACHINE=alphapca56 ;; PCA57) UNAME_MACHINE=alphapca56 ;; EV6) UNAME_MACHINE=alphaev6 ;; EV67) UNAME_MACHINE=alphaev67 ;; EV68*) UNAME_MACHINE=alphaev68 ;; esac objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} exit ;; padre:Linux:*:*) echo sparc-unknown-linux-gnu exit ;; parisc:Linux:*:* | hppa:Linux:*:*) # Look for CPU level case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in PA7*) echo hppa1.1-unknown-linux-gnu ;; PA8*) echo hppa2.0-unknown-linux-gnu ;; *) echo hppa-unknown-linux-gnu ;; esac exit ;; parisc64:Linux:*:* | hppa64:Linux:*:*) echo hppa64-unknown-linux-gnu exit ;; s390:Linux:*:* | s390x:Linux:*:*) echo ${UNAME_MACHINE}-ibm-linux exit ;; sh64*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; sh*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; sparc:Linux:*:* | sparc64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; vax:Linux:*:*) echo ${UNAME_MACHINE}-dec-linux-gnu exit ;; x86_64:Linux:*:*) echo x86_64-unknown-linux-gnu exit ;; xtensa*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; i*86:Linux:*:*) # The BFD linker knows what the default object file format is, so # first see if it will tell us. cd to the root directory to prevent # problems with other programs or directories called `ld' in the path. # Set LC_ALL=C to ensure ld outputs messages in English. ld_supported_targets=`cd /; LC_ALL=C ld --help 2>&1 \ | sed -ne '/supported targets:/!d s/[ ][ ]*/ /g s/.*supported targets: *// s/ .*// p'` case "$ld_supported_targets" in elf32-i386) TENTATIVE="${UNAME_MACHINE}-pc-linux-gnu" ;; a.out-i386-linux) echo "${UNAME_MACHINE}-pc-linux-gnuaout" exit ;; "") # Either a pre-BFD a.out linker (linux-gnuoldld) or # one that does not give us useful --help. echo "${UNAME_MACHINE}-pc-linux-gnuoldld" exit ;; esac # Determine whether the default compiler is a.out or elf eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include #ifdef __ELF__ # ifdef __GLIBC__ # if __GLIBC__ >= 2 LIBC=gnu # else LIBC=gnulibc1 # endif # else LIBC=gnulibc1 # endif #else #if defined(__INTEL_COMPILER) || defined(__PGI) || defined(__SUNPRO_C) || defined(__SUNPRO_CC) LIBC=gnu #else LIBC=gnuaout #endif #endif #ifdef __dietlibc__ LIBC=dietlibc #endif EOF eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' /^LIBC/{ s: ::g p }'`" test x"${LIBC}" != x && { echo "${UNAME_MACHINE}-pc-linux-${LIBC}" exit } test x"${TENTATIVE}" != x && { echo "${TENTATIVE}"; exit; } ;; i*86:DYNIX/ptx:4*:*) # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. # earlier versions are messed up and put the nodename in both # sysname and nodename. echo i386-sequent-sysv4 exit ;; i*86:UNIX_SV:4.2MP:2.*) # Unixware is an offshoot of SVR4, but it has its own version # number series starting with 2... # I am not positive that other SVR4 systems won't match this, # I just have to hope. -- rms. # Use sysv4.2uw... so that sysv4* matches it. echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} exit ;; i*86:OS/2:*:*) # If we were able to find `uname', then EMX Unix compatibility # is probably installed. echo ${UNAME_MACHINE}-pc-os2-emx exit ;; i*86:XTS-300:*:STOP) echo ${UNAME_MACHINE}-unknown-stop exit ;; i*86:atheos:*:*) echo ${UNAME_MACHINE}-unknown-atheos exit ;; i*86:syllable:*:*) echo ${UNAME_MACHINE}-pc-syllable exit ;; i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*) echo i386-unknown-lynxos${UNAME_RELEASE} exit ;; i*86:*DOS:*:*) echo ${UNAME_MACHINE}-pc-msdosdjgpp exit ;; i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*) UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'` if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then echo ${UNAME_MACHINE}-univel-sysv${UNAME_REL} else echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL} fi exit ;; i*86:*:5:[678]*) # UnixWare 7.x, OpenUNIX and OpenServer 6. case `/bin/uname -X | grep "^Machine"` in *486*) UNAME_MACHINE=i486 ;; *Pentium) UNAME_MACHINE=i586 ;; *Pent*|*Celeron) UNAME_MACHINE=i686 ;; esac echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION} exit ;; i*86:*:3.2:*) if test -f /usr/options/cb.name; then UNAME_REL=`sed -n 's/.*Version //p' /dev/null >/dev/null ; then UNAME_REL=`(/bin/uname -X|grep Release|sed -e 's/.*= //')` (/bin/uname -X|grep i80486 >/dev/null) && UNAME_MACHINE=i486 (/bin/uname -X|grep '^Machine.*Pentium' >/dev/null) \ && UNAME_MACHINE=i586 (/bin/uname -X|grep '^Machine.*Pent *II' >/dev/null) \ && UNAME_MACHINE=i686 (/bin/uname -X|grep '^Machine.*Pentium Pro' >/dev/null) \ && UNAME_MACHINE=i686 echo ${UNAME_MACHINE}-pc-sco$UNAME_REL else echo ${UNAME_MACHINE}-pc-sysv32 fi exit ;; pc:*:*:*) # Left here for compatibility: # uname -m prints for DJGPP always 'pc', but it prints nothing about # the processor, so we play safe by assuming i586. # Note: whatever this is, it MUST be the same as what config.sub # prints for the "djgpp" host, or else GDB configury will decide that # this is a cross-build. echo i586-pc-msdosdjgpp exit ;; Intel:Mach:3*:*) echo i386-pc-mach3 exit ;; paragon:*:*:*) echo i860-intel-osf1 exit ;; i860:*:4.*:*) # i860-SVR4 if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4 else # Add other i860-SVR4 vendors below as they are discovered. echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4 fi exit ;; mini*:CTIX:SYS*5:*) # "miniframe" echo m68010-convergent-sysv exit ;; mc68k:UNIX:SYSTEM5:3.51m) echo m68k-convergent-sysv exit ;; M680?0:D-NIX:5.3:*) echo m68k-diab-dnix exit ;; M68*:*:R3V[5678]*:*) test -r /sysV68 && { echo 'm68k-motorola-sysv'; exit; } ;; 3[345]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0 | SHG2:*:4.0:3.0 | S7501*:*:4.0:3.0) OS_REL='' test -r /etc/.relid \ && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ && { echo i486-ncr-sysv4.3${OS_REL}; exit; } /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;; 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ && { echo i486-ncr-sysv4; exit; } ;; NCR*:*:4.2:* | MPRAS*:*:4.2:*) OS_REL='.3' test -r /etc/.relid \ && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ && { echo i486-ncr-sysv4.3${OS_REL}; exit; } /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ && { echo i586-ncr-sysv4.3${OS_REL}; exit; } /bin/uname -p 2>/dev/null | /bin/grep pteron >/dev/null \ && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;; m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) echo m68k-unknown-lynxos${UNAME_RELEASE} exit ;; mc68030:UNIX_System_V:4.*:*) echo m68k-atari-sysv4 exit ;; TSUNAMI:LynxOS:2.*:*) echo sparc-unknown-lynxos${UNAME_RELEASE} exit ;; rs6000:LynxOS:2.*:*) echo rs6000-unknown-lynxos${UNAME_RELEASE} exit ;; PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.0*:*) echo powerpc-unknown-lynxos${UNAME_RELEASE} exit ;; SM[BE]S:UNIX_SV:*:*) echo mips-dde-sysv${UNAME_RELEASE} exit ;; RM*:ReliantUNIX-*:*:*) echo mips-sni-sysv4 exit ;; RM*:SINIX-*:*:*) echo mips-sni-sysv4 exit ;; *:SINIX-*:*:*) if uname -p 2>/dev/null >/dev/null ; then UNAME_MACHINE=`(uname -p) 2>/dev/null` echo ${UNAME_MACHINE}-sni-sysv4 else echo ns32k-sni-sysv fi exit ;; PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort # says echo i586-unisys-sysv4 exit ;; *:UNIX_System_V:4*:FTX*) # From Gerald Hewes . # How about differentiating between stratus architectures? -djm echo hppa1.1-stratus-sysv4 exit ;; *:*:*:FTX*) # From seanf@swdc.stratus.com. echo i860-stratus-sysv4 exit ;; i*86:VOS:*:*) # From Paul.Green@stratus.com. echo ${UNAME_MACHINE}-stratus-vos exit ;; *:VOS:*:*) # From Paul.Green@stratus.com. echo hppa1.1-stratus-vos exit ;; mc68*:A/UX:*:*) echo m68k-apple-aux${UNAME_RELEASE} exit ;; news*:NEWS-OS:6*:*) echo mips-sony-newsos6 exit ;; R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) if [ -d /usr/nec ]; then echo mips-nec-sysv${UNAME_RELEASE} else echo mips-unknown-sysv${UNAME_RELEASE} fi exit ;; BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. echo powerpc-be-beos exit ;; BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only. echo powerpc-apple-beos exit ;; BePC:BeOS:*:*) # BeOS running on Intel PC compatible. echo i586-pc-beos exit ;; BePC:Haiku:*:*) # Haiku running on Intel PC compatible. echo i586-pc-haiku exit ;; SX-4:SUPER-UX:*:*) echo sx4-nec-superux${UNAME_RELEASE} exit ;; SX-5:SUPER-UX:*:*) echo sx5-nec-superux${UNAME_RELEASE} exit ;; SX-6:SUPER-UX:*:*) echo sx6-nec-superux${UNAME_RELEASE} exit ;; SX-7:SUPER-UX:*:*) echo sx7-nec-superux${UNAME_RELEASE} exit ;; SX-8:SUPER-UX:*:*) echo sx8-nec-superux${UNAME_RELEASE} exit ;; SX-8R:SUPER-UX:*:*) echo sx8r-nec-superux${UNAME_RELEASE} exit ;; Power*:Rhapsody:*:*) echo powerpc-apple-rhapsody${UNAME_RELEASE} exit ;; *:Rhapsody:*:*) echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE} exit ;; *:Darwin:*:*) UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown case $UNAME_PROCESSOR in unknown) UNAME_PROCESSOR=powerpc ;; esac echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} exit ;; *:procnto*:*:* | *:QNX:[0123456789]*:*) UNAME_PROCESSOR=`uname -p` if test "$UNAME_PROCESSOR" = "x86"; then UNAME_PROCESSOR=i386 UNAME_MACHINE=pc fi echo ${UNAME_PROCESSOR}-${UNAME_MACHINE}-nto-qnx${UNAME_RELEASE} exit ;; *:QNX:*:4*) echo i386-pc-qnx exit ;; NSE-?:NONSTOP_KERNEL:*:*) echo nse-tandem-nsk${UNAME_RELEASE} exit ;; NSR-?:NONSTOP_KERNEL:*:*) echo nsr-tandem-nsk${UNAME_RELEASE} exit ;; *:NonStop-UX:*:*) echo mips-compaq-nonstopux exit ;; BS2000:POSIX*:*:*) echo bs2000-siemens-sysv exit ;; DS/*:UNIX_System_V:*:*) echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE} exit ;; *:Plan9:*:*) # "uname -m" is not consistent, so use $cputype instead. 386 # is converted to i386 for consistency with other x86 # operating systems. if test "$cputype" = "386"; then UNAME_MACHINE=i386 else UNAME_MACHINE="$cputype" fi echo ${UNAME_MACHINE}-unknown-plan9 exit ;; *:TOPS-10:*:*) echo pdp10-unknown-tops10 exit ;; *:TENEX:*:*) echo pdp10-unknown-tenex exit ;; KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*) echo pdp10-dec-tops20 exit ;; XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*) echo pdp10-xkl-tops20 exit ;; *:TOPS-20:*:*) echo pdp10-unknown-tops20 exit ;; *:ITS:*:*) echo pdp10-unknown-its exit ;; SEI:*:*:SEIUX) echo mips-sei-seiux${UNAME_RELEASE} exit ;; *:DragonFly:*:*) echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` exit ;; *:*VMS:*:*) UNAME_MACHINE=`(uname -p) 2>/dev/null` case "${UNAME_MACHINE}" in A*) echo alpha-dec-vms ; exit ;; I*) echo ia64-dec-vms ; exit ;; V*) echo vax-dec-vms ; exit ;; esac ;; *:XENIX:*:SysV) echo i386-pc-xenix exit ;; i*86:skyos:*:*) echo ${UNAME_MACHINE}-pc-skyos`echo ${UNAME_RELEASE}` | sed -e 's/ .*$//' exit ;; i*86:rdos:*:*) echo ${UNAME_MACHINE}-pc-rdos exit ;; i*86:AROS:*:*) echo ${UNAME_MACHINE}-pc-aros exit ;; esac #echo '(No uname command or uname output not recognized.)' 1>&2 #echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 eval $set_cc_for_build cat >$dummy.c < # include #endif main () { #if defined (sony) #if defined (MIPSEB) /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, I don't know.... */ printf ("mips-sony-bsd\n"); exit (0); #else #include printf ("m68k-sony-newsos%s\n", #ifdef NEWSOS4 "4" #else "" #endif ); exit (0); #endif #endif #if defined (__arm) && defined (__acorn) && defined (__unix) printf ("arm-acorn-riscix\n"); exit (0); #endif #if defined (hp300) && !defined (hpux) printf ("m68k-hp-bsd\n"); exit (0); #endif #if defined (NeXT) #if !defined (__ARCHITECTURE__) #define __ARCHITECTURE__ "m68k" #endif int version; version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; if (version < 4) printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); else printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); exit (0); #endif #if defined (MULTIMAX) || defined (n16) #if defined (UMAXV) printf ("ns32k-encore-sysv\n"); exit (0); #else #if defined (CMU) printf ("ns32k-encore-mach\n"); exit (0); #else printf ("ns32k-encore-bsd\n"); exit (0); #endif #endif #endif #if defined (__386BSD__) printf ("i386-pc-bsd\n"); exit (0); #endif #if defined (sequent) #if defined (i386) printf ("i386-sequent-dynix\n"); exit (0); #endif #if defined (ns32000) printf ("ns32k-sequent-dynix\n"); exit (0); #endif #endif #if defined (_SEQUENT_) struct utsname un; uname(&un); if (strncmp(un.version, "V2", 2) == 0) { printf ("i386-sequent-ptx2\n"); exit (0); } if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ printf ("i386-sequent-ptx1\n"); exit (0); } printf ("i386-sequent-ptx\n"); exit (0); #endif #if defined (vax) # if !defined (ultrix) # include # if defined (BSD) # if BSD == 43 printf ("vax-dec-bsd4.3\n"); exit (0); # else # if BSD == 199006 printf ("vax-dec-bsd4.3reno\n"); exit (0); # else printf ("vax-dec-bsd\n"); exit (0); # endif # endif # else printf ("vax-dec-bsd\n"); exit (0); # endif # else printf ("vax-dec-ultrix\n"); exit (0); # endif #endif #if defined (alliant) && defined (i860) printf ("i860-alliant-bsd\n"); exit (0); #endif exit (1); } EOF $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && SYSTEM_NAME=`$dummy` && { echo "$SYSTEM_NAME"; exit; } # Apollos put the system type in the environment. test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit; } # Convex versions that predate uname can use getsysinfo(1) if [ -x /usr/convex/getsysinfo ] then case `getsysinfo -f cpu_type` in c1*) echo c1-convex-bsd exit ;; c2*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi exit ;; c34*) echo c34-convex-bsd exit ;; c38*) echo c38-convex-bsd exit ;; c4*) echo c4-convex-bsd exit ;; esac fi cat >&2 < in order to provide the needed information to handle your system. config.guess timestamp = $timestamp uname -m = `(uname -m) 2>/dev/null || echo unknown` uname -r = `(uname -r) 2>/dev/null || echo unknown` uname -s = `(uname -s) 2>/dev/null || echo unknown` uname -v = `(uname -v) 2>/dev/null || echo unknown` /usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null` /bin/uname -X = `(/bin/uname -X) 2>/dev/null` hostinfo = `(hostinfo) 2>/dev/null` /bin/universe = `(/bin/universe) 2>/dev/null` /usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null` /bin/arch = `(/bin/arch) 2>/dev/null` /usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null` /usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null` UNAME_MACHINE = ${UNAME_MACHINE} UNAME_RELEASE = ${UNAME_RELEASE} UNAME_SYSTEM = ${UNAME_SYSTEM} UNAME_VERSION = ${UNAME_VERSION} EOF exit 1 # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "timestamp='" # time-stamp-format: "%:y-%02m-%02d" # time-stamp-end: "'" # End: covered-0.7.10/config.h.in0000644000076500007650000000670511356776516015316 0ustar trevorwtrevorw/* config.h.in. Generated from configure.in by autoheader. */ /* Define if building universal (internal helper macro) */ #undef AC_APPLE_UNIVERSAL_BUILD /* Browser to view help pages with */ #undef COVERED_BROWSER /* Define to 1 if you have the header file. */ #undef HAVE_INTTYPES_H /* Define to 1 if you have the `m' library (-lm). */ #undef HAVE_LIBM /* Define to 1 if you have the `tk' library (-ltk). */ #undef HAVE_LIBTK /* Define to 1 if you have the `z' library (-lz). */ #undef HAVE_LIBZ /* Define to 1 if you have the header file. */ #undef HAVE_MATH_H /* Define to 1 if you have the header file. */ #undef HAVE_MEMORY_H /* Define to 1 if you have the header file. */ #undef HAVE_STDINT_H /* Define to 1 if you have the header file. */ #undef HAVE_STDLIB_H /* Define to 1 if you have the header file. */ #undef HAVE_STRINGS_H /* Define to 1 if you have the header file. */ #undef HAVE_STRING_H /* Define to 1 if you have the header file. */ #undef HAVE_SYS_STAT_H /* Define to 1 if you have the header file. */ #undef HAVE_SYS_TIME_H /* Define to 1 if you have the header file. */ #undef HAVE_SYS_TYPES_H /* Define if you have the Tcl/Tk headers and libraries and want Tcl/Tk support to be built. */ #undef HAVE_TCLTK /* Define to 1 if you have the header file. */ #undef HAVE_UNISTD_H /* Name of package */ #undef PACKAGE /* Define to the address where bug reports for this package should be sent. */ #undef PACKAGE_BUGREPORT /* Define to the full name of this package. */ #undef PACKAGE_NAME /* Define to the full name and version of this package. */ #undef PACKAGE_STRING /* Define to the one symbol short name of this package. */ #undef PACKAGE_TARNAME /* Define to the home page for this package. */ #undef PACKAGE_URL /* Define to the version of this package. */ #undef PACKAGE_VERSION /* Define as the return type of signal handlers (`int' or `void'). */ #undef RETSIGTYPE /* The size of `char', as computed by sizeof. */ #undef SIZEOF_CHAR /* The size of `double', as computed by sizeof. */ #undef SIZEOF_DOUBLE /* The size of `float', as computed by sizeof. */ #undef SIZEOF_FLOAT /* The size of `int', as computed by sizeof. */ #undef SIZEOF_INT /* The size of `long', as computed by sizeof. */ #undef SIZEOF_LONG /* The size of `long long', as computed by sizeof. */ #undef SIZEOF_LONG_LONG /* The size of `short', as computed by sizeof. */ #undef SIZEOF_SHORT /* Define to 1 if you have the ANSI C header files. */ #undef STDC_HEADERS /* Version number of package */ #undef VERSION /* Define WORDS_BIGENDIAN to 1 if your processor stores words with the most significant byte first (like Motorola and SPARC, unlike Intel). */ #if defined AC_APPLE_UNIVERSAL_BUILD # if defined __BIG_ENDIAN__ # define WORDS_BIGENDIAN 1 # endif #else # ifndef WORDS_BIGENDIAN # undef WORDS_BIGENDIAN # endif #endif /* Define to 1 if the X Window System is missing or not being used. */ #undef X_DISPLAY_MISSING /* Define to 1 if `lex' declares `yytext' as a `char *' by default, not a `char[]'. */ #undef YYTEXT_POINTER /* Number of bits in a file offset, on hosts where this is settable. */ #undef _FILE_OFFSET_BITS /* Define for large files, on AIX-style hosts. */ #undef _LARGE_FILES /* Define to empty if `const' does not conform to ANSI C. */ #undef const /* Define to `unsigned int' if does not define. */ #undef size_t covered-0.7.10/config.sub0000644000076500007650000010224011270512352015217 0ustar trevorwtrevorw#! /bin/sh # Configuration validation subroutine script. # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, # 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 # Free Software Foundation, Inc. timestamp='2009-04-17' # This file is (in principle) common to ALL GNU software. # The presence of a machine in this file suggests that SOME GNU software # can handle that machine. It does not imply ALL GNU software can. # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA # 02110-1301, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Please send patches to . Submit a context # diff and a properly formatted ChangeLog entry. # # Configuration subroutine to validate and canonicalize a configuration type. # Supply the specified configuration type as an argument. # If it is invalid, we print an error message on stderr and exit with code 1. # Otherwise, we print the canonical config type on stdout and succeed. # This file is supposed to be the same for all GNU packages # and recognize all the CPU types, system types and aliases # that are meaningful with *any* GNU software. # Each package is responsible for reporting which valid configurations # it does not support. The user should be able to distinguish # a failure to support a valid configuration from a meaningless # configuration. # The goal of this file is to map all the various variations of a given # machine specification into a single specification in the form: # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM # or in some cases, the newer four-part form: # CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM # It is wrong to echo any other type of specification. me=`echo "$0" | sed -e 's,.*/,,'` usage="\ Usage: $0 [OPTION] CPU-MFR-OPSYS $0 [OPTION] ALIAS Canonicalize a configuration name. Operation modes: -h, --help print this help, then exit -t, --time-stamp print date of last modification, then exit -v, --version print version number, then exit Report bugs and patches to ." version="\ GNU config.sub ($timestamp) Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." help=" Try \`$me --help' for more information." # Parse command line while test $# -gt 0 ; do case $1 in --time-stamp | --time* | -t ) echo "$timestamp" ; exit ;; --version | -v ) echo "$version" ; exit ;; --help | --h* | -h ) echo "$usage"; exit ;; -- ) # Stop option processing shift; break ;; - ) # Use stdin as input. break ;; -* ) echo "$me: invalid option $1$help" exit 1 ;; *local*) # First pass through any local machine types. echo $1 exit ;; * ) break ;; esac done case $# in 0) echo "$me: missing argument$help" >&2 exit 1;; 1) ;; *) echo "$me: too many arguments$help" >&2 exit 1;; esac # Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any). # Here we must recognize all the valid KERNEL-OS combinations. maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` case $maybe_os in nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \ uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \ kopensolaris*-gnu* | \ storm-chaos* | os2-emx* | rtmk-nova*) os=-$maybe_os basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` ;; *) basic_machine=`echo $1 | sed 's/-[^-]*$//'` if [ $basic_machine != $1 ] then os=`echo $1 | sed 's/.*-/-/'` else os=; fi ;; esac ### Let's recognize common machines as not being operating systems so ### that things like config.sub decstation-3100 work. We also ### recognize some manufacturers as not being operating systems, so we ### can provide default operating systems below. case $os in -sun*os*) # Prevent following clause from handling this invalid input. ;; -dec* | -mips* | -sequent* | -encore* | -pc532* | -sgi* | -sony* | \ -att* | -7300* | -3300* | -delta* | -motorola* | -sun[234]* | \ -unicom* | -ibm* | -next | -hp | -isi* | -apollo | -altos* | \ -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ -apple | -axis | -knuth | -cray) os= basic_machine=$1 ;; -sim | -cisco | -oki | -wec | -winbond) os= basic_machine=$1 ;; -scout) ;; -wrs) os=-vxworks basic_machine=$1 ;; -chorusos*) os=-chorusos basic_machine=$1 ;; -chorusrdb) os=-chorusrdb basic_machine=$1 ;; -hiux*) os=-hiuxwe2 ;; -sco6) os=-sco5v6 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco5) os=-sco3.2v5 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco4) os=-sco3.2v4 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco3.2.[4-9]*) os=`echo $os | sed -e 's/sco3.2./sco3.2v/'` basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco3.2v[4-9]*) # Don't forget version if it is 3.2v4 or newer. basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco5v6*) # Don't forget version if it is 3.2v4 or newer. basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco*) os=-sco3.2v2 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -udk*) basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -isc) os=-isc2.2 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -clix*) basic_machine=clipper-intergraph ;; -isc*) basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -lynx*) os=-lynxos ;; -ptx*) basic_machine=`echo $1 | sed -e 's/86-.*/86-sequent/'` ;; -windowsnt*) os=`echo $os | sed -e 's/windowsnt/winnt/'` ;; -psos*) os=-psos ;; -mint | -mint[0-9]*) basic_machine=m68k-atari os=-mint ;; esac # Decode aliases for certain CPU-COMPANY combinations. case $basic_machine in # Recognize the basic CPU types without company name. # Some are omitted here because they have special meanings below. 1750a | 580 \ | a29k \ | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ | am33_2.0 \ | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ | bfin \ | c4x | clipper \ | d10v | d30v | dlx | dsp16xx \ | fido | fr30 | frv \ | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ | i370 | i860 | i960 | ia64 \ | ip2k | iq2000 \ | lm32 \ | m32c | m32r | m32rle | m68000 | m68k | m88k \ | maxq | mb | microblaze | mcore | mep | metag \ | mips | mipsbe | mipseb | mipsel | mipsle \ | mips16 \ | mips64 | mips64el \ | mips64octeon | mips64octeonel \ | mips64orion | mips64orionel \ | mips64r5900 | mips64r5900el \ | mips64vr | mips64vrel \ | mips64vr4100 | mips64vr4100el \ | mips64vr4300 | mips64vr4300el \ | mips64vr5000 | mips64vr5000el \ | mips64vr5900 | mips64vr5900el \ | mipsisa32 | mipsisa32el \ | mipsisa32r2 | mipsisa32r2el \ | mipsisa64 | mipsisa64el \ | mipsisa64r2 | mipsisa64r2el \ | mipsisa64sb1 | mipsisa64sb1el \ | mipsisa64sr71k | mipsisa64sr71kel \ | mipstx39 | mipstx39el \ | mn10200 | mn10300 \ | moxie \ | mt \ | msp430 \ | nios | nios2 \ | ns16k | ns32k \ | or32 \ | pdp10 | pdp11 | pj | pjl \ | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \ | pyramid \ | score \ | sh | sh[1234] | sh[24]a | sh[24]aeb | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \ | sh64 | sh64le \ | sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \ | sparcv8 | sparcv9 | sparcv9b | sparcv9v \ | spu | strongarm \ | tahoe | thumb | tic4x | tic80 | tron \ | v850 | v850e \ | we32k \ | x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \ | z8k | z80) basic_machine=$basic_machine-unknown ;; m6811 | m68hc11 | m6812 | m68hc12) # Motorola 68HC11/12. basic_machine=$basic_machine-unknown os=-none ;; m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k) ;; ms1) basic_machine=mt-unknown ;; # We use `pc' rather than `unknown' # because (1) that's what they normally are, and # (2) the word "unknown" tends to confuse beginning users. i*86 | x86_64) basic_machine=$basic_machine-pc ;; # Object if more than one company name word. *-*-*) echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 exit 1 ;; # Recognize the basic CPU types with company name. 580-* \ | a29k-* \ | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \ | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ | avr-* | avr32-* \ | bfin-* | bs2000-* \ | c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \ | clipper-* | craynv-* | cydra-* \ | d10v-* | d30v-* | dlx-* \ | elxsi-* \ | f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \ | h8300-* | h8500-* \ | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ | i*86-* | i860-* | i960-* | ia64-* \ | ip2k-* | iq2000-* \ | lm32-* \ | m32c-* | m32r-* | m32rle-* \ | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ | m88110-* | m88k-* | maxq-* | mcore-* | metag-* \ | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ | mips16-* \ | mips64-* | mips64el-* \ | mips64octeon-* | mips64octeonel-* \ | mips64orion-* | mips64orionel-* \ | mips64r5900-* | mips64r5900el-* \ | mips64vr-* | mips64vrel-* \ | mips64vr4100-* | mips64vr4100el-* \ | mips64vr4300-* | mips64vr4300el-* \ | mips64vr5000-* | mips64vr5000el-* \ | mips64vr5900-* | mips64vr5900el-* \ | mipsisa32-* | mipsisa32el-* \ | mipsisa32r2-* | mipsisa32r2el-* \ | mipsisa64-* | mipsisa64el-* \ | mipsisa64r2-* | mipsisa64r2el-* \ | mipsisa64sb1-* | mipsisa64sb1el-* \ | mipsisa64sr71k-* | mipsisa64sr71kel-* \ | mipstx39-* | mipstx39el-* \ | mmix-* \ | mt-* \ | msp430-* \ | nios-* | nios2-* \ | none-* | np1-* | ns16k-* | ns32k-* \ | orion-* \ | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ | pyramid-* \ | romp-* | rs6000-* \ | sh-* | sh[1234]-* | sh[24]a-* | sh[24]aeb-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \ | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ | sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \ | sparclite-* \ | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | strongarm-* | sv1-* | sx?-* \ | tahoe-* | thumb-* \ | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* | tile-* \ | tron-* \ | v850-* | v850e-* | vax-* \ | we32k-* \ | x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \ | xstormy16-* | xtensa*-* \ | ymp-* \ | z8k-* | z80-*) ;; # Recognize the basic CPU types without company name, with glob match. xtensa*) basic_machine=$basic_machine-unknown ;; # Recognize the various machine names and aliases which stand # for a CPU type and a company and sometimes even an OS. 386bsd) basic_machine=i386-unknown os=-bsd ;; 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) basic_machine=m68000-att ;; 3b*) basic_machine=we32k-att ;; a29khif) basic_machine=a29k-amd os=-udi ;; abacus) basic_machine=abacus-unknown ;; adobe68k) basic_machine=m68010-adobe os=-scout ;; alliant | fx80) basic_machine=fx80-alliant ;; altos | altos3068) basic_machine=m68k-altos ;; am29k) basic_machine=a29k-none os=-bsd ;; amd64) basic_machine=x86_64-pc ;; amd64-*) basic_machine=x86_64-`echo $basic_machine | sed 's/^[^-]*-//'` ;; amdahl) basic_machine=580-amdahl os=-sysv ;; amiga | amiga-*) basic_machine=m68k-unknown ;; amigaos | amigados) basic_machine=m68k-unknown os=-amigaos ;; amigaunix | amix) basic_machine=m68k-unknown os=-sysv4 ;; apollo68) basic_machine=m68k-apollo os=-sysv ;; apollo68bsd) basic_machine=m68k-apollo os=-bsd ;; aros) basic_machine=i386-pc os=-aros ;; aux) basic_machine=m68k-apple os=-aux ;; balance) basic_machine=ns32k-sequent os=-dynix ;; blackfin) basic_machine=bfin-unknown os=-linux ;; blackfin-*) basic_machine=bfin-`echo $basic_machine | sed 's/^[^-]*-//'` os=-linux ;; c90) basic_machine=c90-cray os=-unicos ;; cegcc) basic_machine=arm-unknown os=-cegcc ;; convex-c1) basic_machine=c1-convex os=-bsd ;; convex-c2) basic_machine=c2-convex os=-bsd ;; convex-c32) basic_machine=c32-convex os=-bsd ;; convex-c34) basic_machine=c34-convex os=-bsd ;; convex-c38) basic_machine=c38-convex os=-bsd ;; cray | j90) basic_machine=j90-cray os=-unicos ;; craynv) basic_machine=craynv-cray os=-unicosmp ;; cr16) basic_machine=cr16-unknown os=-elf ;; crds | unos) basic_machine=m68k-crds ;; crisv32 | crisv32-* | etraxfs*) basic_machine=crisv32-axis ;; cris | cris-* | etrax*) basic_machine=cris-axis ;; crx) basic_machine=crx-unknown os=-elf ;; da30 | da30-*) basic_machine=m68k-da30 ;; decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) basic_machine=mips-dec ;; decsystem10* | dec10*) basic_machine=pdp10-dec os=-tops10 ;; decsystem20* | dec20*) basic_machine=pdp10-dec os=-tops20 ;; delta | 3300 | motorola-3300 | motorola-delta \ | 3300-motorola | delta-motorola) basic_machine=m68k-motorola ;; delta88) basic_machine=m88k-motorola os=-sysv3 ;; dicos) basic_machine=i686-pc os=-dicos ;; djgpp) basic_machine=i586-pc os=-msdosdjgpp ;; dpx20 | dpx20-*) basic_machine=rs6000-bull os=-bosx ;; dpx2* | dpx2*-bull) basic_machine=m68k-bull os=-sysv3 ;; ebmon29k) basic_machine=a29k-amd os=-ebmon ;; elxsi) basic_machine=elxsi-elxsi os=-bsd ;; encore | umax | mmax) basic_machine=ns32k-encore ;; es1800 | OSE68k | ose68k | ose | OSE) basic_machine=m68k-ericsson os=-ose ;; fx2800) basic_machine=i860-alliant ;; genix) basic_machine=ns32k-ns ;; gmicro) basic_machine=tron-gmicro os=-sysv ;; go32) basic_machine=i386-pc os=-go32 ;; h3050r* | hiux*) basic_machine=hppa1.1-hitachi os=-hiuxwe2 ;; h8300hms) basic_machine=h8300-hitachi os=-hms ;; h8300xray) basic_machine=h8300-hitachi os=-xray ;; h8500hms) basic_machine=h8500-hitachi os=-hms ;; harris) basic_machine=m88k-harris os=-sysv3 ;; hp300-*) basic_machine=m68k-hp ;; hp300bsd) basic_machine=m68k-hp os=-bsd ;; hp300hpux) basic_machine=m68k-hp os=-hpux ;; hp3k9[0-9][0-9] | hp9[0-9][0-9]) basic_machine=hppa1.0-hp ;; hp9k2[0-9][0-9] | hp9k31[0-9]) basic_machine=m68000-hp ;; hp9k3[2-9][0-9]) basic_machine=m68k-hp ;; hp9k6[0-9][0-9] | hp6[0-9][0-9]) basic_machine=hppa1.0-hp ;; hp9k7[0-79][0-9] | hp7[0-79][0-9]) basic_machine=hppa1.1-hp ;; hp9k78[0-9] | hp78[0-9]) # FIXME: really hppa2.0-hp basic_machine=hppa1.1-hp ;; hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893) # FIXME: really hppa2.0-hp basic_machine=hppa1.1-hp ;; hp9k8[0-9][13679] | hp8[0-9][13679]) basic_machine=hppa1.1-hp ;; hp9k8[0-9][0-9] | hp8[0-9][0-9]) basic_machine=hppa1.0-hp ;; hppa-next) os=-nextstep3 ;; hppaosf) basic_machine=hppa1.1-hp os=-osf ;; hppro) basic_machine=hppa1.1-hp os=-proelf ;; i370-ibm* | ibm*) basic_machine=i370-ibm ;; # I'm not sure what "Sysv32" means. Should this be sysv3.2? i*86v32) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv32 ;; i*86v4*) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv4 ;; i*86v) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv ;; i*86sol2) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-solaris2 ;; i386mach) basic_machine=i386-mach os=-mach ;; i386-vsta | vsta) basic_machine=i386-unknown os=-vsta ;; iris | iris4d) basic_machine=mips-sgi case $os in -irix*) ;; *) os=-irix4 ;; esac ;; isi68 | isi) basic_machine=m68k-isi os=-sysv ;; m68knommu) basic_machine=m68k-unknown os=-linux ;; m68knommu-*) basic_machine=m68k-`echo $basic_machine | sed 's/^[^-]*-//'` os=-linux ;; m88k-omron*) basic_machine=m88k-omron ;; magnum | m3230) basic_machine=mips-mips os=-sysv ;; merlin) basic_machine=ns32k-utek os=-sysv ;; mingw32) basic_machine=i386-pc os=-mingw32 ;; mingw32ce) basic_machine=arm-unknown os=-mingw32ce ;; miniframe) basic_machine=m68000-convergent ;; *mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*) basic_machine=m68k-atari os=-mint ;; mips3*-*) basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` ;; mips3*) basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown ;; monitor) basic_machine=m68k-rom68k os=-coff ;; morphos) basic_machine=powerpc-unknown os=-morphos ;; msdos) basic_machine=i386-pc os=-msdos ;; ms1-*) basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'` ;; mvs) basic_machine=i370-ibm os=-mvs ;; ncr3000) basic_machine=i486-ncr os=-sysv4 ;; netbsd386) basic_machine=i386-unknown os=-netbsd ;; netwinder) basic_machine=armv4l-rebel os=-linux ;; news | news700 | news800 | news900) basic_machine=m68k-sony os=-newsos ;; news1000) basic_machine=m68030-sony os=-newsos ;; news-3600 | risc-news) basic_machine=mips-sony os=-newsos ;; necv70) basic_machine=v70-nec os=-sysv ;; next | m*-next ) basic_machine=m68k-next case $os in -nextstep* ) ;; -ns2*) os=-nextstep2 ;; *) os=-nextstep3 ;; esac ;; nh3000) basic_machine=m68k-harris os=-cxux ;; nh[45]000) basic_machine=m88k-harris os=-cxux ;; nindy960) basic_machine=i960-intel os=-nindy ;; mon960) basic_machine=i960-intel os=-mon960 ;; nonstopux) basic_machine=mips-compaq os=-nonstopux ;; np1) basic_machine=np1-gould ;; nsr-tandem) basic_machine=nsr-tandem ;; op50n-* | op60c-*) basic_machine=hppa1.1-oki os=-proelf ;; openrisc | openrisc-*) basic_machine=or32-unknown ;; os400) basic_machine=powerpc-ibm os=-os400 ;; OSE68000 | ose68000) basic_machine=m68000-ericsson os=-ose ;; os68k) basic_machine=m68k-none os=-os68k ;; pa-hitachi) basic_machine=hppa1.1-hitachi os=-hiuxwe2 ;; paragon) basic_machine=i860-intel os=-osf ;; parisc) basic_machine=hppa-unknown os=-linux ;; parisc-*) basic_machine=hppa-`echo $basic_machine | sed 's/^[^-]*-//'` os=-linux ;; pbd) basic_machine=sparc-tti ;; pbb) basic_machine=m68k-tti ;; pc532 | pc532-*) basic_machine=ns32k-pc532 ;; pc98) basic_machine=i386-pc ;; pc98-*) basic_machine=i386-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentium | p5 | k5 | k6 | nexgen | viac3) basic_machine=i586-pc ;; pentiumpro | p6 | 6x86 | athlon | athlon_*) basic_machine=i686-pc ;; pentiumii | pentium2 | pentiumiii | pentium3) basic_machine=i686-pc ;; pentium4) basic_machine=i786-pc ;; pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*) basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentiumpro-* | p6-* | 6x86-* | athlon-*) basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentiumii-* | pentium2-* | pentiumiii-* | pentium3-*) basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentium4-*) basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pn) basic_machine=pn-gould ;; power) basic_machine=power-ibm ;; ppc) basic_machine=powerpc-unknown ;; ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppcle | powerpclittle | ppc-le | powerpc-little) basic_machine=powerpcle-unknown ;; ppcle-* | powerpclittle-*) basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppc64) basic_machine=powerpc64-unknown ;; ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppc64le | powerpc64little | ppc64-le | powerpc64-little) basic_machine=powerpc64le-unknown ;; ppc64le-* | powerpc64little-*) basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ps2) basic_machine=i386-ibm ;; pw32) basic_machine=i586-unknown os=-pw32 ;; rdos) basic_machine=i386-pc os=-rdos ;; rom68k) basic_machine=m68k-rom68k os=-coff ;; rm[46]00) basic_machine=mips-siemens ;; rtpc | rtpc-*) basic_machine=romp-ibm ;; s390 | s390-*) basic_machine=s390-ibm ;; s390x | s390x-*) basic_machine=s390x-ibm ;; sa29200) basic_machine=a29k-amd os=-udi ;; sb1) basic_machine=mipsisa64sb1-unknown ;; sb1el) basic_machine=mipsisa64sb1el-unknown ;; sde) basic_machine=mipsisa32-sde os=-elf ;; sei) basic_machine=mips-sei os=-seiux ;; sequent) basic_machine=i386-sequent ;; sh) basic_machine=sh-hitachi os=-hms ;; sh5el) basic_machine=sh5le-unknown ;; sh64) basic_machine=sh64-unknown ;; sparclite-wrs | simso-wrs) basic_machine=sparclite-wrs os=-vxworks ;; sps7) basic_machine=m68k-bull os=-sysv2 ;; spur) basic_machine=spur-unknown ;; st2000) basic_machine=m68k-tandem ;; stratus) basic_machine=i860-stratus os=-sysv4 ;; sun2) basic_machine=m68000-sun ;; sun2os3) basic_machine=m68000-sun os=-sunos3 ;; sun2os4) basic_machine=m68000-sun os=-sunos4 ;; sun3os3) basic_machine=m68k-sun os=-sunos3 ;; sun3os4) basic_machine=m68k-sun os=-sunos4 ;; sun4os3) basic_machine=sparc-sun os=-sunos3 ;; sun4os4) basic_machine=sparc-sun os=-sunos4 ;; sun4sol2) basic_machine=sparc-sun os=-solaris2 ;; sun3 | sun3-*) basic_machine=m68k-sun ;; sun4) basic_machine=sparc-sun ;; sun386 | sun386i | roadrunner) basic_machine=i386-sun ;; sv1) basic_machine=sv1-cray os=-unicos ;; symmetry) basic_machine=i386-sequent os=-dynix ;; t3e) basic_machine=alphaev5-cray os=-unicos ;; t90) basic_machine=t90-cray os=-unicos ;; tic54x | c54x*) basic_machine=tic54x-unknown os=-coff ;; tic55x | c55x*) basic_machine=tic55x-unknown os=-coff ;; tic6x | c6x*) basic_machine=tic6x-unknown os=-coff ;; tile*) basic_machine=tile-unknown os=-linux-gnu ;; tx39) basic_machine=mipstx39-unknown ;; tx39el) basic_machine=mipstx39el-unknown ;; toad1) basic_machine=pdp10-xkl os=-tops20 ;; tower | tower-32) basic_machine=m68k-ncr ;; tpf) basic_machine=s390x-ibm os=-tpf ;; udi29k) basic_machine=a29k-amd os=-udi ;; ultra3) basic_machine=a29k-nyu os=-sym1 ;; v810 | necv810) basic_machine=v810-nec os=-none ;; vaxv) basic_machine=vax-dec os=-sysv ;; vms) basic_machine=vax-dec os=-vms ;; vpp*|vx|vx-*) basic_machine=f301-fujitsu ;; vxworks960) basic_machine=i960-wrs os=-vxworks ;; vxworks68) basic_machine=m68k-wrs os=-vxworks ;; vxworks29k) basic_machine=a29k-wrs os=-vxworks ;; w65*) basic_machine=w65-wdc os=-none ;; w89k-*) basic_machine=hppa1.1-winbond os=-proelf ;; xbox) basic_machine=i686-pc os=-mingw32 ;; xps | xps100) basic_machine=xps100-honeywell ;; ymp) basic_machine=ymp-cray os=-unicos ;; z8k-*-coff) basic_machine=z8k-unknown os=-sim ;; z80-*-coff) basic_machine=z80-unknown os=-sim ;; none) basic_machine=none-none os=-none ;; # Here we handle the default manufacturer of certain CPU types. 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They are # bogus both because they are the default anyway, and because # using them would break gcc on systems where it needs fixed includes. case $ac_im_incroot in /usr/include) ac_x_includes= ;; *) test -f "$ac_im_incroot/X11/Xos.h" && ac_x_includes=$ac_im_incroot;; esac case $ac_im_usrlibdir in /usr/lib | /usr/lib64 | /lib | /lib64) ;; *) test -d "$ac_im_usrlibdir" && ac_x_libraries=$ac_im_usrlibdir ;; esac fi cd .. rm -f -r conftest.dir fi # Standard set of common directories for X headers. # Check X11 before X11Rn because it is often a symlink to the current release. ac_x_header_dirs=' /usr/X11/include /usr/X11R7/include /usr/X11R6/include /usr/X11R5/include /usr/X11R4/include /usr/include/X11 /usr/include/X11R7 /usr/include/X11R6 /usr/include/X11R5 /usr/include/X11R4 /usr/local/X11/include /usr/local/X11R7/include /usr/local/X11R6/include /usr/local/X11R5/include /usr/local/X11R4/include /usr/local/include/X11 /usr/local/include/X11R7 /usr/local/include/X11R6 /usr/local/include/X11R5 /usr/local/include/X11R4 /usr/X386/include /usr/x386/include /usr/XFree86/include/X11 /usr/include /usr/local/include /usr/unsupported/include /usr/athena/include /usr/local/x11r5/include /usr/lpp/Xamples/include /usr/openwin/include /usr/openwin/share/include' if test "$ac_x_includes" = no; then # Guess where to find include files, by looking for Xlib.h. # First, try using that file with no special directory specified. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include _ACEOF if ac_fn_c_try_cpp "$LINENO"; then : # We can compile using X headers with no special include directory. ac_x_includes= else for ac_dir in $ac_x_header_dirs; do if test -r "$ac_dir/X11/Xlib.h"; then ac_x_includes=$ac_dir break fi done fi rm -f conftest.err conftest.$ac_ext fi # $ac_x_includes = no if test "$ac_x_libraries" = no; then # Check for the libraries. # See if we find them without any special options. # Don't add to $LIBS permanently. ac_save_LIBS=$LIBS LIBS="-lX11 $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include int main () { XrmInitialize () ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : LIBS=$ac_save_LIBS # We can link X programs with no special library path. ac_x_libraries= else LIBS=$ac_save_LIBS for ac_dir in `$as_echo "$ac_x_includes $ac_x_header_dirs" | sed s/include/lib/g` do # Don't even attempt the hair of trying to link an X program! for ac_extension in a so sl dylib la dll; do if test -r "$ac_dir/libX11.$ac_extension"; then ac_x_libraries=$ac_dir break 2 fi done done fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext fi # $ac_x_libraries = no case $ac_x_includes,$ac_x_libraries in #( no,* | *,no | *\'*) # Didn't find X, or a directory has "'" in its name. ac_cv_have_x="have_x=no";; #( *) # Record where we found X for the cache. ac_cv_have_x="have_x=yes\ ac_x_includes='$ac_x_includes'\ ac_x_libraries='$ac_x_libraries'" esac fi ;; #( *) have_x=yes;; esac eval "$ac_cv_have_x" fi # $with_x != no if test "$have_x" != yes; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $have_x" >&5 $as_echo "$have_x" >&6; } no_x=yes else # If each of the values was on the command line, it overrides each guess. test "x$x_includes" = xNONE && x_includes=$ac_x_includes test "x$x_libraries" = xNONE && x_libraries=$ac_x_libraries # Update the cache value to reflect the command line values. ac_cv_have_x="have_x=yes\ ac_x_includes='$x_includes'\ ac_x_libraries='$x_libraries'" { $as_echo "$as_me:${as_lineno-$LINENO}: result: libraries $x_libraries, headers $x_includes" >&5 $as_echo "libraries $x_libraries, headers $x_includes" >&6; } fi if test "$no_x" = yes; then # Not all programs may use this symbol, but it does not hurt to define it. $as_echo "#define X_DISPLAY_MISSING 1" >>confdefs.h X_CFLAGS= X_PRE_LIBS= X_LIBS= X_EXTRA_LIBS= else if test -n "$x_includes"; then X_CFLAGS="$X_CFLAGS -I$x_includes" fi # It would also be nice to do this for all -L options, not just this one. if test -n "$x_libraries"; then X_LIBS="$X_LIBS -L$x_libraries" # For Solaris; some versions of Sun CC require a space after -R and # others require no space. Words are not sufficient . . . . { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether -R must be followed by a space" >&5 $as_echo_n "checking whether -R must be followed by a space... " >&6; } ac_xsave_LIBS=$LIBS; LIBS="$LIBS -R$x_libraries" ac_xsave_c_werror_flag=$ac_c_werror_flag ac_c_werror_flag=yes cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } X_LIBS="$X_LIBS -R$x_libraries" else LIBS="$ac_xsave_LIBS -R $x_libraries" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } X_LIBS="$X_LIBS -R $x_libraries" else { $as_echo "$as_me:${as_lineno-$LINENO}: result: neither works" >&5 $as_echo "neither works" >&6; } fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext ac_c_werror_flag=$ac_xsave_c_werror_flag LIBS=$ac_xsave_LIBS fi # Check for system-dependent libraries X programs must link with. # Do this before checking for the system-independent R6 libraries # (-lICE), since we may need -lsocket or whatever for X linking. if test "$ISC" = yes; then X_EXTRA_LIBS="$X_EXTRA_LIBS -lnsl_s -linet" else # Martyn Johnson says this is needed for Ultrix, if the X # libraries were built with DECnet support. And Karl Berry says # the Alpha needs dnet_stub (dnet does not exist). ac_xsave_LIBS="$LIBS"; LIBS="$LIBS $X_LIBS -lX11" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char XOpenDisplay (); int main () { return XOpenDisplay (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : else { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dnet_ntoa in -ldnet" >&5 $as_echo_n "checking for dnet_ntoa in -ldnet... " >&6; } if test "${ac_cv_lib_dnet_dnet_ntoa+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldnet $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dnet_ntoa (); int main () { return dnet_ntoa (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_dnet_dnet_ntoa=yes else ac_cv_lib_dnet_dnet_ntoa=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dnet_dnet_ntoa" >&5 $as_echo "$ac_cv_lib_dnet_dnet_ntoa" >&6; } if test "x$ac_cv_lib_dnet_dnet_ntoa" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -ldnet" fi if test $ac_cv_lib_dnet_dnet_ntoa = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dnet_ntoa in -ldnet_stub" >&5 $as_echo_n "checking for dnet_ntoa in -ldnet_stub... " >&6; } if test "${ac_cv_lib_dnet_stub_dnet_ntoa+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldnet_stub $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dnet_ntoa (); int main () { return dnet_ntoa (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_dnet_stub_dnet_ntoa=yes else ac_cv_lib_dnet_stub_dnet_ntoa=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dnet_stub_dnet_ntoa" >&5 $as_echo "$ac_cv_lib_dnet_stub_dnet_ntoa" >&6; } if test "x$ac_cv_lib_dnet_stub_dnet_ntoa" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -ldnet_stub" fi fi fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS="$ac_xsave_LIBS" # msh@cis.ufl.edu says -lnsl (and -lsocket) are needed for his 386/AT, # to get the SysV transport functions. # Chad R. Larson says the Pyramis MIS-ES running DC/OSx (SVR4) # needs -lnsl. # The nsl library prevents programs from opening the X display # on Irix 5.2, according to T.E. Dickey. # The functions gethostbyname, getservbyname, and inet_addr are # in -lbsd on LynxOS 3.0.1/i386, according to Lars Hecking. ac_fn_c_check_func "$LINENO" "gethostbyname" "ac_cv_func_gethostbyname" if test "x$ac_cv_func_gethostbyname" = x""yes; then : fi if test $ac_cv_func_gethostbyname = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for gethostbyname in -lnsl" >&5 $as_echo_n "checking for gethostbyname in -lnsl... " >&6; } if test "${ac_cv_lib_nsl_gethostbyname+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lnsl $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char gethostbyname (); int main () { return gethostbyname (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_nsl_gethostbyname=yes else ac_cv_lib_nsl_gethostbyname=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_nsl_gethostbyname" >&5 $as_echo "$ac_cv_lib_nsl_gethostbyname" >&6; } if test "x$ac_cv_lib_nsl_gethostbyname" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -lnsl" fi if test $ac_cv_lib_nsl_gethostbyname = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for gethostbyname in -lbsd" >&5 $as_echo_n "checking for gethostbyname in -lbsd... " >&6; } if test "${ac_cv_lib_bsd_gethostbyname+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lbsd $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char gethostbyname (); int main () { return gethostbyname (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_bsd_gethostbyname=yes else ac_cv_lib_bsd_gethostbyname=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_bsd_gethostbyname" >&5 $as_echo "$ac_cv_lib_bsd_gethostbyname" >&6; } if test "x$ac_cv_lib_bsd_gethostbyname" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -lbsd" fi fi fi # lieder@skyler.mavd.honeywell.com says without -lsocket, # socket/setsockopt and other routines are undefined under SCO ODT # 2.0. But -lsocket is broken on IRIX 5.2 (and is not necessary # on later versions), says Simon Leinen: it contains gethostby* # variants that don't use the name server (or something). -lsocket # must be given before -lnsl if both are needed. We assume that # if connect needs -lnsl, so does gethostbyname. ac_fn_c_check_func "$LINENO" "connect" "ac_cv_func_connect" if test "x$ac_cv_func_connect" = x""yes; then : fi if test $ac_cv_func_connect = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for connect in -lsocket" >&5 $as_echo_n "checking for connect in -lsocket... " >&6; } if test "${ac_cv_lib_socket_connect+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lsocket $X_EXTRA_LIBS $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char connect (); int main () { return connect (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_socket_connect=yes else ac_cv_lib_socket_connect=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_socket_connect" >&5 $as_echo "$ac_cv_lib_socket_connect" >&6; } if test "x$ac_cv_lib_socket_connect" = x""yes; then : X_EXTRA_LIBS="-lsocket $X_EXTRA_LIBS" fi fi # Guillermo Gomez says -lposix is necessary on A/UX. ac_fn_c_check_func "$LINENO" "remove" "ac_cv_func_remove" if test "x$ac_cv_func_remove" = x""yes; then : fi if test $ac_cv_func_remove = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for remove in -lposix" >&5 $as_echo_n "checking for remove in -lposix... " >&6; } if test "${ac_cv_lib_posix_remove+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lposix $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char remove (); int main () { return remove (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_posix_remove=yes else ac_cv_lib_posix_remove=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_posix_remove" >&5 $as_echo "$ac_cv_lib_posix_remove" >&6; } if test "x$ac_cv_lib_posix_remove" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -lposix" fi fi # BSDI BSD/OS 2.1 needs -lipc for XOpenDisplay. ac_fn_c_check_func "$LINENO" "shmat" "ac_cv_func_shmat" if test "x$ac_cv_func_shmat" = x""yes; then : fi if test $ac_cv_func_shmat = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for shmat in -lipc" >&5 $as_echo_n "checking for shmat in -lipc... " >&6; } if test "${ac_cv_lib_ipc_shmat+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lipc $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char shmat (); int main () { return shmat (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_ipc_shmat=yes else ac_cv_lib_ipc_shmat=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_ipc_shmat" >&5 $as_echo "$ac_cv_lib_ipc_shmat" >&6; } if test "x$ac_cv_lib_ipc_shmat" = x""yes; then : X_EXTRA_LIBS="$X_EXTRA_LIBS -lipc" fi fi fi # Check for libraries that X11R6 Xt/Xaw programs need. ac_save_LDFLAGS=$LDFLAGS test -n "$x_libraries" && LDFLAGS="$LDFLAGS -L$x_libraries" # SM needs ICE to (dynamically) link under SunOS 4.x (so we have to # check for ICE first), but we must link in the order -lSM -lICE or # we get undefined symbols. So assume we have SM if we have ICE. # These have to be linked with before -lX11, unlike the other # libraries we check for below, so use a different variable. # John Interrante, Karl Berry { $as_echo "$as_me:${as_lineno-$LINENO}: checking for IceConnectionNumber in -lICE" >&5 $as_echo_n "checking for IceConnectionNumber in -lICE... " >&6; } if test "${ac_cv_lib_ICE_IceConnectionNumber+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lICE $X_EXTRA_LIBS $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char IceConnectionNumber (); int main () { return IceConnectionNumber (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_ICE_IceConnectionNumber=yes else ac_cv_lib_ICE_IceConnectionNumber=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_ICE_IceConnectionNumber" >&5 $as_echo "$ac_cv_lib_ICE_IceConnectionNumber" >&6; } if test "x$ac_cv_lib_ICE_IceConnectionNumber" = x""yes; then : X_PRE_LIBS="$X_PRE_LIBS -lSM -lICE" fi LDFLAGS=$ac_save_LDFLAGS fi if test "${want_tcltk}" = yes; then have_tcltk=yes ## (Note that the subsequent 3 macros assume that have_tcltk has been ## set appropriately.) for ac_prog in ${TCL_CONFIG} tclConfig.sh do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if test "${ac_cv_path_TCL_CONFIG+set}" = set; then : $as_echo_n "(cached) " >&6 else case $TCL_CONFIG in [\\/]* | ?:[\\/]*) ac_cv_path_TCL_CONFIG="$TCL_CONFIG" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_path_TCL_CONFIG="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi TCL_CONFIG=$ac_cv_path_TCL_CONFIG if test -n "$TCL_CONFIG"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $TCL_CONFIG" >&5 $as_echo "$TCL_CONFIG" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi test -n "$TCL_CONFIG" && break done if test -z "${TCL_CONFIG}"; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tclConfig.sh in library (sub)directories" >&5 $as_echo_n "checking for tclConfig.sh in library (sub)directories... " >&6; } if test "${r_cv_path_TCL_CONFIG+set}" = set; then : $as_echo_n "(cached) " >&6 else for ldir in /opt/lib /sw/lib /usr/local/lib /usr/lib /lib /usr/lib64 ; do for dir in \ ${ldir} \ `ls -d ${ldir}/tcl[8-9].[0-9]* 2>/dev/null | sort -r`; do if test -f ${dir}/tclConfig.sh; then r_cv_path_TCL_CONFIG="${dir}/tclConfig.sh" break 2 fi done done fi if test -n "${r_cv_path_TCL_CONFIG}"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: ${r_cv_path_TCL_CONFIG}" >&5 $as_echo "${r_cv_path_TCL_CONFIG}" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test -n "${r_cv_path_TCL_CONFIG}"; then TCL_CONFIG="${r_cv_path_TCL_CONFIG}" fi fi for ac_prog in ${TK_CONFIG} tkConfig.sh do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if test "${ac_cv_path_TK_CONFIG+set}" = set; then : $as_echo_n "(cached) " >&6 else case $TK_CONFIG in [\\/]* | ?:[\\/]*) ac_cv_path_TK_CONFIG="$TK_CONFIG" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_path_TK_CONFIG="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi TK_CONFIG=$ac_cv_path_TK_CONFIG if test -n "$TK_CONFIG"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $TK_CONFIG" >&5 $as_echo "$TK_CONFIG" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi test -n "$TK_CONFIG" && break done if test -z "${TK_CONFIG}"; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tkConfig.sh in library (sub)directories" >&5 $as_echo_n "checking for tkConfig.sh in library (sub)directories... " >&6; } if test "${r_cv_path_TK_CONFIG+set}" = set; then : $as_echo_n "(cached) " >&6 else for ldir in /opt/lib /sw/lib /usr/local/lib /usr/lib /lib /usr/lib64 ; do for dir in \ ${ldir} \ `ls -d ${ldir}/tk[8-9].[0-9]* 2>/dev/null | sort -r`; do if test -f ${dir}/tkConfig.sh; then r_cv_path_TK_CONFIG="${dir}/tkConfig.sh" break 2 fi done done fi if test -n "${r_cv_path_TK_CONFIG}"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: ${r_cv_path_TK_CONFIG}" >&5 $as_echo "${r_cv_path_TK_CONFIG}" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test -n "${r_cv_path_TK_CONFIG}"; then TK_CONFIG="${r_cv_path_TK_CONFIG}" fi fi if test -z "${TCLTK_CPPFLAGS}" \ || test -z "${TCLTK_LIBS}"; then ## Check whether the versions found via the *Config.sh files are at ## least 8; otherwise, issue a warning and turn off Tcl/Tk support. ## Note that in theory a system could have outdated versions of the ## *Config.sh scripts and yet up-to-date installations of Tcl/Tk in ## standard places ... if test -n "${TCL_CONFIG}"; then . ${TCL_CONFIG} if test ${TCL_MAJOR_VERSION} -lt 8; then warn_tcltk_version="Tcl/Tk support requires Tcl version >= 8" { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: ${warn_tcltk_version}" >&5 $as_echo "$as_me: WARNING: ${warn_tcltk_version}" >&2;} have_tcltk=no fi fi if test -n "${TK_CONFIG}" \ && test -z "${warn_tcltk_version}"; then . ${TK_CONFIG} if test ${TK_MAJOR_VERSION} -lt 8; then warn_tcltk_version="Tcl/Tk support requires Tk version >= 8" { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: ${warn_tcltk_version}" >&5 $as_echo "$as_me: WARNING: ${warn_tcltk_version}" >&2;} have_tcltk=no fi fi if test -n "${TCL_CONFIG}" \ && test -n "${TK_CONFIG}" \ && test -z "${warn_tcltk_version}"; then if test ${TCL_MAJOR_VERSION} -ne ${TK_MAJOR_VERSION} \ || test ${TCL_MINOR_VERSION} -ne ${TK_MINOR_VERSION}; then warn_tcltk_version="Tcl and Tk major or minor versions disagree" { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: ${warn_tcltk_version}" >&5 $as_echo "$as_me: WARNING: ${warn_tcltk_version}" >&2;} have_tcltk=no fi fi fi if test -z "${TCLTK_CPPFLAGS}"; then ## We have to do the work. if test "${have_tcltk}" = yes; then ## Part 1. Check for tcl.h. found_tcl_h=no if test -n "${TCL_CONFIG}"; then . ${TCL_CONFIG} ## Look for tcl.h in ## ${TCL_PREFIX}/include/tcl${TCL_VERSION} ## ${TCL_PREFIX}/include ## Also look in ## ${TCL_PREFIX}/include/tcl${TCL_VERSION}/generic ## to deal with current FreeBSD layouts. These also link the real ## thing to the version subdir, but the link cannot be used as it ## fails to include 'tclDecls.h' which is not linked. Hence we ## must look for the real thing first. Argh ... for dir in \ ${TCL_PREFIX}/include/tcl${TCL_VERSION}/generic \ ${TCL_PREFIX}/include/tcl${TCL_VERSION} \ ${TCL_PREFIX}/include; do as_ac_Header=`$as_echo "ac_cv_header_${dir}/tcl.h" | $as_tr_sh` ac_fn_c_check_header_mongrel "$LINENO" "${dir}/tcl.h" "$as_ac_Header" "$ac_includes_default" eval as_val=\$$as_ac_Header if test "x$as_val" = x""yes; then : TCLTK_CPPFLAGS="-I${dir}" found_tcl_h=yes break fi done fi if test "${found_tcl_h}" = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tcl.h" >&5 $as_echo_n "checking for tcl.h... " >&6; } if test "${r_cv_header_tcl_h+set}" = set; then : $as_echo_n "(cached) " >&6 else cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include #if (TCL_MAJOR_VERSION >= 8) yes #endif _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "yes" >/dev/null 2>&1; then : r_cv_header_tcl_h=yes else r_cv_header_tcl_h=no fi rm -f conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $r_cv_header_tcl_h" >&5 $as_echo "$r_cv_header_tcl_h" >&6; } if test "${r_cv_header_tcl_h}" = yes; then found_tcl_h=yes else have_tcltk=no fi fi fi if test "${have_tcltk}" = yes; then ## Part 2. Check for tk.h. found_tk_h=no if test -n "${TK_CONFIG}"; then . ${TK_CONFIG} ## Look for tk.h in ## ${TK_PREFIX}/include/tk${TK_VERSION} ## ${TK_PREFIX}/include ## Also look in ## ${TK_PREFIX}/include/tcl${TK_VERSION} ## to compensate for Debian madness ... ## Also look in ## ${TK_PREFIX}/include/tk${TK_VERSION}/generic ## to deal with current FreeBSD layouts. See above for details. ## ## As the AC_CHECK_HEADER test tries including the header file and ## tk.h includes tcl.h and X11/Xlib.h, we need to change CPPFLAGS ## for the check. r_save_CPPFLAGS="${CPPFLAGS}" CPPFLAGS="${CPPFLAGS} ${TK_XINCLUDES} ${TCLTK_CPPFLAGS}" for dir in \ ${TK_PREFIX}/include/tk${TK_VERSION}/generic \ ${TK_PREFIX}/include/tk${TK_VERSION} \ ${TK_PREFIX}/include/tcl${TK_VERSION} \ ${TK_PREFIX}/include; do as_ac_Header=`$as_echo "ac_cv_header_${dir}/tk.h" | $as_tr_sh` ac_fn_c_check_header_mongrel "$LINENO" "${dir}/tk.h" "$as_ac_Header" "$ac_includes_default" eval as_val=\$$as_ac_Header if test "x$as_val" = x""yes; then : TCLTK_CPPFLAGS="${TCLTK_CPPFLAGS} -I${dir}" found_tk_h=yes break fi done CPPFLAGS="${r_save_CPPFLAGS}" fi if test "${found_tk_h}" = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for tk.h" >&5 $as_echo_n "checking for tk.h... " >&6; } if test "${r_cv_header_tk_h+set}" = set; then : $as_echo_n "(cached) " >&6 else cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include #if (TK_MAJOR_VERSION >= 8) yes #endif _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "yes" >/dev/null 2>&1; then : r_cv_header_tk_h=yes else r_cv_header_tk_h=no fi rm -f conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $r_cv_header_tk_h" >&5 $as_echo "$r_cv_header_tk_h" >&6; } if test "{r_cv_header_tk_h}" = yes; then found_tk_h=yes else have_tcltk=no fi fi fi fi if test "${have_tcltk}" = yes; then if test -n "${TK_XINCLUDES}"; then TCLTK_CPPFLAGS="${TCLTK_CPPFLAGS} ${TK_XINCLUDES}" else TCLTK_CPPFLAGS="${TCLTK_CPPFLAGS} ${X_CFLAGS}" fi fi if test -z "${TCLTK_LIBS}"; then ## We have to do the work. if test "${have_tcltk}" = yes; then ## Part 1. Try finding the tcl library. if test -n "${TCL_CONFIG}"; then . ${TCL_CONFIG} TCLTK_LIBS="${TCL_LIB_SPEC}" else { $as_echo "$as_me:${as_lineno-$LINENO}: checking for Tcl_CreateInterp in -ltcl" >&5 $as_echo_n "checking for Tcl_CreateInterp in -ltcl... " >&6; } if test "${ac_cv_lib_tcl_Tcl_CreateInterp+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ltcl $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char Tcl_CreateInterp (); int main () { return Tcl_CreateInterp (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_tcl_Tcl_CreateInterp=yes else ac_cv_lib_tcl_Tcl_CreateInterp=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_tcl_Tcl_CreateInterp" >&5 $as_echo "$ac_cv_lib_tcl_Tcl_CreateInterp" >&6; } if test "x$ac_cv_lib_tcl_Tcl_CreateInterp" = x""yes; then : TCLTK_LIBS=-ltcl else have_tcltk=no fi fi fi if test "${have_tcltk}" = yes; then ## Part 2. Try finding the tk library. if test -n "${TK_CONFIG}"; then . ${TK_CONFIG} TCLTK_LIBS="${TCLTK_LIBS} ${TK_LIB_SPEC} ${TK_LIBS}" else { $as_echo "$as_me:${as_lineno-$LINENO}: checking for Tk_Init in -ltk" >&5 $as_echo_n "checking for Tk_Init in -ltk... " >&6; } if test "${ac_cv_lib_tk_Tk_Init+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ltk ${TCLTK_LIBS} $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char Tk_Init (); int main () { return Tk_Init (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_tk_Tk_Init=yes else ac_cv_lib_tk_Tk_Init=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_tk_Tk_Init" >&5 $as_echo "$ac_cv_lib_tk_Tk_Init" >&6; } if test "x$ac_cv_lib_tk_Tk_Init" = x""yes; then : cat >>confdefs.h <<_ACEOF #define HAVE_LIBTK 1 _ACEOF LIBS="-ltk $LIBS" fi if test "${ac_cv_lib_tk_Tk_Init}" = no; then ## Grr, simple -ltk does not work. ## But maybe we simply need to add X11 libs. ## Note that we cannot simply repeat the above test with extra ## libs, because AC_CHECK_LIB uses the corresponding cache var ## (ac_cv_lib_tk_Tk_Init in our case) if set. As using unset ## is not portable shell programming according to the Autoconf ## docs, we use Tk_SafeInit in the test with X11 libs added. { $as_echo "$as_me:${as_lineno-$LINENO}: checking for Tk_SafeInit in -ltk" >&5 $as_echo_n "checking for Tk_SafeInit in -ltk... " >&6; } if test "${ac_cv_lib_tk_Tk_SafeInit+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ltk ${TCLTK_LIBS} ${X_LIBS} $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char Tk_SafeInit (); int main () { return Tk_SafeInit (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_tk_Tk_SafeInit=yes else ac_cv_lib_tk_Tk_SafeInit=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_tk_Tk_SafeInit" >&5 $as_echo "$ac_cv_lib_tk_Tk_SafeInit" >&6; } if test "x$ac_cv_lib_tk_Tk_SafeInit" = x""yes; then : TCLTK_LIBS="${TCLTK_LIBS} -ltk ${X_LIBS}" else have_tcltk=no fi fi fi fi ## Postprocessing for AIX. ## On AIX, the *_LIB_SPEC variables need to contain '-bI:' flags for ## the Tcl export file. These are really flags for ld rather than the ## C/C++ compilers, and hence may need protection via '-Wl,'. ## We have two ways of doing that: ## * Recording whether '-Wl,' is needed for the C or C++ compilers, ## and getting this info into the TCLTK_LIBS make variable ... mess! ## * Protecting all entries in TCLTK_LIBS that do not start with '-l' ## or '-L' with '-Wl,' (hoping that all compilers understand this). ## Easy, hence ... case "${host_os}" in aix*) orig_TCLTK_LIBS="${TCLTK_LIBS}" TCLTK_LIBS= for flag in ${orig_TCLTK_LIBS}; do case "${flag}" in -l*|-L*|-Wl,*) ;; *) flag="-Wl,${flag}" ;; esac TCLTK_LIBS="${TCLTK_LIBS} ${flag}" done ;; esac ## Force evaluation ('-ltcl8.3${TCL_DBGX}' and friends ...). eval "TCLTK_LIBS=\"${TCLTK_LIBS}\"" fi if test "${have_tcltk}" = yes; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether compiling/linking Tcl/Tk code works" >&5 $as_echo_n "checking whether compiling/linking Tcl/Tk code works... " >&6; } if test "${r_cv_tcltk_works+set}" = set; then : $as_echo_n "(cached) " >&6 else ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu r_save_CPPFLAGS="${CPPFLAGS}" r_save_LIBS="${LIBS}" CPPFLAGS="${CPPFLAGS} ${TCLTK_CPPFLAGS}" LIBS="${LIBS} ${TCLTK_LIBS}" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include #include int main () { static char * p1 = (char *) Tcl_Init; static char * p2 = (char *) Tk_Init; ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : r_cv_tcltk_works=yes else r_cv_tcltk_works=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext CPPFLAGS="${r_save_CPPFLAGS}" LIBS="${r_save_LIBS}" ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $r_cv_tcltk_works" >&5 $as_echo "$r_cv_tcltk_works" >&6; } have_tcltk=${r_cv_tcltk_works} fi else have_tcltk=no ## Just making sure. TCLTK_CPPFLAGS= TCLTK_LIBS= fi if test "${have_tcltk}" = yes; then $as_echo "#define HAVE_TCLTK 1" >>confdefs.h use_tcltk=yes else use_tcltk=no fi ## Check for browser for help pages if test -z "${COVERED_BROWSER}"; then for ac_prog in firefox safari netscape mozilla galeon kfmclient opera gnome-moz-remote open do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... 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then warn_browser="I could not determine a browser" { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: ${warn_browser}" >&5 $as_echo "$as_me: WARNING: ${warn_browser}" >&2;} else { $as_echo "$as_me:${as_lineno-$LINENO}: result: using default browser ... ${COVERED_BROWSER}" >&5 $as_echo "using default browser ... ${COVERED_BROWSER}" >&6; } fi cat >>confdefs.h <<_ACEOF #define COVERED_BROWSER "$COVERED_BROWSER" _ACEOF # Check whether --enable-debug was given. if test "${enable_debug+set}" = set; then : enableval=$enable_debug; DEBUGDEF="-DDEBUG_MODE" fi # Check whether --enable-profiling was given. if test "${enable_profiling+set}" = set; then : enableval=$enable_profiling; PROFILEDEF="-DPROFILER" fi # Check whether --enable-test was given. if test "${enable_test+set}" = set; then : enableval=$enable_test; TESTMODEDEF="-DTESTMODE" fi ## Simulators supported # Check whether --with-iv was given. if test "${with_iv+set}" = set; then : withval=$with_iv; if test "${withval}" = no; then want_iv=no elif test "${withval}" = yes; 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AC_INIT(src/main.c) AM_CONFIG_HEADER(config.h) AM_INIT_AUTOMAKE(covered,covered-0.7.10) dnl Get host information AC_CANONICAL_HOST case $host_os in *cygwin* ) build_cygwin=yes;; * ) build_cygwin=no;; esac AM_CONDITIONAL([BUILD_CYGWIN], [test x$build_cygwin = xyes]) dnl Checks for programs. AC_PROG_MAKE_SET AC_PROG_CC dnl AC_ARG_PROGRAM AC_PROG_INSTALL AC_PROG_MAKE_SET AC_PROG_RANLIB AC_PROG_YACC AC_PROG_LEX AC_SYS_LARGEFILE AC_C_BIGENDIAN AC_CHECK_PROGS(XGPERF,gperf,none) if test "$XGPERF" = "none" then echo "*** Error: No suitable gperf found. ***" echo " Please install the 'gperf' package." exit 1 fi dnl Libraries AC_CHECK_LIB(z,gzdopen) ## Tcl/Tk. AC_ARG_WITH([tcltk], [AC_HELP_STRING([--with-tcltk], [use Tcl/Tk, or specify its library dir @<:@yes@:>@])], [if test "${withval}" = no; then want_tcltk=no elif test "${withval}" = yes; then want_tcltk=yes else want_tcltk=yes LDFLAGS="${LDFLAGS} -L${withval}" tcltk_prefix="${withval}" fi], [want_tcltk=yes]) AC_ARG_WITH([tcl-config], [AC_HELP_STRING([--with-tcl-config=TCL_CONFIG], [specify location of tclConfig.sh @<:@@:>@])], [TCL_CONFIG="${withval}"], [TCL_CONFIG=""]) AC_ARG_WITH([tk-config], [AC_HELP_STRING([--with-tk-config=TK_CONFIG], [specify location of tkConfig.sh @<:@@:>@])], [TK_CONFIG="${withval}"], [TK_CONFIG=""]) AC_ARG_VAR([TCLTK_LIBS], [flags needed for linking against the Tcl and Tk libraries]) AC_ARG_VAR([TCLTK_CPPFLAGS], [flags needed for finding the tcl.h and tk.h headers]) ## Tcl/Tk. COVERED_TCLTK ## Check for browser for help pages COVERED_PROG_BROWSER dnl Specify debug enabling COVERED_DEBUG dnl Specify profiler enabling COVERED_PROFILER dnl Specify test-mode enabling COVERED_TEST ## Simulators supported AC_ARG_WITH([iv], [AC_HELP_STRING([--with-iv=IV_BASE_DIR], [Create covered.vpi module for the Icarus Verilog simulator with the specified base directory @<:@@:>@])], [if test "${withval}" = no; then want_iv=no elif test "${withval}" = yes; then want_iv=yes else AC_CHECK_HEADER([$withval/include/iverilog/vpi_user.h], [want_iv=yes iv_prefix="${withval}" iv_inc_prefix="${withval}/include/iverilog"], [AC_CHECK_HEADER([$withval/include/vpi_user.h], [want_iv=yes iv_prefix="${withval}" iv_inc_prefix="${withval}/include"], [AC_CHECK_HEADER([$withval/include/verilog/vpi_user.h], [want_iv=yes iv_prefix="${withval}" iv_inc_prefix="${withval}/include/verilog"],AC_MSG_ERROR([Invalid base directory specified in --with-iv]))])]) fi], [want_iv=no]) if test "$want_iv" = yes; then AC_SUBST([IVLIB], ['covered.vpi']) AC_SUBST([IVDIR], ["${iv_prefix}"]) AC_SUBST([IVINC], ["${iv_inc_prefix}"]) fi AC_ARG_WITH([vcs], [AC_HELP_STRING([--with-vcs=VCS_INCLUDE_DIR], [Create covered.vcs.so file for the VCS simulator with the specified include directory @<:@@:>@])], [if test "${withval}" = no; then want_vcs=no elif test "${withval}" = yes; then want_vcs=yes else AC_CHECK_HEADER([$withval/vpi_user.h], [want_vcs=yes vcs_prefix="${withval}"],AC_MSG_ERROR([Invalid include directory specified in --with-vcs])) fi], [want_vcs=no]) if test "$want_vcs" = yes; then if test "$build_cygwin" = yes; then AC_MSG_ERROR([Cygwin version of VCS library is not available]) else AC_SUBST([VCSLIB], ['covered.vcs.so']) AC_SUBST([VCSINC], ["${vcs_prefix}"]) fi fi AC_ARG_WITH([ncv], [AC_HELP_STRING([--with-ncv=NCV_INCLUDE_DIR], [Create covered.ncv.so file for the NCVerilog simulator with the specified include directory @<:@@:>@])], [if test "${withval}" = no; then want_ncv=no elif test "${withval}" = yes; then want_ncv=yes else AC_CHECK_HEADER([$withval/vpi_user.h], [want_ncv=yes ncv_prefix="${withval}"],AC_MSG_ERROR([Invalid include directory specified in --with-ncv])) fi], [want_ncv=no]) if test "$want_ncv" = yes; then if test "$build_cygwin" = yes; then AC_MSG_ERROR([Cygwin version of NCVerilog library is not available]) else AC_SUBST([NCVLIB], ['covered.ncv.so']) AC_SUBST([NCVINC], ["${ncv_prefix}"]) fi fi AC_ARG_WITH([cver], [AC_HELP_STRING([--with-cver=CVER_INCLUDE_DIR], [Create covered.cver.so file for the CVER simulator with the specified include directory @<:@@:>@])], [if test "${withval}" = no; then want_cver=no elif test "${withval}" = yes; then want_cver=yes else AC_CHECK_HEADER([$withval/vpi_user.h], [want_cver=yes cver_prefix="${withval}"],AC_MSG_ERROR([Invalid include directory specified in --with-cver])) fi], [want_cver=no]) if test "$want_cver" = yes; then if test "$build_cygwin" = yes; then AC_SUBST([CVERLIB], ['covered.cver.dll']) else AC_SUBST([CVERLIB], ['covered.cver.so']) fi AC_SUBST([CVERINC], ["${cver_prefix}"]) fi dnl AC_CHECK_HEADERS(getopt.h) AC_CHECK_HEADERS(string.h) AC_CHECK_HEADERS(sys/time.h) AC_CHECK_HEADERS(math.h) dnl Checks for libraries. dnl AM_WITH_MPATROL(yes) dnl Checks for header files. AC_HEADER_STDC dnl Checks for typedefs, structures, and compiler characteristics. AC_C_CONST AC_CHECK_SIZEOF(char,4) AC_CHECK_SIZEOF(short,4) AC_CHECK_SIZEOF(int,4) AC_CHECK_SIZEOF(long,4) AC_CHECK_SIZEOF([long long],4) AC_CHECK_SIZEOF(float,4) AC_CHECK_SIZEOF(double,4) dnl Checks for library functions. AC_TYPE_SIGNAL AC_TYPE_SIZE_T AC_CHECK_LIB(m,round) AC_CHECK_LIB(m,roundf) dnl Stuff for creating dynamically loadable shared objects in a system-neutral way # Compiler option for position independent code, needed when making shared objects. # CFLAGS inherited by cadpli/Makefile? AX_C_PICFLAG # may modify CPPFLAGS and CFLAGS AX_CPP_PRECOMP # Linker option used when compiling the target AX_LD_RDYNAMIC # linker options when building a shared library AX_LD_SHAREDLIB_OPTS AC_OUTPUT(Makefile src/Makefile lib/Makefile scripts/Makefile doc/Makefile doc/docbook/Makefile) if test -n "${warn_tcltk_version}"; then AC_MSG_WARN([${warn_tcltk_version}]) fi covered-0.7.10/COPYING0000644000076500007650000004312707457705006014316 0ustar trevorwtrevorw GNU GENERAL PUBLIC LICENSE Version 2, June 1991 Copyright (C) 1989, 1991 Free Software Foundation, Inc. 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. Preamble The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Library General Public License instead.) You can apply it to your programs, too. When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it. For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights. We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software. Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations. Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all. The precise terms and conditions for copying, distribution and modification follow. GNU GENERAL PUBLIC LICENSE TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION 0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you". Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does. 1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. 2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change. b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License. c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.) These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program. In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. 3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following: a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, c) Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.) The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable. If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code. 4. You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. 5. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it. 6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License. 7. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program. If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances. It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice. This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License. 8. If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. 9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. 10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. NO WARRANTY 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. END OF TERMS AND CONDITIONS How to Apply These Terms to Your New Programs If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. Copyright (C) 19yy This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA Also add information on how to contact you by electronic and paper mail. If the program is interactive, make it output a short notice like this when it starts in an interactive mode: Gnomovision version 69, Copyright (C) 19yy name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program. You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names: Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker. , 1 April 1989 Ty Coon, President of Vice This General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Library General Public License instead of this License. covered-0.7.10/depcomp0000755000076500007650000004426711270512353014633 0ustar trevorwtrevorw#! /bin/sh # depcomp - compile a program generating dependencies as side-effects scriptversion=2009-04-28.21; # UTC # Copyright (C) 1999, 2000, 2003, 2004, 2005, 2006, 2007, 2009 Free # Software Foundation, Inc. # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2, or (at your option) # any later version. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # You should have received a copy of the GNU General Public License # along with this program. If not, see . # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Originally written by Alexandre Oliva . case $1 in '') echo "$0: No command. Try \`$0 --help' for more information." 1>&2 exit 1; ;; -h | --h*) cat <<\EOF Usage: depcomp [--help] [--version] PROGRAM [ARGS] Run PROGRAMS ARGS to compile a file, generating dependencies as side-effects. Environment variables: depmode Dependency tracking mode. source Source file read by `PROGRAMS ARGS'. object Object file output by `PROGRAMS ARGS'. DEPDIR directory where to store dependencies. depfile Dependency file to output. tmpdepfile Temporary file to use when outputing dependencies. libtool Whether libtool is used (yes/no). Report bugs to . EOF exit $? ;; -v | --v*) echo "depcomp $scriptversion" exit $? ;; esac if test -z "$depmode" || test -z "$source" || test -z "$object"; then echo "depcomp: Variables source, object and depmode must be set" 1>&2 exit 1 fi # Dependencies for sub/bar.o or sub/bar.obj go into sub/.deps/bar.Po. depfile=${depfile-`echo "$object" | sed 's|[^\\/]*$|'${DEPDIR-.deps}'/&|;s|\.\([^.]*\)$|.P\1|;s|Pobj$|Po|'`} tmpdepfile=${tmpdepfile-`echo "$depfile" | sed 's/\.\([^.]*\)$/.T\1/'`} rm -f "$tmpdepfile" # Some modes work just like other modes, but use different flags. We # parameterize here, but still list the modes in the big case below, # to make depend.m4 easier to write. Note that we *cannot* use a case # here, because this file can only contain one case statement. if test "$depmode" = hp; then # HP compiler uses -M and no extra arg. gccflag=-M depmode=gcc fi if test "$depmode" = dashXmstdout; then # This is just like dashmstdout with a different argument. dashmflag=-xM depmode=dashmstdout fi cygpath_u="cygpath -u -f -" if test "$depmode" = msvcmsys; then # This is just like msvisualcpp but w/o cygpath translation. # Just convert the backslash-escaped backslashes to single forward # slashes to satisfy depend.m4 cygpath_u="sed s,\\\\\\\\,/,g" depmode=msvisualcpp fi case "$depmode" in gcc3) ## gcc 3 implements dependency tracking that does exactly what ## we want. Yay! Note: for some reason libtool 1.4 doesn't like ## it if -MD -MP comes after the -MF stuff. Hmm. ## Unfortunately, FreeBSD c89 acceptance of flags depends upon ## the command line argument order; so add the flags where they ## appear in depend2.am. Note that the slowdown incurred here ## affects only configure: in makefiles, %FASTDEP% shortcuts this. for arg do case $arg in -c) set fnord "$@" -MT "$object" -MD -MP -MF "$tmpdepfile" "$arg" ;; *) set fnord "$@" "$arg" ;; esac shift # fnord shift # $arg done "$@" stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile" exit $stat fi mv "$tmpdepfile" "$depfile" ;; gcc) ## There are various ways to get dependency output from gcc. Here's ## why we pick this rather obscure method: ## - Don't want to use -MD because we'd like the dependencies to end ## up in a subdir. Having to rename by hand is ugly. ## (We might end up doing this anyway to support other compilers.) ## - The DEPENDENCIES_OUTPUT environment variable makes gcc act like ## -MM, not -M (despite what the docs say). ## - Using -M directly means running the compiler twice (even worse ## than renaming). if test -z "$gccflag"; then gccflag=-MD, fi "$@" -Wp,"$gccflag$tmpdepfile" stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile" exit $stat fi rm -f "$depfile" echo "$object : \\" > "$depfile" alpha=ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz ## The second -e expression handles DOS-style file names with drive letters. sed -e 's/^[^:]*: / /' \ -e 's/^['$alpha']:\/[^:]*: / /' < "$tmpdepfile" >> "$depfile" ## This next piece of magic avoids the `deleted header file' problem. ## The problem is that when a header file which appears in a .P file ## is deleted, the dependency causes make to die (because there is ## typically no way to rebuild the header). We avoid this by adding ## dummy dependencies for each header file. Too bad gcc doesn't do ## this for us directly. tr ' ' ' ' < "$tmpdepfile" | ## Some versions of gcc put a space before the `:'. On the theory ## that the space means something, we add a space to the output as ## well. ## Some versions of the HPUX 10.20 sed can't process this invocation ## correctly. Breaking it into two sed invocations is a workaround. sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile" rm -f "$tmpdepfile" ;; hp) # This case exists only to let depend.m4 do its work. It works by # looking at the text of this script. This case will never be run, # since it is checked for above. exit 1 ;; sgi) if test "$libtool" = yes; then "$@" "-Wp,-MDupdate,$tmpdepfile" else "$@" -MDupdate "$tmpdepfile" fi stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile" exit $stat fi rm -f "$depfile" if test -f "$tmpdepfile"; then # yes, the sourcefile depend on other files echo "$object : \\" > "$depfile" # Clip off the initial element (the dependent). Don't try to be # clever and replace this with sed code, as IRIX sed won't handle # lines with more than a fixed number of characters (4096 in # IRIX 6.2 sed, 8192 in IRIX 6.5). We also remove comment lines; # the IRIX cc adds comments like `#:fec' to the end of the # dependency line. tr ' ' ' ' < "$tmpdepfile" \ | sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' | \ tr ' ' ' ' >> "$depfile" echo >> "$depfile" # The second pass generates a dummy entry for each header file. tr ' ' ' ' < "$tmpdepfile" \ | sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' -e 's/$/:/' \ >> "$depfile" else # The sourcefile does not contain any dependencies, so just # store a dummy comment line, to avoid errors with the Makefile # "include basename.Plo" scheme. echo "#dummy" > "$depfile" fi rm -f "$tmpdepfile" ;; aix) # The C for AIX Compiler uses -M and outputs the dependencies # in a .u file. In older versions, this file always lives in the # current directory. Also, the AIX compiler puts `$object:' at the # start of each line; $object doesn't have directory information. # Version 6 uses the directory in both cases. dir=`echo "$object" | sed -e 's|/[^/]*$|/|'` test "x$dir" = "x$object" && dir= base=`echo "$object" | sed -e 's|^.*/||' -e 's/\.o$//' -e 's/\.lo$//'` if test "$libtool" = yes; then tmpdepfile1=$dir$base.u tmpdepfile2=$base.u tmpdepfile3=$dir.libs/$base.u "$@" -Wc,-M else tmpdepfile1=$dir$base.u tmpdepfile2=$dir$base.u tmpdepfile3=$dir$base.u "$@" -M fi stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" exit $stat fi for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" do test -f "$tmpdepfile" && break done if test -f "$tmpdepfile"; then # Each line is of the form `foo.o: dependent.h'. # Do two passes, one to just change these to # `$object: dependent.h' and one to simply `dependent.h:'. sed -e "s,^.*\.[a-z]*:,$object:," < "$tmpdepfile" > "$depfile" # That's a tab and a space in the []. sed -e 's,^.*\.[a-z]*:[ ]*,,' -e 's,$,:,' < "$tmpdepfile" >> "$depfile" else # The sourcefile does not contain any dependencies, so just # store a dummy comment line, to avoid errors with the Makefile # "include basename.Plo" scheme. echo "#dummy" > "$depfile" fi rm -f "$tmpdepfile" ;; icc) # Intel's C compiler understands `-MD -MF file'. However on # icc -MD -MF foo.d -c -o sub/foo.o sub/foo.c # ICC 7.0 will fill foo.d with something like # foo.o: sub/foo.c # foo.o: sub/foo.h # which is wrong. We want: # sub/foo.o: sub/foo.c # sub/foo.o: sub/foo.h # sub/foo.c: # sub/foo.h: # ICC 7.1 will output # foo.o: sub/foo.c sub/foo.h # and will wrap long lines using \ : # foo.o: sub/foo.c ... \ # sub/foo.h ... \ # ... "$@" -MD -MF "$tmpdepfile" stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile" exit $stat fi rm -f "$depfile" # Each line is of the form `foo.o: dependent.h', # or `foo.o: dep1.h dep2.h \', or ` dep3.h dep4.h \'. # Do two passes, one to just change these to # `$object: dependent.h' and one to simply `dependent.h:'. sed "s,^[^:]*:,$object :," < "$tmpdepfile" > "$depfile" # Some versions of the HPUX 10.20 sed can't process this invocation # correctly. Breaking it into two sed invocations is a workaround. sed 's,^[^:]*: \(.*\)$,\1,;s/^\\$//;/^$/d;/:$/d' < "$tmpdepfile" | sed -e 's/$/ :/' >> "$depfile" rm -f "$tmpdepfile" ;; hp2) # The "hp" stanza above does not work with aCC (C++) and HP's ia64 # compilers, which have integrated preprocessors. The correct option # to use with these is +Maked; it writes dependencies to a file named # 'foo.d', which lands next to the object file, wherever that # happens to be. # Much of this is similar to the tru64 case; see comments there. dir=`echo "$object" | sed -e 's|/[^/]*$|/|'` test "x$dir" = "x$object" && dir= base=`echo "$object" | sed -e 's|^.*/||' -e 's/\.o$//' -e 's/\.lo$//'` if test "$libtool" = yes; then tmpdepfile1=$dir$base.d tmpdepfile2=$dir.libs/$base.d "$@" -Wc,+Maked else tmpdepfile1=$dir$base.d tmpdepfile2=$dir$base.d "$@" +Maked fi stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile1" "$tmpdepfile2" exit $stat fi for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" do test -f "$tmpdepfile" && break done if test -f "$tmpdepfile"; then sed -e "s,^.*\.[a-z]*:,$object:," "$tmpdepfile" > "$depfile" # Add `dependent.h:' lines. sed -ne '2,${ s/^ *// s/ \\*$// s/$/:/ p }' "$tmpdepfile" >> "$depfile" else echo "#dummy" > "$depfile" fi rm -f "$tmpdepfile" "$tmpdepfile2" ;; tru64) # The Tru64 compiler uses -MD to generate dependencies as a side # effect. `cc -MD -o foo.o ...' puts the dependencies into `foo.o.d'. # At least on Alpha/Redhat 6.1, Compaq CCC V6.2-504 seems to put # dependencies in `foo.d' instead, so we check for that too. # Subdirectories are respected. dir=`echo "$object" | sed -e 's|/[^/]*$|/|'` test "x$dir" = "x$object" && dir= base=`echo "$object" | sed -e 's|^.*/||' -e 's/\.o$//' -e 's/\.lo$//'` if test "$libtool" = yes; then # With Tru64 cc, shared objects can also be used to make a # static library. This mechanism is used in libtool 1.4 series to # handle both shared and static libraries in a single compilation. # With libtool 1.4, dependencies were output in $dir.libs/$base.lo.d. # # With libtool 1.5 this exception was removed, and libtool now # generates 2 separate objects for the 2 libraries. These two # compilations output dependencies in $dir.libs/$base.o.d and # in $dir$base.o.d. We have to check for both files, because # one of the two compilations can be disabled. We should prefer # $dir$base.o.d over $dir.libs/$base.o.d because the latter is # automatically cleaned when .libs/ is deleted, while ignoring # the former would cause a distcleancheck panic. tmpdepfile1=$dir.libs/$base.lo.d # libtool 1.4 tmpdepfile2=$dir$base.o.d # libtool 1.5 tmpdepfile3=$dir.libs/$base.o.d # libtool 1.5 tmpdepfile4=$dir.libs/$base.d # Compaq CCC V6.2-504 "$@" -Wc,-MD else tmpdepfile1=$dir$base.o.d tmpdepfile2=$dir$base.d tmpdepfile3=$dir$base.d tmpdepfile4=$dir$base.d "$@" -MD fi stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" "$tmpdepfile4" exit $stat fi for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" "$tmpdepfile4" do test -f "$tmpdepfile" && break done if test -f "$tmpdepfile"; then sed -e "s,^.*\.[a-z]*:,$object:," < "$tmpdepfile" > "$depfile" # That's a tab and a space in the []. sed -e 's,^.*\.[a-z]*:[ ]*,,' -e 's,$,:,' < "$tmpdepfile" >> "$depfile" else echo "#dummy" > "$depfile" fi rm -f "$tmpdepfile" ;; #nosideeffect) # This comment above is used by automake to tell side-effect # dependency tracking mechanisms from slower ones. dashmstdout) # Important note: in order to support this mode, a compiler *must* # always write the preprocessed file to stdout, regardless of -o. "$@" || exit $? # Remove the call to Libtool. if test "$libtool" = yes; then while test "X$1" != 'X--mode=compile'; do shift done shift fi # Remove `-o $object'. IFS=" " for arg do case $arg in -o) shift ;; $object) shift ;; *) set fnord "$@" "$arg" shift # fnord shift # $arg ;; esac done test -z "$dashmflag" && dashmflag=-M # Require at least two characters before searching for `:' # in the target name. This is to cope with DOS-style filenames: # a dependency such as `c:/foo/bar' could be seen as target `c' otherwise. "$@" $dashmflag | sed 's:^[ ]*[^: ][^:][^:]*\:[ ]*:'"$object"'\: :' > "$tmpdepfile" rm -f "$depfile" cat < "$tmpdepfile" > "$depfile" tr ' ' ' ' < "$tmpdepfile" | \ ## Some versions of the HPUX 10.20 sed can't process this invocation ## correctly. Breaking it into two sed invocations is a workaround. sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile" rm -f "$tmpdepfile" ;; dashXmstdout) # This case only exists to satisfy depend.m4. It is never actually # run, as this mode is specially recognized in the preamble. exit 1 ;; makedepend) "$@" || exit $? # Remove any Libtool call if test "$libtool" = yes; then while test "X$1" != 'X--mode=compile'; do shift done shift fi # X makedepend shift cleared=no eat=no for arg do case $cleared in no) set ""; shift cleared=yes ;; esac if test $eat = yes; then eat=no continue fi case "$arg" in -D*|-I*) set fnord "$@" "$arg"; shift ;; # Strip any option that makedepend may not understand. Remove # the object too, otherwise makedepend will parse it as a source file. -arch) eat=yes ;; -*|$object) ;; *) set fnord "$@" "$arg"; shift ;; esac done obj_suffix=`echo "$object" | sed 's/^.*\././'` touch "$tmpdepfile" ${MAKEDEPEND-makedepend} -o"$obj_suffix" -f"$tmpdepfile" "$@" rm -f "$depfile" cat < "$tmpdepfile" > "$depfile" sed '1,2d' "$tmpdepfile" | tr ' ' ' ' | \ ## Some versions of the HPUX 10.20 sed can't process this invocation ## correctly. Breaking it into two sed invocations is a workaround. sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile" rm -f "$tmpdepfile" "$tmpdepfile".bak ;; cpp) # Important note: in order to support this mode, a compiler *must* # always write the preprocessed file to stdout. "$@" || exit $? # Remove the call to Libtool. if test "$libtool" = yes; then while test "X$1" != 'X--mode=compile'; do shift done shift fi # Remove `-o $object'. IFS=" " for arg do case $arg in -o) shift ;; $object) shift ;; *) set fnord "$@" "$arg" shift # fnord shift # $arg ;; esac done "$@" -E | sed -n -e '/^# [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' \ -e '/^#line [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' | sed '$ s: \\$::' > "$tmpdepfile" rm -f "$depfile" echo "$object : \\" > "$depfile" cat < "$tmpdepfile" >> "$depfile" sed < "$tmpdepfile" '/^$/d;s/^ //;s/ \\$//;s/$/ :/' >> "$depfile" rm -f "$tmpdepfile" ;; msvisualcpp) # Important note: in order to support this mode, a compiler *must* # always write the preprocessed file to stdout. "$@" || exit $? # Remove the call to Libtool. if test "$libtool" = yes; then while test "X$1" != 'X--mode=compile'; do shift done shift fi IFS=" " for arg do case "$arg" in -o) shift ;; $object) shift ;; "-Gm"|"/Gm"|"-Gi"|"/Gi"|"-ZI"|"/ZI") set fnord "$@" shift shift ;; *) set fnord "$@" "$arg" shift shift ;; esac done "$@" -E 2>/dev/null | sed -n '/^#line [0-9][0-9]* "\([^"]*\)"/ s::\1:p' | $cygpath_u | sort -u > "$tmpdepfile" rm -f "$depfile" echo "$object : \\" > "$depfile" sed < "$tmpdepfile" -n -e 's% %\\ %g' -e '/^\(.*\)$/ s:: \1 \\:p' >> "$depfile" echo " " >> "$depfile" sed < "$tmpdepfile" -n -e 's% %\\ %g' -e '/^\(.*\)$/ s::\1\::p' >> "$depfile" rm -f "$tmpdepfile" ;; msvcmsys) # This case exists only to let depend.m4 do its work. It works by # looking at the text of this script. This case will never be run, # since it is checked for above. exit 1 ;; none) exec "$@" ;; *) echo "Unknown depmode $depmode" 1>&2 exit 1 ;; esac exit 0 # Local Variables: # mode: shell-script # sh-indentation: 2 # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "scriptversion=" # time-stamp-format: "%:y-%02m-%02d.%02H" # time-stamp-time-zone: "UTC" # time-stamp-end: "; # UTC" # End: covered-0.7.10/doc/0000755000076500007650000000000011475644735014027 5ustar trevorwtrevorwcovered-0.7.10/doc/covered.10000644000076500007650000006722111475640523015537 0ustar trevorwtrevorw.TH "Covered" "1" "covered-0.7.10" "Trevor Williams" "Code Analysis" .SH "NAME" .LP Covered \- Verilog Code Coverage Analyzer .SH "SYNTAX" .LP \fBcovered\fR [\fIglobal_options\fR] \fBscore\fR [\fIoptions\fR] .br \fBcovered\fR [\fIglobal_options\fR] \fBmerge\fR [\fIoptions\fR] \fIexisting_database\fR \fIdatabase_to_merge\fR+ .br \fBcovered\fR [\fIglobal_options\fR] \fBreport\fR [\fIoptions\fR] \fIdatabase_file\fR .br \fBcovered\fR [\fIglobal_options\fR] \fBrank\fR [\fIoptions\fR] \fIdatabase_to_rank\fR \fIdatabase_to_rank\fR+ .br \fBcovered\fR [\fIglobal_options\fR] \fBexclude\fR [\fIoptions\fR] \fIexclusion_id\fR+ \fIdatabase_file\fR .SH "DESCRIPTION" .LP \fICovered\fR is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test. Covered reads in the Verilog design files and a VCD, LXT2 or FST formatted dumpfile from a diagnostic run and generates a database file called a Coverage Description Database (CDD) file, using the score command. Covered's score command can alternatively be used to generate a CDD file and a Verilog module for using Covered as a VPI module in a testbench which can obtain coverage information in parallel with simulation (see \fIUSING COVERED AS A VPI MODULE\fR). The resulting CDD file can be merged with other CDD files from the same design to create accummulated coverage, using the merge command. Once a CDD file is created, the user can use Covered to generate various human\-readable coverage reports in an ASCII format or use Covered's GUI to interactively look at coverage results, using the report command. If uncovered coverage points are found that the user wants to exclude from coverage, this can be handled with either the command\-line exclude command or within the GUI. When multiple CDD files are created from the same design, the user may obtain a coverage ranking of those CDD files to determine an ideal order for regression testing as well as understand which CDD files can be excluded from regressions due to their inability to hit new coverage points. Additionally, as part of Covered's score command, race condition possibilities are found in the design files and can be either ignored, flagged as warnings or flagged as errors. By specifying race conditions as errors, Covered can also be used as a race condition checker. .SH "GLOBAL OPTIONS" .LP These options are placed immediately after the keyword \fIcovered\fR in the command\-line. They can be used for any command (with the exception of \fI\-v\fR and \fI\-h\fR) and have the same effect in each case. .TP \fB\-B\fR Obfuscate. Obfuscates all design\-sensitive names before outputting in user\-readable format. This option is useful when sharing output with the developers of Covered for debugging purposes. .TP \fB\-D\fR Debug. Display information helpful for debugging tool problems. Note: This option is now only available when covered is built with the \-\-enable\-debug configuration option. .TP \fB\-h\fR Help. Display this usage information. .TP \fB\-P\fR [\fIfilename\fR] Profiling mode. Turns on internal source code profiler that will produce a profiling report of the run command to either the specified \fIfilename\fR or, if no \fIfilename\fR is present, to a file called \fIcovered.prof\fR. This option is only available if the \fI\-\-enable\-profiling\fR configuration option was specified when Covered was built. .TP \fB\-Q\fR Quiet mode. Causes all output to be suppressed. .TP \fB\-T\fR Terse mode. Causes all output to be suppressed with the exception of warning messages and the Covered header information. .TP \fB\-v\fR Version. Display current Covered version. .SH "COMMANDS" .LP .TP \fBscore\fR Parses Verilog files and VCD/LXT2/FST dumpfiles to create database file used for merging and reporting. .TP \fBmerge\fR Merges two or more database files into one. .TP \fBreport\fR Generates human\-readable coverage reports from database file or starts the coverage report GUI. .TP \fBrank\fR Generates a report that specifies an ideal order to run regressions and specifies CDD files that do not add new coverage information (and can, therefore, be excluded from regressions, if desired). .TP \fBexclude\fR Allows one or more coverage points (identified with exclusion IDs in a report generated with the \-x option) to have their exclusion property toggled (include to exclude or exclude to include) and, if the exclusion property is set to exclude, optionally allow a reason for the exclusion to be associated with it and stored in the specified CDD file. .SH "SCORE COMMAND" .LP The following options are valid for the score command: .TP \fB\-A ovl\fR Causes OVL assertions to be used for assertion coverage. This flag must be given to the score command if assertion coverage metrics are needed in the report command. .TP \fB\-cdd\fR \fIdatabase\fR Same as the \-o option. Useful when CDD file being scored is an input to the score command. .TP \fB\-cli\fR [\fIfilename\fR] Causes the command\-line debugger to be used during VCD/LXT2/FST dumpfile scoring. If \fIfilename\fR is specified, this file contains information saved in a previous call to savehist on the CLI and causes the history contained in this file to be replayed prior to the CLI command prompt. If \fIfilename\fR is not specified, the CLI prompt will be immediately available at the start of simulation. This option is only available when Covered is configured with the \fI\-\-enable\-debug\fR option. .TP \fB\-conservative\fR If this option is specified, any logic blocks that contain code that could cause coverage discrepancies leading to potentially inaccurate coverage results are removed from coverage consideration. See User's Guide for more information on what type of code can lead to coverage inaccuracies. .TP \fB\-dumpvars\fR [\fIfilename\fR] If this option is specified without the \-vcd or \-lxt options, the design is parsed, a CDD file is created and a top\-level Verilog module file named \fIfilename\fR (if this value is specified) or "covered_dump.v" (if \fIfilename\fR is not specified) is created. This file is used in the compilation of the simulator to create a dumpfile that is optimized for obtaining coverage for the specified CDD file. If either the \-vcd or \-lxt options are specified, this option has no effect. See the User's Guide for more information on how to use this option. .TP \fB\-D\fR \fIdefine_name\fR Defines the specified name to 1. .TP \fB\-D\fR \fIdefine_name=value\fR Defines the specified name to the specified value. .TP \fB\-e\fR \fIblock_name\fR Name of module, task, function or named begin/end block to not score. Causes all subblocks in the Verilog tree under this block to also not be scored. .TP \fB\-ea\fR Excludes all always blocks from being considered for coverage. .TP \fB\-ec\fR Excludes all continuous assignments from being considered for coverage. .TP \fB\-ei\fR Excludes all initial blocks from being considered for coverage. .TP \fB\-ef\fR Excludes all final blocks from being considered for coverage. .TP \fB\-ep\fR [\fIname\fR] Excludes all code found between '// coverage off' and '// coverage on' pragmas embedded within the design. If \fIname\fR is specified, the keyword in the pragma will be changed to that name instead of the default "coverage", allowing the user to change the look of the pragma if it conflicts with any other tools. .TP \fB\-F\fR \fImodule_name=[in_expr,]out_expr\fR Indicates to the parser where to find the FSM located in module \fImodule_name\fR which has an input state expression called \fIin_expr\fR and output state expression called \fIout_expr\fR. If \fIin_expr\fR is not specified, \fIout_expr\fR is used as both the input and output state expression. .TP \fB\-f\fR \fIfilename\fR Name of file containing additional arguments to parse. .TP \fB\-fst\fR \fIfilename\fR Name of FST dumpfile to score design with. If \-vcd, \-lxt or this option is not used, Covered will only create an initial CDD file from the design and will not attempt to score the design. .TP \fB\-g\fR \fI[module_name=](1|2|3)\fR Allows the user to limit the parser to a specific generation of the Verilog standard for a specific module or the entire design, where 1=Verilog\-1995, 2=Verilog\-2001, 3=SystemVerilog. If \fImodule_name=\fR is specified, the parser uses the specified Verilog standard for that module only, allowing the rest of the design to use the global standard. By default, the global standard is set to the most recent version (3). This option can be specified more than once for a given call to the score command; however, if the \-g option specifies more than global value (i.e., without the \fImodule=\fR prefix), only the last option value will be used. .TP \fB\-h\fR Displays this help information. .TP \fB\-I\fR \fIdirectory\fR Directory to find included Verilog files. .TP \fB\-i\fR \fIinstance_name\fR Verilog hierarchical reference to the module that is at the top of the tree to be scored. This option is necessary if module to verify coverage is not the top\-level module in the design. If not specified, \fI\-t\fR value is used. .TP \fB\-lxt\fR \fIfilename\fR Name of LXT2 dumpfile to score design with. If \-vcd, \-fst or this option is not used, Covered will only create an initial CDD file from the design and will not attempt to score the design. .TP \fB\-m\fR \fImessage\fR Allows the user to specify information about this CDD file. This information can be anything (messages with whitespace should be surrounded by double\-quotation marks), but may include something about the simulation arguments to more easily link the CDD file to its simulation for purposes of recreating the CDD file. .TP \fB\-o\fR \fIdatabase\fR Name of database to write coverage information to. If not specified, the output database filename will be "cov.cdd". .TP \fB\-p\fR \fIfilename\fR Overrides default filename used to store intermediate preprocessor output. .TP \fB\-P\fR \fIparameter_scope=value\fR Performs a defparam on the specified parameter with value. .TP \fB\-rS\fR When race condition checks are violated, the offending logic blocks are removed from coverage consideration and all output is suppressed regarding the race condition violation. See user documentation for more information about race condition checking usage. .TP \fB\-rW\fR When race condition checks are violated, the offending logic blocks are removed from coverage consideration and the race condition violation is output. This is the default behavior for race condition handling. See user documentation for more information about race condition checking usage. .TP \fB\-rE\fR When race condition checks are violated, the reason is output and scoring ends immediately. See user documentation for more information about race condition checking usage. .TP \fB\-rI[=\fImodule name\fR]\fR If \fImodule name\fR is not specified, race condition checking is skipped altogether for the entire design. If \fImodule name\fR is specified, race condition checking is skipped for the specified module. See user documentation for more information about race condition checking usage. .TP \fB\-rP[=\fIname\fR])\fR Uses embedded pragmas for ignoring certain code from race condition checking consideration (if \fIname\fR is specified it is used as the pragma keyword). See user documentation for more information about race condition checking usage. .TP \fB\-S\fR Outputs simulation statistics after simulation has completed. This information is currently only useful for the developers of Covered. .TP \fB\-t\fR \fItop\-level module\fR Specifies the module name of the top\-most module that will be measured. Note that this module does not need to be the top\-most module in the simulator. This field is required for all calls to the score command. .TP \fB\-top_ts\fR \fItimescale\fR This option is only valid when the \-vpi or \-dumpvars options have been specified. This option allows the user to specify a timescale for the generated Verilog module created with the \-vpi/\-dumpvars option. If this option is not specified, no timescale will be created for the generated module. The value of \fItimescale\fR is specified as follows: .IP \fB(1|10|100)(s|ms|us|ns|ps|fs)/(1|10|100)(s|ms|us|ns|ps|fs)\fR .IP If whitespace is needed between the various values, place the entire contents of \fItimescale\fR in double quotes. .TP \fB\-ts\fR \fInumber\fR When scoring occurs, this option allows the user to see how far the simulator has progressed by outputting the current timestep to standard output. The value of \fInumber\fR specifies how many timesteps are allowed to be simulated before outputting the current timestep (results in less calls to output stream). .TP \fB\-T (min|typ|max)\fR Specifies which value to use when encountering a delay expression in the form: min:typ:max. If this option is not specified, 'typ' select is used by default. .TP \fB\-v\fR \fIfilename\fR Name of specific Verilog file to score. .TP \fB\-vcd\fR \fIfilename\fR Name of VCD dumpfile to score design with. If \-lxt, \-fst or this option is not used, Covered will only create an initial CDD file from the design and will not attempt to score the design. .TP \fB\-vpi\fR [\fIfilename\fR] If this option is specified without the \-vcd, \-lxt or \-fst options, the design is parsed, a CDD file is created and a top\-level Verilog module file named \fIfilename\fR (if this value is specified) or "covered_vpi.v" (if \fIfilename\fR is not specified) is created along with a PLI table file called \fIfilename\fR.ta b or "covered_vpi.v.ta b". Both of these files are used in the compilation of the simulator to use Covered as a VPI module. If either the \-vcd, \-lxt or \-fst options are specified, this option has no effect. .TP \fB\-Wignore\fR Suppress the output of warnings during code parsing and simulation. .TP \fB\-y\fR \fIdirectory\fR Directory to find unspecified Verilog files. .TP \fB+libext+\fR\fI.extension\fR[\fB+\fR\fI.extension\fR]*\fB+\fR\fR Extensions of Verilog files to allow in scoring. .SH "MERGE COMMAND" .LP The following options are valid for the merge command: .TP \fB\-d\fR \fIfilename\fR Directory to search for CDD files to include. This option is used in conjunction with the \fB\-ext\fR option which specifies the file extension to use for determining which files in the directory are CDD files. .TP \fB\-er\fR (\fIfirst\fR|\fIlast\fR|\fIall\fR|\fInew\fR|\fIold\fR) Specifies how to handle exclusion reason resolution. If two or more CDD files being merged have exclusion reasons specified for the same coverage point, the exclusion reason needs to be resolved (unless it is the same string value). If this option is not specified and a conflict is found, Covered will interactively request input for each exclusion as to how to handle it. If this option is specified, it tells Covered how to handle all exclusion reason conflicts. The values are as follows:.br .IP \fIfirst\fR \- CDD file that contained the first exclusion reason is used. .IP \fIlast\fR \- CDD file that contained the last exclusion reason is used. .IP \fIall\fR \- All exclusion reasons are used (concatenated). .IP \fInew\fR \- Use the newest exclusion reason specified. .IP \fIold\fR \- Use the oldest exclusion reason specified. .TP \fB\-ext\fR \fIextension\fR Used in conjunction with the \fB\-d\fR option. If no \fB\-ext\fR options are specified on the command\-line, the default value of '.cdd' is used. Note that a period (.) should be specified. .TP \fB\-f\fR \fIfilename\fR Name of file containing additional arguments to parse. .TP \fB\-h\fR Displays this help information. .TP \fB\-m\fR \fImessage\fR Allows the user to specify information about this CDD file. This information can be anything (messages with whitespace should be surrounded by double\-quotation marks). .TP \fB\-o\fR \fIfilename\fR File to output new database to. If this argument is not specified, the \fIexisting_database\fR is used as the output database name. .SH "REPORT COMMAND" .LP The following options are valid with the report command: .TP \fB\-b\fR If combinational logic verbose output is reported and the expression is a vector operation, this option outputs the coverage information on a bitwise basis. .TP \fB\-c\fR If \fI\-v\fR is specified, displays covered metrics only. Default is to display uncovered information only. .TP \fB\-d\fR \fI(s|d|v)\fR Level of detail to provide in coverage report information (s = summary, d = detailed, v = verbose). Default is summary. .TP \fB\-e\fR Outputs all excluded coverage points to the report file along with any specified exclusion reasons if the \fB\-d d\fR or \fB\-d v\fR options are specified. .TP \fB\-f\fR \fIfilename\fR Name of file containing additional arguments to parse. .TP \fB\-h\fR Displays this help information. .TP \fB\-i\fR Provides coverage information for instances instead of module. .TP \fB\-m\fR \fI[l][t][c][f][r][a][m]\fR Type(s) of metrics to report. l=line, t=toggle, c=combinational logic, f=FSM state and state transition, r=race conditions, a=assertion, m=memory. Default is \fIltcf\fR. .TP \fB\-o\fR \fIfilename\fR File to output report information to. Default is standard output. .TP \fB\-s\fR Suppresses modules/instances that contain no coverage information from being output to the report. Used to help eliminate potentially meaningless information from the report. .TP \fB\-v\fR Deprecated. Replaced by '\-d d' or '\-d v'. .TP \fB\-view\fR Starts the GUI interface for interactive coverage reporting. .TP \fB\-w (\fR\fInumber\fR\fB)\fR Specifies the maximum line width (in characters) that can be used to output Verilog information. If this option is not specified, all Verilog code in the report will retain the same formatting as was specified in the original Verilog code. If this option is specified, Verilog code will be formatted to use as much of the current line as possible, wrapping text when the line reaches the maximum line width. The default maximum line width is 115 characters (this value is used if no number is specified with the \-w option). If a number is specified with the \-w option, this value is used for the maximum line width. .TP \fB\-x\fR Outputs the exclusion IDs of all uncovered and excluded coverage points within parenthesis before the associated verbose output of the coverage point. The exclusion IDs can be used to exclude/include coverage points via the exclude command. .SH "RANK COMMAND" .LP The following options are valid with the rank command: .TP \fB\-d\fR \fIfilename\fR Directory to search for CDD files to include. This option is used in conjunction with the \fB\-ext\fR option which specifies the file extension to use for determining which files in the directory are CDD files. .TP \fB\-depth\fR \fInumber\fR Specifies the minimum number of needed CDD files to hit each coverage point. The value of \fInumber\fR should be greater than zero. Default is 1. .TP \fB\-ext\fR \fIextension\fR Used in conjunction with the \fB\-d\fR option. If no \fB\-ext\fR options are specified on the command\-line, the default value of '.cdd' is used. Note that a period (.) should be specified. .TP \fB\-f\fR \fIfilename\fR Name of file containing additional arguments to parse. .TP \fB\-h\fR Displays help information for the rank command. .TP \fB\-names\-only\fR If specified, outputs only the needed CDD filenames that need to be run in the order they need to be run. If this option is not set, a report\-style output is provided with additional information. This option is meant to be useful in scripts that only want CDD filenames to run as output. .TP \fB\-o\fR \fIfilename\fR Name of file to output ranking information to. Default is standard output. .TP \fB\-required\-cdd\fR \fIfilename\fR Name of CDD that should be considered a required CDD to rank (i.e., it cannot be excluded for any reason). .TP \fB\-required\-list\fR \fIfilename\fR Name of a file that contains a list of CDDs that should be considered required CDDs to rank. The filenames should be separated by whitespace or newline characters within the file. .TP \fB\-v\fR Causes verbose output to be displayed when the rank command is run. It outputs diagnostic information about each of the different phases of the ranking algorithm including run\-time, number of CDD files included/excluded and number of coverage points hit by ranked CDDs during each phase. This information is meant to be useful for those interested in the ranking algorithm and its performance. .TP \fB\-weight\-assert\fR \fInumber\fR Specifies a relative weighting for assertion coverage used to rank non\-unique coverage points. The value of \fInumber\fR is relative to the values used in the \fB\-weight\-toggle\fR, \fB\-weight\-memory\fR, \fB\-weight\-comb\fR, \fB\-weight\-fsm\fR and \fB\-weight\-line\fR rank command options. .TP \fB\-weight\-comb\fR \fInumber\fR Specifies a relative weighting for combinational logic coverage used to rank non\-unique coverage points. The value of \fInumber\fR is relative to the values used in the \fB\-weight\-toggle\fR, \fB\-weight\-memory\fR, \fB\-weight\-assert\fR, \fB\-weight\-fsm\fR and \fB\-weight\-line\fR rank command options. .TP \fB\-weight\-fsm\fR \fInumber\fR Specifies a relative weighting for FSM state and state transition coverage used to rank non\-unique coverage points. The value of \fInumber\fR is relative to the values used in the \fB\-weight\-toggle\fR, \fB\-weight\-memory\fR, \fB\-weight\-comb\fR, \fB\-weight\-assert\fR and \fB\-weight\-line\fR rank command options. .TP \fB\-weight\-line\fR \fInumber\fR Specifies a relative weighting for line coverage used to rank non\-unique coverage points. The value of \fInumber\fR is relative to the values used in the \fB\-weight\-toggle\fR, \fB\-weight\-memory\fR, \fB\-weight\-comb\fR, \fB\-weight\-fsm\fR and \fB\-weight\-assert\fR rank command options. .TP \fB\-weight\-memory\fR \fInumber\fR Specifies a relative weighting for memory coverage used to rank non\-unique coverage points. The value of \fInumber\fR is relative to the values used in the \fB\-weight\-toggle\fR, \fB\-weight\-line\fR, \fB\-weight\-comb\fR, \fB\-weight\-fsm\fR and \fB\-weight\-assert\fR rank command options. .TP \fB\-weight\-toggle\fR \fInumber\fR Specifies a relative weighting for toggle coverage used to rank non\-unique coverage points. The value of \fInumber\fR is relative to the values used in the \fB\-weight\-memory\fR, \fB\-weight\-line\fR, \fB\-weight\-comb\fR, \fB\-weight\-fsm\fR and \fB\-weight\-assert\fR rank command options. .SH "EXCLUDE COMMAND" .LP The following options are valid with the exclude command: .TP \fB\-f\fR \fIfilename\fR Specifies the name of a file that contains more options to the exclude command. This option may be specified as many times as necessary for a single call to the exclude command. .TP \fB\-h\fR Generates usage information for the exclude command. .TP \fB\-m\fR Allows for an exclusion message to be associated with any coverage points going from the included state to the excluded state. For each coverage point that meets this requirement, the user will be prompted to input a reason. The reason may be any length and any number of lines; however, all formatting characters (i.e., newlines, tabs, extra spaces, etc.) will be removed and replaced with a single space when it is later displayed. To end the input of a message, hit a return, enter a single period (.) character and hit return again. The final period character will not be part of the exclusion message. .TP \fB\-p\fR Causes all specified coverage points to print their current exclusion status and exclusion reason (if one exists for the excluded coverage point) to standard output. If this option is specified, the \fB\-m\fP option will be ignored. .SH "USING COVERED AS A VPI MODULE" .TP In addition to using Covered's score command to parse a VCD, LXT2 or FST file to abstract coverage information, Covered may also be used as a VPI module within a simulator to extract this information. The advantages to using Covered as a VPI over a dumpfile reader include the following. First, VCD files can be extrememly large, especially for long simulations, using up valuable disk space. Second, if you are using a simulator that dumps files in a different format than VCD, LXT2 or FST and you want to convert these dump file types to one of these versions, the cost of disk space and time can make creating dumpfiles that Covered requires undesirable. Additionally, though using Covered as a VPI module will slow down your simulation speed, it is most likely that the total time spent simulating your design and scoring the design in one step will be shorter than doing so in two steps. As a result, Covered's configure utility can generate VPI\-ready libraries for the following free and commercial simulators (Icarus Verilog, CVER and VCS). .TP To automatically build the VPI\-ready library files when generating Covered from source, simply specify one or more of the following when running the "configure" utility in the base Covered directory: \-\-with\-iv=, \-\-with\-vcs=, \-\-with\-cver=. After Covered has been configured, simply type 'make' and 'make install'. This will install the VPI\-ready library files in the installation libexec directory (by default this path will be /usr/local/libexec). .TP Before you are ready to compile the design, you must first create a CDD file, a top\-level Verilog file, and a PLI table file (the last file is only needed for the VCS compiler). This is done by specifying the \fB\-vpi\fR (\fIfilename\fR) option to Covered's score command. If no filename is specified after \-vpi, the files covered_vpi.v and covered_vpi.ta b will be created along with the generated coverage file. Note that this step only needs to be performed once unless the design files change. You are now ready to compile the simulator. .TP If you are compiling an Icarus Verilog simulation, simply add '\-m /usr/local/libexec/covered.vpi covered_vpi.v' to the 'iverilog' command\-line. Once compilation is complete, run the generated executable file as you normally would. .TP If you are compiling a CVER simulation, simply add '+loadvpi=/usr/local/libexec/covered.cver.so:vpi_compat_bootstrap covered_vpi.v' to the 'cver' command\-line. .TP If you are compiling a VCS simulation, simply add '+vpi \-load /usr/local/libexec/covered.vcs.so:covered_register covered_vpi.v' to the 'vcs' command\-line. Once compilation is complete, run the generated executable file as you normally would. .TP If you are compiling a NC-Verilog simulation, switch to NC-Verilog's irun command to load the covered shared object: '\-loadvpi /usr/local/libexec/covered.ncv.so:covered_register' and enable all access with '\-access +rwc'. You can hardcode the $covered_sim call into your RTL or you can run it dynamically using the CLI, by adding the \-input input.tcl switch to irun. Where the input.tcl file looks like the following and tb.dut is the coverage instance: .br call -systf {$covered_sim} {"scored.cdd"} tb.dut .br run .TP There are two plusargs that can be passed to the generated executable when it is run that Covered will parse. The '+covered_cdd=' option will cause Covered to output the scored design contents to the CDD file specified by . This allows multiple runs of the simulator to generate several different CDD files without needed a recompile to occur. The '+covered_debug' option will cause Covered to dump a lot of excessive output about its internal run\-time state during simulation. This output will only be generated if Covered was configured with the \-\-enable\-debug option. This plusarg option should not be used by regular users as it is primarily intended to aid the developers of Covered in debugging. .SH "AUTHORS" .LP Trevor Williams .SH "SEE ALSO" .LP For more information on how to use the Covered code coverage tool, please consult the User's Guide included with this release at /usr/local/share/covered/doc/html/index.html. covered-0.7.10/doc/covered.dox0000644000076500007650000002161511475640523016166 0ustar trevorwtrevorw# Doxyfile 1.5.4 #--------------------------------------------------------------------------- # Project related configuration options #--------------------------------------------------------------------------- DOXYFILE_ENCODING = UTF-8 PROJECT_NAME = Covered PROJECT_NUMBER = covered-0.7.10 OUTPUT_DIRECTORY = ./devel CREATE_SUBDIRS = NO OUTPUT_LANGUAGE = English BRIEF_MEMBER_DESC = YES REPEAT_BRIEF = YES ABBREVIATE_BRIEF = ALWAYS_DETAILED_SEC = YES INLINE_INHERITED_MEMB = NO FULL_PATH_NAMES = YES STRIP_FROM_PATH = STRIP_FROM_INC_PATH = SHORT_NAMES = NO JAVADOC_AUTOBRIEF = NO QT_AUTOBRIEF = NO MULTILINE_CPP_IS_BRIEF = NO DETAILS_AT_TOP = YES INHERIT_DOCS = YES SEPARATE_MEMBER_PAGES = NO TAB_SIZE = 8 ALIASES = OPTIMIZE_OUTPUT_FOR_C = YES OPTIMIZE_OUTPUT_JAVA = NO BUILTIN_STL_SUPPORT = NO CPP_CLI_SUPPORT = NO SIP_SUPPORT = NO DISTRIBUTE_GROUP_DOC = NO SUBGROUPING = YES TYPEDEF_HIDES_STRUCT = NO #--------------------------------------------------------------------------- # Build related configuration options #--------------------------------------------------------------------------- EXTRACT_ALL = YES EXTRACT_PRIVATE = NO EXTRACT_STATIC = YES EXTRACT_LOCAL_CLASSES = YES EXTRACT_LOCAL_METHODS = NO EXTRACT_ANON_NSPACES = NO HIDE_UNDOC_MEMBERS = NO HIDE_UNDOC_CLASSES = NO HIDE_FRIEND_COMPOUNDS = NO HIDE_IN_BODY_DOCS = NO INTERNAL_DOCS = NO CASE_SENSE_NAMES = YES HIDE_SCOPE_NAMES = NO SHOW_INCLUDE_FILES = YES INLINE_INFO = YES SORT_MEMBER_DOCS = YES SORT_BRIEF_DOCS = NO SORT_BY_SCOPE_NAME = NO GENERATE_TODOLIST = YES GENERATE_TESTLIST = YES GENERATE_BUGLIST = YES GENERATE_DEPRECATEDLIST= YES ENABLED_SECTIONS = MAX_INITIALIZER_LINES = 30 SHOW_USED_FILES = YES SHOW_DIRECTORIES = YES FILE_VERSION_FILTER = #--------------------------------------------------------------------------- # configuration options related to warning and progress messages #--------------------------------------------------------------------------- QUIET = NO WARNINGS = YES WARN_IF_UNDOCUMENTED = YES WARN_IF_DOC_ERROR = YES WARN_NO_PARAMDOC = YES WARN_FORMAT = WARN_LOGFILE = dox.err #--------------------------------------------------------------------------- # configuration options related to the input files #--------------------------------------------------------------------------- INPUT = ../src INPUT_ENCODING = UTF-8 FILE_PATTERNS = *.c \ *.h RECURSIVE = NO EXCLUDE = lexer.c \ lexer.h \ parser.c \ parser.h \ pplexer.c \ pplexer.h \ static_parser.c \ static_parser.h \ static_lexer.c \ static_lexer.h EXCLUDE_SYMLINKS = NO EXCLUDE_PATTERNS = EXCLUDE_SYMBOLS = EXAMPLE_PATH = EXAMPLE_PATTERNS = EXAMPLE_RECURSIVE = NO IMAGE_PATH = ./devel/img INPUT_FILTER = FILTER_PATTERNS = FILTER_SOURCE_FILES = NO #--------------------------------------------------------------------------- # configuration options related to source browsing #--------------------------------------------------------------------------- SOURCE_BROWSER = NO INLINE_SOURCES = YES STRIP_CODE_COMMENTS = YES REFERENCED_BY_RELATION = YES REFERENCES_RELATION = YES REFERENCES_LINK_SOURCE = YES USE_HTAGS = NO VERBATIM_HEADERS = YES #--------------------------------------------------------------------------- # configuration options related to the alphabetical class index #--------------------------------------------------------------------------- ALPHABETICAL_INDEX = YES COLS_IN_ALPHA_INDEX = 5 IGNORE_PREFIX = #--------------------------------------------------------------------------- # configuration options related to the HTML output #--------------------------------------------------------------------------- GENERATE_HTML = YES HTML_OUTPUT = HTML_FILE_EXTENSION = .html HTML_HEADER = HTML_FOOTER = HTML_STYLESHEET = HTML_ALIGN_MEMBERS = YES GENERATE_HTMLHELP = NO HTML_DYNAMIC_SECTIONS = NO CHM_FILE = HHC_LOCATION = GENERATE_CHI = NO BINARY_TOC = NO TOC_EXPAND = NO DISABLE_INDEX = NO ENUM_VALUES_PER_LINE = 4 GENERATE_TREEVIEW = NO TREEVIEW_WIDTH = 250 #--------------------------------------------------------------------------- # configuration options related to the LaTeX output #--------------------------------------------------------------------------- GENERATE_LATEX = YES LATEX_OUTPUT = LATEX_CMD_NAME = latex MAKEINDEX_CMD_NAME = makeindex COMPACT_LATEX = NO PAPER_TYPE = a4wide EXTRA_PACKAGES = LATEX_HEADER = PDF_HYPERLINKS = NO USE_PDFLATEX = NO LATEX_BATCHMODE = NO LATEX_HIDE_INDICES = NO #--------------------------------------------------------------------------- # configuration options related to the RTF output #--------------------------------------------------------------------------- GENERATE_RTF = NO RTF_OUTPUT = COMPACT_RTF = NO RTF_HYPERLINKS = NO RTF_STYLESHEET_FILE = RTF_EXTENSIONS_FILE = #--------------------------------------------------------------------------- # configuration options related to the man page output #--------------------------------------------------------------------------- GENERATE_MAN = NO MAN_OUTPUT = MAN_EXTENSION = MAN_LINKS = NO #--------------------------------------------------------------------------- # configuration options related to the XML output #--------------------------------------------------------------------------- GENERATE_XML = NO XML_OUTPUT = xml XML_SCHEMA = XML_DTD = XML_PROGRAMLISTING = YES #--------------------------------------------------------------------------- # configuration options for the AutoGen Definitions output #--------------------------------------------------------------------------- GENERATE_AUTOGEN_DEF = NO #--------------------------------------------------------------------------- # configuration options related to the Perl module output #--------------------------------------------------------------------------- GENERATE_PERLMOD = NO PERLMOD_LATEX = NO PERLMOD_PRETTY = YES PERLMOD_MAKEVAR_PREFIX = #--------------------------------------------------------------------------- # Configuration options related to the preprocessor #--------------------------------------------------------------------------- ENABLE_PREPROCESSING = YES MACRO_EXPANSION = NO EXPAND_ONLY_PREDEF = NO SEARCH_INCLUDES = YES INCLUDE_PATH = INCLUDE_FILE_PATTERNS = PREDEFINED = EXPAND_AS_DEFINED = SKIP_FUNCTION_MACROS = YES #--------------------------------------------------------------------------- # Configuration::additions related to external references #--------------------------------------------------------------------------- TAGFILES = GENERATE_TAGFILE = ALLEXTERNALS = NO EXTERNAL_GROUPS = YES PERL_PATH = #--------------------------------------------------------------------------- # Configuration options related to the dot tool #--------------------------------------------------------------------------- CLASS_DIAGRAMS = YES MSCGEN_PATH = /Applications/Doxygen.app/Contents/Resources/ HIDE_UNDOC_RELATIONS = YES HAVE_DOT = NO CLASS_GRAPH = YES COLLABORATION_GRAPH = YES GROUP_GRAPHS = YES UML_LOOK = NO TEMPLATE_RELATIONS = NO INCLUDE_GRAPH = YES INCLUDED_BY_GRAPH = YES CALL_GRAPH = NO CALLER_GRAPH = NO GRAPHICAL_HIERARCHY = YES DIRECTORY_GRAPH = YES DOT_IMAGE_FORMAT = png DOT_PATH = /Applications/Doxygen.app/Contents/Resources/ DOTFILE_DIRS = DOT_GRAPH_MAX_NODES = 50 MAX_DOT_GRAPH_DEPTH = 0 DOT_TRANSPARENT = NO DOT_MULTI_TARGETS = NO GENERATE_LEGEND = YES DOT_CLEANUP = YES #--------------------------------------------------------------------------- # Configuration::additions related to the search engine #--------------------------------------------------------------------------- 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##ÃÉÉ©²²òÁƒdõ[µÂçó===†‰‹‹ëÕ«í8Ñ­+¤¬­­`ÆŒ¥¥¥´ã(TMMÍܹsE"Ñš5k°V!u†­+¤§§çãÇgÎœyòäIÚqgÕªU;wî´··×ÑÑ¡!j°\!¥‘’’âææVYYyþüù)S¦ÐŽ£W®\7n—Ë}ôè.h‹Ôv"¥aoo¿k×.˜={vBBí8r—žžîïïÏ0Ì?þñ¬Uaë )™¹sçž8q¢}ûöIII¦¦¦´ãÈKII‰§§gbbâ!Cnݺ%¿‰RX®’©©©0`@lll¿~ýîܹ£¯¯O;‘ì1 3jÔ¨7n8;;GEEÑN„}؈”Œ¶¶öµk×lllø|þرc…B!íD2&‰¦M›vãÆ:\¹rkB–+¤|ÌÌÌÂÃÃÛ·o÷îÝ€€@@;‘Ì0 3sæÌsçΆ‡‡[[[ÓN„[`¹BJÉÎÎîÖ­[†††dQ¢ÚÚZÚ‰d@(~ùå—¡¡¡úúúaaa8¼!ixï )±ØØØáÇ 2äÂ… mÛ¶¥¨åª««'Mš¦££sûöm5\¼¡Æa¹BÊíÙ³gŸ}öYII‰ƒƒÃÍ›7;wîL;QK¼{÷n„ |>ßÄÄ$,,¬oß¾´!Ä:؈”[Ïž=œœœ^¼xáîî~ûömÚ‰š-66ÖÕÕ•ÏçGFFb­B¨AX®Ò³²²Š‰‰>|x~~þˆ#öìÙ£,} Ãìرƒlè5hР”””=zÐ…Ka¹Bª@[[ûúõëAAA°bÅ //¯—/_Òõ #GŽ\½zummm``à;wTxÖ3B­‡÷®J¹{÷î¤I“ y<Þ† 6nÜÈåri‡ªK,Ÿv.xþüùøñãÝÜÜâââ,,,ÂÂÂ.^¼ˆµ ¡&ÂÖRYB¡000pçÎdÙ‹ &,Z´hèСŠOòèÑ£ààà«W¯2 c``ðí·ß®\¹R%W;DH~°\!WTT´cÇŽ½{÷–••@‡Ö¬Y³xñb]]]y_º¼¼<44ôÈ‘#111 ¥¥µvíÚuëÖéééÉûÒ©,WH->|xß¾}ïß¿çëë;lذٳgkkkËöZ•••aaa.\¸zõjEE˜˜˜|ýõ׫W¯Vêu7¢ ËR#b±øôéÓ¡¡¡·nÝ‹Å ¡¡áçç׫W////--­Ÿ922òáÇwîܹÿ¾d COOÏ… úùùɼ("¤n°\!uTQQqäÈ‘?ÿü322R$‘'555œœœÜÜÜÌÍÍ-,,lllôõõõõõ%=‡ ´´ôǹ¹¹999¯^½JNNNJJzúô)©DŸ>}¦L™biiIáÛCHa¹BjM \ºt)******>>^ºäHãr¹§‘½µ8Ž³³³››ÛèÑ£GŽ‰›T!$sX®úêêêçÏŸ'&&&&&feeåäädee•—————WWW“c´´´ LLL,,,Ú·oß­[·nݺYXX >œ…ó‘R%ÿÕ;áM< ¾ÈIEND®B`‚covered-0.7.10/doc/docbook/0000755000076500007650000000000011475644735015447 5ustar trevorwtrevorwcovered-0.7.10/doc/docbook/catalog.xml0000644000076500007650000000146011352543425017570 0ustar trevorwtrevorw 2 covered-0.7.10/doc/docbook/chapter_attributes.xml0000644000076500007650000002737611352460107022063 0ustar trevorwtrevorw Inline Attributes What are inline attributes? In the IEEE Verilog 1364-2001 standard, an attribute is a way to add information to a Verilog object, statement or groups of statements that is tool-specific and does not affect simulation of that design. All Verilog-2001 attributes begin with the token (* and end with the token *). An attribute can be multi-line and is "attached" to the Verilog object, statement, or group of statements that is specified immediately beneath the attribute. Covered uses the Verilog-2001 attribute for allowing users to specify coverage-specific information about embedded objects within a particular design. When an attribute is found, it is interrogated to see if it is a Covered attribute. If the attribute is a Covered attribute, its contents are parsed. If the attribute is not found to be a Covered attribute, it is ignored and parsing continues normally. The rest of this chapter specifies the attributes that Covered is capable of handling, along with their use and syntax. Adding FSM attributes There are two ways that Covered currently allows the user to specify the location of and information about FSMs embedded in a particular design. The first way to specify an FSM is on the score command-line. The benefit to specifying the location of a state machine this way is that the source code does not need to be modified. The potential disadvantage to this method is that the FSM location and coverage information can get lost if the FSM is used in a different testbench (or even a different project if the FSM code is reused in a later project). For more information on specifying an FSM on the score command-line, please refer to . The second way that an FSM can be specified to Covered is through the use of the Verilog-2001 attribute. The advantages to using this method are that the FSM information specified in an attribute stays embedded in the design (for ease of reusing the FSM and still retaining information relevent to coverage). Additionally, at the current release of Covered, using attributes to specify an FSM is the only way to tell Covered what all of the valid states and state-transitions are for a specific FSM (the command-line specification does not allow for this). This provides a unique advantage of this method over the command-line method. The potential disadvantage of this method for specifying FSM information is that source code needs to be modified. To learn how to specify an FSM attribute within a design, let's use an example of an FSM that is embedded in a design. Module Containing an Embedded FSM This example shows an FSM that has an input FSM variable called "state" and an output FSM variable called "next_state". There are four states in the state machine that are represented with the parameters located in this module (STATE_IDLE, STATE_HEAD, STATE_DATA, STATE_TAIL). There are a total of eight (8) state transitions that this FSM can take. They are the following: STATE_IDLE -> STATE_IDLE (loopback) STATE_IDLE -> STATE_HEAD STATE_HEAD -> STATE_DATA STATE_HEAD -> STATE_TAIL STATE_DATA -> STATE_DATA (loopback) STATE_DATA -> STATE_TAIL STATE_TAIL -> STATE_HEAD STATE_TAIL -> STATE_IDLE All attributes that specify information for an FSM are a comma-separated list of values that contain the following information: "covered_fsm" attribute keyword MUST be first value in the attribute list Specifies to Covered that this attribute contains information for an FSM that Covered needs to handle. FSM identifier MUST be second value in the attribute list Specifies a alphanumeric name for this FSM. The name will eventually be used to tie individual attributes that specify information for the same FSM. Input state expression (optional) Syntax: is="expression" If this is specified, MUST be specified third in the list. Specifies the input state expression. Can be a combination of signal names, signal bit selects, and concatenation operators. See for more information on the specification of an input state expression. Output state expression Syntax: os="expression" If the input state expression is specified, MUST be fourth value in list; otherwise, MUST be third value in list. Specifies the output state expression of the FSM. Can be a combination of signal names, signal bit selects, and concatenation operators. See for more information on the specification of an output state expression. State-transition specifiers (optional) Syntax: trans="from_state->to_state" MUST be specified after the above has been specified in the list. Arguments MUST be constant values (parameters; numerical values -- binary, octal, decimal, hexidecimal; and defines that equate to one of these two types of values). Each transition that is specified is a unique value in the attribute list. You may optionally add characters after the "trans" keyword and before the '=' character (with the exception of the '=' character) to make each transition parameter name unique. Covered will ignore these extra characters, but this can be useful to avoid warning messages that may get emitted from your Verilog compiler when these attributes are parsed (some compilers expect each parameter name in an attribute list to have a unique name). This feature was put in the 0.7.8 stable release. To specify the FSM attribute in the above example, including input state, output state and all state transitions, the code would be modified to look like: FSM Attribute Code Sample STATE_IDLE", trans="STATE_IDLE->STATE_HEAD", trans="STATE_HEAD->STATE_DATA", trans="STATE_HEAD->STATE_TAIL", trans="STATE_DATA->STATE_DATA", trans="STATE_DATA->STATE_TAIL", trans="STATE_TAIL->STATE_HEAD", trans="STATE_TAIL->STATE_IDLE" *) always @(reset or state or head or tail or valid) ... ]]> covered-0.7.10/doc/docbook/chapter_boundaries.xml0000644000076500007650000002415611101717501022014 0ustar trevorwtrevorw Coverage Boundaries To properly evaluate the effectiveness of any coverage tool, it is necessary to understand what kinds of logic are able to be analyzed and which kinds of logic are unable to be analyzed (along with a reason for why the logic cannot be adequately covered). Understanding the limitations of tools up front can often guide the user of those tools to make better decisions in their usage. In the case of Covered and the open source community, it may also help drive ideas to how to correct or get around these limitations. For these reasons, a list of what type of logic can be analyzed and what type of logic cannot be currently analyzed is listed below. Note that both of these lists may not be exhaustive and are subject to change between releases of the tool. Also note that it is the goal of Covered to be able to parse all of the Verilog-1995, Verilog-2001, and a subset of SystemVerilog constructs though some portions of these may be ignored for coverage purposes. What logic can be analyzed? Verilog-1995 constructs All expressional logic which is comprised of the following data types and operators which exist in an assign block, always block, initial block, task, function or named begin/end block: Nets: wire, tri, tri0, tri1, wor, wand, trior, triand, supply0, suppl1 Triregs: trireg Registers: reg Parameter values String values Integer values Unary operators: Arithmetic operators: Logical operators: Relational operators: , <, >=, <=]]> Equality operators: ==, ===, !=, !== Bitwise operators: Shift operators: >]]> Concatentation/replication operators: {}, {{...}} Bit select operators: [], [:] Conditional operator: ?: case, casex, casez statements if, if/else statements Delays when delay value is integer Delayed procedural assignments (i.e., "a = #5 b;" or "a = @(c) b;") Event waits and triggers: wait, @(posedge), @(negedge), @(), -> Repetition statements: for, while, repeat Fork/join statements Memories $finish and $stop system calls $time and $random system functions Real numbers Real number system tasks: $rtoi, $itor, $realtobits, $bitstoreal $test$plusargs system function The following system tasks are allowed within logic blocks being considered for coverage: $display, $dumpall, $dumpfile, $dumpflush, $dumplimit, $dumpvars, $dumpoff, $dumpon, $fdisplay, $fmonitor, $fstrobe, $fwrite, $history, $key, $list, $log, $monitor, $monitoroff, $monitoron, $nokey, $nolog, $printtimescale, $showscopes, $showvariables, $showvars, $strobe, $timeformat, $write Verilog-2001 constructs `ifndef and `elsif directives `file and `line directives Constant functions calls Inline parameter passing by name Localparam support Implicit event sensitivity lists: @* Comma-separated event lists (alternative to the "or" keyword) Signed value support Immediate register assignment (i.e., reg a = 1'b0) Variable multi-bit selects (i.e., a[b+:3], a[b-:3]) Exponential power operator: a**b Arithmetic shift operators: >>]]> Pre-port parameter listing (i.e., module foo #(parameter a=0) (...);) Inline port listing (i.e., module foo (input wire a, output reg b);) Attributes (note: Covered only performs attributes that it recognizes) Arrays of instances Generate blocks "Automatic" or reentrant tasks/recursive functions $value$plusargs system function call The following system tasks are allowed within logic blocks being considered for coverage: $dumpports, $dumpportsall, $dumpportsoff, $dumpportson, $dumpportslimit, $dumpportsflush, $fclose, $ferror, $fflush, $swrite, $swriteb, $swriteh, $swriteo, $ungetc SystemVerilog constructs New integer types: char, byte, bit, logic, int, shortint, longint Op-and-assign statements: >=, <<<=, >>>=, ++, --]]> Proper support for always_comb, always_latch, always_ff, final blocks do..while loops Enumerations Typedefs $root scope support Unnamed scope support Multi-dimensional arrays including packed/unpacked dimensions and bit-select, part-select and slicing Parsing support for unique and priority if/case labels Parsing support for implicit .name ports (i.e., foo f( .a, .b, .c );) Parsing support for implicit .* ports (i.e., foo f( .* );) Parsing support for assertions, properties and sequences Functional support for $urandom, $urandom_range, $srandom, $shortrealtobits, $bitstoshortreal What logic cannot be currently analyzed? Verilog-1995 constructs All gate types (i.e., buf, not, or, and, etc.) All user defined primitives (UDPs) System task calls (or any $... call) that are not mentioned in the supported list above Verilog-2001 constructs Configuration statements What is done with code blocks that contain code that cannot be analyzed? When logic is encountered that cannot be analyzed within an always, initial, task, function or named block, Covered will disregard the entire always block. If the entire block cannot be analyzed, it does not try to get coverage statistics as these will most likely be incorrect (i.e., disregarded logic could affect the state of the logic that is being covered). covered-0.7.10/doc/docbook/chapter_debug.xml0000644000076500007650000004526711207662775021000 0ustar trevorwtrevorw Debugging As much as it pains the developers of Covered to admit, there will be times when a user of Covered will encounter a problem in the resimulation process or will experience a performance issue during certain runs and will want to investigate the issue a bit themselves before posting a bug report. There may also be people out there who just might want to learn more about how Covered operates "under the hood". For those people whom I have just mentioned, this section is for you. Verbose Debug Output The brute force method of understanding Covered's internals is to generate verbose debug output using the global "-D" option to any of Covered's commands. The user of this method should take care to note that using this option may generate an extremely large amount of output and will definitely cause Covered's runtime performance to degrade considerably. If this option is used, its output should probably be redirected to a file for post-processing purposes. It should be noted that the verbose debug output is most useful for the developer's of Covered and is not meant to be of much help to the normal user. Building Covered for Verbose Debug Outputting Because generating verbose debug output can have a tremendous degradation in performance when it is even compiled, Covered requires the user to specify an option to the configuration/build process to enable this feature. To enable verbose debug outputting, simply specify the --enable-debug option to the configure script. This will cause Covered to compile in verbose debug output support and enable the use of the -D global option. If the user has not specified the --enable-debug option to the configuration script but proceeds to specify the -D global option, Covered will emit a warning message that it is unable to output verbose debug information due to the lack of the --enable-debug option being specified. It will then proceed to ignore the -D option. Command-Line Interface (CLI) As an alternative to simply outputting the verbose debug output from Covered, the score command comes equipped with its own interactive debugging mechanism called the CLI (Command-Line Interface). This interface is a command-line driven utility that starts at the beginning of the resimulation. Its purpose is to allow the user to step through simulation execution and view the contents of signals, time, scopes, code and internal thread queues for the purposes of debugging and/or understanding Covered. This utility works much in the same way as simulator CLIs and the GDB debugging utility. Building Covered for the CLI Because interactive command-line debugging has a small performance penalty when compiled in and is closely associated with the verbose debug output option, Covered requires the user to specify an option to the configuation/build process to enable this feature. To enable the CLI, simply specify the --enable-debug option to the configure script. This will cause Covered to compile in CLI capabilities and enable the user of the -cli score command option. Using the CLI To allow the score command to use the CLI for interactive resimulation, simply specify the -cli [filename] option to the score command. If filename is specified to this option, the contents of this file will be parsed and executed once the score command has reached the resimulation process. The contents of this file are a series of CLI commands (one command per line) in ASCII format and can be automatically produced with the "savehist" CLI command (see below). This feature allows a user to quickly save off the CLI commands made during one score run and reuse them in a subsequent score run without having to remember and manually input the same commands. Once the -cli option is invoked, Covered will run the score command until it gets to the beginning of the resimulation process. At this time, if the optional filename is specified, it will parse the contents of this file and execute the CLI commands found there until all commands are executed. If filename was not specified, a prompt will be displayed and the resimulation execution will halt until the user has specified otherwise via command-line options. After entering a command-line option, simply press return to invoke that command. In the event that the command was a step, next or continue option, resimulation will resume until it reaches the next stop point. During resimulation, if the -cli option is specified to the score command, the user may stop simulation at any time by hitting Ctrl-C. This will stop the simulation and display a CLI prompt where the user may continue to interact with the simulation. CLI commands The following is a list of all of the CLI options available to the user: CLI Command-line Options Option Description step [num] Advances to the next statement if num is not specified; otherwise, advances num statements before returning to the CLI prompt. next [num] Advances to the next timestep if num is not specified; otherwise, advances num timesteps before returning to the CLI prompt. goto time num Simulates to the given timestep (or the next timestep after the given value if the timestep is not executed) specified by num. goto line [filename:]num Simulates until the specified line is the next line to be executed. If filename is specified, the line specified by num within that file is the line to stop on. If filename if not specified, the current filename is used. goto expr name bool_op value Simulates until the given expression is evaluated to true where name is the name of a signal in the design to evaluate, bool_op is a boolean operation (i.e., ==, !=, ===, !==, , >=]]>), and value is a legal Verilog value (i.e., 30, 4'h0, etc.). run Runs the simulation to completion. continue Continues running the simulation to completion. thread active Displays the current state of the internal active simulation queue. This queue consists of process threads that will be executed in the current timestep. thread delayed Displays the current state of the internal delayed simulation queue. This queue consists of process threads that will be executed at a later time as dictated by a delay statement. thread waiting Displays the current state of the internal waiting simulation queue. This queue consists of process threads that are not active or delayed but may be activated by a value change in one of the signals in its expression tree. thread all Displays the current state of all process threads in the simulator. current Displays the current scope, block, filename and line number of the statement that is about to be executed in the active queue. time Displays the current simulation time. signal name Displays the current value of the given net/variable. expr num Displays the given expression and its current value where num is the ID of the expression to output. debug [less | more | off] Specifies the amount of debug information that is output during simulation. The value of 'less' only outputs the current statement that is being executed (along with line number). The value of 'more' outputs verbose output that is really only useful for the developer's of Covered. The value of 'off' turns off all debug output during simulation. If 'less', 'more', or 'off' is not specified, displays the current debug mode. list [num] Lists the contents of the file where the current statement is to be executed. If num is specified, outputs the given number of lines; otherwise, outputs 10 lines. savehist filename Saves the current history to the specified file. history [(num | all)] Displays the last 10 lines of command-line history. If 'all' is specified, the entire history contents will be displayed. If num is specified, the last num commands will be displayed. !num Executes the command at the num position in history. !! Executes the last valid command. help Displays the available command-line options. quit Ends simulation immediately.
Source Code Profiling The built-in source code profiling facility allows the user to run any Covered command and understand performance metrics about the internal Covered source code, such as how many times a given function was called, how much wall-clock time was spent executing a given function, how many times a function allocated and deallocated memory from the heap, etc. This information can be useful in understanding where performance bottlenecks are during a given Covered command run. This feature does not provide the end-user any useful information about the design that they are testing. Building Covered for Profiling Because internal source code profiling is not a function of obtaining Verilog code coverage and adds a performance penalty for being compiled in and used, Covered requires the user to specify an option to the configuration/build process to enable this feature. To enable internal source code profiling, simply specify the --enable-profiling option to the configure script. This will cause Covered to compile in profiling capabilities and enable the use of the -P global option. If the user has not specified the --enable-profiling option to the configuration script but proceeds to specify the -P global option, Covered will emit a warning message that it is unable to do profiling due to the lack of the --enable-profiling option being specified. It will then proceed to ignore the -P option. Using Source Code Profiling Once Covered has had profiling functionality configured and built into it, the user may optionally enable profiling for any command by specifying the -P [filename] global option. If the -P option is specified without a filename associated with it, the profiling report generated from the command run will be output to a file called "covered.prof" in the same directory where Covered was run. If a filename is associated with the -P option, the contents of the profiling report will be output to that file. The specified filename can be anything except "score", "merge" or "report" as this name will be interpreted by Covered's command-line parser to indicate the type of command being run. If one of these command keywords are specified after the -P option, it is assumed that the user has not specified a filename and the contents of the profiling report will be sent to the default file of "covered.prof". Understanding the Profiling Report After a command has been run with the global -P option specified, a report file will contain several profiling statistics, including the following: The amount of time spent running the entire command The number of times each executed function was called The total amount of wall clock time spent executing each function The average amount of time spent executing each function The number of times each function allocated heap memory The number of times each function deallocated heap memory In addition to providing this information on a per function basis, the profiling report also provides the information in three different sections with each function ordered from most to least by the following statistic columns: The number of times each executed function was called The total amount of wall clock time spent executing each function The average amount of time spent executing each function By ordering this information, it will help the users and developers determine where the performance bottlenecks in execution are for a given command run. covered-0.7.10/doc/docbook/chapter_epilogue.xml0000644000076500007650000006313711472127327021510 0ustar trevorwtrevorw Epilogue Author Covered is programmed and documented by Trevor Williams (phase1geo@gmail.com) Special Thanks I would like to acknowledge certain individuals for their help in making Covered the tool that it is today. Ed Spittles - Thank you for your tireless efforts in logging bugs, providing suggestions on enhancements/optimizations (including the tip on using of FIFOs to replace VCD/LXT2/FST file usage), your input into scoring optimizations for vectors and CDD ranking, and for allowing me access to needed information for fixing those "hard to reproduce" bugs. Clifford E. Cummings - provided race condition checking rules and clarifications about those rules. Stephen Williams - Thanks for helping me understand some of the ins and outs of what's required "under the hood" to handle some of Verilog's constructs. Daniel McMahill - testing and patches for 64-bit compatibility Reporting Bugs If you have read this user's guide, chances are that you might be a Covered user. As such, it is encouraged that any bugs that you might find while using Covered get reported so that this project may become more stable for yourself and for other users. To submit a bug report or a request for enhancement, you may either send an e-mail to Trevor Williams (see or, if you have a SourceForge login, can report a bug by going to: http://sourceforge.net/projects/covered and clicking on the "Bugs" link. Mailing List The Covered project has a user mailing list. Whenever there are stable releases being made of the project, an e-mail will get sent out to this list stating the new release is available. Additionally, the mailing list is a great way to bring up usability issues with the tool and, of course, bugs. The mailing list can also be useful if you have a question about using Covered -- there is probably someone else who has encountered the same problem that might be able to provide you with some help. To subscribe to this e-mail list, please visit the following URL, enter the prescribed information and click on the "Submit" button. http://lists.sourceforge.net/lists/listinfo/covered-users Homepage The Covered project homepage is established on SourceForge at the following URL address. http://covered.sourceforge.net Copyright and Licensing This program is distributed under the GNU Public License GPL. GNU GENERAL PUBLIC LICENSE Version 2, June 1991 Copyright (C) 1989, 1991 Free Software Foundation, Inc. 675 Mass Ave, Cambridge, MA 02139, USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. Preamble The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software-to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Library General Public License instead.) You can apply it to your programs, too. When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it. For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights. We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software. Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations. Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all. The precise terms and conditions for copying, distribution and modification follow. Terms and Conditions for Copying, Distribution, and Modification [0.] This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The ``Program'', below, refers to any such program or work, and a ``work based on the Program'' means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term ``modification''.) Each licensee is addressed as ``you''. Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does. [1.] You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. [2.] You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: [a.] You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change. [b.] You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License. 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If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code. [4.] You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. [5.] You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it. [6.] Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License. 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[8.] If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. [9.] The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and ``any later version'', you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. [10.] If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. NO WARRANTY [11.] BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM ``AS IS'' WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. [12.] IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. END OF TERMS AND CONDITIONS Appendix: How to Apply These Terms to Your New Programs If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the ``copyright'' line and a pointer to where the full notice is found.
Copyright © 20yy This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
covered-0.7.10/doc/docbook/chapter_exclude.xml0000644000076500007650000001020611061140436021303 0ustar trevorwtrevorw The exclude Command The exclude command allows the user to exclude uncovered coverage points from coverage (effectively turning the uncovered points into covered points) or include coverage points that were previously excluded. Additionally, the exclude command allows the user to specify a reason why the coverage point is being excluded. This capability allows for good documentation of these coverage points for later evaluation and can be output into various report formats to go along with a verification testplan. Usage The exclude command is specified with the given call: covered [global options] exclude [options] exclusion ID+ CDD file The exclusion ID information can be obtained via a Covered report command call with the -d (d|v) and -e options. Exclusion IDs consist of an alphanumeric value that will be specified with parenthesis prior to a coverage point. You may specify one or more exclusion IDs per call to the exclude command. If the -m option is specified, a prompt will be specified for each exclusion ID, individually. If a coverage point is currently included in the CDD prior to an exclude call, the coverage point will be toggled to be excluded and a user message can be attached to the coverage point, specifying the reason for exclusion. If a coverage point is currently excluded in the CDD prior to an exclude call, the coverage point will be toggled to be included and any previouly assigned user message will be forgotten. Options Options to the exclude command Option Description -f filename Allows the user to specify a file that contains additional exclude command options to parse. This option may be specified more than once for a single call to the exclude command. -h Displays help information for the exclude command. -m Allows a user message specifying the reason for excluding any coverage points being excluded on the command-line. An interactive prompt will be specified in the shell. Simply enter your reason at the prompt, hit return and specify a single period (.) character followed by a return to end the user input for a coverage point. You may use as many lines of text that you would like; however, all formatting characters (i.e., newlines, tabs, extra spaces, etc.) will be removed when reporting the information. -p Outputs the current exclusion status of the specified exclusion ID(s) and displays any exclusion reason messages associated with the specified exclusion ID(s) to standard output.
covered-0.7.10/doc/docbook/chapter_faq.xml0000644000076500007650000002256611472127327020447 0ustar trevorwtrevorw FAQ This page contains a list of accummulated Frequently Asked Questions. If you are having difficulties using Covered or have questions that are not answered in the User's Guide, please check this list for answers. If you do not find the information that you are looking for in the User's Guide or this FAQ, please send an e-mail to: phase1geo@gmail.com Is a CDD file generated from a newer version of Covered compatible with a CDD file generated from an older version? The answer to this question is, "Well, that depends...". Since the format of the CDD file is only used by Covered, the contents and format of this file may be changed to suit the needs of Covered. This means that it is possible for a CDD file created from an older version of Covered to be incompatible with a newer version. Additionally, the developers of Covered will not make any attempts to make sure that older CDD files can be properly read by a newer version of Covered. It is suggested that any CDD files generated from a particular version of Covered be merged and/or reported on by that same version, and if Covered is upgraded, new CDD files should be generated. This being said, it is also a possibility that between versions of Covered a "backwards compatibility" may be maintained if a change to this file's format is not required. When I run the score command, Covered seems to take a long time to run. Is there anything that I can do to speed up scoring? While Covered is continuously being enhanced to provide better performance for all commands (especially the score command), it may still take a while to complete scoring if one or more of the following is true: The design being scored is sufficiently large The VCD/LXT2/FST dumpfile is sufficiently large The VCD/LXT2/FST dumpfile contains dump information for a part of the design not being scored When Covered was configured, the --enable-debug and/or --enable-profiling options were specified If reason (1) is true, speeding up each run can be achieved by one of the following suggestions: Reduce the scored design in size by eliminating modules or constructs from its design tree. (See for more information on how to accomplish this) Split up the design into smaller parts along module boundaries and generate coverage for those parts. It is not currently possible to append these modules into one file. Merging and reporting must be done on these smaller pieces independently from one another. If reason (2) is true, nothing can be done except to shorten the run time of the diagnostics to produce shorter dumpfiles. If reason (3) is true, the $dumpvars call in the simulator should be modified to only generate VCD/LXT2/FST dump information for the modules included in scoring. If there are modules not being scored which are included in the $dumpvars calls, please remove these unnecessary modules from dumpfile output. If reason (4) is true, Covered should be reconfigured without these options specified. The debugging and profiling facilities are enormous performance degraders and immediate simulation performance enhancement will be seen if Covered is rebuilt without these options specified. If you believe that you have a situation which is void of these prevailing reasons and Covered is still running slowly, please send an e-mail to me. I will consider these problems to be of lower priority than actual bugs but will look into the situation to see where code can be optimized. I get an assertion error when running Covered, what should I do? Covered uses C assertions to make sure that internal pointers are not be referenced when NULL and that certain internal situations do not arise. If you receive some type of assertion error when running Covered, it means that something went wrong internally in Covered. The error is NOT due to user error. Please submit a bug report containing the assertion error message, file and line number. Additionally, run the Covered command with the -D global option (covered -D command) and provide the output from doing this with the bug report (please only specify tail of output if the output is too lengthy). If Covered provides any other type of error message (something other than a core dump), Covered has found a user error that must be fixed by the user. Please do not submit bug reports if these errors are encountered, unless you wish to add a question about it to the FAQ. Covered is giving me a parser error for Verilog code that seems to be syntactically correct. What is wrong? If Covered displays a syntax (parse) error during the score command and the Verilog code is written correctly, it is because Covered's parser is incomplete. Please submit a bug or send an e-mail containing a code snippet of the unsupported Verilog. Is Covered's Verilog parser Verilog-2001 compliant? This is currently being worked on. The parser should properly parse all code; however, not all Verilog-2001 constructs are considered for coverage due to lack of support for them in Covered's core. If there is code that will not parse that should, please submit a bug report for this. What is the difference between the stable release and the development release? Covered's development consists of two active "branches": the stable branch and the development branch. When a new stable branch is created (ex. 0.4 or 0.5), it represents the latest version of the development branch. As Covered's development branch is worked on (adding new features, changes to the core, etc.), the stable branch remains in a feature frozen stage. Only bug fixes, documentation updates or minor enhancements (changes that will not affect the core code) are made to the stable branch. When a number of these changes have been accumulated on the stable branch, a snapshot of the stable branch is made available for public download (ex. 0.4.1). User's of the stable release should expect no major feature changes from minor rev to minor rev and should expect a somewhat polished version of the project (few if any bugs and correct user documentation). User's of the development releases should expect to see more bugs and fewer documentation consistencies (although an attempt is made to minimize both) but should expect lots of feature additions, optimizations, improvements, etc. from release to release. Bug findings found in the stable release are applied to the development branch when applicable. It is important to note that both the stable and development releases contain a regression testbench that must fully pass before either release is made. This should minimize bugs in both releases and give user's of either branch a level of confidence that the release is usable. covered-0.7.10/doc/docbook/chapter_gui.xml0000644000076500007650000000504411054713225020446 0ustar trevorwtrevorw Introduction to the GUI The Covered report viewer GUI allows a user to view the coverage results from one or more CDD (Covered Design Database) files that have been previously generated using the Covered score and/or merge commands. The advantages of using the GUI versus using an ASCII file to view coverage results are the following: View code that is covered/uncovered within the actual source file text (more context) Quickly see which modules/instances were uncovered for each coverage metric. Ability to hide/unhide verbose information for uncovered code. Quickly find expressions that caused combinational logic cases to be uncovered. Allows user to focus on a particular expression/signal/module/instance that is uncovered. Non-useful coverage cases can be interactively excluded/included and summary information automatically recalculated. Because the nature of a GUI interface is much more interactive than a generated text file report, the Covered report viewer is meant to provide the user a more in-depth look at the logic to identify the reasons for not achieving full coverage. This is the ultimate goal of the GUI interface -- to be an interactive tool for identifying and understanding why full code coverage was not achieved and how to write tests that will cover those areas. The GUI report viewer is invoked by specifying the '-view' option to the Covered report command. The report viewer is part of the report command and is, therefore, not used to parse/score a design. However, merging maytake place with the GUI as multiple CDD files may be read, merged (assumingall of the CDD files came from the same DUT) and saved in CDD file format. The rest of the user manual pages describe the various widgets and windows of the GUI and their functionality. Additionally, this user manual contains information on how to get the most out of the Covered GUI report viewer. covered-0.7.10/doc/docbook/chapter_gui_assert.xml0000644000076500007650000001672011061564253022035 0ustar trevorwtrevorw Navigating the Assertion Coverage Window The Verbose Assertion Coverage window allows the user to see exactly which coverage points were hit or missed for a selected assertion instantiation in the design and, if hit, how many times the assertion coverage point (ACP) was hit during simulation. Additionally, this window allows you to bring up the verbose assertion window to view the internal assertion module code for the currently selected assertion instance. This lets the user view the code to determine what logically needs to occur to hit a given ACP. To view this window, select the "Assert" mode in the coverage bar in the main window and click on an underlined assertion instance name in the file viewer. Note that both covered and uncovered assertion instance names can be selected. Doing so will cause the Verbose Assertion Coverage Window to be displayed for the selected assertion instantiation. shows an example of a zero_one_hot assertion that had the "test_expr_change covered" ACP covered (hit twice during simulation) and the other two ACPs uncovered during simulation.
Verbose Assertion Coverage Window
Navigating the Assertion Coverage Window The window is made up of a simple table which contains the coverage point names within the selected assertion on the left and the number of times each of these coverage points were hit during simulation on the right. If a coverage point has not been hit, both the coverage point name and the number of hits (0) will be highlighted with the "uncovered" color selection as selected in the preferences window. If a coverage point has been hit at least once, both the coverage point name and the number of hits will be highlighted with the "covered" color selection as selected in the Preferences window. Below the table the name of the currently selected assertion type is named. To view the source code for this assertion, simply click on the Show Code button at the bottom right-hand portion of the coverage table. This will cause the source code for this assertion to be displayed in a new assertion source viewer. To exit this window, simply click on Close button. To see this help page for the assertion coverage window, click on the help (?) button. Excluding/Including Assertion Coverage Points Individual ACPs can be excluded/included for coverage consideration using the verbose assertion coverage window. This is accomplished by clicking on the "0" (ACP is currently included in coverage) or "E" (ACP is current excluded from coverage) value in the "# of hits" column. Changing an ACP from "0" to "E" (excluding the ACP from coverage consideration) will cause the exclusion reason popup window to be displayed, allowing you to specify a reason for excluding the ACP. Once a reason has been entered, the summary assertion coverage information to be recalculated and redisplayed in the listbox and the background color of the ACP will change from the uncovered to the covered background color. Changing an ACP from "E" to "0" (including the ACP for coverage consideration) will cause the summary assertion coverage information to be recalculated and redisplayed in the Main Window Summary Bar and background color of the ACP will change from the covered to the uncovered background color. below shows the above assertion instance with the last coverage point excluded from coverage.
Example of excluded ACP
If all ACPs for a given assertion instance have been excluded from coverage consideration, the file viewer will automatically change the background color of the assertion instance name from the uncovered to the covered background color. The assertion instance name will still be underlined, allowing the user to still see the coverage information for that given assertion instance. If the user excludes any ACP in the design, the Save CDD... option in the file menu will be enabled. This allows the user to save the excluded property either back to the CDD file (or to a newly named CDD file). Doing so will allow the user to load the CDD file at a different time and retain the knowledge of which ACPs have been excluded/included for coverage along with any specified reasons for exclusion. Additionally, if a saved CDD file with coverage exclusion is merged with another CDD file, the excluded ACP information is preserved for the resulting merged CDD file. If an ACP has been excluded from coverage and an exclusion reason was specified, you can view the reason for exclusion by right-click-and-holding on the "E" next to the ACP. This will cause a tooltip-style window to be displayed specifying the reason for exclusion. The background color of the tooltip will be the same color as the "covered" background color to help distinguish it from a normal tooltip. To cause the exclusion reason tooltip to disappear, simply release the button. Displaying a New Assertion Instance If the Verbose Assertion Coverage window is currently displayed, the user may select a new assertion in the file viewer of the Main window. When a new assertion is selected, its information immediately replaces the currently selected assertion. This feature allows many different assertions to be viewed one after the other without having to create/destroy a new window for each. The user may also see the previous or next uncovered assertion in the main viewer by clicking either the left arrow button (for previous signal viewing) or the right arrow button (for next signal viewing). Note that the left arrow button will be disabled if there is not a signal previous to the current signal in the given module and the right arrow button will be disabled if there is not a signal after the current signal in the given module. covered-0.7.10/doc/docbook/chapter_gui_assert_src.xml0000644000076500007650000000421511055051326022673 0ustar trevorwtrevorw Navigating the Assertion Source Code Window The Assertion Source Viewer window allows the user to see the source code for the current assertion in the verbose assertion window. To view this window, simply click the Show Code button in the Verbose Assertion Coverage window. shows a zero_one_hot OVL assertion code with syntax highlighting applied.
Assertion Source Viewer Window
Navigating the Source Code The source code for the current assertion will be automatically displayed in the text viewer when the window is created. However, the source code will be displayed as it is found in the file system, without preprocessing applied to it. This means that included files will not be displayed in an in-lined fashion. To view included files, simply click on the included filename (it will be underlined). This will cause the included file to replace its includer in the text viewer. An infinite number of includes may be traversed in this manner. To go back to the file that included the current file, simply click on the Back button located in the bottom left-hand corner of the window. This will cause the current source code to be replaced with its "parent" source code. Note that the Back button will be disabled when the top-level assertion file is currently displayed. To exit this window, simply click on Close button. To see this help page for the assertion source code window, click on the help (?) button. covered-0.7.10/doc/docbook/chapter_gui_exclude.xml0000644000076500007650000000556411061140436022162 0ustar trevorwtrevorw The Exclusion Reason Popup Window When an uncovered coverage point needs to be excluded for various reasons, a user-supplied message may be associated with the exclusion, specifying the reason for the exclusion. This information can be useful documentation for a coverage analysis and is possible to achieve using the Covered GUI. This task is accomplished with the exclusion reason popup window which is automatically popped up when a coverage point is marked for exclusion (assuming that the capability is enabled in the exclusion preferences pane). shows what this popup window looks like.
The Exclusion Reason Popup Window
To specify an exclusion reason, you may do either enter the exclusion reason into the textbox located on the left side of this window or you may select a pre-created, general purpose exclusion reason in the drop-down table. To view this table, click on the down arrow button at the bottom of this window (see ). To hide this table, click on the same button (which will be changed to an up arrow button). If a general-purpose exclusion reason is selected from the table, it will be displayed in the top textbox where it may be optionally edited for the current coverage point.
Full View of the Exclusion Reason Popup Window
Once the exclusion reason has been entered as desired in the textbox (please note that any formatting characters such as newlines, tabs and/or multiple spaces will be automatically removed and replaced with a single space character), simply click on the OK button which will associate the exclusion reason with the excluded coverage point and close the popup window. Note that the OK button will only be enabled if at least one character is entered in the textbox. Editing a general purpose reason in the popup window only has an effect for this coverage point; it does not change the general purpose reason value itself (this can only be done in the preferences window). To not specify an exclusion reason with an excluded coverage point, simply click on the Cancel button. covered-0.7.10/doc/docbook/chapter_gui_fsm.xml0000644000076500007650000002121011061646413021306 0ustar trevorwtrevorw Navigating the FSM State/State Transition Coverage Window The Verbose FSM State/State Transition Coverage window allows the user to see which states and state transitions of a currently selected FSM have been covered or are uncovered. To view this window, simply select the "FSM" coverage metric mode in the coverage bar in the main window and select an underlined FSM state variable in the file viewer. This will cause the FSM Coverage window to be displayed with the currently selected FSM information loaded. below shows an example of this window.
Verbose FSM Coverage Window
Navigating the FSM Window The Verbose FSM window is split into two main frames. The top frame contains the expressions that make up the input and output states of the selected FSM. The bottom frame contains a two-dimensional table showing the covered and/or uncovered states and state transitions. The state/state transition table is a two-dimensional table with all possible values of the input states in the left-most column, the output states in the upper-most row, and the state transitions in the rest of the table. To determine which states have been uncovered in the table, simply find all state values in the input column or output row (both show the same information) which are highlighted with the "Uncovered" color selection specified in the preferences window. To determine which states have been covered in the table, simply find all state values in the input column or output row which are highlighted with the "Covered" color selection. All other state values which are not highlighted are either impossible values (if all of the state transitions were specified in the Verilog file) or are unknown for coverage (if not all of the state transitions were specified in the Verilog file). To determine which state transitions have been uncovered in the table, simply find all empty boxes in the table that are highlighted with the "Uncovered" background color. If one of these exist, it specifies that the transition of "input state" (the value specified in the left-most column in the same row) to "output state" (the value specified in the upper-most row in the same column) did not occur. In the example above, we can see that the following state transitions did not occur: 2 -> 4 4 -> 1 Follow the same procedure for finding all covered state transitions in the table except that these boxes will be highlighted with the "Covered" background color. In the example above, we can see that the following state transitions occurred: 1 -> 2 1 -> 1 (loopback case) 2 -> 2 (loopback case) All other state transition boxes that are not highlighted are either impossible state transitions (if all state transitions were specified in the Verilog source code) or are unknown in their coverage (either not hit or impossible transition if all state transitions were not specified in the Verilog source code). To exit this window, simply click on Close button. To see this help page for the FSM window, click on the help (?) button. Excluding/Including a State Transition Uncovered state transitions can be excluded/included for FSM coverage consideration. This is done by clicking on the "I" (state transition is currently included in coverage results) or "E" (state transition is currently excluded from coverage results) character in the middle of a state transition square. Changing a state transition from an "I" to an "E" will automatically cause a exclusion reason popup window to be displayed, allowing you to specify the reason for excluding this state transition. After a reason has been entered, the state transition summary coverage information in the listbox to be updated and the background color of the state transition box will change from the uncovered color to the covered color. Changing a state transition from an "E" to an "I" will automatically cause the state transition summary coverage information in the Main Window Summary Bar to be updated and the background color of the state transition box will change from the covered color to the uncovered color. below shows an example of the state machine coverage information with a couple of state transitions excluded from coverage.
Example of excluded state transitions
If all of the state transitions for a state machine have been excluded for coverage consideration, the output state variable in the file viewer will change its background from the uncovered to the covered background color. However, the underline will remain under the variable to allow the user to still examine the verbose FSM information for that state machine. If the user excludes any state transition in the design, the Save CDD... option in the file menu will be enabled. This allows the user to save the excluded property either back to the CDD file (or to a newly named CDD file). Doing so will allow the user to load the CDD file at a different time and retain the knowledge of which state transitions have been excluded/included for coverage. Additionally, if a saved CDD file with coverage exclusion is merged with another CDD file, the excluded state transition information is preserved for the resulting merged CDD file. If a state transition has been excluded from coverage and an exclusion reason was specified, you can view the reason for exclusion by moving the cursor over the state transition. This will cause a tooltip-style window to be displayed specifying the state transition and the reason for exclusion. The background color of the tooltip will be the same color as the "covered" background color to help distinguish it from a normal tooltip. To cause the exclusion reason tooltip to disappear, simply move the cursor off of the state transition cell. Displaying a New FSM If the Verbose FSM Coverage window is currently displayed, the user may select a new FSM state variable in the file viewer of the Main window. When a new FSM is selected, its information immediately replaces the currently selected FSM. This feature allows many different FSMs to be viewed one after the other without having to create/destroy a new window for each. The user may also see the previous or next uncovered FSM in the main viewer by clicking either the left arrow button (for previous signal viewing) or the right arrow button (for next signal viewing). Note that the left arrow button will be disabled if there is not a signal previous to the current signal in the given module and the right arrow button will be disabled if there is not a signal after the current signal in the given module. covered-0.7.10/doc/docbook/chapter_gui_intro.xml0000644000076500007650000000511411054713225021657 0ustar trevorwtrevorw Introduction to the GUI The Covered report viewer GUI allows a user to view the coverage results from one or more CDD (Covered Design Database) files that have been previously generated using the Covered score and/or merge commands. The advantages of using the GUI versus using an ASCII file to view coverage results are the following: View code that is covered/uncovered within the actual source file text (more context) Quickly see which modules/instances were uncovered for each coverage metric. Ability to hide/unhide verbose information for uncovered code. Quickly find expressions that caused combinational logic cases to be uncovered. Allows user to focus on a particular expression/signal/module/instance that is uncovered. Non-useful coverage cases can be interactively excluded/included and summary information automatically recalculated. Because the nature of a GUI interface is much more interactive than a generated text file report, the Covered report viewer is meant to provide the user a more in-depth look at the logic to identify the reasons for not achieving full coverage. This is the ultimate goal of the GUI interface -- to be an interactive tool for identifying and understanding why full code coverage was not achieved and how to write tests that will cover those areas. The GUI report viewer is invoked by specifying the -view option to the Covered report command. The report viewer is part of the report command and is, therefore, not used to parse/score a design. However, merging maytake place with the GUI as multiple CDD files may be read, merged (assuming all of the CDD files came from the same DUT) and saved in CDD file format. The rest of the user manual pages describe the various widgets and windows of the GUI and their functionality. Additionally, this user manual contains information on how to get the most out of the Covered GUI report viewer. covered-0.7.10/doc/docbook/chapter_gui_line.xml0000644000076500007650000002135011061564253021456 0ustar trevorwtrevorw Navigating the Line Coverage Window Line coverage is the quickest way to determine what logic in your design is being exercised and which logic has not be exercised during simulation. If a line was found to not be simulated, this is an indication that there was some event that did not occur or did not occur at the proper time to cause a previous conditional expression to be evaluated to true or false. For example, if a block of code looked something like: Line Coverage Example If line 3 was shown to be not covered, this would indicate that at the positive edge of the term "clock", the value of "a" never evaluated to a value of 1 (true). To make line 3 become covered, we would need to setup a situation in the diagnostic that caused "a" to become true at the positive edge of the term "clock". On the other hand, if all lines 2 - 5 were found to be uncovered, this would indicate the the term "clock" never made a transition from some value to a 1 (true) value during simulation. Viewing Uncovered Lines To view line coverage for all uncovered lines for a specific module/instance, do the following: Make sure that the Show Uncovered menu item in the report menu is selected. Select the line coverage metric in the coverage bar by left-clicking on selection button to the left of "Line". Select one of the modules/instances that is highlighted in the uncovered color scheme (to change this color scheme, see ) in the listbox. This will cause the selected module/instance source code to be displayed in the file viewer. Once the selected module/instance has been displayed, scroll down in the Coverage File Viewer window (using the scroll bars to the right and below the Coverage File Viewer window) until you have reached a line that is highlighted in the uncovered color scheme. The line number of the highlighted line will be printed to the left of the source code line. This line represents a line that was found to not be hit during the simulation of this module/instance. Excluding/Included Uncovered Lines from Line Coverage Any uncovered line in the design may be included/excluded from coverage consideration. To the left of each uncovered line is an underlined "I" (line is currently included in coverage) or "E" (line is currently excluded in coverage). Clicking on an "I" will cause a exclusion reason popup window to be displayed, allowing you to specify a reason for excluding this line. Once a reason has been entered, the coverage exclusion property of the line will change to an "E" and be highlighted in the "covered" color scheme and the summary line coverage information will be recalculated and redisplayed in the listbox to reflect the current status of line coverage for the current module/instance. Clicking on an "E" will cause the current line to be displayed in the "uncovered" color scheme, the "E" will change to an "I", and the summary line coverage will be recalculated and redisplayed in the summary listbox. shows an uncovered line that is included for coverage consideration. shows the same line which is now excluded from coverage consideration.
Example of uncovered line included for line coverage consideration
Example of uncovered line excluded for line coverage consideration
In addition to changing the line coverage information, the combinational logic coverage information for an uncovered statement on that line will also be implicitly excluded from coverage (though the exclude properties for each subexpression of the statement will not change). If the user excludes any line in the design, the Save CDD... option in the file menu will be enabled. This allows the user to save the excluded property either back to the CDD file (or to a newly named CDD file). Doing so will allow the user to load the CDD file at a different time and retain the knowledge of which lines have been excluded/included for coverage. Additionally, if a saved CDD file with coverage exclusion is merged with another CDD file, the excluded line information is preserved for the resulting merged CDD file. If a line has been excluded from coverage and an exclusion reason was specified, you can view the reason for exclusion by right-click-and-hold on the "E" on the desired line. This will cause a tooltip-style window to be displayed specifying the reason for exclusion. The background color of the tooltip will be the same color as the "covered" background color to help distinguish it from a normal tooltip. To cause the exclusion reason tooltip to disappear, simply release the button. Viewing Covered Lines To view line coverage for all covered lines for a specific module/instance, do the following: Make sure that the Show Covered menu item in the report menu is selected. Select the line coverage metric in the coverage bar by left-clicking on the selection button to the left of "Line". Select one of the modules/instances in the listbox that shows that at least one line was considered coverable by Covered. Once the selected module/instance has been displayed, scroll down in the Coverage File Viewer window (using the scroll bars to the right and below the Coverage File Viewer window) until you have reached a line that is highlighted in the covered color scheme. The line number of the highlighted line will be printed to the left of the source code line. This line represents a line that was found to be hit during the simulation of this module/instance. You may see both the covered and uncovered line coverage simultaneously by selecting both the Show Uncovered and Show Covered items in the Report menu. This is sometimes useful to see what logic Covered was not able to provide coverage support for (all lines which contain code that are not highlighted in either the uncovered or covered color schemes). covered-0.7.10/doc/docbook/chapter_gui_logic.xml0000644000076500007650000005257111061564253021635 0ustar trevorwtrevorw Navigating the Combinational Logic Window The Verbose Combinational Logic viewer allows the user to look at the subexpressions of a selected statement to determine exactly why a statement did not achieve 100% coverage. The window is split up into two text frames. The top frame displays the selected statement, underlining and numbering subexpressions that were found to not achieve full coverage. The bottom frame displays which combinations of a selected subexpression were hit/missed, allowing the user to discern which combinations of logic are still in need of verification. Figure 1 shows the verbose combination logic window.
Example of the verbose combinational logic window
Navigating a Statement To understand what subexpressions of a statement caused it to not achieve 100% coverage, the viewer window allows the user to traverse uncovered subexpressions, displaying the coverage information for each subexpression in the lower frame. To see an uncovered subexpression in the lower frame, simply click the left mouse on the underlined subexpression. If the subexpression has one or more children subexpressions, these will be individually underlined and numbered. If the subexpression is a leaf subexpression of the statement, only its coverage information will be displayed in the lower pane. To traverse upward in a subexpression, simply click the right mouse button on the underlined subexpression. This will cause the parent subexpression to be underlined and its parent (if one exists) will have its coverage information displayed in the lower frame. To exit this window, simply click on Close button. To see this help page for the combinational logic window, click on the help (?) button. Understanding the Coverage Information The coverage information for a selected subexpression can be one of four different types: Event Subexpression These subexpressions do not have any children expressions. Their coverage is in terms of: Did this event occur? The following operators are considered events: At-event operators: @(posedge expression) @(negedge expression) @(expression) @* Event trigger operator: -> event_variable
Example Coverage Output for an Uncovered Event Subexpression
In this diagram, we see that a certain @(posedge clock) expression never occured. Unary Subexpression These subexpressions do not have any children expressions. Their coverage is in terms of: Did this expression evaluate to a value of 0? Did this expression evaluate to a non-zero value? The following operators are considered unary subexpressions: Signal/Bit Selectors: signal_value signal_value[expression] signal_value[value:value] signal_value[expression+:value] signal_value[expression-:value] Function call: function_name( ... ) Relational operators: !expression expression expression expression ]]> expression expression expression expression =]]> expression expression == expression expression != expression expression === expression expression !== expression Shift operators: expression value expression >]]> value expression value expression >>]]> value Conditional operator: expression ? expression : expression Unary operators: expression expression |expression ^expression expression ~|expression ~^expression Concatenation operators: {value{expression} } {expression, expression, ... } Case equality
Example Coverage Output for an Uncovered Unary Subexpression
Simple Combinational Subexpression These subexpressions have two child expressions (L=left and R=right). There are three flavors of simple combinational subexpressions: AND-type, OR-type and other. The differences are explained below. Simple AND-type Combinational Subexpressions These subexpressions have three possible combinational outcomes: Did the left expression evaluate to 0? Did the right expression evaluate to 0? Did the left expression evaluate to 1 when the right expression evaluated to 1? The following operators are considered simple AND-like combinational subexpressions: Logical operators: expression expression expression expression expression expression
Example Coverage Output for an Uncovered Simple AND-type Combinational Subexpression
Simple OR-type Combinational Subexpressions These subexpressions have three possible combinational outcomes: Did the left expression evaluate to 1? Did the right expression evaluate to 1? Did the left expression evaluate to 0 when the right expression evaluated to 0? The following operators are considered simple OR-like combinational subexpressions: Logical operators expression | expression expression ~| expression expression || expression
Example Coverage Output for an Uncovered Simple OR-type Combinational Subexpression
Simple Other-type Combinational Subexpressions These subexpressions have four possible combinational outcomes: Did the left expression evaluate to 0 when the right expression evaluated to 0? Did the left expression evaluate to 0 when the right expression evaluated to 1? Did the left expression evaluate to 1 when the right expression evaluated to 0? Did the left expression evaluate to 1 when the right expression evaluated to 1? The following operators are considered simple combinational subexpressions: Mathematical operators: expression + expression expression - expression Logical operators: expression ^ expression expression ~^ expression
Example Coverage Output for an Uncovered Simple Combinational Subexpression
Complex Combinational Subexpression These subexpression have three or more child expressions that all are connected by the same operator. For example, the statement would contain the complex combinational subexpression of where b, c and d are the three child expressions all combined using the bitwise AND operator. The effect of each subexpression on the value of the entire subexpression as well as the combination of each child toward the parent is displayed. For example, if the combinational operator is a bitwise OR, each child is checked to see if it evaluated to TRUE (in an OR operation, only one subexpression needs to evaluate to TRUE for the entire subexpression to be TRUE). Additionally, all child subexpressions are checked to see if all evaluated to 0 simultaneously (this is the only way to get the whole subexpression to evaluate to 0). The unique identifier below each subexpression is used in the displayed coverage information for these types of subexpressions for identifying which subexpression did not behave correctly. All simple combinational subexpressions can be output as complex combinational subexpressions if there are three or more child subexpressions to the operation.
Example Coverage Output for an Uncovered Complex Combinational Subexpression
In this example, subexpression 1 never evaluated to a value of TRUE (which would have made the entire expression TRUE) and all three subexpressions 1, 2, and 3 were never a value of 0 simultaneously (which would have made the entire expression FALSE). However, subexpressions 2 and 3 both evaluated to TRUE at some point. Excluding/Including a Subexpression For any displayed subexpression within a statement, the user may choose to disregard the coverage information for that subexpression by clicking on the Excluded checkbutton on the right side of the window. If this option is checked, Covered will display a exclusion reason popup window to allow the user to specify a reason for excluding the subexpression. Once a reason has been entered, the combinational logic summary coverage information will be recalculated for the current module/instance by adding to the "Exclude" count the number of uncovered combinational logic values for the given subexpression (and all subexpressions below this expression within the expression tree). This new summary information will be redisplayed on the listbox. The subexpression background color in the top frame will also change from the uncovered background color to the covered background color. However, the subexpression will still contain an underline that may be clicked on at any time to view its coverage information or the coverage information for any subexpressions that are uncovered. To include a previously excluded subexpression, simply uncheck the Excluded checkbutton. This will automatically cause the summary information and background color to be updated for the given subexpression. below shows an example of a subexpression that has been excluded from coverage consideration.
Example of an excluded subexpression
If an expression tree has been entirely excluded from coverage (all subexpressions have the Excluded checkbutton checked), the background color in the file viewer will change from an uncovered background color to the covered background color to indicate at the top-level that this entire statement has been excluded from coverage. However, the statement will still be underlined in the Main Coverage File Viewer to allow the user to view the statement, if necessary. If the user excludes any subexpression in the design, the Save CDD... option in the file menu will be enabled. This allows the user to save the excluded property either back to the CDD file (or to a newly named CDD file). Doing so will allow the user to load the CDD file at a different time and retain the knowledge of which subexpressions have been excluded/included for coverage. Additionally, if a saved CDD file with coverage exclusion is merged with another CDD file, the excluded subexpression information is preserved for the resulting merged CDD file. If a subexpression has been excluded from coverage and an exclusion reason was specified, you can view the reason for exclusion by selecting the subexpression in the top window (so that it is displayed in the lower window and right-click-and-holding on the Excluded checkbutton. This will cause a tooltip-style window to be displayed specifying the reason for exclusion. The background color of the tooltip will be the same color as the "covered" background color to help distinguish it from a normal tooltip. To cause the exclusion reason tooltip to disappear, simply release the button. Displaying a New Statement If the Verbose Combinational Logic Coverage window is currently displayed with a statement, the user may select a new statement in the file viewer of the Mainwindow. When a new statement is selected, its value immediately replaces the currently selected statement. This feature allows many different statements to be viewed one after the other without having to create/destroy a new window for each. The user may also see the previous or next uncovered statement in the main viewer by clicking either the left arrow button (for previous signal viewing) or the right arrow button (for next signal viewing). Note that the left arrow button will be disabled if there is not a signal previous to the current signal in the given module and the right arrow button will be disabled if there is not a signal after the current signal in the given module. covered-0.7.10/doc/docbook/chapter_gui_main.xml0000644000076500007650000011136011055051326021447 0ustar trevorwtrevorw Navigating the Main Window shows the main window prior to a CDD file being loaded. There are five main components of the main window. These components are the following (from top to bottom, left to right): The menu bar The coverage type bar The module/instance summary listbox The coverage file viewer The information bar
Covered Main Window
The Main Menu Bar The Main Menu Bar consists of four menus at the top of the main window. below shows the menu bar portion of the GUI bordered in red. These menus are the following: File - Creates, opens, merges, saves and closes CDD files, generates reports, and exits the application. Report - Specifies what type of report to show. View - Provides additional viewing options. Help - Provides access to online help manual and tool information.
Covered Main Window Highlighting the Menu Bar
On Mac OS X, the main menubar does not exist in the application window. Like most Mac OS X applications, the main menubar exists at the top of the display. The File Menu The file menu is used to open a new CDD file, merge a related CDD file (derived from the same design as the currently opened CDD file, save the currently opened CDD file(s), close all opened CDD files, generate different types of output and view the names of all currently opened CDD files. Additionally, the user selects this menu bar to exit the Covered report viewer GUI. shows the file menu contents within the main window.
The File Menu
Open/Merge CDDs... This menu option is used to either open a new CDD file or merge a related CDD file into the currently opened CDD file(s). This action needs to be performed before any coverage viewing can take place. When this option is selected, a standard file window is displayed allowing the user to select one (or possibly more depending on your version of Tcl/Tk) CDD file to open or merge. To select more than one CDD file with one call to this option, simply press and hold the Control key while selecting files with the left mouse button. If your version of Tcl/Tk supports this feature, you will see multiple files highlighted for selection; otherwise, only the last selected file will be selected. If no CDD files currently are opened, any CDD file may be opened. If one or more CDD files have been opened/merged, only CDD files generated from the same design may be merged. Note that this option has an accelerator keystroke <Control-O>. Hitting this keystroke combination will also open new CDD file(s). View Loaded CDD(s)... This menu option is only available after an initial CDD file has been opened using the Open/Merge CDDs... file menu option. When this menu option is selected, a new window displaying all currently opened CDD files is displayed (see below). If another CDD file is merged and this window is currently displayed, it is automatically updated with the newly added file. If the Close CDDs... file menu option is selected while this window is opened, all filenames will be automatically removed to indicate this. The View Loaded CDD(s)... menu option is useful for helping the user see exactly which files have been merged or not merged in the current viewer. Simply click on the Close button in the Loaded CDD file viewer window to close the window.
The CDD Opened File Viewer
Save CDD... This menu option is only available after one or more CDD files have been opened/merged. It is used to save the opened or merged CDD files as a single, merged CDD file than can be viewed as a separate CDD file or can be merged with other CDD files. It is also used to save any changes that the user has made to exclude/include coverage cases within the GUI. If you would like to retain this information, please save the CDD file. By default, the name of the first loaded CDD file is placed in the "Save As" window when this option is selected. The user may choose to replace the old CDD file with the new one, or the user may save it under a different name. Once a CDD file has been saved, this option is deselected until either a new CDD file is merged or the user changes the exclude/include property of any coverage case within the GUI. Note that this option has an accelerator keystroke <Control-s>. Hitting this keystroke combination will also save the current CDD. Close CDDs This menu option is used to close all opened/merged CDD files so that the user may view a different CDD file without needing to exit and re-enter the GUI. The user may open and close as many times as needed without needing to reinvoke the GUI. When CDD files are closed, any opened coverage windows are automatically closed and all necessary GUI components are restored to their original state as when the GUI is first invoked. If the currently opened CDD file(s) have not been saved, a window (shown in below) is displayed to ask the user if they would like to save prior to closing. To save the CDD file, simply click "Yes" and a "Save As" window will prompt you for a location/name to save it as. To close the CDD file without saving, simply click "No". To cancel the close operation, simply click Cancel. To view another CDD file after closing all CDD files, simply select the Open/Merge CDDs... file menu option. Note that this option has an accelerator keystroke <Control-w>. Hitting this keystroke combination will also close all opened CDD files.
The Close Warning Window
Generate This option, when selected, displays a submenu of items that can be generated by the GUI. The following options (with descriptions) are available (see ).
The Generate Menu List
New CDD... Selecting this submenu option will cause Covered to allow for the creation of a new CDD file (note: this can be accomplished on the command-line with the "score" command). When this option is selected, the new CDD creation wizard window is created. See for more information on the navigation of this window. Note that this option has an accelerator keystroke <Control-n>. Hitting this keystroke combination will also cause the new CDD creation window to be displayed. ASCII Report... Selecting this submenu option will cause Covered to generate an ASCII version of the coverage report to a specified file (note: this can also be accomplished with the "report" command of Covered's command-line interface). When this option is selected, the ASCII report generation wizard window is created. See for more information on the navigation of this window. Note that this option has an accelerator keystroke <Control-r>. Hitting this keystroke combination will also cause the ASCII report generator window to be displayed. CDD Ranking Report... Selecting this submenu option will cause Covered to generate a CDD ranking report to a specified file (note: this can also be accomplished on the command-line with the "rank" command). When this option is selected, the CDD ranking wizard window is created. See for more information on the navigation of this window. Note that this option has an accelerator keystroke <Control-c>. Hitting this keystroke combination will also cause the CDD ranking window to be displayed. Exit This menu option will exit the entire GUI application, closing all opened windows created by this application. Use this option to exit the application. If the currently opened CDD file(s) have not been saved, a window (shown in below) is displayed to ask the user if they would like to save prior to exiting. To save the CDD file, simply click Yes and a "Save As" window will prompt you for a location/name to save it as. To close the CDD file without saving, simply click No. To cancel the close operation, simply click Cancel. Note that this option has an accelerator keystroke <Control-x> (or <Command-Q> on Mac OS X). Hitting this keystroke combination will also close the entire application.
The Exit Warning Window
The Report Menu The report menu allows the user to display the currently opened CDD file contents in a number of different ways for analyzing. The options specified in this menu closely imitate the options in the "report" command. The type of report can be changed at any point in time while a CDD is loaded. When a report menu option is selected, Covered will automatically convert all information in the GUI to represent this report type. below shows the contents of the report menu. Each menu item is described below the figure.
The Report Menu
Module-Based When the diamond to the left of this option is selected, the generated report information will be in module-based representation. A module-based report gathers all of the module instances that instantiate the same module and merges their results based on the module name. This is useful for understanding what logic in a module has been tested or untested without care to individual instance contribution. Selecting this report type (the default) will cause the Instance-based menu option to be automatically deselected (the two report types are mutually exclusive). Instance-Based When the diamond to the left of this option is selected, the generated report information will be in instance-based representation. An instance-based report shows the coverage information for each module instance within the design. This allows the user to discern what logic is being covered in individual instances. Selecting this report type will cause the Module-based menu option to be automatically deselected (the two report types are mutually exclusive). Line, Toggle, Memory, Logic, FSM, Assert These menu options are directly tied to the coverage metric select menubutton in the coverage bar (see ). Changing the value in the menubutton will change the selection of this menu item and vice versa. Only one of these menu items will be selected at a given time. Show Uncovered When the square to the left of this option is selected (the default), all uncovered lines, toggles, logic, and FSM states/arcs within the file viewer window will be highlighted for the user to quickly see what code was monitored by Covered but determined to not be fully covered. This option may be selected along with the Show Covered menu option to see both covered and uncovered logic within the same file. Show Covered When the square to the left of this option is selected, all covered lines, toggles, logic, and FSM states/arcs within the file viewer window will be highlighted for the user to quickly see what code was monitored by Covered and determined to be fully covered. This option is useful for the user of Covered to understand what logic was monitored during simulation. This option may be selected along with the Show Uncovered menu option to see both covered and uncovered logic within the same file. Show Race Conditions When the square to the left of this option is selected, all logic lines that were found to contain a potential race condition and was, therefore, eliminated from coverage consideration by Covered will be highlighted by the colors as selected in the preference menu. This option is useful for the user of Covered to understand what logic was not considered for coverage information due to a detected potential race condition situation. Please see for more information on what Covered looks for in logic to consider it to be a possible race condition. The View Menu The View menu allows the user to select or change the current way the information in Covered is viewed. shows the contents of the View menu.
The View Menu
Next Uncovered Causes the line containing the next uncovered metric to be visible in the file viewer. If the next uncovered line is already visible, this menu item will have no visible effect. The search for the next uncovered line starts at (a) the top of the module (when the module is first displayed in the the Coverage Viewer), (b) from the last uncovered line searched for with the Next Uncovered or Previous Uncovered calls, or (c) from the last currently selected line (only valid for toggle and combinational logic views). This menu item is only enabled when another uncovered line exists after the current uncovered line. It can also be accessed with the accelerator keystroke <Control-n> or the right arrow button in the Main Window. Previous Uncovered Causes the line containing the previous uncovered metric to be visible in the file viewer. If the previous uncovered line is already visible, this menu item will have no visible effect. The search for the previous uncovered line starts at (a) the top of the module (when the module is first displayed in the the Coverage Viewer), (b) from the last uncovered line searched for with the Next Uncovered or Previous Uncovered calls, or (c) from the last currently selected line (only valid for toggle and combinational logic views). This menu item is only enabled when another uncovered line exists before the current uncovered line. It can also be accessed with the accelerator keystroke <Control-p> or the left arrow button in the Main Window. Show Current Selection This menu item is only available if the current metric mode is not "Line", the user has clicked on an uncovered segment of code, and the associated toggle, memory, logic, FSM or assertion verbose window exists. The currently selected line is visually identified in the file viewer area on the left-hand side of the line containing the uncovered code. If this line is not currently visible in the Coverage Viewer, selecting this menu item will cause it to be visible. An accelerator keystroke <Control-c> will also invoke this menu item. Wizard... Displays the Covered wizard window which normally opens upon starting the Covered GUI. The Wizard window allows the user to easily create a new CDD file, open/ merge existing CDD files, rank existing CDD files and get user documentation. See for more information. Preferences... Causes the preferences window to be created if it currently does not exist or forces it into the foreground if it does exist. On Mac OS X, this menu item does not exist in the "Report Menu" but rather in the Covered application menu to remain consistent with the Mac OS X environment. The Help Menu The help menu contains all of the user documentation for Covered. Additionally, information regarding the version of Covered used and other contact information for application problems, suggestions, etc. can be found in this menu.
The Help Menu
Manual Selecting this menu item causes Covered to display the user manual in a web browser. About Covered Selecting this menu item causes Covered to bring up a window showing the current release number, developer contact information and credits. On Mac OS X, this menu item does not exist in the Help Menu but rather in the application's menu to remain consistent with the Mac OS X environment. The Coverage Type View Bar shows the location of the coverage type view bar. The bar contains two selection buttons. The selection button on the left side of the bar shows the currently selected coverage metric. There are six main types of coverage metrics that Covered can provide: line, toggle, memory, logic (combinational logic), FSM (state and arc) and assert (assertion coverage). When the Covered GUI is first invoked, the line coverage metric is the default mode. To view a different metric, simply left click, select the desired coverage metric, and left click again. Doing so will automatically set the selection indicator to the new mode and display the new metric information in the Module/Instance listbox and file viewer. The selection button on the right side of the bar shows the current coverage accumulation mode: module or instance. Module coverage takes all of the similar module instances and merges their coverages. Instance coverage displays each module instance individually. To select a different value than the one displayed, simply left click the selection button, highlight the desired value and left click again. This will repopulate the Module/Instance lisbox and clear the file viewer.
Covered Main Coverage Type View Bar
The Module/Instance Listbox After a CDD file has been opened in the GUI, the module/instance selection box (shown in below) will contain either a list of all of the modules within the specified design or a list of all of the instances within the design, based on the type of report selected in the report menu. Left-clicking on a module/instance name within this box will cause that file to be output in the file viewer to the right of the selection box. In addition to the names of the modules or instances of the design, each line also contains a summary view of the coverage for the currently selected metric for each module or instance. The summary coverage information includes the number of hits, number of misses, total number and hit percentage. Each column in the table can be resized by clicking on the separator bar between the column headers and sliding the column to the left or to the right. Additionally, columns may be hidden or shown in the module/instance selection box by clicking on the button at the right-hand side of the column header bar (and above the vertical scrollbar). When this button is left-clicked, a popup menu will be displayed showing which columns are currently shown (a check to the left of the column name) and which are hidden (no check). To change the display for a particular column, simply click on the column name in the popup window. This will cause the associated column to be hidden or shown and will close the popup window. If the popup window is displayed and the user does not wish to change the display values of any of the shown columns, simply click anywhere on the screen but on the popup window. This will cause the popup window to disappear and no column display values will be changed. Depending on the selected coverage metric (specified in the coverage bar) and the coverage results for each module/instance, a module/ instance item will be highlighted in the uncovered logic color if the corresponding module/instance was found to have uncovered logic within that module/instance. If the specified module/instance was found to be fully covered for the currently selected metric, it will be highlighted with the selected covered logic color. This can help the user quickly identify modules/instances that contain uncovered logic cases. Note that when a different coverage metric is selected, the highlights will be recalculated for that metric. Additionally, the currently selected module/instance will be displayed in a darker version of the covered/uncovered color.
Populated Module/Instance Selection Box
The Coverage File Viewer shows the area of the main window where the coverage file viewer window is located.
Covered Main Coverage File Viewer
The coverage file viewer shows the currently selected module (indicated in the information bar) Verilog source. The coverage file viewer provides a read-only view of the original source code so all editing of the file must be done in a separate editor. Each source code line in the viewer window is numbered to the left of the line to aid in debugging and finding the lines in an editor. Depending on the coverage metric currently selected in the coverage bar and the covered/uncovered/race condition selections in the report menu, the lines that are found to be uncovered, covered, and/or considered a race condition are highlighted in their respective color schemes in the coverage file viewer window. Using the scrollbars to the right and below the coverage file viewer, the user can find the missed/hit lines quickly for further analysis. The coverage file viewer is the place where the user can invoke the toggle, memory,combinational logic, FSM and/or assertion detail windows. To view one of these windows, do the following: Select either the Toggle, Memory, Logic, FSM or Assert coverage metric selection button in the coverage bar. Select a module/instance that contains uncovered code in the listbox. In the coverage file viewer, find code that is highlighted as being uncovered. Left click on the uncovered piece of logic. Doing so will automatically bring up either the toggle, the memory, the logic, the FSM or the assertion verbose coverage windows. Additionally, the logical blocks that have been disregarded by Covered due to a potential race condition existing are highlighted. By placing the cursor over one of these logical blocks, the reason for why the logical block was disregarded is output in the information bar. To view a new module/instance, simply left click on one in the Module/Instance Listbox. The source code for the selected module/instance will be immediately loaded into the coverage file viewer in the currently selected coverage metric. To view a new coverage metric, simply left click on one of the coverage metrics in the Coverage Type Bar. The currently selected module/instance will be immediately updated in the coverage file viewer, highlighting the uncovered/covered code for the current metric. Searching for an Uncovered Line in the Coverage Viewer To find the next or previous line containing uncovered logic for the current metric mode, click the left arrow (Previous) or right arrow (Next) buttons. Doing so will cause the next or previous uncovered line to be visible in the Coverage File Viewer. Clicking these buttons has the same effect as the "Next Uncovered" or "Previous Uncovered" menu items in the view menu. Searching for a String in the Coverage Viewer The Coverage Viewer contains a find (magnifying lens) button, an entry field, and a clear (X) button for performing text searches in the Coverage File Viewer. The user may type in any string (wildcards and pattern matching is not supported) in the entry field. Hitting the "return" key or the find button will cause the string search to commence. If a match to the search value is found, it is made visible in the Coverage File Viewer and highlighted. The user may search on the value again by clicking the find button. To clear the current value in the entry field, click on the clear button. If a match occurs, the specified value in the entry field will remain until either a new value is entered or the clear button is clicked. If a match was not found for the given string, a message window will pop-up specifying that the given string was not found. Clicking the OK button will cause this message window to close and the entry field will automatically be cleared. The Information Bar The information bar at the bottom of each window in the report viewer provides information about the current mode, file, or operation the user should take next. All information is state and context sensitive. If you are in doubt of what to do next, first see the information bar.
Covered Main Information Bar
covered-0.7.10/doc/docbook/chapter_gui_memory.xml0000644000076500007650000002562511061564253022050 0ustar trevorwtrevorw Navigating the Memory Coverage Window The verbose memory window allows the user to interactively view all of the coverage information for a selected memory, including the following for each addressable memory element: Have all bits toggled from 0 -> 1 and from 1 -> 0? Has the entry been written? Has the entry been read? To display this window, simply click on a highlighted/underlined uncovered memory in the file viewer. This will cause the verbose memory viewer to be created for the specified memory as well as display a "-->" symbol in the Coverage Viewer on the same line as the selected memory. This symbol is simply meant to help the user identify in the Coverage Viewer which memory is currently displayed in the Memory Viewer window. Figure 1 shows the Memory Viewer loaded with a 4-dimensional memory called "mem" in which two of the dimensions are unpacked (all combinations of unpacked dimensions make up the total number of addressable elements in the memory), creating a total of 18 addressable elements. The first addressable element "[0][0]" is shown in the lower frame in which only a single bit has been toggled from 0 to 1, the element has been written, but it has not been read.
Verbose Memory Window
Understanding the Layout The Memory Coverage window is split up into three main frames stacked from top to bottom. These frames, in order from top to bottom, are the "Addressable Memory Elements" frame, the "Element Coverage" frame, and the button frame. Each are described in detail below. Addressable Memory Elements Frame The uppermost frame contains all of the addressable memory elements (AMEs) of the memory. An AME is a single memory entry that is addressed by specifying a unique combination of values for each of the unpacked dimensions of the memory. For example, consider the following memory: reg [15:0] foo[0:1][0:3]; This memory called "foo" contains three dimensions. One packed dimension which is a 16-bit little endian value and two unpacked dimensions, containing two entries of four entries (for a total of eight addressable memory elements). Each AME being 16 bits wide. The AMEs for this memory would be: foo[0][0] foo[0][1] foo[0][2] foo[0][3] foo[1][0] foo[1][1] foo[1][2] foo[1][3] The upper frame will contain all of the AMEs for the selected memory. The uncovered AMEs will be highlighted in the uncovered color scheme (as specified in the preferences window) while all fully covered AMEs will remain unhighlighted. To view the coverage information for any uncovered AME, simply click on it and the information will be viewable in the "Element Coverage" frame below it. Element Coverage Frame The Element Coverage frame shows all of the coverage information for the currently selected AME including toggle coverage (which bits of the element toggled from 0->1 and 1->0), write coverage (was this entry written to) and read coverage (was this entry accessed). The bit vector displayed in the toggle window is a binary bit vector, where each value (0 or 1) represents whether that bit in the signal either toggled (1) or did not toggle (0) during simulation. There are two bit vectors displayed for the AME, the top vector shows the 0->1 toggle information while the bottom vector shows the 1->0 toggle information. The name of the memory along with its dimensional range information is displayed below the toggle window; however, if the mouse cursor is placed over a specific bit in the toggle box, the packed dimensional range information will be changed to show the displayed bit, making it easy for the user to discern exactly which bit has toggled/not toggled. If the width of the AME exceeds the given space for the toggle window, a scrollbar will be allowed to slide left and right to view the rest of the toggle information. Below the memory name are two other pieces of coverage information about the AME. The value to the right of the Written: label will be set to either "Yes" or "No". If the value is "Yes", this indicates that the currently selected AME was written during simulation and value will be highlighted with the covered color scheme (as selected in the preferences window). If the value is "No", this indicates that the currently selected AME was not written during simulation and the value will be highlighted with the uncovered color scheme. To the right of the Written information is the Read label which will also be set to either a value of "Yes" or "No". If the value is "Yes", this indicates that the currently selected AME was accessed during simulation and the value will be highlighted with the covered color scheme. If the value is "No", this indicates that the currently selected AME was not accessed during simulation and the value will be highlighted with the uncovered color scheme. Button Frame The button frame contains buttons for closing the Memory Coverage window, displaying this help page, or moving to the next/previous uncovered memory in the same module/instance. To exit this window, simply click on Close button. To see this help page from the toggle window, click on the Help button. Excluding/Including a Memory for Memory Coverage The user may exclude/include any uncovered memory in the design for memory coverage by simply clicking on the Excluded checkbutton in the upper right-hand portion of the Memory Coverage window. If this checkbutton is checked, the exclusion reason popup window will be displayed automatically, allowing the user to specify a reason for excluding the memory. Once a reason has been entered, the summary coverage information will automatically be recalculated and redisplayed in the listbox and the background color of the underlined memory in the file viewer will change from the uncovered background color to the covered background color. However, the memory will still remain underlined, allowing the user to see the verbose memory coverage information, if necessary. If the Excluded checkbutton is unchecked, the summary coverage information and background colors will be readjusted to include the coverage information for this memory. If the user excludes any memory for memory coverage in the design, the Save CDD... option in the file menu. This allows the user to save the excluded property either back to the CDD file (or to a newly named CDD file). Doing so will allow the user to load the CDD file at a different time and retain the knowledge of which memories have been excluded/included for memory coverage. Additionally, if a saved CDD file with coverage exclusion is merged with another CDD file, the excluded memory information is preserved for the resulting merged CDD file. If a memory has been excluded from coverage and an exclusion reason was specified, you can view the reason for exclusion by right-click-and-holding on the Excluded checkbutton. This will cause a tooltip-style window to be displayed specifying the reason for exclusion. The background color of the tooltip will be the same color as the "covered" background color to help distinguish it from a normal tooltip. To cause the exclusion reason tooltip to disappear, simply release the button. Displaying a New Memory for Memory Coverage If the Verbose Memory Coverage window is currently displayed with a memory, the user may select a new memory in the file viewer of the Main window. When a new memory is selected, its value immediately replaces the currently selecting memory value. This feature allows many different memories to be viewed one after the other without having to create/destroy a new window for each memory. The user may also see the previous or next uncovered memory in the main viewer by clicking either the left arrow button (for previous memory viewing) or the right arrow button (for next memory viewing). Note that the left arrow button will be disabled if there is not a memory previous to the current memory in the given module and the right arrow button will be disabled if there is not a memory after the current memory in the given module. covered-0.7.10/doc/docbook/chapter_gui_new.xml0000644000076500007650000010176511472127327021334 0ustar trevorwtrevorw Creating a New CDD Creating a new CDD file from the GUI can be accomplished by either clicking on the Generate New CDD File button in the Wizard window (see for more details on this window), by selecting the File -> Generate -> New CDD... menu option, or using the shortcut "Shift-Control-N". This file creation "wizard" allows the user to create a new CDD file that can be opened/merged into the GUI for coverage analysis. The methods that the CDD creation GUI allows for creating a new CDD file are quite flexible and are completely compatible with the command-line commands. The following subsections describe the various windows used to create a CDD. Note that the CDD creation wizard uses several "pages" to describe the various options to set for creating a new CDD file, using Back and Next buttons on each page for navigation. Clicking on the Back button will not cause previously filled in pages to be reverted to their default values but rather will remain populated with the user's data. Similarly, if a page has been filled in with data and the Back button is clicked and then the Next button is clicked, the page contents are retained. The only way to clear out fields is to click the Cancel button at the bottom of each page and startup the CDD creation wizard again. Clicking the Cancel button at any time will cause the CDD creation wizard to immediately exit. Clicking on the help (?) button at any time will bring up the user documentation for the current page (context sensitive help). Navigating the New CDD Creation Option Selection Page Figure shows the look of this page of the CDD creation wizard.
CDD Creation Option Selection Page
The first page of the CDD creation window allows the user to select whether all options should be interactively selected within the GUI or if a file should be read in which contains command-line options to the score command to use. If the latter is chosen, the contents of that file are read in and are populated in the GUI, but the CDD creation wizard will continue in the same fashion as the first option, allowing the user to change, remove or add to the options found in that file. If the Create CDD by interactively selecting options entry is currently selected and the user wishes to not use a command-line file to populate the rest of the CDD creation pages, simply click on the Next button at the bottom of the page to continue. If the Create CDD by using option file entry is currently selected, the user must either type a valid filename or select one by clicking the Browse... button to the right of the file entry area and select a valid file. Once a valid filename is selected, the Next button will be enabled and the user may then click it to continue to the next page. Note that any filename can be selected (whether it's a valid command file or not). Only valid score command options found in that file are used to populate the wizard entries. No error message will be displayed if the file does not contain this information. Navigating the New CDD Creation CDD Name Page This page is used to specify the name of the output CDD file. shows the display of this page.
CDD Creation Output Name Page
The output CDD name must be specified and, as such, the Next button is disabled until a name is specified in the entry field. Any filename is allowed. If the user wishes to make use of a "Save As" style window for creating a filename, click the Browse... button and use the window for creating a filename. When the Save button is clicked, the specified filename is placed in the entry field and the Next button is enabled. CDD Creation Type Page This page is used to specify what type of CDD file to create. The four types of CDD files that can be created are: An unscored CDD file that was created by parsing the design. This CDD file can later be scored via a VCD, LXT2 or FST dumpfile. This option can be chosen by selecting the Parse Design Only radiobutton. A scored CDD file created from the design and from a previously created VCD, LXT2 or FST dumpfile. This option can be chosen by selecting the Dumpfile: option. If this option is chosen, a VCD, LXT2 or FST dumpfile is required to be specified before the next option page can be used. Either specify this dumpfile name by typing in an existing dumpfile name in the entry field or use the Browse... button to select a dumpfile. An unscored CDD file, a top-level Verilog file containing a PLI call to run Covered in VPI mode, and a PLI tab file that can be used by some simulators for compilation purposes. See for details on how to use these files for simulation/scoring purposes. This option can be chosen by selecting the VPI Module: radiobutton. If this option is chosen, the name specified will be the name of the module file created that is used to allow Covered to run in VPI mode within a simulation. The basename of the module file will be used for the top-level module. In addition to providing a module name when this option is selected, the simulator type that will be used when scoring can be specified as well as the timescale information that can, optionally, be specified at the top of the generated module. An unscored CDD file and a top-level Verilog file containing the necessary $dumpfile/$dumpvars calls to score the design. This module can be compiled as a top-level module along with the design to produce a VCD/LXT2/FST dumpfile to be used for coverage scoring. See for details on how to use these files for simulation/scoring purposes. This option can be chosen by selecting the Dumpvars Module: radiobutton. If this option is chosen, the name specified will be the name of the module file created (the basename will be the name of the module and the basename of the VCD/LXT2/FST dumpfile created from the simulation) that will contain the $dumpfile/$dumpvars calls needed to score the design. The timescale specifiers will be enabled if either the "VPI Module" or "Dumpvars Module" buttons are selected. Selecting the "Set Top Module Timescale" checkbutton will allow you to specify a timescale that will be added to the top of the VPI or dumpvars module file (setting the timescale in top-level modules is sometimes necessary for compilation purposes). If the checkbutton is not selected, no timescale information will be added to the generated top-level module file. Figure displays the contents of this page. When all necessary fields have been specified, the Next button will be enabled and clicking it will lead to the next option page.
CDD Creation Type Page
CDD Creation Options1 Page This page is used to specify several options to Covered's score command. See figure for the layout of this window.
CDD Creation Options1 Page
The following is a description about each of the CDD creation options available on this page. General Options Toplevel module name Required? Yes The name of the top-level module must be specified for a given design to be parsed and a CDD generated from that source. Simply type in the name of the top-most module in the provided entry field. Once a name is provided, the Next button will be enabled to allow traversal to the next option page. Root pathname Required? No This entry field is an optional one to fill. This value is only necessary if the top-most module to be scored is not the top-most module of the simulator. If this is true, then the value that must be provided in the associated entry field must be the hierarchical reference to the module to be scored. An example of a valid root pathname would be something like: top.foo.bar.dut See for more information. Delay Type This value specifies which delay should be used when a delay type of #(delay_max:delay_typ:delay_min) is encountered in the scored design. If this type of delay specification is not encountered, there is no need to change this value in the GUI. If the delay specification is encountered in the design and this value has not been specified, the default of typ will be used. Otherwise, the user can specify which delay value should be chosen by changing the displayed type to either max, typ, or min. Race Condition Action After the design has been parsed and elaborated, Covered performs a static race condition check on the design to verify that no potential race conditions exist. If a race condition exists in the design, this would cause the coverage results to potentially be errant. This parameter allows the user to tell Covered what to do if a race condition is found in the design. The valid values are: Silent Specifies that no output should be generated. Any blocks with race conditions existing within them will be automatically removed from coverage consideration. Warning Specifies that race condition should be output and those blocks containing the race condition will be automatically removed from coverage consideration. Error Causes Covered to display the race condition violations and stop scoring after all race condition checking has occurred. Ignore Causes Covered to skip race condition checking completely. This option can be used if the user is confident that no real race conditions exist in the design but Covered's static race condition checker is displaying potential problems. If no race conditions actually exist, ignoring race condition checking results allows more of the design to be considered for coverage. Use embedded race condition pragmas If this option is selected, a user-specified pragma ("racecheck" by default) is parsed and any potential race conditions found between the off/on pragma pair are ignored by the race condition checker. See for more details. Default Verilog Generation Covered's parser supports parsing for Verilog-1995, Verilog-2001 and SystemVerilog, defaulting its parser to support SystemVerilog. However, for older designs which may contain names that are keywords in the newer versions, it may be necessary to change the parser of Covered for the entire design. This option specifies the version of the parser which is used for the entire design. For information regarding the ability to specify a certain version of the parser for a specific module, see . Include OVL Assertions If this option is selected, any OVL assertion modules found within the scored design will have assertion coverage information extracted from them. Exclude Options Exclude Always Blocks If this option is selected, all always code blocks will be excluded from coverage consideration. Exclude Assign Blocks If this option is selected, all assign code blocks will be excluded from coverage consideration. Exclude Initial Blocks If this option is selected, all initial code blocks will be excluded from coverage consideration. Exclude Final Blocks If this option is selected, all final code blocks will be excluded from coverage consideration. Exclude Within Pragma If this option is selected, all code blocks will be excluded between the exclusion off/on pragmas. The name of the exclusion pragma is defaulted to "coverage" but can be changed within the associated entry field. See for more information. CDD Creation Options2 Page The second CDD creation options page contains a listbox which will contain the various user-specified options that have been inserted via the Insert... menubutton. Any options that exist within this listbox can be edited by selecting the option and clicking on the Edit... button or deleted by clicking on the Delete button. Additionally, options may be reorganized within the listbox by simply clicking on an option and dragging it into the needed position. See figure for the layout of this option page.
CDD Creation Options2 Page
To add an option to the listbox, simply click on the Insert... menubutton which will display a list of options. Select one of these options to display a window where the contents of that option can be specified. Clicking the OK button in one of those windows will cause the option to be added to the option listbox. Clicking Cancel in one of those windows will cause the option to not be added to the listbox. Clicking help (?) will display context-sensitive help information to be displayed about the current window. Figure shows the contents of the Insert... menubutton. The following sections describe each option and its corresponding entry window.
CDD Creation Insert Menubutton
Source File... Selecting this insert option will cause an open file selector window to be displayed. Use it to choose a single file that will be parsed as a library file (i.e., the -v option to most Verilog compilers). Library Directory... Selecting this insert option will cause an open directory selector window to be displayed. Use it to choose a single directory that will be used as a library directory (i.e., the -y option to most Verilog compilers). Library Extension(s)... Selecting this insert option will cause a window to be displayed that will allow the user to add library file extensions to the library file parser (i.e., the +libext+ option to most Verilog compilers). is a display of this window.
CDD Creation Library Extension Window
To add a new extension, select the Click to Add New Extension item in the extension box (selected by default), type in the name of the extension in the upper entry box and either hit the "Enter" key or click on the Update button. If an incorrect extension was input, you may edit it by clicking on the incorrect item in the extension listbox. This will cause the item to be listed in the upper entry box where it can be edited or removed. Click the OK button to accept the specified library extensions and add these to the main window listbox. Click the Cancel button to ignore the recent updates in this window. Include Directory... Selecting this insert option will cause an open directory selector window to be displayed. Use it to choose a single directory that will be used as an include directory (i.e., the +incdir+ option to most Verilog compilers). Define... Selecting this insert option will cause a window to be displayed that will allow the user to add a command-line variable definition to be added to the score command (i.e., the +define+ option to most Verilog compilers).
CDD Creation Define Window
To add a new define, enter the name of the definition variable in the entry box to the right of "Define name:". If the variable does not require a value, simply click on the OK button to submit it to the main window option listbox. If the variable requires a value, click on the = button, enter the value in the entry box to the left of that button, and click on the OK button. To abort the addition of the definition, simply click on the Cancel button. The OK will only be enabled when the user has entered a value in the "Define name:" entry box. Parameter Override... Selecting this insert option will cause a window to be displayed that will allow the user to add a parameter overload option to the score command. Because Verilog "defparam" is not used by the Covered parser, this option is the only way to override parameter values.
CDD Creation Parameter Override Window
To add a new parameter override option, enter the full hierarchical path to the parameter to override in the left entry box and add the override value in the right entry box. See for details on how to specify an override value. After both values have been input, click the OK button to add the parameter override option to the main window listbox. To abort the parameter override addition, click on the Cancel button. The OK button will only be enabled if both values are input in the entry boxes. FSM... Selecting this insert option will cause a window to be displayed that will allow the user to add an FSM input/output state on the score command line. This option allows the user to specify the location of FSMs within the design without inlining this information with the use of pragmas for the purposes of gaining FSM coverage information.
CDD Creation FSM Specification Window
To add a new FSM option, enter the name of the module containing the FSM in the upper-left entry box, the description of the output state in the upper-right entry box (see for information on properly specifying the output/input state information). If the input state is the same as the output state, simply click on the Input == Output button which will fill in the input state with the same value as the output state value. If the input state differs from the output state, enter the input state in the lower-right entry box. When all entry fields have been filled in, click on the OK button to add the FSM description to the main window listbox. To abort the addition, click on the Cancel button. The OK button will only be enabled if all entry fields have been filled in. Module Generation... Selecting this insert option will cause a window to be displayed that will allow the user to specify a Verilog generation (Verilog 1995, Verilog 2001 or SystemVerilog) for a particular module. This generation value will override the universal generation value (see the "Default Verilog Generation" item in ) for the design.
CDD Creation Module Generation Window
To specify a Verilog generation to be used for a specific module, enter the name of the module in the left entry box and select one of the Verilog generations in the drop-down menu on the left. Once this information has been specified, click on the OK button to add this option to the main window listbox. To abort the module generation addition, click on the Cancel button. The OK button will only be enabled if a module name is specified in the left entry box. Module Exclusion... Selecting this insert option will cause a window to be displayed that will allow the user to specify a module to exclude from parsing and coverage consideration. More information on the purpose for excluding modules is discussed in .
CDD Creation Module Exclusion Window
To specify a Verilog module to exclude from the score command parser, enter the name of the module in the entry box to exclude. Click on the OK button to add the module exclusion option to the main window listbox. Click on the Cancel button to abort the option addition. The OK button will only be enabled if a value is specified in the entry box. Command File... Selecting this insert option will cause an open file selector window to be displayed which will allow the user to find a file that contains Covered score command-line options within it. Select a file and click on the Open button to cause the selected file to be added to the main window listbox. Click on the Cancel button to abort this action. Other Notes After all options have been specified, the Save Options to File... button can be clicked to cause all previously specified options to be saved to a file which can later be loaded by the new CDD creation window. Simply click the button and specify a filename to save the options under and click the Save button. When all options have been setup, click the Generate button to create the new CDD file. This button will advance to another page containing the output from Covered's score command. CDD Creation Output Pane The final pane in the CDD creation window wizard is the output window. After the Generate button is pressed, the user-supplied options are gathered and executed within a system shell and the output of that command is sent to this pane's textbox. If the score command run was a success, the Open/Merge the newly created CDD checkbutton will be enabled, allowing the user to open or merge the new CDD file into the GUI immediately. To exit the CDD creation process, click on the Finish button. If the score command failed for any reason, the user may click on the Back button to change the options specified to the score command or simply click the Finish button to exit the new CDD creation wizard.
CDD Creation Output Window
covered-0.7.10/doc/docbook/chapter_gui_preferences.xml0000644000076500007650000005371211067547607023051 0ustar trevorwtrevorw Navigating the Preferences Window The preferences window allows the user to adjust the view of some of the GUI elements for the purpose of more easily analyzing coverage information for a specific user. shows the preferences window that is created when the user selects the View > Preferences... menu option from the main window.
Main Preferences Window
Option Categories On the left side of the preferences window is a list of option categories that can be modified. Selecting any one of the items in the listbox will display the modifiable options to the frame to the right of the listbox. The following option categories exist: Preference Buttons Apply Button Clicking on the Apply button will cause the currently selected preference options to be immediately updated in Covered but will not update the preference option values in the .coveredrc file. This has the effect of changing the preferences for the current application only. Clicking on this button will not close the Preferences window. OK Button Clicking on the OK button will cause the currently selected preference options to be immediately updated in Covered and will update the .coveredrc file with the new values. This also causes the Preferences window to close. Cancel Button Clicking on the Cancel button will cause the the Preferences window to close without updating Covered with the currently selected values and without updating the .coveredrc file. Help (?) Button Clicking on the help (?) button will cause the help page for the currently selected'Option Category' to be displayed. Preferences Configuration File User preferences are loaded from the ".coveredrc" file that is searched for in the following order: Current directory that the 'covered report -view' command was executed from. The user's home directory. The installation directory (by default this is /usr/local/share/covered). If user preferences are changed in this window and the OK button is pressed, the settings are immediately saved back to a configuration file and the GUI is immediately updated to reflect the new user changes. If the Cancel button is pressed, all changes are thrown away and the configuration file remains unchanged. The location of the stored configuration file depends on which configuration file location was initially loaded. The following table describes this correlation. Location of Written .coveredrc File According to the Location of Read .coveredrc File Loaded config file location Stored config file location Current directory Current directory Home directory Home directory Install directory Current directory None found Current directory
Preferences General Pane The general preferences pane allows the user to control Covered's settings that are not specific to an individual task. The following subsections describe the controls available within this pane. Show wizard window on startup This checkbutton selects if Covered's wizard popup window will be displayed upon starting Covered. Simply check this button if you would like to see the wizard at the beginning of each startup or uncheck it to cause the wizard window to not be displayed on startup. On the wizard window itself, there is an option to change this behavior as well. Note that you can always display the wizard window by selecting its menu option in the view menu. Save state of GUI when exiting the application This checkbutton determines if certain GUI element (i.e., window placement/sizing, module/instance listbox column arrangement/width/state, etc.) information is saved when the GUI exits. If this checkbutton is selected, the state is saved to the configuration file on application exit and will be used when the application is started. If the checkbutton is deselected, the state will not be saved and the default GUI element behaviors will be used. This setting allows the user to setup the various GUI elements to their liking and retains this information whenever the application is restarted, saving the user the hassle of getting the environment setup again. While the application is being used, any GUI state information will be remembered for the duration of the application run, regardless of the setting of this preference item. Show tooltips This checkbutton specifies if GUI widget tooltips should be displayed if the user hovers the cursor over a GUI element that has a tooltip associated with it. To disable tooltips from being used, uncheck this option and click either the Apply or OK buttons. Preferences Color Pane The color preference pane allows the user to adjust the foreground and background colors for all code that is considered covered, uncovered, or in a race condition state. Set Highlight Color This frame contains six buttons that affect the foreground and background colors used to highlight code in the file viewer portion of the main window. The currently selected foreground/background colors are displayed to the left of the corresponding buttons to allow the user to see the selections prior to committing to them by clicking the Apply or OK buttons at the bottom of the Preferences window. The "F" button controls the foreground color while the "B" button controls the background color. Clicking one of these buttons will bring up a color selection window that you can use to modify the current color to one of your choosing. Preference Coverage Goals Pane The coverage goals preference pane allows the user to change the acceptable coverage goals for each coverage metric.
Coverage Goals Window
Set Acceptable Coverage Goals Frame This frame contains four spinner boxes that contains values between 0 and 100. These values correspond to a coverage percentage for each coverage metric that the user deems to be "good enough". These values are used by the listbox to help visually identify modules/instances that are meeting or exceeding these goals and which modules are not meeting these goals. If a coverage percentage for a module/instance is less than this value, the module is colored red. If the coverage percentage is greater than or equal to this value, the module/instance is colored yellow (or green which indicates that the module/instance reached 100% coverage for a given metric). To increase the specified percentage value, simply click on the "Up" button to the right of the percentage until the desired value is displayed. To decrease the specified percentage value, simply click on the "down" button to the right of the percentage until the desired value is displayed. Line Coverage % Sets the coverage goal of line coverage to the specified percentage to the right. If line coverage for a given module/instance meets or exceeds this percentage value, it will be displayed yellow in the Module/Instance listbox on the Main window. Toggle Coverage % Sets the coverage goal of toggle coverage to the specified percentage to the right. If toggle coverage for a given module/instance meets or exceeds this percentage value, it will be displayed yellow in the Module/Instance listbox on the Main window. Memory Coverage % Sets the coverage goal of memory coverage to the specified percentage to the right. If memory coverage for a given module/instance meets or exceeds this percentage value, it will be displayed yellow in the Module/Instance listbox on the Main window. Combinational Logic Coverage % Sets the coverage goal of combinational coverage to the specified percentage to the right. If combinational logic coverage for a given module/instance meets or exceeds this percentage value, it will be displayed yellow in the Module/Instance listbox on the Main window. FSM State/Arc Coverage % Sets the coverage goal of FSM state/arc coverage to the specified percentage to the right. If FSM state/arc coverage for a given module/instance meets or exceeds this percentage value, it will be displayed yellow in the Module/Instance listbox on the Main window. Assertion Coverage % Sets the coverage goal of assertion coverage to the specified percentage to the right. If assertion coverage for a given module/instance meets or exceeds this percentage value, it will be displayed yellow in the Module/Instance listbox on the Main window. Preferences Syntax Highlighting Pane The syntax highlighting preferences pane allows the user to adjust the syntax highlighting mode and colors for any displayed Verilog source code.
Syntax Highlighting Preferences Pane
Set Syntax Highlighting Options This frame allows the user to specify if syntax highlighting should be performed in all Verilog source viewers or not. When the square to the left of the Turn on syntax highlighting mode is selected, syntax highlighting will occur; otherwise, it will not perform syntax highlighting. The various colored buttons below the selection mode allow the user to select the foreground color of the text associated with its specified syntax type (Comments, Preprocessor Keywords, Verilog Keywords, Strings, Constant Values, and Operation Symbols). Simply click on one of the buttons to change its color. Doing so will cause a color selection window (see above) to be displayed. If the syntax highlighting mode is disabled by the user, the color selection buttons will be disabled. Preferences Exclusion Pane The exclude preferences pane allows the user to control whether or not the coverage exclusion reason window automatically pops up when a coverage point is excluded, and it allows the user to create some general purpose exclusion reasons. The reasons created in this pane can be selected in the exclusion reason window's drop-down table and can help to expedite the exclusion process when many coverage points are being excluded for the same reason. shows the layout of this preference pane.
Exclusion Preferences Pane
Enable exclusion reason support when items are excluded If this option is enabled, whenever the user clicks on a coverage point to cause it to be excluded from coverage, a popup window will be displayed, allowing for an exclusion message to be associated with the excluded coverage point. If this option is not enabled, the coverage point will still be excluded but no exclusion message will be associated with it. If a coverage point was excluded and is selected to be included and the coverage point had an exclusion message associated with it, the exclusion message will be forgotten/deleted. Create General Exclusion Reasons This frame allows the user to add/delete general purpose exclusion reasons that can be selected from within the exclusion reason popup window's drop-down table. Having these reasons specified can help to speed up coverage point exclusion when multiple coverage points need to be excluded for the same reason. To add a new general purpose exclusion reason, simply type in the general purpose exclusion reason in the bottom textbox (note that any formatting characters such as newlines, tabs, extra spaces will be removed from the exclusion message) and click the "+" button. You will see the exclusion reason get added to the table when this occurs. Note that the "+" button will only be enabled when you have entered at least one character in the textbox. To remove a general purpose exclusion reason from the table, simply click on the reason in the table and click the "-" button. Note that the "-" button will only be enabled once an entry has been selected in the table. To help find an exclusion reason more easily within the exclusion reason popup window, you may also rearrange the order of the exclusions within the table by simply clicking on an entry and dragging it to the desired location. The order of the exclusion reasons specified in this table will be the initial order of the exclusion reasons in the popup window. Preference Merging Pane The merging pane is needed to specify to Covered how to resolve conflicts that are found when merging CDD files. Although coverage points and exclusions are simply merged (ORed) together, things such as exclusion reasons can exist for the same coverage point but contain different information. When two exclusion reasons are given for the same coverage point, Covered must decide how to resolve this information and this preference pane allows the user to set what this behavior will be.
Merging Preferences Pane
Exclusion Reason Conflict Resolution Frame This frame allows the user to specify the way in which exclusion reason conflicts should be resolved. The following options are provided: Use the first reason Specifies if two or more exclusion reasons are found for the same coverage point, Covered should use the exclusion reason found in the first CDD file merged. The rest of the exclusion reasons are thrown away. Use the last reason Specifies if two or more exclusion reasons are found for the same coverage point, Covered should use the exclusion reason found in the last CDD file merged. The rest of the exclusion reasons are thrown away. Use the newest reason Specifies if two or more exclusion reasons are found for the same coverage point, Covered should use the newest exclusion reason (when an exclusion is created, a timestamp is saved along with the coverage reason). The rest of the exclusion reasons are thrown away. Use the oldest reason Specifies if two or more exclusion reasons are found for the same coverage point, Covered should use the oldest exclusion reason. The rest of the exclusion reasons are thrown away. Merge all reasons Specifies if two or more exclusion reasons are found for the same coverage point, Covered should merge all of them. No information is lost in this case. covered-0.7.10/doc/docbook/chapter_gui_rank.xml0000644000076500007650000004104011055051326021453 0ustar trevorwtrevorw Creating a CDD Ranking Report Generating a ranking report (see for more information) can be accomplished in the GUI by either selecting the Rank CDD Coverage button in the Wizard window (see for details), selecting the File -> Generate -> CDD Ranking Report... menu option, or using the keyboard shortcut Shift-Cntrl-C. Any of these actions will cause the CDD ranking report wizard window to be started. The following subsections describe the various windows used to create a CDD ranking report file. Note that the CDD ranking wizard uses several "pages" to describe the various options to set for creating a CDD ranking report file, using Back and Next buttons on each page for navigation. Clicking on the Back button will not cause previously filled in pages to be reverted to their default values but rather will remain populated with the user's data. Similarly, if a page has been filled in with data and the Back button is clicked and then the Next button is clicked, the page contents are retained. The only way to clear out fields is to click the Cancel button at the bottom of each page and startup the CDD ranking wizard again. Clicking the Cancel button at any time will cause the CDD ranking wizard to immediately exit. Clicking on the help (?) button at any time will bring up the user documentation for the current page (context sensitive help). CDD Ranking Option Selection Page Figure shows the look of this page of the CDD ranking wizard.
CDD Ranking Option Selection Page
The first page of the CDD ranking wizard allows the user to select whether all options should be interactively selected within the GUI or if a file should be read in which contains command-line options to the rank command to use. If the latter is chosen, the contents of that file are read in and are populated in the GUI, but the CDD ranking wizard will continue in the same fashion as the first option, allowing the user to change, remove or add to the options found in that file. If the Create CDD ranking by interactively selecting options entry is currently selected and the user wishes to not use a command-line file to populate the rest of the CDD ranking pages, simply click on the Next button at the bottom of the page to continue. If the Create CDD ranking by using option file entry is currently selected, the user must either type a valid filename or select one by clicking the Browse... button to the right of the file entry area and select a valid file. Once a valid filename is selected, the Next button will be enabled and the user may then click it to continue to the next page. Note that any filename can be selected (whether it's a valid command file or not). Only valid rank command options found in that file are used to populate the wizard entries. No error message will be displayed if the file does not contain this information. CDD Ranking Option Page This page of the CDD ranking wizard allows the user to specify certain options to the ranking command when it is run. The following subsections document each option within this window.
CDD Ranking Options Page
Output ranking report name This option is a required field to fill in before the rank command can be run. Simply specify a filename in the entry box or use the Browse... button to help create a filename to save the ranking report file to. The Next button will not be enabled until a filename has been specified in the entry box. Coverage metric weighting The checkboxes within this frame allow the user to specify an importance value for each coverage metric. The allowed values within the entry box for each metric is a value greater than zero, where all values are relative to each other. In other words, if the weight for line coverage is set to a value of 10 and the weight of toggle coverage is set to a value of 1, it indicates that line coverage should be considered 10x more important for coverage selection purposes than toggle coverage. Changing the various weight values can have an impact on which CDD files are chosen to be included in the "need to run" list and/or the order in which CDD files should be run to maximize the coverage obtained. By default, all metrics are included (except for assertion coverage) and are given a weight value of 1 (all coverage metrics are considered to be equally important for ranking purposes). To remove a metric from ranking consideration, simply uncheck the checkbox to the left of the metric line. Generating only names When a CDD ranking report is generated, the report contains header information and a columnar list of accumulated and per CDD ranking information. If the user is only interested in creating a report that includes the names of the CDD files that are needed to run (and the order to run these CDD files in), checking this option will produce just that, allowing for easier usage in Makefiles or other commands needed to run regression runs. Displaying verbose information when running rank command When the ranking order is being generated, there is output from the rank command concerning the filenames that are being read and when the command is writing to the output file; however, if you would like to know more information about what's going on "under the hood", enabling this option will cause more verbose information to be reported in the output screen, including the amount of time spent executing each phase of the rank process, the number of files selected for ranking in each phase, the number of coverage points hit by selected CDD files for each phase and the number of files excluded from ranking. Leave this box unchecked if this information is not important/interesting to you. CDD Ranking Input File Selection Page This page allows the user to add all of the CDD files to rank. Since the GUI CDD ranking generation command can be run at any time (even when no CDD files have currently been loaded), the input files to the rank command can be any valid CDD file that can be merged with each other. As can be seen in the following figure, the window is comprised of a filename listbox in the upper left-hand corner of the page, several buttons that allow for various file selection strategies on the right-hand side of the page, a current file count information bar beneath the listbox, a button to allowing saving the currently setup ranking options to be saved to a file, a button to save any selected "required" CDD files to a file, and a Generate button in the bottom navigation bar.
CDD Ranking Input File Selection Page
Adding CDD files Adding CDD files to be ranked is performed by clicking on one or more of the buttons on the right-hand side of the page. When files are added to the input file listbox, the current number of CDD files in the listbox are reported in the information bar beneath the listbox. Next to each filename specified in the input file listbox is a checkbutton that specifies if the associated CDD file should be considered a mandatory CDD file to be ranked (i.e., it cannot be excluded from the list of CDD files that should be run during regression to achieve full coverage). This checkbutton can be set/cleared at any time for any CDD file in the listbox. The following are the various ways that CDD files can be added to or removed from the input file listbox. Add File(s) Clicking this button will bring up a file selection box that will allow the user to select one or more files that will will be added to the input file listbox with the "Required" field left unchecked. This option is useful for selecting certain files within one or more directories to rank. Add CDDs from Directory Clicking this button will bring up a directory selection box that will allow the user to specify a directory to load CDD files from. Only files with the ".cdd" extension that exist in this directory will be added to the input file listbox. Add Currently Opened Clicking this button will add any CDD files that are currently opened within the GUI into the input file list. Add Required CDD File(s) Clicking this button will bring up a file selection box that will allow the user to select one or more files that will be added to the input file listbox with the "Required" field checked. Add Required CDDs from List Clicking this button will bring up a file selection box that will allow the user to select a file that contains a list of CDD files to be required for ranking (files will be added into the input file listbox with the "Required" field checked). Delete When one or more CDD files are selected in the input file listbox, the Delete button will be enabled. Clicking this button will remove the selected files from the input file listbox. The information bar displaying the number of currently selected CDD files will be updated accordingly. If desired, any CDD files listed in the input file listbox can be moved to change the order of the input files. However, it should be noted that the input file order will not necessarily have any impact on the CDD ranking order list. Saving the CDD ranking options If the user wishes to save the current option/file list setup, click on the Save Options to File... button. This will cause a file save window be displayed where a filename can be chosen and saved to by clicking on the Save button in this window. To cancel the option save, click on the Cancel button in that window. The generated options file can be used in the window or in the command-line call to the rank command's -f option. Save Required CDDs to File... If one or more files are labeled as "Required" in the input file listbox, this button will be enabled. Clicking on this button will bring up a "Save As" file selection box. Specifying a filename and clicking on the "Save" button will cause a file by that name to be created that contains a list of all of the CDD files listed as "Required". This file may be used at a later time via the -required-list option to the rank command (if using the rank command on the command-line) or by clicking on the Add Required CDDs from List button in the rank command wizard input file selection page. Generating the CDD ranking report After all of the input files have been included (you must include more than one to create a CDD ranking report), the Generate button will be enabled, click on this button to advance to the next page in the CDD ranking wizard where the CDD ranking report command will be run and its output displayed. CDD ranking Command Output Page
CDD Ranking Command Output Page
The above figure shows an example of output displayed to the CDD ranking command output page. The purpose of this page is to show you the results of the rank command run. If any errors occurred during this run, the output from those errors will be displayed within this page. If the command ran successfully, the Finish button will be enabled at the bottom of the screen. Additionally, the View the ranking report in the GUI button will be enabled. When clicked, this button will display the created report file in a file viewer which may be read and searched. Click on the window manager "X" button to close the file viewer window. The following figure shows an example of the file viewer window and an example of the report output.
CDD Ranking Report Page
When the user has successfully generated a CDD ranking report, clicking the Finish button will close the CDD ranking report window. covered-0.7.10/doc/docbook/chapter_gui_report_gen.xml0000644000076500007650000003317611054713225022701 0ustar trevorwtrevorw Creating an ASCII report file Though Covered's graphical coverage analyzer is very useful for examining coverage, there may still be times when a textual report is necessary. For that purpose, the GUI has a menu item for generating an ASCII coverage report, running Covered's "report" command on the currently loaded coverage information. The ASCII report generator options are only available if one or more CDD files are currently loaded in the GUI. When the File -> Generate -> ASCII Report menu option is selected (or the "Cntrl-Shift-R" shortcut is used), the ASCII Report Generator Window is created to allow the user to specify the current report output options and generate the report file. Once the report has been generated, it can be viewed within the GUI itself or it can be viewed with any type of file viewer/editor available. The following subsections describe the various windows used to create a report file. Note that the report generation wizard uses several "pages" to describe the various options to set for creating a new report file, using Back and Next buttons on each page for navigation. Clicking on the Back button will not cause previously filled in pages to be reverted to their default values but rather will remain populated with the user's data. Similarly, if a page has been filled in with data and the Back button is clicked and then the Next button is clicked, the page contents are retained. The only way to clear out fields is to click the Cancel button at the bottom of each page and startup the report generation wizard again. Clicking the Cancel button at any time will cause the report generation wizard to immediately exit. Clicking on the ? button at any time will bring up the user documentation for the current page (context sensitive help). Navigating the Report Generator Selection Page shows the look of this page of the report generation wizard.
Report Generation Option Selection Page
The first page of the report generation window allows the user to select whether all options should be interactively selected within the GUI or if a file should be read in which contains command-line options to the report command to use. If the latter is chosen, the contents of that file are read in and are populated in the GUI, but the report generation wizard will continue in the same fashion as the first option, allowing the user to change, remove or add to the options found in that file. If the Create report by interactively selecting options entry is currently selected and the user wishes to not use a command-line file to populate the rest of the report generation pages, simply click on the Next button at the bottom of the page to continue. If the Create report by using option file entry is currently selected, the user must either type a valid filename or select one by clicking the Browse... button to the right of the file entry area and select a valid file. Once a valid filename is selected, the Next button will be enabled and the user may then click it to continue to the next page. Note that any filename can be selected (whether it's a valid command file or not). Only valid report command options found in that file are used to populate the wizard entries. No error message will be displayed if the file does not contain this information. Report Generation Options Page This wizard page allows you to setup the options to create the needed report. Figure shows the contents of this page.
Report Generation Options Page
The options page is split into several different categories of options: Set ASCII Report Generation Options Level of Detail Accumulate By Coverage Type Show Metrics Set ASCII Report Generation Options Limit line width to X characters If this option is checked, the number of characters that will be displayed per line when outputting design logic will be limited to the number of characters specified in the entry box. If this option is unchecked, the length of the output design logic will be determined by the way the logic was formatted in the design file. This option can be useful for printing purposes where a logic design file contains logic that is formatted to exceed the number of characters than can be printed on a page or viewed on a screen. Suppress modules/instances from output if they contain no coverage information If this option is checked, any modules (or instances) that were considered for code coverage but did not contain any coverable code will be excluded from the report. If this option is unchecked, all modules/instances will be reported. This option may help make the report files easier to view if there are many modules/instances that do not contain coverage points. Output combinational logic vector operations in bitwise format Outputs combinational vector logic expressions in bitwise format instead of treating the vector as a 0 or "not 0" value. This can create quite a bit of extra output when creating verbose reports, but can provide the information for a more thorough analysis for these expression types. This option has the same effect as the -b option to the report command. Level of Detail These radiobuttons control the level of detail that is output in the generated report. Only one value can be selected for the three available detail values: Summary Detailed Verbose See for information on the difference between these three options. Accumulate By These radiobuttons control whether coverage information is accumulated by instance or by module. Only one value can be selected for the two available options. See for information on the difference between these two options. Coverage Type These radiobuttons control whether covered or uncovered coverage points are output in the report. Only one value can be selected for the two available options. See for information on the difference between these two options. Show Metrics These checkbuttons control which coverage metric information is output in the generated report. You may select any number (or combinations) of these options. All of the metrics available for viewing in the GUI can be output to a report file, including: Line Toggle Memory Combinational Logic FSM Assertion Race Conditions This item, though it is not a coverage metric, can be useful for understanding what logic was not considered for coverage due to violating the static race condition checks and what check was violated for each block. Save Options to File... Once the above options have been specified, it can be useful to save those parameters to a file which can be loaded at a later time in the page of the GUI report generation wizard. This same file can also be fed "as is" into the Covered's command-line report command via the -f option. Click on this button to open a "Save As" window where you can create a filename to save this information into. Click on the Save button of this window to exit the window and save the information. Click on the Cancel button to abort this action. Output report to file frame This frame of the ASCII Report window allows the user to specify a filename/location for the generated output file. By default, the report name is the same as the first CDD file loaded, substituting the .cdd extension for a .rpt extension. By default, the directory location to store the generated report is the same directory that the first CDD file exists in. To change this name/location, the user may either enter a value in the entry field or click on the Browse... button to display a "Save As" type window. View the report in the GUI after it is created Selecting this option will cause a window to open after the report has been generated which will contain the contents of the generated report in a read-only view. You can search in this window and scroll to help view the entire document. Once you have completed setting everything up as you need, click on the Create button to generate the report file. If everything worked, the report generation window will close and, if enabled via the selector, a file viewer window will be displayed with the contents of the newly generated report file. Click on the "X" button in the window manager to close this window when you have finished with it. covered-0.7.10/doc/docbook/chapter_gui_toggle.xml0000644000076500007650000001366011061564253022015 0ustar trevorwtrevorw Navigating the Toggle Coverage Window The verbose toggle window allows the user to see which bits for a given signal have toggled from a 0->1 or a 1->0 during simulation. To display this window, simply click on a highlighted/underlined uncovered signal in the file viewer of the main window. This will cause the verbose toggle viewer to be created for the specified signal as well as display a "-->" symbol in the Coverage Viewer on the same line as the selected signal. This symbol is simply meant to help the user identify in the Coverage Viewer which signal is currently displayed in the Toggle Viewer window. shows the Toggle Viewer loaded with a 4-bit signal called "err_vec" in which bits 3:2 have successfully toggled from a 0->1.
Verbose Toggle Window
Understanding the Layout The bit vector displayed is a binary bit vector, each value (0 or 1) represents whether that bit in the signal either toggled (1) or did not toggle (0) during simulation. There are two bit vectors displayed for the signal, the top vector shows the 0->1 toggle information while the bottom vector shows the 1->0 toggle information. The name of the signal along with its MSB:LSB information is displayed at the bottom of the window; however, if the mouse cursor is placed over a specific bit in the toggle box, the MSB:LSB will be changed to show the displayed bit, making it easy for the user to discern exactly which bit has toggled/not toggled. If the width of the signal exceeds the given space for the toggle window, a scrollbar will be allowed to slide left and right to view the rest of the toggle information. To exit this window, simply click on Close button. To see this help page from the toggle window, click on the help (?) button. Excluding/Including a Signal for Toggle Coverage The user may exclude/include any uncovered signal in the design for toggle coverage by simply clicking on the Excluded checkbutton. If this checkbutton is checked, the exclusion reason popup window will be displayed, allowing the user to specify a reason for excluding this signal from toggle coverage. Once a reason has been specified, the summary coverage information will automatically be recalculated and redisplayed in the listbox and the background color of the underlined signal in the file viewer will change from the uncovered background color to the covered background color. However, the signal will still remain underlined, allowing the user to see the verbose toggle coverage information, if necessary. If the Excluded checkbutton is unchecked, the summary coverage information and background colors will be readjusted to include the coverage information for this signal. If the user excludes any signal for toggle coverage in the design, the Save CDD... option in the file menu will be enabled. This allows the user to save the excluded property either back to the CDD file (or to a newly named CDD file). Doing so will allow the user to load the CDD file at a different time and retain the knowledge of which signals have been excluded/included for toggle coverage. Additionally, if a saved CDD file with coverage exclusion is merged with another CDD file, the excluded signal information is preserved for the resulting merged CDD file. If a signal has been excluded from coverage and an exclusion reason was specified, you can view the reason for exclusion by right-click-and-holding on the Excluded checkbutton. This will cause a tooltip-style window to be displayed specifying the reason for exclusion. The background color of the tooltip will be the same color as the "covered" background color to help distinguish it from a normal tooltip. To cause the exclusion reason tooltip to disappear, simply release the button. Displaying a New Signal for Toggle Coverage If the Verbose Toggle Coverage window is currently displayed with a signal, the user may select a new signal in the file viewer of the Main window. When a new signal is selected, its value immediately replaces the currently selecting signal value. This feature allows many different signals to be viewed one after the other without having to create/destroy a new window for each signal. The user may also see the previous or next uncovered signal in the main viewer by clicking either the left arrow button (for previous signal viewing) or the right arrow button (for next signal viewing). Note that the left arrow button will be disabled if there is not a signal previous to the current signal in the given module and the right arrow button will be disabled if there is not a signal after the current signal in the given module. covered-0.7.10/doc/docbook/chapter_gui_wizard.xml0000644000076500007650000000545711055051326022034 0ustar trevorwtrevorw Navigating the Wizard Window The Wizard window starts up automatically at the start of the Covered GUI. It allows the user to quickly perform some of the more regular tasks within the GUI. The window is not necessary for performing these tasks, but for the new user it makes figuring out how to perform these tasks a bit easier. shows the layout of this window.
Covered GUI Wizard Window
The buttons at the top of the window are shortcuts to performing the tasks displayed on the button. Clicking the associated button will cause a window to open to perform the given task. The following are the available shortcut buttons: Generate New CDD File Allows the user to create a new CDD file for a given design by specifying the various scoring options needed to create the CDD file. Open/Merge CDD File(s) Opens a CDD file for coverage viewing. If one or more CDD files have previously been opened, this option opens and merges one or more CDD files with the coverage results of the previous CDD files for coverage viewing. Rank CDD Files Allows the user to specify CDD files that will be compared with one another and ranked in the order that they should be run in a regression to achieve the most coverage in the least amount of time. It also indicates which CDD files do not add any interesting coverage information and could, therefore, be excluded from regression for the purposes of code coverage. At the bottom of the wizard window, there is a checkbutton option that allows the user to not display the wizard window on startup. This option can be changed in the at any time. When the wizard window is closed, it can be redisplayed by clicking on the View > Wizard... menu item. The window will automatically be closed when a button on the wizard window is clicked or when the user closes the window with the window manager's "X" button. covered-0.7.10/doc/docbook/chapter_installation.xml0000644000076500007650000002167211054636164022376 0ustar trevorwtrevorw Installation Prerequisites The goal of Covered was to create a tool that has very few requirements to allow it to be compiled and run on all platforms. The following is a list of all utilities/resources required to compile Covered. However, Covered is primarily developed on RedHat/Fedora Core Linux and Mac OS X and as such is primarily tested by the developers on these platforms. gcc (Version 2.96 or higher) flex (Version 2.5.4 or higher) bison (Version 1.28 or higher) GNU make (Version 3.27.1 or higher) GNU gperf (Version 2.7.2 or higher) Tcl/Tk (Versions 8.4 or higher) tablelist Tcl/Tk widget (Version 4.9 or higher) Covered is primarily developed on Fedora Core but has been known to compile with both 32-bit and 64-bit compilers that contain the general GNU library of tools. It has also been compiled and run on Cygwin and Mac OS X. Downloading source To download the source files in .tar.gz format, go to the following URL: http://covered.sourceforge.net/downloads/ Double-click on the .tar.gz version that you wish to install. The browser should immediately bring up a window asking if you would like to save to disk or open immediately. Choose the "Save to Disk" option. Another window will pop up, allowing you to choose the directory to store the tarball in. After selecting a directory, click the "Save" button. The download utility will begin downloading the tarball to the selected directory. Once you have downloaded a tarball, enter the following to unzip and untar the package: > gzip -dc tarball_filename | tar xvf - This will create a directory called covered-version, where version will be of the form major version.minor version for stable releases or date for development releases. Enter that directory to begin configuring, building and compiling Covered from source. Configuring the build At this point, you are ready to configure the build environment to create the executables, libraries and/or documentation for Covered. However, before you configure the build environment, you will need to make a few decisions which will lead to different options given to the configure script. These questions are the following: Do you need to debug Covered? (for most users, the answer to this will be "no") If the answer to this question is yes, configure the build environment with the --enable-debug option to the configure script. Doing so will allow you to use the global -D option and/or the -cli () score command option for debugging; however, it will also have the side effect of causing the score command to run noticably slower. For normal usage of Covered, this option should not be specified when configuring. Do you want to profile Covered's internal functionality? (for most users, the answer to this will be "no") If the answer to this question is yes, configure the build environment with the --enable-profiling option to the configure script. Doing so will allow you to use the global -P option to generate an output file containing internal profiling information for the run command. See for more information on the -P option. Will you being using Covered as a VPI module and, if so, what simulator(s) will you need VPI modules built for? If the answer to this question is yes and you need to build a VPI module for the Icarus Verilog simulation tool, simply add --with-iv on the configure command-line. If a VPI shared object module is needed for the Cver simulator, simply add --with-cver=cver_include_dir on the configure command line, where cver_include_dir specifies the directory that contains the vpi_user.h file. If a VPI shared object module is needed for the VCS simulator, simply add --with-vcs=vcs_include_dir on the configure command line, where vcs_include_dir specifies the directory that contains the vpi_user.h file. Do you want to use Covered's Tcl/Tk GUI for interactive coverage analysis or just the command-line created reports? If the answer to this question is yes and you have a Tcl/Tk distribution that the configure script cannot find (i.e., the tcl-config and tk-config scripts exist in a non-standard directory location), please specify the --with-tcl-config=tcl-config_pathname and --with-tk-config=tk-config_pathname options to the configure script. If the answer to this question is no, specify the --with-tcltk=no option to the configure script to cause the GUI to not be built. Once you have determined which configuration options you need, simply enter the following command: > ./configure options This command will create the Makefiles/include files necessary for your machine to compile the source code correctly. If any errors are generated during this command run, it is usually an indication that some program or library is missing from your computer that is necessary for Covered to compile/run. Please install any missing programs/libraries and type this command again. Compiling and Installing If the configure script completes successfully, you may compile the source with the following command: > make This will begin the process of compiling/linking the source code for Covered. This stage may take a while. When the source files have been compiled, the covered executable file will have been created. To install this executable in your /usr/local/bin directory, enter the following command: > make install This will install the covered executable and manpage help files. Once covered is installed, make sure that /usr/local/bin is in your environment path. You are now ready to run Covered. covered-0.7.10/doc/docbook/chapter_intro.xml0000644000076500007650000001454711472127327021033 0ustar trevorwtrevorw Introduction What is Covered? Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test (DUT). It is command-line based with an optional Tcl/Tk GUI report viewer, making it portable across almost all platforms. What can code coverage do? Typically, in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document. When the test suite contains all of the tests required by the design specification, the test writer may ask: "How much logic in the design is actually being exercised?" "Does my test suite cover all of the DUT?" "Am I done writing tests for the logic?" "Do I have any redundant diagnostics in my test suite?" When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful. The metrics obtained by using a code coverage analysis tool can be very useful for determining the following about a design and the test suite testing that design: Completeness of the test suite in terms of logic coverage. Unexercised logic in the design (useful in helping to determine what types of tests need to be added to the test suite). Corner cases in design that are untestable. What can't code coverage do? It is important to note that any code coverage tool is only useful in indicating how much logic is being covered by a test suite. It does not indicate that the covered logic works appropriately. This, of course, can only be verified by the diagnostics themselves. Additionally, it is possible that two or more diagnostics can achieve the same coverage and yet be functionally testing different characteristics of a design. Since the coverage metrics are not improved in this case, one may conclude that the second test is unnecessary. This may or may not be true depending on what is being tested; it is always up to the test writer to determine the necessity of a diagnostic. Using the code coverage tool results as the sole means of making this determination is not recommended. Use common sense in these areas. What does Covered do? Covered is a tool that uses your design files along with standard VCD, LXT2 or FST dump files to analyze the code coverage of the DUT. The code coverage information is stored in a special database file that can be retrieved and "merged" with new coverage information to create a summed coverage total for several tests. After a database file has been created, the user may generate various ASCII reports that summarize the coverage information or run Covered's GUI to interactively analyze the coverage information. Additionally, multiple CDD files from the same design can be ranked for the purposes of running regressions and understanding which CDD files do not add coverage information and can be excluded from regressions runs, if needed. What does Covered NOT do? Though Covered does perform some resimulation of the design to derive line, combinational logic, memory, and assertion coverage, Covered is NOT a full-fledged compiler/simulator and should not be used for such purposes. Additionally, Covered is NOT a linting tool. Many syntax/semantic issues that are not allowed by the LRM are allowed by Covered for purposes of making Covered's core more generic and/or simplistic. Please make sure that your code is properly linted in your design flow using an appropriate tool. What makes Covered different? Most Verilog code coverage tools perform a pre-compilation procedure known as instrumenting. During this procedure, the coverage tool will read in the DUT and generate its own version of the DUT with additional code added to aid in calculating coverage after the simulation is complete. The benefits to this style are higher performance of the coverage tool when it is run after the simulation. The drawbacks to this approach are that it slows down simulation speed and a trust issue that the coverage tool did not alter your simulation model when it performed the instrumentation. Covered, on the other hand, omits the instrumenting procedure all-together and only performs its analysis on a pre-simulated design. This means that Covered cannot make a mistake to your simulation and the simulation is allowed to run faster since there is no additional code that must be run to get coverage data. The drawback is that there is some overhead in post-simulation for extracting coverage data but this is typically less than the simulation overhead in the other method. Additionally, unlike all other commercial coverage tools, Covered is free! No license managers to invoke and maintain. No licensing fees and negotiations. The only thing the developers of Covered want in return are bug reports and user input (and perhaps a donation if you find the software useful and want to see its development continue). Isn't the open source life grand?! covered-0.7.10/doc/docbook/chapter_merge.xml0000644000076500007650000002664011111060031020746 0ustar trevorwtrevorw The merge Command Usage The merge command is initiated with the following call: covered merge [options] existing_CDD CDD_to_merge+ The existing_CDD specifier relates to any existing CDD. If the -o option is not specified (see below for details), this file will be replaced with the merged CDD created by the merge. This is important to remember since merging is an irreversible operation (apart from generating a brand-new CDD from the design and dumpfile using the score command). The CDD_to_merge specifier relates to any existing CDD that is not the existing_CDD. Though it is not illegal to merge the same CDD to itself, the result is the same as the original CDD. Note that all files treated as CDD_to_merge are guaranteed not to be modified by the merge command. These files are only read by Covered and then merged into the information contained in the existing_CDD. Options Options to merge Command Option Description -d directory Directory to search for CDD files to include. This option is used in conjunction with the -ext option which specifies the file extension to use for determining which files in the directory are CDD files. -er (first|last|all|new|old) Specifies how to handle exclusion reason resolution. If two or more CDD files being merged have exclusion reasons specified for the same coverage point, the exclusion reason needs to be resolved (unless it is the same string value). If this option is not specified and a conflict is found, Covered will interactively request input for each exclusion as to how to handle it. If this option is specified, it tells Covered how to handle all exclusion reason conflicts. The values are as follows:
Value Description first The CDD file that contained the first occurence of the exclusion should use its reason in the merged CDD file. last The last CDD file that conflicts with a previous CDD file should use its reason in the merged CDD file. all All conflicting coverage points will merge their exclusion reason information into a single exclusion reason. new The newest exclusion reason should be used (all exclusion reasons are timestamped). old The oldest exclusion reason should be used (all exclusion reasons are timestamped).
-ext extension Used in conjunction with the -d option. If no -ext options are specified on the command-line, the default value of '.cdd' is used. Note that a period (.) should be specified. -f filename Name of file containing additional arguments to parse. You may specify this option more than once on a command-line. -h Outputs usage information for the merge command. -m message Allows the user to specify information about this CDD file which can be most anything. All messages found in merged CDDs will not be included in the merged CDD file. -o filename Name of CDD to write merged coverage information to (if not specified, the existing_CDD is overwritten with merged CDD). Merging Rules In previous versions of Covered, merging could only be accomplished when the top-most scored modules of each CDD were the same the module. Typically, the user would score the entire DUT in each diagnostic run, creating a set of CDD files that could be merged together to see the overall coverage of the diagnostic runs. While this capability still exists, Covered has recently been enhanced to allow more complex merging which provides some new capabilities. Block Merging Covered's merging algorithms have now been enhanced to allow merging CDDs that are generated for different parts of the same DUT. That is to say that each instance or sub-tree in the design can be scored individually and can be merged together. This ability allows for the DUT to be split up into smaller parts, scored in parallel and then merged back together to create a single CDD containing the scored results for the entire DUT. This parallel scoring capability can now be used to speed up scoring of large designs by taking advantage of multiple CPUs or CPU cores. The following is an example of a DUT (top-most module of the DUT is block A) and the generic covered calls to score and create a single CDD file containing coverage for the entire design.
Example of Verilog hierarchy to be scored in parallel
The following commands could be used to score the DUT comprised of blocks A-G in parallel (each score command below could occur in parallel with all other score commands). covered score -t A -i MAIN.A -e B -e C -o A.cdd ... covered score -t B -i MAIN.A.B -e D -e E -o B.cdd ... covered score -t C -i MAIN.A.C -e F -e G -o C.cdd ... covered score -t D -i MAIN.A.C.D -o D.cdd ... covered score -t E -i MAIN.A.C.E -o E.cdd ... covered score -t F -i MAIN.A.B.F -o F.cdd ... covered score -t G -i MAIN.A.B.G -o G.cdd ... covered merge -o total.cdd A.cdd B.cdd C.cdd D.cdd E.cdd F.cdd G.cdd In addition to allowing for parallel scoring, this merge method allows users to gain coverage results for smaller parts of the design and merge them into a single CDD containing coverage results for the entire design. This can be advantageous for those that are focused on increasing coverage for a specific portion of the design. Scoring can be done on that small part and the coverage gained can be added into an existing CDD containing coverage information for the entire design. Using this type of merging would be performed as such: covered score -t A -i MAIN.A total.cdd // The initial coverage file for the entire design covered score -t C -i MAIN.A.C -o CDE.cdd ... // Coverage obtained for modules C, D and E only covered merge total.cdd CDE.cdd Single Module Merging Along with the capability to merge different portions of the same large design, it is also possible to merge CDDs that were generated from different testbenches but have modules that are in common with each other. This allows different teams to work together to enhance coverage for shared design blocks. It is important to note that when this type of merging is being performed that the top-most covered module in the CDDs labeled CDD_to_merge exist exactly once in the CDD labeled existing_CDD for instance coverage information to be reported correctly. If the module is instantiated more than once in the existing_CDD, the CDD will still be merged but only the module coverage information will be correct. covered-0.7.10/doc/docbook/chapter_metrics.xml0000644000076500007650000005031411061140437021325 0ustar trevorwtrevorw Coverage Metrics Covered currently generates six types of code coverage metrics. Line Coverage Description Line coverage simply answers the question, "Was this line of code executed during simulation?" Covered will display the number of logical lines of code that exist in a particular file with the number of logical lines that were executed during the simulation along with a percentage indicating the percentage of lines executed. If verbose mode is selected for a report, Covered will display the lines of logic that were not executed during the simulation run. Example Suppose that the following module was specified in your DUT that is being analyzed: Line Coverage Code Sample module test; reg a, b, c; initial begin a = 0; // Line 1 b = 1; // Line 2 if( a ) c = b; // Line 3 else c = ~b; // Line 4 end endmodule If this code were simulated as stated, the simulator would execute lines 1 and 2, and due to the value assigned to a, line 4 would be executed. This means that during execution, out of a possibility of 4 lines, only 3 were executed. Therefore, Covered would state that for this module the line coverage percentage would be 75% (or 3 out of 4). Recommendations For a design to pass full coverage, it is recommended that the line coverage for all modules in a design receive 100% coverage. If a line of logic is not executed during simulation, the design has not been fully exercised. Line coverage is useful for determining holes in the test suite. Toggle Coverage Description Toggle coverage answers the question, "Did this bit of this wire/register change from a value of zero (0) to one (1) and back from one (1) to zero (0) during simulation?" A bit is said to be fully covered when it toggles back and forth at least once. This metric does not indicate to the user that every value of a multi-bit vector was seen. For example, if we have a two bit vector called "foo", toggle coverage will not tell you that the value of foo was set to the values of 0, 1, 2 and 3. However, it will tell you that all bits in that vector were toggled back and forth. Example Suppose that a DUT was comprised of the following module: Toggle Coverage Code Sample module test; reg [2:0] a; initial begin a = 3'b0; #10; a = 3'b110; #10; a = 3'b010; #10; end endmodule The register called "a", after being simulated, would have achieved a total toggle percentage of 50% (or 3 out of 6). Can you see which toggles are missing? Bit 0 has never toggled to 1 (and has never been at a value of 1 and toggled to 0); therefore, bit-0 has toggled 0% (0 out of 2). Bit 1 has toggled from a value of 0 to 1, but has not toggled from a value of 1 to 0; therefore, bit-1 has toggled 50% (0 out of 2). Bit 2 is the only bit that has fully toggled, achieving a toggle percentage of 100% (2 out of 2). If you add all of the possible toggles to the number of achieved toggles, you end up with 3 out of 6 (or 50% total toggle coverage). Recommendations For a design to pass full coverage, it is recommended that the toggle coverage for all modules in a design received 100% coverage. If a bit is never changes value, it is usually an indication that a mode is not being exercised in the design or a datapath has a stuck-at issue. Memory Coverage Description Memory coverage answers a number of questions about memories/multi-dimensional arrays being used in your design, including the following: Did all bits of each addressable memory element toggle from 0 to 1? Did all bits of each addressable memory element toggle from 1 to 0? Did every addressable memory element get written? Did every addressable memory element get read? Memories/multi-dimensional arrays can have two types of dimensions, packed and unpacked. Packed dimensional information is specified to the left of an array declaration while unpacked dimensional information is specified to the right of an array declaration. Consider the following example: Memory Coverage Code Sample reg [3:0][2:0] foo[0:15]; The memory "foo" consists of three dimensions. The first dimension is an unpacked dimension which specifies that there are 16 addressable memory elements (AME). The number of AMEs are determined by multiplying the unpacked dimension of an array. The second two dimensions are packed dimensions, creating a total of 12 bits for each AME. Other than getting toggle coverage information for each AME, memory coverage also allows us to easily see which AMEs were written and read during simulation. If all entries of a memory have not been written during a regression run, it could indicate several shortcomings of either the testbench or a logical problem with the write control logic, including, but not limited to, the following: If no AMEs for a given memory were written, it could indicate that the testsuite was never able to get out of bypass mode for that memory. If fewer AMEs for a given memory were written than were read, it could indicate that there is a read controller issue leading to an underflow issue with the memory. For memories that act like stacks or use lowest/highest address first write selection scheme, indicates that the memory was never completely filled (may miss out on things like buffer overflow errors). For memories that are written in a round-robin fashion, indicates that either not enough entries were written (could miss a write pointer wrap bug) or that there is a logical issue by which the write pointer did not properly increment in a round-robin fashion. If there are "holes" in the write coverage of the AMEs (that is an AME is found to not have been written while those above and below it have been), this could indicate a corner case logic bug or other testsuite issue that needs to be addressed. If all entries of a memory have not been read during a regression run, it could indicate several other shortcomings of either the testbench or a logical problem with the read control logic, including, but not limited to, the following: If no AMEs for a given memory were read, it could indicate that the testsuite was never able to get out of bypass mode for that memory. If fewer AMEs for a given memory were read than written, it could indicate that a resource allocation issue. For memories that are written in a round-robin fashion, indicates that either not enough entries were read (could miss a read pointer wrap bug) or that there is a logical issue by which the read pointer did not properly increment in a round-robin fashion. If there are "holes" in the read coverage of the AMEs (that is an AME is found to not have been read while those above and below it have been), this could indicate a corner case logic bug or other testsuite issue that needs to be addressed. Currently, Covered simulates all memories/multi-dimensional arrays and its coverage is automatically accumulated during the score command. To see its report information, either specify the -m m option to the report command or bring up the GUI for interactive analysis. Recommendations For a design to pass full coverage, it is recommended that the write/read memory coverage for all modules in a design receive 100% coverage. If every AME was not both written and read during simulation, the design has not been fully exercised. Toggle coverage per AME need not receive 100% since a memory element that is written once will not cause toggle coverage to change. Combinational Logic Coverage Description Combinational logic coverage answers the question, "What values did an expression (or subexpression) evaluate to (or not evaluate to) during the course of the simulation?" This type of coverage is extremely useful in determining logical combinations of signals that were not tried during simulation, exposing potential holes in verification. Example Suppose the DUT comprised of the following module: Combinational Logic Coverage Code Sample module test; reg a; reg b; wire c; initial begin a = 1'b0; b = 1'b1; #10; a = 1'b1; #10; end assign c = a | b; endmodule This module comprises of only one expression: a | b. If this module were simulated it would result in a combinational coverage value of 50% (2 out of 4). Can you determine which cases are not being covered? The expression "a | b" can result in two values, 0 and 1, but can do so in four combinations: a = 0, b = 0, c = 0 a = 0, b = 1, c = 1 a = 1, b = 0, c = 1 a = 1, b = 1, c = 1 Noticing the values assigned to a and b during simulation, shows that combinations (2) and (4) were hit during execution while combinations (1) and (3) were not (2 out of 4 - 50%). This also shows us that the value of c was never 0 during simulation. Recommendations For a design to pass full coverage, it is recommended that the combinational logic coverage for all modules be 80% or higher. If the expression coverage for an expression is not 100%, it is recommended that the verification engineer closely examine these missed cases to determine if more testing is required. Sometimes certain combinations of signals are unachievable due to design constraints, keeping the expression coverage from ever reaching a value of 100% but still can be considered fully covered. Finite State Machine (FSM) Coverage Description Finite state machine (FSM) coverage answers the question, "Did I reach all of the states and traverse all possible paths through a given state machine?" There are two types of coverage detail for FSMs that Covered can handle: State coverage - answers the question "Were all states of an FSM hit during simulation?" State transition coverage - answers the question "Did the FSM transition between all states (that are achievable) in simulation?" Example Suppose the DUT comprised of the following finite state machine: FSM Coverage Code Sample To help visualize this state machine, let's also display it as a digraph.
Digraph Version of Example FSM
This state machine has four states: IDLE, REQ, WAIT, GNT. During simulation, 75% of the states were hit (3 out of 4) including IDLE, REQ and GNT. You can see that the WAIT state was never hit during simulation since the gnt signal was asserted the clock period after the req signal asserted. Additionally, this state machine contains 7 state "arcs" which are represented in the digraph as arrowed lines. They are the following: IDLE -> IDLE (hit) IDLE -> REQ (hit) REQ -> WAIT (missed) REQ -> GNT (hit) WAIT -> WAIT (missed) WAIT -> GNT (missed) GNT -> IDLE (hit) Counting the number of traversed arcs during simulation, we can see that we have covered 4 out of 7 (or 57%) of the possible arcs in this state machine. Recommendations For a design to pass full coverage, it is recommended that the FSM coverage for all finite state machines in the design to receive 100% coverage for the state coverage and 100% for all achievable state transitions. Since Covered will not determine which state transitions are achievable, it is up to the verification engineer to examine the executed state transitions to determine if 100% of possible transitions occurred. Assertion Coverage Description Assertion coverage answers the question, "Did I hit all of the possible coverage points of the assertions that I included in the design?" Currently, Covered is capable of finding all OVL (Open Verification Language) assertion modules instantiated within the design (when the -A ovl option has been specified to the score command). Within most OVL assertion modules are one or more built-in coverage points. When the user has specified a particular assertion instance to check for a coverage point, Covered simulates this assertion module, keeping track of which coverage points within the assertion have been hit during simulation (and how many times each coverage point has been hit) and which have not. This allows the user to check for more complex coverage scenarios within the design. Currently, only OVL version 1.6 (and newer) are supported. Older versions of the OVL may not work and are not planned to be supported. Recommendations For a design to pass full coverage, it is recommended that the assertion coverage for all modules in a design receive 100% coverage. If an assertion coverage point is not hit during simulation, the design has not been fully exercised. Assertion coverage is useful for determining more specific corner case holes in the test suite. covered-0.7.10/doc/docbook/chapter_race.xml0000644000076500007650000002234311174115776020607 0ustar trevorwtrevorw Race Condition Checking Due to Covered's method of abstracting coverage from a dumpfile, a partial "resimulation" of the design is needed to obtain proper statistics for line, combinational logic and FSM metrics. Therefore, accurately resimulating what occurred in the actual simulation is a requirement for obtaining correct results. This can be easily achieved so long as the design doesn't contain any code that could result in potential race conditions. Checked Coding Guidelines To avoid this problem Covered performs automatic race condition checking on the specified design after parsing has been completed but before simulation/scoring is performed. All statement blocks in the design that don't adhere to certain coding guidelines are removed from coverage consideration by Covered. By following these coding guidelines, a design should be void of race condition scenarios that would lead to faulty simulation results. The following coding guidelines are applied by Covered when checking for race conditions: All sequential logic and latches use non-blocking assignments. All combinational logic in an always block uses blocking assignments. All mixed sequential and combinational logic in the same always block uses non-blocking assignments. Blocking and non-blocking assignments should not be used in the same always block. Assignments made to a variable should only be done within one always block. The $strobe system call should only be used to display variables that were assigned using non-blocking assignments. (Not currently implemented) No #0 procedural assignments should exist. (Not currently implemented) Race Condition Handling If Covered detects a block as violating any one of the above mentioned coding guidelines, it will do one of two things depending on options specified to the score command by the user. If the -rS, -rW or none of the -r options are specified, Covered will simply remove the non-conforming always block from coverage consideration and continue with scoring. -rW will display a message describing detected race conditions during the scoring command while the -rS option will display no messages. If the -rE option is specified, Covered will halt the score command after all race condition checking has been performed with a message to the user specifying how many always blocks were found to be in non-compliance to the race-condition-free coding guidelines. The first mode of operation is the recommended mode of operation as this will allow Covered to continue calculating coverage information for the design while still providing accurate coverage information for the logic that is still under consideration. The second mode of operation is meant to allow the user to use Covered as a race-condition checking tool. Avoiding Race Condition Checking Covered has three means of avoiding race condition checking: (1) skip race condition checking for the entire design altogether, (2) skip race condition checking for one or more specified modules, or (3) place inline pragmas around specific logic blocks to avoid checking. The main advantage for using either of these methods is to allow Covered to score more of the design that would otherwise be excluded due to failing a static race condition checkpoint. The main disadvantage to avoiding race condition checking using either of these methods is that you could potentially be ignoring code that contains an actual race condition, causing Covered to potentially generate incorrect coverage information without warning. These types of "errors" are not assumed to be Covered bugs. To exclude the entire design from race condition checking, simply specify the -rI option on the score command-line. This will cause Covered to skip the race condition checking phase entirely, outputting a warning message (unless the global -Q option has been specified). The use of this command-line option is highly discouraged due to its general assumption by the user that the entire design is void of race conditions. To exclude an entire module from race condition checking, simply specify the -rI=module name option on the score command-line. This option may be specified one or more times on the score command-line (once for each module to be skipped). To exclude portions of the design from race condition checking, the user may also place inline comment-based pragmas in the design and specify the -rP option to the score command-line. The inline pragmas look like the following: Using a Race Condition Pragma This example will cause the initial block surrounded by the racecheck pragmas to be ignored from race condition checking, thus making it available for coverage consideration. If there are any race condition rules that this block contains or is a part of, they will not be reported. The keyword racecheck is the default pragma keyword for race condition checking avoidance; however, if this name needs to be changed to something else by the user (i.e., if racecheck is used by another tool and has a different meaning or format), the user may make this keyword anything they please as long as the meaning is preserved (i.e., keyword off means that race condition checking should be turned off for all subsequent code until its matching keyword on pragma is seen). The new name of this keyword is passed to the -rP option by specifying -rP=keyword. It should also be noted that race condition pragmas can be embedded within each other (all code within the outside pair are removed from race checking) and race condition avoidance pragmas (racecheck off) are in effect on a file-basis -- that is, they are in effect even beyond their current scope but are no longer in effect after the current file. Reporting Race Conditions Even though race condition information is displayed (assuming the -rS option was not specified in the score command-line) during the scoring process, it may be convenient to view this information in a generated report as well. Because of this need, Covered saves all race condition information to the CDD file for use in using the report command. By specifying 'r' in the -m option to the report command (race condition report output is not turned on by default), the statement blocks which were eliminated from coverage consideration will be output to the coverage report file. Summary coverage will contain the total number of statement blocks eliminated for each module. Verbose coverage will contain each eliminated statement block, organized by module, specifying both the starting line of the eliminated statement block and the reason for why the statement block was removed. covered-0.7.10/doc/docbook/chapter_rank.xml0000644000076500007650000006411211061140437020613 0ustar trevorwtrevorw The rank Command The rank command allows the user to specify a number of CDD files that have been created from the same DUT (presumably in a regression run -- but not necessarily) and rank them in order of coverage importance. This information can be useful in accomplishing the following tasks: Understand which CDD files (simulations) can be eliminated from regression due to their inability to add useful coverage information that selected CDD files already hit. Understand the best order to run simulations in full regression. It can help in creating a quick (confidence) regression which is meant to hit a good deal of the overall coverage points in a short period of time to verify that recent changes don't massively break a previously working DUT. This can be accomplished by selecting the first N simulation CDD files in the ranked list. The selection can easily be done by either using the simulation order, accumulated hit, hit percent or timestep column values as a means of selection. Options Options to rank Command Option Description -depth number Specifies the minimum number of CDD files to hit each coverage point. The value of number should be a value of 1 or more. Default is 1. -d directory Directory to search for CDD files to include. This option is used in conjunction with the -ext option which specifies the file extension to use for determining which files in the directory are CDD files. -ext extension Used in conjunction with the -d option. If no -ext options are specified on the command-line, the default value of '.cdd' is used. Note that a period (.) should be specified. -f filename Name of file containing additional arguments to parse. -h Displays help information for the rank command. -names-only If specified, outputs only the needed CDD filenames that need to be run in the order they need to be run. If this option is not set, a report-style output is provided with additional information. -o filename Name of file to output ranking information to. Default is stdout. -require-cdd filename Name of CDD file to use as a required CDD file for ranking, regardless of whether it is necessary to achieve full coverage or not. -require-list filename Name of file containing list of CDD files which are required to be in the list of ranked CDDs to be run, regardless of whether they are necessary to achieve full coverage or not. -v Outputs verbose information during the run of the rank command. Useful for selection process understanding and command performance. -weight-assert number Specifies a relative weighting for assertion coverage used to rank non-unique coverage points. -weight-comb number Specifies a relative weighting for combinational logic coverage used to rank non-unique coverage points. -weight-fsm number Specifies a relative weighting for FSM state/state transition coverage used to rank non-unique coverage points. -weight-line number Specifies a relative weighting for line coverage used to rank non-unique coverage points. -weight-memory number Specifies a relative weighting for memory coverage used to rank non-unique coverage points. -weight-toggle number Specifies a relative weighting for toggle coverage used to rank non-unique coverage points.
Methods for specifying CDDs to rank The rank command provides several mechanisms for specifying CDD files to rank. Feel free to use any combination of methods for providing this information to Covered as it makes sense to do in your environment. The following is the list of input methods: Specify each CDD file after the rank command options have been specified. This method is best when there are a relatively small number of CDD files to rank as the length of the command-line in a shell is typically limited to a certain number of characters. Create a file containing the list of CDD files to rank and pass this file to the rank command's -f option. Using this method, one can selectively specify a large number of CDD files. You may specify as many "-f filename" options as is necessary. Use shell commands to create a list of CDD files and pass them to Covered's standard input via command-line piping and the -f - command-line option (the - means use standard input). The following line is an example of this usage: You may specify only one "-f -" option to the rank command. Use the -d directory and -ext extension options to tell Covered to retrieve all files found in the directory specified by directory that contain the file extension of extension (if the -ext option is not specified, the default extension of ".cdd" is used). The following is an example of this usage: You may specify as many -d options on the command-line as is necessary; however, only one -ext option is allowed. Specify a single CDD file that MUST be included in the final ranking list via the -require-cdd option. You can specify as many -require-cdd options to the rank command as necessary. Create a file containing a list of CDDs that MUST be included in the final ranking list where each CDD filename is separated by a newline or whitespace. Pass this file to the -require-list option. You can specify as many -require-list options to the rank command as necessary. Specifying metric weights The rank command has several options that allow the user to weight any and all of the coverage metrics that Covered supplies. Weights are used to ascribe the importance of its metric in ranking the value of a CDD file. Weight values are non-negative numbers whose values are relative to each other. A value of 0 effectively disables the associated weight from consideration in ranking. All other values are considered relative to each other. In other words, if the line weight is set to a value of 5 while the toggle weight is set to 1, line coverage is considered 5 times more important than toggle coverage in ranking. By default, each metric is given an equal weight of 1. Adjust each of the metrics as necessary to potentially modify which CDD files are chosen and what order those CDD files are given in the ranked list of diagnostics to run. Understanding the rank command output information After the rank command has been executed, the output will either be displayed to standard output (if no -o option was specified) or it will be output to a file. If the -names_only option was specified, the output will be a list of CDD filenames (one per line) which are output in the order in which they should be run to achieve full coverage in the shortest amount of time. If the -names_only option was not specified, the output will be in the form of a table (similar to reports generated with the report command) which describes not only the order that CDD files should be run but also various statistical data and the names of CDD files which are considered redundant in terms of coverage information. The following example shows an example of this report output. Rank Output With No Required Files After the header information, there is a summary of the ranking reduction (if one occurred) specified in both number of files and number of simulation timesteps. shows what this information looks like when no file reduction has occurred. After the summary information, there is the rank output table which displays both the individual CDD information and the accumulative coverage information. Each row of the table contains one CDD file where the first row contains the first CDD that should be run in regression for maximum coverage impact. Each successive row contains CDD files that add less and less coverage to the overall coverage gained. If there were CDD files that were found to not add any coverage information to the above CDD files, a line is drawn and these CDD files displayed below that line. These CDD files can be excluded from regression because they don't add any useful coverage information over-and-above the CDD files that are selected to be run in regression. The first major column is the simulation order. This value increments by one for each successive row. If you would like to create a shorter running regression that is limited to a certain number of simulations, this row information can be useful for figuring out which simulations to include in these type of regressions. The second major column is the accumulative coverage statistics which include the following: Hit The first row contains the number of coverage points that the first CDD file hit. All successive rows add the unique coverage points hit by the CDD file listed on that line to the above hit total. For example, in "rank1c.cdd" contains 9 hit coverage points (accumulative hit count = 9). The second highest ranked file, "rank1b.cdd", contains 8 hit coverage points but only 4 of those coverage points are different than the coverage points hit by "rank1c.cdd"; therefore, the accumulative coverage hit count is 13. The third coverage file, "rank1c.cdd", contains 8 coverage points but none of them add to the coverage points hit by the first two coverage files; therefore, it is considered unnecessary for regression. Total The "accumulative" total represents the total number of coverage points in each CDD file. Since this number must be the same for each CDD file, this value will be the same for each row. % This column represents the hit percentage and is a simple calculation of hit / total for each row. Timesteps This column represents the number of accumulated simulation timesteps. This value represents the number of timesteps that need to transpire to gain the amount of accumulated coverage. One of the goals of the ranking algorithm is to gain the most amount of coverage in the least amount of simulation time. The third major column is the individual coverage information for the CDD file listed in the row which includes the following information: R This column represents whether the current CDD file was a required CDD file by the user (a file listed via the -require-list or -require-cdd options). If the file is a required CDD file, an asterisk (*) is listed in this column. If the file was not required, nothing will be listed in this column. provides an example of what this output looks like. Name Filename of the CDD file that was selected for this row. Hit This column represents the number of coverage points hit by the CDD file. Total This column represents the total number of coverage points within the CDD file that could be hit. % This column represents the hit percentage (a calculation of hit / total. Timesteps This column represents the number of simulation timesteps that the CDD file took to run during simulation. This value does not necessarily represent the ending simulation time. Rank Output With Required Files Description of ranking algorithm This section describes the overall algorithm that is used to rank the specified CDD files. The algorithm is being presented in this document for the purposes of providing an explanation for how diagnostics are selected for ranking and how they are ranked. Knowing this information is not necessary for using the rank command or understanding its results. The algorithm makes use of three different types of structures. The first structure is a bit-compressed structure where each bit corresponds to one coverage point in the associated CDD file. The purpose of this structure is to store a large amount of information as concisely and immediately available as possible. In addition to coverage point information, each structure also contains the following information: Name of CDD file that the structure is associated with (for reporting purposes only). The number of timesteps that occurred during the CDD simulation. This is used for calculating the average number of coverage points hit during a single clock period -- used for ranking selection. The total number of coverage points hit by the CDD. This is used for calculating the average number of coverage points hit during a single clock period -- used for ranking selection. The total number of coverage points that were hit by this CDD that were not hit by any other CDD listed in the rank command-line. This information is used to figure out which CDDs are absolutely necessary to be included in the ranked list. The current score associated with the CDD file. This value is updated for each selection iteration. Each of these structures are maintained in an array that is iterated on during the ranking process. The second structure is an array of 16-bit values where each value corresponds to a single coverage point. Its value is a sum of the number of unranked CDD files that have hit that coverage point. Each value is decremented by one when a CDD file is moved from the unranked list to the ranked list and that CDD file hits the given coverage point. If a coverage point value is a value of 1 and a CDD file has its corresponding coverage bit set, we know that the CDD is the only one that hits the coverage point. The third structure is similar to the second and works similarly, except that it stores the number of CDD files in the ranked list that hit a particular coverage point. The specified CDD files are ranked in a series of steps, some of which are reiterated for each CDD that is selected to be ranked. Here is the basic algorithm (in pseudo-code): highest score and a "unique" coverage point was found { set highest_score to our score } } move the CDD file indexed by highest_score from the unranked list to the ranked list } resort ranked list from most unique to least unique (if there is a tie, select the CDD that hit the most coverage points in the least amount of time) ]]> covered-0.7.10/doc/docbook/chapter_reading.xml0000644000076500007650000010113311054713225021267 0ustar trevorwtrevorw Reading the Report This chapter describes the meanings of the textual report output that Covered generates when the report command is issued. It is well understood by the developers of Covered that a code coverage tool is only as good as the output that it generates, and this, of course, includes the ability to discern the information provided by the report. To help describe the various sections of a Covered report, we will use a relatively small Verilog file containing our DUT, generating the two main types of reports (module and instance) based on the CDD generated for this file. This example file is provided here After being compiled and run, this module is scored with the following Covered command: covered score -t main -v example.v -o example.cdd -vcd example.vcd The module-based verbose report can be viewed in its entirety and is generated with the following command: covered report -d v example.cdd The instance-based verbose report can be viewed in its entirety here and is generated with the following command: covered report -i -d v example.cdd The instructions for analyzing each of the six types of coverage information from the report can be found on the following pages. For information on reading race condition information in the report, please see the user guide page detailing race conditions and viewing the reports. Reading Line Coverage Summary Information Description - Module-based For module-based reports, the summary table for line metrics includes information for the name of each module that was covered and the name of the file in which the module is described in. Lines 15 through 24 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma and fsmb. The table shows that all three modules were described in the file "example.v". Summary Information Description - Instance-based For instance-based reports, the summary table for line metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand-side of each row. Lines of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1" and "main.fsm2". Summary Information Description - Both On the right-hand side of each row in the table are the hit, miss and total numbers for the line coverage, followed by a calculated percent of the lines that were hit (calculated by taking the number of lines hit during simulation divided by the total number of lines that Covered simulated). The hit value indicates how many lines were executed during the simulation; the miss value indicates the number of lines not executed during simulation; and the total value indicates the total number of lines within the specified module/instance that Covered was able to simulate. If the percentage value in the far left of the summary table is 100%, this indicates that all lines that Covered was capable of simulating (for the module/instance of this row) were executed. If the value of the percentage is less than 100%, this indicates that some number of lines were not executed and full coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any lines in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%. Verbose Information Description - Both If the miss value for a particular module was not 0 (indicating that lines were missed during simulation) and the '-d v' option was specified on the command-line (specifying to output verbose reporting information), the line that was missed during simulation will be output below the summary information per module that contained missed lines. In our sample report, there was one line that was missed during simulation (according to the summary output) for the module called "fsmb" (instance "main.fsmb"). The line number and Verilog line that was missed is output in lines 25 through 29 of the module-based report and in lines 25 through 29 of the instance-based report. If a module does not contain any missed lines and the '-d v' option was specified, no verbose output will be displayed for this module. Likewise, if a module/instance does not contain any lines that Covered could execute, no verbose output will be displayed. The definition of what Covered considers a line is a statement (ex. assignment, conditional, etc.). If a statement is written in such a way that it consumes multiple file lines, Covered only counts the statement as one line. The user can assume that if the beginning of a statement is labeled as missed, the entire expression was missed (not just the first line of the expression). For example, consider the following code: If the expression is not executed during simulation, Covered will indicate that only one line was missed during execution (not two), and it will display the missing line (if verbose reporting is specified with the '-d v' option) as the following: The "..." notation at the end of the Verilog output indicates that the statement was a multiline statement in the source code but is only considered one line. Reading Toggle Coverage Summary Information Description - Module-based For module-based reports, the summary table for toggle metrics includes information for the name of each module that was covered and the name of the file in which the module is described in. Lines 41 through 51 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma and fsmb. The table shows that all three modules were described in the file "example.v". Summary Information Description - Instance-based For instance-based reports, the summary table for toggle metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand-side of each row. Lines 41 through 51 of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1" and "main.fsm2". Summary Information Description - Both On the right-hand side of each row in the table are the hit, miss and total numbers for the toggle 0->1 coverage, followed by a calculated percent of the signal bits that toggled from a value of 0 to a value of 1 (calculated by taking the number of bits that toggled from 0 to 1 during simulation divided by the total number of signal bits). The hit value indicates how many signal bits were toggle from a value of 0 to 1 during simulation; the miss value indicates the number of signal bits that were not toggled from a value of 0 to 1 during simulation; and the total value indicates the total number of signal bits within the specified module/instance that Covered was able to simulate. To the right of this information is the hit, miss and total statistics for signal bits that toggled from a value of 1 to a value of 0. If the percentage values in the right of the summary table are 100%, this indicates that all signal bits toggled from a value of 0 to 1 and back to 0 during simulating (for the module/instance of this row). If the values of the percentage are less than 100%, this indicates that some signal bits did not fully toggle during simulation and full toggle coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any signals in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%. Verbose Information Description - Both If the miss value for a particular module/instance was not 0 (indicating that one or more signal bits did not fully toggle during simulation) and the '-d v' option was specified on the command-line (specifying to output verbose reporting information), the signals that were missed during simulation will be output below the summary information per module/instance that contained missed signal bit toggles. In our sample module-based report, there were three signals in module "main" ("go", "state", and "error"), three signals in module "fsma" ("go", "state" and "next_state"), and three signals in module "fsmb" ("go", "next_state" and "state") that were not fully toggled (see lines 53 through 90). For each signal in the verbose toggle table, the format is the following: 0->1: .......................1->0: ]]> The name of the signal is specified in the upper left corner. The bitwise toggle information for the signal from a value of 0 to a value of 1 is specified in the upper right corner. The hexidecimal value represents bits in the signal, each bit corresponding to the matching bit of the signal. If a bit value is set to the value 1, this indicates that this bit in the signal toggled from a value of 0 to a value of 1. If a bit value is set to the value 0, this indicates that this bit in the signal did NOT toggle from a value of 0 to a value of 1; therefore, full toggle coverage was not achieved for this signal. For example, for the signal called "go" in the module/instance "main", the verbose toggle information looks like: go 0->1: 1'b1 ...........1->0: 1'b0 This is indicating that bit 0 of the signal called "go" successfully toggled from a value of 0 to 1 during simulation (because the bit value at bit location 0 is a value of 1). However, the signal did not toggle from a value of 1 to a value of 0 during simulation, thus the signal was not considered fully toggled. It is important to note that the hexidecimal values are displayed with the least-significant bit of the signal being output on the far right of the value while the most-significant bit of the signal is output on the far left of the value. Reading Memory Coverage Summary Information Description - Module-based For module-based reports, the summary table for memory metrics includes information for the name of each module, instantiating one or more memories, that was analyzed and the name of the file in which the module is described in. Lines 93 through 111 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma and fsmb. The table shows that all three modules were described in the file "example.v". Summary Information Description - Instance-based For instance-based reports, the summary table for memory metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand-side of each row. Lines 93 through 111 of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1" and "main.fsm2". Summary Information Description - Both On the right-hand side of each row in the table are the hit, miss and total numbers for the various memory coverage metrics, followed by a calculated percent of each memory coverage metric that was hit (calculated by taking the number hit during simulation divided by the total number that Covered could have simulated). The hit value indicates how many were executed during the simulation; the miss value indicates the number not executed during simulation; and the total value indicates the total number within the specified module/instance that Covered can simulate. All four metrics (AME toggle 0->1, AME toggle 1->0, AME write and AME read) are listed in the summary section. If the percentage value in the far left of the summary table is 100%, this indicates that all coverage points that Covered was capable of simulating (for the module/instance of this row) were executed. If the value of the percentage is less than 100%, this indicates that some number of coverage points were not executed and full coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any coverage points in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%. Verbose Information Description - Both When a module/instance is found to be not fully covered (i.e., the number of each hit coverage points is not equal to the associated number of attainable coverage points), the missed coverage points for each AME in the memory are output to the report as follows: Written: <0 or 1> 0->1: ..... Read: <0 or 1> 1->0: ... ]]> The answers to each of the questions listed above are specified with a 0 (meaning that the answer is "NO") or a 1 (meaning that the answer is "YES"). Note that in the toggle coverage information, like toggle coverage verbose information, the individual bits are grouped together and displayed in hexidecimal form to conserve space and make the task of figuring out exactly which bit positions did not toggle easier. See lines 117 through 151 for an example of this output. If the -c option is used, Covered outputs the names of the memories that were fully covered during simulation only. Reading Combinational Logic Coverage Summary Information Description - Module-based For module-based reports, the summary table for combinational logic metrics includes information for the name of each module that was covered and the name of the file in which the module is described in. Lines 154 through 164 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma, and fsmb. The table shows that all three modules were described in the file "example.v". Summary Information Description - Instance-based For instance-based reports, the summary table for combinational logic metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand-side of each row. Lines 154 through 164 of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1", and "main.fsm2". Summary Information Description - Both On the right-hand side of each row in the table are the hit, miss and total numbers for the combinational logic coverage, followed by a calculated percent of the combinational logic expression values that were hit (calculated by taking the number of combinational logic expression values hit during simulation divided by the total number of expression values that Covered could have simulated). The hit value indicates how many expression values were achieved during the simulation; the miss value indicates the number of expression values not achieved during simulation; and the total value indicates the total number of combinational logic expression values that could have been achieved in the specified module/instance. If the percentage value in the far left of the summary table is 100%, this indicates that all combinational logic expression values that Covered was capable of achieving (for the module/instance of this row) were hit. If the value of the percentage is less than 100%, this indicates that some number of expression values were not achieved and full coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any combinational logic expressions in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%. Verbose Information Description - Both The verbose output for combinational coverage is a bit more sophisticated than the line or toggle. Basically, for each expression that was found to not be fully covered (either the expression itself or some sub-expression in the tree was not fully covered), the expression is output with various sub-expressions underlined and identified with a number. Each expression is also supplied with the line number that the expression started at in its module file. In our example, there is an uncovered expression in the module called "main" (see lines 170 through 205 (numbered 5) which contains four uncovered subexpressions (numbered 1 through 4). Below each expression, there will be one or more tables which specify a particular sub-expression that was not fully covered along with information describing what cases were not covered for that sub-expression. In the report output above, we see that there was one expression in module "main" that did not achieve 100% coverage that starts on line 14 of the Verilog source. The expression is output to the report with certain sub-expressions underlined and labeled with an integer value for reference. For this one expression, there were found to be four subexpressions (labeled 1, 2, 3, 4) that were found to not be 100% covered. Taking a look at subexpression 1 report output, the numbers to the right of the string "Expression 1" tell us the number of logical combinations of this subexpression that were hit (in this case 2 combinations were hit) and the total number of logical combinations that this subexpression can have (in this case 3 combinations were achievable). The character string below this information tells us the type of subexpression that we are examining. For subexpression 1, the type is the bitwise AND operator. The table below this information for subexpression 1, lists the potential combinations that this subexpression could have reached with a '*' character placed underneath the combination(s) that were missed. In the case of subexpression 1, the left and right subexpressions did not evaluate to values of 1 simultaneously. The letter 'L' above each possible combination indicates the value that the left subexpression achieved at the same time as the value under the right subexpression indicated with the letter 'R'. Legal values for a subexpression are '0', '1' or '-' (which indicates that this subexpression value could either be 0 or 1). Reading FSM Coverage Summary Information Description - Module-based For module-based reports, the summary table for FSM metrics includes information for the name of each module that was covered and the name of the file in which the module is described in. Lines 344 through 354 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma and fsmb. The table shows that all three modules were described in the file "example.v". Summary Information Description - Instance-based For instance-based reports, the summary table for FSM metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand-side of each row. Lines 344 through 354 of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1" and "main.fsm2". Summary Information Description - Both On the right-hand side of each row in the table are the hit, miss and total numbers for the FSM state coverage, followed by a calculated percent of the FSM states that were hit (calculated by taking the number of FSM states hit during simulation divided by the total number of FSM states that Covered could have simulated). The hit value indicates how many FSM states were executed during the simulation; the miss value indicates the number of FSM states not executed during simulation; and the total value indicates the total number of FSM states within the specified module/instance that Covered can simulate. To the right of the FSM state summary information is the FSM state-transition hit, miss, total and percentage hit summary information for each module/instance. If the percentage value in the far left of the summary table is 100%, this indicates that all FSM states and state-transitions that Covered was capable of simulating (for the module/instance of this row) were executed. If the value of the percentage is less than 100%, this indicates that some number of FSM states and/or FSM state-transitions were not executed and full coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any FSMs in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%. Verbose Information Description - Both The verbose output for FSM coverage is split into the state coverage information and the state transition coverage information. When an FSM is found to be not fully covered (i.e., the number of hit states/state transitions is not equal to the number of attainable states/state transitions), the missed states are output to the report as a list of state values in hexidecimal format as follows: ]]> When an FSM is found to be not fully covered, the missed state transitions are output to the report as a list of state transitions in the format below: -> ]]> If the -c option is used or the number of attainable state/state transitions are unknown for the specified FSM, Covered outputs this information in the same way as the missed cases except that the title of the output is "Hit cases". If the number of attainable states/state transitions is unknown, providing the cases that were hit during simulation is useful in aiding the user in determining coverage. In this case, the summary report will output question marks in the missed and total categories, showing the user that this information was not known by Covered. Reading Assertion Coverage Summary Information Description - Module-based For module-based reports, the summary table for assertion metrics includes information for the name of each module, instantiating one or more assertions, that was covered and the name of the file in which the module is described in. Lines 397 through 405 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma and fsmb. The table shows that all three modules were described in the file "example.v". Summary Information Description - Instance-based For instance-based reports, the summary table for assertion metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand side of each row. Lines 397 through 405 of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1" and "main.fsm2". Summary Information Description - Both On the right-hand side of each row in the table are the hit, miss and total numbers for the assertion coverage points (ACP), followed by a calculated percent of the ACPs that were hit (calculated by taking the number of ACPs hit during simulation divided by the total number of ACPs that Covered could have simulated). The hit value indicates how many ACPs were executed during the simulation; the miss value indicates the number of ACPs not executed during simulation; and the total value indicates the total number of ACPs within the specified module/instance that Covered can simulate. Note that more than one coverage point may exist within a single assertion coverage module. If the percentage value in the far left of the summary table is 100%, this indicates that all ACPs that Covered was capable of simulating (for the module/instance of this row) were executed. If the value of the percentage is less than 100%, this indicates that some number of ACPs were not executed and full coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any ACPs in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%. Verbose Information Description - Both When a module/instance is found to be not fully covered (i.e., the number of hit ACPs is not equal to the number of attainable ACPs), the missed coverage points are output to the report as follows: ]]> If the -c option is used, Covered outputs this information in the same way as the missed cases except that the title of the output is "Hit cases" and the number of times each ACP was hit is indicated. covered-0.7.10/doc/docbook/chapter_report.xml0000644000076500007650000003001711312316510021164 0ustar trevorwtrevorw The report Command Usage The report command is initiated with the following call: covered report (-h | -view [CDD_filename] | [options] CDD_filename) The CDD_filename refers to the name of the CDD to generate the report for. This CDD may be either the result of a score or the result of merging CDDs. If the -view option is specified, Covered's GUI is run. You may specify the CDD filename to initially load with the -view option. See for instructions on using the GUI for interactive coverage analysis. Options The following table lists the options available for use with the report command. Options to report Command Option Description -b If combinational logic verbose output is reported and the expression is a vector operation, this option outputs the coverage information on a bitwise basis. -c Used in conjunction with the '-d d' or '-d v' option. If set, causes covered logic to be reported instead of default behavior of reporting uncovered logic. See -d (s|d|v) Level of report detail (s=summary, d=detailed, v=verbose). Default is to display summary coverage information. See . -e Outputs exclusion cases when the -d v or -d d options are specified on the command-line. The exclusion cases are displayed in the verbose format along with an exclusion reason (if one is associated with the excluded case). -f filename Name of file containing additional arguments to parse. You may specify this option more than once on a command-line. -h Outputs usage information for the report command. -i Generates report information for each instance (default is to generate per module). See -m [l][t][c][f][r][a][m] Specifies type of coverage information to report (l=line, t=toggle, c=combinational logic, f=FSM state/arc, r=race condition, a=assertion, m=memory). Default is ltcf. -o filename Specifies output file to stream report to (default is standard output). -s Suppresses modules/instances that do not contain any coverage information from being output to the coverage report. This may eliminate potentially meaningless information from the report. -view Starts the interactive Covered report viewer GUI. -w (number) Specifies the maximum line width (in characters) that can be used to output Verilog information. If this option is not specified, all Verilog code in the report will retain the same formatting as was specified in the original Verilog code. If this option is specified, Verilog code will be formatted to use as much of the current line as possible, wrapping text when the line reaches the maximum line width. The default maximum line width is 115 characters (this value is used if no number is specified with the -w option). If a number is specified with the -w option, this value is used for the maximum line width. -x When used in conjunction with the -d v or -d d option, causes all uncovered or excluded coverage points to display an associated "exclusion ID" to the left of the verbose output within parenthesis. This exclusion ID can be used in calls to the exclude command for the purposes of excluding or including coverage points.
Summary Vs. Detailed Vs. Verbose There are three forms of reports that can be generated by the Covered report function: summary, detailed, and verbose. The three forms are described below. Summary Report A summary report shows at a very high-level what the coverage for a specific module (or instance) is in terms of line, toggle, combinational and/or FSM coverage (depending on which types are selected on the command line). Each coverage metric for the module is given a percentage of items covered for that metric as well as the total number of items per metric, the number of items "hit" during simulation and the number of items "missed" during execution. See the chapter on "Reading the Report" for more information on understanding the formats of line, toggle, combinational logic, and FSM summary information. The summary report is useful for understanding exactly which modules are missing coverage (and what type(s) of coverage are missing) as well as what modules are fully covered. This can help guide you more easily in understanding where you need to improve your code coverage without getting lost in all of the details that the verbose reporting provides. Detailed Report The detailed report is useful for understanding where logic was found to be uncovered in the design along with some higher-level information to understand why it was considered to be uncovered. This amount of detail is between the minimum (summary coverage) and the maximum (verbose coverage) and should be used as the first detailed report to be looked at since it is easier to read and comprehend the coverage results. Verbose Report The verbose report contains all of the data that the summary report contains; however, in addition to the summary information for a module (or instance), a more in-depth look at the exact cases that were "missed" during simulation are provided. This report outputting option is useful for combinational logic report information when a more in-depth look at why certain expressions did not reach full coverage is needed. This option allows the user to look at all subexpressions of an expression that were not fully covered. Module Vs. Instance Any report can be calculated by module or by instance. Both reports are of interest for verification purposes and the differences are described as follows. Module reporting combines the results of all instances that come from the same module. That is, when a module is instantiated multiple times in a design, the coverage results from all covered instances are merged together and output as one combined module. This reporting format allows a test writer to see if any logic within a module has not been touched during simulation. Instance reporting displays each instance in the covered design separately (no combining occurs). This reporting format is useful for determining if certain instances within a design are being neglected. For instance, if a module is instantiated four times (i.e., four instances of the same buffer), it may be that the first buffer is used more often than the other three buffers. This could indicate controller errors or just an indication that there was not enough activity during simulation to fill the other buffers (need to bolster diagnostics or possibly some buffers could be removed?) This type of information would not be viewable if only module reporting were performed. Covered Vs. Uncovered Covered has the ability the generate reports from any given CDD file that displays either uncovered logic (the default behavior) or covered logic. It is understandable why one would want to generate reports displaying uncovered logic (this is probably the reason why you are interested in this tool in the first place). However, why would anyone be interested in reporting covered logic? The reason for having this option is two-fold (and maybe there are other reasons). First, this option is useful in debugging the report command since it let's the user evaluate whether a particular signal or portion of logic was actually fully covered or not. Second, it may be useful for user's of the tool to understand what logic is being evaluated for coverage and what logic is not. If only uncovered logic was supplied for evaluation of the tool, one could not evaluate the effectiveness of the tool. However, by allowing the user to see what logic is covered and uncovered, a more full picture of the tool's capability can be understood. To generate a report that specifies what logic is not covered (output only available in verbose reporting mode), no further options are needed. To generate a report that specifies what logic is being covered, simply specify the -c option along with the -v option when calling the report command. covered-0.7.10/doc/docbook/chapter_score.xml0000644000076500007650000012513211472127327021004 0ustar trevorwtrevorw The score Command Usage The score command is initiated with the following call: covered [global_options] score -t top_module [options] The top_module parameter is required for the scoring purposes and represents the top-most module that will be covered. It is important to note that Covered does not need to parse the entire DUT. It only parses that part of the design which will receive coverage results. More on this will be described below. Options The following table describes the additional options that can be passed to the score command. Note that it is optional in how you tell Covered where to find the Verilog design files; however, it is not optional to exclude the Verilog files. If no Verilog can be found that contains at least the top instance, Covered will generate an error message to the user specifying that it was unable to find the required Verilog modules. Options to score Command Option Description -A ovl Causes OVL assertions to be used for assertion coverage. This flag must be given to the score command if assertion coverage metrics are needed in the report command. See . -cli [filename] Causes the command-line debugger to be used during VCD/LXT2/FST dumpfile scoring. If filename is specified, this file contains information saved in a previous call to savehist on the CLI and causes the history contained in this file to be replayed prior to the CLI command prompt. If filename is not specified, the CLI prompt will be immediately available at the start of simulation. This option is only available when Covered is configured with the --enable-debug option. See . -conservative If this option is specified, any logic blocks that contain code that would cause coverage discrepancies leading to potentially inaccurate coverage results are removed from coverage consideration. See for more information.s -D name[=value] Defines the specified name to 1 or the specified value. -dumpvars [filename] If this option is specified without the -vcd, -lxt or -fst options, the design is parsed, a CDD file is created and a top-level Verilog module named filename (if this value is specified) or "covered_dump.v" (if filename is not specified) is created. If compiled as a top-level module along with your design and no other $dumpfile/$dumpvars calls are made, this dump module will provide additional performance gains. If either the -vcd, -lxt or -fst options are specified, this option has no effect. See . -e module Name of module, task, function or named begin/end block to not score. You may specify this option more than once on a command-line; one for each block to remove from coverage. See . -ea Specifies that all always blocks in the design should be excluded from coverage consideration. This option may help to increase performance of the score command if all always blocks in the design do not need to be checked for coverage. By default, always blocks are considered for coverage. See . -ec Specifies that all continuous assignments in the design should be excluded from coverage consideration. This option may help to increase performance of the score command if all assign blocks in the design do not need to be checked for coverage. By default, continuous assignments are considered for coverage. See . -ef Specifies that all final blocks in the design should be excluded from coverage consideration. This option may help to increase performance of the score command if all final blocks in the design do not need to be checked for coverage. By default, final blocks are considered for coverage. See . -ei Specifies that all initial blocks in the design should be excluded from coverage consideration. This option may help to increase performance of the score command if all initial blocks in the design do not need to be checked for coverage. By default, initial blocks are considered for coverage. See . -ep [name] Causes any code that is inbetween inline coverage pragmas (eg. '// coverage off' ... '//coverage on') to be excluded from coverage consideration. The code specified between these pragmas is not removed from resimulation but is marked as being excluded from coverage for reporting purposes. These exclusions may be undone via the GUI, if necessary, without requiring the design to be resimulated by Covered. If name is specified, its value will be used by Covered as the pragma keyword to search for in the design (instead of the default value of 'coverage'). This feature can be useful in the event that other tools being used on the design use a similar pragma name and there are tool conflicts. See . -F module=[in_expr,]out_expr Specifies the location to find an FSM to score where module is the Verilog module containing the FSM, in_expr is the input state expression and out_expr is the output state expression. If in_expr is not specified, out_expr is used as both the input and output state expression. -f filename Name of file containing additional arguments to parse. You may specify this option more than once on a command-line. -fst dumpfile Name of FST dumpfile to score design with. If -vcd, -lxt or this option is not used, Covered will only create an initial CDD file from the design and will not attempt to score the design. -g [module=](1|2|3) Specifies what generation of Verilog to use for parsing the design. If module is specified, uses the given generation value for that module only. If module is not specified, applies that generation to the entire design. This option may be specified multiple times on the command-line, where options to the left take precedence over the values to the right. 1=Verilog-1995, 2=Verilog-2001, 3=SystemVerilog. -h Outputs usage information for the score command. -I directory Directory to find included Verilog files. You may use this option as many times as necessary on the command-line, one for each directory. -i instance Instance name of top-level module. Necessary if module to verify coverage is not the top-level module in the design. If not specified, -t value is used. See . -lxt dumpfile Name of LXT2 dumpfile to score design with. If -vcd, -fst or this option is not used, Covered will only create an initial CDD file from the design and will not attempt to score the design. -m message Allows the user to specify information about this CDD file. This information can be anything (messages with whitespace should be surrounded by double-quotation marks), but may include something about the simulation arguments to more easily link the CDD file to its simulation for purposes of recreating the CDD file. -o filename Name of CDD to write coverage information to. -p filename Overrides filename used for outputting intermediate preprocessor output. See . -P parameter_scope=value Performs a defparam on the specified parameter with value. See . -rS Performs race condition checking and removes any offending logic blocks from coverage consideration without reporting the information. See . -rW Performs race condition checking, removes any offending logic blocks from coverage consideration, and displays this information to standard output. This is the default race condition checking behavior. See . -rE Performs race condition checking, reports any offending logic and immediately stops scoring. This option allows Covered to be used as a static race condition checking tool. See . -rI[=module name] If =module name is not specified, race condition checking is not performed for the entire design. If =module name is specified, race condition checking is not performed on the specified module only. This option may be specified more than once. See . -rP[=name] Skip race condition checking for all code surrounded by "// racecheck off/on" embedded pragmas. The "racecheck" keyword can be changed by specifying =name where name is the new name for the race condition pragma keyword. See . -S Outputs simulation statistics after simulation has completed. This information is currently only useful for the developers of Covered. -top_ts (1|10|100)(s|ms|us|ns|ps|fs)/(1|10|100)(s|ms|us|ns|ps|fs) This option is only valid when the -vpi or -dumpvars options have been specified. This option allows the user to specify a timescale for the generated Verilog module created with the -vpi or -dumpvars options. If this option is not specified, no timescale will be created for the generated module. If whitespace is needed between the various values, place the entire contents of timescale in double quotes. -ts number When scoring occurs, this option allows the user to see how far the simulator has progressed by outputting the current timestep to standard output. The value of number specifies how many timesteps are allowed to be simulated before outputting the current timestep (results in less calls to output stream). -T (min|typ|max) Specifies which value to use in min:typ:max delay expressions. Default is typ. -v filename Name of specific Verilog file to score. You may specify this option more than once on a command-line; one for each filename to parse. -vcd dumpfile Name of VCD dumpfile to score design with. If -lxt, -fst or this option is not used, Covered will only create an initial CDD file from the design and will not attempt to score the design. -vpi [filename] If this option is specified without the -vcd, -lxt or -fst options, the design is parsed, a CDD file is created and a top-level Verilog module named filename (if this value is specified) or "covered_vpi.v" (if filename is not specified) is created along with a PLI table file called filename.tab or "covered_vpi.v.tab". Both of these files are used in the compilation of the simulator to use Covered as a VPI module. If either the -vcd, -lxt or -fst options are specified, this option has no effect. See . -Wignore Suppresses any warning output during code parsing and/or simulation. -y directory Directory to find unspecified Verilog files. You may specify this option more than once on a command-line; one for each directory required. +libext+.extension[+.extension]*+ Extensions of Verilog files to allow in scoring.
Specifying What to Cover Covered is not a logic simulator and, therefore, is not required to parse the entire DUT. True simulation is performed by the Verilog simulator used to generate the VCD/LXT2/FST dumpfile. Covered, therefore, is given the ability to parse only the part of the DUT that is to be scored for coverage. Having this ability to ignore parts of the DUT has several advantages in the way of performance. Less memory is necessary for coverage simulation/ calculation. Additionally, less processing is also required which leads to faster turnaround. On the other hand, since Covered ignores the parts of the design not being scored, some information is not automatically extracted by Covered that is required for scoring the specified part of the DUT. The defparam statement is one such statement. More on this is mentioned in the following section. The following example describes a complete DUT and how to cause Covered to score various parts of the DUT.
Hierarchical Tree View of Example DUT
Assume that the following Verilog modules are used to create this tree. module "test" instantiated as "test" in the above figure module "foomod" instantiated as "foo" module "barmod" instantiated as "bar" module "amod" instantiated as "a" module "bmod" instantiated as "b" To get coverage for the entire design, the covered command line would be: covered score -t test -i test (rest of command-line) Because both the -t and -i options are the same value (the module name is the same as the instance name), only the -t option needs to be specified. If the -i option is not specified, Covered will assume that the instance name of the top module is the same name as the top module itself. Note that the -t option always needs to be specified for the score command. To get coverage for the instance foo and all modules below it, the covered command line would be: covered score -t foomod -i test.foo (rest of command-line) In this case, we do not wish to score the module test (the top-level file for the design) but rather wish to gain coverage information for module foomod and all instantiated modules underneath it. Since foomod is not the top-level design file, the -i option must be specified to tell Covered what the hierarchical scope of the top-level score file is in relation to the entire design. The main reason why this is necessary is so that Covered will be able to locate the dumpfile information for the modules/instances that need to be scored. To get coverage for only the instance foo (and none of the modules instantiated below it in the hierarchy), Covered command-line would look like the following: covered score -t foomod -i test.foo -e amod -e bmod Here we see the use of the -e option, it takes a module name as its value. When a module with the matching name is found in the hierarchy, it and all of its submodules are removed from coverage. You may specify as many -e arguments as necessary to select the appropriate modules to cover. To get coverage for the instance foo and all modules below it, in addition to the instance bar, you would have to run Covered twice (once for each top instance). The -vcd vcd_dumpfile, -lxt lxt_dumpfile or -fst fst_dumpfile parameter is simply the name of the VCD/LXT2/FST dumpfile that contains all of the module instances selected by the -t parameter (in combination with the -e option -- see below). Specifying What Not to Cover (Coverage Exclusions) Besides the -e option (scope exclusion), Covered comes equipped with several other means of excluding codes from coverage consideration. The -ea, - ec, -ei and -ef exclusion options cause Covered to not simulate always blocks, continuous assignment blocks, initial blocks and final blocks, respectively, allowing for additional score command performance enhancement opportunities. These options affect all code that is under coverage consideration for the current score command, and cannot be turned on/off on an individual basis. Using the -ep Option for Exclusion The -ep exclusion option allows Covered to exclude all code that has user-specified coverage pragmas embedded inline in the code being considered for coverage. By default, these pragmas look like the following: Inline Pragmas to Turn Coverage Exclusion On/Off module foo; // coverage off ... // coverage on endmodule; Any registers, nets, variables, blocks, expressions, FSMs or assertions found within these pragmas within the design being parsed by Covered will be excluded from coverage consideration when the -ep option is specified. If the -ep option is not specified, these pragmas are ignored by Covered. The code that is found between these pragmas is not removed from resimulation, however. Therefore, if the user decides that any code found within these pragmas needs to be considered, they may change the exclusion properties via the GUI without needing to rerun Covered's score command. Coverage numbers in generated reports will treat excluded code as though it has been hit (i.e., the coverage points will be a part of the total number and the hit counts will be increased as though these coverage points were hit during simulation). The coverage pragmas may use either the single-line C++ comment style (//) or the multi-line C comment style (/* */). By default, the pragma is identified with the keyword 'coverage' following the comment characters. This value can be changed by the user, if needed, by specifying a string value to the right of the -ep option in the score command. This can be useful if there are other programs that use the same pragma keyword and causes conflicts with Covered's use of this pragma name. The value specified after the keyword is either 'off' (meaning that code should be excluded from coverage consideration after this comment) or 'on' (meaning that code should be considered for coverage after this comment). The values of 'off' and 'on' have the same meanings regardless of the pragma keyword so be sure to rename the pragma keyword to something that is appropriate. Coverage pragmas may be embedded within each other, if desired. That is the following code example is allowed and handled properly by Covered' parser: Example of Embedded Coverage On/Off Pragmas The net effect of this example is that all code between the outer 'coverage off' and 'coverage on' pragmas are excluded from coverage. One last note about the -ep option is that coverage exclusion is restricted on a per file basis. That is, if the user specifies a '// coverage off' pragma within a file and does not specify a '// coverage on' pragma later in the file, the next file to be parsed by Covered will be handled as if coverage is on. Coverage pragmas can, however, span across multiple modules or other entities within the same file. Overriding Parameters (-P option) The defparam statement can override any parameter specified in the DUT from any module in the DUT. Since parameter information is not typically specified in VCD/LXT2/FST dumpfiles, Covered needs to know about all parameter values at score time. Since all defparam statements are ignored by the Covered parser (even those in the DUT being scored), the user must inform Covered of any parameters that need to be overridden. This is accomplished with the -P option to the score command. The first value in the -P option is the hierarchical reference to the parameter that needs to be overridden. The second value (following the '=' sign) specifies the value to assign the parameter to. This will override any default value assigned to that parameter. The user may not override the same parameter value twice on the command-line. Additionally, if the parameter is already being overridden in the design via an inline parameter override (parameter overrides specified in the '#(...)' part of the module instantiation). As an example of how to override a parameter value on the score command-line, let's assume that there is a parameter called 'google' in the module called 'amod' used in the example in Section 9.3. The parameter definition in this module looks like the following: parameter google = 4'hf; To override this value to a new value of 18, use the following option in the score command: -P test.foo.a.google=18 In this example, notice that we have not only changed the value of google, but we have also changed the bit-width of google from 4 bits to 32 bits (the size of an integer). This is considered legal behavior by Covered. It is also possible to specify non-integer values to the parameter override option. Decimal, binary, octal and hexidecimal values may also be specified, using the same syntax as they are specified in Verilog. The following examples would also be other ways to override the value to 18. -P test.foo.a.google=5'b10010 -P test.foo.a.google=4'o22 -P test.foo.a.google=12'h12 -P test.foo.a.google='d18 In fact, you may specify any value (with the exception of real numbers) to override a parameter, including the following value types: 'x', 'X', 'z', 'Z', '_', '?'. This means that unknowns may be specified in a parameter. Note that this may generate user reported errors if parameters overridden to unknown values are used in mathematical equations or are used to specify the width of wires, regs, etc. If a defparam statement is encountered in the DUT being scored, a warning message will be output to the user specifying that it has encountered a defparam statement. The defparam statement is ignored by Covered; however, if the parameter that it is overridding is used in the DUT being scored, the results of Covered may differ from actual simulation results. As such, please review all of these warning types to determine if the parameter should be overridden or not. If defparams are not parsed (seen by Covered), no such warning will be output. Please review the DUT for defparams which affect the DUT being scored. Scoring FSMs At this time Covered does not have the ability to automatically extract FSM information from the design. As a result, it is up to the user to specify FSM information for Covered to use in scoring FSMs. The ability to automatically extract FSM information is planned to be supported in the future; however, it is always a good idea to allow the user to specify and potentially override Covered's automatic extraction in the case where Covered either misses an FSM or incorrectly determines logic to be an FSM in cases where none exists. The information specified in this section describes how to tell Covered where an FSM exists within the design as of the current development version of Covered. First, we need to make a few assumptions about the type of FSMs that Covered will be able to handle and, in the future, identify. The FSM is a synchronous design with edge-triggered flip-flops. There are no FSMs embedded in another FSM. The FSM is not a pipe-lined system. The entire FSM must exist within the same module. All state registers/variables must be less than 2^16 bits in width. There is currently only one way, via the command-line, to specify to Covered where to find FSMs within the design. In the future, the inline Verilog-2001 "$attribute" function will be used to also allow the user to specify to Covered where an FSM is located. Using the command-line method, no changes need to be to source Verilog code for Covered's purposes. To specify where an FSM exists within the design, the -F option must be specified to Covered's score command. Each -F option specifies one FSM within the design. Multiple -F options to the score command are allowed, allowing more than one FSM to be scored simultaneously. The -F option takes one argument that is subdivided into two or three parts: -F module=(input_state_expression,)output_state_expression The module specifies the Verilog module where the FSM state variables exist. The input_state_expression specifies the name of the variable(s) that represent the input state of the state machine. The output_state_expression specifies the name of the variable(s) that represent the output state of the state machine. Most FSMs have one variable as the input state (in most cases a registered version of the output state) such that the input variable is different than the output variable of the state machine. Specifying both variables in the -F option provides the user to more accurately specify to Covered the FSM. In the case that an FSM has the same variable for the input and output state, the user must specify only the output state variable (omitting the input_state_expression and comma character in the argument). The input and output expression to the -F command can represent any signals, parts of signals, or combinations of signals. Constant values or parameters in the specification of the input/output expression is currently not supported (in fact, there are no future plans to support this behavior unless user-feedback demands it). The following examples show various legal ways to specify input/output expressions. The syntax is limited to what it shown in these examples. -F foobar=a Example 1 specifies that the entire vector called "a" should be considered both the input and output state variable. -F foobar=a[2] Example 2 specifies that bit 2 of the vector called "a" should be considered both the input and output state variable. -F foobar=a[3:1] Example 3 specifies that bits 3:1 of the vector called "a" should be considered both the input and output state variable. -F foobar={a,b} Example 4 specifies that vectors "a" and "b" should be concatenated to form the input/output state variable. Only one set of curly brackets may be used to specify a concatenated state expression; however, 2 or more signals may be specified within those brackets. Any combination of the above four examples can be used to formalate the input state expression or the output state expression. If the user specifies an FSM that Covered is not able to find (either the module was not included in the design that Covered is scoring or the FSM uses Verilog code that Covered is not able to handle), an error message is displayed to the user. It is then up to the user to determine if the FSM was incorrectly specified to Covered or otherwise. This warning is not considered to be a bug in Covered (unless of course, it can be proven that the FSM should have been found). At the current time, Covered does not have the ability to extract the states and state transitions of the specified FSM from the design. Currently, it also doesn't have the ability to specify this information in other ways. To provide meaningful coverage information for the FSM, Covered outputs all hit states and state transitions in the report when all achievable states and state transitions are not known. This information will be able to be specified by the user in future versions of Covered, with the ability to automatically extract this information also in the works. The reason for the -conservative feature Though Covered has support for many Verilog-1995, Verilog-2001 and SystemVerilog constructs there are handful of supported constructs that are dependent on correct simulation ordering to provide accurate coverage information. In certain cases, Covered will be able to accurately determine the order of simulation, but in some cases, it may not. In these cases, it is best for Covered to run in a "conservative" mode of operation whereby logic blocks that contain these code issues are removed from coverage consideration. Removing logic blocks does not have a negative impact (in terms of coverage accuracy) on the rest of the design. The only negative consequence is that no coverage results can be obtained for a given logic block. For example, consider the following code: If only module "foo" is chosen to gather coverage information, the call to the $random function will result in a value that will not match the actual simulation if the -conservative option is not specified. This is due to the ordering importance of $random system task calls. The first call to $random will return a value of X while the second call will return a value of Y. If we remove the code that calls $random the first time, the code that still calls X will receive the incorrect value. This discrepancy in simulation results will result in incorrect coverage results. If the -conservative option is specified to the score command, Covered will automatically remove any coverage blocks that make a call to the $random system function from coverage consideration and any assigned values within these removed blocks will get their value from the dumpfile instead of being calculated by Covered directly. This will result in correct coverage information for the module "foo". The constructs that can cause issues with Covered simulation correctness (in some situations) are the following: $random $urandom $urandom_range It is currently up to the user to determine whether liberal or conservative coverage accumulation should occur and use the -conservative option to the score command as needed. Specifying Plus Arguments When Scoring Covered supports the $test$plusargs and $value$plusargs system function calls and, as such, runtime command-line options are allowed to be specified when scoring the design. To specify plusargs to the score command, simply specify them anywhere after the score command keyword just as you would specify them to a simulator. Any plusargs specified to the score command which are not recognized for compilation purposes are used for $test$plusargs and $value$plusargs comparisons, Note that specifying plusargs to the score command is only necessary when the score command is given either the -vcd, -lxt or -fst options. If the VPI method of coverage scoring is used, specify the plusargs to the simulation runtime as required. Covered will automatically extract the plusargs from the simulator runtime for its purposes. Other Notes When the Verilog files are parsed, a preprocessor is run on each file that is to be read in by Covered. The preprocessor generates an intermediate form of each file, resolving defined values and included files. The intermediate form is output to a file which is called "tmpXXXXXX" where XXXXXX represents some alphanumeric sequence chosen by the OS via the mkstemp() function. The file is guaranteed to be unique to all other files in the directory and it is automatically removed by Covered when parsing is completed. If the user does not want Covered to use this naming convention for specifying this file, the user may use the -p option (see Options section above) to override the default name. Covered will then use this filename instead of generating a unique name. Make sure that the file specified does not contain any useful data since Covered will overwrite this file when the score command is run. covered-0.7.10/doc/docbook/chapter_start.xml0000644000076500007650000004211211472127327021022 0ustar trevorwtrevorw Getting Started Methods for scoring the design Before you are ready to being scoring, merging and generating coverage reports from the design, you will first need to decide whether you want to post-process VCD/LXT2/FST -formatted dumpfiles generated from simulation, co-process VCD/LXT2/FST -formatted dumpfiles using two processes (one for the simulation process and one for the Covered process) and a Unix FIFO, or whether you want to accummulate coverage information alongside the simulator using the simulator's VPI interface. There are advantages and disadvantages to these methods, so select the method that will best work for you. Post-processing VCD/LXT2/FST dumpfiles Generating post-process coverage information from VCD/LXT2/FST -formatted dumpfiles requires three steps: Compile the simulator to dump in the specified format. Run the simulation. Run Covered's score command using the dumpfile as input along with the design. Performing these steps will generate the needed CDD file that can be used for merging or reporting. The advantages to this approach is that the steps are fairly simple and are compiler/simulator -independent. However, there are two main drawbacks. First, compiling with dumping enabled often slows simulation by some significant factor. Second, the dumpfiles generated from simulation can often be quite large (especially for VCD dumping), consuming a lot of disk space. Additionally, if your simulator dumps in a format different from VCD, LXT2 or FST, you will need to perform an additional step in transforming the original dumpfile into one of these formats. This is often a time-consuming task if the design and/or dumpfile is significantly large. If you are generating lots of dumpfiles for coverage (say from running a regression), the amount of disk space needed to store these files can be tremendous, making this approach almost not feasible. Co-processing VCD/LXT2/FST dumpfiles via FIFO Generating co-process coverage information from VCD/LXT2/FST -formatted dumpfiles requires four steps: Compile the simulator to dump in the specified format. Create a Unix FIFO via the mkfifo fifoname command. Create an empty CDD file for the design using Covered's score command. Run the simulation and Covered's score command simultaneously. The following is an example of a testbench and command-line commands: Running Covered Alongside a Simulation Process Using a Unix FIFO to Pass Dumpfile Information mkfifo dump_fifo > vcs test.v > covered score -t tb -v test.v -o test.cdd > ./simv & > covered score -cdd test.cdd -vcd dump_fifo ]]> The end result of these steps is the same CDD file that results from using the dumpfile method described above. The primary advantages of this approach are that no dumpfiles are actually created, saving on disk space, and it does not significantly slow down the simulation process. Because both simulation and coverage scoring occur simultaneously, there should be a wall clock time improvement with this method. The drawbacks of this approach are basically that the time improvement won't be significant if you are running on a single processor/core system and that it is restricted to machines that support the Unix fifo (this may not be an actual restriction, however). Using the VPI interface to gather coverage information Generating coverage information using the VPI interface of the simulator requires three main steps: Create a base CDD file from the design along with a top-level Verilog module and PLI table file (this second file is needed for the commercial VCS compiler). Compile the simulator using the Covered VPI module (or shared object). Run the simulation. The end result of these steps is the same CDD file that results from using the dumpfile method described above. The primary advantage of this approach is that no dumpfiles are required, saving on disk space and dumpfile processing time. The drawbacks of this approach are the following: Simulation runs much slower using the VPI and Covered (most likely slower than creating dumpfiles from the simulator). Covered VPI modules are only available for certain compilers (Icarus Verilog, Cver and VCS currently); however, adding support for other compilers should not be a difficult thing to do. The VPI modules will only work for compilers that support the VPI interface (a Verilog-2001 feature). What is needed for dumpfile scoring? Before Covered can be invoked for dumpfile scoring, you must have a simulatable Verilog design and a VCD, LXT2 or FST dumpfile containing information from a simulation run of the design that dumps the module(s) that you want to check for coverage. The VCD dumpfile style was chosen due to its universal support by Verilog simulators while the LXT2 and FST dumpfile styles were chosen due to their compactness and growing support by other open source simulators and dumpfile readers. Once you have these two parts, you are ready to begin generating coverage results. Selecting What to Dump If coverage is being scored via a VCD/LXT2/FST dumpfile, it is necessary for the user to setup $dumpfile and $dumpvars calls to dump the various modules that are being scored. Covered allows the user to do this in one of two ways. First, the user may hand create these calls within their testbench. If this approach is taken, it is necessary that all modules being scored by Covered be included in the $dumpvars calls. Eliminating scored modules from the dumpfile will result in inaccurate coverage information. Additionally, it is mandatory that the dumpfile start at time 0 and that all dump information be included in the dumpfile (i.e., using the $dumplimit system task could cause dump information to be lost that will result in inaccurate coverage results). Second, the user may take advantage of Covered's -dumpvars option to the score command. Adding this parameter (and the optional -top_ts option) will create a top-level module file that can be compiled along with the testbench that will dump all of the parts of the Covered design that are needed by Covered. Using this approach will result in the best overall performance for dumpfile coverage accumulation as all unnecessary dump information will be stripped, resulting in both faster simulation and faster coverage scoring. If the second approach is taken, simply use the score command to parse the design and output an unscored CDD and the dumpvars module, using a command similar to the following: covered score -t top -v dut.v -dumpvars dut_dump.v -o dut.cdd If `timescale is specified at the top of dut.v, it may be necessary for compiling purposes to have the timescale specified at the top of dut_dump.v. To do this, simply specify the -top_ts option in the score command. Note that the example command does not list either the -vcd, -lxt or -fst options. If either of these options are present on the score command-line, the dut_dump.v file will not be created and the score command will attempt to score the design with the specified dumpfile. After the dut_dump.v file has been created, simply compile it along with your DUT as a top-level module. For example, iverilog dut.v dut_dump.v After the simulation has been compiled and run, a dumpfile called "dut_dump.vcd" (using the above example) will exist in the run directory. This dumpfile can then be used in a second call to the score command via the -vcd, -lxt or -fst options along with the unscored CDD file to create a scored version of the CDD file. Creating a VCD dumpfile By default, the $dumpfile system task call will create a file and populate it with VCD-style dumpfile information. Simply use the resulting VCD dumpfile in the -vcd option to the score command to obtain coverage for that design. Creating an LXT2 dumpfile An LXT2 dumpfile can be created in several different ways depending on the Verilog simulation tool that you are using. If you are using the Icarus Verilog open source simulator, you can simply generate an LXT2-style dumpfile by specifying the -lxt2 option to the simulator command-line. For example, if you had a file called "foo.v" that contained the same $dumpfile and $dumpvars commands used for VCD dumping and compiled it with Icarus Verilog into a VVP file called "a.out", you could cause Icarus Verilog to generate an LXT2 dumpfile (instead of a VCD dumpfile) by calling "vvp a.out -lxt2". This will cause an LXT2 style dumpfile instead of the standard VCD style dumpfile. You can also transform many different dumpfile formats into an LXT2 style dumpfile with the helper programs that come with the GtkWave waveform viewer. Creating an FST dumpfile An FST dumpfile can be created in several different ways depending on the Verilog simulation tool that you are using. If you are using the Icarus Verilog open source simulator, you can simply generate an FST-style dumpfile by specifying the -fst option to the simulator command-line. For example, if you had a file called "foo.v" that contained the same $dumpfile and $dumpvars commands used for VCD dumping and compiled it with Icarus Verilog into a VVP file called "a.out", you could cause Icarus Verilog to generate an FST dumpfile (instead of a VCD dumpfile) by calling "vvp a.out -fst". This will cause an FST style dumpfile instead of the standard VCD style dumpfile. You can also transform many different dumpfile formats into an FST style dumpfile with the helper programs that come with the GtkWave waveform viewer. What is needed for VPI scoring? After Covered has been configured and built to include the creation of a VPI loadable module or shared object file (see for details), Covered is capable of scoring during a simulation run by using the VPI (Verilog Procedural Interface) access mechanism. This is done by loading the Covered VPI module (or shared object) into the simulator executable prior to running (depending on the simulator being used). The following steps should be taken to create a scored CDD file using this method. Create the Verilog file that will be compiled as a top-level module in the design (alongside the actual top-level(s)). This is done by running the score command with the -vpi option. The following example command-line shows how this step is done, creating a file called "covered_vpi.v". > covered score -t top -vpi Compile the simulator executable, including the previously generated file and the Covered VPI module. See the compile instructions for the Icarus Verilog, Cver or VCS simulators below. Run the simulation. Once simulation is complete, the resulting CDD file will be a completely scored database, ready to be merged with other CDD files from the same design or reported on. Compiling for Icarus Verilog If you are compiling an Icarus Verilog simulation, simply add -m tool_install_root/libexec/covered.vpi covered_vpi.v to the command-line. Compiling for Cver If you are compiling a Cver simulation, simply add +loadvpi=tool_install_root/libexec/covered.cver.so:vpi_compat_bootstrap covered_vpi.v to the command-line. Compiling for VCS If you are compiling a VCS simulation, simply add +vpi -load tool_install_root/libexec/covered.vcs.so:covered_register covered_vpi.v to the command-line. Compiling for NC-Verilog If you are compiling a NC-Verilog simulation, switch to NC-Verilog's irun command to load the covered shared object: -loadvpi tool_install_root/libexec/covered.ncv.so:covered_register and enable all access with -access +rwc. You can hardcode the $covered_sim call into your RTL or you can run it dynamically using the CLI, by adding the -input input.tcl switch to irun. Where the input.tcl file looks like the following and tb.dut is the coverage instance: covered-0.7.10/doc/docbook/chapter_using.xml0000644000076500007650000003116311340606227021011 0ustar trevorwtrevorw Using Covered Work Flow Covered has four basic commands that it uses for gaining coverage information about a design and displaying that information to the user. score merge report rank Scoring the Design To begin using Covered, you will need to create a special database file called a coverage description database (CDD). Covered uses this file to store coverage-specific information about the DUT. This file is a text-based file that is written in a specific format (the format of this file is not discussed in this document but can be found in the developer's document) that Covered understands. To create the CDD and populate it with the simulation dumpfile results, you must use the score (see for details) command. This command parses in the DUT files and generates an initial CDD for the design. This CDD does not contain any coverage details but only the design elements that Covered needs to gain coverage results. Once the initial CDD has been created, the score command reads in the specified VCD/LXT2 dumpfile from the given DUT. If Covered recognizes that the VCD/LXT2 dumpfile does not correspond to the DUT that it parses (dumpfile was not generated from the DUT specified), an error message is supplied to the user telling them this. Once the dumpfile has been parsed, Covered generates a new version of the CDD containing a populated database. This CDD may be merged with another CDD from the same DUT and/or reports may be generated from this CDD. Merging CDDs When two or more CDDs have been generated from the same DUT. It is often desirable to merge their contents to see what the total coverage is for both simulation runs. The reasons why merging is desirable is that often several tests are written to exercise the entire design (not just one). This makes tests easier to write and maintain. Since, typically, only one test is run per simulation run and that test does not fully test the DUT, it is necessary to combine the results of the multiple simulations to the see the combined effect of the tests on the design. This is where merging comes into play. Merging multiple CDDs from the same design is easy with Covered, and is accomplished with the merge (see for details) command. This command reads in two or more CDDs, merges their results and outputs the merged CDD to a different file or replaces the first CDD with the results of the merge. Creating Coverage Reports After a CDD is created or merged, the contents of the CDD can be extracted and transformed into human-readable coverage reports with the report (see for details) command. A summary report containing the percentage of metrics covered is generated for each module. Additionally, to aid in understanding what and why something was not covered, a verbose reporting mechanism exists. Verbose reporting will explicitly point to and describe why something was not fully covered for a specific metric. Reports are text-based output that by default are directed toward standard output but may, with the use of an option flag, be output to a specific file for storage purposes. Ranking CDDs After a collection of CDDs have been generated from a single design (most likely due to a regression run), it is desirable to know which CDDs have an effect on coverage and which CDDs do not add any new coverage information. The CDDs that do not provide additional coverage may be unnecessary for regression and removing them may significantly improve a regression runs time (which can help in a projects schedule). Additionally, it also good to know an order that simulations should be run in to produce the maximum amount of coverage the quickest. This information can be useful for creating a quick (or "sanity check" or "confidence") regression that runs in a relatively short period of time and, when run successfully, provides the engineer a level of confidence that recent changes have not severely broke the functionality of the design. This is the purpose of the rank (see for details) command. It produces a report that shows the diagnostics that add to the overall coverage of the suite, the order that those diagnostics should run, and each diagnostic's overall effect on coverage when it is run. Excluding CDD Coverage Points Not all unhit coverage points reported by Covered will be valid for your design. Some coverage points may be extraneous, some may be due to obsolete logic that is not pulled from the design for various reasons, and some coverage points may be hit in other verification environments but not in the current environment. Whatever the reason may be (and some reasons may be much more specific that these suggestions), Covered allows the user to exclude those coverage points from coverage reporting (they will still be reported but they will be considered "covered" points instead of "uncovered" points). Additionally, each excluded coverage point can have an option message attached to it that explains the reason for exclusion. This message is stored with the coverage information in the CDD file and can be displayed in a standard coverage report or in a stand-alone exclusion report. This information helps to document the coverage analysis process. In addition to being able to exclude coverage points, the user can also include previously excluded coverage points (in the event that a mistake was made or if the design has changed). Coverage exclusion can be accomplished via the command-line exclude command or within the GUI coverage analyzer. Covered usage Covered is initiated with the following command: covered (-h | -v | [-P [filename]] [-B] [-D|-T|-Q]) (score|merge|report|rank) command_options) The -v command (described below) is mutually exclusive from the rest of the commands and has the highest priority. If Covered is called with this option and any other options, the version will only be displayed. The -h command (described below) is mutually exclusive from the rest of the commands and has the second highest priority. If Covered is called with this option and the -v option is not specified, the usage information will be displayed to the screen. The -Q option suppresses all normal user output from standard output. The only output that will not be suppressed are messages to standard error. This option may be used with any of the Covered commands to achieve this effect. By default, normal user output is sent to standard output. The -T option suppresses all normal user output from standard output with the exception of the Covered header banner, warning messages. This type of output is a bit more informative than output generated with the -Q option but not as much as running without any output limiters. The -D option outputs debug information to standard output. Its effect overrides the -Q option. This option may be used in conjunction with any other Covered command for the purposes of debugging tool failures. By default, debug mode is turned off and must be enabled in the build of Covered (using the --enable-debug option to configure). This command should only be used for debugging as it generates an immense amount of output which may hinder performance. The -B option obfuscates all design-sensitive signal, module, task, function, instance, file and parameter names when outputting them to either stdout, stderr or a file (with the exception of CDD file output). This mode is intended to be used for sharing output information with others (including the developer's of Covered) which is sensitive information for the purposes of debugging. The -P option causes Covered to enable internal code profiling and generates a profiling report that is output to either the given filename or the default filename of "covered.prof". This option is only available if the --enable-profiling configuration option is specified and will cause performance degradation. This option should only be used by Covered developers or those interested in finding performance bottlenecks in Covered's code. It is not recommended that the --enable-profiling configuration option and the -P global option be specified for normal users of Covered. See for more information on profiling and understanding the profiling report file. Covered global options The following table describes options that Covered will accept apart from its normal commands which are described in the next several chapters. Global Options to Covered Option Description -Q Quiet mode. Suppresses user output to screen. Use in conjunction with a command. -T Terse mode. Causes all output to be suppressed with the exception of warning messages and the Covered header information. Use in conjunction with a command. -D Debug mode. Outputs code debug information to screen. Use in conjunction with commands. -B Obfuscate. Obfuscates all design sensitive names before outputting them. -P [filename] Profiling mode. Outputs profiling report to either the given filename or "covered.prof" if no filename was specified. -h Generates usage output to standard output. -v Outputs current version of Covered.
covered-0.7.10/doc/docbook/covered.xsl0000644000076500007650000000471211426534466017625 0ustar trevorwtrevorw #dfeef8 black #0000FF #840084 #0000FF
covered-0.7.10/doc/docbook/covered_doc.xml0000644000076500007650000000672211353136363020440 0ustar trevorwtrevorw ]> Covered User's Guide - 0.7.9 Verilog Code Coverage Analyzer Trevor Williams
phase1geo@gmail.com
0.7.9 2008-2010 Trevor Williams Overview &cintro; &cmetrics; &cboundaries; &crace; &cattributes; Installation &cinstallation; Command-line Usage &cstarting; &cusing; &cscore; &cmerge; &creport; &crank; &cexclude; &creading; &cdebug; Graphical User Interface &cguiintro; &cguimain; &cguiline; &cguitoggle; &cguimemory; &cguilogic; &cguifsm; &cguiassert; &cguiassertsrc; &cguinew; &cguireportgen; &cguirank; &cguipreferences; &cguiexclude; &cguiwizard; FAQ &cfaq; Epilogue &cepilogue; covered-0.7.10/doc/docbook/Makefile.am0000644000076500007650000000013311053051400017445 0ustar trevorwtrevorwhtml: XML_CATALOG_FILES="catalog.xml" xsltproc covered.xsl covered_doc.xml covered-0.7.10/doc/docbook/Makefile.in0000644000076500007650000002273211475644670017520 0ustar trevorwtrevorw# Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; 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Chapter 5. Inline Attributes
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Chapter 5. Inline Attributes

Table of Contents

5.1. What are inline attributes?
5.2. Adding FSM attributes

5.1. What are inline attributes?

In the IEEE Verilog 1364-2001 standard, an attribute is a way to add information to a Verilog object, statement or groups of statements that is tool-specific and does not affect simulation of that design. All Verilog-2001 attributes begin with the token (* and end with the token *). An attribute can be multi-line and is "attached" to the Verilog object, statement, or group of statements that is specified immediately beneath the attribute.

Covered uses the Verilog-2001 attribute for allowing users to specify coverage-specific information about embedded objects within a particular design. When an attribute is found, it is interrogated to see if it is a Covered attribute. If the attribute is a Covered attribute, its contents are parsed. If the attribute is not found to be a Covered attribute, it is ignored and parsing continues normally.

The rest of this chapter specifies the attributes that Covered is capable of handling, along with their use and syntax.

5.2. Adding FSM attributes

There are two ways that Covered currently allows the user to specify the location of and information about FSMs embedded in a particular design. The first way to specify an FSM is on the score command-line. The benefit to specifying the location of a state machine this way is that the source code does not need to be modified. The potential disadvantage to this method is that the FSM location and coverage information can get lost if the FSM is used in a different testbench (or even a different project if the FSM code is reused in a later project). For more information on specifying an FSM on the score command-line, please refer to Section 9.6, “Scoring FSMs”.

The second way that an FSM can be specified to Covered is through the use of the Verilog-2001 attribute. The advantages to using this method are that the FSM information specified in an attribute stays embedded in the design (for ease of reusing the FSM and still retaining information relevent to coverage). Additionally, at the current release of Covered, using attributes to specify an FSM is the only way to tell Covered what all of the valid states and state-transitions are for a specific FSM (the command-line specification does not allow for this). This provides a unique advantage of this method over the command-line method. The potential disadvantage of this method for specifying FSM information is that source code needs to be modified.

To learn how to specify an FSM attribute within a design, let's use an example of an FSM that is embedded in a design.

Example 5.1. Module Containing an Embedded FSM

  module foo (
    input clk,
    input reset,
    input head,
    input tail,
    input valid
  );
      
    parameter STATE_IDLE = 2'b00,
              STATE_HEAD = 2'b01,
              STATE_DATA = 2'b10,
              STATE_TAIL = 2'b11;
                
    reg [1:0] state;
    reg [1:0] next_state;
      
    always @(posedge clock)
      state <= reset ? STATE_IDLE : next_state;
        
    always @(reset or state or head or valid or tail)
      begin
        case( state )
          STATE_IDLE: next_state = (valid & head) ?
                                     STATE_HEAD : STATE_IDLE;
          STATE_HEAD: next_state = (valid & tail) ?
                                     STATE_TAIL : STATE_DATA;
          STATE_DATA: next_state = (valid & tail) ?
                                     STATE_TAIL : STATE_DATA;
          STATE_TAIL: next_state = (valid & head) ?
                                     STATE_HEAD : STATE_IDLE;
        endcase
      end   
      
  endmodule


This example shows an FSM that has an input FSM variable called "state" and an output FSM variable called "next_state". There are four states in the state machine that are represented with the parameters located in this module (STATE_IDLE, STATE_HEAD, STATE_DATA, STATE_TAIL). There are a total of eight (8) state transitions that this FSM can take. They are the following:

  1. STATE_IDLE -> STATE_IDLE (loopback)

  2. STATE_IDLE -> STATE_HEAD

  3. STATE_HEAD -> STATE_DATA

  4. STATE_HEAD -> STATE_TAIL

  5. STATE_DATA -> STATE_DATA (loopback)

  6. STATE_DATA -> STATE_TAIL

  7. STATE_TAIL -> STATE_HEAD

  8. STATE_TAIL -> STATE_IDLE

All attributes that specify information for an FSM are a comma-separated list of values that contain the following information:

  1. "covered_fsm" attribute keyword

    • MUST be first value in the attribute list

    • Specifies to Covered that this attribute contains information for an FSM that Covered needs to handle.

  2. FSM identifier

    • MUST be second value in the attribute list

    • Specifies a alphanumeric name for this FSM.

    • The name will eventually be used to tie individual attributes that specify information for the same FSM.

  3. Input state expression (optional)

    • Syntax: is="expression"

    • If this is specified, MUST be specified third in the list.

    • Specifies the input state expression.

    • Can be a combination of signal names, signal bit selects, and concatenation operators.

    • See Section 9.6, “Scoring FSMs” for more information on the specification of an input state expression.

  4. Output state expression

    • Syntax: os="expression"

    • If the input state expression is specified, MUST be fourth value in list; otherwise, MUST be third value in list.

    • Specifies the output state expression of the FSM.

    • Can be a combination of signal names, signal bit selects, and concatenation operators.

    • See Section 9.6, “Scoring FSMs” for more information on the specification of an output state expression.

  5. State-transition specifiers (optional)

    • Syntax: trans="from_state->to_state"

    • MUST be specified after the above has been specified in the list.

    • Arguments MUST be constant values (parameters; numerical values -- binary, octal, decimal, hexidecimal; and defines that equate to one of these two types of values).

    • Each transition that is specified is a unique value in the attribute list.

    • You may optionally add characters after the "trans" keyword and before the '=' character (with the exception of the '=' character) to make each transition parameter name unique. Covered will ignore these extra characters, but this can be useful to avoid warning messages that may get emitted from your Verilog compiler when these attributes are parsed (some compilers expect each parameter name in an attribute list to have a unique name). This feature was put in the 0.7.8 stable release.

To specify the FSM attribute in the above example, including input state, output state and all state transitions, the code would be modified to look like:

Example 5.2. FSM Attribute Code Sample

  (* covered_fsm, channel, is="state", os="next_state",
                           trans="STATE_IDLE->STATE_IDLE",
                           trans="STATE_IDLE->STATE_HEAD",
                           trans="STATE_HEAD->STATE_DATA",
                           trans="STATE_HEAD->STATE_TAIL",
                           trans="STATE_DATA->STATE_DATA",
                           trans="STATE_DATA->STATE_TAIL",
                           trans="STATE_TAIL->STATE_HEAD",
                           trans="STATE_TAIL->STATE_IDLE" *)
  always @(reset or state or head or tail or valid)
    ...


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covered-0.7.10/doc/html/chapter.boundaries.html0000644000076500007650000003036011426534466021436 0ustar trevorwtrevorwChapter 3. Coverage Boundaries
Chapter 3. Coverage Boundaries
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Chapter 3. Coverage Boundaries

Table of Contents

3.1. What logic can be analyzed?
Verilog-1995 constructs
Verilog-2001 constructs
SystemVerilog constructs
3.2. What logic cannot be currently analyzed?
Verilog-1995 constructs
Verilog-2001 constructs
3.3. What is done with code blocks that contain code that cannot be analyzed?

To properly evaluate the effectiveness of any coverage tool, it is necessary to understand what kinds of logic are able to be analyzed and which kinds of logic are unable to be analyzed (along with a reason for why the logic cannot be adequately covered). Understanding the limitations of tools up front can often guide the user of those tools to make better decisions in their usage. In the case of Covered and the open source community, it may also help drive ideas to how to correct or get around these limitations.

For these reasons, a list of what type of logic can be analyzed and what type of logic cannot be currently analyzed is listed below. Note that both of these lists may not be exhaustive and are subject to change between releases of the tool. Also note that it is the goal of Covered to be able to parse all of the Verilog-1995, Verilog-2001, and a subset of SystemVerilog constructs though some portions of these may be ignored for coverage purposes.

3.1. What logic can be analyzed?

Verilog-1995 constructs

  1. All expressional logic which is comprised of the following data types and operators which exist in an assign block, always block, initial block, task, function or named begin/end block:

    • Nets: wire, tri, tri0, tri1, wor, wand, trior, triand, supply0, suppl1

    • Triregs: trireg

    • Registers: reg

    • Parameter values

    • String values

    • Integer values

    • Unary operators: +, -, ~, &, |, ^, ~&, ~|, ~^

    • Arithmetic operators: +, -, *, /, %

    • Logical operators: &&, ||, !

    • Relational operators: >, <, >=, <=

    • Equality operators: ==, ===, !=, !==

    • Bitwise operators: &, |, ^, ~&, ~|, ~^

    • Shift operators: <<, >>

    • Concatentation/replication operators: {}, {{...}}

    • Bit select operators: [], [:]

    • Conditional operator: ?:

  2. case, casex, casez statements

  3. if, if/else statements

  4. Delays when delay value is integer

  5. Delayed procedural assignments (i.e., "a = #5 b;" or "a = @(c) b;")

  6. Event waits and triggers: wait, @(posedge), @(negedge), @(), ->

  7. Repetition statements: for, while, repeat

  8. Fork/join statements

  9. Memories

  10. $finish and $stop system calls

  11. $time and $random system functions

  12. Real numbers

  13. Real number system tasks: $rtoi, $itor, $realtobits, $bitstoreal

  14. $test$plusargs system function

  15. The following system tasks are allowed within logic blocks being considered for coverage:

    $display, $dumpall, $dumpfile, $dumpflush, $dumplimit, $dumpvars, $dumpoff, $dumpon, $fdisplay, $fmonitor, $fstrobe, $fwrite, $history, $key, $list, $log, $monitor, $monitoroff, $monitoron, $nokey, $nolog, $printtimescale, $showscopes, $showvariables, $showvars, $strobe, $timeformat, $write

Verilog-2001 constructs

  1. `ifndef and `elsif directives

  2. `file and `line directives

  3. Constant functions calls

  4. Inline parameter passing by name

  5. Localparam support

  6. Implicit event sensitivity lists: @*

  7. Comma-separated event lists (alternative to the "or" keyword)

  8. Signed value support

  9. Immediate register assignment (i.e., reg a = 1'b0)

  10. Variable multi-bit selects (i.e., a[b+:3], a[b-:3])

  11. Exponential power operator: a**b

  12. Arithmetic shift operators: <<<, >>>

  13. Pre-port parameter listing (i.e., module foo #(parameter a=0) (...);)

  14. Inline port listing (i.e., module foo (input wire a, output reg b);)

  15. Attributes (note: Covered only performs attributes that it recognizes)

  16. Arrays of instances

  17. Generate blocks

  18. "Automatic" or reentrant tasks/recursive functions

  19. $value$plusargs system function call

  20. The following system tasks are allowed within logic blocks being considered for coverage:

    $dumpports, $dumpportsall, $dumpportsoff, $dumpportson, $dumpportslimit, $dumpportsflush, $fclose, $ferror, $fflush, $swrite, $swriteb, $swriteh, $swriteo, $ungetc

SystemVerilog constructs

  1. New integer types: char, byte, bit, logic, int, shortint, longint

  2. Op-and-assign statements: +=, -=, *=, /=, %=, &=, |=, ^=, <<=, >>=, <<<=, >>>=, ++, --

  3. Proper support for always_comb, always_latch, always_ff, final blocks

  4. do..while loops

  5. Enumerations

  6. Typedefs

  7. $root scope support

  8. Unnamed scope support

  9. Multi-dimensional arrays including packed/unpacked dimensions and bit-select, part-select and slicing

  10. Parsing support for unique and priority if/case labels

  11. Parsing support for implicit .name ports (i.e., foo f( .a, .b, .c );)

  12. Parsing support for implicit .* ports (i.e., foo f( .* );)

  13. Parsing support for assertions, properties and sequences

  14. Functional support for $urandom, $urandom_range, $srandom, $shortrealtobits, $bitstoshortreal

3.2. What logic cannot be currently analyzed?

Verilog-1995 constructs

  1. All gate types (i.e., buf, not, or, and, etc.)

  2. All user defined primitives (UDPs)

  3. System task calls (or any $... call) that are not mentioned in the supported list above

Verilog-2001 constructs

  1. Configuration statements

3.3. What is done with code blocks that contain code that cannot be analyzed?

When logic is encountered that cannot be analyzed within an always, initial, task, function or named block, Covered will disregard the entire always block. If the entire block cannot be analyzed, it does not try to get coverage statistics as these will most likely be incorrect (i.e., disregarded logic could affect the state of the logic that is being covered).

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covered-0.7.10/doc/html/chapter.debug.html0000644000076500007650000005513711426534466020402 0ustar trevorwtrevorwChapter 15. Debugging
Chapter 15. Debugging
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Chapter 15. Debugging

Table of Contents

15.1. Verbose Debug Output
Building Covered for Verbose Debug Outputting
15.2. Command-Line Interface (CLI)
Building Covered for the CLI
Using the CLI
CLI commands
15.3. Source Code Profiling
Building Covered for Profiling
Using Source Code Profiling
Understanding the Profiling Report

As much as it pains the developers of Covered to admit, there will be times when a user of Covered will encounter a problem in the resimulation process or will experience a performance issue during certain runs and will want to investigate the issue a bit themselves before posting a bug report. There may also be people out there who just might want to learn more about how Covered operates "under the hood". For those people whom I have just mentioned, this section is for you.

15.1. Verbose Debug Output

The brute force method of understanding Covered's internals is to generate verbose debug output using the global "-D" option to any of Covered's commands. The user of this method should take care to note that using this option may generate an extremely large amount of output and will definitely cause Covered's runtime performance to degrade considerably. If this option is used, its output should probably be redirected to a file for post-processing purposes. It should be noted that the verbose debug output is most useful for the developer's of Covered and is not meant to be of much help to the normal user.

Building Covered for Verbose Debug Outputting

Because generating verbose debug output can have a tremendous degradation in performance when it is even compiled, Covered requires the user to specify an option to the configuration/build process to enable this feature. To enable verbose debug outputting, simply specify the --enable-debug option to the configure script. This will cause Covered to compile in verbose debug output support and enable the use of the -D global option.

[Note]Note

If the user has not specified the --enable-debug option to the configuration script but proceeds to specify the -D global option, Covered will emit a warning message that it is unable to output verbose debug information due to the lack of the --enable-debug option being specified. It will then proceed to ignore the -D option.

15.2. Command-Line Interface (CLI)

As an alternative to simply outputting the verbose debug output from Covered, the score command comes equipped with its own interactive debugging mechanism called the CLI (Command-Line Interface). This interface is a command-line driven utility that starts at the beginning of the resimulation. Its purpose is to allow the user to step through simulation execution and view the contents of signals, time, scopes, code and internal thread queues for the purposes of debugging and/or understanding Covered. This utility works much in the same way as simulator CLIs and the GDB debugging utility.

Building Covered for the CLI

Because interactive command-line debugging has a small performance penalty when compiled in and is closely associated with the verbose debug output option, Covered requires the user to specify an option to the configuation/build process to enable this feature. To enable the CLI, simply specify the --enable-debug option to the configure script. This will cause Covered to compile in CLI capabilities and enable the user of the -cli score command option.

Using the CLI

To allow the score command to use the CLI for interactive resimulation, simply specify the -cli [filename] option to the score command. If filename is specified to this option, the contents of this file will be parsed and executed once the score command has reached the resimulation process. The contents of this file are a series of CLI commands (one command per line) in ASCII format and can be automatically produced with the "savehist" CLI command (see below). This feature allows a user to quickly save off the CLI commands made during one score run and reuse them in a subsequent score run without having to remember and manually input the same commands.

Once the -cli option is invoked, Covered will run the score command until it gets to the beginning of the resimulation process. At this time, if the optional filename is specified, it will parse the contents of this file and execute the CLI commands found there until all commands are executed. If filename was not specified, a prompt will be displayed and the resimulation execution will halt until the user has specified otherwise via command-line options. After entering a command-line option, simply press return to invoke that command. In the event that the command was a step, next or continue option, resimulation will resume until it reaches the next stop point.

During resimulation, if the -cli option is specified to the score command, the user may stop simulation at any time by hitting Ctrl-C. This will stop the simulation and display a CLI prompt where the user may continue to interact with the simulation.

CLI commands

The following is a list of all of the CLI options available to the user:

Table 15.1. CLI Command-line Options

OptionDescription
step [num] Advances to the next statement if num is not specified; otherwise, advances num statements before returning to the CLI prompt.
next [num] Advances to the next timestep if num is not specified; otherwise, advances num timesteps before returning to the CLI prompt.
goto time num Simulates to the given timestep (or the next timestep after the given value if the timestep is not executed) specified by num.
goto line [filename:]num Simulates until the specified line is the next line to be executed. If filename is specified, the line specified by num within that file is the line to stop on. If filename if not specified, the current filename is used.
goto expr name bool_op value Simulates until the given expression is evaluated to true where name is the name of a signal in the design to evaluate, bool_op is a boolean operation (i.e., ==, !=, ===, !==, <, <=, >, >=), and value is a legal Verilog value (i.e., 30, 4'h0, etc.).
run Runs the simulation to completion.
continue Continues running the simulation to completion.
thread active Displays the current state of the internal active simulation queue. This queue consists of process threads that will be executed in the current timestep.
thread delayed Displays the current state of the internal delayed simulation queue. This queue consists of process threads that will be executed at a later time as dictated by a delay statement.
thread waiting Displays the current state of the internal waiting simulation queue. This queue consists of process threads that are not active or delayed but may be activated by a value change in one of the signals in its expression tree.
thread all Displays the current state of all process threads in the simulator.
current Displays the current scope, block, filename and line number of the statement that is about to be executed in the active queue.
time Displays the current simulation time.
signal name Displays the current value of the given net/variable.
expr num Displays the given expression and its current value where num is the ID of the expression to output.
debug [less | more | off] Specifies the amount of debug information that is output during simulation. The value of 'less' only outputs the current statement that is being executed (along with line number). The value of 'more' outputs verbose output that is really only useful for the developer's of Covered. The value of 'off' turns off all debug output during simulation. If 'less', 'more', or 'off' is not specified, displays the current debug mode.
list [num] Lists the contents of the file where the current statement is to be executed. If num is specified, outputs the given number of lines; otherwise, outputs 10 lines.
savehist filename Saves the current history to the specified file.
history [(num | all)] Displays the last 10 lines of command-line history. If 'all' is specified, the entire history contents will be displayed. If num is specified, the last num commands will be displayed.
!num Executes the command at the num position in history.
!! Executes the last valid command.
help Displays the available command-line options.
quit Ends simulation immediately.

15.3. Source Code Profiling

The built-in source code profiling facility allows the user to run any Covered command and understand performance metrics about the internal Covered source code, such as how many times a given function was called, how much wall-clock time was spent executing a given function, how many times a function allocated and deallocated memory from the heap, etc. This information can be useful in understanding where performance bottlenecks are during a given Covered command run. This feature does not provide the end-user any useful information about the design that they are testing.

Building Covered for Profiling

Because internal source code profiling is not a function of obtaining Verilog code coverage and adds a performance penalty for being compiled in and used, Covered requires the user to specify an option to the configuration/build process to enable this feature. To enable internal source code profiling, simply specify the --enable-profiling option to the configure script. This will cause Covered to compile in profiling capabilities and enable the use of the -P global option.

[Note]Note

If the user has not specified the --enable-profiling option to the configuration script but proceeds to specify the -P global option, Covered will emit a warning message that it is unable to do profiling due to the lack of the --enable-profiling option being specified. It will then proceed to ignore the -P option.

Using Source Code Profiling

Once Covered has had profiling functionality configured and built into it, the user may optionally enable profiling for any command by specifying the -P [filename] global option. If the -P option is specified without a filename associated with it, the profiling report generated from the command run will be output to a file called "covered.prof" in the same directory where Covered was run. If a filename is associated with the -P option, the contents of the profiling report will be output to that file.

[Note]Note

The specified filename can be anything except "score", "merge" or "report" as this name will be interpreted by Covered's command-line parser to indicate the type of command being run. If one of these command keywords are specified after the -P option, it is assumed that the user has not specified a filename and the contents of the profiling report will be sent to the default file of "covered.prof".

Understanding the Profiling Report

After a command has been run with the global -P option specified, a report file will contain several profiling statistics, including the following:

  1. The amount of time spent running the entire command

  2. The number of times each executed function was called

  3. The total amount of wall clock time spent executing each function

  4. The average amount of time spent executing each function

  5. The number of times each function allocated heap memory

  6. The number of times each function deallocated heap memory

In addition to providing this information on a per function basis, the profiling report also provides the information in three different sections with each function ordered from most to least by the following statistic columns:

  1. The number of times each executed function was called

  2. The total amount of wall clock time spent executing each function

  3. The average amount of time spent executing each function

By ordering this information, it will help the users and developers determine where the performance bottlenecks in execution are for a given command run.

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Chapter 32. Epilogue
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Chapter 32. Epilogue

Table of Contents

32.1. Author
32.2. Special Thanks
32.3. Reporting Bugs
32.4. Mailing List
32.5. Homepage
32.6. Copyright and Licensing
GNU GENERAL PUBLIC LICENSE

32.1. Author

Covered is programmed and documented by Trevor Williams ()

32.2. Special Thanks

I would like to acknowledge certain individuals for their help in making Covered the tool that it is today.

  • Ed Spittles - Thank you for your tireless efforts in logging bugs, providing suggestions on enhancements/optimizations (including the tip on using of FIFOs to replace VCD/LXT2/FST file usage), your input into scoring optimizations for vectors and CDD ranking, and for allowing me access to needed information for fixing those "hard to reproduce" bugs.

  • Clifford E. Cummings - provided race condition checking rules and clarifications about those rules.

  • Stephen Williams - Thanks for helping me understand some of the ins and outs of what's required "under the hood" to handle some of Verilog's constructs.

  • Daniel McMahill - testing and patches for 64-bit compatibility

32.3. Reporting Bugs

If you have read this user's guide, chances are that you might be a Covered user. As such, it is encouraged that any bugs that you might find while using Covered get reported so that this project may become more stable for yourself and for other users. To submit a bug report or a request for enhancement, you may either send an e-mail to Trevor Williams (see Section 32.1, “Author” or, if you have a SourceForge login, can report a bug by going to:

http://sourceforge.net/projects/covered

and clicking on the "Bugs" link.

32.4. Mailing List

The Covered project has a user mailing list. Whenever there are stable releases being made of the project, an e-mail will get sent out to this list stating the new release is available. Additionally, the mailing list is a great way to bring up usability issues with the tool and, of course, bugs. The mailing list can also be useful if you have a question about using Covered -- there is probably someone else who has encountered the same problem that might be able to provide you with some help.

To subscribe to this e-mail list, please visit the following URL, enter the prescribed information and click on the "Submit" button.

http://lists.sourceforge.net/lists/listinfo/covered-users

32.5. Homepage

The Covered project homepage is established on SourceForge at the following URL address.

http://covered.sourceforge.net

32.6. Copyright and Licensing

This program is distributed under the GNU Public License GPL.

GNU GENERAL PUBLIC LICENSE

Version 2, June 1991

Copyright (C) 1989, 1991 Free Software Foundation, Inc. 675 Mass Ave, Cambridge, MA 02139, USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed.

Preamble

The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software-to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Library General Public License instead.) You can apply it to your programs, too.

When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things.

To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it.

For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights.

We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software.

Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations.

Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all.

The precise terms and conditions for copying, distribution and modification follow.

Terms and Conditions for Copying, Distribution, and Modification

  • [0.] This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The ``Program'', below, refers to any such program or work, and a ``work based on the Program'' means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term ``modification''.) Each licensee is addressed as ``you''.

    Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does.

  • [1.] You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program.

    You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee.

  • [2.] You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions:

    • [a.] You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change.

    • [b.] You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License.

    • [c.] If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.)

    These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it.

    Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program.

    In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License.

  • [3.] You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following:

    • [a.] Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or,

    • [b.] Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or,

    • [c.] Accompany it with the information you received as to the offer to distribute corresponding source code. (This alternative is allowed only for noncommercial distribution and only if you received the program in object code or executable form with such an offer, in accord with Subsection b above.)

    The source code for a work means the preferred form of the work for making modifications to it. For an executable work, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the executable. However, as a special exception, the source code distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable.

    If distribution of executable or object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place counts as distribution of the source code, even though third parties are not compelled to copy the source along with the object code.

  • [4.] You may not copy, modify, sublicense, or distribute the Program except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense or distribute the Program is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance.

  • [5.] You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Program or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it.

  • [6.] Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License.

  • [7.] If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Program at all. For example, if a patent license would not permit royalty-free redistribution of the Program by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Program.

    If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply and the section as a whole is intended to apply in other circumstances.

    It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system, which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice.

    This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License.

  • [8.] If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License.

  • [9.] The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns.

    Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and ``any later version'', you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation.

  • [10.] If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally.

    NO WARRANTY

  • [11.] BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM ``AS IS'' WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION.

  • [12.] IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.

    END OF TERMS AND CONDITIONS

Appendix: How to Apply These Terms to Your New Programs

If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms.

To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the ``copyright'' line and a pointer to where the full notice is found.

Copyright © 20yy This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version.

This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details.

You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.

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Chapter 13. The exclude Command
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Chapter 13. The exclude Command

Table of Contents

13.1. Usage
13.2. Options

The exclude command allows the user to exclude uncovered coverage points from coverage (effectively turning the uncovered points into covered points) or include coverage points that were previously excluded. Additionally, the exclude command allows the user to specify a reason why the coverage point is being excluded. This capability allows for good documentation of these coverage points for later evaluation and can be output into various report formats to go along with a verification testplan.

13.1. Usage

The exclude command is specified with the given call:

covered [global options] exclude [options] exclusion ID+ CDD file

The exclusion ID information can be obtained via a Covered report command call with the -d (d|v) and -e options. Exclusion IDs consist of an alphanumeric value that will be specified with parenthesis prior to a coverage point.

You may specify one or more exclusion IDs per call to the exclude command. If the -m option is specified, a prompt will be specified for each exclusion ID, individually. If a coverage point is currently included in the CDD prior to an exclude call, the coverage point will be toggled to be excluded and a user message can be attached to the coverage point, specifying the reason for exclusion. If a coverage point is currently excluded in the CDD prior to an exclude call, the coverage point will be toggled to be included and any previouly assigned user message will be forgotten.

13.2. Options

Table 13.1. Options to the exclude command

Option Description
-f filename Allows the user to specify a file that contains additional exclude command options to parse. This option may be specified more than once for a single call to the exclude command.
-h Displays help information for the exclude command.
-m Allows a user message specifying the reason for excluding any coverage points being excluded on the command-line. An interactive prompt will be specified in the shell. Simply enter your reason at the prompt, hit return and specify a single period (.) character followed by a return to end the user input for a coverage point. You may use as many lines of text that you would like; however, all formatting characters (i.e., newlines, tabs, extra spaces, etc.) will be removed when reporting the information.
-p Outputs the current exclusion status of the specified exclusion ID(s) and displays any exclusion reason messages associated with the specified exclusion ID(s) to standard output.


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Chapter 31. FAQ
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Chapter 31. FAQ

This page contains a list of accummulated Frequently Asked Questions. If you are having difficulties using Covered or have questions that are not answered in the User's Guide, please check this list for answers. If you do not find the information that you are looking for in the User's Guide or this FAQ, please send an e-mail to:

31.1. Is a CDD file generated from a newer version of Covered compatible with a CDD file generated from an older version?
31.2. When I run the score command, Covered seems to take a long time to run. Is there anything that I can do to speed up scoring?
31.3. I get an assertion error when running Covered, what should I do?
31.4. Covered is giving me a parser error for Verilog code that seems to be syntactically correct. What is wrong?
31.5. Is Covered's Verilog parser Verilog-2001 compliant?
31.6. What is the difference between the stable release and the development release?
31.1.

Is a CDD file generated from a newer version of Covered compatible with a CDD file generated from an older version?

The answer to this question is, "Well, that depends...". Since the format of the CDD file is only used by Covered, the contents and format of this file may be changed to suit the needs of Covered. This means that it is possible for a CDD file created from an older version of Covered to be incompatible with a newer version. Additionally, the developers of Covered will not make any attempts to make sure that older CDD files can be properly read by a newer version of Covered. It is suggested that any CDD files generated from a particular version of Covered be merged and/or reported on by that same version, and if Covered is upgraded, new CDD files should be generated.

This being said, it is also a possibility that between versions of Covered a "backwards compatibility" may be maintained if a change to this file's format is not required.

31.2.

When I run the score command, Covered seems to take a long time to run. Is there anything that I can do to speed up scoring?

While Covered is continuously being enhanced to provide better performance for all commands (especially the score command), it may still take a while to complete scoring if one or more of the following is true:

  1. The design being scored is sufficiently large

  2. The VCD/LXT2/FST dumpfile is sufficiently large

  3. The VCD/LXT2/FST dumpfile contains dump information for a part of the design not being scored

  4. When Covered was configured, the --enable-debug and/or --enable-profiling options were specified

If reason (1) is true, speeding up each run can be achieved by one of the following suggestions:

  • Reduce the scored design in size by eliminating modules or constructs from its design tree. (See Section 9.3, “Specifying What to Cover” for more information on how to accomplish this)

  • Split up the design into smaller parts along module boundaries and generate coverage for those parts.

    [Note]Note

    It is not currently possible to append these modules into one file. Merging and reporting must be done on these smaller pieces independently from one another.

If reason (2) is true, nothing can be done except to shorten the run time of the diagnostics to produce shorter dumpfiles.

If reason (3) is true, the $dumpvars call in the simulator should be modified to only generate VCD/LXT2/FST dump information for the modules included in scoring. If there are modules not being scored which are included in the $dumpvars calls, please remove these unnecessary modules from dumpfile output.

If reason (4) is true, Covered should be reconfigured without these options specified. The debugging and profiling facilities are enormous performance degraders and immediate simulation performance enhancement will be seen if Covered is rebuilt without these options specified.

If you believe that you have a situation which is void of these prevailing reasons and Covered is still running slowly, please send an e-mail to me. I will consider these problems to be of lower priority than actual bugs but will look into the situation to see where code can be optimized.

31.3.

I get an assertion error when running Covered, what should I do?

Covered uses C assertions to make sure that internal pointers are not be referenced when NULL and that certain internal situations do not arise. If you receive some type of assertion error when running Covered, it means that something went wrong internally in Covered. The error is NOT due to user error. Please submit a bug report containing the assertion error message, file and line number. Additionally, run the Covered command with the -D global option (covered -D command) and provide the output from doing this with the bug report (please only specify tail of output if the output is too lengthy).

If Covered provides any other type of error message (something other than a core dump), Covered has found a user error that must be fixed by the user. Please do not submit bug reports if these errors are encountered, unless you wish to add a question about it to the FAQ.

31.4.

Covered is giving me a parser error for Verilog code that seems to be syntactically correct. What is wrong?

If Covered displays a syntax (parse) error during the score command and the Verilog code is written correctly, it is because Covered's parser is incomplete. Please submit a bug or send an e-mail containing a code snippet of the unsupported Verilog.

31.5.

Is Covered's Verilog parser Verilog-2001 compliant?

This is currently being worked on. The parser should properly parse all code; however, not all Verilog-2001 constructs are considered for coverage due to lack of support for them in Covered's core. If there is code that will not parse that should, please submit a bug report for this.

31.6.

What is the difference between the stable release and the development release?

Covered's development consists of two active "branches": the stable branch and the development branch. When a new stable branch is created (ex. 0.4 or 0.5), it represents the latest version of the development branch. As Covered's development branch is worked on (adding new features, changes to the core, etc.), the stable branch remains in a feature frozen stage. Only bug fixes, documentation updates or minor enhancements (changes that will not affect the core code) are made to the stable branch. When a number of these changes have been accumulated on the stable branch, a snapshot of the stable branch is made available for public download (ex. 0.4.1). User's of the stable release should expect no major feature changes from minor rev to minor rev and should expect a somewhat polished version of the project (few if any bugs and correct user documentation).

User's of the development releases should expect to see more bugs and fewer documentation consistencies (although an attempt is made to minimize both) but should expect lots of feature additions, optimizations, improvements, etc. from release to release. Bug findings found in the stable release are applied to the development branch when applicable. It is important to note that both the stable and development releases contain a regression testbench that must fully pass before either release is made. This should minimize bugs in both releases and give user's of either branch a level of confidence that the release is usable.

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Part V. FAQ Home Part VI. Epilogue
covered-0.7.10/doc/html/chapter.gui.assert.html0000644000076500007650000002633011426534466021371 0ustar trevorwtrevorwChapter 23. Navigating the Assertion Coverage Window
Chapter 23. Navigating the Assertion Coverage Window
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Chapter 23. Navigating the Assertion Coverage Window

Table of Contents

23.1. Navigating the Assertion Coverage Window
23.2. Excluding/Including Assertion Coverage Points
23.3. Displaying a New Assertion Instance

The Verbose Assertion Coverage window allows the user to see exactly which coverage points were hit or missed for a selected assertion instantiation in the design and, if hit, how many times the assertion coverage point (ACP) was hit during simulation. Additionally, this window allows you to bring up the verbose assertion window to view the internal assertion module code for the currently selected assertion instance. This lets the user view the code to determine what logically needs to occur to hit a given ACP.

To view this window, select the "Assert" mode in the coverage bar in the main window and click on an underlined assertion instance name in the file viewer. Note that both covered and uncovered assertion instance names can be selected. Doing so will cause the Verbose Assertion Coverage Window to be displayed for the selected assertion instantiation. Figure 23.1, “Verbose Assertion Coverage Window” shows an example of a zero_one_hot assertion that had the "test_expr_change covered" ACP covered (hit twice during simulation) and the other two ACPs uncovered during simulation.

Figure 23.1. Verbose Assertion Coverage Window

Verbose Assertion Coverage Window


23.1. Navigating the Assertion Coverage Window

The window is made up of a simple table which contains the coverage point names within the selected assertion on the left and the number of times each of these coverage points were hit during simulation on the right. If a coverage point has not been hit, both the coverage point name and the number of hits (0) will be highlighted with the "uncovered" color selection as selected in the preferences window. If a coverage point has been hit at least once, both the coverage point name and the number of hits will be highlighted with the "covered" color selection as selected in the Preferences window.

Below the table the name of the currently selected assertion type is named. To view the source code for this assertion, simply click on the Show Code button at the bottom right-hand portion of the coverage table. This will cause the source code for this assertion to be displayed in a new assertion source viewer.

To exit this window, simply click on Close button. To see this help page for the assertion coverage window, click on the help (?) button.

23.2. Excluding/Including Assertion Coverage Points

Individual ACPs can be excluded/included for coverage consideration using the verbose assertion coverage window. This is accomplished by clicking on the "0" (ACP is currently included in coverage) or "E" (ACP is current excluded from coverage) value in the "# of hits" column. Changing an ACP from "0" to "E" (excluding the ACP from coverage consideration) will cause the exclusion reason popup window to be displayed, allowing you to specify a reason for excluding the ACP. Once a reason has been entered, the summary assertion coverage information to be recalculated and redisplayed in the listbox and the background color of the ACP will change from the uncovered to the covered background color. Changing an ACP from "E" to "0" (including the ACP for coverage consideration) will cause the summary assertion coverage information to be recalculated and redisplayed in the Main Window Summary Bar and background color of the ACP will change from the covered to the uncovered background color. Figure 23.2, “Example of excluded ACP” below shows the above assertion instance with the last coverage point excluded from coverage.

Figure 23.2. Example of excluded ACP

Example of excluded ACP


If all ACPs for a given assertion instance have been excluded from coverage consideration, the file viewer will automatically change the background color of the assertion instance name from the uncovered to the covered background color. The assertion instance name will still be underlined, allowing the user to still see the coverage information for that given assertion instance.

If the user excludes any ACP in the design, the Save CDD... option in the file menu will be enabled. This allows the user to save the excluded property either back to the CDD file (or to a newly named CDD file). Doing so will allow the user to load the CDD file at a different time and retain the knowledge of which ACPs have been excluded/included for coverage along with any specified reasons for exclusion. Additionally, if a saved CDD file with coverage exclusion is merged with another CDD file, the excluded ACP information is preserved for the resulting merged CDD file.

If an ACP has been excluded from coverage and an exclusion reason was specified, you can view the reason for exclusion by right-click-and-holding on the "E" next to the ACP. This will cause a tooltip-style window to be displayed specifying the reason for exclusion. The background color of the tooltip will be the same color as the "covered" background color to help distinguish it from a normal tooltip. To cause the exclusion reason tooltip to disappear, simply release the button.

23.3. Displaying a New Assertion Instance

If the Verbose Assertion Coverage window is currently displayed, the user may select a new assertion in the file viewer of the Main window. When a new assertion is selected, its information immediately replaces the currently selected assertion. This feature allows many different assertions to be viewed one after the other without having to create/destroy a new window for each.

The user may also see the previous or next uncovered assertion in the main viewer by clicking either the left arrow button (for previous signal viewing) or the right arrow button (for next signal viewing). Note that the left arrow button will be disabled if there is not a signal previous to the current signal in the given module and the right arrow button will be disabled if there is not a signal after the current signal in the given module.

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Chapter 22. Navigating the FSM State/State Transition Coverage Window Home Chapter 24. Navigating the Assertion Source Code Window
covered-0.7.10/doc/html/chapter.gui.assert.source.html0000644000076500007650000001143211426534466022665 0ustar trevorwtrevorwChapter 24. Navigating the Assertion Source Code Window
Chapter 24. Navigating the Assertion Source Code Window
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Chapter 24. Navigating the Assertion Source Code Window

Table of Contents

24.1. Navigating the Source Code

The Assertion Source Viewer window allows the user to see the source code for the current assertion in the verbose assertion window. To view this window, simply click the Show Code button in the Verbose Assertion Coverage window. Figure 24.1, “Assertion Source Viewer Window” shows a zero_one_hot OVL assertion code with syntax highlighting applied.

Figure 24.1. Assertion Source Viewer Window

Assertion Source Viewer Window


24.1. Navigating the Source Code

The source code for the current assertion will be automatically displayed in the text viewer when the window is created. However, the source code will be displayed as it is found in the file system, without preprocessing applied to it. This means that included files will not be displayed in an in-lined fashion. To view included files, simply click on the included filename (it will be underlined). This will cause the included file to replace its includer in the text viewer. An infinite number of includes may be traversed in this manner. To go back to the file that included the current file, simply click on the Back button located in the bottom left-hand corner of the window. This will cause the current source code to be replaced with its "parent" source code.

Note that the Back button will be disabled when the top-level assertion file is currently displayed.

To exit this window, simply click on Close button. To see this help page for the assertion source code window, click on the help (?) button.

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Chapter 23. Navigating the Assertion Coverage Window Home Chapter 25. Creating a New CDD
covered-0.7.10/doc/html/chapter.gui.exclude.html0000644000076500007650000001334411426534466021522 0ustar trevorwtrevorwChapter 29. The Exclusion Reason Popup Window
Chapter 29. The Exclusion Reason Popup Window
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Chapter 29. The Exclusion Reason Popup Window

When an uncovered coverage point needs to be excluded for various reasons, a user-supplied message may be associated with the exclusion, specifying the reason for the exclusion. This information can be useful documentation for a coverage analysis and is possible to achieve using the Covered GUI. This task is accomplished with the exclusion reason popup window which is automatically popped up when a coverage point is marked for exclusion (assuming that the capability is enabled in the exclusion preferences pane). Figure 29.1, “The Exclusion Reason Popup Window” shows what this popup window looks like.

Figure 29.1. The Exclusion Reason Popup Window

The Exclusion Reason Popup Window


To specify an exclusion reason, you may do either enter the exclusion reason into the textbox located on the left side of this window or you may select a pre-created, general purpose exclusion reason in the drop-down table. To view this table, click on the down arrow button at the bottom of this window (see Figure 29.2, “Full View of the Exclusion Reason Popup Window”). To hide this table, click on the same button (which will be changed to an up arrow button). If a general-purpose exclusion reason is selected from the table, it will be displayed in the top textbox where it may be optionally edited for the current coverage point.

Figure 29.2. Full View of the Exclusion Reason Popup Window

Full View of the Exclusion Reason Popup Window


Once the exclusion reason has been entered as desired in the textbox (please note that any formatting characters such as newlines, tabs and/or multiple spaces will be automatically removed and replaced with a single space character), simply click on the OK button which will associate the exclusion reason with the excluded coverage point and close the popup window. Note that the OK button will only be enabled if at least one character is entered in the textbox.

[Note]Note
Editing a general purpose reason in the popup window only has an effect for this coverage point; it does not change the general purpose reason value itself (this can only be done in the preferences window).

To not specify an exclusion reason with an excluded coverage point, simply click on the Cancel button.

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Chapter 28. Navigating the Preferences Window Home Chapter 30. Navigating the Wizard Window
covered-0.7.10/doc/html/chapter.gui.fsm.html0000644000076500007650000003027711426534466020662 0ustar trevorwtrevorwChapter 22. Navigating the FSM State/State Transition Coverage Window
Chapter 22. Navigating the FSM State/State Transition Coverage Window
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Chapter 22. Navigating the FSM State/State Transition Coverage Window

Table of Contents

22.1. Navigating the FSM Window
22.2. Excluding/Including a State Transition
22.3. Displaying a New FSM

The Verbose FSM State/State Transition Coverage window allows the user to see which states and state transitions of a currently selected FSM have been covered or are uncovered. To view this window, simply select the "FSM" coverage metric mode in the coverage bar in the main window and select an underlined FSM state variable in the file viewer. This will cause the FSM Coverage window to be displayed with the currently selected FSM information loaded. Figure 22.1, “Verbose FSM Coverage Window” below shows an example of this window.

Figure 22.1. Verbose FSM Coverage Window

Verbose FSM Coverage Window


22.1. Navigating the FSM Window

The Verbose FSM window is split into two main frames. The top frame contains the expressions that make up the input and output states of the selected FSM. The bottom frame contains a two-dimensional table showing the covered and/or uncovered states and state transitions.

The state/state transition table is a two-dimensional table with all possible values of the input states in the left-most column, the output states in the upper-most row, and the state transitions in the rest of the table.

To determine which states have been uncovered in the table, simply find all state values in the input column or output row (both show the same information) which are highlighted with the "Uncovered" color selection specified in the preferences window. To determine which states have been covered in the table, simply find all state values in the input column or output row which are highlighted with the "Covered" color selection. All other state values which are not highlighted are either impossible values (if all of the state transitions were specified in the Verilog file) or are unknown for coverage (if not all of the state transitions were specified in the Verilog file).

To determine which state transitions have been uncovered in the table, simply find all empty boxes in the table that are highlighted with the "Uncovered" background color. If one of these exist, it specifies that the transition of "input state" (the value specified in the left-most column in the same row) to "output state" (the value specified in the upper-most row in the same column) did not occur. In the example above, we can see that the following state transitions did not occur:

  • 2 -> 4

  • 4 -> 1

Follow the same procedure for finding all covered state transitions in the table except that these boxes will be highlighted with the "Covered" background color. In the example above, we can see that the following state transitions occurred:

  • 1 -> 2

  • 1 -> 1 (loopback case)

  • 2 -> 2 (loopback case)

All other state transition boxes that are not highlighted are either impossible state transitions (if all state transitions were specified in the Verilog source code) or are unknown in their coverage (either not hit or impossible transition if all state transitions were not specified in the Verilog source code).

To exit this window, simply click on Close button. To see this help page for the FSM window, click on the help (?) button.

22.2. Excluding/Including a State Transition

Uncovered state transitions can be excluded/included for FSM coverage consideration. This is done by clicking on the "I" (state transition is currently included in coverage results) or "E" (state transition is currently excluded from coverage results) character in the middle of a state transition square. Changing a state transition from an "I" to an "E" will automatically cause a exclusion reason popup window to be displayed, allowing you to specify the reason for excluding this state transition. After a reason has been entered, the state transition summary coverage information in the listbox to be updated and the background color of the state transition box will change from the uncovered color to the covered color. Changing a state transition from an "E" to an "I" will automatically cause the state transition summary coverage information in the Main Window Summary Bar to be updated and the background color of the state transition box will change from the covered color to the uncovered color. Figure 22.2, “Example of excluded state transitions” below shows an example of the Figure 22.1, “Verbose FSM Coverage Window” state machine coverage information with a couple of state transitions excluded from coverage.

Figure 22.2. Example of excluded state transitions

Example of excluded state transitions


If all of the state transitions for a state machine have been excluded for coverage consideration, the output state variable in the file viewer will change its background from the uncovered to the covered background color. However, the underline will remain under the variable to allow the user to still examine the verbose FSM information for that state machine.

If the user excludes any state transition in the design, the Save CDD... option in the file menu will be enabled. This allows the user to save the excluded property either back to the CDD file (or to a newly named CDD file). Doing so will allow the user to load the CDD file at a different time and retain the knowledge of which state transitions have been excluded/included for coverage. Additionally, if a saved CDD file with coverage exclusion is merged with another CDD file, the excluded state transition information is preserved for the resulting merged CDD file.

If a state transition has been excluded from coverage and an exclusion reason was specified, you can view the reason for exclusion by moving the cursor over the state transition. This will cause a tooltip-style window to be displayed specifying the state transition and the reason for exclusion. The background color of the tooltip will be the same color as the "covered" background color to help distinguish it from a normal tooltip. To cause the exclusion reason tooltip to disappear, simply move the cursor off of the state transition cell.

22.3. Displaying a New FSM

If the Verbose FSM Coverage window is currently displayed, the user may select a new FSM state variable in the file viewer of the Main window. When a new FSM is selected, its information immediately replaces the currently selected FSM. This feature allows many different FSMs to be viewed one after the other without having to create/destroy a new window for each.

The user may also see the previous or next uncovered FSM in the main viewer by clicking either the left arrow button (for previous signal viewing) or the right arrow button (for next signal viewing). Note that the left arrow button will be disabled if there is not a signal previous to the current signal in the given module and the right arrow button will be disabled if there is not a signal after the current signal in the given module.

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Chapter 21. Navigating the Combinational Logic Window Home Chapter 23. Navigating the Assertion Coverage Window
covered-0.7.10/doc/html/chapter.gui.genreport.html0000644000076500007650000004541111426534466022076 0ustar trevorwtrevorwChapter 26. Creating an ASCII report file
Chapter 26. Creating an ASCII report file
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Chapter 26. Creating an ASCII report file

Table of Contents

26.1. Navigating the Report Generator Selection Page
26.2. Report Generation Options Page
Set ASCII Report Generation Options
Level of Detail
Accumulate By
Coverage Type
Show Metrics
Save Options to File...
Output report to file frame
View the report in the GUI after it is created

Though Covered's graphical coverage analyzer is very useful for examining coverage, there may still be times when a textual report is necessary. For that purpose, the GUI has a menu item for generating an ASCII coverage report, running Covered's "report" command on the currently loaded coverage information.

[Note]Note
The ASCII report generator options are only available if one or more CDD files are currently loaded in the GUI.

When the File -> Generate -> ASCII Report menu option is selected (or the "Cntrl-Shift-R" shortcut is used), the ASCII Report Generator Window is created to allow the user to specify the current report output options and generate the report file. Once the report has been generated, it can be viewed within the GUI itself or it can be viewed with any type of file viewer/editor available.

The following subsections describe the various windows used to create a report file. Note that the report generation wizard uses several "pages" to describe the various options to set for creating a new report file, using Back and Next buttons on each page for navigation. Clicking on the Back button will not cause previously filled in pages to be reverted to their default values but rather will remain populated with the user's data. Similarly, if a page has been filled in with data and the Back button is clicked and then the Next button is clicked, the page contents are retained. The only way to clear out fields is to click the Cancel button at the bottom of each page and startup the report generation wizard again.

Clicking the Cancel button at any time will cause the report generation wizard to immediately exit. Clicking on the ? button at any time will bring up the user documentation for the current page (context sensitive help).

26.1. Navigating the Report Generator Selection Page

Figure 26.1, “Report Generation Option Selection Page” shows the look of this page of the report generation wizard.

Figure 26.1. Report Generation Option Selection Page

Report Generation Option Selection Page


The first page of the report generation window allows the user to select whether all options should be interactively selected within the GUI or if a file should be read in which contains command-line options to the report command to use. If the latter is chosen, the contents of that file are read in and are populated in the GUI, but the report generation wizard will continue in the same fashion as the first option, allowing the user to change, remove or add to the options found in that file.

If the Create report by interactively selecting options entry is currently selected and the user wishes to not use a command-line file to populate the rest of the report generation pages, simply click on the Next button at the bottom of the page to continue. If the Create report by using option file entry is currently selected, the user must either type a valid filename or select one by clicking the Browse... button to the right of the file entry area and select a valid file. Once a valid filename is selected, the Next button will be enabled and the user may then click it to continue to the next page. Note that any filename can be selected (whether it's a valid command file or not). Only valid report command options found in that file are used to populate the wizard entries. No error message will be displayed if the file does not contain this information.

26.2. Report Generation Options Page

This wizard page allows you to setup the options to create the needed report. Figure Figure 26.2, “Report Generation Options Page” shows the contents of this page.

Figure 26.2. Report Generation Options Page

Report Generation Options Page


The options page is split into several different categories of options:

Set ASCII Report Generation Options

  • Limit line width to X characters

    If this option is checked, the number of characters that will be displayed per line when outputting design logic will be limited to the number of characters specified in the entry box. If this option is unchecked, the length of the output design logic will be determined by the way the logic was formatted in the design file.

    This option can be useful for printing purposes where a logic design file contains logic that is formatted to exceed the number of characters than can be printed on a page or viewed on a screen.

  • Suppress modules/instances from output if they contain no coverage information

    If this option is checked, any modules (or instances) that were considered for code coverage but did not contain any coverable code will be excluded from the report. If this option is unchecked, all modules/instances will be reported.

    This option may help make the report files easier to view if there are many modules/instances that do not contain coverage points.

  • Output combinational logic vector operations in bitwise format

    Outputs combinational vector logic expressions in bitwise format instead of treating the vector as a 0 or "not 0" value. This can create quite a bit of extra output when creating verbose reports, but can provide the information for a more thorough analysis for these expression types. This option has the same effect as the -b option to the report command.

Level of Detail

These radiobuttons control the level of detail that is output in the generated report. Only one value can be selected for the three available detail values:

  • Summary

  • Detailed

  • Verbose

See Section 11.3, “Summary Vs. Detailed Vs. Verbose” for information on the difference between these three options.

Accumulate By

These radiobuttons control whether coverage information is accumulated by instance or by module. Only one value can be selected for the two available options. See Section 11.4, “Module Vs. Instance” for information on the difference between these two options.

Coverage Type

These radiobuttons control whether covered or uncovered coverage points are output in the report. Only one value can be selected for the two available options. See Section 11.5, “Covered Vs. Uncovered” for information on the difference between these two options.

Show Metrics

These checkbuttons control which coverage metric information is output in the generated report. You may select any number (or combinations) of these options. All of the metrics available for viewing in the GUI can be output to a report file, including:

  • Line

  • Toggle

  • Memory

  • Combinational Logic

  • FSM

  • Assertion

  • Race Conditions

    This item, though it is not a coverage metric, can be useful for understanding what logic was not considered for coverage due to violating the static race condition checks and what check was violated for each block.

Save Options to File...

Once the above options have been specified, it can be useful to save those parameters to a file which can be loaded at a later time in the Section 26.1, “Navigating the Report Generator Selection Page” page of the GUI report generation wizard. This same file can also be fed "as is" into the Covered's command-line report command via the -f option. Click on this button to open a "Save As" window where you can create a filename to save this information into. Click on the Save button of this window to exit the window and save the information. Click on the Cancel button to abort this action.

Output report to file frame

This frame of the ASCII Report window allows the user to specify a filename/location for the generated output file. By default, the report name is the same as the first CDD file loaded, substituting the .cdd extension for a .rpt extension. By default, the directory location to store the generated report is the same directory that the first CDD file exists in. To change this name/location, the user may either enter a value in the entry field or click on the Browse... button to display a "Save As" type window.

View the report in the GUI after it is created

Selecting this option will cause a window to open after the report has been generated which will contain the contents of the generated report in a read-only view. You can search in this window and scroll to help view the entire document.

Once you have completed setting everything up as you need, click on the Create button to generate the report file. If everything worked, the report generation window will close and, if enabled via the the section called “View the report in the GUI after it is created” selector, a file viewer window will be displayed with the contents of the newly generated report file. Click on the "X" button in the window manager to close this window when you have finished with it.

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Chapter 25. Creating a New CDD Home Chapter 27. Creating a CDD Ranking Report
covered-0.7.10/doc/html/chapter.gui.intro.html0000644000076500007650000001051311426534466021217 0ustar trevorwtrevorwChapter 16. Introduction to the GUI
Chapter 16. Introduction to the GUI
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Chapter 16. Introduction to the GUI

The Covered report viewer GUI allows a user to view the coverage results from one or more CDD (Covered Design Database) files that have been previously generated using the Covered score and/or merge commands. The advantages of using the GUI versus using an ASCII file to view coverage results are the following:

  1. View code that is covered/uncovered within the actual source file text (more context)

  2. Quickly see which modules/instances were uncovered for each coverage metric.

  3. Ability to hide/unhide verbose information for uncovered code.

  4. Quickly find expressions that caused combinational logic cases to be uncovered.

  5. Allows user to focus on a particular expression/signal/module/instance that is uncovered.

  6. Non-useful coverage cases can be interactively excluded/included and summary information automatically recalculated.

Because the nature of a GUI interface is much more interactive than a generated text file report, the Covered report viewer is meant to provide the user a more in-depth look at the logic to identify the reasons for not achieving full coverage. This is the ultimate goal of the GUI interface -- to be an interactive tool for identifying and understanding why full code coverage was not achieved and how to write tests that will cover those areas.

The GUI report viewer is invoked by specifying the -view option to the Covered report command. The report viewer is part of the report command and is, therefore, not used to parse/score a design. However, merging maytake place with the GUI as multiple CDD files may be read, merged (assuming all of the CDD files came from the same DUT) and saved in CDD file format.

The rest of the user manual pages describe the various widgets and windows of the GUI and their functionality. Additionally, this user manual contains information on how to get the most out of the Covered GUI report viewer.

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Part IV. Graphical User Interface Home Chapter 17. Navigating the Main Window
covered-0.7.10/doc/html/chapter.gui.line.html0000644000076500007650000003135311426534466021020 0ustar trevorwtrevorwChapter 18. Navigating the Line Coverage Window
Chapter 18. Navigating the Line Coverage Window
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Chapter 18. Navigating the Line Coverage Window

Table of Contents

18.1. Viewing Uncovered Lines
18.2. Excluding/Included Uncovered Lines from Line Coverage
18.3. Viewing Covered Lines

Line coverage is the quickest way to determine what logic in your design is being exercised and which logic has not be exercised during simulation. If a line was found to not be simulated, this is an indication that there was some event that did not occur or did not occur at the proper time to cause a previous conditional expression to be evaluated to true or false. For example, if a block of code looked something like:

Example 18.1. Line Coverage Example

  always @(posedge clock)  // Line 1
    if( a )                // Line 2
      b <= 1'b0;           // Line 3
    else                   // Line 4
      b <= 1'b1;           // Line 5


If line 3 was shown to be not covered, this would indicate that at the positive edge of the term "clock", the value of "a" never evaluated to a value of 1 (true). To make line 3 become covered, we would need to setup a situation in the diagnostic that caused "a" to become true at the positive edge of the term "clock".

On the other hand, if all lines 2 - 5 were found to be uncovered, this would indicate the the term "clock" never made a transition from some value to a 1 (true) value during simulation.

18.1. Viewing Uncovered Lines

To view line coverage for all uncovered lines for a specific module/instance, do the following:

  1. Make sure that the Show Uncovered menu item in the report menu is selected.

  2. Select the line coverage metric in the coverage bar by left-clicking on selection button to the left of "Line".

  3. Select one of the modules/instances that is highlighted in the uncovered color scheme (to change this color scheme, see Chapter 28, Navigating the Preferences Window) in the listbox. This will cause the selected module/instance source code to be displayed in the file viewer.

Once the selected module/instance has been displayed, scroll down in the Coverage File Viewer window (using the scroll bars to the right and below the Coverage File Viewer window) until you have reached a line that is highlighted in the uncovered color scheme. The line number of the highlighted line will be printed to the left of the source code line. This line represents a line that was found to not be hit during the simulation of this module/instance.

18.2. Excluding/Included Uncovered Lines from Line Coverage

Any uncovered line in the design may be included/excluded from coverage consideration. To the left of each uncovered line is an underlined "I" (line is currently included in coverage) or "E" (line is currently excluded in coverage). Clicking on an "I" will cause a exclusion reason popup window to be displayed, allowing you to specify a reason for excluding this line. Once a reason has been entered, the coverage exclusion property of the line will change to an "E" and be highlighted in the "covered" color scheme and the summary line coverage information will be recalculated and redisplayed in the listbox to reflect the current status of line coverage for the current module/instance. Clicking on an "E" will cause the current line to be displayed in the "uncovered" color scheme, the "E" will change to an "I", and the summary line coverage will be recalculated and redisplayed in the summary listbox. Figure 18.1, “Example of uncovered line included for line coverage consideration” shows an uncovered line that is included for coverage consideration. Figure 18.2, “Example of uncovered line excluded for line coverage consideration” shows the same line which is now excluded from coverage consideration.

Figure 18.1. Example of uncovered line included for line coverage consideration

Example of uncovered line included for line coverage consideration


Figure 18.2. Example of uncovered line excluded for line coverage consideration

Example of uncovered line excluded for line coverage consideration


In addition to changing the line coverage information, the combinational logic coverage information for an uncovered statement on that line will also be implicitly excluded from coverage (though the exclude properties for each subexpression of the statement will not change).

If the user excludes any line in the design, the Save CDD... option in the file menu will be enabled. This allows the user to save the excluded property either back to the CDD file (or to a newly named CDD file). Doing so will allow the user to load the CDD file at a different time and retain the knowledge of which lines have been excluded/included for coverage. Additionally, if a saved CDD file with coverage exclusion is merged with another CDD file, the excluded line information is preserved for the resulting merged CDD file.

If a line has been excluded from coverage and an exclusion reason was specified, you can view the reason for exclusion by right-click-and-hold on the "E" on the desired line. This will cause a tooltip-style window to be displayed specifying the reason for exclusion. The background color of the tooltip will be the same color as the "covered" background color to help distinguish it from a normal tooltip. To cause the exclusion reason tooltip to disappear, simply release the button.

18.3. Viewing Covered Lines

To view line coverage for all covered lines for a specific module/instance, do the following:

  1. Make sure that the Show Covered menu item in the report menu is selected.

  2. Select the line coverage metric in the coverage bar by left-clicking on the selection button to the left of "Line".

  3. Select one of the modules/instances in the listbox that shows that at least one line was considered coverable by Covered.

Once the selected module/instance has been displayed, scroll down in the Coverage File Viewer window (using the scroll bars to the right and below the Coverage File Viewer window) until you have reached a line that is highlighted in the covered color scheme. The line number of the highlighted line will be printed to the left of the source code line. This line represents a line that was found to be hit during the simulation of this module/instance.

[Note]Note

You may see both the covered and uncovered line coverage simultaneously by selecting both the Show Uncovered and Show Covered items in the Report menu. This is sometimes useful to see what logic Covered was not able to provide coverage support for (all lines which contain code that are not highlighted in either the uncovered or covered color schemes).

Prev Up Next
Chapter 17. Navigating the Main Window Home Chapter 19. Navigating the Toggle Coverage Window
covered-0.7.10/doc/html/chapter.gui.logic.html0000644000076500007650000006446311426534466021176 0ustar trevorwtrevorwChapter 21. Navigating the Combinational Logic Window
Chapter 21. Navigating the Combinational Logic Window
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Chapter 21. Navigating the Combinational Logic Window

Table of Contents

21.1. Navigating a Statement
21.2. Understanding the Coverage Information
Event Subexpression
Unary Subexpression
Simple Combinational Subexpression
Complex Combinational Subexpression
21.3. Excluding/Including a Subexpression
21.4. Displaying a New Statement

The Verbose Combinational Logic viewer allows the user to look at the subexpressions of a selected statement to determine exactly why a statement did not achieve 100% coverage. The window is split up into two text frames. The top frame displays the selected statement, underlining and numbering subexpressions that were found to not achieve full coverage. The bottom frame displays which combinations of a selected subexpression were hit/missed, allowing the user to discern which combinations of logic are still in need of verification. Figure 1 shows the verbose combination logic window.

Figure 21.1. Example of the verbose combinational logic window

Example of the verbose combinational logic window


21.1. Navigating a Statement

To understand what subexpressions of a statement caused it to not achieve 100% coverage, the viewer window allows the user to traverse uncovered subexpressions, displaying the coverage information for each subexpression in the lower frame. To see an uncovered subexpression in the lower frame, simply click the left mouse on the underlined subexpression. If the subexpression has one or more children subexpressions, these will be individually underlined and numbered. If the subexpression is a leaf subexpression of the statement, only its coverage information will be displayed in the lower pane. To traverse upward in a subexpression, simply click the right mouse button on the underlined subexpression. This will cause the parent subexpression to be underlined and its parent (if one exists) will have its coverage information displayed in the lower frame.

To exit this window, simply click on Close button. To see this help page for the combinational logic window, click on the help (?) button.

21.2. Understanding the Coverage Information

The coverage information for a selected subexpression can be one of four different types:

Event Subexpression

These subexpressions do not have any children expressions. Their coverage is in terms of:

  • Did this event occur?

The following operators are considered events:

  • At-event operators:

      @(posedge expression)
  @(negedge expression)
  @(expression)
  @*

  • Event trigger operator:

      -> event_variable

Figure 21.2. Example Coverage Output for an Uncovered Event Subexpression

Example Coverage Output for an Uncovered Event Subexpression


In this diagram, we see that a certain @(posedge clock) expression never occured.

Unary Subexpression

These subexpressions do not have any children expressions. Their coverage is in terms of:

  • Did this expression evaluate to a value of 0?

  • Did this expression evaluate to a non-zero value?

The following operators are considered unary subexpressions:

  • Signal/Bit Selectors:

      signal_value
  signal_value[expression]
  signal_value[value:value]
  signal_value[expression+:value]
  signal_value[expression-:value]

  • Function call:

      function_name( ... )

  • Relational operators:

      !expression
  expression  <    expression
  expression  >    expression
  expression  <=   expression
  expression  >=   expression
  expression  ==   expression
  expression  !=   expression
  expression  ===  expression
  expression  !==  expression

  • Shift operators:

      expression <<  value
  expression >>  value
  expression <<< value
  expression >>> value

  • Conditional operator:

      expression ? expression : expression

  • Unary operators:

      expression
  &expression
  |expression
  ^expression
  ~&expression
  ~|expression
  ~^expression

  • Concatenation operators:

      {value{expression} }
  {expression, expression, ... }

  • Case equality

Figure 21.3. Example Coverage Output for an Uncovered Unary Subexpression

Example Coverage Output for an Uncovered Unary Subexpression


Simple Combinational Subexpression

These subexpressions have two child expressions (L=left and R=right). There are three flavors of simple combinational subexpressions: AND-type, OR-type and other. The differences are explained below.

Simple AND-type Combinational Subexpressions

These subexpressions have three possible combinational outcomes:

  • Did the left expression evaluate to 0?

  • Did the right expression evaluate to 0?

  • Did the left expression evaluate to 1 when the right expression evaluated to 1?

The following operators are considered simple AND-like combinational subexpressions:

  • Logical operators:

      expression  &   expression
  expression  ~&  expression
  expression  &&  expression

Figure 21.4. Example Coverage Output for an Uncovered Simple AND-type Combinational Subexpression

Example Coverage Output for an Uncovered Simple AND-type Combinational Subexpression


Simple OR-type Combinational Subexpressions

These subexpressions have three possible combinational outcomes:

  • Did the left expression evaluate to 1?

    Did the right expression evaluate to 1?

    Did the left expression evaluate to 0 when the right expression evaluated to 0?

The following operators are considered simple OR-like combinational subexpressions:

  • Logical operators

  •   expression  |   expression
  expression  ~|  expression
  expression  ||  expression

Figure 21.5. Example Coverage Output for an Uncovered Simple OR-type Combinational Subexpression

Example Coverage Output for an Uncovered Simple OR-type Combinational Subexpression


Simple Other-type Combinational Subexpressions

These subexpressions have four possible combinational outcomes:

  • Did the left expression evaluate to 0 when the right expression evaluated to 0?

  • Did the left expression evaluate to 0 when the right expression evaluated to 1?

  • Did the left expression evaluate to 1 when the right expression evaluated to 0?

  • Did the left expression evaluate to 1 when the right expression evaluated to 1?

The following operators are considered simple combinational subexpressions:

  • Mathematical operators:

      expression + expression
  expression - expression

  • Logical operators:

      expression ^  expression
  expression ~^ expression

Figure 21.6. Example Coverage Output for an Uncovered Simple Combinational Subexpression

Example Coverage Output for an Uncovered Simple Combinational Subexpression


Complex Combinational Subexpression

These subexpression have three or more child expressions that all are connected by the same operator. For example, the statement a = (b & c & d) would contain the complex combinational subexpression of (b & c & d) where b, c and d are the three child expressions all combined using the bitwise AND operator.

The effect of each subexpression on the value of the entire subexpression as well as the combination of each child toward the parent is displayed. For example, if the combinational operator is a bitwise OR, each child is checked to see if it evaluated to TRUE (in an OR operation, only one subexpression needs to evaluate to TRUE for the entire subexpression to be TRUE). Additionally, all child subexpressions are checked to see if all evaluated to 0 simultaneously (this is the only way to get the whole subexpression to evaluate to 0).

The unique identifier below each subexpression is used in the displayed coverage information for these types of subexpressions for identifying which subexpression did not behave correctly.

All simple combinational subexpressions can be output as complex combinational subexpressions if there are three or more child subexpressions to the operation.

Figure 21.7. Example Coverage Output for an Uncovered Complex Combinational Subexpression

Example Coverage Output for an Uncovered Complex Combinational Subexpression


In this example, subexpression 1 never evaluated to a value of TRUE (which would have made the entire expression TRUE) and all three subexpressions 1, 2, and 3 were never a value of 0 simultaneously (which would have made the entire expression FALSE). However, subexpressions 2 and 3 both evaluated to TRUE at some point.

21.3. Excluding/Including a Subexpression

For any displayed subexpression within a statement, the user may choose to disregard the coverage information for that subexpression by clicking on the Excluded checkbutton on the right side of the window. If this option is checked, Covered will display a exclusion reason popup window to allow the user to specify a reason for excluding the subexpression. Once a reason has been entered, the combinational logic summary coverage information will be recalculated for the current module/instance by adding to the "Exclude" count the number of uncovered combinational logic values for the given subexpression (and all subexpressions below this expression within the expression tree). This new summary information will be redisplayed on the listbox. The subexpression background color in the top frame will also change from the uncovered background color to the covered background color. However, the subexpression will still contain an underline that may be clicked on at any time to view its coverage information or the coverage information for any subexpressions that are uncovered. To include a previously excluded subexpression, simply uncheck the Excluded checkbutton. This will automatically cause the summary information and background color to be updated for the given subexpression. Figure 21.8, “Example of an excluded subexpression” below shows an example of a subexpression that has been excluded from coverage consideration.

Figure 21.8. Example of an excluded subexpression

Example of an excluded subexpression


If an expression tree has been entirely excluded from coverage (all subexpressions have the Excluded checkbutton checked), the background color in the file viewer will change from an uncovered background color to the covered background color to indicate at the top-level that this entire statement has been excluded from coverage. However, the statement will still be underlined in the Main Coverage File Viewer to allow the user to view the statement, if necessary.

If the user excludes any subexpression in the design, the Save CDD... option in the file menu will be enabled. This allows the user to save the excluded property either back to the CDD file (or to a newly named CDD file). Doing so will allow the user to load the CDD file at a different time and retain the knowledge of which subexpressions have been excluded/included for coverage. Additionally, if a saved CDD file with coverage exclusion is merged with another CDD file, the excluded subexpression information is preserved for the resulting merged CDD file.

If a subexpression has been excluded from coverage and an exclusion reason was specified, you can view the reason for exclusion by selecting the subexpression in the top window (so that it is displayed in the lower window and right-click-and-holding on the Excluded checkbutton. This will cause a tooltip-style window to be displayed specifying the reason for exclusion. The background color of the tooltip will be the same color as the "covered" background color to help distinguish it from a normal tooltip. To cause the exclusion reason tooltip to disappear, simply release the button.

21.4. Displaying a New Statement

If the Verbose Combinational Logic Coverage window is currently displayed with a statement, the user may select a new statement in the file viewer of the Mainwindow. When a new statement is selected, its value immediately replaces the currently selected statement. This feature allows many different statements to be viewed one after the other without having to create/destroy a new window for each.

The user may also see the previous or next uncovered statement in the main viewer by clicking either the left arrow button (for previous signal viewing) or the right arrow button (for next signal viewing). Note that the left arrow button will be disabled if there is not a signal previous to the current signal in the given module and the right arrow button will be disabled if there is not a signal after the current signal in the given module.

Prev Up Next
Chapter 20. Navigating the Memory Coverage Window Home Chapter 22. Navigating the FSM State/State Transition Coverage Window
covered-0.7.10/doc/html/chapter.gui.main.html0000644000076500007650000013445611426534466021025 0ustar trevorwtrevorwChapter 17. Navigating the Main Window
Chapter 17. Navigating the Main Window
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Chapter 17. Navigating the Main Window

Table of Contents

17.1. The Main Menu Bar
The File Menu
The Report Menu
The View Menu
The Help Menu
17.2. The Coverage Type View Bar
17.3. The Module/Instance Listbox
17.4. The Coverage File Viewer
Searching for an Uncovered Line in the Coverage Viewer
Searching for a String in the Coverage Viewer
17.5. The Information Bar

Figure 17.1, “Covered Main Window” shows the main window prior to a CDD file being loaded. There are five main components of the main window. These components are the following (from top to bottom, left to right):

  1. The menu bar

  2. The coverage type bar

  3. The module/instance summary listbox

  4. The coverage file viewer

  5. The information bar

Figure 17.1. Covered Main Window

Covered Main Window


17.1. The Main Menu Bar

The Main Menu Bar consists of four menus at the top of the main window. Figure 17.2, “Covered Main Window Highlighting the Menu Bar” below shows the menu bar portion of the GUI bordered in red. These menus are the following:

  1. File - Creates, opens, merges, saves and closes CDD files, generates reports, and exits the application.

  2. Report - Specifies what type of report to show.

  3. View - Provides additional viewing options.

  4. Help - Provides access to online help manual and tool information.

Figure 17.2. Covered Main Window Highlighting the Menu Bar

Covered Main Window Highlighting the Menu Bar


[Note]Note

On Mac OS X, the main menubar does not exist in the application window. Like most Mac OS X applications, the main menubar exists at the top of the display.

The File Menu

The file menu is used to open a new CDD file, merge a related CDD file (derived from the same design as the currently opened CDD file, save the currently opened CDD file(s), close all opened CDD files, generate different types of output and view the names of all currently opened CDD files. Additionally, the user selects this menu bar to exit the Covered report viewer GUI. Figure 17.3, “The File Menu” shows the file menu contents within the main window.

Figure 17.3. The File Menu

The File Menu


Open/Merge CDDs...

This menu option is used to either open a new CDD file or merge a related CDD file into the currently opened CDD file(s). This action needs to be performed before any coverage viewing can take place. When this option is selected, a standard file window is displayed allowing the user to select one (or possibly more depending on your version of Tcl/Tk) CDD file to open or merge. To select more than one CDD file with one call to this option, simply press and hold the Control key while selecting files with the left mouse button. If your version of Tcl/Tk supports this feature, you will see multiple files highlighted for selection; otherwise, only the last selected file will be selected. If no CDD files currently are opened, any CDD file may be opened. If one or more CDD files have been opened/merged, only CDD files generated from the same design may be merged.

Note that this option has an accelerator keystroke <Control-O>. Hitting this keystroke combination will also open new CDD file(s).

View Loaded CDD(s)...

This menu option is only available after an initial CDD file has been opened using the Open/Merge CDDs... file menu option. When this menu option is selected, a new window displaying all currently opened CDD files is displayed (see Figure 17.4, “The CDD Opened File Viewer” below). If another CDD file is merged and this window is currently displayed, it is automatically updated with the newly added file. If the Close CDDs... file menu option is selected while this window is opened, all filenames will be automatically removed to indicate this. The View Loaded CDD(s)... menu option is useful for helping the user see exactly which files have been merged or not merged in the current viewer. Simply click on the Close button in the Loaded CDD file viewer window to close the window.

Figure 17.4. The CDD Opened File Viewer

The CDD Opened File Viewer


Save CDD...

This menu option is only available after one or more CDD files have been opened/merged. It is used to save the opened or merged CDD files as a single, merged CDD file than can be viewed as a separate CDD file or can be merged with other CDD files. It is also used to save any changes that the user has made to exclude/include coverage cases within the GUI. If you would like to retain this information, please save the CDD file. By default, the name of the first loaded CDD file is placed in the "Save As" window when this option is selected. The user may choose to replace the old CDD file with the new one, or the user may save it under a different name. Once a CDD file has been saved, this option is deselected until either a new CDD file is merged or the user changes the exclude/include property of any coverage case within the GUI.

Note that this option has an accelerator keystroke <Control-s>. Hitting this keystroke combination will also save the current CDD.

Close CDDs

This menu option is used to close all opened/merged CDD files so that the user may view a different CDD file without needing to exit and re-enter the GUI. The user may open and close as many times as needed without needing to reinvoke the GUI. When CDD files are closed, any opened coverage windows are automatically closed and all necessary GUI components are restored to their original state as when the GUI is first invoked. If the currently opened CDD file(s) have not been saved, a window (shown in Figure 17.5, “The Close Warning Window” below) is displayed to ask the user if they would like to save prior to closing. To save the CDD file, simply click "Yes" and a "Save As" window will prompt you for a location/name to save it as. To close the CDD file without saving, simply click "No". To cancel the close operation, simply click Cancel. To view another CDD file after closing all CDD files, simply select the Open/Merge CDDs... file menu option.

Note that this option has an accelerator keystroke <Control-w>. Hitting this keystroke combination will also close all opened CDD files.

Figure 17.5. The Close Warning Window

The Close Warning Window


Generate

This option, when selected, displays a submenu of items that can be generated by the GUI. The following options (with descriptions) are available (see Figure 17.6, “The Generate Menu List”).

Figure 17.6. The Generate Menu List

The Generate Menu List


  • New CDD...

    Selecting this submenu option will cause Covered to allow for the creation of a new CDD file (note: this can be accomplished on the command-line with the "score" command). When this option is selected, the new CDD creation wizard window is created. See Chapter 25, Creating a New CDD for more information on the navigation of this window.

    Note that this option has an accelerator keystroke <Control-n>. Hitting this keystroke combination will also cause the new CDD creation window to be displayed.

  • ASCII Report...

    Selecting this submenu option will cause Covered to generate an ASCII version of the coverage report to a specified file (note: this can also be accomplished with the "report" command of Covered's command-line interface). When this option is selected, the ASCII report generation wizard window is created. See Chapter 26, Creating an ASCII report file for more information on the navigation of this window.

    Note that this option has an accelerator keystroke <Control-r>. Hitting this keystroke combination will also cause the ASCII report generator window to be displayed.

  • CDD Ranking Report...

    Selecting this submenu option will cause Covered to generate a CDD ranking report to a specified file (note: this can also be accomplished on the command-line with the "rank" command). When this option is selected, the CDD ranking wizard window is created. See Chapter 27, Creating a CDD Ranking Report for more information on the navigation of this window.

    Note that this option has an accelerator keystroke <Control-c>. Hitting this keystroke combination will also cause the CDD ranking window to be displayed.

Exit

This menu option will exit the entire GUI application, closing all opened windows created by this application. Use this option to exit the application. If the currently opened CDD file(s) have not been saved, a window (shown in Figure 17.7, “The Exit Warning Window” below) is displayed to ask the user if they would like to save prior to exiting. To save the CDD file, simply click Yes and a "Save As" window will prompt you for a location/name to save it as. To close the CDD file without saving, simply click No. To cancel the close operation, simply click Cancel.

Note that this option has an accelerator keystroke <Control-x> (or <Command-Q> on Mac OS X). Hitting this keystroke combination will also close the entire application.

Figure 17.7. The Exit Warning Window

The Exit Warning Window


The Report Menu

The report menu allows the user to display the currently opened CDD file contents in a number of different ways for analyzing. The options specified in this menu closely imitate the options in the "report" command. The type of report can be changed at any point in time while a CDD is loaded. When a report menu option is selected, Covered will automatically convert all information in the GUI to represent this report type. Figure 17.8, “The Report Menu” below shows the contents of the report menu. Each menu item is described below the figure.

Figure 17.8. The Report Menu

The Report Menu


Module-Based

When the diamond to the left of this option is selected, the generated report information will be in module-based representation. A module-based report gathers all of the module instances that instantiate the same module and merges their results based on the module name. This is useful for understanding what logic in a module has been tested or untested without care to individual instance contribution. Selecting this report type (the default) will cause the Instance-based menu option to be automatically deselected (the two report types are mutually exclusive).

Instance-Based

When the diamond to the left of this option is selected, the generated report information will be in instance-based representation. An instance-based report shows the coverage information for each module instance within the design. This allows the user to discern what logic is being covered in individual instances. Selecting this report type will cause the Module-based menu option to be automatically deselected (the two report types are mutually exclusive).

Line, Toggle, Memory, Logic, FSM, Assert

These menu options are directly tied to the coverage metric select menubutton in the coverage bar (see Section 17.2, “The Coverage Type View Bar”). Changing the value in the menubutton will change the selection of this menu item and vice versa. Only one of these menu items will be selected at a given time.

Show Uncovered

When the square to the left of this option is selected (the default), all uncovered lines, toggles, logic, and FSM states/arcs within the file viewer window will be highlighted for the user to quickly see what code was monitored by Covered but determined to not be fully covered. This option may be selected along with the Show Covered menu option to see both covered and uncovered logic within the same file.

Show Covered

When the square to the left of this option is selected, all covered lines, toggles, logic, and FSM states/arcs within the file viewer window will be highlighted for the user to quickly see what code was monitored by Covered and determined to be fully covered. This option is useful for the user of Covered to understand what logic was monitored during simulation. This option may be selected along with the Show Uncovered menu option to see both covered and uncovered logic within the same file.

Show Race Conditions

When the square to the left of this option is selected, all logic lines that were found to contain a potential race condition and was, therefore, eliminated from coverage consideration by Covered will be highlighted by the colors as selected in the preference menu. This option is useful for the user of Covered to understand what logic was not considered for coverage information due to a detected potential race condition situation. Please see Chapter 4, Race Condition Checking for more information on what Covered looks for in logic to consider it to be a possible race condition.

The View Menu

The View menu allows the user to select or change the current way the information in Covered is viewed. Figure 17.9, “The View Menu” shows the contents of the View menu.

Figure 17.9. The View Menu

The View Menu


Next Uncovered

Causes the line containing the next uncovered metric to be visible in the file viewer. If the next uncovered line is already visible, this menu item will have no visible effect. The search for the next uncovered line starts at (a) the top of the module (when the module is first displayed in the the Coverage Viewer), (b) from the last uncovered line searched for with the Next Uncovered or Previous Uncovered calls, or (c) from the last currently selected line (only valid for toggle and combinational logic views).

This menu item is only enabled when another uncovered line exists after the current uncovered line. It can also be accessed with the accelerator keystroke <Control-n> or the right arrow button in the Main Window.

Previous Uncovered

Causes the line containing the previous uncovered metric to be visible in the file viewer. If the previous uncovered line is already visible, this menu item will have no visible effect. The search for the previous uncovered line starts at (a) the top of the module (when the module is first displayed in the the Coverage Viewer), (b) from the last uncovered line searched for with the Next Uncovered or Previous Uncovered calls, or (c) from the last currently selected line (only valid for toggle and combinational logic views).

This menu item is only enabled when another uncovered line exists before the current uncovered line. It can also be accessed with the accelerator keystroke <Control-p> or the left arrow button in the Main Window.

Show Current Selection

This menu item is only available if the current metric mode is not "Line", the user has clicked on an uncovered segment of code, and the associated toggle, memory, logic, FSM or assertion verbose window exists. The currently selected line is visually identified in the file viewer area on the left-hand side of the line containing the uncovered code. If this line is not currently visible in the Coverage Viewer, selecting this menu item will cause it to be visible.

An accelerator keystroke <Control-c> will also invoke this menu item.

Wizard...

Displays the Covered wizard window which normally opens upon starting the Covered GUI. The Wizard window allows the user to easily create a new CDD file, open/ merge existing CDD files, rank existing CDD files and get user documentation. See Chapter 30, Navigating the Wizard Window for more information.

Preferences...

Causes the preferences window to be created if it currently does not exist or forces it into the foreground if it does exist.

[Note]Note

On Mac OS X, this menu item does not exist in the "Report Menu" but rather in the Covered application menu to remain consistent with the Mac OS X environment.

The Help Menu

The help menu contains all of the user documentation for Covered. Additionally, information regarding the version of Covered used and other contact information for application problems, suggestions, etc. can be found in this menu.

Figure 17.10. The Help Menu

The Help Menu


Manual

Selecting this menu item causes Covered to display the user manual in a web browser.

About Covered

Selecting this menu item causes Covered to bring up a window showing the current release number, developer contact information and credits.

[Note]Note

On Mac OS X, this menu item does not exist in the Help Menu but rather in the application's menu to remain consistent with the Mac OS X environment.

17.2. The Coverage Type View Bar

Figure 17.11, “Covered Main Coverage Type View Bar” shows the location of the coverage type view bar. The bar contains two selection buttons. The selection button on the left side of the bar shows the currently selected coverage metric. There are six main types of coverage metrics that Covered can provide: line, toggle, memory, logic (combinational logic), FSM (state and arc) and assert (assertion coverage). When the Covered GUI is first invoked, the line coverage metric is the default mode. To view a different metric, simply left click, select the desired coverage metric, and left click again. Doing so will automatically set the selection indicator to the new mode and display the new metric information in the Module/Instance listbox and file viewer.

The selection button on the right side of the bar shows the current coverage accumulation mode: module or instance. Module coverage takes all of the similar module instances and merges their coverages. Instance coverage displays each module instance individually. To select a different value than the one displayed, simply left click the selection button, highlight the desired value and left click again. This will repopulate the Module/Instance lisbox and clear the file viewer.

Figure 17.11. Covered Main Coverage Type View Bar

Covered Main Coverage Type View Bar


17.3. The Module/Instance Listbox

After a CDD file has been opened in the GUI, the module/instance selection box (shown in Figure 17.12, “Populated Module/Instance Selection Box” below) will contain either a list of all of the modules within the specified design or a list of all of the instances within the design, based on the type of report selected in the report menu. Left-clicking on a module/instance name within this box will cause that file to be output in the file viewer to the right of the selection box.

In addition to the names of the modules or instances of the design, each line also contains a summary view of the coverage for the currently selected metric for each module or instance. The summary coverage information includes the number of hits, number of misses, total number and hit percentage. Each column in the table can be resized by clicking on the separator bar between the column headers and sliding the column to the left or to the right. Additionally, columns may be hidden or shown in the module/instance selection box by clicking on the button at the right-hand side of the column header bar (and above the vertical scrollbar). When this button is left-clicked, a popup menu will be displayed showing which columns are currently shown (a check to the left of the column name) and which are hidden (no check). To change the display for a particular column, simply click on the column name in the popup window. This will cause the associated column to be hidden or shown and will close the popup window. If the popup window is displayed and the user does not wish to change the display values of any of the shown columns, simply click anywhere on the screen but on the popup window. This will cause the popup window to disappear and no column display values will be changed.

Depending on the selected coverage metric (specified in the coverage bar) and the coverage results for each module/instance, a module/ instance item will be highlighted in the uncovered logic color if the corresponding module/instance was found to have uncovered logic within that module/instance. If the specified module/instance was found to be fully covered for the currently selected metric, it will be highlighted with the selected covered logic color. This can help the user quickly identify modules/instances that contain uncovered logic cases. Note that when a different coverage metric is selected, the highlights will be recalculated for that metric. Additionally, the currently selected module/instance will be displayed in a darker version of the covered/uncovered color.

Figure 17.12. Populated Module/Instance Selection Box

Populated Module/Instance Selection Box


17.4. The Coverage File Viewer

Figure 17.13, “Covered Main Coverage File Viewer” shows the area of the main window where the coverage file viewer window is located.

Figure 17.13. Covered Main Coverage File Viewer

Covered Main Coverage File Viewer


The coverage file viewer shows the currently selected module (indicated in the information bar) Verilog source. The coverage file viewer provides a read-only view of the original source code so all editing of the file must be done in a separate editor. Each source code line in the viewer window is numbered to the left of the line to aid in debugging and finding the lines in an editor.

Depending on the coverage metric currently selected in the coverage bar and the covered/uncovered/race condition selections in the report menu, the lines that are found to be uncovered, covered, and/or considered a race condition are highlighted in their respective color schemes in the coverage file viewer window. Using the scrollbars to the right and below the coverage file viewer, the user can find the missed/hit lines quickly for further analysis.

The coverage file viewer is the place where the user can invoke the toggle, memory,combinational logic, FSM and/or assertion detail windows. To view one of these windows, do the following:

  1. Select either the Toggle, Memory, Logic, FSM or Assert coverage metric selection button in the coverage bar.

  2. Select a module/instance that contains uncovered code in the listbox.

  3. In the coverage file viewer, find code that is highlighted as being uncovered.

  4. Left click on the uncovered piece of logic. Doing so will automatically bring up either the toggle, the memory, the logic, the FSM or the assertion verbose coverage windows.

Additionally, the logical blocks that have been disregarded by Covered due to a potential race condition existing are highlighted. By placing the cursor over one of these logical blocks, the reason for why the logical block was disregarded is output in the information bar.

To view a new module/instance, simply left click on one in the Module/Instance Listbox. The source code for the selected module/instance will be immediately loaded into the coverage file viewer in the currently selected coverage metric.

To view a new coverage metric, simply left click on one of the coverage metrics in the Coverage Type Bar. The currently selected module/instance will be immediately updated in the coverage file viewer, highlighting the uncovered/covered code for the current metric.

Searching for an Uncovered Line in the Coverage Viewer

To find the next or previous line containing uncovered logic for the current metric mode, click the left arrow (Previous) or right arrow (Next) buttons. Doing so will cause the next or previous uncovered line to be visible in the Coverage File Viewer. Clicking these buttons has the same effect as the "Next Uncovered" or "Previous Uncovered" menu items in the view menu.

Searching for a String in the Coverage Viewer

The Coverage Viewer contains a find (magnifying lens) button, an entry field, and a clear (X) button for performing text searches in the Coverage File Viewer. The user may type in any string (wildcards and pattern matching is not supported) in the entry field. Hitting the "return" key or the find button will cause the string search to commence.

If a match to the search value is found, it is made visible in the Coverage File Viewer and highlighted. The user may search on the value again by clicking the find button. To clear the current value in the entry field, click on the clear button. If a match occurs, the specified value in the entry field will remain until either a new value is entered or the clear button is clicked. If a match was not found for the given string, a message window will pop-up specifying that the given string was not found. Clicking the OK button will cause this message window to close and the entry field will automatically be cleared.

17.5. The Information Bar

The information bar at the bottom of each window in the report viewer provides information about the current mode, file, or operation the user should take next. All information is state and context sensitive. If you are in doubt of what to do next, first see the information bar.

Figure 17.14. Covered Main Information Bar

Covered Main Information Bar


Prev Up Next
Chapter 16. Introduction to the GUI Home Chapter 18. Navigating the Line Coverage Window
covered-0.7.10/doc/html/chapter.gui.memory.html0000644000076500007650000003461011426534466021400 0ustar trevorwtrevorwChapter 20. Navigating the Memory Coverage Window
Chapter 20. Navigating the Memory Coverage Window
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Chapter 20. Navigating the Memory Coverage Window

Table of Contents

20.1. Understanding the Layout
Addressable Memory Elements Frame
Element Coverage Frame
Button Frame
20.2. Excluding/Including a Memory for Memory Coverage
20.3. Displaying a New Memory for Memory Coverage

The verbose memory window allows the user to interactively view all of the coverage information for a selected memory, including the following for each addressable memory element:

  1. Have all bits toggled from 0 -> 1 and from 1 -> 0?

  2. Has the entry been written?

  3. Has the entry been read?

To display this window, simply click on a highlighted/underlined uncovered memory in the file viewer. This will cause the verbose memory viewer to be created for the specified memory as well as display a "-->" symbol in the Coverage Viewer on the same line as the selected memory. This symbol is simply meant to help the user identify in the Coverage Viewer which memory is currently displayed in the Memory Viewer window. Figure 1 shows the Memory Viewer loaded with a 4-dimensional memory called "mem" in which two of the dimensions are unpacked (all combinations of unpacked dimensions make up the total number of addressable elements in the memory), creating a total of 18 addressable elements. The first addressable element "[0][0]" is shown in the lower frame in which only a single bit has been toggled from 0 to 1, the element has been written, but it has not been read.

Figure 20.1. Verbose Memory Window

Verbose Memory Window


20.1. Understanding the Layout

The Memory Coverage window is split up into three main frames stacked from top to bottom. These frames, in order from top to bottom, are the "Addressable Memory Elements" frame, the "Element Coverage" frame, and the button frame. Each are described in detail below.

Addressable Memory Elements Frame

The uppermost frame contains all of the addressable memory elements (AMEs) of the memory. An AME is a single memory entry that is addressed by specifying a unique combination of values for each of the unpacked dimensions of the memory. For example, consider the following memory: 

  reg [15:0] foo[0:1][0:3];

This memory called "foo" contains three dimensions. One packed dimension which is a 16-bit little endian value and two unpacked dimensions, containing two entries of four entries (for a total of eight addressable memory elements). Each AME being 16 bits wide. The AMEs for this memory would be:

  • foo[0][0]

  • foo[0][1]

  • foo[0][2]

  • foo[0][3]

  • foo[1][0]

  • foo[1][1]

  • foo[1][2]

  • foo[1][3]

The upper frame will contain all of the AMEs for the selected memory. The uncovered AMEs will be highlighted in the uncovered color scheme (as specified in the preferences window) while all fully covered AMEs will remain unhighlighted. To view the coverage information for any uncovered AME, simply click on it and the information will be viewable in the "Element Coverage" frame below it.

Element Coverage Frame

The Element Coverage frame shows all of the coverage information for the currently selected AME including toggle coverage (which bits of the element toggled from 0->1 and 1->0), write coverage (was this entry written to) and read coverage (was this entry accessed).

The bit vector displayed in the toggle window is a binary bit vector, where each value (0 or 1) represents whether that bit in the signal either toggled (1) or did not toggle (0) during simulation. There are two bit vectors displayed for the AME, the top vector shows the 0->1 toggle information while the bottom vector shows the 1->0 toggle information.

The name of the memory along with its dimensional range information is displayed below the toggle window; however, if the mouse cursor is placed over a specific bit in the toggle box, the packed dimensional range information will be changed to show the displayed bit, making it easy for the user to discern exactly which bit has toggled/not toggled. If the width of the AME exceeds the given space for the toggle window, a scrollbar will be allowed to slide left and right to view the rest of the toggle information.

Below the memory name are two other pieces of coverage information about the AME. The value to the right of the Written: label will be set to either "Yes" or "No". If the value is "Yes", this indicates that the currently selected AME was written during simulation and value will be highlighted with the covered color scheme (as selected in the preferences window). If the value is "No", this indicates that the currently selected AME was not written during simulation and the value will be highlighted with the uncovered color scheme.

To the right of the Written information is the Read label which will also be set to either a value of "Yes" or "No". If the value is "Yes", this indicates that the currently selected AME was accessed during simulation and the value will be highlighted with the covered color scheme. If the value is "No", this indicates that the currently selected AME was not accessed during simulation and the value will be highlighted with the uncovered color scheme.

Button Frame

The button frame contains buttons for closing the Memory Coverage window, displaying this help page, or moving to the next/previous uncovered memory in the same module/instance.

To exit this window, simply click on Close button. To see this help page from the toggle window, click on the Help button.

20.2. Excluding/Including a Memory for Memory Coverage

The user may exclude/include any uncovered memory in the design for memory coverage by simply clicking on the Excluded checkbutton in the upper right-hand portion of the Memory Coverage window. If this checkbutton is checked, the exclusion reason popup window will be displayed automatically, allowing the user to specify a reason for excluding the memory. Once a reason has been entered, the summary coverage information will automatically be recalculated and redisplayed in the listbox and the background color of the underlined memory in the file viewer will change from the uncovered background color to the covered background color. However, the memory will still remain underlined, allowing the user to see the verbose memory coverage information, if necessary. If the Excluded checkbutton is unchecked, the summary coverage information and background colors will be readjusted to include the coverage information for this memory.

If the user excludes any memory for memory coverage in the design, the Save CDD... option in the file menu. This allows the user to save the excluded property either back to the CDD file (or to a newly named CDD file). Doing so will allow the user to load the CDD file at a different time and retain the knowledge of which memories have been excluded/included for memory coverage. Additionally, if a saved CDD file with coverage exclusion is merged with another CDD file, the excluded memory information is preserved for the resulting merged CDD file.

If a memory has been excluded from coverage and an exclusion reason was specified, you can view the reason for exclusion by right-click-and-holding on the Excluded checkbutton. This will cause a tooltip-style window to be displayed specifying the reason for exclusion. The background color of the tooltip will be the same color as the "covered" background color to help distinguish it from a normal tooltip. To cause the exclusion reason tooltip to disappear, simply release the button.

20.3. Displaying a New Memory for Memory Coverage

If the Verbose Memory Coverage window is currently displayed with a memory, the user may select a new memory in the file viewer of the Main window. When a new memory is selected, its value immediately replaces the currently selecting memory value. This feature allows many different memories to be viewed one after the other without having to create/destroy a new window for each memory.

The user may also see the previous or next uncovered memory in the main viewer by clicking either the left arrow button (for previous memory viewing) or the right arrow button (for next memory viewing). Note that the left arrow button will be disabled if there is not a memory previous to the current memory in the given module and the right arrow button will be disabled if there is not a memory after the current memory in the given module.

Prev Up Next
Chapter 19. Navigating the Toggle Coverage Window Home Chapter 21. Navigating the Combinational Logic Window
covered-0.7.10/doc/html/chapter.gui.new.html0000644000076500007650000012404211472127327020653 0ustar trevorwtrevorwChapter 25. Creating a New CDD
Chapter 25. Creating a New CDD
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Chapter 25. Creating a New CDD

Table of Contents

25.1. Navigating the New CDD Creation Option Selection Page
25.2. Navigating the New CDD Creation CDD Name Page
25.3. CDD Creation Type Page
25.4. CDD Creation Options1 Page
General Options
Exclude Options
25.5. CDD Creation Options2 Page
Source File...
Library Directory...
Library Extension(s)...
Include Directory...
Define...
Parameter Override...
FSM...
Module Generation...
Module Exclusion...
Command File...
Other Notes
25.6. CDD Creation Output Pane

Creating a new CDD file from the GUI can be accomplished by either clicking on the Generate New CDD File button in the Wizard window (see Chapter 30, Navigating the Wizard Window for more details on this window), by selecting the File -> Generate -> New CDD... menu option, or using the shortcut "Shift-Control-N". This file creation "wizard" allows the user to create a new CDD file that can be opened/merged into the GUI for coverage analysis. The methods that the CDD creation GUI allows for creating a new CDD file are quite flexible and are completely compatible with the command-line commands.

The following subsections describe the various windows used to create a CDD. Note that the CDD creation wizard uses several "pages" to describe the various options to set for creating a new CDD file, using Back and Next buttons on each page for navigation. Clicking on the Back button will not cause previously filled in pages to be reverted to their default values but rather will remain populated with the user's data. Similarly, if a page has been filled in with data and the Back button is clicked and then the Next button is clicked, the page contents are retained. The only way to clear out fields is to click the Cancel button at the bottom of each page and startup the CDD creation wizard again.

Clicking the Cancel button at any time will cause the CDD creation wizard to immediately exit. Clicking on the help (?) button at any time will bring up the user documentation for the current page (context sensitive help).

25.1. Navigating the New CDD Creation Option Selection Page

Figure Figure 25.1, “CDD Creation Option Selection Page” shows the look of this page of the CDD creation wizard.

Figure 25.1. CDD Creation Option Selection Page

CDD Creation Option Selection Page


The first page of the CDD creation window allows the user to select whether all options should be interactively selected within the GUI or if a file should be read in which contains command-line options to the score command to use. If the latter is chosen, the contents of that file are read in and are populated in the GUI, but the CDD creation wizard will continue in the same fashion as the first option, allowing the user to change, remove or add to the options found in that file.

If the Create CDD by interactively selecting options entry is currently selected and the user wishes to not use a command-line file to populate the rest of the CDD creation pages, simply click on the Next button at the bottom of the page to continue. If the Create CDD by using option file entry is currently selected, the user must either type a valid filename or select one by clicking the Browse... button to the right of the file entry area and select a valid file. Once a valid filename is selected, the Next button will be enabled and the user may then click it to continue to the next page. Note that any filename can be selected (whether it's a valid command file or not). Only valid score command options found in that file are used to populate the wizard entries. No error message will be displayed if the file does not contain this information.

25.2. Navigating the New CDD Creation CDD Name Page

This page is used to specify the name of the output CDD file. Figure 25.2, “CDD Creation Output Name Page” shows the display of this page.

Figure 25.2. CDD Creation Output Name Page

CDD Creation Output Name Page


The output CDD name must be specified and, as such, the Next button is disabled until a name is specified in the entry field. Any filename is allowed. If the user wishes to make use of a "Save As" style window for creating a filename, click the Browse... button and use the window for creating a filename. When the Save button is clicked, the specified filename is placed in the entry field and the Next button is enabled.

25.3. CDD Creation Type Page

This page is used to specify what type of CDD file to create. The four types of CDD files that can be created are:

  1. An unscored CDD file that was created by parsing the design. This CDD file can later be scored via a VCD, LXT2 or FST dumpfile.

    This option can be chosen by selecting the Parse Design Only radiobutton.

  2. A scored CDD file created from the design and from a previously created VCD, LXT2 or FST dumpfile.

    This option can be chosen by selecting the Dumpfile: option. If this option is chosen, a VCD, LXT2 or FST dumpfile is required to be specified before the next option page can be used. Either specify this dumpfile name by typing in an existing dumpfile name in the entry field or use the Browse... button to select a dumpfile.

  3. An unscored CDD file, a top-level Verilog file containing a PLI call to run Covered in VPI mode, and a PLI tab file that can be used by some simulators for compilation purposes. See Section 7.3, “What is needed for VPI scoring?” for details on how to use these files for simulation/scoring purposes.

    This option can be chosen by selecting the VPI Module: radiobutton. If this option is chosen, the name specified will be the name of the module file created that is used to allow Covered to run in VPI mode within a simulation. The basename of the module file will be used for the top-level module.

    In addition to providing a module name when this option is selected, the simulator type that will be used when scoring can be specified as well as the timescale information that can, optionally, be specified at the top of the generated module.

  4. An unscored CDD file and a top-level Verilog file containing the necessary $dumpfile/$dumpvars calls to score the design. This module can be compiled as a top-level module along with the design to produce a VCD/LXT2/FST dumpfile to be used for coverage scoring. See the section called “Selecting What to Dump” for details on how to use these files for simulation/scoring purposes.

    This option can be chosen by selecting the Dumpvars Module: radiobutton. If this option is chosen, the name specified will be the name of the module file created (the basename will be the name of the module and the basename of the VCD/LXT2/FST dumpfile created from the simulation) that will contain the $dumpfile/$dumpvars calls needed to score the design.

The timescale specifiers will be enabled if either the "VPI Module" or "Dumpvars Module" buttons are selected. Selecting the "Set Top Module Timescale" checkbutton will allow you to specify a timescale that will be added to the top of the VPI or dumpvars module file (setting the timescale in top-level modules is sometimes necessary for compilation purposes). If the checkbutton is not selected, no timescale information will be added to the generated top-level module file.

Figure Figure 25.3, “CDD Creation Type Page” displays the contents of this page. When all necessary fields have been specified, the Next button will be enabled and clicking it will lead to the next option page.

Figure 25.3. CDD Creation Type Page

CDD Creation Type Page


25.4. CDD Creation Options1 Page

This page is used to specify several options to Covered's score command. See figure Figure 25.4, “CDD Creation Options1 Page” for the layout of this window.

Figure 25.4. CDD Creation Options1 Page

CDD Creation Options1 Page


The following is a description about each of the CDD creation options available on this page.

General Options

  • Toplevel module name

    Required? Yes

    The name of the top-level module must be specified for a given design to be parsed and a CDD generated from that source. Simply type in the name of the top-most module in the provided entry field. Once a name is provided, the Next button will be enabled to allow traversal to the next option page.

  • Root pathname

    Required? No

    This entry field is an optional one to fill. This value is only necessary if the top-most module to be scored is not the top-most module of the simulator. If this is true, then the value that must be provided in the associated entry field must be the hierarchical reference to the module to be scored.

    An example of a valid root pathname would be something like: top.foo.bar.dut

    See Section 9.3, “Specifying What to Cover” for more information.

  • Delay Type

    This value specifies which delay should be used when a delay type of #(delay_max:delay_typ:delay_min) is encountered in the scored design. If this type of delay specification is not encountered, there is no need to change this value in the GUI. If the delay specification is encountered in the design and this value has not been specified, the default of typ will be used. Otherwise, the user can specify which delay value should be chosen by changing the displayed type to either max, typ, or min.

  • Race Condition Action

    After the design has been parsed and elaborated, Covered performs a static race condition check on the design to verify that no potential race conditions exist. If a race condition exists in the design, this would cause the coverage results to potentially be errant.

    This parameter allows the user to tell Covered what to do if a race condition is found in the design. The valid values are:

    • Silent

      Specifies that no output should be generated. Any blocks with race conditions existing within them will be automatically removed from coverage consideration.

    • Warning

      Specifies that race condition should be output and those blocks containing the race condition will be automatically removed from coverage consideration.

    • Error

      Causes Covered to display the race condition violations and stop scoring after all race condition checking has occurred.

    • Ignore

      Causes Covered to skip race condition checking completely. This option can be used if the user is confident that no real race conditions exist in the design but Covered's static race condition checker is displaying potential problems. If no race conditions actually exist, ignoring race condition checking results allows more of the design to be considered for coverage.

  • Use embedded race condition pragmas

    If this option is selected, a user-specified pragma ("racecheck" by default) is parsed and any potential race conditions found between the off/on pragma pair are ignored by the race condition checker.

    See Section 4.3, “Avoiding Race Condition Checking” for more details.

  • Default Verilog Generation

    Covered's parser supports parsing for Verilog-1995, Verilog-2001 and SystemVerilog, defaulting its parser to support SystemVerilog. However, for older designs which may contain names that are keywords in the newer versions, it may be necessary to change the parser of Covered for the entire design. This option specifies the version of the parser which is used for the entire design.

    For information regarding the ability to specify a certain version of the parser for a specific module, see the section called “Module Generation...”.

  • Include OVL Assertions

    If this option is selected, any OVL assertion modules found within the scored design will have assertion coverage information extracted from them.

Exclude Options

  • Exclude Always Blocks

    If this option is selected, all always code blocks will be excluded from coverage consideration.

  • Exclude Assign Blocks

    If this option is selected, all assign code blocks will be excluded from coverage consideration.

  • Exclude Initial Blocks

    If this option is selected, all initial code blocks will be excluded from coverage consideration.

  • Exclude Final Blocks

    If this option is selected, all final code blocks will be excluded from coverage consideration.

  • Exclude Within Pragma

    If this option is selected, all code blocks will be excluded between the exclusion off/on pragmas. The name of the exclusion pragma is defaulted to "coverage" but can be changed within the associated entry field.

    See the section called “Using the -ep Option for Exclusion” for more information.

25.5. CDD Creation Options2 Page

The second CDD creation options page contains a listbox which will contain the various user-specified options that have been inserted via the Insert... menubutton. Any options that exist within this listbox can be edited by selecting the option and clicking on the Edit... button or deleted by clicking on the Delete button. Additionally, options may be reorganized within the listbox by simply clicking on an option and dragging it into the needed position. See figure Figure 25.5, “CDD Creation Options2 Page” for the layout of this option page.

Figure 25.5. CDD Creation Options2 Page

CDD Creation Options2 Page


To add an option to the listbox, simply click on the Insert... menubutton which will display a list of options. Select one of these options to display a window where the contents of that option can be specified. Clicking the OK button in one of those windows will cause the option to be added to the option listbox. Clicking Cancel in one of those windows will cause the option to not be added to the listbox. Clicking help (?) will display context-sensitive help information to be displayed about the current window.

Figure Figure 25.6, “CDD Creation Insert Menubutton” shows the contents of the Insert... menubutton. The following sections describe each option and its corresponding entry window.

Figure 25.6. CDD Creation Insert Menubutton

CDD Creation Insert Menubutton


Source File...

Selecting this insert option will cause an open file selector window to be displayed. Use it to choose a single file that will be parsed as a library file (i.e., the -v option to most Verilog compilers).

Library Directory...

Selecting this insert option will cause an open directory selector window to be displayed. Use it to choose a single directory that will be used as a library directory (i.e., the -y option to most Verilog compilers).

Library Extension(s)...

Selecting this insert option will cause a window to be displayed that will allow the user to add library file extensions to the library file parser (i.e., the +libext+ option to most Verilog compilers). Figure 25.7, “CDD Creation Library Extension Window” is a display of this window.

Figure 25.7. CDD Creation Library Extension Window

CDD Creation Library Extension Window


To add a new extension, select the Click to Add New Extension item in the extension box (selected by default), type in the name of the extension in the upper entry box and either hit the "Enter" key or click on the Update button. If an incorrect extension was input, you may edit it by clicking on the incorrect item in the extension listbox. This will cause the item to be listed in the upper entry box where it can be edited or removed. Click the OK button to accept the specified library extensions and add these to the main window listbox. Click the Cancel button to ignore the recent updates in this window.

Include Directory...

Selecting this insert option will cause an open directory selector window to be displayed. Use it to choose a single directory that will be used as an include directory (i.e., the +incdir+ option to most Verilog compilers).

Define...

Selecting this insert option will cause a window to be displayed that will allow the user to add a command-line variable definition to be added to the score command (i.e., the +define+ option to most Verilog compilers).

Figure 25.8. CDD Creation Define Window

CDD Creation Define Window


To add a new define, enter the name of the definition variable in the entry box to the right of "Define name:". If the variable does not require a value, simply click on the OK button to submit it to the main window option listbox. If the variable requires a value, click on the = button, enter the value in the entry box to the left of that button, and click on the OK button. To abort the addition of the definition, simply click on the Cancel button.

[Note]Note
The OK will only be enabled when the user has entered a value in the "Define name:" entry box.

Parameter Override...

Selecting this insert option will cause a window to be displayed that will allow the user to add a parameter overload option to the score command. Because Verilog "defparam" is not used by the Covered parser, this option is the only way to override parameter values.

Figure 25.9. CDD Creation Parameter Override Window

CDD Creation Parameter Override Window


To add a new parameter override option, enter the full hierarchical path to the parameter to override in the left entry box and add the override value in the right entry box. See Section 9.5, “Overriding Parameters (-P option)” for details on how to specify an override value. After both values have been input, click the OK button to add the parameter override option to the main window listbox. To abort the parameter override addition, click on the Cancel button.

[Note]Note
The OK button will only be enabled if both values are input in the entry boxes.

FSM...

Selecting this insert option will cause a window to be displayed that will allow the user to add an FSM input/output state on the score command line. This option allows the user to specify the location of FSMs within the design without inlining this information with the use of pragmas for the purposes of gaining FSM coverage information.

Figure 25.10. CDD Creation FSM Specification Window

CDD Creation FSM Specification Window


To add a new FSM option, enter the name of the module containing the FSM in the upper-left entry box, the description of the output state in the upper-right entry box (see Section 9.6, “Scoring FSMs” for information on properly specifying the output/input state information). If the input state is the same as the output state, simply click on the Input == Output button which will fill in the input state with the same value as the output state value. If the input state differs from the output state, enter the input state in the lower-right entry box. When all entry fields have been filled in, click on the OK button to add the FSM description to the main window listbox. To abort the addition, click on the Cancel button.

[Note]Note
The OK button will only be enabled if all entry fields have been filled in.

Module Generation...

Selecting this insert option will cause a window to be displayed that will allow the user to specify a Verilog generation (Verilog 1995, Verilog 2001 or SystemVerilog) for a particular module. This generation value will override the universal generation value (see the "Default Verilog Generation" item in the section called “General Options”) for the design.

Figure 25.11. CDD Creation Module Generation Window

CDD Creation Module Generation Window


To specify a Verilog generation to be used for a specific module, enter the name of the module in the left entry box and select one of the Verilog generations in the drop-down menu on the left. Once this information has been specified, click on the OK button to add this option to the main window listbox. To abort the module generation addition, click on the Cancel button.

[Note]Note
The OK button will only be enabled if a module name is specified in the left entry box.

Module Exclusion...

Selecting this insert option will cause a window to be displayed that will allow the user to specify a module to exclude from parsing and coverage consideration. More information on the purpose for excluding modules is discussed in Section 9.3, “Specifying What to Cover”.

Figure 25.12. CDD Creation Module Exclusion Window

CDD Creation Module Exclusion Window


To specify a Verilog module to exclude from the score command parser, enter the name of the module in the entry box to exclude. Click on the OK button to add the module exclusion option to the main window listbox. Click on the Cancel button to abort the option addition.

[Note]Note
The OK button will only be enabled if a value is specified in the entry box.

Command File...

Selecting this insert option will cause an open file selector window to be displayed which will allow the user to find a file that contains Covered score command-line options within it. Select a file and click on the Open button to cause the selected file to be added to the main window listbox. Click on the Cancel button to abort this action.

Other Notes

After all options have been specified, the Save Options to File... button can be clicked to cause all previously specified options to be saved to a file which can later be loaded by the new CDD creation window. Simply click the button and specify a filename to save the options under and click the Save button.

When all options have been setup, click the Generate button to create the new CDD file. This button will advance to another page containing the output from Covered's score command.

25.6. CDD Creation Output Pane

The final pane in the CDD creation window wizard is the output window. After the Generate button is pressed, the user-supplied options are gathered and executed within a system shell and the output of that command is sent to this pane's textbox. If the score command run was a success, the Open/Merge the newly created CDD checkbutton will be enabled, allowing the user to open or merge the new CDD file into the GUI immediately. To exit the CDD creation process, click on the Finish button. If the score command failed for any reason, the user may click on the Back button to change the options specified to the score command or simply click the Finish button to exit the new CDD creation wizard.

Figure 25.13. CDD Creation Output Window

CDD Creation Output Window


Prev Up Next
Chapter 24. Navigating the Assertion Source Code Window Home Chapter 26. Creating an ASCII report file
covered-0.7.10/doc/html/chapter.gui.preferences.html0000644000076500007650000007334511426534466022401 0ustar trevorwtrevorwChapter 28. Navigating the Preferences Window
Chapter 28. Navigating the Preferences Window
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Chapter 28. Navigating the Preferences Window

Table of Contents

28.1. Option Categories
28.2. Preference Buttons
Apply Button
OK Button
Cancel Button
Help (?) Button
28.3. Preferences Configuration File
28.4. Preferences General Pane
Show wizard window on startup
Save state of GUI when exiting the application
Show tooltips
28.5. Preferences Color Pane
Set Highlight Color
28.6. Preference Coverage Goals Pane
Set Acceptable Coverage Goals Frame
28.7. Preferences Syntax Highlighting Pane
Set Syntax Highlighting Options
28.8. Preferences Exclusion Pane
Enable exclusion reason support when items are excluded
Create General Exclusion Reasons
28.9. Preference Merging Pane
Exclusion Reason Conflict Resolution Frame

The preferences window allows the user to adjust the view of some of the GUI elements for the purpose of more easily analyzing coverage information for a specific user. Figure 28.1, “Main Preferences Window” shows the preferences window that is created when the user selects the View > Preferences... menu option from the main window.

Figure 28.1. Main Preferences Window

Main Preferences Window


28.1. Option Categories

On the left side of the preferences window is a list of option categories that can be modified. Selecting any one of the items in the listbox will display the modifiable options to the frame to the right of the listbox. The following option categories exist:

28.2. Preference Buttons

Apply Button

Clicking on the Apply button will cause the currently selected preference options to be immediately updated in Covered but will not update the preference option values in the .coveredrc file. This has the effect of changing the preferences for the current application only. Clicking on this button will not close the Preferences window.

OK Button

Clicking on the OK button will cause the currently selected preference options to be immediately updated in Covered and will update the .coveredrc file with the new values. This also causes the Preferences window to close.

Cancel Button

Clicking on the Cancel button will cause the the Preferences window to close without updating Covered with the currently selected values and without updating the .coveredrc file.

Help (?) Button

Clicking on the help (?) button will cause the help page for the currently selected'Option Category' to be displayed.

28.3. Preferences Configuration File

User preferences are loaded from the ".coveredrc" file that is searched for in the following order:

  1. Current directory that the 'covered report -view' command was executed from.

  2. The user's home directory.

  3. The installation directory (by default this is /usr/local/share/covered).

If user preferences are changed in this window and the OK button is pressed, the settings are immediately saved back to a configuration file and the GUI is immediately updated to reflect the new user changes. If the Cancel button is pressed, all changes are thrown away and the configuration file remains unchanged. The location of the stored configuration file depends on which configuration file location was initially loaded. The following table describes this correlation.

Table 28.1. Location of Written .coveredrc File According to the Location of Read .coveredrc File

Loaded config file locationStored config file location
Current directoryCurrent directory
Home directoryHome directory
Install directoryCurrent directory
None foundCurrent directory


28.4. Preferences General Pane

The general preferences pane allows the user to control Covered's settings that are not specific to an individual task. The following subsections describe the controls available within this pane.

Show wizard window on startup

This checkbutton selects if Covered's wizard popup window will be displayed upon starting Covered. Simply check this button if you would like to see the wizard at the beginning of each startup or uncheck it to cause the wizard window to not be displayed on startup. On the wizard window itself, there is an option to change this behavior as well.

Note that you can always display the wizard window by selecting its menu option in the view menu.

Save state of GUI when exiting the application

This checkbutton determines if certain GUI element (i.e., window placement/sizing, module/instance listbox column arrangement/width/state, etc.) information is saved when the GUI exits. If this checkbutton is selected, the state is saved to the configuration file on application exit and will be used when the application is started. If the checkbutton is deselected, the state will not be saved and the default GUI element behaviors will be used.

This setting allows the user to setup the various GUI elements to their liking and retains this information whenever the application is restarted, saving the user the hassle of getting the environment setup again.

[Note]Note
While the application is being used, any GUI state information will be remembered for the duration of the application run, regardless of the setting of this preference item.

Show tooltips

This checkbutton specifies if GUI widget tooltips should be displayed if the user hovers the cursor over a GUI element that has a tooltip associated with it. To disable tooltips from being used, uncheck this option and click either the Apply or OK buttons.

28.5. Preferences Color Pane

The color preference pane allows the user to adjust the foreground and background colors for all code that is considered covered, uncovered, or in a race condition state.

Set Highlight Color

This frame contains six buttons that affect the foreground and background colors used to highlight code in the file viewer portion of the main window. The currently selected foreground/background colors are displayed to the left of the corresponding buttons to allow the user to see the selections prior to committing to them by clicking the Apply or OK buttons at the bottom of the Preferences window.

The "F" button controls the foreground color while the "B" button controls the background color. Clicking one of these buttons will bring up a color selection window that you can use to modify the current color to one of your choosing.

28.6. Preference Coverage Goals Pane

The coverage goals preference pane allows the user to change the acceptable coverage goals for each coverage metric.

Figure 28.2. Coverage Goals Window

Coverage Goals Window


Set Acceptable Coverage Goals Frame

This frame contains four spinner boxes that contains values between 0 and 100. These values correspond to a coverage percentage for each coverage metric that the user deems to be "good enough". These values are used by the listbox to help visually identify modules/instances that are meeting or exceeding these goals and which modules are not meeting these goals. If a coverage percentage for a module/instance is less than this value, the module is colored red. If the coverage percentage is greater than or equal to this value, the module/instance is colored yellow (or green which indicates that the module/instance reached 100% coverage for a given metric).

To increase the specified percentage value, simply click on the "Up" button to the right of the percentage until the desired value is displayed. To decrease the specified percentage value, simply click on the "down" button to the right of the percentage until the desired value is displayed.

  • Line Coverage %

    Sets the coverage goal of line coverage to the specified percentage to the right. If line coverage for a given module/instance meets or exceeds this percentage value, it will be displayed yellow in the Module/Instance listbox on the Main window.

  • Toggle Coverage %

    Sets the coverage goal of toggle coverage to the specified percentage to the right. If toggle coverage for a given module/instance meets or exceeds this percentage value, it will be displayed yellow in the Module/Instance listbox on the Main window.

  • Memory Coverage %

    Sets the coverage goal of memory coverage to the specified percentage to the right. If memory coverage for a given module/instance meets or exceeds this percentage value, it will be displayed yellow in the Module/Instance listbox on the Main window.

  • Combinational Logic Coverage %

    Sets the coverage goal of combinational coverage to the specified percentage to the right. If combinational logic coverage for a given module/instance meets or exceeds this percentage value, it will be displayed yellow in the Module/Instance listbox on the Main window.

  • FSM State/Arc Coverage %

    Sets the coverage goal of FSM state/arc coverage to the specified percentage to the right. If FSM state/arc coverage for a given module/instance meets or exceeds this percentage value, it will be displayed yellow in the Module/Instance listbox on the Main window.

  • Assertion Coverage %

    Sets the coverage goal of assertion coverage to the specified percentage to the right. If assertion coverage for a given module/instance meets or exceeds this percentage value, it will be displayed yellow in the Module/Instance listbox on the Main window.

28.7. Preferences Syntax Highlighting Pane

The syntax highlighting preferences pane allows the user to adjust the syntax highlighting mode and colors for any displayed Verilog source code.

Figure 28.3. Syntax Highlighting Preferences Pane

Syntax Highlighting Preferences Pane


Set Syntax Highlighting Options

This frame allows the user to specify if syntax highlighting should be performed in all Verilog source viewers or not. When the square to the left of the Turn on syntax highlighting mode is selected, syntax highlighting will occur; otherwise, it will not perform syntax highlighting. The various colored buttons below the selection mode allow the user to select the foreground color of the text associated with its specified syntax type (Comments, Preprocessor Keywords, Verilog Keywords, Strings, Constant Values, and Operation Symbols). Simply click on one of the buttons to change its color. Doing so will cause a color selection window (see Figure 28.3, “Syntax Highlighting Preferences Pane” above) to be displayed.

If the syntax highlighting mode is disabled by the user, the color selection buttons will be disabled.

28.8. Preferences Exclusion Pane

The exclude preferences pane allows the user to control whether or not the coverage exclusion reason window automatically pops up when a coverage point is excluded, and it allows the user to create some general purpose exclusion reasons. The reasons created in this pane can be selected in the exclusion reason window's drop-down table and can help to expedite the exclusion process when many coverage points are being excluded for the same reason. Figure 28.4, “Exclusion Preferences Pane” shows the layout of this preference pane.

Figure 28.4. Exclusion Preferences Pane

Exclusion Preferences Pane


Enable exclusion reason support when items are excluded

If this option is enabled, whenever the user clicks on a coverage point to cause it to be excluded from coverage, a popup window will be displayed, allowing for an exclusion message to be associated with the excluded coverage point.

If this option is not enabled, the coverage point will still be excluded but no exclusion message will be associated with it.

[Note]Note
If a coverage point was excluded and is selected to be included and the coverage point had an exclusion message associated with it, the exclusion message will be forgotten/deleted.

Create General Exclusion Reasons

This frame allows the user to add/delete general purpose exclusion reasons that can be selected from within the exclusion reason popup window's drop-down table. Having these reasons specified can help to speed up coverage point exclusion when multiple coverage points need to be excluded for the same reason.

To add a new general purpose exclusion reason, simply type in the general purpose exclusion reason in the bottom textbox (note that any formatting characters such as newlines, tabs, extra spaces will be removed from the exclusion message) and click the "+" button. You will see the exclusion reason get added to the table when this occurs. Note that the "+" button will only be enabled when you have entered at least one character in the textbox.

To remove a general purpose exclusion reason from the table, simply click on the reason in the table and click the "-" button. Note that the "-" button will only be enabled once an entry has been selected in the table.

To help find an exclusion reason more easily within the exclusion reason popup window, you may also rearrange the order of the exclusions within the table by simply clicking on an entry and dragging it to the desired location. The order of the exclusion reasons specified in this table will be the initial order of the exclusion reasons in the popup window.

28.9. Preference Merging Pane

The merging pane is needed to specify to Covered how to resolve conflicts that are found when merging CDD files. Although coverage points and exclusions are simply merged (ORed) together, things such as exclusion reasons can exist for the same coverage point but contain different information. When two exclusion reasons are given for the same coverage point, Covered must decide how to resolve this information and this preference pane allows the user to set what this behavior will be.

Figure 28.5. Merging Preferences Pane

Merging Preferences Pane


Exclusion Reason Conflict Resolution Frame

This frame allows the user to specify the way in which exclusion reason conflicts should be resolved. The following options are provided:

  • Use the first reason

    Specifies if two or more exclusion reasons are found for the same coverage point, Covered should use the exclusion reason found in the first CDD file merged. The rest of the exclusion reasons are thrown away.

  • Use the last reason

    Specifies if two or more exclusion reasons are found for the same coverage point, Covered should use the exclusion reason found in the last CDD file merged. The rest of the exclusion reasons are thrown away.

  • Use the newest reason

    Specifies if two or more exclusion reasons are found for the same coverage point, Covered should use the newest exclusion reason (when an exclusion is created, a timestamp is saved along with the coverage reason). The rest of the exclusion reasons are thrown away.

  • Use the oldest reason

    Specifies if two or more exclusion reasons are found for the same coverage point, Covered should use the oldest exclusion reason. The rest of the exclusion reasons are thrown away.

  • Merge all reasons

    Specifies if two or more exclusion reasons are found for the same coverage point, Covered should merge all of them. No information is lost in this case.

Prev Up Next
Chapter 27. Creating a CDD Ranking Report Home Chapter 29. The Exclusion Reason Popup Window
covered-0.7.10/doc/html/chapter.gui.rank.html0000644000076500007650000005346311426534466021032 0ustar trevorwtrevorwChapter 27. Creating a CDD Ranking Report
Chapter 27. Creating a CDD Ranking Report
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Chapter 27. Creating a CDD Ranking Report

Table of Contents

27.1. CDD Ranking Option Selection Page
27.2. CDD Ranking Option Page
Output ranking report name
Coverage metric weighting
Generating only names
Displaying verbose information when running rank command
27.3. CDD Ranking Input File Selection Page
Adding CDD files
Saving the CDD ranking options
Save Required CDDs to File...
Generating the CDD ranking report
27.4. CDD ranking Command Output Page

Generating a ranking report (see Chapter 12, The rank Command for more information) can be accomplished in the GUI by either selecting the Rank CDD Coverage button in the Wizard window (see Chapter 30, Navigating the Wizard Window for details), selecting the File -> Generate -> CDD Ranking Report... menu option, or using the keyboard shortcut Shift-Cntrl-C. Any of these actions will cause the CDD ranking report wizard window to be started.

The following subsections describe the various windows used to create a CDD ranking report file. Note that the CDD ranking wizard uses several "pages" to describe the various options to set for creating a CDD ranking report file, using Back and Next buttons on each page for navigation. Clicking on the Back button will not cause previously filled in pages to be reverted to their default values but rather will remain populated with the user's data. Similarly, if a page has been filled in with data and the Back button is clicked and then the Next button is clicked, the page contents are retained. The only way to clear out fields is to click the Cancel button at the bottom of each page and startup the CDD ranking wizard again.

Clicking the Cancel button at any time will cause the CDD ranking wizard to immediately exit. Clicking on the help (?) button at any time will bring up the user documentation for the current page (context sensitive help).

27.1. CDD Ranking Option Selection Page

Figure Figure 27.1, “CDD Ranking Option Selection Page” shows the look of this page of the CDD ranking wizard.

Figure 27.1. CDD Ranking Option Selection Page

CDD Ranking Option Selection Page


The first page of the CDD ranking wizard allows the user to select whether all options should be interactively selected within the GUI or if a file should be read in which contains command-line options to the rank command to use. If the latter is chosen, the contents of that file are read in and are populated in the GUI, but the CDD ranking wizard will continue in the same fashion as the first option, allowing the user to change, remove or add to the options found in that file.

If the Create CDD ranking by interactively selecting options entry is currently selected and the user wishes to not use a command-line file to populate the rest of the CDD ranking pages, simply click on the Next button at the bottom of the page to continue. If the Create CDD ranking by using option file entry is currently selected, the user must either type a valid filename or select one by clicking the Browse... button to the right of the file entry area and select a valid file. Once a valid filename is selected, the Next button will be enabled and the user may then click it to continue to the next page. Note that any filename can be selected (whether it's a valid command file or not). Only valid rank command options found in that file are used to populate the wizard entries. No error message will be displayed if the file does not contain this information.

27.2. CDD Ranking Option Page

This page of the CDD ranking wizard allows the user to specify certain options to the ranking command when it is run. The following subsections document each option within this window.

Figure 27.2. CDD Ranking Options Page

CDD Ranking Options Page


Output ranking report name

This option is a required field to fill in before the rank command can be run. Simply specify a filename in the entry box or use the Browse... button to help create a filename to save the ranking report file to.

[Note]Note
The Next button will not be enabled until a filename has been specified in the entry box.

Coverage metric weighting

The checkboxes within this frame allow the user to specify an importance value for each coverage metric. The allowed values within the entry box for each metric is a value greater than zero, where all values are relative to each other. In other words, if the weight for line coverage is set to a value of 10 and the weight of toggle coverage is set to a value of 1, it indicates that line coverage should be considered 10x more important for coverage selection purposes than toggle coverage. Changing the various weight values can have an impact on which CDD files are chosen to be included in the "need to run" list and/or the order in which CDD files should be run to maximize the coverage obtained.

By default, all metrics are included (except for assertion coverage) and are given a weight value of 1 (all coverage metrics are considered to be equally important for ranking purposes). To remove a metric from ranking consideration, simply uncheck the checkbox to the left of the metric line.

Generating only names

When a CDD ranking report is generated, the report contains header information and a columnar list of accumulated and per CDD ranking information. If the user is only interested in creating a report that includes the names of the CDD files that are needed to run (and the order to run these CDD files in), checking this option will produce just that, allowing for easier usage in Makefiles or other commands needed to run regression runs.

Displaying verbose information when running rank command

When the ranking order is being generated, there is output from the rank command concerning the filenames that are being read and when the command is writing to the output file; however, if you would like to know more information about what's going on "under the hood", enabling this option will cause more verbose information to be reported in the output screen, including the amount of time spent executing each phase of the rank process, the number of files selected for ranking in each phase, the number of coverage points hit by selected CDD files for each phase and the number of files excluded from ranking. Leave this box unchecked if this information is not important/interesting to you.

27.3. CDD Ranking Input File Selection Page

This page allows the user to add all of the CDD files to rank. Since the GUI CDD ranking generation command can be run at any time (even when no CDD files have currently been loaded), the input files to the rank command can be any valid CDD file that can be merged with each other.

As can be seen in the following figure, the window is comprised of a filename listbox in the upper left-hand corner of the page, several buttons that allow for various file selection strategies on the right-hand side of the page, a current file count information bar beneath the listbox, a button to allowing saving the currently setup ranking options to be saved to a file, a button to save any selected "required" CDD files to a file, and a Generate button in the bottom navigation bar.

Figure 27.3. CDD Ranking Input File Selection Page

CDD Ranking Input File Selection Page


Adding CDD files

Adding CDD files to be ranked is performed by clicking on one or more of the buttons on the right-hand side of the page. When files are added to the input file listbox, the current number of CDD files in the listbox are reported in the information bar beneath the listbox.

Next to each filename specified in the input file listbox is a checkbutton that specifies if the associated CDD file should be considered a mandatory CDD file to be ranked (i.e., it cannot be excluded from the list of CDD files that should be run during regression to achieve full coverage). This checkbutton can be set/cleared at any time for any CDD file in the listbox.

The following are the various ways that CDD files can be added to or removed from the input file listbox.

  • Add File(s)

    Clicking this button will bring up a file selection box that will allow the user to select one or more files that will will be added to the input file listbox with the "Required" field left unchecked. This option is useful for selecting certain files within one or more directories to rank.

  • Add CDDs from Directory

    Clicking this button will bring up a directory selection box that will allow the user to specify a directory to load CDD files from. Only files with the ".cdd" extension that exist in this directory will be added to the input file listbox.

  • Add Currently Opened

    Clicking this button will add any CDD files that are currently opened within the GUI into the input file list.

  • Add Required CDD File(s)

    Clicking this button will bring up a file selection box that will allow the user to select one or more files that will be added to the input file listbox with the "Required" field checked.

  • Add Required CDDs from List

    Clicking this button will bring up a file selection box that will allow the user to select a file that contains a list of CDD files to be required for ranking (files will be added into the input file listbox with the "Required" field checked).

  • Delete

    When one or more CDD files are selected in the input file listbox, the Delete button will be enabled. Clicking this button will remove the selected files from the input file listbox. The information bar displaying the number of currently selected CDD files will be updated accordingly.

If desired, any CDD files listed in the input file listbox can be moved to change the order of the input files. However, it should be noted that the input file order will not necessarily have any impact on the CDD ranking order list.

Saving the CDD ranking options

If the user wishes to save the current option/file list setup, click on the Save Options to File... button. This will cause a file save window be displayed where a filename can be chosen and saved to by clicking on the Save button in this window. To cancel the option save, click on the Cancel button in that window.

The generated options file can be used in the Section 27.1, “CDD Ranking Option Selection Page” window or in the command-line call to the rank command's -f option.

Save Required CDDs to File...

If one or more files are labeled as "Required" in the input file listbox, this button will be enabled. Clicking on this button will bring up a "Save As" file selection box. Specifying a filename and clicking on the "Save" button will cause a file by that name to be created that contains a list of all of the CDD files listed as "Required". This file may be used at a later time via the -required-list option to the rank command (if using the rank command on the command-line) or by clicking on the Add Required CDDs from List button in the rank command wizard input file selection page.

Generating the CDD ranking report

After all of the input files have been included (you must include more than one to create a CDD ranking report), the Generate button will be enabled, click on this button to advance to the next page in the CDD ranking wizard where the CDD ranking report command will be run and its output displayed.

27.4. CDD ranking Command Output Page

Figure 27.4. CDD Ranking Command Output Page

CDD Ranking Command Output Page


The above figure shows an example of output displayed to the CDD ranking command output page. The purpose of this page is to show you the results of the rank command run. If any errors occurred during this run, the output from those errors will be displayed within this page. If the command ran successfully, the Finish button will be enabled at the bottom of the screen.

Additionally, the View the ranking report in the GUI button will be enabled. When clicked, this button will display the created report file in a file viewer which may be read and searched. Click on the window manager "X" button to close the file viewer window. The following figure shows an example of the file viewer window and an example of the report output.

Figure 27.5. CDD Ranking Report Page

CDD Ranking Report Page


When the user has successfully generated a CDD ranking report, clicking the Finish button will close the CDD ranking report window.

Prev Up Next
Chapter 26. Creating an ASCII report file Home Chapter 28. Navigating the Preferences Window
covered-0.7.10/doc/html/chapter.gui.toggle.html0000644000076500007650000002232711426534466021353 0ustar trevorwtrevorwChapter 19. Navigating the Toggle Coverage Window
Chapter 19. Navigating the Toggle Coverage Window
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Chapter 19. Navigating the Toggle Coverage Window

Table of Contents

19.1. Understanding the Layout
19.2. Excluding/Including a Signal for Toggle Coverage
19.3. Displaying a New Signal for Toggle Coverage

The verbose toggle window allows the user to see which bits for a given signal have toggled from a 0->1 or a 1->0 during simulation. To display this window, simply click on a highlighted/underlined uncovered signal in the file viewer of the main window. This will cause the verbose toggle viewer to be created for the specified signal as well as display a "-->" symbol in the Coverage Viewer on the same line as the selected signal. This symbol is simply meant to help the user identify in the Coverage Viewer which signal is currently displayed in the Toggle Viewer window. Figure 19.1, “Verbose Toggle Window” shows the Toggle Viewer loaded with a 4-bit signal called "err_vec" in which bits 3:2 have successfully toggled from a 0->1.

Figure 19.1. Verbose Toggle Window

Verbose Toggle Window


19.1. Understanding the Layout

The bit vector displayed is a binary bit vector, each value (0 or 1) represents whether that bit in the signal either toggled (1) or did not toggle (0) during simulation. There are two bit vectors displayed for the signal, the top vector shows the 0->1 toggle information while the bottom vector shows the 1->0 toggle information.

The name of the signal along with its MSB:LSB information is displayed at the bottom of the window; however, if the mouse cursor is placed over a specific bit in the toggle box, the MSB:LSB will be changed to show the displayed bit, making it easy for the user to discern exactly which bit has toggled/not toggled. If the width of the signal exceeds the given space for the toggle window, a scrollbar will be allowed to slide left and right to view the rest of the toggle information.

To exit this window, simply click on Close button. To see this help page from the toggle window, click on the help (?) button.

19.2. Excluding/Including a Signal for Toggle Coverage

The user may exclude/include any uncovered signal in the design for toggle coverage by simply clicking on the Excluded checkbutton. If this checkbutton is checked, the exclusion reason popup window will be displayed, allowing the user to specify a reason for excluding this signal from toggle coverage. Once a reason has been specified, the summary coverage information will automatically be recalculated and redisplayed in the listbox and the background color of the underlined signal in the file viewer will change from the uncovered background color to the covered background color. However, the signal will still remain underlined, allowing the user to see the verbose toggle coverage information, if necessary. If the Excluded checkbutton is unchecked, the summary coverage information and background colors will be readjusted to include the coverage information for this signal.

If the user excludes any signal for toggle coverage in the design, the Save CDD... option in the file menu will be enabled. This allows the user to save the excluded property either back to the CDD file (or to a newly named CDD file). Doing so will allow the user to load the CDD file at a different time and retain the knowledge of which signals have been excluded/included for toggle coverage. Additionally, if a saved CDD file with coverage exclusion is merged with another CDD file, the excluded signal information is preserved for the resulting merged CDD file.

If a signal has been excluded from coverage and an exclusion reason was specified, you can view the reason for exclusion by right-click-and-holding on the Excluded checkbutton. This will cause a tooltip-style window to be displayed specifying the reason for exclusion. The background color of the tooltip will be the same color as the "covered" background color to help distinguish it from a normal tooltip. To cause the exclusion reason tooltip to disappear, simply release the button.

19.3. Displaying a New Signal for Toggle Coverage

If the Verbose Toggle Coverage window is currently displayed with a signal, the user may select a new signal in the file viewer of the Main window. When a new signal is selected, its value immediately replaces the currently selecting signal value. This feature allows many different signals to be viewed one after the other without having to create/destroy a new window for each signal.

The user may also see the previous or next uncovered signal in the main viewer by clicking either the left arrow button (for previous signal viewing) or the right arrow button (for next signal viewing). Note that the left arrow button will be disabled if there is not a signal previous to the current signal in the given module and the right arrow button will be disabled if there is not a signal after the current signal in the given module.

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covered-0.7.10/doc/html/chapter.gui.wizard.html0000644000076500007650000001170111426534466021364 0ustar trevorwtrevorwChapter 30. Navigating the Wizard Window
Chapter 30. Navigating the Wizard Window
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Chapter 30. Navigating the Wizard Window

The Wizard window starts up automatically at the start of the Covered GUI. It allows the user to quickly perform some of the more regular tasks within the GUI. The window is not necessary for performing these tasks, but for the new user it makes figuring out how to perform these tasks a bit easier. Figure 30.1, “Covered GUI Wizard Window” shows the layout of this window.

Figure 30.1. Covered GUI Wizard Window

Covered GUI Wizard Window


The buttons at the top of the window are shortcuts to performing the tasks displayed on the button. Clicking the associated button will cause a window to open to perform the given task. The following are the available shortcut buttons:

  • Generate New CDD File

    Allows the user to create a new CDD file for a given design by specifying the various scoring options needed to create the CDD file.

  • Open/Merge CDD File(s)

    Opens a CDD file for coverage viewing. If one or more CDD files have previously been opened, this option opens and merges one or more CDD files with the coverage results of the previous CDD files for coverage viewing.

  • Rank CDD Files

    Allows the user to specify CDD files that will be compared with one another and ranked in the order that they should be run in a regression to achieve the most coverage in the least amount of time. It also indicates which CDD files do not add any interesting coverage information and could, therefore, be excluded from regression for the purposes of code coverage.

At the bottom of the wizard window, there is a checkbutton option that allows the user to not display the wizard window on startup. This option can be changed in the Section 28.4, “Preferences General Pane” at any time.

When the wizard window is closed, it can be redisplayed by clicking on the View > Wizard... menu item. The window will automatically be closed when a button on the wizard window is clicked or when the user closes the window with the window manager's "X" button.

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Chapter 29. The Exclusion Reason Popup Window Home Part V. FAQ
covered-0.7.10/doc/html/chapter.installation.html0000644000076500007650000002774111426534466022015 0ustar trevorwtrevorwChapter 6. Installation
Chapter 6. Installation
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Chapter 6. Installation

Table of Contents

6.1. Prerequisites
6.2. Downloading source
6.3. Configuring the build
6.4. Compiling and Installing

6.1. Prerequisites

The goal of Covered was to create a tool that has very few requirements to allow it to be compiled and run on all platforms. The following is a list of all utilities/resources required to compile Covered. However, Covered is primarily developed on RedHat/Fedora Core Linux and Mac OS X and as such is primarily tested by the developers on these platforms.

Covered is primarily developed on Fedora Core but has been known to compile with both 32-bit and 64-bit compilers that contain the general GNU library of tools. It has also been compiled and run on Cygwin and Mac OS X.

6.2. Downloading source

To download the source files in .tar.gz format, go to the following URL:

http://covered.sourceforge.net/downloads/

Double-click on the .tar.gz version that you wish to install. The browser should immediately bring up a window asking if you would like to save to disk or open immediately. Choose the "Save to Disk" option. Another window will pop up, allowing you to choose the directory to store the tarball in. After selecting a directory, click the "Save" button. The download utility will begin downloading the tarball to the selected directory.

Once you have downloaded a tarball, enter the following to unzip and untar the package:

> gzip -dc tarball_filename | tar xvf -

This will create a directory called covered-version, where version will be of the form major version.minor version for stable releases or date for development releases. Enter that directory to begin configuring, building and compiling Covered from source.

6.3. Configuring the build

At this point, you are ready to configure the build environment to create the executables, libraries and/or documentation for Covered. However, before you configure the build environment, you will need to make a few decisions which will lead to different options given to the configure script. These questions are the following:

  1. Do you need to debug Covered? (for most users, the answer to this will be "no")

    If the answer to this question is yes, configure the build environment with the --enable-debug option to the configure script. Doing so will allow you to use the global -D option and/or the -cli (Section 15.2, “Command-Line Interface (CLI)”) score command option for debugging; however, it will also have the side effect of causing the score command to run noticably slower. For normal usage of Covered, this option should not be specified when configuring.

  2. Do you want to profile Covered's internal functionality? (for most users, the answer to this will be "no")

    If the answer to this question is yes, configure the build environment with the --enable-profiling option to the configure script. Doing so will allow you to use the global -P option to generate an output file containing internal profiling information for the run command. See Section 15.3, “Source Code Profiling” for more information on the -P option.

  3. Will you being using Covered as a VPI module and, if so, what simulator(s) will you need VPI modules built for?

    If the answer to this question is yes and you need to build a VPI module for the Icarus Verilog simulation tool, simply add --with-iv on the configure command-line. If a VPI shared object module is needed for the Cver simulator, simply add --with-cver=cver_include_dir on the configure command line, where cver_include_dir specifies the directory that contains the vpi_user.h file. If a VPI shared object module is needed for the VCS simulator, simply add --with-vcs=vcs_include_dir on the configure command line, where vcs_include_dir specifies the directory that contains the vpi_user.h file.

  4. Do you want to use Covered's Tcl/Tk GUI for interactive coverage analysis or just the command-line created reports?

    If the answer to this question is yes and you have a Tcl/Tk distribution that the configure script cannot find (i.e., the tcl-config and tk-config scripts exist in a non-standard directory location), please specify the --with-tcl-config=tcl-config_pathname and --with-tk-config=tk-config_pathname options to the configure script. If the answer to this question is no, specify the --with-tcltk=no option to the configure script to cause the GUI to not be built.

Once you have determined which configuration options you need, simply enter the following command:

> ./configure options

This command will create the Makefiles/include files necessary for your machine to compile the source code correctly. If any errors are generated during this command run, it is usually an indication that some program or library is missing from your computer that is necessary for Covered to compile/run. Please install any missing programs/libraries and type this command again.

6.4. Compiling and Installing

If the configure script completes successfully, you may compile the source with the following command:

> make

This will begin the process of compiling/linking the source code for Covered. This stage may take a while. When the source files have been compiled, the covered executable file will have been created. To install this executable in your /usr/local/bin directory, enter the following command:

> make install

This will install the covered executable and manpage help files. Once covered is installed, make sure that /usr/local/bin is in your environment path. You are now ready to run Covered.

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Chapter 1. Introduction
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Chapter 1. Introduction

Table of Contents

1.1. What is Covered?
1.2. What can code coverage do?
1.3. What can't code coverage do?
1.4. What does Covered do?
1.5. What does Covered NOT do?
1.6. What makes Covered different?

1.1. What is Covered?

Covered is a Verilog code coverage analysis tool that can be useful for determining how well a diagnostic test suite is covering the design under test (DUT). It is command-line based with an optional Tcl/Tk GUI report viewer, making it portable across almost all platforms.

1.2. What can code coverage do?

Typically, in the design verification work flow, a design verification engineer will develop a self-checking test suite to verify design elements/functions specified by a design's specification document. When the test suite contains all of the tests required by the design specification, the test writer may ask:

  • "How much logic in the design is actually being exercised?"

  • "Does my test suite cover all of the DUT?"

  • "Am I done writing tests for the logic?"

  • "Do I have any redundant diagnostics in my test suite?"

When the design verification gets to this point, it is often useful to get some metrics for determining logic coverage. This is where a code coverage utility, such as Covered, is very useful.

The metrics obtained by using a code coverage analysis tool can be very useful for determining the following about a design and the test suite testing that design:

  1. Completeness of the test suite in terms of logic coverage.

  2. Unexercised logic in the design (useful in helping to determine what types of tests need to be added to the test suite).

  3. Corner cases in design that are untestable.

1.3. What can't code coverage do?

It is important to note that any code coverage tool is only useful in indicating how much logic is being covered by a test suite. It does not indicate that the covered logic works appropriately. This, of course, can only be verified by the diagnostics themselves.

Additionally, it is possible that two or more diagnostics can achieve the same coverage and yet be functionally testing different characteristics of a design. Since the coverage metrics are not improved in this case, one may conclude that the second test is unnecessary. This may or may not be true depending on what is being tested; it is always up to the test writer to determine the necessity of a diagnostic. Using the code coverage tool results as the sole means of making this determination is not recommended. Use common sense in these areas.

1.4. What does Covered do?

Covered is a tool that uses your design files along with standard VCD, LXT2 or FST dump files to analyze the code coverage of the DUT. The code coverage information is stored in a special database file that can be retrieved and "merged" with new coverage information to create a summed coverage total for several tests. After a database file has been created, the user may generate various ASCII reports that summarize the coverage information or run Covered's GUI to interactively analyze the coverage information. Additionally, multiple CDD files from the same design can be ranked for the purposes of running regressions and understanding which CDD files do not add coverage information and can be excluded from regressions runs, if needed.

1.5. What does Covered NOT do?

Though Covered does perform some resimulation of the design to derive line, combinational logic, memory, and assertion coverage, Covered is NOT a full-fledged compiler/simulator and should not be used for such purposes. Additionally, Covered is NOT a linting tool. Many syntax/semantic issues that are not allowed by the LRM are allowed by Covered for purposes of making Covered's core more generic and/or simplistic. Please make sure that your code is properly linted in your design flow using an appropriate tool.

1.6. What makes Covered different?

Most Verilog code coverage tools perform a pre-compilation procedure known as instrumenting. During this procedure, the coverage tool will read in the DUT and generate its own version of the DUT with additional code added to aid in calculating coverage after the simulation is complete. The benefits to this style are higher performance of the coverage tool when it is run after the simulation. The drawbacks to this approach are that it slows down simulation speed and a trust issue that the coverage tool did not alter your simulation model when it performed the instrumentation.

Covered, on the other hand, omits the instrumenting procedure all-together and only performs its analysis on a pre-simulated design. This means that Covered cannot make a mistake to your simulation and the simulation is allowed to run faster since there is no additional code that must be run to get coverage data. The drawback is that there is some overhead in post-simulation for extracting coverage data but this is typically less than the simulation overhead in the other method.

Additionally, unlike all other commercial coverage tools, Covered is free! No license managers to invoke and maintain. No licensing fees and negotiations. The only thing the developers of Covered want in return are bug reports and user input (and perhaps a donation if you find the software useful and want to see its development continue). Isn't the open source life grand?!

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Chapter 10. The merge Command
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Chapter 10. The merge Command

Table of Contents

10.1. Usage
10.2. Options
10.3. Merging Rules
Block Merging
Single Module Merging

10.1. Usage

The merge command is initiated with the following call:

covered merge [options] existing_CDD CDD_to_merge+

The existing_CDD specifier relates to any existing CDD. If the -o option is not specified (see below for details), this file will be replaced with the merged CDD created by the merge. This is important to remember since merging is an irreversible operation (apart from generating a brand-new CDD from the design and dumpfile using the score command).

The CDD_to_merge specifier relates to any existing CDD that is not the existing_CDD. Though it is not illegal to merge the same CDD to itself, the result is the same as the original CDD. Note that all files treated as CDD_to_merge are guaranteed not to be modified by the merge command. These files are only read by Covered and then merged into the information contained in the existing_CDD.

10.2. Options

Table 10.1. Options to merge Command

Option Description
-d directory Directory to search for CDD files to include. This option is used in conjunction with the -ext option which specifies the file extension to use for determining which files in the directory are CDD files.
-er (first|last|all|new|old)

Specifies how to handle exclusion reason resolution. If two or more CDD files being merged have exclusion reasons specified for the same coverage point, the exclusion reason needs to be resolved (unless it is the same string value). If this option is not specified and a conflict is found, Covered will interactively request input for each exclusion as to how to handle it. If this option is specified, it tells Covered how to handle all exclusion reason conflicts. The values are as follows:

Table 10.2. 

Value Description
first The CDD file that contained the first occurence of the exclusion should use its reason in the merged CDD file.
last The last CDD file that conflicts with a previous CDD file should use its reason in the merged CDD file.
all All conflicting coverage points will merge their exclusion reason information into a single exclusion reason.
new The newest exclusion reason should be used (all exclusion reasons are timestamped).
old The oldest exclusion reason should be used (all exclusion reasons are timestamped).


-ext extension Used in conjunction with the -d option. If no -ext options are specified on the command-line, the default value of '.cdd' is used. Note that a period (.) should be specified.
-f filename Name of file containing additional arguments to parse. You may specify this option more than once on a command-line.
-h Outputs usage information for the merge command.
-m message Allows the user to specify information about this CDD file which can be most anything. All messages found in merged CDDs will not be included in the merged CDD file.
-o filename Name of CDD to write merged coverage information to (if not specified, the existing_CDD is overwritten with merged CDD).


10.3. Merging Rules

In previous versions of Covered, merging could only be accomplished when the top-most scored modules of each CDD were the same the module. Typically, the user would score the entire DUT in each diagnostic run, creating a set of CDD files that could be merged together to see the overall coverage of the diagnostic runs. While this capability still exists, Covered has recently been enhanced to allow more complex merging which provides some new capabilities.

Block Merging

Covered's merging algorithms have now been enhanced to allow merging CDDs that are generated for different parts of the same DUT. That is to say that each instance or sub-tree in the design can be scored individually and can be merged together. This ability allows for the DUT to be split up into smaller parts, scored in parallel and then merged back together to create a single CDD containing the scored results for the entire DUT. This parallel scoring capability can now be used to speed up scoring of large designs by taking advantage of multiple CPUs or CPU cores.

The following is an example of a DUT (top-most module of the DUT is block A) and the generic covered calls to score and create a single CDD file containing coverage for the entire design.

Figure 10.1. Example of Verilog hierarchy to be scored in parallel

Example of Verilog hierarchy to be scored in parallel


The following commands could be used to score the DUT comprised of blocks A-G in parallel (each score command below could occur in parallel with all other score commands). 

  covered score -t A -i MAIN.A -e B -e C -o A.cdd ...
  covered score -t B -i MAIN.A.B -e D -e E -o B.cdd ...
  covered score -t C -i MAIN.A.C -e F -e G -o C.cdd ...
  covered score -t D -i MAIN.A.C.D -o D.cdd ...
  covered score -t E -i MAIN.A.C.E -o E.cdd ...
  covered score -t F -i MAIN.A.B.F -o F.cdd ...
  covered score -t G -i MAIN.A.B.G -o G.cdd ...

  covered merge -o total.cdd A.cdd B.cdd C.cdd D.cdd E.cdd F.cdd G.cdd

In addition to allowing for parallel scoring, this merge method allows users to gain coverage results for smaller parts of the design and merge them into a single CDD containing coverage results for the entire design. This can be advantageous for those that are focused on increasing coverage for a specific portion of the design. Scoring can be done on that small part and the coverage gained can be added into an existing CDD containing coverage information for the entire design.

Using Figure 10.1, “Example of Verilog hierarchy to be scored in parallel” this type of merging would be performed as such: 

  covered score -t A -i MAIN.A total.cdd   // The initial coverage file for the entire design

  covered score -t C -i MAIN.A.C -o CDE.cdd ...   // Coverage obtained for modules C, D and E only

  covered merge total.cdd CDE.cdd

Single Module Merging

Along with the capability to merge different portions of the same large design, it is also possible to merge CDDs that were generated from different testbenches but have modules that are in common with each other. This allows different teams to work together to enhance coverage for shared design blocks. It is important to note that when this type of merging is being performed that the top-most covered module in the CDDs labeled CDD_to_merge exist exactly once in the CDD labeled existing_CDD for instance coverage information to be reported correctly. If the module is instantiated more than once in the existing_CDD, the CDD will still be merged but only the module coverage information will be correct.

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Chapter 9. The score Command Home Chapter 11. The report Command
covered-0.7.10/doc/html/chapter.metrics.html0000644000076500007650000006242611426534466020761 0ustar trevorwtrevorwChapter 2. Coverage Metrics
Chapter 2. Coverage Metrics
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Chapter 2. Coverage Metrics

Table of Contents

2.1. Line Coverage
Description
Example
Recommendations
2.2. Toggle Coverage
Description
Example
Recommendations
2.3. Memory Coverage
Description
Recommendations
2.4. Combinational Logic Coverage
Description
Example
Recommendations
2.5. Finite State Machine (FSM) Coverage
Description
Example
Recommendations
2.6. Assertion Coverage
Description
Recommendations

Covered currently generates six types of code coverage metrics.

2.1. Line Coverage

Description

Line coverage simply answers the question, "Was this line of code executed during simulation?"

Covered will display the number of logical lines of code that exist in a particular file with the number of logical lines that were executed during the simulation along with a percentage indicating the percentage of lines executed. If verbose mode is selected for a report, Covered will display the lines of logic that were not executed during the simulation run.

Example

Suppose that the following module was specified in your DUT that is being analyzed:

Example 2.1. Line Coverage Code Sample

  module test;

    reg a, b, c;

    initial begin
      a = 0;    // Line 1
      b = 1;    // Line 2
      if( a )
        c = b;  // Line 3
      else
        c = ~b; // Line 4
    end

  endmodule


If this code were simulated as stated, the simulator would execute lines 1 and 2, and due to the value assigned to a, line 4 would be executed. This means that during execution, out of a possibility of 4 lines, only 3 were executed. Therefore, Covered would state that for this module the line coverage percentage would be 75% (or 3 out of 4).

Recommendations

For a design to pass full coverage, it is recommended that the line coverage for all modules in a design receive 100% coverage. If a line of logic is not executed during simulation, the design has not been fully exercised. Line coverage is useful for determining holes in the test suite.

2.2. Toggle Coverage

Description

Toggle coverage answers the question, "Did this bit of this wire/register change from a value of zero (0) to one (1) and back from one (1) to zero (0) during simulation?"

A bit is said to be fully covered when it toggles back and forth at least once. This metric does not indicate to the user that every value of a multi-bit vector was seen. For example, if we have a two bit vector called "foo", toggle coverage will not tell you that the value of foo was set to the values of 0, 1, 2 and 3. However, it will tell you that all bits in that vector were toggled back and forth.

Example

Suppose that a DUT was comprised of the following module:

Example 2.2. Toggle Coverage Code Sample

  module test;

    reg [2:0] a;

    initial begin
      a = 3'b0;
      #10;
      a = 3'b110;
      #10;
      a = 3'b010;
      #10;
    end

  endmodule


The register called "a", after being simulated, would have achieved a total toggle percentage of 50% (or 3 out of 6). Can you see which toggles are missing?

Bit 0 has never toggled to 1 (and has never been at a value of 1 and toggled to 0); therefore, bit-0 has toggled 0% (0 out of 2). Bit 1 has toggled from a value of 0 to 1, but has not toggled from a value of 1 to 0; therefore, bit-1 has toggled 50% (0 out of 2). Bit 2 is the only bit that has fully toggled, achieving a toggle percentage of 100% (2 out of 2). If you add all of the possible toggles to the number of achieved toggles, you end up with 3 out of 6 (or 50% total toggle coverage).

Recommendations

For a design to pass full coverage, it is recommended that the toggle coverage for all modules in a design received 100% coverage. If a bit is never changes value, it is usually an indication that a mode is not being exercised in the design or a datapath has a stuck-at issue.

2.3. Memory Coverage

Description

Memory coverage answers a number of questions about memories/multi-dimensional arrays being used in your design, including the following:

  1. Did all bits of each addressable memory element toggle from 0 to 1?

  2. Did all bits of each addressable memory element toggle from 1 to 0?

  3. Did every addressable memory element get written?

  4. Did every addressable memory element get read?

Memories/multi-dimensional arrays can have two types of dimensions, packed and unpacked. Packed dimensional information is specified to the left of an array declaration while unpacked dimensional information is specified to the right of an array declaration. Consider the following example:

Example 2.3. Memory Coverage Code Sample

  reg [3:0][2:0] foo[0:15];


The memory "foo" consists of three dimensions. The first dimension is an unpacked dimension which specifies that there are 16 addressable memory elements (AME). The number of AMEs are determined by multiplying the unpacked dimension of an array. The second two dimensions are packed dimensions, creating a total of 12 bits for each AME.

Other than getting toggle coverage information for each AME, memory coverage also allows us to easily see which AMEs were written and read during simulation. If all entries of a memory have not been written during a regression run, it could indicate several shortcomings of either the testbench or a logical problem with the write control logic, including, but not limited to, the following:

  1. If no AMEs for a given memory were written, it could indicate that the testsuite was never able to get out of bypass mode for that memory.

  2. If fewer AMEs for a given memory were written than were read, it could indicate that there is a read controller issue leading to an underflow issue with the memory.

  3. For memories that act like stacks or use lowest/highest address first write selection scheme, indicates that the memory was never completely filled (may miss out on things like buffer overflow errors).

  4. For memories that are written in a round-robin fashion, indicates that either not enough entries were written (could miss a write pointer wrap bug) or that there is a logical issue by which the write pointer did not properly increment in a round-robin fashion.

  5. If there are "holes" in the write coverage of the AMEs (that is an AME is found to not have been written while those above and below it have been), this could indicate a corner case logic bug or other testsuite issue that needs to be addressed.

If all entries of a memory have not been read during a regression run, it could indicate several other shortcomings of either the testbench or a logical problem with the read control logic, including, but not limited to, the following:

  1. If no AMEs for a given memory were read, it could indicate that the testsuite was never able to get out of bypass mode for that memory.

  2. If fewer AMEs for a given memory were read than written, it could indicate that a resource allocation issue.

  3. For memories that are written in a round-robin fashion, indicates that either not enough entries were read (could miss a read pointer wrap bug) or that there is a logical issue by which the read pointer did not properly increment in a round-robin fashion.

  4. If there are "holes" in the read coverage of the AMEs (that is an AME is found to not have been read while those above and below it have been), this could indicate a corner case logic bug or other testsuite issue that needs to be addressed.

Currently, Covered simulates all memories/multi-dimensional arrays and its coverage is automatically accumulated during the score command. To see its report information, either specify the -m m option to the report command or bring up the GUI for interactive analysis.

Recommendations

For a design to pass full coverage, it is recommended that the write/read memory coverage for all modules in a design receive 100% coverage. If every AME was not both written and read during simulation, the design has not been fully exercised. Toggle coverage per AME need not receive 100% since a memory element that is written once will not cause toggle coverage to change.

2.4. Combinational Logic Coverage

Description

Combinational logic coverage answers the question, "What values did an expression (or subexpression) evaluate to (or not evaluate to) during the course of the simulation?"

This type of coverage is extremely useful in determining logical combinations of signals that were not tried during simulation, exposing potential holes in verification.

Example

Suppose the DUT comprised of the following module:

Example 2.4. Combinational Logic Coverage Code Sample

  module test;

    reg  a;
    reg  b;
    wire c;

    initial begin
      a = 1'b0;
      b = 1'b1;
      #10;
      a = 1'b1;
      #10;
    end

    assign c = a | b;

  endmodule


This module comprises of only one expression: a | b. If this module were simulated it would result in a combinational coverage value of 50% (2 out of 4). Can you determine which cases are not being covered?

The expression "a | b" can result in two values, 0 and 1, but can do so in four combinations:

  1. a = 0, b = 0, c = 0

  2. a = 0, b = 1, c = 1

  3. a = 1, b = 0, c = 1

  4. a = 1, b = 1, c = 1

Noticing the values assigned to a and b during simulation, shows that combinations (2) and (4) were hit during execution while combinations (1) and (3) were not (2 out of 4 - 50%). This also shows us that the value of c was never 0 during simulation.

Recommendations

For a design to pass full coverage, it is recommended that the combinational logic coverage for all modules be 80% or higher. If the expression coverage for an expression is not 100%, it is recommended that the verification engineer closely examine these missed cases to determine if more testing is required. Sometimes certain combinations of signals are unachievable due to design constraints, keeping the expression coverage from ever reaching a value of 100% but still can be considered fully covered.

2.5. Finite State Machine (FSM) Coverage

Description

Finite state machine (FSM) coverage answers the question, "Did I reach all of the states and traverse all possible paths through a given state machine?"

There are two types of coverage detail for FSMs that Covered can handle:

  1. State coverage - answers the question "Were all states of an FSM hit during simulation?"

  2. State transition coverage - answers the question "Did the FSM transition between all states (that are achievable) in simulation?"

Example

Suppose the DUT comprised of the following finite state machine:

Example 2.5. FSM Coverage Code Sample

  module test( clock );
  
    input clock;

    reg [1:0] state;
    reg req, gnt;

    parameter IDLE 2'b00;
    parameter REQ  2'b01;
    parameter WAIT 2'b10;
    parameter GNT  2'b11;

    initial begin
      req = 1'b0;
      gnt = 1'b0;
      repeat(4) @(posedge clock);
      req <= 1'b1;
      @(posedge clock);
      req <= 1'b0;
      gnt <= 1'b1;
      @(posedge clock);
      gnt <= 1'b0;
      repeat(2) @(posedge clock);
    end

    always @(posedge clock)
      case( state )
        IDLE : state <= req ? REQ : IDLE;
        REQ  : state <= gnt ? GNT : WAIT;
        WAIT : state <= gnt ? GNT : WAIT;
        GNT  : state <= IDLE;
        default : state <= 2'bx;
    endcase

  endmodule


To help visualize this state machine, let's also display it as a digraph.

Figure 2.1. Digraph Version of Example FSM

Digraph Version of Example FSM


This state machine has four states: IDLE, REQ, WAIT, GNT. During simulation, 75% of the states were hit (3 out of 4) including IDLE, REQ and GNT. You can see that the WAIT state was never hit during simulation since the gnt signal was asserted the clock period after the req signal asserted.

Additionally, this state machine contains 7 state "arcs" which are represented in the digraph as arrowed lines. They are the following: 

  1. IDLE -> IDLE  (hit)
  2. IDLE -> REQ   (hit)
  3. REQ  -> WAIT  (missed)
  4. REQ  -> GNT   (hit)
  5. WAIT -> WAIT  (missed)
  6. WAIT -> GNT   (missed)
  7. GNT  -> IDLE  (hit)

Counting the number of traversed arcs during simulation, we can see that we have covered 4 out of 7 (or 57%) of the possible arcs in this state machine.

Recommendations

For a design to pass full coverage, it is recommended that the FSM coverage for all finite state machines in the design to receive 100% coverage for the state coverage and 100% for all achievable state transitions. Since Covered will not determine which state transitions are achievable, it is up to the verification engineer to examine the executed state transitions to determine if 100% of possible transitions occurred.

2.6. Assertion Coverage

Description

Assertion coverage answers the question, "Did I hit all of the possible coverage points of the assertions that I included in the design?"

Currently, Covered is capable of finding all OVL (Open Verification Language) assertion modules instantiated within the design (when the -A ovl option has been specified to the score command). Within most OVL assertion modules are one or more built-in coverage points. When the user has specified a particular assertion instance to check for a coverage point, Covered simulates this assertion module, keeping track of which coverage points within the assertion have been hit during simulation (and how many times each coverage point has been hit) and which have not. This allows the user to check for more complex coverage scenarios within the design.

Currently, only OVL version 1.6 (and newer) are supported. Older versions of the OVL may not work and are not planned to be supported.

Recommendations

For a design to pass full coverage, it is recommended that the assertion coverage for all modules in a design receive 100% coverage. If an assertion coverage point is not hit during simulation, the design has not been fully exercised. Assertion coverage is useful for determining more specific corner case holes in the test suite.

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Chapter 4. Race Condition Checking
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Chapter 4. Race Condition Checking

Table of Contents

4.1. Checked Coding Guidelines
4.2. Race Condition Handling
4.3. Avoiding Race Condition Checking
4.4. Reporting Race Conditions

Due to Covered's method of abstracting coverage from a dumpfile, a partial "resimulation" of the design is needed to obtain proper statistics for line, combinational logic and FSM metrics. Therefore, accurately resimulating what occurred in the actual simulation is a requirement for obtaining correct results. This can be easily achieved so long as the design doesn't contain any code that could result in potential race conditions.

4.1. Checked Coding Guidelines

To avoid this problem Covered performs automatic race condition checking on the specified design after parsing has been completed but before simulation/scoring is performed. All statement blocks in the design that don't adhere to certain coding guidelines are removed from coverage consideration by Covered. By following these coding guidelines, a design should be void of race condition scenarios that would lead to faulty simulation results. The following coding guidelines are applied by Covered when checking for race conditions:

  1. All sequential logic and latches use non-blocking assignments.

  2. All combinational logic in an always block uses blocking assignments.

  3. All mixed sequential and combinational logic in the same always block uses non-blocking assignments.

  4. Blocking and non-blocking assignments should not be used in the same always block.

  5. Assignments made to a variable should only be done within one always block.

  6. The $strobe system call should only be used to display variables that were assigned using non-blocking assignments. (Not currently implemented)

  7. No #0 procedural assignments should exist. (Not currently implemented)

4.2. Race Condition Handling

If Covered detects a block as violating any one of the above mentioned coding guidelines, it will do one of two things depending on options specified to the score command by the user.

  1. If the -rS, -rW or none of the -r options are specified, Covered will simply remove the non-conforming always block from coverage consideration and continue with scoring. -rW will display a message describing detected race conditions during the scoring command while the -rS option will display no messages.

  2. If the -rE option is specified, Covered will halt the score command after all race condition checking has been performed with a message to the user specifying how many always blocks were found to be in non-compliance to the race-condition-free coding guidelines.

The first mode of operation is the recommended mode of operation as this will allow Covered to continue calculating coverage information for the design while still providing accurate coverage information for the logic that is still under consideration. The second mode of operation is meant to allow the user to use Covered as a race-condition checking tool.

4.3. Avoiding Race Condition Checking

Covered has three means of avoiding race condition checking: (1) skip race condition checking for the entire design altogether, (2) skip race condition checking for one or more specified modules, or (3) place inline pragmas around specific logic blocks to avoid checking. The main advantage for using either of these methods is to allow Covered to score more of the design that would otherwise be excluded due to failing a static race condition checkpoint. The main disadvantage to avoiding race condition checking using either of these methods is that you could potentially be ignoring code that contains an actual race condition, causing Covered to potentially generate incorrect coverage information without warning. These types of "errors" are not assumed to be Covered bugs.

To exclude the entire design from race condition checking, simply specify the -rI option on the score command-line. This will cause Covered to skip the race condition checking phase entirely, outputting a warning message (unless the global -Q option has been specified). The use of this command-line option is highly discouraged due to its general assumption by the user that the entire design is void of race conditions.

To exclude an entire module from race condition checking, simply specify the -rI=module name option on the score command-line. This option may be specified one or more times on the score command-line (once for each module to be skipped).

To exclude portions of the design from race condition checking, the user may also place inline comment-based pragmas in the design and specify the -rP option to the score command-line. The inline pragmas look like the following:

Example 4.1. Using a Race Condition Pragma

  module foobar;
      
    ...
      
    // racecheck off 
    always @(posedge clock) begin
      ...
    end
    // racecheck on
      
    ...
      
  endmodule


This example will cause the initial block surrounded by the racecheck pragmas to be ignored from race condition checking, thus making it available for coverage consideration. If there are any race condition rules that this block contains or is a part of, they will not be reported.

The keyword racecheck is the default pragma keyword for race condition checking avoidance; however, if this name needs to be changed to something else by the user (i.e., if racecheck is used by another tool and has a different meaning or format), the user may make this keyword anything they please as long as the meaning is preserved (i.e., keyword off means that race condition checking should be turned off for all subsequent code until its matching keyword on pragma is seen). The new name of this keyword is passed to the -rP option by specifying -rP=keyword. It should also be noted that race condition pragmas can be embedded within each other (all code within the outside pair are removed from race checking) and race condition avoidance pragmas (racecheck off) are in effect on a file-basis -- that is, they are in effect even beyond their current scope but are no longer in effect after the current file.

4.4. Reporting Race Conditions

Even though race condition information is displayed (assuming the -rS option was not specified in the score command-line) during the scoring process, it may be convenient to view this information in a generated report as well. Because of this need, Covered saves all race condition information to the CDD file for use in using the report command. By specifying 'r' in the -m option to the report command (race condition report output is not turned on by default), the statement blocks which were eliminated from coverage consideration will be output to the coverage report file. Summary coverage will contain the total number of statement blocks eliminated for each module. Verbose coverage will contain each eliminated statement block, organized by module, specifying both the starting line of the eliminated statement block and the reason for why the statement block was removed.

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Chapter 12. The rank Command
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Chapter 12. The rank Command

Table of Contents

12.1. Options
12.2. Methods for specifying CDDs to rank
12.3. Specifying metric weights
12.4. Understanding the rank command output information
12.5. Description of ranking algorithm

The rank command allows the user to specify a number of CDD files that have been created from the same DUT (presumably in a regression run -- but not necessarily) and rank them in order of coverage importance. This information can be useful in accomplishing the following tasks:

  • Understand which CDD files (simulations) can be eliminated from regression due to their inability to add useful coverage information that selected CDD files already hit.

  • Understand the best order to run simulations in full regression.

  • It can help in creating a quick (confidence) regression which is meant to hit a good deal of the overall coverage points in a short period of time to verify that recent changes don't massively break a previously working DUT. This can be accomplished by selecting the first N simulation CDD files in the ranked list. The selection can easily be done by either using the simulation order, accumulated hit, hit percent or timestep column values as a means of selection.

12.1. Options

Table 12.1. Options to rank Command

Option Description
-depth number Specifies the minimum number of CDD files to hit each coverage point. The value of number should be a value of 1 or more. Default is 1.
-d directory Directory to search for CDD files to include. This option is used in conjunction with the -ext option which specifies the file extension to use for determining which files in the directory are CDD files.
-ext extension Used in conjunction with the -d option. If no -ext options are specified on the command-line, the default value of '.cdd' is used. Note that a period (.) should be specified.
-f filename Name of file containing additional arguments to parse.
-h Displays help information for the rank command.
-names-only If specified, outputs only the needed CDD filenames that need to be run in the order they need to be run. If this option is not set, a report-style output is provided with additional information.
-o filename Name of file to output ranking information to. Default is stdout.
-require-cdd filename Name of CDD file to use as a required CDD file for ranking, regardless of whether it is necessary to achieve full coverage or not.
-require-list filename Name of file containing list of CDD files which are required to be in the list of ranked CDDs to be run, regardless of whether they are necessary to achieve full coverage or not.
-v Outputs verbose information during the run of the rank command. Useful for selection process understanding and command performance.
-weight-assert number Specifies a relative weighting for assertion coverage used to rank non-unique coverage points.
-weight-comb number Specifies a relative weighting for combinational logic coverage used to rank non-unique coverage points.
-weight-fsm number Specifies a relative weighting for FSM state/state transition coverage used to rank non-unique coverage points.
-weight-line number Specifies a relative weighting for line coverage used to rank non-unique coverage points.
-weight-memory number Specifies a relative weighting for memory coverage used to rank non-unique coverage points.
-weight-toggle number Specifies a relative weighting for toggle coverage used to rank non-unique coverage points.


12.2. Methods for specifying CDDs to rank

The rank command provides several mechanisms for specifying CDD files to rank. Feel free to use any combination of methods for providing this information to Covered as it makes sense to do in your environment. The following is the list of input methods:

  • Specify each CDD file after the rank command options have been specified. This method is best when there are a relatively small number of CDD files to rank as the length of the command-line in a shell is typically limited to a certain number of characters.

  • Create a file containing the list of CDD files to rank and pass this file to the rank command's -f option. Using this method, one can selectively specify a large number of CDD files. You may specify as many "-f filename" options as is necessary.

  • Use shell commands to create a list of CDD files and pass them to Covered's standard input via command-line piping and the -f - command-line option (the - means use standard input). The following line is an example of this usage: 

      ls foo*.cdd | covered rank -f -

    You may specify only one "-f -" option to the rank command.

  • Use the -d directory and -ext extension options to tell Covered to retrieve all files found in the directory specified by directory that contain the file extension of extension (if the -ext option is not specified, the default extension of ".cdd" is used). The following is an example of this usage: 

      covered rank -d /home/bubba/cdd_dir -ext .mycdd

    You may specify as many -d options on the command-line as is necessary; however, only one -ext option is allowed.

  • Specify a single CDD file that MUST be included in the final ranking list via the -require-cdd option. You can specify as many -require-cdd options to the rank command as necessary.

  • Create a file containing a list of CDDs that MUST be included in the final ranking list where each CDD filename is separated by a newline or whitespace. Pass this file to the -require-list option. You can specify as many -require-list options to the rank command as necessary.

12.3. Specifying metric weights

The rank command has several options that allow the user to weight any and all of the coverage metrics that Covered supplies. Weights are used to ascribe the importance of its metric in ranking the value of a CDD file.

Weight values are non-negative numbers whose values are relative to each other. A value of 0 effectively disables the associated weight from consideration in ranking. All other values are considered relative to each other. In other words, if the line weight is set to a value of 5 while the toggle weight is set to 1, line coverage is considered 5 times more important than toggle coverage in ranking.

By default, each metric is given an equal weight of 1. Adjust each of the metrics as necessary to potentially modify which CDD files are chosen and what order those CDD files are given in the ranked list of diagnostics to run.

12.4. Understanding the rank command output information

After the rank command has been executed, the output will either be displayed to standard output (if no -o option was specified) or it will be output to a file. If the -names_only option was specified, the output will be a list of CDD filenames (one per line) which are output in the order in which they should be run to achieve full coverage in the shortest amount of time. If the -names_only option was not specified, the output will be in the form of a table (similar to reports generated with the report command) which describes not only the order that CDD files should be run but also various statistical data and the names of CDD files which are considered redundant in terms of coverage information. The following example shows an example of this report output.

Example 12.1. Rank Output With No Required Files

                                           ::::::::::::::::::::::::::::::::::::::::::::::::::::
                                           ::                                                ::
                                           ::     Covered -- Simulation Ranked Run Order     ::
                                           ::                                                ::
                                           ::::::::::::::::::::::::::::::::::::::::::::::::::::



* Reduced 3 CDD files down to 2 needed to maintain coverage ( 33% reduction,   1.5x improvement)
* Reduced 9 timesteps down to 6 needed to maintain coverage ( 33% reduction,   1.5x improvement)

-----------+-------------------------------------------+----------------------------------------------------------
           |                ACCUMULATIVE               |                             CDD
Simulation |-------------------------------------------+----------------------------------------------------------
Order      |        Hit /      Total     %   Timesteps |  R  Name               Hit /      Total     %   Timesteps
-----------+-------------------------------------------+----------------------------------------------------------
         
         1            9           17   53%           3       rank1c.cdd           9           17   53%           3 
         2           13           17   76%           6       rank1b.cdd           8           17   47%           3 

---------------------------------------  The following CDD files add no additional coverage  ----------------------------------------------

         3           13           17   76%           9       rank1a.cdd           8           17   47%           3


After the header information, there is a summary of the ranking reduction (if one occurred) specified in both number of files and number of simulation timesteps. Example 12.2, “Rank Output With Required Files” shows what this information looks like when no file reduction has occurred.

After the summary information, there is the rank output table which displays both the individual CDD information and the accumulative coverage information. Each row of the table contains one CDD file where the first row contains the first CDD that should be run in regression for maximum coverage impact. Each successive row contains CDD files that add less and less coverage to the overall coverage gained. If there were CDD files that were found to not add any coverage information to the above CDD files, a line is drawn and these CDD files displayed below that line. These CDD files can be excluded from regression because they don't add any useful coverage information over-and-above the CDD files that are selected to be run in regression.

The first major column is the simulation order. This value increments by one for each successive row. If you would like to create a shorter running regression that is limited to a certain number of simulations, this row information can be useful for figuring out which simulations to include in these type of regressions.

The second major column is the accumulative coverage statistics which include the following:

  • Hit

    The first row contains the number of coverage points that the first CDD file hit. All successive rows add the unique coverage points hit by the CDD file listed on that line to the above hit total.

    For example, in Example 12.1, “Rank Output With No Required Files” "rank1c.cdd" contains 9 hit coverage points (accumulative hit count = 9). The second highest ranked file, "rank1b.cdd", contains 8 hit coverage points but only 4 of those coverage points are different than the coverage points hit by "rank1c.cdd"; therefore, the accumulative coverage hit count is 13. The third coverage file, "rank1c.cdd", contains 8 coverage points but none of them add to the coverage points hit by the first two coverage files; therefore, it is considered unnecessary for regression.

  • Total

    The "accumulative" total represents the total number of coverage points in each CDD file. Since this number must be the same for each CDD file, this value will be the same for each row.

  • %

    This column represents the hit percentage and is a simple calculation of hit / total for each row.

  • Timesteps

    This column represents the number of accumulated simulation timesteps. This value represents the number of timesteps that need to transpire to gain the amount of accumulated coverage. One of the goals of the ranking algorithm is to gain the most amount of coverage in the least amount of simulation time.

The third major column is the individual coverage information for the CDD file listed in the row which includes the following information:

  • R

    This column represents whether the current CDD file was a required CDD file by the user (a file listed via the -require-list or -require-cdd options). If the file is a required CDD file, an asterisk (*) is listed in this column. If the file was not required, nothing will be listed in this column. Example 12.2, “Rank Output With Required Files” provides an example of what this output looks like.

  • Name

    Filename of the CDD file that was selected for this row.

  • Hit

    This column represents the number of coverage points hit by the CDD file.

  • Total

    This column represents the total number of coverage points within the CDD file that could be hit.

  • %

    This column represents the hit percentage (a calculation of hit / total.

  • Timesteps

    This column represents the number of simulation timesteps that the CDD file took to run during simulation. This value does not necessarily represent the ending simulation time.

Example 12.2. Rank Output With Required Files

                                           ::::::::::::::::::::::::::::::::::::::::::::::::::::
                                           ::                                                ::
                                           ::     Covered -- Simulation Ranked Run Order     ::
                                           ::                                                ::
                                           ::::::::::::::::::::::::::::::::::::::::::::::::::::



No reduction occurred 

-----------+-------------------------------------------+------------------------------------------------------------
           |                ACCUMULATIVE               |                              CDD
Simulation |-------------------------------------------+------------------------------------------------------------
Order      |        Hit /      Total     %   Timesteps |  R  Name                 Hit /      Total     %   Timesteps
-----------+-------------------------------------------+------------------------------------------------------------

         1            9           17   53%           3       rank1.1c.cdd           9           17   53%           3
         2           13           17   76%           6    *  rank1.1b.cdd           8           17   47%           3
         3           13           17   76%           9    *  rank1.1a.cdd           8           17   47%           3


12.5. Description of ranking algorithm

This section describes the overall algorithm that is used to rank the specified CDD files. The algorithm is being presented in this document for the purposes of providing an explanation for how diagnostics are selected for ranking and how they are ranked. Knowing this information is not necessary for using the rank command or understanding its results.

The algorithm makes use of three different types of structures. The first structure is a bit-compressed structure where each bit corresponds to one coverage point in the associated CDD file. The purpose of this structure is to store a large amount of information as concisely and immediately available as possible. In addition to coverage point information, each structure also contains the following information:

  • Name of CDD file that the structure is associated with (for reporting purposes only).

  • The number of timesteps that occurred during the CDD simulation. This is used for calculating the average number of coverage points hit during a single clock period -- used for ranking selection.

  • The total number of coverage points hit by the CDD. This is used for calculating the average number of coverage points hit during a single clock period -- used for ranking selection.

  • The total number of coverage points that were hit by this CDD that were not hit by any other CDD listed in the rank command-line. This information is used to figure out which CDDs are absolutely necessary to be included in the ranked list.

  • The current score associated with the CDD file. This value is updated for each selection iteration.

Each of these structures are maintained in an array that is iterated on during the ranking process.

The second structure is an array of 16-bit values where each value corresponds to a single coverage point. Its value is a sum of the number of unranked CDD files that have hit that coverage point. Each value is decremented by one when a CDD file is moved from the unranked list to the ranked list and that CDD file hits the given coverage point. If a coverage point value is a value of 1 and a CDD file has its corresponding coverage bit set, we know that the CDD is the only one that hits the coverage point.

The third structure is similar to the second and works similarly, except that it stores the number of CDD files in the ranked list that hit a particular coverage point.

The specified CDD files are ranked in a series of steps, some of which are reiterated for each CDD that is selected to be ranked. Here is the basic algorithm (in pseudo-code): 

      
  calculate the size of the compressed coverage point structure
  
  foreach CDD in CDD_list {
    convert CDD to compressed coverage point structure
  }
  
  foreach CDD in CDD_list {
    if this CDD contains uniquely hit coverage points {
      move the CDD file into the ranked list
    }
  }
  
  foreach CDD in unranked list {
    foreach CDD in unranked list {
      calculate score (((total_num_cov_points_hit / num_timesteps) * 100) * metric_weight_value)
      if any unranked elements are less than the -depth option value and are hit by this CDD {
        set unique_found to true
      }
      if our score > highest score and a "unique" coverage point was found {
        set highest_score to our score
      }
    }
    move the CDD file indexed by highest_score from the unranked list to the ranked list
  }
  
  resort ranked list from most unique to least unique (if there is a tie, select the CDD that hit the most coverage
    points in the least amount of time)

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Chapter 11. The report Command Home Chapter 13. The exclude Command
covered-0.7.10/doc/html/chapter.reading.html0000644000076500007650000012250611426534466020720 0ustar trevorwtrevorwChapter 14. Reading the Report
Chapter 14. Reading the Report
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Chapter 14. Reading the Report

Table of Contents

14.1. Reading Line Coverage
Summary Information Description - Module-based
Summary Information Description - Instance-based
Summary Information Description - Both
Verbose Information Description - Both
14.2. Reading Toggle Coverage
Summary Information Description - Module-based
Summary Information Description - Instance-based
Summary Information Description - Both
Verbose Information Description - Both
14.3. Reading Memory Coverage
Summary Information Description - Module-based
Summary Information Description - Instance-based
Summary Information Description - Both
Verbose Information Description - Both
14.4. Reading Combinational Logic Coverage
Summary Information Description - Module-based
Summary Information Description - Instance-based
Summary Information Description - Both
Verbose Information Description - Both
14.5. Reading FSM Coverage
Summary Information Description - Module-based
Summary Information Description - Instance-based
Summary Information Description - Both
Verbose Information Description - Both
14.6. Reading Assertion Coverage
Summary Information Description - Module-based
Summary Information Description - Instance-based
Summary Information Description - Both
Verbose Information Description - Both

This chapter describes the meanings of the textual report output that Covered generates when the report command is issued. It is well understood by the developers of Covered that a code coverage tool is only as good as the output that it generates, and this, of course, includes the ability to discern the information provided by the report.

To help describe the various sections of a Covered report, we will use a relatively small Verilog file containing our DUT, generating the two main types of reports (module and instance) based on the CDD generated for this file. This example file is provided here

After being compiled and run, this module is scored with the following Covered command:

covered score -t main -v example.v -o example.cdd -vcd example.vcd

The module-based verbose report can be viewed in its entirety example.rptM.html and is generated with the following command:

covered report -d v example.cdd

The instance-based verbose report can be viewed in its entirety here and is generated with the following command:

covered report -i -d v example.cdd

The instructions for analyzing each of the six types of coverage information from the report can be found on the following pages.

  1. Section 14.1, “Reading Line Coverage”

  2. Section 14.2, “Reading Toggle Coverage”

  3. Section 14.3, “Reading Memory Coverage”

  4. Section 14.4, “Reading Combinational Logic Coverage”

  5. Section 14.5, “Reading FSM Coverage”

  6. Section 14.6, “Reading Assertion Coverage”

For information on reading race condition information in the report, please see the user guide page detailing race conditions and viewing the reports.

14.1. Reading Line Coverage

Summary Information Description - Module-based

For module-based reports, the summary table for line metrics includes information for the name of each module that was covered and the name of the file in which the module is described in. Lines 15 through 24 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma and fsmb. The table shows that all three modules were described in the file "example.v".

Summary Information Description - Instance-based

For instance-based reports, the summary table for line metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand-side of each row. Lines example.rptI.html#15 of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1" and "main.fsm2".

Summary Information Description - Both

On the right-hand side of each row in the table are the hit, miss and total numbers for the line coverage, followed by a calculated percent of the lines that were hit (calculated by taking the number of lines hit during simulation divided by the total number of lines that Covered simulated). The hit value indicates how many lines were executed during the simulation; the miss value indicates the number of lines not executed during simulation; and the total value indicates the total number of lines within the specified module/instance that Covered was able to simulate.

If the percentage value in the far left of the summary table is 100%, this indicates that all lines that Covered was capable of simulating (for the module/instance of this row) were executed. If the value of the percentage is less than 100%, this indicates that some number of lines were not executed and full coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any lines in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%.

Verbose Information Description - Both

If the miss value for a particular module was not 0 (indicating that lines were missed during simulation) and the '-d v' option was specified on the command-line (specifying to output verbose reporting information), the line that was missed during simulation will be output below the summary information per module that contained missed lines. In our sample report, there was one line that was missed during simulation (according to the summary output) for the module called "fsmb" (instance "main.fsmb"). The line number and Verilog line that was missed is output in lines 25 through 29 of the module-based report and in lines 25 through 29 of the instance-based report.

If a module does not contain any missed lines and the '-d v' option was specified, no verbose output will be displayed for this module. Likewise, if a module/instance does not contain any lines that Covered could execute, no verbose output will be displayed.

[Note]Note

The definition of what Covered considers a line is a statement (ex. assignment, conditional, etc.). If a statement is written in such a way that it consumes multiple file lines, Covered only counts the statement as one line. The user can assume that if the beginning of a statement is labeled as missed, the entire expression was missed (not just the first line of the expression). For example, consider the following code: 

  always @(posedge b)
    a <= (b & c) |
         (d & e);

If the expression 

  a <= (b & c) | (d & e);

is not executed during simulation, Covered will indicate that only one line was missed during execution (not two), and it will display the missing line (if verbose reporting is specified with the '-d v' option) as the following: 

  2:      assign a <= (b & c) ...

The "..." notation at the end of the Verilog output indicates that the statement was a multiline statement in the source code but is only considered one line.

14.2. Reading Toggle Coverage

Summary Information Description - Module-based

For module-based reports, the summary table for toggle metrics includes information for the name of each module that was covered and the name of the file in which the module is described in. Lines 41 through 51 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma and fsmb. The table shows that all three modules were described in the file "example.v".

Summary Information Description - Instance-based

For instance-based reports, the summary table for toggle metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand-side of each row. Lines 41 through 51 of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1" and "main.fsm2".

Summary Information Description - Both

On the right-hand side of each row in the table are the hit, miss and total numbers for the toggle 0->1 coverage, followed by a calculated percent of the signal bits that toggled from a value of 0 to a value of 1 (calculated by taking the number of bits that toggled from 0 to 1 during simulation divided by the total number of signal bits). The hit value indicates how many signal bits were toggle from a value of 0 to 1 during simulation; the miss value indicates the number of signal bits that were not toggled from a value of 0 to 1 during simulation; and the total value indicates the total number of signal bits within the specified module/instance that Covered was able to simulate.

To the right of this information is the hit, miss and total statistics for signal bits that toggled from a value of 1 to a value of 0.

If the percentage values in the right of the summary table are 100%, this indicates that all signal bits toggled from a value of 0 to 1 and back to 0 during simulating (for the module/instance of this row). If the values of the percentage are less than 100%, this indicates that some signal bits did not fully toggle during simulation and full toggle coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any signals in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%.

Verbose Information Description - Both

If the miss value for a particular module/instance was not 0 (indicating that one or more signal bits did not fully toggle during simulation) and the '-d v' option was specified on the command-line (specifying to output verbose reporting information), the signals that were missed during simulation will be output below the summary information per module/instance that contained missed signal bit toggles. In our sample module-based report, there were three signals in module "main" ("go", "state", and "error"), three signals in module "fsma" ("go", "state" and "next_state"), and three signals in module "fsmb" ("go", "next_state" and "state") that were not fully toggled (see lines 53 through 90).

For each signal in the verbose toggle table, the format is the following: 

        <signal_name>          0->1: <hexidecimal_value>
        .......................1->0: <hexidecimal_value>

The name of the signal is specified in the upper left corner. The bitwise toggle information for the signal from a value of 0 to a value of 1 is specified in the upper right corner. The hexidecimal value represents bits in the signal, each bit corresponding to the matching bit of the signal. If a bit value is set to the value 1, this indicates that this bit in the signal toggled from a value of 0 to a value of 1. If a bit value is set to the value 0, this indicates that this bit in the signal did NOT toggle from a value of 0 to a value of 1; therefore, full toggle coverage was not achieved for this signal. For example, for the signal called "go" in the module/instance "main", the verbose toggle information looks like: 

  go         0->1: 1'b1
  ...........1->0: 1'b0

This is indicating that bit 0 of the signal called "go" successfully toggled from a value of 0 to 1 during simulation (because the bit value at bit location 0 is a value of 1). However, the signal did not toggle from a value of 1 to a value of 0 during simulation, thus the signal was not considered fully toggled.

It is important to note that the hexidecimal values are displayed with the least-significant bit of the signal being output on the far right of the value while the most-significant bit of the signal is output on the far left of the value.

14.3. Reading Memory Coverage

Summary Information Description - Module-based

For module-based reports, the summary table for memory metrics includes information for the name of each module, instantiating one or more memories, that was analyzed and the name of the file in which the module is described in. Lines 93 through 111 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma and fsmb. The table shows that all three modules were described in the file "example.v".

Summary Information Description - Instance-based

For instance-based reports, the summary table for memory metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand-side of each row. Lines 93 through 111 of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1" and "main.fsm2".

Summary Information Description - Both

On the right-hand side of each row in the table are the hit, miss and total numbers for the various memory coverage metrics, followed by a calculated percent of each memory coverage metric that was hit (calculated by taking the number hit during simulation divided by the total number that Covered could have simulated). The hit value indicates how many were executed during the simulation; the miss value indicates the number not executed during simulation; and the total value indicates the total number within the specified module/instance that Covered can simulate. All four metrics (AME toggle 0->1, AME toggle 1->0, AME write and AME read) are listed in the summary section.

If the percentage value in the far left of the summary table is 100%, this indicates that all coverage points that Covered was capable of simulating (for the module/instance of this row) were executed. If the value of the percentage is less than 100%, this indicates that some number of coverage points were not executed and full coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any coverage points in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%.

Verbose Information Description - Both

When a module/instance is found to be not fully covered (i.e., the number of each hit coverage points is not equal to the associated number of attainable coverage points), the missed coverage points for each AME in the memory are output to the report as follows: 

  <AME>  Written: <0 or 1>  0->1: <hexidecimal_value>
  .....  Read:    <0 or 1>  1->0: <hexidecimal_value> ...

The answers to each of the questions listed above are specified with a 0 (meaning that the answer is "NO") or a 1 (meaning that the answer is "YES"). Note that in the toggle coverage information, like toggle coverage verbose information, the individual bits are grouped together and displayed in hexidecimal form to conserve space and make the task of figuring out exactly which bit positions did not toggle easier. See lines 117 through 151 for an example of this output.

If the -c option is used, Covered outputs the names of the memories that were fully covered during simulation only.

14.4. Reading Combinational Logic Coverage

Summary Information Description - Module-based

For module-based reports, the summary table for combinational logic metrics includes information for the name of each module that was covered and the name of the file in which the module is described in. Lines 154 through 164 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma, and fsmb. The table shows that all three modules were described in the file "example.v".

Summary Information Description - Instance-based

For instance-based reports, the summary table for combinational logic metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand-side of each row. Lines 154 through 164 of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1", and "main.fsm2".

Summary Information Description - Both

On the right-hand side of each row in the table are the hit, miss and total numbers for the combinational logic coverage, followed by a calculated percent of the combinational logic expression values that were hit (calculated by taking the number of combinational logic expression values hit during simulation divided by the total number of expression values that Covered could have simulated). The hit value indicates how many expression values were achieved during the simulation; the miss value indicates the number of expression values not achieved during simulation; and the total value indicates the total number of combinational logic expression values that could have been achieved in the specified module/instance.

If the percentage value in the far left of the summary table is 100%, this indicates that all combinational logic expression values that Covered was capable of achieving (for the module/instance of this row) were hit. If the value of the percentage is less than 100%, this indicates that some number of expression values were not achieved and full coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any combinational logic expressions in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%.

Verbose Information Description - Both

The verbose output for combinational coverage is a bit more sophisticated than the line or toggle. Basically, for each expression that was found to not be fully covered (either the expression itself or some sub-expression in the tree was not fully covered), the expression is output with various sub-expressions underlined and identified with a number. Each expression is also supplied with the line number that the expression started at in its module file. In our example, there is an uncovered expression in the module called "main" (see lines 170 through 205 (numbered 5) which contains four uncovered subexpressions (numbered 1 through 4).

Below each expression, there will be one or more tables which specify a particular sub-expression that was not fully covered along with information describing what cases were not covered for that sub-expression.

In the report output above, we see that there was one expression in module "main" that did not achieve 100% coverage that starts on line 14 of the Verilog source. The expression is output to the report with certain sub-expressions underlined and labeled with an integer value for reference.

For this one expression, there were found to be four subexpressions (labeled 1, 2, 3, 4) that were found to not be 100% covered. Taking a look at subexpression 1 report output, the numbers to the right of the string "Expression 1" tell us the number of logical combinations of this subexpression that were hit (in this case 2 combinations were hit) and the total number of logical combinations that this subexpression can have (in this case 3 combinations were achievable). The character string below this information tells us the type of subexpression that we are examining. For subexpression 1, the type is the bitwise AND operator.

The table below this information for subexpression 1, lists the potential combinations that this subexpression could have reached with a '*' character placed underneath the combination(s) that were missed. In the case of subexpression 1, the left and right subexpressions did not evaluate to values of 1 simultaneously. The letter 'L' above each possible combination indicates the value that the left subexpression achieved at the same time as the value under the right subexpression indicated with the letter 'R'. Legal values for a subexpression are '0', '1' or '-' (which indicates that this subexpression value could either be 0 or 1).

14.5. Reading FSM Coverage

Summary Information Description - Module-based

For module-based reports, the summary table for FSM metrics includes information for the name of each module that was covered and the name of the file in which the module is described in. Lines 344 through 354 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma and fsmb. The table shows that all three modules were described in the file "example.v".

Summary Information Description - Instance-based

For instance-based reports, the summary table for FSM metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand-side of each row. Lines 344 through 354 of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1" and "main.fsm2".

Summary Information Description - Both

On the right-hand side of each row in the table are the hit, miss and total numbers for the FSM state coverage, followed by a calculated percent of the FSM states that were hit (calculated by taking the number of FSM states hit during simulation divided by the total number of FSM states that Covered could have simulated). The hit value indicates how many FSM states were executed during the simulation; the miss value indicates the number of FSM states not executed during simulation; and the total value indicates the total number of FSM states within the specified module/instance that Covered can simulate.

To the right of the FSM state summary information is the FSM state-transition hit, miss, total and percentage hit summary information for each module/instance.

If the percentage value in the far left of the summary table is 100%, this indicates that all FSM states and state-transitions that Covered was capable of simulating (for the module/instance of this row) were executed. If the value of the percentage is less than 100%, this indicates that some number of FSM states and/or FSM state-transitions were not executed and full coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any FSMs in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%.

Verbose Information Description - Both

The verbose output for FSM coverage is split into the state coverage information and the state transition coverage information. When an FSM is found to be not fully covered (i.e., the number of hit states/state transitions is not equal to the number of attainable states/state transitions), the missed states are output to the report as a list of state values in hexidecimal format as follows: 

  <hexidecimal value>

When an FSM is found to be not fully covered, the missed state transitions are output to the report as a list of state transitions in the format below: 

  <hexidecimal input state value> -> <hexidecimal output state value>

If the -c option is used or the number of attainable state/state transitions are unknown for the specified FSM, Covered outputs this information in the same way as the missed cases except that the title of the output is "Hit cases". If the number of attainable states/state transitions is unknown, providing the cases that were hit during simulation is useful in aiding the user in determining coverage. In this case, the summary report will output question marks in the missed and total categories, showing the user that this information was not known by Covered.

14.6. Reading Assertion Coverage

Summary Information Description - Module-based

For module-based reports, the summary table for assertion metrics includes information for the name of each module, instantiating one or more assertions, that was covered and the name of the file in which the module is described in. Lines 397 through 405 of the module-based report show what this information looks like in the report. We have three modules that were scored within our DUT: main, fsma and fsmb. The table shows that all three modules were described in the file "example.v".

Summary Information Description - Instance-based

For instance-based reports, the summary table for assertion metrics includes information for the Verilog hierarchy pertaining to each instance on the left-hand side of each row. Lines 397 through 405 of the instance-based report show what this information looks like in the report. In our DUT example, there are three instances within the design with the Verilog hierarchies of "main", "main.fsm1" and "main.fsm2".

Summary Information Description - Both

On the right-hand side of each row in the table are the hit, miss and total numbers for the assertion coverage points (ACP), followed by a calculated percent of the ACPs that were hit (calculated by taking the number of ACPs hit during simulation divided by the total number of ACPs that Covered could have simulated). The hit value indicates how many ACPs were executed during the simulation; the miss value indicates the number of ACPs not executed during simulation; and the total value indicates the total number of ACPs within the specified module/instance that Covered can simulate. Note that more than one coverage point may exist within a single assertion coverage module.

If the percentage value in the far left of the summary table is 100%, this indicates that all ACPs that Covered was capable of simulating (for the module/instance of this row) were executed. If the value of the percentage is less than 100%, this indicates that some number of ACPs were not executed and full coverage was not achieved for that module/instance. Note that for a module/instance which does not contain any ACPs in which Covered was able to simulate, the values of hit, miss, and total will be 0 while the hit percentage value will indicate 100%.

Verbose Information Description - Both

When a module/instance is found to be not fully covered (i.e., the number of hit ACPs is not equal to the number of attainable ACPs), the missed coverage points are output to the report as follows: 

  <Instance Name>	<Assertion Name>	<Coverage Point Description>

If the -c option is used, Covered outputs this information in the same way as the missed cases except that the title of the output is "Hit cases" and the number of times each ACP was hit is indicated.

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Chapter 13. The exclude Command Home Chapter 15. Debugging
covered-0.7.10/doc/html/chapter.report.html0000644000076500007650000003620111426534466020616 0ustar trevorwtrevorwChapter 11. The report Command
Chapter 11. The report Command
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Chapter 11. The report Command

Table of Contents

11.1. Usage
11.2. Options
11.3. Summary Vs. Detailed Vs. Verbose
Summary Report
Detailed Report
Verbose Report
11.4. Module Vs. Instance
11.5. Covered Vs. Uncovered

11.1. Usage

The report command is initiated with the following call:

covered report (-h | -view [CDD_filename] | [options] CDD_filename)

The CDD_filename refers to the name of the CDD to generate the report for. This CDD may be either the result of a score or the result of merging CDDs.

If the -view option is specified, Covered's GUI is run. You may specify the CDD filename to initially load with the -view option. See Chapter 16, Introduction to the GUI for instructions on using the GUI for interactive coverage analysis.

11.2. Options

The following table lists the options available for use with the report command.

Table 11.1. Options to report Command

Option Description
-b If combinational logic verbose output is reported and the expression is a vector operation, this option outputs the coverage information on a bitwise basis.
-c Used in conjunction with the '-d d' or '-d v' option. If set, causes covered logic to be reported instead of default behavior of reporting uncovered logic. See Section 11.5, “Covered Vs. Uncovered”
-d (s|d|v) Level of report detail (s=summary, d=detailed, v=verbose). Default is to display summary coverage information. See Section 11.3, “Summary Vs. Detailed Vs. Verbose”.
-e Outputs exclusion cases when the -d v or -d d options are specified on the command-line. The exclusion cases are displayed in the verbose format along with an exclusion reason (if one is associated with the excluded case).
-f filename Name of file containing additional arguments to parse. You may specify this option more than once on a command-line.
-h Outputs usage information for the report command.
-i Generates report information for each instance (default is to generate per module). See Section 11.4, “Module Vs. Instance”
-m [l][t][c][f][r][a][m] Specifies type of coverage information to report (l=line, t=toggle, c=combinational logic, f=FSM state/arc, r=race condition, a=assertion, m=memory). Default is ltcf.
-o filename Specifies output file to stream report to (default is standard output).
-s Suppresses modules/instances that do not contain any coverage information from being output to the coverage report. This may eliminate potentially meaningless information from the report.
-view Starts the interactive Covered report viewer GUI.
-w (number) Specifies the maximum line width (in characters) that can be used to output Verilog information. If this option is not specified, all Verilog code in the report will retain the same formatting as was specified in the original Verilog code. If this option is specified, Verilog code will be formatted to use as much of the current line as possible, wrapping text when the line reaches the maximum line width. The default maximum line width is 115 characters (this value is used if no number is specified with the -w option). If a number is specified with the -w option, this value is used for the maximum line width.
-x When used in conjunction with the -d v or -d d option, causes all uncovered or excluded coverage points to display an associated "exclusion ID" to the left of the verbose output within parenthesis. This exclusion ID can be used in calls to the exclude command for the purposes of excluding or including coverage points.


11.3. Summary Vs. Detailed Vs. Verbose

There are three forms of reports that can be generated by the Covered report function: summary, detailed, and verbose. The three forms are described below.

Summary Report

A summary report shows at a very high-level what the coverage for a specific module (or instance) is in terms of line, toggle, combinational and/or FSM coverage (depending on which types are selected on the command line). Each coverage metric for the module is given a percentage of items covered for that metric as well as the total number of items per metric, the number of items "hit" during simulation and the number of items "missed" during execution. See the chapter on "Reading the Report" for more information on understanding the formats of line, toggle, combinational logic, and FSM summary information.

The summary report is useful for understanding exactly which modules are missing coverage (and what type(s) of coverage are missing) as well as what modules are fully covered. This can help guide you more easily in understanding where you need to improve your code coverage without getting lost in all of the details that the verbose reporting provides.

Detailed Report

The detailed report is useful for understanding where logic was found to be uncovered in the design along with some higher-level information to understand why it was considered to be uncovered. This amount of detail is between the minimum (summary coverage) and the maximum (verbose coverage) and should be used as the first detailed report to be looked at since it is easier to read and comprehend the coverage results.

Verbose Report

The verbose report contains all of the data that the summary report contains; however, in addition to the summary information for a module (or instance), a more in-depth look at the exact cases that were "missed" during simulation are provided. This report outputting option is useful for combinational logic report information when a more in-depth look at why certain expressions did not reach full coverage is needed. This option allows the user to look at all subexpressions of an expression that were not fully covered.

11.4. Module Vs. Instance

Any report can be calculated by module or by instance. Both reports are of interest for verification purposes and the differences are described as follows.

Module reporting combines the results of all instances that come from the same module. That is, when a module is instantiated multiple times in a design, the coverage results from all covered instances are merged together and output as one combined module. This reporting format allows a test writer to see if any logic within a module has not been touched during simulation.

Instance reporting displays each instance in the covered design separately (no combining occurs). This reporting format is useful for determining if certain instances within a design are being neglected. For instance, if a module is instantiated four times (i.e., four instances of the same buffer), it may be that the first buffer is used more often than the other three buffers. This could indicate controller errors or just an indication that there was not enough activity during simulation to fill the other buffers (need to bolster diagnostics or possibly some buffers could be removed?) This type of information would not be viewable if only module reporting were performed.

11.5. Covered Vs. Uncovered

Covered has the ability the generate reports from any given CDD file that displays either uncovered logic (the default behavior) or covered logic. It is understandable why one would want to generate reports displaying uncovered logic (this is probably the reason why you are interested in this tool in the first place). However, why would anyone be interested in reporting covered logic?

The reason for having this option is two-fold (and maybe there are other reasons). First, this option is useful in debugging the report command since it let's the user evaluate whether a particular signal or portion of logic was actually fully covered or not. Second, it may be useful for user's of the tool to understand what logic is being evaluated for coverage and what logic is not. If only uncovered logic was supplied for evaluation of the tool, one could not evaluate the effectiveness of the tool. However, by allowing the user to see what logic is covered and uncovered, a more full picture of the tool's capability can be understood.

To generate a report that specifies what logic is not covered (output only available in verbose reporting mode), no further options are needed. To generate a report that specifies what logic is being covered, simply specify the -c option along with the -v option when calling the report command.

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Chapter 10. The merge Command Home Chapter 12. The rank Command
covered-0.7.10/doc/html/chapter.score.html0000644000076500007650000013600511472127327020414 0ustar trevorwtrevorwChapter 9. The score Command
Chapter 9. The score Command
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Chapter 9. The score Command

Table of Contents

9.1. Usage
9.2. Options
9.3. Specifying What to Cover
9.4. Specifying What Not to Cover (Coverage Exclusions)
Using the -ep Option for Exclusion
9.5. Overriding Parameters (-P option)
9.6. Scoring FSMs
9.7. The reason for the -conservative feature
9.8. Specifying Plus Arguments When Scoring
9.9. Other Notes

9.1. Usage

The score command is initiated with the following call:

covered [global_options] score -t top_module [options]

The top_module parameter is required for the scoring purposes and represents the top-most module that will be covered. It is important to note that Covered does not need to parse the entire DUT. It only parses that part of the design which will receive coverage results. More on this will be described Section 9.3, “Specifying What to Cover” below.

9.2. Options

The following table describes the additional options that can be passed to the score command. Note that it is optional in how you tell Covered where to find the Verilog design files; however, it is not optional to exclude the Verilog files. If no Verilog can be found that contains at least the top instance, Covered will generate an error message to the user specifying that it was unable to find the required Verilog modules.

Table 9.1. Options to score Command

Option Description
-A ovl Causes OVL assertions to be used for assertion coverage. This flag must be given to the score command if assertion coverage metrics are needed in the report command. See Section 2.6, “Assertion Coverage”.
-cli [filename] Causes the command-line debugger to be used during VCD/LXT2/FST dumpfile scoring. If filename is specified, this file contains information saved in a previous call to savehist on the CLI and causes the history contained in this file to be replayed prior to the CLI command prompt. If filename is not specified, the CLI prompt will be immediately available at the start of simulation. This option is only available when Covered is configured with the --enable-debug option. See Section 15.2, “Command-Line Interface (CLI)”.
-conservative If this option is specified, any logic blocks that contain code that would cause coverage discrepancies leading to potentially inaccurate coverage results are removed from coverage consideration. See Section 9.7, “The reason for the -conservative feature” for more information.s
-D name[=value] Defines the specified name to 1 or the specified value.
-dumpvars [filename] If this option is specified without the -vcd, -lxt or -fst options, the design is parsed, a CDD file is created and a top-level Verilog module named filename (if this value is specified) or "covered_dump.v" (if filename is not specified) is created. If compiled as a top-level module along with your design and no other $dumpfile/$dumpvars calls are made, this dump module will provide additional performance gains. If either the -vcd, -lxt or -fst options are specified, this option has no effect. See the section called “Selecting What to Dump”.
-e module Name of module, task, function or named begin/end block to not score. You may specify this option more than once on a command-line; one for each block to remove from coverage. See Section 9.4, “Specifying What Not to Cover (Coverage Exclusions)”.
-ea Specifies that all always blocks in the design should be excluded from coverage consideration. This option may help to increase performance of the score command if all always blocks in the design do not need to be checked for coverage. By default, always blocks are considered for coverage. See Section 9.4, “Specifying What Not to Cover (Coverage Exclusions)”.
-ec Specifies that all continuous assignments in the design should be excluded from coverage consideration. This option may help to increase performance of the score command if all assign blocks in the design do not need to be checked for coverage. By default, continuous assignments are considered for coverage. See Section 9.4, “Specifying What Not to Cover (Coverage Exclusions)”.
-ef Specifies that all final blocks in the design should be excluded from coverage consideration. This option may help to increase performance of the score command if all final blocks in the design do not need to be checked for coverage. By default, final blocks are considered for coverage. See Section 9.4, “Specifying What Not to Cover (Coverage Exclusions)”.
-ei Specifies that all initial blocks in the design should be excluded from coverage consideration. This option may help to increase performance of the score command if all initial blocks in the design do not need to be checked for coverage. By default, initial blocks are considered for coverage. See Section 9.4, “Specifying What Not to Cover (Coverage Exclusions)”.
-ep [name] Causes any code that is inbetween inline coverage pragmas (eg. '// coverage off' ... '//coverage on') to be excluded from coverage consideration. The code specified between these pragmas is not removed from resimulation but is marked as being excluded from coverage for reporting purposes. These exclusions may be undone via the GUI, if necessary, without requiring the design to be resimulated by Covered. If name is specified, its value will be used by Covered as the pragma keyword to search for in the design (instead of the default value of 'coverage'). This feature can be useful in the event that other tools being used on the design use a similar pragma name and there are tool conflicts. See Section 9.4, “Specifying What Not to Cover (Coverage Exclusions)”.
-F module=[in_expr,]out_expr Specifies the location to find an FSM to score where module is the Verilog module containing the FSM, in_expr is the input state expression and out_expr is the output state expression. If in_expr is not specified, out_expr is used as both the input and output state expression.
-f filename Name of file containing additional arguments to parse. You may specify this option more than once on a command-line.
-fst dumpfile Name of FST dumpfile to score design with. If -vcd, -lxt or this option is not used, Covered will only create an initial CDD file from the design and will not attempt to score the design.
-g [module=](1|2|3) Specifies what generation of Verilog to use for parsing the design. If module is specified, uses the given generation value for that module only. If module is not specified, applies that generation to the entire design. This option may be specified multiple times on the command-line, where options to the left take precedence over the values to the right. 1=Verilog-1995, 2=Verilog-2001, 3=SystemVerilog.
-h Outputs usage information for the score command.
-I directory Directory to find included Verilog files. You may use this option as many times as necessary on the command-line, one for each directory.
-i instance Instance name of top-level module. Necessary if module to verify coverage is not the top-level module in the design. If not specified, -t value is used. See Section 9.3, “Specifying What to Cover”.
-lxt dumpfile Name of LXT2 dumpfile to score design with. If -vcd, -fst or this option is not used, Covered will only create an initial CDD file from the design and will not attempt to score the design.
-m message Allows the user to specify information about this CDD file. This information can be anything (messages with whitespace should be surrounded by double-quotation marks), but may include something about the simulation arguments to more easily link the CDD file to its simulation for purposes of recreating the CDD file.
-o filename Name of CDD to write coverage information to.
-p filename Overrides filename used for outputting intermediate preprocessor output. See Section 9.9, “Other Notes”.
-P parameter_scope=value Performs a defparam on the specified parameter with value. See Section 9.5, “Overriding Parameters (-P option)”.
-rS Performs race condition checking and removes any offending logic blocks from coverage consideration without reporting the information. See Section 4.2, “Race Condition Handling”.
-rW Performs race condition checking, removes any offending logic blocks from coverage consideration, and displays this information to standard output. This is the default race condition checking behavior. See Section 4.2, “Race Condition Handling”.
-rE Performs race condition checking, reports any offending logic and immediately stops scoring. This option allows Covered to be used as a static race condition checking tool. See Section 4.2, “Race Condition Handling”.
-rI[=module name] If =module name is not specified, race condition checking is not performed for the entire design. If =module name is specified, race condition checking is not performed on the specified module only. This option may be specified more than once. See Section 4.3, “Avoiding Race Condition Checking”.
-rP[=name] Skip race condition checking for all code surrounded by "// racecheck off/on" embedded pragmas. The "racecheck" keyword can be changed by specifying =name where name is the new name for the race condition pragma keyword. See Section 4.3, “Avoiding Race Condition Checking”.
-S Outputs simulation statistics after simulation has completed. This information is currently only useful for the developers of Covered.
-top_ts (1|10|100)(s|ms|us|ns|ps|fs)/(1|10|100)(s|ms|us|ns|ps|fs) This option is only valid when the -vpi or -dumpvars options have been specified. This option allows the user to specify a timescale for the generated Verilog module created with the -vpi or -dumpvars options. If this option is not specified, no timescale will be created for the generated module. If whitespace is needed between the various values, place the entire contents of timescale in double quotes.
-ts number When scoring occurs, this option allows the user to see how far the simulator has progressed by outputting the current timestep to standard output. The value of number specifies how many timesteps are allowed to be simulated before outputting the current timestep (results in less calls to output stream).
-T (min|typ|max) Specifies which value to use in min:typ:max delay expressions. Default is typ.
-v filename Name of specific Verilog file to score. You may specify this option more than once on a command-line; one for each filename to parse.
-vcd dumpfile Name of VCD dumpfile to score design with. If -lxt, -fst or this option is not used, Covered will only create an initial CDD file from the design and will not attempt to score the design.
-vpi [filename] If this option is specified without the -vcd, -lxt or -fst options, the design is parsed, a CDD file is created and a top-level Verilog module named filename (if this value is specified) or "covered_vpi.v" (if filename is not specified) is created along with a PLI table file called filename.tab or "covered_vpi.v.tab". Both of these files are used in the compilation of the simulator to use Covered as a VPI module. If either the -vcd, -lxt or -fst options are specified, this option has no effect. See the section called “Creating an LXT2 dumpfile”.
-Wignore Suppresses any warning output during code parsing and/or simulation.
-y directory Directory to find unspecified Verilog files. You may specify this option more than once on a command-line; one for each directory required.
+libext+.extension[+.extension]*+ Extensions of Verilog files to allow in scoring.


9.3. Specifying What to Cover

Covered is not a logic simulator and, therefore, is not required to parse the entire DUT. True simulation is performed by the Verilog simulator used to generate the VCD/LXT2/FST dumpfile. Covered, therefore, is given the ability to parse only the part of the DUT that is to be scored for coverage. Having this ability to ignore parts of the DUT has several advantages in the way of performance. Less memory is necessary for coverage simulation/ calculation. Additionally, less processing is also required which leads to faster turnaround. On the other hand, since Covered ignores the parts of the design not being scored, some information is not automatically extracted by Covered that is required for scoring the specified part of the DUT. The defparam statement is one such statement. More on this is mentioned in the following section.

The following example describes a complete DUT and how to cause Covered to score various parts of the DUT.

Figure 9.1. Hierarchical Tree View of Example DUT

Hierarchical Tree View of Example DUT


Assume that the following Verilog modules are used to create this tree.

  • module "test" instantiated as "test" in the above figure

  • module "foomod" instantiated as "foo"

  • module "barmod" instantiated as "bar"

  • module "amod" instantiated as "a"

  • module "bmod" instantiated as "b"

To get coverage for the entire design, the covered command line would be:

covered score -t test -i test (rest of command-line)

Because both the -t and -i options are the same value (the module name is the same as the instance name), only the -t option needs to be specified. If the -i option is not specified, Covered will assume that the instance name of the top module is the same name as the top module itself. Note that the -t option always needs to be specified for the score command.

To get coverage for the instance foo and all modules below it, the covered command line would be:

covered score -t foomod -i test.foo (rest of command-line)

In this case, we do not wish to score the module test (the top-level file for the design) but rather wish to gain coverage information for module foomod and all instantiated modules underneath it. Since foomod is not the top-level design file, the -i option must be specified to tell Covered what the hierarchical scope of the top-level score file is in relation to the entire design. The main reason why this is necessary is so that Covered will be able to locate the dumpfile information for the modules/instances that need to be scored.

To get coverage for only the instance foo (and none of the modules instantiated below it in the hierarchy), Covered command-line would look like the following:

covered score -t foomod -i test.foo -e amod -e bmod

Here we see the use of the -e option, it takes a module name as its value. When a module with the matching name is found in the hierarchy, it and all of its submodules are removed from coverage. You may specify as many -e arguments as necessary to select the appropriate modules to cover.

To get coverage for the instance foo and all modules below it, in addition to the instance bar, you would have to run Covered twice (once for each top instance).

The -vcd vcd_dumpfile, -lxt lxt_dumpfile or -fst fst_dumpfile parameter is simply the name of the VCD/LXT2/FST dumpfile that contains all of the module instances selected by the -t parameter (in combination with the -e option -- see below).

9.4. Specifying What Not to Cover (Coverage Exclusions)

Besides the -e option (scope exclusion), Covered comes equipped with several other means of excluding codes from coverage consideration. The -ea, - ec, -ei and -ef exclusion options cause Covered to not simulate always blocks, continuous assignment blocks, initial blocks and final blocks, respectively, allowing for additional score command performance enhancement opportunities. These options affect all code that is under coverage consideration for the current score command, and cannot be turned on/off on an individual basis.

Using the -ep Option for Exclusion

The -ep exclusion option allows Covered to exclude all code that has user-specified coverage pragmas embedded inline in the code being considered for coverage. By default, these pragmas look like the following:

Example 9.1. Inline Pragmas to Turn Coverage Exclusion On/Off

  module foo;

    // coverage off
    ...
    // coverage on

  endmodule;


Any registers, nets, variables, blocks, expressions, FSMs or assertions found within these pragmas within the design being parsed by Covered will be excluded from coverage consideration when the -ep option is specified. If the -ep option is not specified, these pragmas are ignored by Covered.

The code that is found between these pragmas is not removed from resimulation, however. Therefore, if the user decides that any code found within these pragmas needs to be considered, they may change the exclusion properties via the GUI without needing to rerun Covered's score command. Coverage numbers in generated reports will treat excluded code as though it has been hit (i.e., the coverage points will be a part of the total number and the hit counts will be increased as though these coverage points were hit during simulation).

The coverage pragmas may use either the single-line C++ comment style (//) or the multi-line C comment style (/* */). By default, the pragma is identified with the keyword 'coverage' following the comment characters. This value can be changed by the user, if needed, by specifying a string value to the right of the -ep option in the score command. This can be useful if there are other programs that use the same pragma keyword and causes conflicts with Covered's use of this pragma name. The value specified after the keyword is either 'off' (meaning that code should be excluded from coverage consideration after this comment) or 'on' (meaning that code should be considered for coverage after this comment). The values of 'off' and 'on' have the same meanings regardless of the pragma keyword so be sure to rename the pragma keyword to something that is appropriate.

Coverage pragmas may be embedded within each other, if desired. That is the following code example is allowed and handled properly by Covered' parser:

Example 9.2. Example of Embedded Coverage On/Off Pragmas

  module foobar;

    reg b, c, d, e;

    // coverage off

    wire a;

    // coverage off
    assign a = b & c;
    // coverage on

    assign e = ~d;
    // coverage on

  endmodule


The net effect of this example is that all code between the outer 'coverage off' and 'coverage on' pragmas are excluded from coverage.

One last note about the -ep option is that coverage exclusion is restricted on a per file basis. That is, if the user specifies a '// coverage off' pragma within a file and does not specify a '// coverage on' pragma later in the file, the next file to be parsed by Covered will be handled as if coverage is on. Coverage pragmas can, however, span across multiple modules or other entities within the same file.

9.5. Overriding Parameters (-P option)

The defparam statement can override any parameter specified in the DUT from any module in the DUT. Since parameter information is not typically specified in VCD/LXT2/FST dumpfiles, Covered needs to know about all parameter values at score time. Since all defparam statements are ignored by the Covered parser (even those in the DUT being scored), the user must inform Covered of any parameters that need to be overridden. This is accomplished with the -P option to the score command.

The first value in the -P option is the hierarchical reference to the parameter that needs to be overridden. The second value (following the '=' sign) specifies the value to assign the parameter to. This will override any default value assigned to that parameter. The user may not override the same parameter value twice on the command-line. Additionally, if the parameter is already being overridden in the design via an inline parameter override (parameter overrides specified in the '#(...)' part of the module instantiation).

As an example of how to override a parameter value on the score command-line, let's assume that there is a parameter called 'google' in the module called 'amod' used in the example in Section 9.3. The parameter definition in this module looks like the following:

parameter google = 4'hf;

To override this value to a new value of 18, use the following option in the score command:

-P test.foo.a.google=18

In this example, notice that we have not only changed the value of google, but we have also changed the bit-width of google from 4 bits to 32 bits (the size of an integer). This is considered legal behavior by Covered.

It is also possible to specify non-integer values to the parameter override option. Decimal, binary, octal and hexidecimal values may also be specified, using the same syntax as they are specified in Verilog. The following examples would also be other ways to override the value to 18. 

  -P test.foo.a.google=5'b10010
  -P test.foo.a.google=4'o22
  -P test.foo.a.google=12'h12
  -P test.foo.a.google='d18

In fact, you may specify any value (with the exception of real numbers) to override a parameter, including the following value types: 'x', 'X', 'z', 'Z', '_', '?'. This means that unknowns may be specified in a parameter. Note that this may generate user reported errors if parameters overridden to unknown values are used in mathematical equations or are used to specify the width of wires, regs, etc.

If a defparam statement is encountered in the DUT being scored, a warning message will be output to the user specifying that it has encountered a defparam statement. The defparam statement is ignored by Covered; however, if the parameter that it is overridding is used in the DUT being scored, the results of Covered may differ from actual simulation results. As such, please review all of these warning types to determine if the parameter should be overridden or not. If defparams are not parsed (seen by Covered), no such warning will be output. Please review the DUT for defparams which affect the DUT being scored.

9.6. Scoring FSMs

At this time Covered does not have the ability to automatically extract FSM information from the design. As a result, it is up to the user to specify FSM information for Covered to use in scoring FSMs. The ability to automatically extract FSM information is planned to be supported in the future; however, it is always a good idea to allow the user to specify and potentially override Covered's automatic extraction in the case where Covered either misses an FSM or incorrectly determines logic to be an FSM in cases where none exists. The information specified in this section describes how to tell Covered where an FSM exists within the design as of the current development version of Covered.

First, we need to make a few assumptions about the type of FSMs that Covered will be able to handle and, in the future, identify.

  1. The FSM is a synchronous design with edge-triggered flip-flops.

  2. There are no FSMs embedded in another FSM.

  3. The FSM is not a pipe-lined system.

  4. The entire FSM must exist within the same module.

  5. All state registers/variables must be less than 2^16 bits in width.

There is currently only one way, via the command-line, to specify to Covered where to find FSMs within the design. In the future, the inline Verilog-2001 "$attribute" function will be used to also allow the user to specify to Covered where an FSM is located. Using the command-line method, no changes need to be to source Verilog code for Covered's purposes.

To specify where an FSM exists within the design, the -F option must be specified to Covered's score command. Each -F option specifies one FSM within the design. Multiple -F options to the score command are allowed, allowing more than one FSM to be scored simultaneously. The -F option takes one argument that is subdivided into two or three parts:

-F module=(input_state_expression,)output_state_expression

The module specifies the Verilog module where the FSM state variables exist. The input_state_expression specifies the name of the variable(s) that represent the input state of the state machine. The output_state_expression specifies the name of the variable(s) that represent the output state of the state machine. Most FSMs have one variable as the input state (in most cases a registered version of the output state) such that the input variable is different than the output variable of the state machine. Specifying both variables in the -F option provides the user to more accurately specify to Covered the FSM. In the case that an FSM has the same variable for the input and output state, the user must specify only the output state variable (omitting the input_state_expression and comma character in the argument).

The input and output expression to the -F command can represent any signals, parts of signals, or combinations of signals. Constant values or parameters in the specification of the input/output expression is currently not supported (in fact, there are no future plans to support this behavior unless user-feedback demands it). The following examples show various legal ways to specify input/output expressions. The syntax is limited to what it shown in these examples.

-F foobar=a

Example 1 specifies that the entire vector called "a" should be considered both the input and output state variable.

-F foobar=a[2]

Example 2 specifies that bit 2 of the vector called "a" should be considered both the input and output state variable.

-F foobar=a[3:1]

Example 3 specifies that bits 3:1 of the vector called "a" should be considered both the input and output state variable.

-F foobar={a,b}

Example 4 specifies that vectors "a" and "b" should be concatenated to form the input/output state variable. Only one set of curly brackets may be used to specify a concatenated state expression; however, 2 or more signals may be specified within those brackets.

Any combination of the above four examples can be used to formalate the input state expression or the output state expression.

If the user specifies an FSM that Covered is not able to find (either the module was not included in the design that Covered is scoring or the FSM uses Verilog code that Covered is not able to handle), an error message is displayed to the user. It is then up to the user to determine if the FSM was incorrectly specified to Covered or otherwise. This warning is not considered to be a bug in Covered (unless of course, it can be proven that the FSM should have been found).

At the current time, Covered does not have the ability to extract the states and state transitions of the specified FSM from the design. Currently, it also doesn't have the ability to specify this information in other ways. To provide meaningful coverage information for the FSM, Covered outputs all hit states and state transitions in the report when all achievable states and state transitions are not known. This information will be able to be specified by the user in future versions of Covered, with the ability to automatically extract this information also in the works.

9.7. The reason for the -conservative feature

Though Covered has support for many Verilog-1995, Verilog-2001 and SystemVerilog constructs there are handful of supported constructs that are dependent on correct simulation ordering to provide accurate coverage information. In certain cases, Covered will be able to accurately determine the order of simulation, but in some cases, it may not. In these cases, it is best for Covered to run in a "conservative" mode of operation whereby logic blocks that contain these code issues are removed from coverage consideration. Removing logic blocks does not have a negative impact (in terms of coverage accuracy) on the rest of the design. The only negative consequence is that no coverage results can be obtained for a given logic block.

For example, consider the following code: 

  module main;
    foo a();
    bar b();
  endmodule

  module foo;
    integer a;
    initial begin
      #10;
      a = $random;
    end
  endmodule

  module bar
    integer a;
    initial begin
      #5;
      a = $random;
    end
  endmodule

If only module "foo" is chosen to gather coverage information, the call to the $random function will result in a value that will not match the actual simulation if the -conservative option is not specified. This is due to the ordering importance of $random system task calls. The first call to $random will return a value of X while the second call will return a value of Y. If we remove the code that calls $random the first time, the code that still calls X will receive the incorrect value. This discrepancy in simulation results will result in incorrect coverage results.

If the -conservative option is specified to the score command, Covered will automatically remove any coverage blocks that make a call to the $random system function from coverage consideration and any assigned values within these removed blocks will get their value from the dumpfile instead of being calculated by Covered directly. This will result in correct coverage information for the module "foo".

The constructs that can cause issues with Covered simulation correctness (in some situations) are the following:

  1. $random

  2. $urandom

  3. $urandom_range

It is currently up to the user to determine whether liberal or conservative coverage accumulation should occur and use the -conservative option to the score command as needed.

9.8. Specifying Plus Arguments When Scoring

Covered supports the $test$plusargs and $value$plusargs system function calls and, as such, runtime command-line options are allowed to be specified when scoring the design. To specify plusargs to the score command, simply specify them anywhere after the score command keyword just as you would specify them to a simulator. Any plusargs specified to the score command which are not recognized for compilation purposes are used for $test$plusargs and $value$plusargs comparisons,

Note that specifying plusargs to the score command is only necessary when the score command is given either the -vcd, -lxt or -fst options. If the VPI method of coverage scoring is used, specify the plusargs to the simulation runtime as required. Covered will automatically extract the plusargs from the simulator runtime for its purposes.

9.9. Other Notes

When the Verilog files are parsed, a preprocessor is run on each file that is to be read in by Covered. The preprocessor generates an intermediate form of each file, resolving defined values and included files. The intermediate form is output to a file which is called "tmpXXXXXX" where XXXXXX represents some alphanumeric sequence chosen by the OS via the mkstemp() function. The file is guaranteed to be unique to all other files in the directory and it is automatically removed by Covered when parsing is completed.

If the user does not want Covered to use this naming convention for specifying this file, the user may use the -p option (see Options section above) to override the default name. Covered will then use this filename instead of generating a unique name. Make sure that the file specified does not contain any useful data since Covered will overwrite this file when the score command is run.

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Chapter 7. Getting Started

Table of Contents

7.1. Methods for scoring the design
Post-processing VCD/LXT2/FST dumpfiles
Co-processing VCD/LXT2/FST dumpfiles via FIFO
Using the VPI interface to gather coverage information
7.2. What is needed for dumpfile scoring?
Selecting What to Dump
Creating a VCD dumpfile
Creating an LXT2 dumpfile
Creating an FST dumpfile
7.3. What is needed for VPI scoring?
Compiling for Icarus Verilog
Compiling for Cver
Compiling for VCS
Compiling for NC-Verilog

7.1. Methods for scoring the design

Before you are ready to being scoring, merging and generating coverage reports from the design, you will first need to decide whether you want to post-process VCD/LXT2/FST -formatted dumpfiles generated from simulation, co-process VCD/LXT2/FST -formatted dumpfiles using two processes (one for the simulation process and one for the Covered process) and a Unix FIFO, or whether you want to accummulate coverage information alongside the simulator using the simulator's VPI interface. There are advantages and disadvantages to these methods, so select the method that will best work for you.

Post-processing VCD/LXT2/FST dumpfiles

Generating post-process coverage information from VCD/LXT2/FST -formatted dumpfiles requires three steps:

  1. Compile the simulator to dump in the specified format.

  2. Run the simulation.

  3. Run Covered's score command using the dumpfile as input along with the design.

Performing these steps will generate the needed CDD file that can be used for merging or reporting. The advantages to this approach is that the steps are fairly simple and are compiler/simulator -independent. However, there are two main drawbacks. First, compiling with dumping enabled often slows simulation by some significant factor. Second, the dumpfiles generated from simulation can often be quite large (especially for VCD dumping), consuming a lot of disk space. Additionally, if your simulator dumps in a format different from VCD, LXT2 or FST, you will need to perform an additional step in transforming the original dumpfile into one of these formats. This is often a time-consuming task if the design and/or dumpfile is significantly large. If you are generating lots of dumpfiles for coverage (say from running a regression), the amount of disk space needed to store these files can be tremendous, making this approach almost not feasible.

Co-processing VCD/LXT2/FST dumpfiles via FIFO

Generating co-process coverage information from VCD/LXT2/FST -formatted dumpfiles requires four steps:

  1. Compile the simulator to dump in the specified format.

  2. Create a Unix FIFO via the mkfifo fifoname command.

  3. Create an empty CDD file for the design using Covered's score command.

  4. Run the simulation and Covered's score command simultaneously. The following is an example of a testbench and command-line commands:

    Example 7.1. Running Covered Alongside a Simulation Process Using a Unix FIFO to Pass Dumpfile Information

      # Module listing for file "test.v"
  module tb;
    ...
    initial begin
            $dumpfile( "dump_fifo" );
            $dumpvars( 0, tb );
            ...
    end
    ...
  endmodule

  # Command-line output
  > mkfifo dump_fifo
  > vcs test.v
  > covered score -t tb -v test.v -o test.cdd
  > ./simv &
  > covered score -cdd test.cdd -vcd dump_fifo


The end result of these steps is the same CDD file that results from using the dumpfile method described above. The primary advantages of this approach are that no dumpfiles are actually created, saving on disk space, and it does not significantly slow down the simulation process. Because both simulation and coverage scoring occur simultaneously, there should be a wall clock time improvement with this method.

The drawbacks of this approach are basically that the time improvement won't be significant if you are running on a single processor/core system and that it is restricted to machines that support the Unix fifo (this may not be an actual restriction, however).

Using the VPI interface to gather coverage information

Generating coverage information using the VPI interface of the simulator requires three main steps:

  1. Create a base CDD file from the design along with a top-level Verilog module and PLI table file (this second file is needed for the commercial VCS compiler).

  2. Compile the simulator using the Covered VPI module (or shared object).

  3. Run the simulation.

The end result of these steps is the same CDD file that results from using the dumpfile method described above. The primary advantage of this approach is that no dumpfiles are required, saving on disk space and dumpfile processing time. The drawbacks of this approach are the following:

  1. Simulation runs much slower using the VPI and Covered (most likely slower than creating dumpfiles from the simulator).

  2. Covered VPI modules are only available for certain compilers (Icarus Verilog, Cver and VCS currently); however, adding support for other compilers should not be a difficult thing to do.

  3. The VPI modules will only work for compilers that support the VPI interface (a Verilog-2001 feature).

7.2. What is needed for dumpfile scoring?

Before Covered can be invoked for dumpfile scoring, you must have a simulatable Verilog design and a VCD, LXT2 or FST dumpfile containing information from a simulation run of the design that dumps the module(s) that you want to check for coverage. The VCD dumpfile style was chosen due to its universal support by Verilog simulators while the LXT2 and FST dumpfile styles were chosen due to their compactness and growing support by other open source simulators and dumpfile readers. Once you have these two parts, you are ready to begin generating coverage results.

Selecting What to Dump

If coverage is being scored via a VCD/LXT2/FST dumpfile, it is necessary for the user to setup $dumpfile and $dumpvars calls to dump the various modules that are being scored. Covered allows the user to do this in one of two ways.

First, the user may hand create these calls within their testbench. If this approach is taken, it is necessary that all modules being scored by Covered be included in the $dumpvars calls. Eliminating scored modules from the dumpfile will result in inaccurate coverage information. Additionally, it is mandatory that the dumpfile start at time 0 and that all dump information be included in the dumpfile (i.e., using the $dumplimit system task could cause dump information to be lost that will result in inaccurate coverage results).

Second, the user may take advantage of Covered's -dumpvars option to the score command. Adding this parameter (and the optional -top_ts option) will create a top-level module file that can be compiled along with the testbench that will dump all of the parts of the Covered design that are needed by Covered. Using this approach will result in the best overall performance for dumpfile coverage accumulation as all unnecessary dump information will be stripped, resulting in both faster simulation and faster coverage scoring.

If the second approach is taken, simply use the score command to parse the design and output an unscored CDD and the dumpvars module, using a command similar to the following: 

  covered score -t top -v dut.v -dumpvars dut_dump.v -o dut.cdd

If `timescale is specified at the top of dut.v, it may be necessary for compiling purposes to have the timescale specified at the top of dut_dump.v. To do this, simply specify the -top_ts option in the score command. Note that the example command does not list either the -vcd, -lxt or -fst options. If either of these options are present on the score command-line, the dut_dump.v file will not be created and the score command will attempt to score the design with the specified dumpfile.

After the dut_dump.v file has been created, simply compile it along with your DUT as a top-level module. For example, 

  iverilog dut.v dut_dump.v

After the simulation has been compiled and run, a dumpfile called "dut_dump.vcd" (using the above example) will exist in the run directory. This dumpfile can then be used in a second call to the score command via the -vcd, -lxt or -fst options along with the unscored CDD file to create a scored version of the CDD file.

Creating a VCD dumpfile

By default, the $dumpfile system task call will create a file and populate it with VCD-style dumpfile information. Simply use the resulting VCD dumpfile in the -vcd option to the score command to obtain coverage for that design.

Creating an LXT2 dumpfile

An LXT2 dumpfile can be created in several different ways depending on the Verilog simulation tool that you are using. If you are using the Icarus Verilog open source simulator, you can simply generate an LXT2-style dumpfile by specifying the -lxt2 option to the simulator command-line. For example, if you had a file called "foo.v" that contained the same $dumpfile and $dumpvars commands used for VCD dumping and compiled it with Icarus Verilog into a VVP file called "a.out", you could cause Icarus Verilog to generate an LXT2 dumpfile (instead of a VCD dumpfile) by calling "vvp a.out -lxt2". This will cause an LXT2 style dumpfile instead of the standard VCD style dumpfile.

You can also transform many different dumpfile formats into an LXT2 style dumpfile with the helper programs that come with the GtkWave waveform viewer.

Creating an FST dumpfile

An FST dumpfile can be created in several different ways depending on the Verilog simulation tool that you are using. If you are using the Icarus Verilog open source simulator, you can simply generate an FST-style dumpfile by specifying the -fst option to the simulator command-line. For example, if you had a file called "foo.v" that contained the same $dumpfile and $dumpvars commands used for VCD dumping and compiled it with Icarus Verilog into a VVP file called "a.out", you could cause Icarus Verilog to generate an FST dumpfile (instead of a VCD dumpfile) by calling "vvp a.out -fst". This will cause an FST style dumpfile instead of the standard VCD style dumpfile.

You can also transform many different dumpfile formats into an FST style dumpfile with the helper programs that come with the GtkWave waveform viewer.

7.3. What is needed for VPI scoring?

After Covered has been configured and built to include the creation of a VPI loadable module or shared object file (see Section 6.3, “Configuring the build” for details), Covered is capable of scoring during a simulation run by using the VPI (Verilog Procedural Interface) access mechanism. This is done by loading the Covered VPI module (or shared object) into the simulator executable prior to running (depending on the simulator being used). The following steps should be taken to create a scored CDD file using this method.

  1. Create the Verilog file that will be compiled as a top-level module in the design (alongside the actual top-level(s)).

    This is done by running the score command with the -vpi option. The following example command-line shows how this step is done, creating a file called "covered_vpi.v".

    > covered score -t top -vpi

  2. Compile the simulator executable, including the previously generated file and the Covered VPI module. See the compile instructions for the Icarus Verilog, Cver or VCS simulators below.

  3. Run the simulation. Once simulation is complete, the resulting CDD file will be a completely scored database, ready to be merged with other CDD files from the same design or reported on.

Compiling for Icarus Verilog

If you are compiling an Icarus Verilog simulation, simply add -m tool_install_root/libexec/covered.vpi covered_vpi.v to the command-line.

Compiling for Cver

If you are compiling a Cver simulation, simply add +loadvpi=tool_install_root/libexec/covered.cver.so:vpi_compat_bootstrap covered_vpi.v to the command-line.

Compiling for VCS

If you are compiling a VCS simulation, simply add +vpi -load tool_install_root/libexec/covered.vcs.so:covered_register covered_vpi.v to the command-line.

Compiling for NC-Verilog

If you are compiling a NC-Verilog simulation, switch to NC-Verilog's irun command to load the covered shared object: -loadvpi tool_install_root/libexec/covered.ncv.so:covered_register and enable all access with -access +rwc.

You can hardcode the $covered_sim call into your RTL or you can run it dynamically using the CLI, by adding the -input input.tcl switch to irun. Where the input.tcl file looks like the following and tb.dut is the coverage instance: 

        call -systf {$covered_sim} {"scored.cdd"} tb.dut
        run

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Chapter 8. Using Covered

Table of Contents

8.1. Work Flow
Scoring the Design
Merging CDDs
Creating Coverage Reports
Ranking CDDs
Excluding CDD Coverage Points
8.2. Covered usage
8.3. Covered global options

8.1. Work Flow

Covered has four basic commands that it uses for gaining coverage information about a design and displaying that information to the user.

  • score

  • merge

  • report

  • rank

Scoring the Design

To begin using Covered, you will need to create a special database file called a coverage description database (CDD). Covered uses this file to store coverage-specific information about the DUT. This file is a text-based file that is written in a specific format (the format of this file is not discussed in this document but can be found in the developer's document) that Covered understands.

To create the CDD and populate it with the simulation dumpfile results, you must use the score (see Chapter 9, The score Command for details) command. This command parses in the DUT files and generates an initial CDD for the design. This CDD does not contain any coverage details but only the design elements that Covered needs to gain coverage results.

Once the initial CDD has been created, the score command reads in the specified VCD/LXT2 dumpfile from the given DUT. If Covered recognizes that the VCD/LXT2 dumpfile does not correspond to the DUT that it parses (dumpfile was not generated from the DUT specified), an error message is supplied to the user telling them this. Once the dumpfile has been parsed, Covered generates a new version of the CDD containing a populated database. This CDD may be merged with another CDD from the same DUT and/or reports may be generated from this CDD.

Merging CDDs

When two or more CDDs have been generated from the same DUT. It is often desirable to merge their contents to see what the total coverage is for both simulation runs. The reasons why merging is desirable is that often several tests are written to exercise the entire design (not just one). This makes tests easier to write and maintain. Since, typically, only one test is run per simulation run and that test does not fully test the DUT, it is necessary to combine the results of the multiple simulations to the see the combined effect of the tests on the design. This is where merging comes into play.

Merging multiple CDDs from the same design is easy with Covered, and is accomplished with the merge (see Chapter 10, The merge Command for details) command. This command reads in two or more CDDs, merges their results and outputs the merged CDD to a different file or replaces the first CDD with the results of the merge.

Creating Coverage Reports

After a CDD is created or merged, the contents of the CDD can be extracted and transformed into human-readable coverage reports with the report (see Chapter 11, The report Command for details) command. A summary report containing the percentage of metrics covered is generated for each module. Additionally, to aid in understanding what and why something was not covered, a verbose reporting mechanism exists. Verbose reporting will explicitly point to and describe why something was not fully covered for a specific metric.

Reports are text-based output that by default are directed toward standard output but may, with the use of an option flag, be output to a specific file for storage purposes.

Ranking CDDs

After a collection of CDDs have been generated from a single design (most likely due to a regression run), it is desirable to know which CDDs have an effect on coverage and which CDDs do not add any new coverage information. The CDDs that do not provide additional coverage may be unnecessary for regression and removing them may significantly improve a regression runs time (which can help in a projects schedule).

Additionally, it also good to know an order that simulations should be run in to produce the maximum amount of coverage the quickest. This information can be useful for creating a quick (or "sanity check" or "confidence") regression that runs in a relatively short period of time and, when run successfully, provides the engineer a level of confidence that recent changes have not severely broke the functionality of the design.

This is the purpose of the rank (see Chapter 12, The rank Command for details) command. It produces a report that shows the diagnostics that add to the overall coverage of the suite, the order that those diagnostics should run, and each diagnostic's overall effect on coverage when it is run.

Excluding CDD Coverage Points

Not all unhit coverage points reported by Covered will be valid for your design. Some coverage points may be extraneous, some may be due to obsolete logic that is not pulled from the design for various reasons, and some coverage points may be hit in other verification environments but not in the current environment.

Whatever the reason may be (and some reasons may be much more specific that these suggestions), Covered allows the user to exclude those coverage points from coverage reporting (they will still be reported but they will be considered "covered" points instead of "uncovered" points). Additionally, each excluded coverage point can have an option message attached to it that explains the reason for exclusion. This message is stored with the coverage information in the CDD file and can be displayed in a standard coverage report or in a stand-alone exclusion report. This information helps to document the coverage analysis process.

In addition to being able to exclude coverage points, the user can also include previously excluded coverage points (in the event that a mistake was made or if the design has changed). Coverage exclusion can be accomplished via the command-line exclude command or within the GUI coverage analyzer.

8.2. Covered usage

Covered is initiated with the following command:

covered (-h | -v | [-P [filename]] [-B] [-D|-T|-Q]) (score|merge|report|rank) command_options)

The -v command (described below) is mutually exclusive from the rest of the commands and has the highest priority. If Covered is called with this option and any other options, the version will only be displayed.

The -h command (described below) is mutually exclusive from the rest of the commands and has the second highest priority. If Covered is called with this option and the -v option is not specified, the usage information will be displayed to the screen.

The -Q option suppresses all normal user output from standard output. The only output that will not be suppressed are messages to standard error. This option may be used with any of the Covered commands to achieve this effect. By default, normal user output is sent to standard output.

The -T option suppresses all normal user output from standard output with the exception of the Covered header banner, warning messages. This type of output is a bit more informative than output generated with the -Q option but not as much as running without any output limiters.

The -D option outputs debug information to standard output. Its effect overrides the -Q option. This option may be used in conjunction with any other Covered command for the purposes of debugging tool failures. By default, debug mode is turned off and must be enabled in the build of Covered (using the --enable-debug option to configure). This command should only be used for debugging as it generates an immense amount of output which may hinder performance.

The -B option obfuscates all design-sensitive signal, module, task, function, instance, file and parameter names when outputting them to either stdout, stderr or a file (with the exception of CDD file output). This mode is intended to be used for sharing output information with others (including the developer's of Covered) which is sensitive information for the purposes of debugging.

The -P option causes Covered to enable internal code profiling and generates a profiling report that is output to either the given filename or the default filename of "covered.prof". This option is only available if the --enable-profiling configuration option is specified and will cause performance degradation. This option should only be used by Covered developers or those interested in finding performance bottlenecks in Covered's code. It is not recommended that the --enable-profiling configuration option and the -P global option be specified for normal users of Covered. See Section 15.3, “Source Code Profiling” for more information on profiling and understanding the profiling report file.

8.3. Covered global options

The following table describes options that Covered will accept apart from its normal commands which are described in the next several chapters.

Table 8.1. Global Options to Covered

Option Description
-Q Quiet mode. Suppresses user output to screen. Use in conjunction with a command.
-T Terse mode. Causes all output to be suppressed with the exception of warning messages and the Covered header information. Use in conjunction with a command.
-D Debug mode. Outputs code debug information to screen. Use in conjunction with commands.
-B Obfuscate. Obfuscates all design sensitive names before outputting them.
-P [filename] Profiling mode. Outputs profiling report to either the given filename or "covered.prof" if no filename was specified.
-h Generates usage output to standard output.
-v Outputs current version of Covered.

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Covered User's Guide - 0.7.9
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Covered User's Guide - 0.7.9

Verilog Code Coverage Analyzer

Trevor Williams


          
        

Copyright © 2008-2010 Trevor Williams

Table of Contents

I. Overview
1. Introduction
2. Coverage Metrics
3. Coverage Boundaries
4. Race Condition Checking
5. Inline Attributes
II. Installation
6. Installation
III. Command-line Usage
7. Getting Started
8. Using Covered
9. The score Command
10. The merge Command
11. The report Command
12. The rank Command
13. The exclude Command
14. Reading the Report
15. Debugging
IV. Graphical User Interface
16. Introduction to the GUI
17. Navigating the Main Window
18. Navigating the Line Coverage Window
19. Navigating the Toggle Coverage Window
20. Navigating the Memory Coverage Window
21. Navigating the Combinational Logic Window
22. Navigating the FSM State/State Transition Coverage Window
23. Navigating the Assertion Coverage Window
24. Navigating the Assertion Source Code Window
25. Creating a New CDD
26. Creating an ASCII report file
27. Creating a CDD Ranking Report
28. Navigating the Preferences Window
29. The Exclusion Reason Popup Window
30. Navigating the Wizard Window
V. FAQ
31. FAQ
VI. Epilogue
32. Epilogue

List of Figures

2.1. Digraph Version of Example FSM
9.1. Hierarchical Tree View of Example DUT
10.1. Example of Verilog hierarchy to be scored in parallel
17.1. Covered Main Window
17.2. Covered Main Window Highlighting the Menu Bar
17.3. The File Menu
17.4. The CDD Opened File Viewer
17.5. The Close Warning Window
17.6. The Generate Menu List
17.7. The Exit Warning Window
17.8. The Report Menu
17.9. The View Menu
17.10. The Help Menu
17.11. Covered Main Coverage Type View Bar
17.12. Populated Module/Instance Selection Box
17.13. Covered Main Coverage File Viewer
17.14. Covered Main Information Bar
18.1. Example of uncovered line included for line coverage consideration
18.2. Example of uncovered line excluded for line coverage consideration
19.1. Verbose Toggle Window
20.1. Verbose Memory Window
21.1. Example of the verbose combinational logic window
21.2. Example Coverage Output for an Uncovered Event Subexpression
21.3. Example Coverage Output for an Uncovered Unary Subexpression
21.4. Example Coverage Output for an Uncovered Simple AND-type Combinational Subexpression
21.5. Example Coverage Output for an Uncovered Simple OR-type Combinational Subexpression
21.6. Example Coverage Output for an Uncovered Simple Combinational Subexpression
21.7. Example Coverage Output for an Uncovered Complex Combinational Subexpression
21.8. Example of an excluded subexpression
22.1. Verbose FSM Coverage Window
22.2. Example of excluded state transitions
23.1. Verbose Assertion Coverage Window
23.2. Example of excluded ACP
24.1. Assertion Source Viewer Window
25.1. CDD Creation Option Selection Page
25.2. CDD Creation Output Name Page
25.3. CDD Creation Type Page
25.4. CDD Creation Options1 Page
25.5. CDD Creation Options2 Page
25.6. CDD Creation Insert Menubutton
25.7. CDD Creation Library Extension Window
25.8. CDD Creation Define Window
25.9. CDD Creation Parameter Override Window
25.10. CDD Creation FSM Specification Window
25.11. CDD Creation Module Generation Window
25.12. CDD Creation Module Exclusion Window
25.13. CDD Creation Output Window
26.1. Report Generation Option Selection Page
26.2. Report Generation Options Page
27.1. CDD Ranking Option Selection Page
27.2. CDD Ranking Options Page
27.3. CDD Ranking Input File Selection Page
27.4. CDD Ranking Command Output Page
27.5. CDD Ranking Report Page
28.1. Main Preferences Window
28.2. Coverage Goals Window
28.3. Syntax Highlighting Preferences Pane
28.4. Exclusion Preferences Pane
28.5. Merging Preferences Pane
29.1. The Exclusion Reason Popup Window
29.2. Full View of the Exclusion Reason Popup Window
30.1. Covered GUI Wizard Window

List of Tables

8.1. Global Options to Covered
9.1. Options to score Command
10.1. Options to merge Command
10.2.
11.1. Options to report Command
12.1. Options to rank Command
13.1. Options to the exclude command
15.1. CLI Command-line Options
28.1. Location of Written .coveredrc File According to the Location of Read .coveredrc File

List of Examples

2.1. Line Coverage Code Sample
2.2. Toggle Coverage Code Sample
2.3. Memory Coverage Code Sample
2.4. Combinational Logic Coverage Code Sample
2.5. FSM Coverage Code Sample
4.1. Using a Race Condition Pragma
5.1. Module Containing an Embedded FSM
5.2. FSM Attribute Code Sample
7.1. Running Covered Alongside a Simulation Process Using a Unix FIFO to Pass Dumpfile Information
9.1. Inline Pragmas to Turn Coverage Exclusion On/Off
9.2. Example of Embedded Coverage On/Off Pragmas
12.1. Rank Output With No Required Files
12.2. Rank Output With Required Files
18.1. Line Coverage Example
   Next
   Part I. Overview
covered-0.7.10/doc/html/part.command.line.usage.html0000644000076500007650000001665211426534466022302 0ustar trevorwtrevorwPart III. Command-line Usage
Part III. Command-line Usage
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Part III. Command-line Usage

Table of Contents

7. Getting Started
7.1. Methods for scoring the design
7.2. What is needed for dumpfile scoring?
7.3. What is needed for VPI scoring?
8. Using Covered
8.1. Work Flow
8.2. Covered usage
8.3. Covered global options
9. The score Command
9.1. Usage
9.2. Options
9.3. Specifying What to Cover
9.4. Specifying What Not to Cover (Coverage Exclusions)
9.5. Overriding Parameters (-P option)
9.6. Scoring FSMs
9.7. The reason for the -conservative feature
9.8. Specifying Plus Arguments When Scoring
9.9. Other Notes
10. The merge Command
10.1. Usage
10.2. Options
10.3. Merging Rules
11. The report Command
11.1. Usage
11.2. Options
11.3. Summary Vs. Detailed Vs. Verbose
11.4. Module Vs. Instance
11.5. Covered Vs. Uncovered
12. The rank Command
12.1. Options
12.2. Methods for specifying CDDs to rank
12.3. Specifying metric weights
12.4. Understanding the rank command output information
12.5. Description of ranking algorithm
13. The exclude Command
13.1. Usage
13.2. Options
14. Reading the Report
14.1. Reading Line Coverage
14.2. Reading Toggle Coverage
14.3. Reading Memory Coverage
14.4. Reading Combinational Logic Coverage
14.5. Reading FSM Coverage
14.6. Reading Assertion Coverage
15. Debugging
15.1. Verbose Debug Output
15.2. Command-Line Interface (CLI)
15.3. Source Code Profiling
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Chapter 6. Installation Home Chapter 7. Getting Started
covered-0.7.10/doc/html/part.epilogue.html0000644000076500007650000000523411426534466020436 0ustar trevorwtrevorwPart VI. Epilogue
Part VI. Epilogue
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Part VI. Epilogue

Table of Contents

32. Epilogue
32.1. Author
32.2. Special Thanks
32.3. Reporting Bugs
32.4. Mailing List
32.5. Homepage
32.6. Copyright and Licensing
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Chapter 31. FAQ Home Chapter 32. Epilogue
covered-0.7.10/doc/html/part.faq.html0000644000076500007650000000377511426534466017404 0ustar trevorwtrevorwPart V. FAQ
Part V. FAQ
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Part V. FAQ

Table of Contents

31. FAQ
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Chapter 30. Navigating the Wizard Window Home Chapter 31. FAQ
covered-0.7.10/doc/html/part.gui.html0000644000076500007650000002374211426534466017415 0ustar trevorwtrevorwPart IV. Graphical User Interface
Part IV. Graphical User Interface
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Part IV. Graphical User Interface

Table of Contents

16. Introduction to the GUI
17. Navigating the Main Window
17.1. The Main Menu Bar
17.2. The Coverage Type View Bar
17.3. The Module/Instance Listbox
17.4. The Coverage File Viewer
17.5. The Information Bar
18. Navigating the Line Coverage Window
18.1. Viewing Uncovered Lines
18.2. Excluding/Included Uncovered Lines from Line Coverage
18.3. Viewing Covered Lines
19. Navigating the Toggle Coverage Window
19.1. Understanding the Layout
19.2. Excluding/Including a Signal for Toggle Coverage
19.3. Displaying a New Signal for Toggle Coverage
20. Navigating the Memory Coverage Window
20.1. Understanding the Layout
20.2. Excluding/Including a Memory for Memory Coverage
20.3. Displaying a New Memory for Memory Coverage
21. Navigating the Combinational Logic Window
21.1. Navigating a Statement
21.2. Understanding the Coverage Information
21.3. Excluding/Including a Subexpression
21.4. Displaying a New Statement
22. Navigating the FSM State/State Transition Coverage Window
22.1. Navigating the FSM Window
22.2. Excluding/Including a State Transition
22.3. Displaying a New FSM
23. Navigating the Assertion Coverage Window
23.1. Navigating the Assertion Coverage Window
23.2. Excluding/Including Assertion Coverage Points
23.3. Displaying a New Assertion Instance
24. Navigating the Assertion Source Code Window
24.1. Navigating the Source Code
25. Creating a New CDD
25.1. Navigating the New CDD Creation Option Selection Page
25.2. Navigating the New CDD Creation CDD Name Page
25.3. CDD Creation Type Page
25.4. CDD Creation Options1 Page
25.5. CDD Creation Options2 Page
25.6. CDD Creation Output Pane
26. Creating an ASCII report file
26.1. Navigating the Report Generator Selection Page
26.2. Report Generation Options Page
27. Creating a CDD Ranking Report
27.1. CDD Ranking Option Selection Page
27.2. CDD Ranking Option Page
27.3. CDD Ranking Input File Selection Page
27.4. CDD ranking Command Output Page
28. Navigating the Preferences Window
28.1. Option Categories
28.2. Preference Buttons
28.3. Preferences Configuration File
28.4. Preferences General Pane
28.5. Preferences Color Pane
28.6. Preference Coverage Goals Pane
28.7. Preferences Syntax Highlighting Pane
28.8. Preferences Exclusion Pane
28.9. Preference Merging Pane
29. The Exclusion Reason Popup Window
30. Navigating the Wizard Window
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Chapter 15. Debugging Home Chapter 16. Introduction to the GUI
covered-0.7.10/doc/html/part.installation.html0000644000076500007650000000513011426534466021321 0ustar trevorwtrevorwPart II. Installation
Part II. Installation
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Part II. Installation

Table of Contents

6. Installation
6.1. Prerequisites
6.2. Downloading source
6.3. Configuring the build
6.4. Compiling and Installing
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Chapter 5. Inline Attributes Home Chapter 6. Installation
covered-0.7.10/doc/html/part.overview.html0000644000076500007650000001177511426534466020502 0ustar trevorwtrevorwPart I. Overview
Part I. Overview
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Part I. Overview

Table of Contents

1. Introduction
1.1. What is Covered?
1.2. What can code coverage do?
1.3. What can't code coverage do?
1.4. What does Covered do?
1.5. What does Covered NOT do?
1.6. What makes Covered different?
2. Coverage Metrics
2.1. Line Coverage
2.2. Toggle Coverage
2.3. Memory Coverage
2.4. Combinational Logic Coverage
2.5. Finite State Machine (FSM) Coverage
2.6. Assertion Coverage
3. Coverage Boundaries
3.1. What logic can be analyzed?
3.2. What logic cannot be currently analyzed?
3.3. What is done with code blocks that contain code that cannot be analyzed?
4. Race Condition Checking
4.1. Checked Coding Guidelines
4.2. Race Condition Handling
4.3. Avoiding Race Condition Checking
4.4. Reporting Race Conditions
5. Inline Attributes
5.1. What are inline attributes?
5.2. Adding FSM attributes
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Covered User's Guide - 0.7.9 Home Chapter 1. Introduction
covered-0.7.10/doc/html/test/0000755000076500007650000000000011475644632015746 5ustar trevorwtrevorwcovered-0.7.10/doc/html/test/example.rptI.html0000644000076500007650000010244211052400252021162 0ustar trevorwtrevorw

      1                               ::::::::::::::::::::::::::::::::::::::::::::::::::
      2                               ::                                              ::
      3                               ::  Covered -- Verilog Coverage Verbose Report  ::
      4                               ::                                              ::
      5                               ::::::::::::::::::::::::::::::::::::::::::::::::::
      6  
      7  
      8  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      9  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   GENERAL INFORMATION   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     10  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     11  * Report generated from CDD file : cov.cdd
     12  
     13  * Reported by                    : Instance
     14  
     15  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     16  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   LINE COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     17  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     18  Instance                                           Hit/ Miss/Total    Percent hit
     19  ---------------------------------------------------------------------------------------------------------------------
     20    $root                                              0/    0/    0      100%
     21    main                                               6/    1/    7       86%
     22    main.fsm1                                          4/    0/    4      100%
     23    main.fsm2                                          3/    1/    4       75%
     24  ---------------------------------------------------------------------------------------------------------------------
     25  
     26      Module: main, File: example.v, Instance: main
     27      -------------------------------------------------------------------------------------------------------------
     28      Missed Lines
     29  
     30             22:    err_cnt = (err_cnt + 1)
     31  
     32  
     33      Module: fsmb, File: example.v, Instance: main.fsm2
     34      -------------------------------------------------------------------------------------------------------------
     35      Missed Lines
     36  
     37             92:    next_state = 3'b1
     38  
     39  
     40  
     41  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     42  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   TOGGLE COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     43  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     44  Instance                                                   Toggle 0 -> 1                       Toggle 1 -> 0
     45                                                     Hit/ Miss/Total    Percent hit      Hit/ Miss/Total    Percent hit
     46  ---------------------------------------------------------------------------------------------------------------------
     47    $root                                              0/    0/    0      100%             0/    0/    0      100%
     48    main                                               4/    6/   10       40%             3/    7/   10       30%
     49    main.fsm1                                          5/    3/    8       62%             4/    4/    8       50%
     50    main.fsm2                                          4/    4/    8       50%             3/    5/    8       38%
     51  ---------------------------------------------------------------------------------------------------------------------
     52  
     53      Module: main, File: example.v, Instance: main
     54      -------------------------------------------------------------------------------------------------------------
     55      Signals not getting 100% toggle coverage
     56  
     57        Signal                    Toggle
     58        ---------------------------------------------------------------------------------------------------------
     59        go                        0->1: 1'h1
     60        ......................... 1->0: 1'h0 ...
     61        state                     0->1: 3'h3
     62        ......................... 1->0: 3'h5 ...
     63        err_cnt                   0->1: 5'h00
     64        ......................... 1->0: 5'h00 ...
     65  
     66      Module: fsma, File: example.v, Instance: main.fsm1
     67      -------------------------------------------------------------------------------------------------------------
     68      Signals not getting 100% toggle coverage
     69  
     70        Signal                    Toggle
     71        ---------------------------------------------------------------------------------------------------------
     72        go                        0->1: 1'h1
     73        ......................... 1->0: 1'h0 ...
     74        state                     0->1: 3'h3
     75        ......................... 1->0: 3'h5 ...
     76        next_state                0->1: 3'h2
     77        ......................... 1->0: 3'h1 ...
     78  
     79      Module: fsmb, File: example.v, Instance: main.fsm2
     80      -------------------------------------------------------------------------------------------------------------
     81      Signals not getting 100% toggle coverage
     82  
     83        Signal                    Toggle
     84        ---------------------------------------------------------------------------------------------------------
     85        go                        0->1: 1'h1
     86        ......................... 1->0: 1'h0 ...
     87        next_state                0->1: 3'h2
     88        ......................... 1->0: 3'h1 ...
     89        state                     0->1: 3'h2
     90        ......................... 1->0: 3'h1 ...
     91  
     92  
     93  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     94  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   MEMORY COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     95  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     96                                                             Toggle 0 -> 1                       Toggle 1 -> 0
     97  Instance                                           Hit/ Miss/Total    Percent hit      Hit/ Miss/Total    Percent hit
     98  ---------------------------------------------------------------------------------------------------------------------
     99    $root                                              0/    0/    0      100%             0/    0/    0      100%
    100    main                                               0/   64/   64        0%             0/   64/   64        0%
    101    main.fsm1                                          0/    0/    0      100%             0/    0/    0      100%
    102    main.fsm2                                          0/    0/    0      100%             0/    0/    0      100%
    103  
    104                                                      Addressable elements written         Addressable elements read
    105                                                     Hit/ Miss/Total    Percent hit      Hit/ Miss/Total    Percent hit
    106  ---------------------------------------------------------------------------------------------------------------------
    107    $root                                              0/    0/    0      100%             0/    0/    0      100%
    108    main                                               1/   15/   16        6%             1/   15/   16        6%
    109    main.fsm1                                          0/    0/    0      100%             0/    0/    0      100%
    110    main.fsm2                                          0/    0/    0      100%             0/    0/    0      100%
    111  ---------------------------------------------------------------------------------------------------------------------
    112  
    113      Module: main, File: example.v, Instance: main
    114      -------------------------------------------------------------------------------------------------------------
    115      Memories not getting 100% coverage
    116  
    117        ---------------------------------------------------------------------------------------------------------
    118        Memory name:  err_mem[0:15]
    119        ---------------------------------------------------------------------------------------------------------
    120          err_mem[0]  Written: 1  0->1: 4'h0
    121          ..........  Read   : 1  1->0: 4'h0 ...
    122          err_mem[1]  Written: 0  0->1: 4'h0
    123          ..........  Read   : 0  1->0: 4'h0 ...
    124          err_mem[2]  Written: 0  0->1: 4'h0
    125          ..........  Read   : 0  1->0: 4'h0 ...
    126          err_mem[3]  Written: 0  0->1: 4'h0
    127          ..........  Read   : 0  1->0: 4'h0 ...
    128          err_mem[4]  Written: 0  0->1: 4'h0
    129          ..........  Read   : 0  1->0: 4'h0 ...
    130          err_mem[5]  Written: 0  0->1: 4'h0
    131          ..........  Read   : 0  1->0: 4'h0 ...
    132          err_mem[6]  Written: 0  0->1: 4'h0
    133          ..........  Read   : 0  1->0: 4'h0 ...
    134          err_mem[7]  Written: 0  0->1: 4'h0
    135          ..........  Read   : 0  1->0: 4'h0 ...
    136          err_mem[8]  Written: 0  0->1: 4'h0
    137          ..........  Read   : 0  1->0: 4'h0 ...
    138          err_mem[9]  Written: 0  0->1: 4'h0
    139          ..........  Read   : 0  1->0: 4'h0 ...
    140          err_mem[10]  Written: 0  0->1: 4'h0
    141          ...........  Read   : 0  1->0: 4'h0 ...
    142          err_mem[11]  Written: 0  0->1: 4'h0
    143          ...........  Read   : 0  1->0: 4'h0 ...
    144          err_mem[12]  Written: 0  0->1: 4'h0
    145          ...........  Read   : 0  1->0: 4'h0 ...
    146          err_mem[13]  Written: 0  0->1: 4'h0
    147          ...........  Read   : 0  1->0: 4'h0 ...
    148          err_mem[14]  Written: 0  0->1: 4'h0
    149          ...........  Read   : 0  1->0: 4'h0 ...
    150          err_mem[15]  Written: 0  0->1: 4'h0
    151          ...........  Read   : 0  1->0: 4'h0 ...
    152  
    153  
    154  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    155  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   COMBINATIONAL LOGIC COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    156  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    157  Instance                                                                    Logic Combinations
    158                                                                        Hit/Miss/Total    Percent hit
    159  ---------------------------------------------------------------------------------------------------------------------
    160    $root                                                                 0/   0/   0      100%
    161    main                                                                 14/  11/  25       56%
    162    main.fsm1                                                             8/   4/  12       67%
    163    main.fsm2                                                             8/   4/  12       67%
    164  ---------------------------------------------------------------------------------------------------------------------
    165  
    166      Module: main, File: example.v, Instance: main
    167      -------------------------------------------------------------------------------------------------------------
    168      Missed Combinations  (* = missed value)
    169  
    170        =========================================================================================================
    171         Line #     Expression
    172        =========================================================================================================
    173               20:    err_mem[err_cnt] = {(state[0] & state[1]), (state[0] & state[2]), (state[1] & state[2]), (state == 3'b0)}
    174                                          |---------1---------|  |---------2---------|  |---------3---------|  |------4------| 
    175                                         |-----------------------------------------5------------------------------------------|
    176  
    177          Expression 1   (2/3)
    178          ^^^^^^^^^^^^^ - &
    179           LR | LR | LR 
    180          =0-=|=-0=|=11=
    181                     *
    182  
    183          Expression 2   (2/3)
    184          ^^^^^^^^^^^^^ - &
    185           LR | LR | LR 
    186          =0-=|=-0=|=11=
    187                     *
    188  
    189          Expression 3   (2/3)
    190          ^^^^^^^^^^^^^ - &
    191           LR | LR | LR 
    192          =0-=|=-0=|=11=
    193                     *
    194  
    195          Expression 4   (1/2)
    196          ^^^^^^^^^^^^^ - ==
    197           E | E
    198          =0=|=1=
    199               *
    200  
    201          Expression 5   (1/2)
    202          ^^^^^^^^^^^^^ - {}
    203           E | E
    204          =0=|=1=
    205               *
    206  
    207        =========================================================================================================
    208         Line #     Expression
    209        =========================================================================================================
    210               21:    if( (!err_cnt[4] && (err_mem[err_cnt] != 0)) )
    211                           |----1----|    |----------2----------|   
    212                          |------------------3-------------------|  
    213  
    214          Expression 1   (1/2)
    215          ^^^^^^^^^^^^^ - !
    216           E | E
    217          =0=|=1=
    218           *    
    219  
    220          Expression 2   (1/2)
    221          ^^^^^^^^^^^^^ - !=
    222           E | E
    223          =0=|=1=
    224               *
    225  
    226          Expression 3   (1/3)
    227          ^^^^^^^^^^^^^ - &&
    228           LR | LR | LR 
    229          =0-=|=-0=|=11=
    230           *         *
    231  
    232        =========================================================================================================
    233         Line #     Expression
    234        =========================================================================================================
    235               22:    err_cnt = (err_cnt + 1)
    236                                |-----1-----|
    237  
    238          Expression 1   (0/2)
    239          ^^^^^^^^^^^^^ - +
    240           E | E
    241          =0=|=1=
    242           *   *
    243  
    244  
    245      Module: fsma, File: example.v, Instance: main.fsm1
    246      -------------------------------------------------------------------------------------------------------------
    247      Missed Combinations  (* = missed value)
    248  
    249        =========================================================================================================
    250         Line #     Expression
    251        =========================================================================================================
    252               61:    case( state ) 
    253                            |-1-|   
    254                      3'b1 :
    255  
    256          Expression 1   (1/2)
    257          ^^^^^^^^^^^^^ - 
    258           E | E
    259          =0=|=1=
    260           *    
    261  
    262        =========================================================================================================
    263         Line #     Expression
    264        =========================================================================================================
    265               61:    next_state =  go ? 3'b10 : 3'b1
    266                                   |-------1--------|
    267  
    268          Expression 1   (1/2)
    269          ^^^^^^^^^^^^^ - ?:
    270           E | E
    271          =0=|=1=
    272           *    
    273  
    274        =========================================================================================================
    275         Line #     Expression
    276        =========================================================================================================
    277               62:    next_state =  go ? 3'b10 : 3'b100
    278                                   |1|                 
    279                                   |--------2---------|
    280  
    281          Expression 1   (1/2)
    282          ^^^^^^^^^^^^^ - 
    283           E | E
    284          =0=|=1=
    285           *    
    286  
    287          Expression 2   (1/2)
    288          ^^^^^^^^^^^^^ - ?:
    289           E | E
    290          =0=|=1=
    291           *    
    292  
    293  
    294      Module: fsmb, File: example.v, Instance: main.fsm2
    295      -------------------------------------------------------------------------------------------------------------
    296      Missed Combinations  (* = missed value)
    297  
    298        =========================================================================================================
    299         Line #     Expression
    300        =========================================================================================================
    301               90:    case( state ) 
    302                            |-1-|   
    303                      3'b1 :
    304  
    305          Expression 1   (1/2)
    306          ^^^^^^^^^^^^^ - 
    307           E | E
    308          =0=|=1=
    309           *    
    310  
    311        =========================================================================================================
    312         Line #     Expression
    313        =========================================================================================================
    314               90:    next_state =  go ? 3'b10 : 3'b1
    315                                   |-------1--------|
    316  
    317          Expression 1   (1/2)
    318          ^^^^^^^^^^^^^ - ?:
    319           E | E
    320          =0=|=1=
    321           *    
    322  
    323        =========================================================================================================
    324         Line #     Expression
    325        =========================================================================================================
    326               91:    next_state =  go ? 3'b10 : 3'b100
    327                                   |1|                 
    328                                   |--------2---------|
    329  
    330          Expression 1   (1/2)
    331          ^^^^^^^^^^^^^ - 
    332           E | E
    333          =0=|=1=
    334           *    
    335  
    336          Expression 2   (1/2)
    337          ^^^^^^^^^^^^^ - ?:
    338           E | E
    339          =0=|=1=
    340           *    
    341  
    342  
    343  
    344  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    345  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   FINITE STATE MACHINE COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    346  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    347                                                                 State                             Arc
    348  Instance                                          Hit/Miss/Total    Percent hit    Hit/Miss/Total    Percent hit
    349  ---------------------------------------------------------------------------------------------------------------------
    350    $root                                             0/   0/   0      100%            0/   0/   0      100%
    351    main                                              0/   0/   0      100%            0/   0/   0      100%
    352    main.fsm1                                         3/  ? /  ?        ? %            4/  ? /  ?        ? %
    353    main.fsm2                                         2/   1/   3       67%            3/   2/   5       60%
    354  ---------------------------------------------------------------------------------------------------------------------
    355  
    356      Module: fsma, File: example.v, Instance: main.fsm1
    357      -------------------------------------------------------------------------------------------------------------
    358        FSM input state (state), output state (next_state)
    359  
    360          Hit States
    361  
    362            States
    363            ======
    364            3'h4
    365            3'h1
    366            3'h2
    367  
    368          Hit State Transitions
    369  
    370            From State    To State  
    371            ==========    ==========
    372            3'h4       -> 3'h1      
    373            3'h1       -> 3'h1      
    374            3'h1       -> 3'h2      
    375            3'h2       -> 3'h2      
    376  
    377  
    378      Module: fsmb, File: example.v, Instance: main.fsm2
    379      -------------------------------------------------------------------------------------------------------------
    380        FSM input state (state), output state (next_state)
    381  
    382          Missed States
    383  
    384            States
    385            ======
    386            3'h4
    387  
    388          Missed State Transitions
    389  
    390            From State    To State  
    391            ==========    ==========
    392            3'h2       -> 3'h4      
    393            3'h4       -> 3'h1      
    394  
    395  
    396  
    397  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    398  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   ASSERTION COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    399  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    400  Instance                                           Hit/ Miss/Total    Percent hit
    401  ---------------------------------------------------------------------------------------------------------------------
    402    $root                                              0/    0/    0      100%
    403    main                                               0/    0/    0      100%
    404    main.fsm1                                          2/    0/    2      100%
    405    main.fsm2                                          1/    1/    2       50%
    406  ---------------------------------------------------------------------------------------------------------------------
    407  
    408      Module: fsmb, File: example.v, Instance: main.fsm2
    409      -------------------------------------------------------------------------------------------------------------
    410      Missed Assertions
    411  
    412        Instance Name               Assertion Name          Coverage Point
    413        ---------------------------------------------------------------------------------------------------------
    414        zzz_check_state             assert_one_hot          "all_one_hots_checked covered          "
    415  
    416  
    417  
    418  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    419  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   RACE CONDITION VIOLATIONS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    420  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    421  Module                    Filename                 Number of Violations found
    422  ---------------------------------------------------------------------------------------------------------------------
    423    $root                   NA                          0
    424    main                    example.v                   0
    425    fsma                    example.v                   1
    426    fsmb                    example.v                   1
    427  ---------------------------------------------------------------------------------------------------------------------
    428  
    429      Module: fsma, File: example.v
    430      -------------------------------------------------------------------------------------------------------------
    431        Starting Line #     Race Condition Violation Reason
    432        ---------------------------------------------------------------------------------------------------------
    433                     56:    Signal assigned in two different statement blocks
    434  
    435  
    436      Module: fsmb, File: example.v
    437      -------------------------------------------------------------------------------------------------------------
    438        Starting Line #     Race Condition Violation Reason
    439        ---------------------------------------------------------------------------------------------------------
    440                     82:    Signal assigned in two different statement blocks
    441  
    442  
    443
covered-0.7.10/doc/html/test/example.rptM.html0000644000076500007650000010047611052400252021173 0ustar trevorwtrevorw

      1                               ::::::::::::::::::::::::::::::::::::::::::::::::::
      2                               ::                                              ::
      3                               ::  Covered -- Verilog Coverage Verbose Report  ::
      4                               ::                                              ::
      5                               ::::::::::::::::::::::::::::::::::::::::::::::::::
      6  
      7  
      8  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
      9  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   GENERAL INFORMATION   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     10  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     11  * Report generated from CDD file : cov.cdd
     12  
     13  * Reported by                    : Module
     14  
     15  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     16  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   LINE COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     17  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     18  Module/Task/Function      Filename                 Hit/ Miss/Total    Percent hit
     19  ---------------------------------------------------------------------------------------------------------------------
     20    $root                   NA                         0/    0/    0      100%
     21    main                    example.v                  6/    1/    7       86%
     22    fsma                    example.v                  4/    0/    4      100%
     23    fsmb                    example.v                  3/    1/    4       75%
     24  ---------------------------------------------------------------------------------------------------------------------
     25  
     26      Module: main, File: example.v
     27      -------------------------------------------------------------------------------------------------------------
     28      Missed Lines
     29  
     30             22:    err_cnt = (err_cnt + 1)
     31  
     32  
     33      Module: fsmb, File: example.v
     34      -------------------------------------------------------------------------------------------------------------
     35      Missed Lines
     36  
     37             92:    next_state = 3'b1
     38  
     39  
     40  
     41  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     42  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   TOGGLE COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     43  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     44  Module/Task/Function      Filename                         Toggle 0 -> 1                       Toggle 1 -> 0
     45                                                     Hit/ Miss/Total    Percent hit      Hit/ Miss/Total    Percent hit
     46  ---------------------------------------------------------------------------------------------------------------------
     47    $root                   NA                         0/    0/    0      100%             0/    0/    0      100%
     48    main                    example.v                  4/    6/   10       40%             3/    7/   10       30%
     49    fsma                    example.v                  5/    3/    8       62%             4/    4/    8       50%
     50    fsmb                    example.v                  4/    4/    8       50%             3/    5/    8       38%
     51  ---------------------------------------------------------------------------------------------------------------------
     52  
     53      Module: main, File: example.v
     54      -------------------------------------------------------------------------------------------------------------
     55      Signals not getting 100% toggle coverage
     56  
     57        Signal                    Toggle
     58        ---------------------------------------------------------------------------------------------------------
     59        go                        0->1: 1'h1
     60        ......................... 1->0: 1'h0 ...
     61        state                     0->1: 3'h3
     62        ......................... 1->0: 3'h5 ...
     63        err_cnt                   0->1: 5'h00
     64        ......................... 1->0: 5'h00 ...
     65  
     66      Module: fsma, File: example.v
     67      -------------------------------------------------------------------------------------------------------------
     68      Signals not getting 100% toggle coverage
     69  
     70        Signal                    Toggle
     71        ---------------------------------------------------------------------------------------------------------
     72        go                        0->1: 1'h1
     73        ......................... 1->0: 1'h0 ...
     74        state                     0->1: 3'h3
     75        ......................... 1->0: 3'h5 ...
     76        next_state                0->1: 3'h2
     77        ......................... 1->0: 3'h1 ...
     78  
     79      Module: fsmb, File: example.v
     80      -------------------------------------------------------------------------------------------------------------
     81      Signals not getting 100% toggle coverage
     82  
     83        Signal                    Toggle
     84        ---------------------------------------------------------------------------------------------------------
     85        go                        0->1: 1'h1
     86        ......................... 1->0: 1'h0 ...
     87        next_state                0->1: 3'h2
     88        ......................... 1->0: 3'h1 ...
     89        state                     0->1: 3'h2
     90        ......................... 1->0: 3'h1 ...
     91  
     92  
     93  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     94  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   MEMORY COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     95  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
     96                                                             Toggle 0 -> 1                       Toggle 1 -> 0
     97  Module/Task/Function      Filename                 Hit/ Miss/Total    Percent hit      Hit/ Miss/Total    Percent hit
     98  ---------------------------------------------------------------------------------------------------------------------
     99    $root                   NA                         0/    0/    0      100%             0/    0/    0      100%
    100    main                    example.v                  0/   64/   64        0%             0/   64/   64        0%
    101    fsma                    example.v                  0/    0/    0      100%             0/    0/    0      100%
    102    fsmb                    example.v                  0/    0/    0      100%             0/    0/    0      100%
    103  
    104                                                      Addressable elements written         Addressable elements read
    105                                                     Hit/ Miss/Total    Percent hit      Hit/ Miss/Total    Percent hit
    106  ---------------------------------------------------------------------------------------------------------------------
    107    $root                   NA                         0/    0/    0      100%             0/    0/    0      100%
    108    main                    example.v                  1/   15/   16        6%             1/   15/   16        6%
    109    fsma                    example.v                  0/    0/    0      100%             0/    0/    0      100%
    110    fsmb                    example.v                  0/    0/    0      100%             0/    0/    0      100%
    111  ---------------------------------------------------------------------------------------------------------------------
    112  
    113      Module: main, File: example.v
    114      -------------------------------------------------------------------------------------------------------------
    115      Memories not getting 100% coverage
    116  
    117        ---------------------------------------------------------------------------------------------------------
    118        Memory name:  err_mem[0:15]
    119        ---------------------------------------------------------------------------------------------------------
    120          err_mem[0]  Written: 1  0->1: 4'h0
    121          ..........  Read   : 1  1->0: 4'h0 ...
    122          err_mem[1]  Written: 0  0->1: 4'h0
    123          ..........  Read   : 0  1->0: 4'h0 ...
    124          err_mem[2]  Written: 0  0->1: 4'h0
    125          ..........  Read   : 0  1->0: 4'h0 ...
    126          err_mem[3]  Written: 0  0->1: 4'h0
    127          ..........  Read   : 0  1->0: 4'h0 ...
    128          err_mem[4]  Written: 0  0->1: 4'h0
    129          ..........  Read   : 0  1->0: 4'h0 ...
    130          err_mem[5]  Written: 0  0->1: 4'h0
    131          ..........  Read   : 0  1->0: 4'h0 ...
    132          err_mem[6]  Written: 0  0->1: 4'h0
    133          ..........  Read   : 0  1->0: 4'h0 ...
    134          err_mem[7]  Written: 0  0->1: 4'h0
    135          ..........  Read   : 0  1->0: 4'h0 ...
    136          err_mem[8]  Written: 0  0->1: 4'h0
    137          ..........  Read   : 0  1->0: 4'h0 ...
    138          err_mem[9]  Written: 0  0->1: 4'h0
    139          ..........  Read   : 0  1->0: 4'h0 ...
    140          err_mem[10]  Written: 0  0->1: 4'h0
    141          ...........  Read   : 0  1->0: 4'h0 ...
    142          err_mem[11]  Written: 0  0->1: 4'h0
    143          ...........  Read   : 0  1->0: 4'h0 ...
    144          err_mem[12]  Written: 0  0->1: 4'h0
    145          ...........  Read   : 0  1->0: 4'h0 ...
    146          err_mem[13]  Written: 0  0->1: 4'h0
    147          ...........  Read   : 0  1->0: 4'h0 ...
    148          err_mem[14]  Written: 0  0->1: 4'h0
    149          ...........  Read   : 0  1->0: 4'h0 ...
    150          err_mem[15]  Written: 0  0->1: 4'h0
    151          ...........  Read   : 0  1->0: 4'h0 ...
    152  
    153  
    154  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    155  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   COMBINATIONAL LOGIC COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    156  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    157  Module/Task/Function                Filename                                Logic Combinations
    158                                                                        Hit/Miss/Total    Percent hit
    159  ---------------------------------------------------------------------------------------------------------------------
    160    $root                             NA                                  0/   0/   0      100%
    161    main                              example.v                          14/  11/  25       56%
    162    fsma                              example.v                           8/   4/  12       67%
    163    fsmb                              example.v                           8/   4/  12       67%
    164  ---------------------------------------------------------------------------------------------------------------------
    165  
    166      Module: main, File: example.v
    167      -------------------------------------------------------------------------------------------------------------
    168      Missed Combinations  (* = missed value)
    169  
    170        =========================================================================================================
    171         Line #     Expression
    172        =========================================================================================================
    173               20:    err_mem[err_cnt] = {(state[0] & state[1]), (state[0] & state[2]), (state[1] & state[2]), (state == 3'b0)}
    174                                          |---------1---------|  |---------2---------|  |---------3---------|  |------4------| 
    175                                         |-----------------------------------------5------------------------------------------|
    176  
    177          Expression 1   (2/3)
    178          ^^^^^^^^^^^^^ - &
    179           LR | LR | LR 
    180          =0-=|=-0=|=11=
    181                     *
    182  
    183          Expression 2   (2/3)
    184          ^^^^^^^^^^^^^ - &
    185           LR | LR | LR 
    186          =0-=|=-0=|=11=
    187                     *
    188  
    189          Expression 3   (2/3)
    190          ^^^^^^^^^^^^^ - &
    191           LR | LR | LR 
    192          =0-=|=-0=|=11=
    193                     *
    194  
    195          Expression 4   (1/2)
    196          ^^^^^^^^^^^^^ - ==
    197           E | E
    198          =0=|=1=
    199               *
    200  
    201          Expression 5   (1/2)
    202          ^^^^^^^^^^^^^ - {}
    203           E | E
    204          =0=|=1=
    205               *
    206  
    207        =========================================================================================================
    208         Line #     Expression
    209        =========================================================================================================
    210               21:    if( (!err_cnt[4] && (err_mem[err_cnt] != 0)) )
    211                           |----1----|    |----------2----------|   
    212                          |------------------3-------------------|  
    213  
    214          Expression 1   (1/2)
    215          ^^^^^^^^^^^^^ - !
    216           E | E
    217          =0=|=1=
    218           *    
    219  
    220          Expression 2   (1/2)
    221          ^^^^^^^^^^^^^ - !=
    222           E | E
    223          =0=|=1=
    224               *
    225  
    226          Expression 3   (1/3)
    227          ^^^^^^^^^^^^^ - &&
    228           LR | LR | LR 
    229          =0-=|=-0=|=11=
    230           *         *
    231  
    232        =========================================================================================================
    233         Line #     Expression
    234        =========================================================================================================
    235               22:    err_cnt = (err_cnt + 1)
    236                                |-----1-----|
    237  
    238          Expression 1   (0/2)
    239          ^^^^^^^^^^^^^ - +
    240           E | E
    241          =0=|=1=
    242           *   *
    243  
    244  
    245      Module: fsma, File: example.v
    246      -------------------------------------------------------------------------------------------------------------
    247      Missed Combinations  (* = missed value)
    248  
    249        =========================================================================================================
    250         Line #     Expression
    251        =========================================================================================================
    252               61:    case( state ) 
    253                            |-1-|   
    254                      3'b1 :
    255  
    256          Expression 1   (1/2)
    257          ^^^^^^^^^^^^^ - 
    258           E | E
    259          =0=|=1=
    260           *    
    261  
    262        =========================================================================================================
    263         Line #     Expression
    264        =========================================================================================================
    265               61:    next_state =  go ? 3'b10 : 3'b1
    266                                   |-------1--------|
    267  
    268          Expression 1   (1/2)
    269          ^^^^^^^^^^^^^ - ?:
    270           E | E
    271          =0=|=1=
    272           *    
    273  
    274        =========================================================================================================
    275         Line #     Expression
    276        =========================================================================================================
    277               62:    next_state =  go ? 3'b10 : 3'b100
    278                                   |1|                 
    279                                   |--------2---------|
    280  
    281          Expression 1   (1/2)
    282          ^^^^^^^^^^^^^ - 
    283           E | E
    284          =0=|=1=
    285           *    
    286  
    287          Expression 2   (1/2)
    288          ^^^^^^^^^^^^^ - ?:
    289           E | E
    290          =0=|=1=
    291           *    
    292  
    293  
    294      Module: fsmb, File: example.v
    295      -------------------------------------------------------------------------------------------------------------
    296      Missed Combinations  (* = missed value)
    297  
    298        =========================================================================================================
    299         Line #     Expression
    300        =========================================================================================================
    301               90:    case( state ) 
    302                            |-1-|   
    303                      3'b1 :
    304  
    305          Expression 1   (1/2)
    306          ^^^^^^^^^^^^^ - 
    307           E | E
    308          =0=|=1=
    309           *    
    310  
    311        =========================================================================================================
    312         Line #     Expression
    313        =========================================================================================================
    314               90:    next_state =  go ? 3'b10 : 3'b1
    315                                   |-------1--------|
    316  
    317          Expression 1   (1/2)
    318          ^^^^^^^^^^^^^ - ?:
    319           E | E
    320          =0=|=1=
    321           *    
    322  
    323        =========================================================================================================
    324         Line #     Expression
    325        =========================================================================================================
    326               91:    next_state =  go ? 3'b10 : 3'b100
    327                                   |1|                 
    328                                   |--------2---------|
    329  
    330          Expression 1   (1/2)
    331          ^^^^^^^^^^^^^ - 
    332           E | E
    333          =0=|=1=
    334           *    
    335  
    336          Expression 2   (1/2)
    337          ^^^^^^^^^^^^^ - ?:
    338           E | E
    339          =0=|=1=
    340           *    
    341  
    342  
    343  
    344  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    345  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   FINITE STATE MACHINE COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    346  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    347                                                                 State                             Arc
    348  Module/Task/Function      Filename                Hit/Miss/Total    Percent Hit    Hit/Miss/Total    Percent hit
    349  ---------------------------------------------------------------------------------------------------------------------
    350    $root                   NA                        0/   0/   0      100%            0/   0/   0      100%
    351    main                    example.v                 0/   0/   0      100%            0/   0/   0      100%
    352    fsma                    example.v                 3/  ? /  ?        ? %            4/  ? /  ?        ? %
    353    fsmb                    example.v                 2/   1/   3       67%            3/   2/   5       60%
    354  ---------------------------------------------------------------------------------------------------------------------
    355  
    356      Module: fsma, File: example.v
    357      -------------------------------------------------------------------------------------------------------------
    358        FSM input state (state), output state (next_state)
    359  
    360          Hit States
    361  
    362            States
    363            ======
    364            3'h4
    365            3'h1
    366            3'h2
    367  
    368          Hit State Transitions
    369  
    370            From State    To State  
    371            ==========    ==========
    372            3'h4       -> 3'h1      
    373            3'h1       -> 3'h1      
    374            3'h1       -> 3'h2      
    375            3'h2       -> 3'h2      
    376  
    377  
    378      Module: fsmb, File: example.v
    379      -------------------------------------------------------------------------------------------------------------
    380        FSM input state (state), output state (next_state)
    381  
    382          Missed States
    383  
    384            States
    385            ======
    386            3'h4
    387  
    388          Missed State Transitions
    389  
    390            From State    To State  
    391            ==========    ==========
    392            3'h2       -> 3'h4      
    393            3'h4       -> 3'h1      
    394  
    395  
    396  
    397  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    398  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   ASSERTION COVERAGE RESULTS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    399  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    400  Module/Task/Function      Filename                 Hit/ Miss/Total    Percent hit
    401  ---------------------------------------------------------------------------------------------------------------------
    402    $root                   NA                         0/    0/    0      100%
    403    main                    example.v                  0/    0/    0      100%
    404    fsma                    example.v                  2/    0/    2      100%
    405    fsmb                    example.v                  2/    0/    2      100%
    406  
    407  
    408  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    409  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~   RACE CONDITION VIOLATIONS   ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    410  ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
    411  Module                    Filename                 Number of Violations found
    412  ---------------------------------------------------------------------------------------------------------------------
    413    $root                   NA                          0
    414    main                    example.v                   0
    415    fsma                    example.v                   1
    416    assert_one_hot          assert_one_hot.vlib         0
    417    fsmb                    example.v                   1
    418  ---------------------------------------------------------------------------------------------------------------------
    419  
    420      Module: fsma, File: example.v
    421      -------------------------------------------------------------------------------------------------------------
    422        Starting Line #     Race Condition Violation Reason
    423        ---------------------------------------------------------------------------------------------------------
    424                     56:    Signal assigned in two different statement blocks
    425  
    426  
    427      Module: fsmb, File: example.v
    428      -------------------------------------------------------------------------------------------------------------
    429        Starting Line #     Race Condition Violation Reason
    430        ---------------------------------------------------------------------------------------------------------
    431                     82:    Signal assigned in two different statement blocks
    432  
    433  
    434
covered-0.7.10/doc/html/test/example.v0000644000076500007650000000363511052400252017552 0ustar trevorwtrevorw`define ST_STOP 3'b001 `define ST_GO 3'b010 `define ST_SLOW 3'b100 module main; reg clk; reg go; wire [2:0] state; reg [3:0] err_mem[0:15]; reg [4:0] err_cnt; fsma fsm1( clk, go, state ); fsmb fsm2( clk, go ); initial begin err_cnt = 0; forever @(posedge clk) begin err_mem[err_cnt] = {(state[0] & state[1]), (state[0] & state[2]), (state[1] & state[2]), (state == 3'b000)}; if( !err_cnt[4] && (err_mem[err_cnt] != 0) ) err_cnt = err_cnt + 1; end end initial begin $dumpfile( "example.vcd" ); $dumpvars( 0, main ); go = 1'b0; repeat( 10 ) @(posedge clk); go = 1'b1; #10; $finish; end initial begin clk = 1'b0; forever #(1) clk = ~clk; end endmodule module fsma( clk, go, state ); input clk; input go; output [2:0] state; reg [2:0] next_state; reg [2:0] state; initial begin state = `ST_SLOW; end always @(posedge clk) state <= next_state; (* covered_fsm, lights, is="state", os="next_state" *) always @(state or go) case( state ) `ST_STOP : next_state = go ? `ST_GO : `ST_STOP; `ST_GO : next_state = go ? `ST_GO : `ST_SLOW; `ST_SLOW : next_state = `ST_STOP; endcase assert_one_hot #(.width(3)) zzz_check_state ( clk, 1'b1, state ); endmodule module fsmb( clk, go ); input clk; input go; reg [2:0] next_state; reg [2:0] state; initial begin state = `ST_STOP; end always @(posedge clk) state <= next_state; (* covered_fsm, lights, is="state", os="next_state", trans="3'b001->3'b010", trans="3'b010->3'b100", trans="3'b100->3'b001" *) always @(state or go) case( state ) `ST_STOP : next_state = go ? `ST_GO : `ST_STOP; `ST_GO : next_state = go ? `ST_GO : `ST_SLOW; `ST_SLOW : next_state = `ST_STOP; endcase assert_one_hot #(.width(3)) zzz_check_state ( clk, 1'b1, state ); endmodule covered-0.7.10/doc/html/test/example.v.html0000644000076500007650000001064211052400252020511 0ustar trevorwtrevorw

      1  `define ST_STOP  3'b001
      2  `define ST_GO    3'b010
      3  `define ST_SLOW  3'b100
      4  
      5  module main;
      6  
      7  reg        clk;
      8  reg        go;
      9  wire [2:0] state;
     10  reg  [3:0] err_mem[0:15];
     11  reg  [4:0] err_cnt;
     12  
     13  fsma fsm1( clk, go, state );
     14  fsmb fsm2( clk, go );
     15  
     16  initial begin
     17          err_cnt = 0;
     18          forever @(posedge clk)
     19            begin
     20             err_mem[err_cnt] = {(state[0] & state[1]), (state[0] & state[2]), (state[1] & state[2]), (state == 3'b000)};
     21             if( !err_cnt[4] && (err_mem[err_cnt] != 0) )
     22               err_cnt = err_cnt + 1;
     23            end
     24  end
     25  
     26  initial begin
     27  	$dumpfile( "example.vcd" );
     28  	$dumpvars( 0, main );
     29  	go = 1'b0;
     30  	repeat( 10 ) @(posedge clk);
     31  	go = 1'b1;
     32  	#10;
     33  	$finish;
     34  end
     35  
     36  initial begin
     37  	clk = 1'b0;
     38  	forever #(1) clk = ~clk;
     39  end
     40  
     41  endmodule
     42  
     43  module fsma( clk, go, state );
     44  
     45  input        clk;
     46  input        go;
     47  output [2:0] state;
     48  
     49  reg [2:0] next_state;
     50  reg [2:0] state;
     51  
     52  initial begin
     53  	state = `ST_SLOW;
     54  end
     55  
     56  always @(posedge clk) state <= next_state;
     57  
     58  (* covered_fsm, lights, is="state", os="next_state" *)
     59  always @(state or go)
     60    case( state )
     61      `ST_STOP :  next_state = go ? `ST_GO : `ST_STOP;
     62      `ST_GO   :  next_state = go ? `ST_GO : `ST_SLOW;
     63      `ST_SLOW :  next_state = `ST_STOP;
     64    endcase
     65  
     66  assert_one_hot #(.width(3)) zzz_check_state ( clk, 1'b1, state );
     67  
     68  endmodule
     69  
     70  module fsmb( clk, go );
     71  
     72  input     clk;
     73  input     go;
     74  
     75  reg [2:0] next_state;
     76  reg [2:0] state;
     77  
     78  initial begin
     79          state = `ST_STOP;
     80  end
     81  
     82  always @(posedge clk) state <= next_state;
     83  
     84  (* covered_fsm, lights, is="state", os="next_state",
     85                          trans="3'b001->3'b010",
     86                          trans="3'b010->3'b100",
     87                          trans="3'b100->3'b001" *)
     88  always @(state or go)
     89    case( state )
     90      `ST_STOP :  next_state = go ? `ST_GO : `ST_STOP;
     91      `ST_GO   :  next_state = go ? `ST_GO : `ST_SLOW;
     92      `ST_SLOW :  next_state = `ST_STOP;
     93    endcase
     94  
     95  assert_one_hot #(.width(3)) zzz_check_state ( clk, 1'b1, state );
     96  
     97  endmodule
covered-0.7.10/doc/html/test/libs0000644000076500007650000000023211052400252016572 0ustar trevorwtrevorw+libext+.vlib +libext+.v +define+OVL_COVER_NONE +define+OVL_COVER_ON +define+OVL_VERILOG +incdir+../../../diags/verilog/ovl -y ../../../diags/verilog/ovl covered-0.7.10/doc/html/test/Makefile0000644000076500007650000000065611052400252017370 0ustar trevorwtrevorwOVL_HOME = ../../../diags/verilog/ovl all: iverilog -v -c libs example.v ./a.out ../../../src/covered -D score -t main -v example.v -vcd example.vcd -A ovl +libext+.vlib+ -y $(OVL_HOME) -y $(OVL_HOME)/vlog95 -I $(OVL_HOME) ../../../src/covered report -d v -m ltcfram -o example.rptM cov.cdd ../../../src/covered report -d v -m ltcfram -i -o example.rptI cov.cdd ./prep_files clean: rm -rf a.out *.cdd *.rptM *.rptI *.vcd covered-0.7.10/doc/html/test/prep_files0000755000076500007650000000111711052400252017777 0ustar trevorwtrevorw#!/usr/bin/perl &transform( "example.v" ); &transform( "example.rptM" ); &transform( "example.rptI" ); sub transform { my $file = $_[0]; open( IFILE, "${file}" ) || die "Cannot open ${file} for reading: $!\n"; open( OFILE, ">${file}.html" ) || die "Cannot open ${file}.html for writing: $!\n"; print OFILE "
\n";
  $line_num = 1;
  while(  ) {
    chomp;
    print OFILE sprintf( "%7d  %s\n", $line_num, $line_num, $_ );
    $line_num++;
  }

  print OFILE "
\n"; close( IFILE ); close( OFILE ); } covered-0.7.10/doc/Makefile.am0000644000076500007650000001107511201714404016041 0ustar trevorwtrevorwSUBDIRS = docbook docdir = $(datadir)/covered/doc/html doc_DATA = html/chapter.attr.html \ html/chapter.boundaries.html \ html/chapter.debug.html \ html/chapter.epilogue.html \ html/chapter.exclude.html \ html/chapter.faq.html \ html/chapter.gui.assert.html \ html/chapter.gui.assert.source.html \ html/chapter.gui.exclude.html \ html/chapter.gui.fsm.html \ html/chapter.gui.genreport.html \ html/chapter.gui.intro.html \ html/chapter.gui.line.html \ html/chapter.gui.logic.html \ html/chapter.gui.main.html \ html/chapter.gui.memory.html \ html/chapter.gui.new.html \ html/chapter.gui.preferences.html \ html/chapter.gui.rank.html \ html/chapter.gui.toggle.html \ html/chapter.gui.wizard.html \ html/chapter.installation.html \ html/chapter.intro.html \ html/chapter.merge.html \ html/chapter.metrics.html \ html/chapter.race.html \ html/chapter.rank.html \ html/chapter.reading.html \ html/chapter.report.html \ html/chapter.score.html \ html/chapter.start.html \ html/chapter.using.html \ html/covered.css \ html/index.html \ html/part.command.line.usage.html \ html/part.epilogue.html \ html/part.faq.html \ html/part.gui.html \ html/part.installation.html \ html/part.overview.html \ html/test/example.rptI.html \ html/test/example.rptM.html \ html/test/example.v.html imgdir = $(datadir)/covered/doc/html/img img_DATA = html/img/app_menu.gif \ html/img/assert_excl.gif \ html/img/assert_src.gif \ html/img/assert_window.gif \ html/img/banner.jpg \ html/img/close_warn.gif \ html/img/col_show_hide.gif \ html/img/comb_complex.gif \ html/img/comb_event.gif \ html/img/comb_simple.gif \ html/img/comb_simple_and.gif \ html/img/comb_simple_or.gif \ html/img/comb_unary.gif \ html/img/dn_button.gif \ html/img/er_full.gif \ html/img/er_part.gif \ html/img/exit_warn.gif \ html/img/file_menu.gif \ html/img/file_viewer.gif \ html/img/fsm_example.png \ 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devel_doc: -doxygen covered.dox devel_doc_clean: rm -rf devel/html devel/latex # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: covered-0.7.10/INSTALL0000644000076500007650000000750211214243360014273 0ustar trevorwtrevorw COVERED User Installation Instructions =================================================================== 1. Supported Systems Covered has been mostly tested on a RedHat Linux 7.2 system. Limited testing has been done on IRIX-6.5.12. The intent of this tool is to support any POSIX standard environment. The Icarus Verilog simulator has been used extensively throughout the development process. VCS and Cver have also been used in testing. 2. Required Tools The following is a list of tools that are necessary for building/compiling the Covered executable. - gcc (Version 2.96 or higher) - flex (Version 2.5.4 -- later versions are known to not work yet) - bison (Version 1.85 or higher) - GNU make (Version 3.27.1 or higher) - GNU gperf (Version 2.7.2 or higher) - tcl (Version 8.5 or higher) - tcl-devel (Version 8.5 or higher) - tk (Version 8.5 or higher) - tk-devel (Version 8.5 or higher) - tablelist4.11 (tablelist is a Tk widget that can be found at: //http://www.nemethi.de/) -- alternatively you can install the tcllib package which includes the tablelist package and many more (that are currently used by Covered). If you would like to use LXT2 formatted dumpfiles with Covered, you now may but it will additionally require you to have the following library package: - zlib-devel Additionally, the development documentation is built using the doxygen utility which can be found at http://www.doxygen.org 3. Configure and Make Process To begin with, untar and ungzip the Covered tarball with the following command: gzip -dc | tar xvf - After this has completed, cd to the Covered directory and perform the following command to build the proper Makefiles and set configuration settings for your system. ./configure If you are debugging a memory allocation failure and would like to use the mpatrol library to accomplish this (please see development documentation for more information), you will need to remove the "dnl" comment in the configure.in file, run aclocal and autoconf, and finally use the following configure command instead. Once these steps have been completed and the source code is compiled and run, an mpatrol.log file will be generated in the run directory. This log file is used to understand memory usage for the program. ./configure --with-mpatrol If you would like to see the built-in debugging information that Covered can produce while it runs a command or use the score command CLI, you will need to specify the following configuration command: ./configure --enable-debug If you would like to use the built-in profiling facility (-P global option), you will need to specify the following configuration command: ./configure --enable-profiling After configure has been called and 'make' run, you can get the Covered debug information generated to standard output by specifying the global '-D' option (see 'covered -h' for more information) with any command. After the configuration process has completed, a Makefile will be created in the Covered directory. To build and compile all source code for the tool, simply type: make This will create the "covered" executable file in the ./src directory. This is the only program that will be needed since there is no run-time linking or underlying libraries supporting the program. To install the executable, simply type: make install This will install the Covered executable into the /usr/local/bin directory. To place this executable in a different location, please use the --prefix= option when calling the ./configure script. If there are any problems with installing Covered, please let me know by either submitting a bug report or sending me an e-mail at phase1geo@gmail.com covered-0.7.10/install-sh0000755000076500007650000003253711270512353015257 0ustar trevorwtrevorw#!/bin/sh # install - install a program, script, or datafile scriptversion=2009-04-28.21; # UTC # This originates from X11R5 (mit/util/scripts/install.sh), which was # later released in X11R6 (xc/config/util/install.sh) with the # following copyright and license. # # Copyright (C) 1994 X Consortium # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to # deal in the Software without restriction, including without limitation the # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or # sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN # AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNEC- # TION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # # Except as contained in this notice, the name of the X Consortium shall not # be used in advertising or otherwise to promote the sale, use or other deal- # ings in this Software without prior written authorization from the X Consor- # tium. # # # FSF changes to this file are in the public domain. # # Calling this script install-sh is preferred over install.sh, to prevent # `make' implicit rules from creating a file called install from it # when there is no Makefile. # # This script is compatible with the BSD install script, but was written # from scratch. nl=' ' IFS=" "" $nl" # set DOITPROG to echo to test this script # Don't use :- since 4.3BSD and earlier shells don't like it. doit=${DOITPROG-} if test -z "$doit"; then doit_exec=exec else doit_exec=$doit fi # Put in absolute file names if you don't have them in your path; # or use environment vars. chgrpprog=${CHGRPPROG-chgrp} chmodprog=${CHMODPROG-chmod} chownprog=${CHOWNPROG-chown} cmpprog=${CMPPROG-cmp} cpprog=${CPPROG-cp} mkdirprog=${MKDIRPROG-mkdir} mvprog=${MVPROG-mv} rmprog=${RMPROG-rm} stripprog=${STRIPPROG-strip} posix_glob='?' initialize_posix_glob=' test "$posix_glob" != "?" || { if (set -f) 2>/dev/null; then posix_glob= else posix_glob=: fi } ' posix_mkdir= # Desired mode of installed file. mode=0755 chgrpcmd= chmodcmd=$chmodprog chowncmd= mvcmd=$mvprog rmcmd="$rmprog -f" stripcmd= src= dst= dir_arg= dst_arg= copy_on_change=false no_target_directory= usage="\ Usage: $0 [OPTION]... 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See the # GNU General Public License for more details. # You should have received a copy of the GNU General Public License # along with this program. If not, see . # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. if test $# -eq 0; then echo 1>&2 "Try \`$0 --help' for more information" exit 1 fi run=: sed_output='s/.* --output[ =]\([^ ]*\).*/\1/p' sed_minuso='s/.* -o \([^ ]*\).*/\1/p' # In the cases where this matters, `missing' is being run in the # srcdir already. if test -f configure.ac; then configure_ac=configure.ac else configure_ac=configure.in fi msg="missing on your system" case $1 in --run) # Try to run requested program, and just exit if it succeeds. run= shift "$@" && exit 0 # Exit code 63 means version mismatch. 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You may want to install GNU tar or Free paxutils, or check the command line arguments." exit 1 ;; *) echo 1>&2 "\ WARNING: \`$1' is needed, and is $msg. You might have modified some files without having the proper tools for further handling them. Check the \`README' file, it often tells you about the needed prerequisites for installing this package. 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Report bugs to ." # process command line arguments while test $# -gt 0 ; do case $1 in -h | --help | --h*) # -h for help echo "$usage" exit $? ;; -m) # -m PERM arg shift test $# -eq 0 && { echo "$usage" 1>&2; exit 1; } dirmode=$1 shift ;; --version) echo "$0 $scriptversion" exit $? ;; --) # stop option processing shift break ;; -*) # unknown option echo "$usage" 1>&2 exit 1 ;; *) # first non-opt arg break ;; esac done for file do if test -d "$file"; then shift else break fi done case $# in 0) exit 0 ;; esac # Solaris 8's mkdir -p isn't thread-safe. If you mkdir -p a/b and # mkdir -p a/c at the same time, both will detect that a is missing, # one will create a, then the other will try to create a and die with # a "File exists" error. This is a problem when calling mkinstalldirs # from a parallel make. We use --version in the probe to restrict # ourselves to GNU mkdir, which is thread-safe. case $dirmode in '') if mkdir -p --version . >/dev/null 2>&1 && test ! -d ./--version; then echo "mkdir -p -- $*" exec mkdir -p -- "$@" else # On NextStep and OpenStep, the `mkdir' command does not # recognize any option. It will interpret all options as # directories to create, and then abort because `.' already # exists. test -d ./-p && rmdir ./-p test -d ./--version && rmdir ./--version fi ;; *) if mkdir -m "$dirmode" -p --version . >/dev/null 2>&1 && test ! -d ./--version; then echo "mkdir -m $dirmode -p -- $*" exec mkdir -m "$dirmode" -p -- "$@" else # Clean up after NextStep and OpenStep mkdir. for d in ./-m ./-p ./--version "./$dirmode"; do test -d $d && rmdir $d done fi ;; esac for file do case $file in /*) pathcomp=/ ;; *) pathcomp= ;; esac oIFS=$IFS IFS=/ set fnord $file shift IFS=$oIFS for d do test "x$d" = x && continue pathcomp=$pathcomp$d case $pathcomp in -*) pathcomp=./$pathcomp ;; esac if test ! -d "$pathcomp"; then echo "mkdir $pathcomp" mkdir "$pathcomp" || lasterr=$? if test ! -d "$pathcomp"; then errstatus=$lasterr else if test ! -z "$dirmode"; then echo "chmod $dirmode $pathcomp" lasterr= chmod "$dirmode" "$pathcomp" || lasterr=$? if test ! -z "$lasterr"; then errstatus=$lasterr fi fi fi fi pathcomp=$pathcomp/ done done exit $errstatus # Local Variables: # mode: shell-script # sh-indentation: 2 # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "scriptversion=" # time-stamp-format: "%:y-%02m-%02d.%02H" # time-stamp-time-zone: "UTC" # time-stamp-end: "; # UTC" # End: covered-0.7.10/NEWS0000644000076500007650000000031111475641161013742 0ustar trevorwtrevorwCovered-Related NEWS ==================== * 12/2/2010 Stable release covered-0.7.10 made. This release updates the FST library to the latest version which contains some fixes and enhancements. covered-0.7.10/README0000644000076500007650000000266111200360521014115 0ustar trevorwtrevorwFor information regarding... * the installation of Covered, see the INSTALL file. * a list of the developers of Covered, see the AUTHORS file. * the CVS change list, see the ChangeLog file. * project-specific news, see the NEWS file. For User documentation... * User's Guide can be found in HTML form at ./doc/html/index.html. * Command-line help can be found by typing "covered -h" after Covered has been installed. * Version information about Covered can be found by typing "covered -v" after Covered has been installed. For Development documentation... * HTML and LaTex are generated (if the doxygen -- http://www.doxygen.org -- utility exists in the user's bin path). * HTML format can be found at ./doc/devel/html/index.html. * LaTex format can be found at ./doc/devel/latex * PDF format can be generated by following the following steps: 1. cd doc/devel/latex 2. make pdf (the PDF file will be called refman.pdf) For GUI documentation... * The GUI User's Guide is available in HTML form at ./doc/html/index.html. * This documentation can also be accessed by clicking on the "Help->User Guide" menu item The Covered website is located... * For members of SourceForge, you can get the project page at http://sourceforge.net/projects/covered - can submit/review bug reports - get to mailing lists - see CVS repository - check out other project related stuff * Homepage can be found at http://covered.sourceforge.net covered-0.7.10/scripts/0000755000076500007650000000000011475644735014751 5ustar trevorwtrevorwcovered-0.7.10/scripts/.coveredrc0000644000076500007650000001671411356776517016741 0ustar trevorwtrevorw# Covered GUI Configuration File #-------------------------------- # All variable assignments below are in the form of "variable = value" # where whitespace must be present between the variable, the "=" character # and the value. Comment lines start with the "#" character. # If set to true, causes the wizard window to be displayed on GUI startup. # If set to false, the wizard window is suppressed. ShowWizardOnStartup = true # If set to true, causes various GUI elements to be saved when exiting the application # which will be used when the application is restarted at a later time. Set to false # to cause the Covered GUI to use the default values. SaveGuiOnExit = true # If set to true, causes tooltips to be used for many widgets within the GUI. If set # to false, causes all tooltip support to be disabled. ShowTooltips = true # Specifies the ttk style type to use for the GUI. TtkStyle = clam # Sets the foreground color for all source code that is found # to be uncovered during simulation. The value can be any legal color # value accepted by Tcl. UncoveredForegroundColor = #000000 # Sets the background color for all source code that is found # to be uncovered during simulation. The value can be any legal color # value accepted by Tcl. UncoveredBackgroundColor = #a14756 # Sets the foreground color for all source code that is found # to be covered during simulation. The value can be any legal color value # accepted by Tcl. CoveredForegroundColor = black # Sets the background color for all source code that is found # to be covered during simulation. The value can be any legal color value. # accepted by Tcl. CoveredBackgroundColor = #90ee90 # Sets the foreground color for all source code that has been detected as # containing a race condition situation. This code is not analyzed by Covered. # The value can be any legal color value accepted by Tcl. RaceConditionForegroundColor = white # Sets the background color for all source code that has been detected as # containing a race condition situation. This code is not analyzed by Covered. # The value can be any legal color value accepted by Tcl. RaceConditionBackgroundColor = blue # Causes the summary color for a module/instance that has achieved a line # coverage percentage greater than or equal to this value (but not 100%) to be # colored "yellow", indicating that the line coverage can possibly be deemed # "good enough". This value must be in the range of 0 - 100. AcceptableLinePercentage = 90 # Causes the summary color for a module/instance that has achieved a toggle # coverage percentage greater than or equal to this value (but not 100%) to be # colored "yellow", indicating that the toggle coverage can possibly be deemed # "good enough". This value must be in the range of 0 - 100. AcceptableTogglePercentage = 90 # Causes the summary color for a module/instance that has achieved a memory # coverage percentage greater than or equal to this value (but not 100%) to be # colored "yellow", indicating that the memory coverage can possibly be deemed # "good enough". This value must be in the range of 0 - 100. AcceptableMemoryPercentage = 90 # Causes the summary color for a module/instance that has achieved a combinational # logic coverage percentage greater than or equal to this value (but not 100%) to be # colored "yellow", indicating that the combinational logic coverage can possibly be # deemed "good enough". This value must be in the range of 0 - 100. AcceptableCombinationalLogicPercentage = 90 # Causes the summary color for a module/instance that has achieved an FSM state/arc # coverage percentage greater than or equal to this value (but not 100%) to be # colored "yellow", indicating that the FSM coverage can possibly be deemed # "good enough". This value must be in the range of 0 - 100. AcceptableFsmPercentage = 90 # Causes the summary color for a module/instance that has achieved an assertion # coverage percentage greater than or equal to this value (but not 100%) to be # colored "yellow", indicating that the assertion coverage can possibly be deemed # "good enough". This value must be in the range of 0 - 100. AcceptableAssertionPercentage = 90 # Causes syntax highlighting to be turned on or off. This value should either be # 'on' or 'off'. HighlightingMode = on # When the syntax highlighting mode is on, causes the preprocessor directive keywords # to be highlighted with the specified color. The value may be any color value that # is acceptable to Tk. HighlightPreprocessorKeywordColor = ForestGreen # When the syntax highlighting mode is on, causes the Verilog keywords to be highlighted # with the specified color. The value may be any color value that is acceptable to Tk. HighlightKeywordColor = purple # When the syntax highlighting mode is on, causes any single or multi-line comments to # be highlighted with the specified color. The value may be any color value that is # acceptable to Tk. HighlightCommentColor = blue # When the syntax highlighting mode is on, causes any defined, binary, octal, decimal or # hexidecimal value to be highlighted with the specified color. The value may be any # color value that is acceptable to Tk. HighlightValueColor = red # When the syntax highlighting mode is on, causes any quoted string to be highlighted with # the specified color. The value may be any color value that is acceptable to Tk. HighlightStringColor = red # When the syntax highlighting mode is on, causes any Verilog symbol to be highlighted with # the specified color. The value may be any color value that is acceptable to Tk. HighlightSymbolColor = coral # If this value is set to true, a popup dialog box will be created whenever the user excludes a coverage # point, allowing for the creation of a reason for the exclusion. If this value is set to false, no popup # box will be displayed when a coverage point is marked for exclusion. The exclusion reason information # is saved to the CDD (if specified from the GUI). EnableExclusionReasons = 1 # This string specifies default reasons for exclusion. These reasons may be used wherever # a coverage point is excluded (or the user may specify a unique reason). ExclusionReasons = {Logic is obsolete but will not be removed for future enhancement possibilities. } # This value specifies how to handle exclusion reason conflicts that arise when two or more CDD files # are merged that contain mismatching exclusion reasons for identical coverage points. The valid # values are the following: # first - Use the exclusion reason from the first CDD file read in that contains the reason # last - Use the exclusion reason from the last CDD file read in that contains the reason # all - Merge all exclusion reasons into one # new - Use the newest exclusion reason specified # old - Use the oldest exclusion reason specified ExclusionReasonConflictResolution = all # THE FOLLOWING LINES ARE FOR STORING GUI STATE INFORMATION -- DO NOT MODIFY LINES BELOW THIS COMMENT! MainWindowGeometry = 1003x567+261+355 ToggleWindowGeometry = 366x125+435+411 MemoryWindowGeometry = 481x381+8+46 CombWindowGeometry = 915x637+8+46 FsmWindowGeometry = 627x480+4+23 AssertWindowGeometry = ModuleInstanceType = Instance ModuleInstanceTableListWidth = 186 ModuleInstanceTableListColumns = 0:Instance Name:left:0:Module Name:left:0:Hit:right:0:Miss:right:0:Excluded:right:0:Total:right:0:Hit %:right:0:Index:left ModuleInstanceTableListInitHidden = 0:0:0:0:0:0:0 covered-0.7.10/scripts/assert.tcl0000644000076500007650000003625611357457470016767 0ustar trevorwtrevorw################################################################################################ # Copyright (c) 2006-2010 Trevor Williams # # # # This program is free software; you can redistribute it and/or modify # # it under the terms of the GNU General Public License as published by the Free Software # # Foundation; either version 2 of the License, or (at your option) any later version. # # # # This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; # # without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. # # See the GNU General Public License for more details. # # # # You should have received a copy of the GNU General Public License along with this program; # # if not, write to the Free Software Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. # ################################################################################################ set curr_assert_ptr "" set assert_geometry "" set assert_gui_saved 0 set assert_excluded 0 set assert_reason "" proc assert_yset {args} { eval [linsert $args 0 .assertwin.f.vb set] assert_yview moveto [lindex [.assertwin.f.vb get] 0] } proc assert_yview {args} { eval [linsert $args 0 .assertwin.f.td yview] eval [linsert $args 0 .assertwin.f.tc yview] } proc display_assert {curr_index} { global prev_assert_index next_assert_index curr_assert_ptr curr_assert_inst # Get range of current instance set curr_range [.bot.right.txt tag prevrange uncov_button "$curr_index + 1 chars"] # Calculate the current instance string set curr_assert_inst [string trim [lindex [split [.bot.right.txt get [lindex $curr_range 0] [lindex $curr_range 1]] "\["] 0]] # Make sure that the selected instance is visible in the text box and is shown as selected set_pointer curr_assert_ptr [lindex [split [lindex $curr_range 0] .] 0] goto_uncov [lindex $curr_range 0] # Get range of previous instance set prev_assert_index [lindex [.bot.right.txt tag prevrange uncov_button [lindex $curr_range 0]] 0] # Get range of next instance set next_assert_index [lindex [.bot.right.txt tag nextrange uncov_button [lindex $curr_range 1]] 0] # Now create the assertion window create_assert_window $curr_assert_inst } proc create_assert_window {inst} { global prev_assert_index next_assert_index global curr_block global curr_assert_ptr assert_cov_points assert_cov_mod global uncov_bgColor uncov_fgColor global cov_bgColor cov_fgColor global HOME assert_geometry assert_gui_saved # Now create the window and set the grab to this window if {[winfo exists .assertwin] == 0} { set assert_gui_saved 0 # Create new window toplevel .assertwin wm title .assertwin "Assertion Coverage - Verbose" ttk::frame .assertwin.f -relief raised -borderwidth 1 # Add toggle information ttk::label .assertwin.f.ld -anchor w -text "Coverage point description" ttk::label .assertwin.f.lc -anchor w -text "# of hits" text .assertwin.f.td -height 5 -width 40 -borderwidth 0 -xscrollcommand ".assertwin.f.hb set" \ -yscrollcommand assert_yset -wrap none -spacing1 2 -spacing3 3 text .assertwin.f.tc -height 5 -width 10 -borderwidth 0 -yscrollcommand assert_yset -wrap none -spacing1 2 -spacing3 3 ttk::scrollbar .assertwin.f.hb -orient horizontal -command ".assertwin.f.td xview" ttk::scrollbar .assertwin.f.vb -command assert_yview ttk::button .assertwin.f.b -text "Show Code" -command { display_assertion_module [lindex $assert_cov_mod 0] [lindex $assert_cov_mod 1] } # Create bottom information bar ttk::label .assertwin.f.info -anchor w # Create bottom button bar ttk::frame .assertwin.bf -relief raised -borderwidth 1 ttk::button .assertwin.bf.close -text "Close" -width 10 -command { rm_pointer curr_assert_ptr destroy .assertwin destroy .amodwin } help_button .assertwin.bf.help chapter.gui.assert ttk::button .assertwin.bf.prev -image [image create photo -file [file join $HOME scripts left_arrow.gif]] -command { display_assert $prev_assert_index } set_balloon .assertwin.bf.prev "Click to view the previous uncovered assertion in this window" ttk::button .assertwin.bf.next -image [image create photo -file [file join $HOME scripts right_arrow.gif]] -command { display_assert $next_assert_index } set_balloon .assertwin.bf.next "Click to view the next uncovered assertion in this window" # Pack the buttons into the button frame pack .assertwin.bf.prev -side left pack .assertwin.bf.next -side left pack .assertwin.bf.help -side right -pady 3 pack .assertwin.bf.close -side right -padx 3 -pady 3 # Pack the widgets into the bottom frame grid rowconfigure .assertwin.f 1 -weight 1 grid columnconfigure .assertwin.f 0 -weight 1 grid columnconfigure .assertwin.f 1 -weight 0 grid .assertwin.f.ld -row 0 -column 0 -sticky nsew grid .assertwin.f.lc -row 0 -column 1 -sticky nsew grid .assertwin.f.td -row 1 -column 0 -sticky nsew grid .assertwin.f.tc -row 1 -column 1 -sticky nsew grid .assertwin.f.vb -row 1 -column 2 -sticky nsew grid .assertwin.f.hb -row 2 -column 0 -sticky nsew grid .assertwin.f.b -row 2 -column 1 -sticky nsew grid .assertwin.f.info -row 3 -column 0 -columnspan 3 -sticky new pack .assertwin.f -fill both -expand yes pack .assertwin.bf -fill x # Set the geometry if it is known if {$assert_geometry != ""} { wm geometry .assertwin $assert_geometry } # Handle the destruction of the assertion window wm protocol .assertwin WM_DELETE_WINDOW { save_assert_gui_elements 0 destroy .assertwin } bind .assertwin { save_assert_gui_elements 0 } } # Disable next or previous buttons if valid if {$prev_assert_index == ""} { .assertwin.bf.prev configure -state disabled } else { .assertwin.bf.prev configure -state normal } if {$next_assert_index == ""} { .assertwin.bf.next configure -state disabled } else { .assertwin.bf.next configure -state normal } # Get verbose toggle information set assert_cov_mod "" set assert_cov_points "" tcl_func_get_assert_coverage $curr_block $inst # Allow us to clear out text boxes .assertwin.f.td configure -state normal .assertwin.f.tc configure -state normal # Clear the text boxes before any insertion is being made .assertwin.f.td delete 1.0 end .assertwin.f.tc delete 1.0 end # Delete any existing tags .assertwin.f.td tag delete td_uncov_colorMap td_cov_colorMap .assertwin.f.tc tag delete tc_uncov_colorMap tc_cov_colorMap tc_excl_colorMap # Create covered/uncovered/underline tags .assertwin.f.td tag configure td_uncov_colorMap -foreground $uncov_fgColor -background $uncov_bgColor .assertwin.f.td tag configure td_cov_colorMap -foreground $cov_fgColor -background $cov_bgColor .assertwin.f.tc tag configure tc_uncov_colorMap -foreground $uncov_fgColor -background $uncov_bgColor .assertwin.f.tc tag configure tc_cov_colorMap -foreground $cov_fgColor -background $cov_bgColor .assertwin.f.tc tag configure tc_uncov_uline -underline true # Write assertion coverage point information in text boxes foreach cov_point $assert_cov_points { if {[lindex $cov_point 1] == 0} { if {[lindex $cov_point 3] == 1} { .assertwin.f.td insert end "[lindex $cov_point 0]\n" td_cov_colorMap .assertwin.f.tc insert end "E\n" {tc_cov_colorMap tc_uncov_uline} } else { .assertwin.f.td insert end "[lindex $cov_point 0]\n" td_uncov_colorMap .assertwin.f.tc insert end "[lindex $cov_point 1]\n" {tc_uncov_colorMap tc_uncov_uline} } } else { .assertwin.f.td insert end "[lindex $cov_point 0]\n" td_cov_colorMap .assertwin.f.tc insert end "[lindex $cov_point 1]\n" tc_cov_colorMap } } # Bind uncovered coverage points .assertwin.f.tc tag bind tc_uncov_uline { set curr_cursor [.assertwin.f.tc cget -cursor] set curr_info [.assertwin.f.info cget -text] .assertwin.f.tc configure -cursor hand2 .assertwin.f.info configure -text "Click the left button to exclude/include coverage point" } .assertwin.f.tc tag bind tc_uncov_uline { .assertwin.f.tc configure -cursor $curr_cursor .assertwin.f.info configure -text $curr_info } .assertwin.f.tc tag bind tc_uncov_uline { set curr_index [expr [lindex [split [.assertwin.f.tc index current] .] 0] - 1] set curr_exp [lindex [lindex $assert_cov_points $curr_index] 2] if {[lindex [lindex $assert_cov_points $curr_index] 3] == 0} { set curr_excl 1 } else { set curr_excl 0 } set assert_reason "" if {$exclude_reasons_enabled == 1 && $curr_excl == 1} { set assert_reason [get_exclude_reason .assertwin] } tcl_func_set_assert_exclude $curr_block $curr_assert_inst $curr_exp $curr_excl $assert_reason set text_x [.bot.right.txt xview] set text_y [.bot.right.txt yview] process_assert_cov .bot.right.txt xview moveto [lindex $text_x 0] .bot.right.txt yview moveto [lindex $text_y 0] populate_listbox enable_cdd_save set_pointer curr_assert_ptr $curr_assert_ptr create_assert_window $curr_assert_inst } .assertwin.f.tc tag bind tc_uncov_uline { set curr_index [expr [lindex [split [.assertwin.f.tc index current] .] 0] - 1] set assert_excluded [lindex [lindex $assert_cov_points $curr_index] 3] set assert_reason [lindex [lindex $assert_cov_points $curr_index] 4] if {$assert_excluded == 1 && $assert_reason != ""} { balloon::show .assertwin.f.tc "Exclude Reason: $assert_reason" $cov_bgColor $cov_fgColor } } .assertwin.f.tc tag bind tc_uncov_uline { set curr_index [expr [lindex [split [.assertwin.f.tc index current] .] 0] - 1] set assert_excluded [lindex [lindex $assert_cov_points $curr_index] 3] set assert_reason [lindex [lindex $assert_cov_points $curr_index] 4] if {$assert_excluded == 1 && $assert_reason != ""} { balloon::hide .assertwin.f.tc } } # Keep user from writing in text boxes .assertwin.f.td configure -state disabled .assertwin.f.tc configure -state disabled # Update informational bar .assertwin.f.info configure -text "Assertion module: [lindex $assert_cov_mod 0]" # Raise this window to the foreground raise .assertwin } # Updates the GUI elements of the assertion window when some type of event causes the # current metric mode to change. proc update_assert {} { global cov_rb prev_assert_index next_assert_index curr_assert_ptr # If the combinational window exists, update the GUI if {[winfo exists .assertwin] == 1} { # If the current metric mode is not assert, disable the prev/next buttons if {$cov_rb != "Assert"} { .assertwin.bf.prev configure -state disabled .assertwin.bf.next configure -state disabled } else { # Restore the pointer if it is set set_pointer curr_assert_ptr $curr_assert_ptr # Restore the previous/next button enables if {$prev_assert_index != ""} { .assertwin.bf.prev configure -state normal } else { .assertwin.bf.prev configure -state disabled } if {$next_assert_index != ""} { .assertwin.bf.next configure -state normal } else { .assertwin.bf.next configure -state disabled } } } } proc clear_assert {} { global curr_assert_ptr # Reset the variables set curr_assert_ptr "" # Destroy the window destroy .assertwin } proc display_assertion_module {name filename} { global open_files if {[winfo exists .amodwin] == 0} { set open_files "" # Create the window viewer toplevel .amodwin set assert_filename [file normalize [file join [tcl_func_get_score_path] $filename]] wm title .amodwin "Assertion Module - $name ($assert_filename)" # Create text viewer windows ttk::frame .amodwin.f -relief raised -borderwidth 1 text .amodwin.f.t -height 30 -width 80 -xscrollcommand ".amodwin.f.hb set" -yscrollcommand ".amodwin.f.vb set" -state disabled ttk::scrollbar .amodwin.f.hb -orient horizontal -command ".amodwin.f.t xview" ttk::scrollbar .amodwin.f.vb -command ".amodwin.f.t yview" ttk::label .amodwin.f.info -anchor w # Layout the text viewer windows grid rowconfigure .amodwin.f 0 -weight 1 grid columnconfigure .amodwin.f 0 -weight 1 grid .amodwin.f.t -row 0 -column 0 -sticky news grid .amodwin.f.vb -row 0 -column 1 -sticky news grid .amodwin.f.hb -row 1 -column 0 -sticky news grid .amodwin.f.info -row 2 -column 0 -columnspan 2 -sticky we # Create the button bar ttk::frame .amodwin.bf -relief raised -borderwidth 1 ttk::button .amodwin.bf.back -text "Back" -width 10 -command { set fname [lindex $open_files 1] set open_files [lreplace $open_files 0 1] populate_assertion_text $fname } -state disabled ttk::button .amodwin.bf.close -text "Close" -width 10 -command { destroy .amodwin } help_button .amodwin.bf.help chapter.gui.assert.source # Pack the button bar pack .amodwin.bf.back -side left -padx 3 -pady 3 pack .amodwin.bf.help -side right -pady 3 pack .amodwin.bf.close -side right -padx 3 -pady 3 # Pack the frames pack .amodwin.f -fill both -expand yes pack .amodwin.bf -fill x } # Write the module information populate_assertion_text $filename # Raise this window to the foreground raise .amodwin } proc populate_assertion_text {fname} { global fileContent open_files # Add the specified file name to the open_files array set open_files [linsert $open_files 0 $fname] # Set the state of the back button accordingly if {[llength $open_files] < 2} { .amodwin.bf.back configure -state disabled } else { .amodwin.bf.back configure -state normal } # Read in the specified filename load_verilog $fname 0 # Allow us to write to the text box .amodwin.f.t configure -state normal # Clear the text-box before any insertion is being made .amodwin.f.t delete 1.0 end set contents [split $fileContent($fname) \n] # Populate text box with file contents foreach phrase $contents { .amodwin.f.t insert end [append phrase "\n"] } # Perform highlighting verilog_highlight .amodwin.f.t # Take care of any included files handle_verilog_includes .amodwin.f.t .amodwin.f.info populate_assertion_text # Set state back to disabled for read-only access .amodwin.f.t configure -state disabled } # Saves the contents of the assertion detailed window for later usage proc save_assert_gui_elements {main_exit} { global assert_geometry assert_gui_saved if {$assert_gui_saved == 0} { if {$main_exit == 0 || [winfo exists .assertwin] == 1} { set assert_gui_saved 1 set assert_geometry [winfo geometry .assertwin] } } } covered-0.7.10/scripts/balloon.tcl0000644000076500007650000000353711061413764017076 0ustar trevorwtrevorwnamespace eval balloon { variable long_delay 750 variable short_delay 50 variable off_delay 5000 variable delay $long_delay variable family {} variable after_id {} } bind . { if {$show_tooltips == true} { if {$balloon::family != ""} { if {[lsearch -exact $balloon::family %W] == -1} { set balloon::family {} set balloon::delay $balloon::long_delay } } } } proc balloon_show {w help} { global show_tooltips if {$show_tooltips == true} { set balloon::after_id [after $balloon::delay [list balloon::show $w $help]] set balloon::delay $balloon::short_delay set balloon::family [balloon::getwfamily $w] set balloon::after_id [after $balloon::off_delay destroy $w.balloon] } } proc balloon_destroy {w} { global show_tooltips if {$show_tooltips == true} { balloon::hide $w } } proc set_balloon {w help} { bind $w "+balloon_show %W [list $help]" bind $w "+balloon_destroy %W" bind $w

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