crystalhd-0.0~git20110715.fdd2f19/0000755000175000017500000000000011610313111015525 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/include/0000755000175000017500000000000011610313111017150 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/include/bc_dts_types.h0000644000175000017500000000330211610313111022001 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: bc_dts_types.h * * Description: Data types * * AU * * HISTORY: * ******************************************************************** * This header is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This header is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this header. If not, see . *******************************************************************/ #ifndef _BC_DTS_TYPES_H_ #define _BC_DTS_TYPES_H_ //#ifdef __LINUX_USER__ /* Don't include these for KERNEL.. */ #if !defined(__KERNEL__) #include #endif #ifndef PVOID typedef void *PVOID; #endif #ifndef BOOL typedef int BOOL; #endif //#ifdef __LINUX_USER__ /* Don't include these for KERNEL */ #if !defined(__KERNEL__) typedef uint32_t ULONG; typedef int32_t LONG; typedef void *HANDLE; #ifndef VOID typedef void VOID; #endif typedef void *LPVOID; typedef uint32_t DWORD; typedef uint32_t UINT32; typedef uint32_t *LPDWORD; typedef unsigned char *PUCHAR; #ifndef TRUE #define TRUE 1 #endif #ifndef FALSE #define FALSE 0 #endif #else /* !__KERNEL__ */ /* For Kernel usage.. */ typedef bool bc_bool_t; #endif /* __KERNEL__ */ #endif crystalhd-0.0~git20110715.fdd2f19/include/bc_decoder_regs.h0000644000175000017500000001450411610313111022416 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: bc_decoder_regs.h * * Description: Common definitions for all components. Only types * is allowed to be included from this file. * * AU * * HISTORY: * ******************************************************************** * This header is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This header is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this header. If not, see . *******************************************************************/ #ifndef _INCLUDE_DECO_REGS_H_ #define _INCLUDE_DECO_REGS_H_ #include "bc_dts_types.h" // These are SDRAM specific registers #define SDRAM_PARAM 0x00040804 #define SDRAM_REF_PARAM 0x00040808 #define SDRAM_REFRESH 0x00040890 #define SDRAM_MODE 0x000408A0 #define SDRAM_EXT_MODE 0x000408A4 #define SDRAM_PRECHARGE 0x000408B0 #define SDRAM_INC 0x00040800 // Registers to access the DRAM #define TOTAL_DRAM_SIZE (64 * 1024 * 1024) // We are using 64MB of DRAM #define DRAM_ACCESS_GRANUALITY 4 // We will always access DRAM ULONG by ULONG. #define DRAM_WINDOW_SIZE (512 * 1024) // 512 K. #define DRAM_WINDOW_BASE 0x00340020 // DRAM Address to access 512K Size of data. #define DRAM_SHADOW_DATA_START 0x00380000 // Start of 512 K of window for shadow data. #define DRAM_SHADOW_DATA_END 0x003FFFFF // End of 512 K of window for shadow data. #define AUD_DSP_MISC_SOFT_RESET 0x00240104 #define AIO_MISC_PLL_RESET 0x0026000C // // To Reset the controller // #define DEC_HOST_SW_RESET 0x00340000 /* Register Map */ #define TS_Host2CpuSnd 0x00000100 #define Hst2CpuMbx1 0x00100F00 #define Cpu2HstMbx1 0x00100F04 #define MbxStat1 0x00100F08 #define Stream2Host_Intr_Sts 0x00100F24 typedef union _STREAM_TO_HOST_INTR_STS_{ struct { ULONG Res1:1; /* Reserved */ ULONG VideoSetupOut0:1; /* Video Setup Intr Occured at port0. This means that the picture is ready to be displayed */ ULONG VideoReleaseOut0:1; /* Video Release Intr Occured at port0. This means that picture is almost Done */ ULONG AsynchEvent:1; /* Video Setup Intr Occured at port1. This means that the picture is ready to be displayed */ ULONG Res2:1; /* Reserved */ ULONG PicAvailIn0:1; /* PIC Avail Interrupt at port 0*/ ULONG PicAvailIn1:1; /* PIC Avail Interrupt at port 1*/ ULONG CRCDataAvail0:1; /* Intr Occured from Stream Entering at port 0*/ ULONG Res3:1; /* Reserved */ ULONG UserDataAvail0:1; /* User Data Intr occured for stream entring at port 0*/ ULONG NewPCROffset:1; /* New PCR offset Intr Occured*/ ULONG ErrNotify:1; /* An Err Notify Intr Occured*/ ULONG HostDMAComplete:1; /* PCI Host Dma Interrupt occured*/ ULONG AudioDecService:1; /* Audio Decoder Intr Occured*/ ULONG InitalPTS:1; /* First Presentation Time Stamp recieved. Host should then write a new STC when in playback mode*/ ULONG PTSDisc:1; /* A PTS discontinuity has occured*/ ULONG Resv4:15; /* Reserved*/ ULONG MailboxIntr:1; /* A Command Respose Mailbox interrupt occured */ }; ULONG WholeReg; /* If you want to access whole register without the bitmap*/ }STRTOHOST_INTR_STS,*PSTRTOHOST_INTR_STS; #define REG_DecCA_RegCinBase 0xa0c #define REG_DecCA_RegCinEnd 0xa10 #define REG_DecCA_RegCinWrPtr 0xa04 #define REG_DecCA_RegCinRdPtr 0xa08 /* TS case.. */ #define REG_Dec_TsUser0Base 0x100864 #define REG_Dec_TsUser0Rdptr 0x100868 #define REG_Dec_TsUser0Wrptr 0x10086C #define REG_Dec_TsUser0Len 0x100870 #define REG_Dec_TsUser0End 0x100874 #define REG_Dec_TsUser0Empty 0x100878 /* ASF Case ...*/ #define REG_Dec_TsAudCDB2Base 0x10036c #define REG_Dec_TsAudCDB2Rdptr 0x100378 #define REG_Dec_TsAudCDB2Wrptr 0x100374 #define REG_Dec_TsAudCDB2End 0x100370 // ----------- registers and bits for master mode DMA bursts into // ----------- block mode code-in port // -- code in block addresses #define BCMPCI_HOST_STREAMA_WINDOW_BASE 0x340200 #define BCMPVI_HOST_STREAMA_WINDOW_END 0x34023f // -- DMA registers #define BCMPCI_DMA_CHAN0_SRC 0x340100 #define BCMPCI_DMA_CHAN0_DEST 0x340104 #define BCMPCI_DMA_CHAN0_CTL 0x340108 #define BCMPCI_ICR 0x0001ec // -- bits in control register // read only status #define BCMPCI_IS_DMA_ACTIVE 0x80000000 #define BCMPCI_IS_DMA_ERROR 0x40000000 #define BCMPCI_IS_DMA_INT 0x20000000 // control bits #define BCMPCI_IS_LOCAL_SDRAM 0x400000 #define BCMPCI_INC_DST 0x200000 #define BCMPCI_INC_SRC 0x100000 // bit mask denoting area containing number of bytes to transfer #define BCMPCI_DMA_BYTES_MASK 0xfffff #define VectorTbl1 (UINT32) 0x00100F0C #define CpuDbg1 (UINT32) 0x00141010 #define AuxRegs1 (UINT32) 0x00145000 #define INIT_VEC1 (UINT32) 0x00000000 #define UartSelectA (UINT32) 0x00100300 #define UartSelectB (UINT32) 0x00100304 #define DecHt_HostSwReset (UINT32) 0x340000 #define TSHostStreamA 0x34002c #define StrTRA_TsFifoStatus 0x10044c #define DecHt_PllACtl 0x34000C #define DecHt_PllBCtl 0x340010 #define DecHt_PllCCtl 0x340014 #define DecHt_PllDCtl 0x340034 #define DecHt_PllECtl 0x340038 #define DQS_CTL_REGISTER 0x00040700 #define DDR_DRIVER_CTL_REGISTER 0x00040704 typedef union _DQS_CTL_REG_ { struct{ ULONG DQS0_DELAY:4; ULONG DQS1_DELAY:4; ULONG DQS2_DELAY:4; ULONG DQS3_DELAY:4; ULONG PULSE_WIDTH:4; ULONG MHZ:4; ULONG OV:1; ULONG SEN:1; ULONG CL25:1; ULONG RSV:5; }; ULONG WholeReg; } DQS_CTL_REG; typedef union _DDR_DRIVER_CTL_REG_ { struct{ ULONG DDQ:2; ULONG SDQ:2; ULONG CL2DQ:1; ULONG RSV:3; ULONG DCTL:2; ULONG SCTL:2; ULONG CL2CTL:1; ULONG RSV1:3; ULONG RSV2:16; }; ULONG WholeReg; } DDR_DRIVER_CTL_REG; #define HALF_EMPTY_BIT 0x80 #define FIFO_HALF_EMPTY(a)\ (a & HALF_EMPTY_BIT ) #define FULL_BIT 0x20 #define FIFO_FULL(a)\ (a & FULL_BIT) #endif crystalhd-0.0~git20110715.fdd2f19/include/link/0000755000175000017500000000000011610313111020105 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/include/link/bc_defines.h0000644000175000017500000000352111610313111022340 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: bc_defines.h * * Description: Driver Interface library Internal. * * AU * * HISTORY: * ******************************************************************** * This header is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This header is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this header. If not, see . *******************************************************************/ #ifndef _BC_DEFINES_ #define _BC_DEFINES_ //The AES and DCI H/W engines are big endian and hence the DATA needs to be //byte swapped when loading the data registers in this block #define rotr32_1(x,n) (((x) >> n) | ((x) << (32 - n))) #define bswap_32_1(x) ((rotr32_1((x), 24) & 0x00ff00ff) | (rotr32_1((x), 8) & 0xff00ff00)) #define DCI_INITIATE_FW_DOWNLOAD (0x1) //bit 0 #define DCI_DOWNLOAD_READY (0x1<<4) //bit 4 #define DCI_DOWNLOAD_COMPLETE (0x1<<1) //bit 2 #define DCI_FIRMWARE_VALIDATED (0x1) //bit 0 #define DCI_SIGNATURE_MATCHED (0x1<<9) //bit 9 #define DCI_SIGNATURE_MISMATCH (0x1<<8) //bit 8 #define DCI_START_PROCESSOR (0x10) //bit 4 #define OTP_KEYS_AVAIL (0x1<<1) #define AES_PREPARE_ENCRYPTION (0x1<<4) #define AES_PREPARE_DONE (0x1<<4) #define AES_WRITE_EEPROM (0x1<<12) #define AES_WRITE_DONE (0x1<<12) #define AES_RANDOM_READY (0x1<<20) #endif crystalhd-0.0~git20110715.fdd2f19/include/link/bcm_70012_regs.h0000644000175000017500000261314011610313111022577 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation. * * Name: bcm_70012_regs.h * * Description: BCM70012 registers * ******************************************************************** * This header is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This header is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this header. If not, see . ***************************************************************************/ #ifndef MACFILE_H__ #define MACFILE_H__ /** * m = memory, c = core, r = register, f = field, d = data. */ #if !defined(GET_FIELD) && !defined(SET_FIELD) #define BRCM_ALIGN(c, r, f) c##_##r##_##f##_ALIGN #define BRCM_BITS(c, r, f) c##_##r##_##f##_BITS #define BRCM_MASK(c, r, f) c##_##r##_##f##_MASK #define BRCM_SHIFT(c, r, f) c##_##r##_##f##_SHIFT #define GET_FIELD(m, c, r, f) \ ((((m) & BRCM_MASK(c, r, f)) >> BRCM_SHIFT(c, r, f)) << BRCM_ALIGN(c, r, f)) #define SET_FIELD(m, c, r, f, d) \ ((m) = (((m) & ~BRCM_MASK(c, r, f)) | ((((d) >> BRCM_ALIGN(c, r, f)) << \ BRCM_SHIFT(c, r, f)) & BRCM_MASK(c, r, f))) \ ) #define SET_TYPE_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, c##_##d) #define SET_NAME_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, c##_##r##_##f##_##d) #define SET_VALUE_FIELD(m, c, r, f, d) SET_FIELD(m, c, r, f, d) #endif /* GET & SET */ /**************************************************************************** * Core Enums. ***************************************************************************/ /**************************************************************************** * Enums: AES_RGR_BRIDGE_RESET_CTRL ***************************************************************************/ #define AES_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 #define AES_RGR_BRIDGE_RESET_CTRL_ASSERT 1 /**************************************************************************** * Enums: CCE_RGR_BRIDGE_RESET_CTRL ***************************************************************************/ #define CCE_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 #define CCE_RGR_BRIDGE_RESET_CTRL_ASSERT 1 /**************************************************************************** * Enums: DBU_RGR_BRIDGE_RESET_CTRL ***************************************************************************/ #define DBU_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 #define DBU_RGR_BRIDGE_RESET_CTRL_ASSERT 1 /**************************************************************************** * Enums: DCI_RGR_BRIDGE_RESET_CTRL ***************************************************************************/ #define DCI_RGR_BRIDGE_RESET_CTRL_DEASSERT 0 #define DCI_RGR_BRIDGE_RESET_CTRL_ASSERT 1 /**************************************************************************** * Enums: GISB_ARBITER_DEASSERT_ASSERT ***************************************************************************/ #define GISB_ARBITER_DEASSERT_ASSERT_DEASSERT 0 #define GISB_ARBITER_DEASSERT_ASSERT_ASSERT 1 /**************************************************************************** * Enums: GISB_ARBITER_UNMASK_MASK ***************************************************************************/ #define GISB_ARBITER_UNMASK_MASK_UNMASK 0 #define GISB_ARBITER_UNMASK_MASK_MASK 1 /**************************************************************************** * Enums: GISB_ARBITER_DISABLE_ENABLE ***************************************************************************/ #define GISB_ARBITER_DISABLE_ENABLE_DISABLE 0 #define GISB_ARBITER_DISABLE_ENABLE_ENABLE 1 /**************************************************************************** * Enums: I2C_GR_BRIDGE_RESET_CTRL ***************************************************************************/ #define I2C_GR_BRIDGE_RESET_CTRL_DEASSERT 0 #define I2C_GR_BRIDGE_RESET_CTRL_ASSERT 1 /**************************************************************************** * Enums: MISC_GR_BRIDGE_RESET_CTRL ***************************************************************************/ #define MISC_GR_BRIDGE_RESET_CTRL_DEASSERT 0 #define MISC_GR_BRIDGE_RESET_CTRL_ASSERT 1 /**************************************************************************** * Enums: OTP_GR_BRIDGE_RESET_CTRL ***************************************************************************/ #define OTP_GR_BRIDGE_RESET_CTRL_DEASSERT 0 #define OTP_GR_BRIDGE_RESET_CTRL_ASSERT 1 /**************************************************************************** * BCM70012_TGT_TOP_PCIE_CFG ***************************************************************************/ #define PCIE_CFG_DEVICE_VENDOR_ID 0x00000000 /* DEVICE_VENDOR_ID Register */ #define PCIE_CFG_STATUS_COMMAND 0x00000004 /* STATUS_COMMAND Register */ #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID 0x00000008 /* PCI_CLASSCODE_AND_REVISION_ID Register */ #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE 0x0000000c /* BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE Register */ #define PCIE_CFG_BASE_ADDRESS_1 0x00000010 /* BASE_ADDRESS_1 Register */ #define PCIE_CFG_BASE_ADDRESS_2 0x00000014 /* BASE_ADDRESS_2 Register */ #define PCIE_CFG_BASE_ADDRESS_3 0x00000018 /* BASE_ADDRESS_3 Register */ #define PCIE_CFG_BASE_ADDRESS_4 0x0000001c /* BASE_ADDRESS_4 Register */ #define PCIE_CFG_CARDBUS_CIS_POINTER 0x00000028 /* CARDBUS_CIS_POINTER Register */ #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID 0x0000002c /* SUBSYSTEM_DEVICE_VENDOR_ID Register */ #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS 0x00000030 /* EXPANSION_ROM_BASE_ADDRESS Register */ #define PCIE_CFG_CAPABILITIES_POINTER 0x00000034 /* CAPABILITIES_POINTER Register */ #define PCIE_CFG_INTERRUPT 0x0000003c /* INTERRUPT Register */ #define PCIE_CFG_VPD_CAPABILITIES 0x00000040 /* VPD_CAPABILITIES Register */ #define PCIE_CFG_VPD_DATA 0x00000044 /* VPD_DATA Register */ #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY 0x00000048 /* POWER_MANAGEMENT_CAPABILITY Register */ #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS 0x0000004c /* POWER_MANAGEMENT_CONTROL_STATUS Register */ #define PCIE_CFG_MSI_CAPABILITY_HEADER 0x00000050 /* MSI_CAPABILITY_HEADER Register */ #define PCIE_CFG_MSI_LOWER_ADDRESS 0x00000054 /* MSI_LOWER_ADDRESS Register */ #define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER 0x00000058 /* MSI_UPPER_ADDRESS_REGISTER Register */ #define PCIE_CFG_MSI_DATA 0x0000005c /* MSI_DATA Register */ #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER 0x00000060 /* BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER Register */ #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES 0x00000064 /* RESET_COUNTERS_INITIAL_VALUES Register */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL 0x00000068 /* MISCELLANEOUS_HOST_CONTROL Register */ #define PCIE_CFG_SPARE 0x0000006c /* SPARE Register */ #define PCIE_CFG_PCI_STATE 0x00000070 /* PCI_STATE Register */ #define PCIE_CFG_CLOCK_CONTROL 0x00000074 /* CLOCK_CONTROL Register */ #define PCIE_CFG_REGISTER_BASE 0x00000078 /* REGISTER_BASE Register */ #define PCIE_CFG_MEMORY_BASE 0x0000007c /* MEMORY_BASE Register */ #define PCIE_CFG_REGISTER_DATA 0x00000080 /* REGISTER_DATA Register */ #define PCIE_CFG_MEMORY_DATA 0x00000084 /* MEMORY_DATA Register */ #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE 0x00000088 /* EXPANSION_ROM_BAR_SIZE Register */ #define PCIE_CFG_EXPANSION_ROM_ADDRESS 0x0000008c /* EXPANSION_ROM_ADDRESS Register */ #define PCIE_CFG_EXPANSION_ROM_DATA 0x00000090 /* EXPANSION_ROM_DATA Register */ #define PCIE_CFG_VPD_INTERFACE 0x00000094 /* VPD_INTERFACE Register */ #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER 0x00000098 /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER Register */ #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER 0x0000009c /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER Register */ #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER 0x000000a0 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER Register */ #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER 0x000000a4 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER Register */ #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER 0x000000a8 /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER Register */ #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER 0x000000ac /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER Register */ #define PCIE_CFG_INT_MAILBOX_UPPER 0x000000b0 /* INT_MAILBOX_UPPER Register */ #define PCIE_CFG_INT_MAILBOX_LOWER 0x000000b4 /* INT_MAILBOX_LOWER Register */ #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION 0x000000bc /* PRODUCT_ID_AND_ASIC_REVISION Register */ #define PCIE_CFG_FUNCTION_EVENT 0x000000c0 /* FUNCTION_EVENT Register */ #define PCIE_CFG_FUNCTION_EVENT_MASK 0x000000c4 /* FUNCTION_EVENT_MASK Register */ #define PCIE_CFG_FUNCTION_PRESENT 0x000000c8 /* FUNCTION_PRESENT Register */ #define PCIE_CFG_PCIE_CAPABILITIES 0x000000cc /* PCIE_CAPABILITIES Register */ #define PCIE_CFG_DEVICE_CAPABILITIES 0x000000d0 /* DEVICE_CAPABILITIES Register */ #define PCIE_CFG_DEVICE_STATUS_CONTROL 0x000000d4 /* DEVICE_STATUS_CONTROL Register */ #define PCIE_CFG_LINK_CAPABILITY 0x000000d8 /* LINK_CAPABILITY Register */ #define PCIE_CFG_LINK_STATUS_CONTROL 0x000000dc /* LINK_STATUS_CONTROL Register */ #define PCIE_CFG_DEVICE_CAPABILITIES_2 0x000000f0 /* DEVICE_CAPABILITIES_2 Register */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_2 0x000000f4 /* DEVICE_STATUS_CONTROL_2 Register */ #define PCIE_CFG_LINK_CAPABILITIES_2 0x000000f8 /* LINK_CAPABILITIES_2 Register */ #define PCIE_CFG_LINK_STATUS_CONTROL_2 0x000000fc /* LINK_STATUS_CONTROL_2 Register */ #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER 0x00000100 /* ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER Register */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS 0x00000104 /* UNCORRECTABLE_ERROR_STATUS Register */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK 0x00000108 /* UNCORRECTABLE_ERROR_MASK Register */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY 0x0000010c /* UNCORRECTABLE_ERROR_SEVERITY Register */ #define PCIE_CFG_CORRECTABLE_ERROR_STATUS 0x00000110 /* CORRECTABLE_ERROR_STATUS Register */ #define PCIE_CFG_CORRECTABLE_ERROR_MASK 0x00000114 /* CORRECTABLE_ERROR_MASK Register */ #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL 0x00000118 /* ADVANCED_ERROR_CAPABILITIES_AND_CONTROL Register */ #define PCIE_CFG_HEADER_LOG_1 0x0000011c /* HEADER_LOG_1 Register */ #define PCIE_CFG_HEADER_LOG_2 0x00000120 /* HEADER_LOG_2 Register */ #define PCIE_CFG_HEADER_LOG_3 0x00000124 /* HEADER_LOG_3 Register */ #define PCIE_CFG_HEADER_LOG_4 0x00000128 /* HEADER_LOG_4 Register */ #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER 0x0000013c /* VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER Register */ #define PCIE_CFG_PORT_VC_CAPABILITY 0x00000140 /* PORT_VC_CAPABILITY Register */ #define PCIE_CFG_PORT_VC_CAPABILITY_2 0x00000144 /* PORT_VC_CAPABILITY_2 Register */ #define PCIE_CFG_PORT_VC_STATUS_CONTROL 0x00000148 /* PORT_VC_STATUS_CONTROL Register */ #define PCIE_CFG_VC_RESOURCE_CAPABILITY 0x0000014c /* VC_RESOURCE_CAPABILITY Register */ #define PCIE_CFG_VC_RESOURCE_CONTROL 0x00000150 /* VC_RESOURCE_CONTROL Register */ #define PCIE_CFG_VC_RESOURCE_STATUS 0x00000154 /* VC_RESOURCE_STATUS Register */ #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER 0x00000160 /* DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER Register */ #define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW 0x00000164 /* DEVICE_SERIAL_NO_LOWER_DW Register */ #define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW 0x00000168 /* DEVICE_SERIAL_NO_UPPER_DW Register */ #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER 0x0000016c /* POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER Register */ #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT 0x00000170 /* POWER_BUDGETING_DATA_SELECT Register */ #define PCIE_CFG_POWER_BUDGETING_DATA 0x00000174 /* POWER_BUDGETING_DATA Register */ #define PCIE_CFG_POWER_BUDGETING_CAPABILITY 0x00000178 /* POWER_BUDGETING_CAPABILITY Register */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1 0x0000017c /* FIRMWARE_POWER_BUDGETING_2_1 Register */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3 0x00000180 /* FIRMWARE_POWER_BUDGETING_4_3 Register */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5 0x00000184 /* FIRMWARE_POWER_BUDGETING_6_5 Register */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7 0x00000188 /* FIRMWARE_POWER_BUDGETING_8_7 Register */ #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING 0x0000018c /* PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING Register */ /**************************************************************************** * BCM70012_TGT_TOP_PCIE_TL ***************************************************************************/ #define PCIE_TL_TL_CONTROL 0x00000400 /* TL_CONTROL Register */ #define PCIE_TL_TRANSACTION_CONFIGURATION 0x00000404 /* TRANSACTION_CONFIGURATION Register */ #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00000408 /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 0x0000040c /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 Register */ #define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00000410 /* DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ #define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 0x00000414 /* DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 Register */ #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC 0x00000418 /* DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC Register */ #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC 0x0000041c /* DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC Register */ #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC 0x00000420 /* READ_DMA_SPLIT_IDS_DIAGNOSTIC Register */ #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC 0x00000424 /* READ_DMA_SPLIT_LENGTH_DIAGNOSTIC Register */ #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC 0x0000043c /* XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC Register */ #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC 0x00000458 /* DMA_COMPLETION_MISC__DIAGNOSTIC Register */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC 0x0000045c /* SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC Register */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC 0x00000460 /* SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC Register */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC 0x00000464 /* SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC Register */ #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO 0x00000468 /* TL_BUS_NO_DEV__NO__FUNC__NO Register */ #define PCIE_TL_TL_DEBUG 0x0000046c /* TL_DEBUG Register */ /**************************************************************************** * BCM70012_TGT_TOP_PCIE_DLL ***************************************************************************/ #define PCIE_DLL_DATA_LINK_CONTROL 0x00000500 /* DATA_LINK_CONTROL Register */ #define PCIE_DLL_DATA_LINK_STATUS 0x00000504 /* DATA_LINK_STATUS Register */ #define PCIE_DLL_DATA_LINK_ATTENTION 0x00000508 /* DATA_LINK_ATTENTION Register */ #define PCIE_DLL_DATA_LINK_ATTENTION_MASK 0x0000050c /* DATA_LINK_ATTENTION_MASK Register */ #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000510 /* NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000514 /* ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00000518 /* PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG 0x0000051c /* RECEIVE_SEQUENCE_NUMBER_DEBUG Register */ #define PCIE_DLL_DATA_LINK_REPLAY 0x00000520 /* DATA_LINK_REPLAY Register */ #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT 0x00000524 /* DATA_LINK_ACK_TIMEOUT Register */ #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD 0x00000528 /* POWER_MANAGEMENT_THRESHOLD Register */ #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG 0x0000052c /* RETRY_BUFFER_WRITE_POINTER_DEBUG Register */ #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG 0x00000530 /* RETRY_BUFFER_READ_POINTER_DEBUG Register */ #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG 0x00000534 /* RETRY_BUFFER_PURGED_POINTER_DEBUG Register */ #define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT 0x00000538 /* RETRY_BUFFER_READ_WRITE_DEBUG_PORT Register */ #define PCIE_DLL_ERROR_COUNT_THRESHOLD 0x0000053c /* ERROR_COUNT_THRESHOLD Register */ #define PCIE_DLL_TL_ERROR_COUNTER 0x00000540 /* TL_ERROR_COUNTER Register */ #define PCIE_DLL_DLLP_ERROR_COUNTER 0x00000544 /* DLLP_ERROR_COUNTER Register */ #define PCIE_DLL_NAK_RECEIVED_COUNTER 0x00000548 /* NAK_RECEIVED_COUNTER Register */ #define PCIE_DLL_DATA_LINK_TEST 0x0000054c /* DATA_LINK_TEST Register */ #define PCIE_DLL_PACKET_BIST 0x00000550 /* PACKET_BIST Register */ #define PCIE_DLL_LINK_PCIE_1_1_CONTROL 0x00000554 /* LINK_PCIE_1_1_CONTROL Register */ /**************************************************************************** * BCM70012_TGT_TOP_PCIE_PHY ***************************************************************************/ #define PCIE_PHY_PHY_MODE 0x00000600 /* TYPE_PHY_MODE Register */ #define PCIE_PHY_PHY_LINK_STATUS 0x00000604 /* TYPE_PHY_LINK_STATUS Register */ #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL 0x00000608 /* TYPE_PHY_LINK_LTSSM_CONTROL Register */ #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER 0x0000060c /* TYPE_PHY_LINK_TRAINING_LINK_NUMBER Register */ #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER 0x00000610 /* TYPE_PHY_LINK_TRAINING_LANE_NUMBER Register */ #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS 0x00000614 /* TYPE_PHY_LINK_TRAINING_N_FTS Register */ #define PCIE_PHY_PHY_ATTENTION 0x00000618 /* TYPE_PHY_ATTENTION Register */ #define PCIE_PHY_PHY_ATTENTION_MASK 0x0000061c /* TYPE_PHY_ATTENTION_MASK Register */ #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER 0x00000620 /* TYPE_PHY_RECEIVE_ERROR_COUNTER Register */ #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER 0x00000624 /* TYPE_PHY_RECEIVE_FRAMING_ERROR_COUNTER Register */ #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD 0x00000628 /* TYPE_PHY_RECEIVE_ERROR_THRESHOLD Register */ #define PCIE_PHY_PHY_TEST_CONTROL 0x0000062c /* TYPE_PHY_TEST_CONTROL Register */ #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE 0x00000630 /* TYPE_PHY_SERDES_CONTROL_OVERRIDE Register */ #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE 0x00000634 /* TYPE_PHY_TIMING_PARAMETER_OVERRIDE Register */ #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES 0x00000638 /* TYPE_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES Register */ #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES 0x0000063c /* TYPE_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES Register */ /**************************************************************************** * BCM70012_TGT_TOP_INTR ***************************************************************************/ #define INTR_INTR_STATUS 0x00000700 /* Interrupt Status Register */ #define INTR_INTR_SET 0x00000704 /* Interrupt Set Register */ #define INTR_INTR_CLR_REG 0x00000708 /* Interrupt Clear Register */ #define INTR_INTR_MSK_STS_REG 0x0000070c /* Interrupt Mask Status Register */ #define INTR_INTR_MSK_SET_REG 0x00000710 /* Interrupt Mask Set Register */ #define INTR_INTR_MSK_CLR_REG 0x00000714 /* Interrupt Mask Clear Register */ #define INTR_EOI_CTRL 0x00000720 /* End of interrupt control register */ /**************************************************************************** * BCM70012_TGT_TOP_MDIO ***************************************************************************/ #define MDIO_CTRL0 0x00000730 /* PCIE Serdes MDIO Control Register 0 */ #define MDIO_CTRL1 0x00000734 /* PCIE Serdes MDIO Control Register 1 */ #define MDIO_CTRL2 0x00000738 /* PCIE Serdes MDIO Control Register 2 */ /**************************************************************************** * BCM70012_TGT_TOP_TGT_RGR_BRIDGE ***************************************************************************/ #define TGT_RGR_BRIDGE_REVISION 0x00000740 /* PCIE RGR Bridge Revision Register */ #define TGT_RGR_BRIDGE_CTRL 0x00000744 /* RGR Bridge Control Register */ #define TGT_RGR_BRIDGE_RBUS_TIMER 0x00000748 /* RGR Bridge RBUS Timer Register */ #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0 0x0000074c /* RGR Bridge Spare Software Reset 0 Register */ #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1 0x00000750 /* RGR Bridge Spare Software Reset 1 Register */ /**************************************************************************** * BCM70012_I2C_TOP_I2C ***************************************************************************/ #define I2C_CHIP_ADDRESS 0x00000800 /* I2C Chip Address And Read/Write Control */ #define I2C_DATA_IN0 0x00000804 /* I2C Write Data Byte 0 */ #define I2C_DATA_IN1 0x00000808 /* I2C Write Data Byte 1 */ #define I2C_DATA_IN2 0x0000080c /* I2C Write Data Byte 2 */ #define I2C_DATA_IN3 0x00000810 /* I2C Write Data Byte 3 */ #define I2C_DATA_IN4 0x00000814 /* I2C Write Data Byte 4 */ #define I2C_DATA_IN5 0x00000818 /* I2C Write Data Byte 5 */ #define I2C_DATA_IN6 0x0000081c /* I2C Write Data Byte 6 */ #define I2C_DATA_IN7 0x00000820 /* I2C Write Data Byte 7 */ #define I2C_CNT_REG 0x00000824 /* I2C Transfer Count Register */ #define I2C_CTL_REG 0x00000828 /* I2C Control Register */ #define I2C_IIC_ENABLE 0x0000082c /* I2C Read/Write Enable And Interrupt */ #define I2C_DATA_OUT0 0x00000830 /* I2C Read Data Byte 0 */ #define I2C_DATA_OUT1 0x00000834 /* I2C Read Data Byte 1 */ #define I2C_DATA_OUT2 0x00000838 /* I2C Read Data Byte 2 */ #define I2C_DATA_OUT3 0x0000083c /* I2C Read Data Byte 3 */ #define I2C_DATA_OUT4 0x00000840 /* I2C Read Data Byte 4 */ #define I2C_DATA_OUT5 0x00000844 /* I2C Read Data Byte 5 */ #define I2C_DATA_OUT6 0x00000848 /* I2C Read Data Byte 6 */ #define I2C_DATA_OUT7 0x0000084c /* I2C Read Data Byte 7 */ #define I2C_CTLHI_REG 0x00000850 /* I2C Control Register */ #define I2C_SCL_PARAM 0x00000854 /* I2C SCL Parameter Register */ /**************************************************************************** * BCM70012_I2C_TOP_I2C_GR_BRIDGE ***************************************************************************/ #define I2C_GR_BRIDGE_REVISION 0x00000be0 /* GR Bridge Revision */ #define I2C_GR_BRIDGE_CTRL 0x00000be4 /* GR Bridge Control Register */ #define I2C_GR_BRIDGE_SPARE_SW_RESET_0 0x00000be8 /* GR Bridge Software Reset 0 Register */ #define I2C_GR_BRIDGE_SPARE_SW_RESET_1 0x00000bec /* GR Bridge Software Reset 1 Register */ /**************************************************************************** * BCM70012_MISC_TOP_MISC1 ***************************************************************************/ #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0 0x00000c00 /* Tx DMA Descriptor List0 First Descriptor lower Address */ #define MISC1_TX_FIRST_DESC_U_ADDR_LIST0 0x00000c04 /* Tx DMA Descriptor List0 First Descriptor Upper Address */ #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1 0x00000c08 /* Tx DMA Descriptor List1 First Descriptor Lower Address */ #define MISC1_TX_FIRST_DESC_U_ADDR_LIST1 0x00000c0c /* Tx DMA Descriptor List1 First Descriptor Upper Address */ #define MISC1_TX_SW_DESC_LIST_CTRL_STS 0x00000c10 /* Tx DMA Software Descriptor List Control and Status */ #define MISC1_TX_DMA_ERROR_STATUS 0x00000c18 /* Tx DMA Engine Error Status */ #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR 0x00000c1c /* Tx DMA List0 Current Descriptor Lower Address */ #define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR 0x00000c20 /* Tx DMA List0 Current Descriptor Upper Address */ #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM 0x00000c24 /* Tx DMA List0 Current Descriptor Upper Address */ #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR 0x00000c28 /* Tx DMA List1 Current Descriptor Lower Address */ #define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR 0x00000c2c /* Tx DMA List1 Current Descriptor Upper Address */ #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM 0x00000c30 /* Tx DMA List1 Current Descriptor Upper Address */ #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0 0x00000c34 /* Y Rx Descriptor List0 First Descriptor Lower Address */ #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0 0x00000c38 /* Y Rx Descriptor List0 First Descriptor Upper Address */ #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1 0x00000c3c /* Y Rx Descriptor List1 First Descriptor Lower Address */ #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1 0x00000c40 /* Y Rx Descriptor List1 First Descriptor Upper Address */ #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS 0x00000c44 /* Y Rx Software Descriptor List Control and Status */ #define MISC1_Y_RX_ERROR_STATUS 0x00000c4c /* Y Rx Engine Error Status */ #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR 0x00000c50 /* Y Rx List0 Current Descriptor Lower Address */ #define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR 0x00000c54 /* Y Rx List0 Current Descriptor Upper Address */ #define MISC1_Y_RX_LIST0_CUR_BYTE_CNT 0x00000c58 /* Y Rx List0 Current Descriptor Byte Count */ #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR 0x00000c5c /* Y Rx List1 Current Descriptor Lower address */ #define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR 0x00000c60 /* Y Rx List1 Current Descriptor Upper address */ #define MISC1_Y_RX_LIST1_CUR_BYTE_CNT 0x00000c64 /* Y Rx List1 Current Descriptor Byte Count */ #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0 0x00000c68 /* UV Rx Descriptor List0 First Descriptor lower Address */ #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0 0x00000c6c /* UV Rx Descriptor List0 First Descriptor Upper Address */ #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1 0x00000c70 /* UV Rx Descriptor List1 First Descriptor Lower Address */ #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1 0x00000c74 /* UV Rx Descriptor List1 First Descriptor Upper Address */ #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS 0x00000c78 /* UV Rx Software Descriptor List Control and Status */ #define MISC1_UV_RX_ERROR_STATUS 0x00000c7c /* UV Rx Engine Error Status */ #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR 0x00000c80 /* UV Rx List0 Current Descriptor Lower Address */ #define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR 0x00000c84 /* UV Rx List0 Current Descriptor Upper Address */ #define MISC1_UV_RX_LIST0_CUR_BYTE_CNT 0x00000c88 /* UV Rx List0 Current Descriptor Byte Count */ #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR 0x00000c8c /* UV Rx List1 Current Descriptor Lower Address */ #define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR 0x00000c90 /* UV Rx List1 Current Descriptor Upper Address */ #define MISC1_UV_RX_LIST1_CUR_BYTE_CNT 0x00000c94 /* UV Rx List1 Current Descriptor Byte Count */ #define MISC1_DMA_DEBUG_OPTIONS_REG 0x00000c98 /* DMA Debug Options Register */ #define MISC1_READ_CHANNEL_ERROR_STATUS 0x00000c9c /* Read Channel Error Status */ #define MISC1_PCIE_DMA_CTRL 0x00000ca0 /* PCIE DMA Control Register */ /**************************************************************************** * BCM70012_MISC_TOP_MISC2 ***************************************************************************/ #define MISC2_GLOBAL_CTRL 0x00000d00 /* Global Control Register */ #define MISC2_INTERNAL_STATUS 0x00000d04 /* Internal Status Register */ #define MISC2_INTERNAL_STATUS_MUX_CTRL 0x00000d08 /* Internal Debug Mux Control */ #define MISC2_DEBUG_FIFO_LENGTH 0x00000d0c /* Debug FIFO Length */ /**************************************************************************** * BCM70012_MISC_TOP_MISC3 ***************************************************************************/ #define MISC3_RESET_CTRL 0x00000e00 /* Reset Control Register */ #define MISC3_BIST_CTRL 0x00000e04 /* BIST Control Register */ #define MISC3_BIST_STATUS 0x00000e08 /* BIST Status Register */ #define MISC3_RX_CHECKSUM 0x00000e0c /* Receive Checksum */ #define MISC3_TX_CHECKSUM 0x00000e10 /* Transmit Checksum */ #define MISC3_ECO_CTRL_CORE 0x00000e14 /* ECO Core Reset Control Register */ #define MISC3_CSI_TEST_CTRL 0x00000e18 /* CSI Test Control Register */ #define MISC3_HD_DVI_TEST_CTRL 0x00000e1c /* HD DVI Test Control Register */ /**************************************************************************** * BCM70012_MISC_TOP_MISC_PERST ***************************************************************************/ #define MISC_PERST_ECO_CTRL_PERST 0x00000e80 /* ECO PCIE Reset Control Register */ #define MISC_PERST_DECODER_CTRL 0x00000e84 /* Decoder Control Register */ #define MISC_PERST_CCE_STATUS 0x00000e88 /* Config Copy Engine Status */ #define MISC_PERST_PCIE_DEBUG 0x00000e8c /* PCIE Debug Control Register */ #define MISC_PERST_PCIE_DEBUG_STATUS 0x00000e90 /* PCIE Debug Status Register */ #define MISC_PERST_VREG_CTRL 0x00000e94 /* Voltage Regulator Control Register */ #define MISC_PERST_MEM_CTRL 0x00000e98 /* Memory Control Register */ #define MISC_PERST_CLOCK_CTRL 0x00000e9c /* Clock Control Register */ /**************************************************************************** * BCM70012_MISC_TOP_GISB_ARBITER ***************************************************************************/ #define GISB_ARBITER_REVISION 0x00000f00 /* GISB ARBITER REVISION */ #define GISB_ARBITER_SCRATCH 0x00000f04 /* GISB ARBITER Scratch Register */ #define GISB_ARBITER_REQ_MASK 0x00000f08 /* GISB ARBITER Master Request Mask Register */ #define GISB_ARBITER_TIMER 0x00000f0c /* GISB ARBITER Timer Value Register */ #define GISB_ARBITER_BP_CTRL 0x00000f10 /* GISB ARBITER Breakpoint Control Register */ #define GISB_ARBITER_BP_CAP_CLR 0x00000f14 /* GISB ARBITER Breakpoint Capture Clear Register */ #define GISB_ARBITER_BP_START_ADDR_0 0x00000f18 /* GISB ARBITER Breakpoint Start Address 0 Register */ #define GISB_ARBITER_BP_END_ADDR_0 0x00000f1c /* GISB ARBITER Breakpoint End Address 0 Register */ #define GISB_ARBITER_BP_READ_0 0x00000f20 /* GISB ARBITER Breakpoint Master Read Control 0 Register */ #define GISB_ARBITER_BP_WRITE_0 0x00000f24 /* GISB ARBITER Breakpoint Master Write Control 0 Register */ #define GISB_ARBITER_BP_ENABLE_0 0x00000f28 /* GISB ARBITER Breakpoint Enable 0 Register */ #define GISB_ARBITER_BP_START_ADDR_1 0x00000f2c /* GISB ARBITER Breakpoint Start Address 1 Register */ #define GISB_ARBITER_BP_END_ADDR_1 0x00000f30 /* GISB ARBITER Breakpoint End Address 1 Register */ #define GISB_ARBITER_BP_READ_1 0x00000f34 /* GISB ARBITER Breakpoint Master Read Control 1 Register */ #define GISB_ARBITER_BP_WRITE_1 0x00000f38 /* GISB ARBITER Breakpoint Master Write Control 1 Register */ #define GISB_ARBITER_BP_ENABLE_1 0x00000f3c /* GISB ARBITER Breakpoint Enable 1 Register */ #define GISB_ARBITER_BP_START_ADDR_2 0x00000f40 /* GISB ARBITER Breakpoint Start Address 2 Register */ #define GISB_ARBITER_BP_END_ADDR_2 0x00000f44 /* GISB ARBITER Breakpoint End Address 2 Register */ #define GISB_ARBITER_BP_READ_2 0x00000f48 /* GISB ARBITER Breakpoint Master Read Control 2 Register */ #define GISB_ARBITER_BP_WRITE_2 0x00000f4c /* GISB ARBITER Breakpoint Master Write Control 2 Register */ #define GISB_ARBITER_BP_ENABLE_2 0x00000f50 /* GISB ARBITER Breakpoint Enable 2 Register */ #define GISB_ARBITER_BP_START_ADDR_3 0x00000f54 /* GISB ARBITER Breakpoint Start Address 3 Register */ #define GISB_ARBITER_BP_END_ADDR_3 0x00000f58 /* GISB ARBITER Breakpoint End Address 3 Register */ #define GISB_ARBITER_BP_READ_3 0x00000f5c /* GISB ARBITER Breakpoint Master Read Control 3 Register */ #define GISB_ARBITER_BP_WRITE_3 0x00000f60 /* GISB ARBITER Breakpoint Master Write Control 3 Register */ #define GISB_ARBITER_BP_ENABLE_3 0x00000f64 /* GISB ARBITER Breakpoint Enable 3 Register */ #define GISB_ARBITER_BP_START_ADDR_4 0x00000f68 /* GISB ARBITER Breakpoint Start Address 4 Register */ #define GISB_ARBITER_BP_END_ADDR_4 0x00000f6c /* GISB ARBITER Breakpoint End Address 4 Register */ #define GISB_ARBITER_BP_READ_4 0x00000f70 /* GISB ARBITER Breakpoint Master Read Control 4 Register */ #define GISB_ARBITER_BP_WRITE_4 0x00000f74 /* GISB ARBITER Breakpoint Master Write Control 4 Register */ #define GISB_ARBITER_BP_ENABLE_4 0x00000f78 /* GISB ARBITER Breakpoint Enable 4 Register */ #define GISB_ARBITER_BP_START_ADDR_5 0x00000f7c /* GISB ARBITER Breakpoint Start Address 5 Register */ #define GISB_ARBITER_BP_END_ADDR_5 0x00000f80 /* GISB ARBITER Breakpoint End Address 5 Register */ #define GISB_ARBITER_BP_READ_5 0x00000f84 /* GISB ARBITER Breakpoint Master Read Control 5 Register */ #define GISB_ARBITER_BP_WRITE_5 0x00000f88 /* GISB ARBITER Breakpoint Master Write Control 5 Register */ #define GISB_ARBITER_BP_ENABLE_5 0x00000f8c /* GISB ARBITER Breakpoint Enable 5 Register */ #define GISB_ARBITER_BP_START_ADDR_6 0x00000f90 /* GISB ARBITER Breakpoint Start Address 6 Register */ #define GISB_ARBITER_BP_END_ADDR_6 0x00000f94 /* GISB ARBITER Breakpoint End Address 6 Register */ #define GISB_ARBITER_BP_READ_6 0x00000f98 /* GISB ARBITER Breakpoint Master Read Control 6 Register */ #define GISB_ARBITER_BP_WRITE_6 0x00000f9c /* GISB ARBITER Breakpoint Master Write Control 6 Register */ #define GISB_ARBITER_BP_ENABLE_6 0x00000fa0 /* GISB ARBITER Breakpoint Enable 6 Register */ #define GISB_ARBITER_BP_START_ADDR_7 0x00000fa4 /* GISB ARBITER Breakpoint Start Address 7 Register */ #define GISB_ARBITER_BP_END_ADDR_7 0x00000fa8 /* GISB ARBITER Breakpoint End Address 7 Register */ #define GISB_ARBITER_BP_READ_7 0x00000fac /* GISB ARBITER Breakpoint Master Read Control 7 Register */ #define GISB_ARBITER_BP_WRITE_7 0x00000fb0 /* GISB ARBITER Breakpoint Master Write Control 7 Register */ #define GISB_ARBITER_BP_ENABLE_7 0x00000fb4 /* GISB ARBITER Breakpoint Enable 7 Register */ #define GISB_ARBITER_BP_CAP_ADDR 0x00000fb8 /* GISB ARBITER Breakpoint Capture Address Register */ #define GISB_ARBITER_BP_CAP_DATA 0x00000fbc /* GISB ARBITER Breakpoint Capture Data Register */ #define GISB_ARBITER_BP_CAP_STATUS 0x00000fc0 /* GISB ARBITER Breakpoint Capture Status Register */ #define GISB_ARBITER_BP_CAP_MASTER 0x00000fc4 /* GISB ARBITER Breakpoint Capture GISB MASTER Register */ #define GISB_ARBITER_ERR_CAP_CLR 0x00000fc8 /* GISB ARBITER Error Capture Clear Register */ #define GISB_ARBITER_ERR_CAP_ADDR 0x00000fcc /* GISB ARBITER Error Capture Address Register */ #define GISB_ARBITER_ERR_CAP_DATA 0x00000fd0 /* GISB ARBITER Error Capture Data Register */ #define GISB_ARBITER_ERR_CAP_STATUS 0x00000fd4 /* GISB ARBITER Error Capture Status Register */ #define GISB_ARBITER_ERR_CAP_MASTER 0x00000fd8 /* GISB ARBITER Error Capture GISB MASTER Register */ /**************************************************************************** * BCM70012_MISC_TOP_MISC_GR_BRIDGE ***************************************************************************/ #define MISC_GR_BRIDGE_REVISION 0x00000fe0 /* GR Bridge Revision */ #define MISC_GR_BRIDGE_CTRL 0x00000fe4 /* GR Bridge Control Register */ #define MISC_GR_BRIDGE_SPARE_SW_RESET_0 0x00000fe8 /* GR Bridge Software Reset 0 Register */ #define MISC_GR_BRIDGE_SPARE_SW_RESET_1 0x00000fec /* GR Bridge Software Reset 1 Register */ /**************************************************************************** * BCM70012_DBU_TOP_DBU ***************************************************************************/ #define DBU_DBU_CMD 0x00001000 /* DBU (Debug UART) command register */ #define DBU_DBU_STATUS 0x00001004 /* DBU (Debug UART) status register */ #define DBU_DBU_CONFIG 0x00001008 /* DBU (Debug UART) configuration register */ #define DBU_DBU_TIMING 0x0000100c /* DBU (Debug UART) timing register */ #define DBU_DBU_RXDATA 0x00001010 /* DBU (Debug UART) recieve data register */ #define DBU_DBU_TXDATA 0x00001014 /* DBU (Debug UART) transmit data register */ /**************************************************************************** * BCM70012_DBU_TOP_DBU_RGR_BRIDGE ***************************************************************************/ #define DBU_RGR_BRIDGE_REVISION 0x000013e0 /* RGR Bridge Revision */ #define DBU_RGR_BRIDGE_CTRL 0x000013e4 /* RGR Bridge Control Register */ #define DBU_RGR_BRIDGE_RBUS_TIMER 0x000013e8 /* RGR Bridge RBUS Timer Register */ #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0 0x000013ec /* RGR Bridge Software Reset 0 Register */ #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1 0x000013f0 /* RGR Bridge Software Reset 1 Register */ /**************************************************************************** * BCM70012_OTP_TOP_OTP ***************************************************************************/ #define OTP_CONFIG_INFO 0x00001400 /* OTP Configuration Register */ #define OTP_CMD 0x00001404 /* OTP Command Register */ #define OTP_STATUS 0x00001408 /* OTP Status Register */ #define OTP_CONTENT_MISC 0x0000140c /* Content : Miscellaneous Register */ #define OTP_CONTENT_AES_0 0x00001410 /* Content : AES Key 0 Register */ #define OTP_CONTENT_AES_1 0x00001414 /* Content : AES Key 1 Register */ #define OTP_CONTENT_AES_2 0x00001418 /* Content : AES Key 2 Register */ #define OTP_CONTENT_AES_3 0x0000141c /* Content : AES Key 3 Register */ #define OTP_CONTENT_SHA_0 0x00001420 /* Content : SHA Key 0 Register */ #define OTP_CONTENT_SHA_1 0x00001424 /* Content : SHA Key 1 Register */ #define OTP_CONTENT_SHA_2 0x00001428 /* Content : SHA Key 2 Register */ #define OTP_CONTENT_SHA_3 0x0000142c /* Content : SHA Key 3 Register */ #define OTP_CONTENT_SHA_4 0x00001430 /* Content : SHA Key 4 Register */ #define OTP_CONTENT_SHA_5 0x00001434 /* Content : SHA Key 5 Register */ #define OTP_CONTENT_SHA_6 0x00001438 /* Content : SHA Key 6 Register */ #define OTP_CONTENT_SHA_7 0x0000143c /* Content : SHA Key 7 Register */ #define OTP_CONTENT_CHECKSUM 0x00001440 /* Content : Checksum Register */ #define OTP_PROG_CTRL 0x00001444 /* Programming Control Register */ #define OTP_PROG_STATUS 0x00001448 /* Programming Status Register */ #define OTP_PROG_PULSE 0x0000144c /* Program Pulse Width Register */ #define OTP_VERIFY_PULSE 0x00001450 /* Verify Pulse Width Register */ #define OTP_PROG_MASK 0x00001454 /* Program Mask Register */ #define OTP_DATA_INPUT 0x00001458 /* Data Input Register */ #define OTP_DATA_OUTPUT 0x0000145c /* Data Output Register */ /**************************************************************************** * BCM70012_OTP_TOP_OTP_GR_BRIDGE ***************************************************************************/ #define OTP_GR_BRIDGE_REVISION 0x000017e0 /* GR Bridge Revision */ #define OTP_GR_BRIDGE_CTRL 0x000017e4 /* GR Bridge Control Register */ #define OTP_GR_BRIDGE_SPARE_SW_RESET_0 0x000017e8 /* GR Bridge Software Reset 0 Register */ #define OTP_GR_BRIDGE_SPARE_SW_RESET_1 0x000017ec /* GR Bridge Software Reset 1 Register */ /**************************************************************************** * BCM70012_AES_TOP_AES ***************************************************************************/ #define AES_CONFIG_INFO 0x00001800 /* AES Configuration Information Register */ #define AES_CMD 0x00001804 /* AES Command Register */ #define AES_STATUS 0x00001808 /* AES Status Register */ #define AES_EEPROM_CONFIG 0x0000180c /* AES EEPROM Configuration Register */ #define AES_EEPROM_DATA_0 0x00001810 /* AES EEPROM Data Register 0 */ #define AES_EEPROM_DATA_1 0x00001814 /* AES EEPROM Data Register 1 */ #define AES_EEPROM_DATA_2 0x00001818 /* AES EEPROM Data Register 2 */ #define AES_EEPROM_DATA_3 0x0000181c /* AES EEPROM Data Register 3 */ /**************************************************************************** * BCM70012_AES_TOP_AES_RGR_BRIDGE ***************************************************************************/ #define AES_RGR_BRIDGE_REVISION 0x00001be0 /* RGR Bridge Revision */ #define AES_RGR_BRIDGE_CTRL 0x00001be4 /* RGR Bridge Control Register */ #define AES_RGR_BRIDGE_RBUS_TIMER 0x00001be8 /* RGR Bridge RBUS Timer Register */ #define AES_RGR_BRIDGE_SPARE_SW_RESET_0 0x00001bec /* RGR Bridge Software Reset 0 Register */ #define AES_RGR_BRIDGE_SPARE_SW_RESET_1 0x00001bf0 /* RGR Bridge Software Reset 1 Register */ /**************************************************************************** * BCM70012_DCI_TOP_DCI ***************************************************************************/ #define DCI_CMD 0x00001c00 /* DCI Command Register */ #define DCI_STATUS 0x00001c04 /* DCI Status Register */ #define DCI_DRAM_BASE_ADDR 0x00001c08 /* DRAM Base Address Register */ #define DCI_FIRMWARE_ADDR 0x00001c0c /* Firmware Address Register */ #define DCI_FIRMWARE_DATA 0x00001c10 /* Firmware Data Register */ #define DCI_SIGNATURE_DATA_0 0x00001c14 /* Signature Data Register 0 */ #define DCI_SIGNATURE_DATA_1 0x00001c18 /* Signature Data Register 1 */ #define DCI_SIGNATURE_DATA_2 0x00001c1c /* Signature Data Register 2 */ #define DCI_SIGNATURE_DATA_3 0x00001c20 /* Signature Data Register 3 */ #define DCI_SIGNATURE_DATA_4 0x00001c24 /* Signature Data Register 4 */ #define DCI_SIGNATURE_DATA_5 0x00001c28 /* Signature Data Register 5 */ #define DCI_SIGNATURE_DATA_6 0x00001c2c /* Signature Data Register 6 */ #define DCI_SIGNATURE_DATA_7 0x00001c30 /* Signature Data Register 7 */ /**************************************************************************** * BCM70012_DCI_TOP_DCI_RGR_BRIDGE ***************************************************************************/ #define DCI_RGR_BRIDGE_REVISION 0x00001fe0 /* RGR Bridge Revision */ #define DCI_RGR_BRIDGE_CTRL 0x00001fe4 /* RGR Bridge Control Register */ #define DCI_RGR_BRIDGE_RBUS_TIMER 0x00001fe8 /* RGR Bridge RBUS Timer Register */ #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0 0x00001fec /* RGR Bridge Software Reset 0 Register */ #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1 0x00001ff0 /* RGR Bridge Software Reset 1 Register */ /**************************************************************************** * BCM70012_CCE_TOP_CCE_RGR_BRIDGE ***************************************************************************/ #define CCE_RGR_BRIDGE_REVISION 0x000023e0 /* RGR Bridge Revision */ #define CCE_RGR_BRIDGE_CTRL 0x000023e4 /* RGR Bridge Control Register */ #define CCE_RGR_BRIDGE_RBUS_TIMER 0x000023e8 /* RGR Bridge RBUS Timer Register */ #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0 0x000023ec /* RGR Bridge Software Reset 0 Register */ #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1 0x000023f0 /* RGR Bridge Software Reset 1 Register */ /**************************************************************************** * BCM70012_TGT_TOP_PCIE_CFG ***************************************************************************/ /**************************************************************************** * PCIE_CFG :: DEVICE_VENDOR_ID ***************************************************************************/ /* PCIE_CFG :: DEVICE_VENDOR_ID :: DEVICE_ID [31:16] */ #define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_MASK 0xffff0000 #define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_ALIGN 0 #define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_BITS 16 #define PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_SHIFT 16 /* PCIE_CFG :: DEVICE_VENDOR_ID :: VENDOR_ID [15:00] */ #define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_MASK 0x0000ffff #define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_ALIGN 0 #define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_BITS 16 #define PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_SHIFT 0 /**************************************************************************** * PCIE_CFG :: STATUS_COMMAND ***************************************************************************/ /* PCIE_CFG :: STATUS_COMMAND :: DETECTED_PARITY_ERROR [31:31] */ #define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_MASK 0x80000000 #define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_BITS 1 #define PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_SHIFT 31 /* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_SYSTEM_ERROR [30:30] */ #define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_MASK 0x40000000 #define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_BITS 1 #define PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_SHIFT 30 /* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_MASTER_ABORT [29:29] */ #define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_MASK 0x20000000 #define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_BITS 1 #define PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_SHIFT 29 /* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_TARGET_ABORT [28:28] */ #define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_MASK 0x10000000 #define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_BITS 1 #define PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_SHIFT 28 /* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_TARGET_ABORT [27:27] */ #define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_MASK 0x08000000 #define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_BITS 1 #define PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_SHIFT 27 /* PCIE_CFG :: STATUS_COMMAND :: DEVSEL_TIMING [26:25] */ #define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_MASK 0x06000000 #define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_BITS 2 #define PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_SHIFT 25 /* PCIE_CFG :: STATUS_COMMAND :: MASTER_DATA_PARITY_ERROR [24:24] */ #define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_MASK 0x01000000 #define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_BITS 1 #define PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_SHIFT 24 /* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_CAPABLE [23:23] */ #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_MASK 0x00800000 #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_BITS 1 #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_SHIFT 23 /* PCIE_CFG :: STATUS_COMMAND :: RESERVED_0 [22:22] */ #define PCIE_CFG_STATUS_COMMAND_RESERVED_0_MASK 0x00400000 #define PCIE_CFG_STATUS_COMMAND_RESERVED_0_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_RESERVED_0_BITS 1 #define PCIE_CFG_STATUS_COMMAND_RESERVED_0_SHIFT 22 /* PCIE_CFG :: STATUS_COMMAND :: CAPABLE_66MHZ [21:21] */ #define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_MASK 0x00200000 #define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_BITS 1 #define PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_SHIFT 21 /* PCIE_CFG :: STATUS_COMMAND :: CAPABILITIES_LIST [20:20] */ #define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_MASK 0x00100000 #define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_BITS 1 #define PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_SHIFT 20 /* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_STATUS [19:19] */ #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_MASK 0x00080000 #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_BITS 1 #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_SHIFT 19 /* PCIE_CFG :: STATUS_COMMAND :: RESERVED_1 [18:16] */ #define PCIE_CFG_STATUS_COMMAND_RESERVED_1_MASK 0x00070000 #define PCIE_CFG_STATUS_COMMAND_RESERVED_1_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_RESERVED_1_BITS 3 #define PCIE_CFG_STATUS_COMMAND_RESERVED_1_SHIFT 16 /* PCIE_CFG :: STATUS_COMMAND :: RESERVED_2 [15:11] */ #define PCIE_CFG_STATUS_COMMAND_RESERVED_2_MASK 0x0000f800 #define PCIE_CFG_STATUS_COMMAND_RESERVED_2_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_RESERVED_2_BITS 5 #define PCIE_CFG_STATUS_COMMAND_RESERVED_2_SHIFT 11 /* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_DISABLE [10:10] */ #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_MASK 0x00000400 #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_BITS 1 #define PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_SHIFT 10 /* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_ENABLE [09:09] */ #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_MASK 0x00000200 #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_BITS 1 #define PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_SHIFT 9 /* PCIE_CFG :: STATUS_COMMAND :: SYSTEM_ERROR_ENABLE [08:08] */ #define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_MASK 0x00000100 #define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_BITS 1 #define PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_SHIFT 8 /* PCIE_CFG :: STATUS_COMMAND :: STEPPING_CONTROL [07:07] */ #define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_MASK 0x00000080 #define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_BITS 1 #define PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_SHIFT 7 /* PCIE_CFG :: STATUS_COMMAND :: PARITY_ERROR_ENABLE [06:06] */ #define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_MASK 0x00000040 #define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_BITS 1 #define PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_SHIFT 6 /* PCIE_CFG :: STATUS_COMMAND :: VGA_PALETTE_SNOOP [05:05] */ #define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_MASK 0x00000020 #define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_BITS 1 #define PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_SHIFT 5 /* PCIE_CFG :: STATUS_COMMAND :: MEMORY_WRITE_AND_INVALIDATE [04:04] */ #define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_MASK 0x00000010 #define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_BITS 1 #define PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_SHIFT 4 /* PCIE_CFG :: STATUS_COMMAND :: SPECIAL_CYCLES [03:03] */ #define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_MASK 0x00000008 #define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_BITS 1 #define PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_SHIFT 3 /* PCIE_CFG :: STATUS_COMMAND :: BUS_MASTER [02:02] */ #define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_MASK 0x00000004 #define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_BITS 1 #define PCIE_CFG_STATUS_COMMAND_BUS_MASTER_SHIFT 2 /* PCIE_CFG :: STATUS_COMMAND :: MEMORY_SPACE [01:01] */ #define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_MASK 0x00000002 #define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_BITS 1 #define PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_SHIFT 1 /* PCIE_CFG :: STATUS_COMMAND :: I_O_SPACE [00:00] */ #define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_MASK 0x00000001 #define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_ALIGN 0 #define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_BITS 1 #define PCIE_CFG_STATUS_COMMAND_I_O_SPACE_SHIFT 0 /**************************************************************************** * PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID ***************************************************************************/ /* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: PCI_CLASSCODE [31:08] */ #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_MASK 0xffffff00 #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_ALIGN 0 #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_BITS 24 #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_SHIFT 8 /* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: REVISION_ID [07:00] */ #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_MASK 0x000000ff #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_ALIGN 0 #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_BITS 8 #define PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_SHIFT 0 /**************************************************************************** * PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE ***************************************************************************/ /* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: BIST [31:24] */ #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_MASK 0xff000000 #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_ALIGN 0 #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_BITS 8 #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_SHIFT 24 /* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: HEADER_TYPE [23:16] */ #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_MASK 0x00ff0000 #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_ALIGN 0 #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_BITS 8 #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_SHIFT 16 /* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: LATENCY_TIMER [15:08] */ #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_MASK 0x0000ff00 #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_ALIGN 0 #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_BITS 8 #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_SHIFT 8 /* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: CACHE_LINE_SIZE [07:00] */ #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_MASK 0x000000ff #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_ALIGN 0 #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_BITS 8 #define PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_SHIFT 0 /**************************************************************************** * PCIE_CFG :: BASE_ADDRESS_1 ***************************************************************************/ /* PCIE_CFG :: BASE_ADDRESS_1 :: BASE_ADDRESS [31:16] */ #define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_MASK 0xffff0000 #define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_ALIGN 0 #define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_BITS 16 #define PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_SHIFT 16 /* PCIE_CFG :: BASE_ADDRESS_1 :: RESERVED_0 [15:04] */ #define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_MASK 0x0000fff0 #define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_ALIGN 0 #define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_BITS 12 #define PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_SHIFT 4 /* PCIE_CFG :: BASE_ADDRESS_1 :: PREFETCHABLE [03:03] */ #define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_MASK 0x00000008 #define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_ALIGN 0 #define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_BITS 1 #define PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_SHIFT 3 /* PCIE_CFG :: BASE_ADDRESS_1 :: TYPE [02:01] */ #define PCIE_CFG_BASE_ADDRESS_1_TYPE_MASK 0x00000006 #define PCIE_CFG_BASE_ADDRESS_1_TYPE_ALIGN 0 #define PCIE_CFG_BASE_ADDRESS_1_TYPE_BITS 2 #define PCIE_CFG_BASE_ADDRESS_1_TYPE_SHIFT 1 /* PCIE_CFG :: BASE_ADDRESS_1 :: MEMORY_SPACE_INDICATOR [00:00] */ #define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_MASK 0x00000001 #define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_ALIGN 0 #define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_BITS 1 #define PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_SHIFT 0 /**************************************************************************** * PCIE_CFG :: BASE_ADDRESS_2 ***************************************************************************/ /* PCIE_CFG :: BASE_ADDRESS_2 :: EXTENDED_BASE_ADDRESS [31:00] */ #define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_MASK 0xffffffff #define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_ALIGN 0 #define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_BITS 32 #define PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_SHIFT 0 /**************************************************************************** * PCIE_CFG :: BASE_ADDRESS_3 ***************************************************************************/ /* PCIE_CFG :: BASE_ADDRESS_3 :: BASE_ADDRESS_2 [31:22] */ #define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_MASK 0xffc00000 #define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_ALIGN 0 #define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_BITS 10 #define PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_2_SHIFT 22 /* PCIE_CFG :: BASE_ADDRESS_3 :: RESERVED_0 [21:04] */ #define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_MASK 0x003ffff0 #define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_ALIGN 0 #define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_BITS 18 #define PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_SHIFT 4 /* PCIE_CFG :: BASE_ADDRESS_3 :: PREFETCHABLE [03:03] */ #define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_MASK 0x00000008 #define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_ALIGN 0 #define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_BITS 1 #define PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_SHIFT 3 /* PCIE_CFG :: BASE_ADDRESS_3 :: TYPE [02:01] */ #define PCIE_CFG_BASE_ADDRESS_3_TYPE_MASK 0x00000006 #define PCIE_CFG_BASE_ADDRESS_3_TYPE_ALIGN 0 #define PCIE_CFG_BASE_ADDRESS_3_TYPE_BITS 2 #define PCIE_CFG_BASE_ADDRESS_3_TYPE_SHIFT 1 /* PCIE_CFG :: BASE_ADDRESS_3 :: MEMORY_SPACE_INDICATOR [00:00] */ #define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_MASK 0x00000001 #define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_ALIGN 0 #define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_BITS 1 #define PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_SHIFT 0 /**************************************************************************** * PCIE_CFG :: BASE_ADDRESS_4 ***************************************************************************/ /* PCIE_CFG :: BASE_ADDRESS_4 :: EXTENDED_BASE_ADDRESS_2 [31:00] */ #define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_MASK 0xffffffff #define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_ALIGN 0 #define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_BITS 32 #define PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_2_SHIFT 0 /**************************************************************************** * PCIE_CFG :: CARDBUS_CIS_POINTER ***************************************************************************/ /* PCIE_CFG :: CARDBUS_CIS_POINTER :: CARDBUS_CIS_POINTER [31:00] */ #define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_MASK 0xffffffff #define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_ALIGN 0 #define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_BITS 32 #define PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_SHIFT 0 /**************************************************************************** * PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID ***************************************************************************/ /* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_DEVICE_ID [31:16] */ #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_MASK 0xffff0000 #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_ALIGN 0 #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_BITS 16 #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_SHIFT 16 /* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_VENDOR_ID [15:00] */ #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_MASK 0x0000ffff #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_ALIGN 0 #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_BITS 16 #define PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0 /**************************************************************************** * PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS ***************************************************************************/ /* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_BASE_ADDRESS [31:16] */ #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_MASK 0xffff0000 #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_ALIGN 0 #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_BITS 16 #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_SHIFT 16 /* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_SIZE_INDICATION [15:11] */ #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_MASK 0x0000f800 #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_ALIGN 0 #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_BITS 5 #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_SHIFT 11 /* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: RESERVED_0 [10:01] */ #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_MASK 0x000007fe #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_ALIGN 0 #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_BITS 10 #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_SHIFT 1 /* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: EXPANSION_ROM_ENABLE [00:00] */ #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_MASK 0x00000001 #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_ALIGN 0 #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_BITS 1 #define PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_SHIFT 0 /**************************************************************************** * PCIE_CFG :: CAPABILITIES_POINTER ***************************************************************************/ /* PCIE_CFG :: CAPABILITIES_POINTER :: CAPABILITIES_POINTER [31:00] */ #define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_MASK 0xffffffff #define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_ALIGN 0 #define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_BITS 32 #define PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_SHIFT 0 /**************************************************************************** * PCIE_CFG :: INTERRUPT ***************************************************************************/ /* PCIE_CFG :: INTERRUPT :: RESERVED_0 [31:16] */ #define PCIE_CFG_INTERRUPT_RESERVED_0_MASK 0xffff0000 #define PCIE_CFG_INTERRUPT_RESERVED_0_ALIGN 0 #define PCIE_CFG_INTERRUPT_RESERVED_0_BITS 16 #define PCIE_CFG_INTERRUPT_RESERVED_0_SHIFT 16 /* PCIE_CFG :: INTERRUPT :: INTERRUPT_PIN [15:08] */ #define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_MASK 0x0000ff00 #define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_ALIGN 0 #define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_BITS 8 #define PCIE_CFG_INTERRUPT_INTERRUPT_PIN_SHIFT 8 /* PCIE_CFG :: INTERRUPT :: INTERRUPT_LINE [07:00] */ #define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_MASK 0x000000ff #define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_ALIGN 0 #define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_BITS 8 #define PCIE_CFG_INTERRUPT_INTERRUPT_LINE_SHIFT 0 /**************************************************************************** * PCIE_CFG :: VPD_CAPABILITIES ***************************************************************************/ /* PCIE_CFG :: VPD_CAPABILITIES :: RESERVED_0 [31:00] */ #define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_MASK 0xffffffff #define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_ALIGN 0 #define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_BITS 32 #define PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_SHIFT 0 /**************************************************************************** * PCIE_CFG :: VPD_DATA ***************************************************************************/ /* PCIE_CFG :: VPD_DATA :: RESERVED_0 [31:00] */ #define PCIE_CFG_VPD_DATA_RESERVED_0_MASK 0xffffffff #define PCIE_CFG_VPD_DATA_RESERVED_0_ALIGN 0 #define PCIE_CFG_VPD_DATA_RESERVED_0_BITS 32 #define PCIE_CFG_VPD_DATA_RESERVED_0_SHIFT 0 /**************************************************************************** * PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY ***************************************************************************/ /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_SUPPORT [31:27] */ #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_MASK 0xf8000000 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_BITS 5 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_SHIFT 27 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D2_SUPPORT [26:26] */ #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_MASK 0x04000000 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_BITS 1 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_SHIFT 26 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D1_SUPPORT [25:25] */ #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_MASK 0x02000000 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_BITS 1 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_SHIFT 25 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: AUX_CURRENT [24:22] */ #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_MASK 0x01c00000 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_BITS 3 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_SHIFT 22 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: DSI [21:21] */ #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_MASK 0x00200000 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_BITS 1 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_SHIFT 21 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: RESERVED_0 [20:20] */ #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_MASK 0x00100000 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_BITS 1 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_SHIFT 20 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_CLOCK [19:19] */ #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_MASK 0x00080000 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_BITS 1 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_SHIFT 19 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: VERSION [18:16] */ #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_MASK 0x00070000 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_BITS 3 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_SHIFT 16 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: NEXT_POINTER [15:08] */ #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_MASK 0x0000ff00 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_BITS 8 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_SHIFT 8 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: CAPABILITY_ID [07:00] */ #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_MASK 0x000000ff #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_BITS 8 #define PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_SHIFT 0 /**************************************************************************** * PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS ***************************************************************************/ /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PM_DATA [31:24] */ #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_MASK 0xff000000 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_BITS 8 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_SHIFT 24 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_0 [23:16] */ #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_MASK 0x00ff0000 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_BITS 8 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_SHIFT 16 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_STATUS [15:15] */ #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_MASK 0x00008000 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_BITS 1 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_SHIFT 15 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SCALE [14:13] */ #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_MASK 0x00006000 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_BITS 2 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_SHIFT 13 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SELECT [12:09] */ #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_MASK 0x00001e00 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_BITS 4 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_SHIFT 9 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_ENABLE [08:08] */ #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_MASK 0x00000100 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_BITS 1 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_SHIFT 8 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_1 [07:04] */ #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_MASK 0x000000f0 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_BITS 4 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_SHIFT 4 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: NO_SOFT_RESET [03:03] */ #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_MASK 0x00000008 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_BITS 1 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_SHIFT 3 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_2 [02:02] */ #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_MASK 0x00000004 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_BITS 1 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_SHIFT 2 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: POWER_STATE [01:00] */ #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_MASK 0x00000003 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_ALIGN 0 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_BITS 2 #define PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_SHIFT 0 /**************************************************************************** * PCIE_CFG :: MSI_CAPABILITY_HEADER ***************************************************************************/ /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_CONTROL [31:24] */ #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_MASK 0xff000000 #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_ALIGN 0 #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_BITS 8 #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_SHIFT 24 /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: ADDRESS_CAPABLE_64_BIT [23:23] */ #define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_MASK 0x00800000 #define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_ALIGN 0 #define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_BITS 1 #define PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_SHIFT 23 /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_ENABLE [22:20] */ #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_MASK 0x00700000 #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_ALIGN 0 #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_BITS 3 #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_SHIFT 20 /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_CAPABLE [19:17] */ #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_MASK 0x000e0000 #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_ALIGN 0 #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_BITS 3 #define PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_SHIFT 17 /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_ENABLE [16:16] */ #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_MASK 0x00010000 #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_ALIGN 0 #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_BITS 1 #define PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_SHIFT 16 /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ #define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 #define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_ALIGN 0 #define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_BITS 8 #define PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ #define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff #define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_ALIGN 0 #define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_BITS 8 #define PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 /**************************************************************************** * PCIE_CFG :: MSI_LOWER_ADDRESS ***************************************************************************/ /* PCIE_CFG :: MSI_LOWER_ADDRESS :: MSI_LOWER_ADDRESS [31:02] */ #define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_MASK 0xfffffffc #define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_ALIGN 0 #define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_BITS 30 #define PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_SHIFT 2 /* PCIE_CFG :: MSI_LOWER_ADDRESS :: RESERVED_0 [01:00] */ #define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_MASK 0x00000003 #define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_ALIGN 0 #define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_BITS 2 #define PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_SHIFT 0 /**************************************************************************** * PCIE_CFG :: MSI_UPPER_ADDRESS_REGISTER ***************************************************************************/ /* PCIE_CFG :: MSI_UPPER_ADDRESS_REGISTER :: MSI_UPPER_ADDRESS [31:00] */ #define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_MASK 0xffffffff #define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_ALIGN 0 #define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_BITS 32 #define PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_SHIFT 0 /**************************************************************************** * PCIE_CFG :: MSI_DATA ***************************************************************************/ /* PCIE_CFG :: MSI_DATA :: RESERVED_0 [31:16] */ #define PCIE_CFG_MSI_DATA_RESERVED_0_MASK 0xffff0000 #define PCIE_CFG_MSI_DATA_RESERVED_0_ALIGN 0 #define PCIE_CFG_MSI_DATA_RESERVED_0_BITS 16 #define PCIE_CFG_MSI_DATA_RESERVED_0_SHIFT 16 /* PCIE_CFG :: MSI_DATA :: MSI_DATA [15:00] */ #define PCIE_CFG_MSI_DATA_MSI_DATA_MASK 0x0000ffff #define PCIE_CFG_MSI_DATA_MSI_DATA_ALIGN 0 #define PCIE_CFG_MSI_DATA_MSI_DATA_BITS 16 #define PCIE_CFG_MSI_DATA_MSI_DATA_SHIFT 0 /**************************************************************************** * PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER ***************************************************************************/ /* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: RESERVED_0 [31:24] */ #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_MASK 0xff000000 #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_ALIGN 0 #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_BITS 8 #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_SHIFT 24 /* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: VENDOR_SPECIFIC_CAPABILITY_LENGTH [23:16] */ #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_MASK 0x00ff0000 #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_ALIGN 0 #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_BITS 8 #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_SHIFT 16 /* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_ALIGN 0 #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_BITS 8 #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 /* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_ALIGN 0 #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_BITS 8 #define PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 /**************************************************************************** * PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES ***************************************************************************/ /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: POR_RESET_COUNTER [31:28] */ #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_MASK 0xf0000000 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_ALIGN 0 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_BITS 4 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_SHIFT 28 /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: HOT_RESET_COUNTER [27:24] */ #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_MASK 0x0f000000 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_ALIGN 0 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_BITS 4 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_SHIFT 24 /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: GRC_RESET_COUNTER [23:16] */ #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_MASK 0x00ff0000 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_ALIGN 0 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_BITS 8 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_SHIFT 16 /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: PERST_RESET_COUNTER [15:08] */ #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_MASK 0x0000ff00 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_ALIGN 0 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_BITS 8 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_SHIFT 8 /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: LINKDOWN_RESET_COUNTER [07:00] */ #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_MASK 0x000000ff #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_ALIGN 0 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_BITS 8 #define PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_SHIFT 0 /**************************************************************************** * PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL ***************************************************************************/ /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: PRODUCT_ID [31:24] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xff000000 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_BITS 8 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 24 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ASIC_REVISION_ID [23:16] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_MASK 0x00ff0000 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_BITS 8 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_SHIFT 16 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TLP_MINOR_ERROR_TOLERANCE [15:15] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x00008000 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: LOG_HEADER_OVERFLOW [14:14] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x00004000 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: BOUNDARY_CHECK [13:13] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK 0x00002000 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: BYTE_ENABLE_RULE_CHECK [12:12] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK 0x00001000 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: INTERRUPT_CHECK [11:11] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK 0x00000800 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: RCB_CHECK [10:10] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK 0x00000400 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TAGGED_STATUS_MODE [09:09] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK 0x00000200 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: MASK_INTERRUPT_MODE [08:08] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK 0x00000100 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_INDIRECT_ACCESS [07:07] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK 0x00000080 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_REGISTER_WORD_SWAP [06:06] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK 0x00000040 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY [05:05] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_MASK 0x00000020 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_SHIFT 5 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY [04:04] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_MASK 0x00000010 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_SHIFT 4 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_ENDIAN_WORD_SWAP [03:03] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK 0x00000008 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_ENDIAN_BYTE_SWAP [02:02] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK 0x00000004 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: MASK_INTERRUPT [01:01] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK 0x00000002 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: CLEAR_INTERRUPT [00:00] */ #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK 0x00000001 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_ALIGN 0 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_BITS 1 #define PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0 /**************************************************************************** * PCIE_CFG :: SPARE ***************************************************************************/ /* PCIE_CFG :: SPARE :: UNUSED_0 [31:16] */ #define PCIE_CFG_SPARE_UNUSED_0_MASK 0xffff0000 #define PCIE_CFG_SPARE_UNUSED_0_ALIGN 0 #define PCIE_CFG_SPARE_UNUSED_0_BITS 16 #define PCIE_CFG_SPARE_UNUSED_0_SHIFT 16 /* PCIE_CFG :: SPARE :: RESERVED_0 [15:15] */ #define PCIE_CFG_SPARE_RESERVED_0_MASK 0x00008000 #define PCIE_CFG_SPARE_RESERVED_0_ALIGN 0 #define PCIE_CFG_SPARE_RESERVED_0_BITS 1 #define PCIE_CFG_SPARE_RESERVED_0_SHIFT 15 /* PCIE_CFG :: SPARE :: UNUSED_1 [14:02] */ #define PCIE_CFG_SPARE_UNUSED_1_MASK 0x00007ffc #define PCIE_CFG_SPARE_UNUSED_1_ALIGN 0 #define PCIE_CFG_SPARE_UNUSED_1_BITS 13 #define PCIE_CFG_SPARE_UNUSED_1_SHIFT 2 /* PCIE_CFG :: SPARE :: BAR2_TARGET_WORD_SWAP [01:01] */ #define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_MASK 0x00000002 #define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_ALIGN 0 #define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_BITS 1 #define PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_SHIFT 1 /* PCIE_CFG :: SPARE :: BAR2_TARGET_BYTE_SWAP [00:00] */ #define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_MASK 0x00000001 #define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_ALIGN 0 #define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_BITS 1 #define PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_SHIFT 0 /**************************************************************************** * PCIE_CFG :: PCI_STATE ***************************************************************************/ /* PCIE_CFG :: PCI_STATE :: RESERVED_0 [31:16] */ #define PCIE_CFG_PCI_STATE_RESERVED_0_MASK 0xffff0000 #define PCIE_CFG_PCI_STATE_RESERVED_0_ALIGN 0 #define PCIE_CFG_PCI_STATE_RESERVED_0_BITS 16 #define PCIE_CFG_PCI_STATE_RESERVED_0_SHIFT 16 /* PCIE_CFG :: PCI_STATE :: CONFIG_RETRY [15:15] */ #define PCIE_CFG_PCI_STATE_CONFIG_RETRY_MASK 0x00008000 #define PCIE_CFG_PCI_STATE_CONFIG_RETRY_ALIGN 0 #define PCIE_CFG_PCI_STATE_CONFIG_RETRY_BITS 1 #define PCIE_CFG_PCI_STATE_CONFIG_RETRY_SHIFT 15 /* PCIE_CFG :: PCI_STATE :: RESERVED_1 [14:12] */ #define PCIE_CFG_PCI_STATE_RESERVED_1_MASK 0x00007000 #define PCIE_CFG_PCI_STATE_RESERVED_1_ALIGN 0 #define PCIE_CFG_PCI_STATE_RESERVED_1_BITS 3 #define PCIE_CFG_PCI_STATE_RESERVED_1_SHIFT 12 /* PCIE_CFG :: PCI_STATE :: MAX_PCI_TARGET_RETRY [11:09] */ #define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK 0x00000e00 #define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_ALIGN 0 #define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_BITS 3 #define PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9 /* PCIE_CFG :: PCI_STATE :: FLAT_VIEW [08:08] */ #define PCIE_CFG_PCI_STATE_FLAT_VIEW_MASK 0x00000100 #define PCIE_CFG_PCI_STATE_FLAT_VIEW_ALIGN 0 #define PCIE_CFG_PCI_STATE_FLAT_VIEW_BITS 1 #define PCIE_CFG_PCI_STATE_FLAT_VIEW_SHIFT 8 /* PCIE_CFG :: PCI_STATE :: VPD_AVAILABLE [07:07] */ #define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_MASK 0x00000080 #define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_ALIGN 0 #define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_BITS 1 #define PCIE_CFG_PCI_STATE_VPD_AVAILABLE_SHIFT 7 /* PCIE_CFG :: PCI_STATE :: PCI_EXPANSION_ROM_RETRY [06:06] */ #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK 0x00000040 #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_ALIGN 0 #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_BITS 1 #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6 /* PCIE_CFG :: PCI_STATE :: PCI_EXPANSION_ROM_DESIRED [05:05] */ #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK 0x00000020 #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_ALIGN 0 #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_BITS 1 #define PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5 /* PCIE_CFG :: PCI_STATE :: RESERVED_2 [04:00] */ #define PCIE_CFG_PCI_STATE_RESERVED_2_MASK 0x0000001f #define PCIE_CFG_PCI_STATE_RESERVED_2_ALIGN 0 #define PCIE_CFG_PCI_STATE_RESERVED_2_BITS 5 #define PCIE_CFG_PCI_STATE_RESERVED_2_SHIFT 0 /**************************************************************************** * PCIE_CFG :: CLOCK_CONTROL ***************************************************************************/ /* PCIE_CFG :: CLOCK_CONTROL :: PL_CLOCK_DISABLE [31:31] */ #define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_MASK 0x80000000 #define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_ALIGN 0 #define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_BITS 1 #define PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_SHIFT 31 /* PCIE_CFG :: CLOCK_CONTROL :: DLL_CLOCK_DISABLE [30:30] */ #define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_MASK 0x40000000 #define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_ALIGN 0 #define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_BITS 1 #define PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_SHIFT 30 /* PCIE_CFG :: CLOCK_CONTROL :: TL_CLOCK_DISABLE [29:29] */ #define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_MASK 0x20000000 #define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_ALIGN 0 #define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_BITS 1 #define PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_SHIFT 29 /* PCIE_CFG :: CLOCK_CONTROL :: PCI_EXPRESS_CLOCK_TO_CORE_CLOCK [28:28] */ #define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_MASK 0x10000000 #define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_ALIGN 0 #define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_BITS 1 #define PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_SHIFT 28 /* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_0 [27:21] */ #define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_MASK 0x0fe00000 #define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_ALIGN 0 #define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_BITS 7 #define PCIE_CFG_CLOCK_CONTROL_UNUSED_0_SHIFT 21 /* PCIE_CFG :: CLOCK_CONTROL :: SELECT_FINAL_ALT_CLOCK_SOURCE [20:20] */ #define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_MASK 0x00100000 #define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_ALIGN 0 #define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_BITS 1 #define PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_SHIFT 20 /* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_1 [19:13] */ #define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_MASK 0x000fe000 #define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_ALIGN 0 #define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_BITS 7 #define PCIE_CFG_CLOCK_CONTROL_UNUSED_1_SHIFT 13 /* PCIE_CFG :: CLOCK_CONTROL :: SELECT_ALT_CLOCK [12:12] */ #define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_MASK 0x00001000 #define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_ALIGN 0 #define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_BITS 1 #define PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_SHIFT 12 /* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_2 [11:08] */ #define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_MASK 0x00000f00 #define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_ALIGN 0 #define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_BITS 4 #define PCIE_CFG_CLOCK_CONTROL_UNUSED_2_SHIFT 8 /* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_3 [07:00] */ #define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_MASK 0x000000ff #define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_ALIGN 0 #define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_BITS 8 #define PCIE_CFG_CLOCK_CONTROL_UNUSED_3_SHIFT 0 /**************************************************************************** * PCIE_CFG :: REGISTER_BASE ***************************************************************************/ /* PCIE_CFG :: REGISTER_BASE :: RESERVED_0 [31:18] */ #define PCIE_CFG_REGISTER_BASE_RESERVED_0_MASK 0xfffc0000 #define PCIE_CFG_REGISTER_BASE_RESERVED_0_ALIGN 0 #define PCIE_CFG_REGISTER_BASE_RESERVED_0_BITS 14 #define PCIE_CFG_REGISTER_BASE_RESERVED_0_SHIFT 18 /* PCIE_CFG :: REGISTER_BASE :: REGISTER_BASE_REGISTER [17:02] */ #define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_MASK 0x0003fffc #define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_ALIGN 0 #define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_BITS 16 #define PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_SHIFT 2 /* PCIE_CFG :: REGISTER_BASE :: RESERVED_1 [01:00] */ #define PCIE_CFG_REGISTER_BASE_RESERVED_1_MASK 0x00000003 #define PCIE_CFG_REGISTER_BASE_RESERVED_1_ALIGN 0 #define PCIE_CFG_REGISTER_BASE_RESERVED_1_BITS 2 #define PCIE_CFG_REGISTER_BASE_RESERVED_1_SHIFT 0 /**************************************************************************** * PCIE_CFG :: MEMORY_BASE ***************************************************************************/ /* PCIE_CFG :: MEMORY_BASE :: RESERVED_0 [31:24] */ #define PCIE_CFG_MEMORY_BASE_RESERVED_0_MASK 0xff000000 #define PCIE_CFG_MEMORY_BASE_RESERVED_0_ALIGN 0 #define PCIE_CFG_MEMORY_BASE_RESERVED_0_BITS 8 #define PCIE_CFG_MEMORY_BASE_RESERVED_0_SHIFT 24 /* PCIE_CFG :: MEMORY_BASE :: MEMORY_BASE_REGISTER [23:02] */ #define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_MASK 0x00fffffc #define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_ALIGN 0 #define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_BITS 22 #define PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_SHIFT 2 /* PCIE_CFG :: MEMORY_BASE :: RESERVED_1 [01:00] */ #define PCIE_CFG_MEMORY_BASE_RESERVED_1_MASK 0x00000003 #define PCIE_CFG_MEMORY_BASE_RESERVED_1_ALIGN 0 #define PCIE_CFG_MEMORY_BASE_RESERVED_1_BITS 2 #define PCIE_CFG_MEMORY_BASE_RESERVED_1_SHIFT 0 /**************************************************************************** * PCIE_CFG :: REGISTER_DATA ***************************************************************************/ /* PCIE_CFG :: REGISTER_DATA :: REGISTER_DATA_REGISTER [31:00] */ #define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_MASK 0xffffffff #define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_ALIGN 0 #define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_BITS 32 #define PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_SHIFT 0 /**************************************************************************** * PCIE_CFG :: MEMORY_DATA ***************************************************************************/ /* PCIE_CFG :: MEMORY_DATA :: MEMORY_DATA_REGISTER [31:00] */ #define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_MASK 0xffffffff #define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_ALIGN 0 #define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_BITS 32 #define PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_SHIFT 0 /**************************************************************************** * PCIE_CFG :: EXPANSION_ROM_BAR_SIZE ***************************************************************************/ /* PCIE_CFG :: EXPANSION_ROM_BAR_SIZE :: RESERVED_0 [31:04] */ #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_MASK 0xfffffff0 #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_ALIGN 0 #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_BITS 28 #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_SHIFT 4 /* PCIE_CFG :: EXPANSION_ROM_BAR_SIZE :: BAR_SIZE [03:00] */ #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_MASK 0x0000000f #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_ALIGN 0 #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_BITS 4 #define PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_SHIFT 0 /**************************************************************************** * PCIE_CFG :: EXPANSION_ROM_ADDRESS ***************************************************************************/ /* PCIE_CFG :: EXPANSION_ROM_ADDRESS :: ROM_CTL_ADDR [31:00] */ #define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_MASK 0xffffffff #define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_ALIGN 0 #define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_BITS 32 #define PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_SHIFT 0 /**************************************************************************** * PCIE_CFG :: EXPANSION_ROM_DATA ***************************************************************************/ /* PCIE_CFG :: EXPANSION_ROM_DATA :: ROM_DATA [31:00] */ #define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_MASK 0xffffffff #define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_ALIGN 0 #define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_BITS 32 #define PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_SHIFT 0 /**************************************************************************** * PCIE_CFG :: VPD_INTERFACE ***************************************************************************/ /* PCIE_CFG :: VPD_INTERFACE :: RESERVED_0 [31:01] */ #define PCIE_CFG_VPD_INTERFACE_RESERVED_0_MASK 0xfffffffe #define PCIE_CFG_VPD_INTERFACE_RESERVED_0_ALIGN 0 #define PCIE_CFG_VPD_INTERFACE_RESERVED_0_BITS 31 #define PCIE_CFG_VPD_INTERFACE_RESERVED_0_SHIFT 1 /* PCIE_CFG :: VPD_INTERFACE :: VPD_REQUEST [00:00] */ #define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_MASK 0x00000001 #define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_ALIGN 0 #define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_BITS 1 #define PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_SHIFT 0 /**************************************************************************** * PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER ***************************************************************************/ /* PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER :: UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX [31:00] */ #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_MASK 0xffffffff #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_ALIGN 0 #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_BITS 32 #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_SHIFT 0 /**************************************************************************** * PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER ***************************************************************************/ /* PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER :: UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX [31:00] */ #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_MASK 0xffffffff #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_ALIGN 0 #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_BITS 32 #define PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_SHIFT 0 /**************************************************************************** * PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER ***************************************************************************/ /* PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER :: UNDI_RECEIVE_RETURN_C_IDX [31:00] */ #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_MASK 0xffffffff #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_ALIGN 0 #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_BITS 32 #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_SHIFT 0 /**************************************************************************** * PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER ***************************************************************************/ /* PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER :: UNDI_RECEIVE_RETURN_C_IDX [31:00] */ #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_MASK 0xffffffff #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_ALIGN 0 #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_BITS 32 #define PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_SHIFT 0 /**************************************************************************** * PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER ***************************************************************************/ /* PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER :: UNDI_SEND_BD_NIC_P_IDX [31:00] */ #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_MASK 0xffffffff #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_ALIGN 0 #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_BITS 32 #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_SHIFT 0 /**************************************************************************** * PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER ***************************************************************************/ /* PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER :: UNDI_SEND_BD_NIC_P_IDX [31:00] */ #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_MASK 0xffffffff #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_ALIGN 0 #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_BITS 32 #define PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_SHIFT 0 /**************************************************************************** * PCIE_CFG :: INT_MAILBOX_UPPER ***************************************************************************/ /* PCIE_CFG :: INT_MAILBOX_UPPER :: INDIRECT_INTERRUPT_MAIL_BOX [31:00] */ #define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_MASK 0xffffffff #define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_ALIGN 0 #define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_BITS 32 #define PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_SHIFT 0 /**************************************************************************** * PCIE_CFG :: INT_MAILBOX_LOWER ***************************************************************************/ /* PCIE_CFG :: INT_MAILBOX_LOWER :: INDIRECT_INTERRUPT_MAIL_BOX [31:00] */ #define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_MASK 0xffffffff #define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_ALIGN 0 #define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_BITS 32 #define PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_SHIFT 0 /**************************************************************************** * PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION ***************************************************************************/ /* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: RESERVED_0 [31:28] */ #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_MASK 0xf0000000 #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_ALIGN 0 #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_BITS 4 #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_SHIFT 28 /* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: PRODUCT_ID [27:08] */ #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_MASK 0x0fffff00 #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_ALIGN 0 #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_BITS 20 #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_SHIFT 8 /* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: ASIC_REVISION_ID [07:00] */ #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_MASK 0x000000ff #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_ALIGN 0 #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_BITS 8 #define PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_SHIFT 0 /**************************************************************************** * PCIE_CFG :: FUNCTION_EVENT ***************************************************************************/ /* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_0 [31:16] */ #define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_MASK 0xffff0000 #define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_ALIGN 0 #define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_BITS 16 #define PCIE_CFG_FUNCTION_EVENT_RESERVED_0_SHIFT 16 /* PCIE_CFG :: FUNCTION_EVENT :: INTA_EVENT [15:15] */ #define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_MASK 0x00008000 #define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_ALIGN 0 #define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_BITS 1 #define PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_SHIFT 15 /* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_1 [14:05] */ #define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_MASK 0x00007fe0 #define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_ALIGN 0 #define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_BITS 10 #define PCIE_CFG_FUNCTION_EVENT_RESERVED_1_SHIFT 5 /* PCIE_CFG :: FUNCTION_EVENT :: GWAKE_EVENT [04:04] */ #define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_MASK 0x00000010 #define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_ALIGN 0 #define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_BITS 1 #define PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_SHIFT 4 /* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_2 [03:00] */ #define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_MASK 0x0000000f #define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_ALIGN 0 #define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_BITS 4 #define PCIE_CFG_FUNCTION_EVENT_RESERVED_2_SHIFT 0 /**************************************************************************** * PCIE_CFG :: FUNCTION_EVENT_MASK ***************************************************************************/ /* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_0 [31:16] */ #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_MASK 0xffff0000 #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_ALIGN 0 #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_BITS 16 #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_SHIFT 16 /* PCIE_CFG :: FUNCTION_EVENT_MASK :: INTA_MASK [15:15] */ #define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_MASK 0x00008000 #define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_ALIGN 0 #define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_BITS 1 #define PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_SHIFT 15 /* PCIE_CFG :: FUNCTION_EVENT_MASK :: WAKE_UP_MASK [14:14] */ #define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_MASK 0x00004000 #define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_ALIGN 0 #define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_BITS 1 #define PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_SHIFT 14 /* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_1 [13:05] */ #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_MASK 0x00003fe0 #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_ALIGN 0 #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_BITS 9 #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_SHIFT 5 /* PCIE_CFG :: FUNCTION_EVENT_MASK :: GWAKE_MASK [04:04] */ #define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_MASK 0x00000010 #define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_ALIGN 0 #define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_BITS 1 #define PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_SHIFT 4 /* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_2 [03:00] */ #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_MASK 0x0000000f #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_ALIGN 0 #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_BITS 4 #define PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_SHIFT 0 /**************************************************************************** * PCIE_CFG :: FUNCTION_PRESENT ***************************************************************************/ /* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_0 [31:16] */ #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_MASK 0xffff0000 #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_ALIGN 0 #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_BITS 16 #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_SHIFT 16 /* PCIE_CFG :: FUNCTION_PRESENT :: INTA_STATUS [15:15] */ #define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_MASK 0x00008000 #define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_ALIGN 0 #define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_BITS 1 #define PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_SHIFT 15 /* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_1 [14:05] */ #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_MASK 0x00007fe0 #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_ALIGN 0 #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_BITS 10 #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_SHIFT 5 /* PCIE_CFG :: FUNCTION_PRESENT :: PME_STATUS [04:04] */ #define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_MASK 0x00000010 #define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_ALIGN 0 #define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_BITS 1 #define PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_SHIFT 4 /* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_2 [03:00] */ #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_MASK 0x0000000f #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_ALIGN 0 #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_BITS 4 #define PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_SHIFT 0 /**************************************************************************** * PCIE_CFG :: PCIE_CAPABILITIES ***************************************************************************/ /* PCIE_CFG :: PCIE_CAPABILITIES :: RESERVED_0 [31:30] */ #define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_MASK 0xc0000000 #define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_ALIGN 0 #define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_BITS 2 #define PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_SHIFT 30 /* PCIE_CFG :: PCIE_CAPABILITIES :: INTERRUPT_MESSAGE_NUMBER [29:25] */ #define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_MASK 0x3e000000 #define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_ALIGN 0 #define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_BITS 5 #define PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_SHIFT 25 /* PCIE_CFG :: PCIE_CAPABILITIES :: SLOT_IMPLEMENTED [24:24] */ #define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_MASK 0x01000000 #define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_ALIGN 0 #define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_BITS 1 #define PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_SHIFT 24 /* PCIE_CFG :: PCIE_CAPABILITIES :: DEVICE_PORT_TYPE [23:20] */ #define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_MASK 0x00f00000 #define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_ALIGN 0 #define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_BITS 4 #define PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_SHIFT 20 /* PCIE_CFG :: PCIE_CAPABILITIES :: CAPABILITY_VERSION [19:16] */ #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_MASK 0x000f0000 #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_ALIGN 0 #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_BITS 4 #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_SHIFT 16 /* PCIE_CFG :: PCIE_CAPABILITIES :: NEXT_POINTER [15:08] */ #define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_MASK 0x0000ff00 #define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_ALIGN 0 #define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_BITS 8 #define PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_SHIFT 8 /* PCIE_CFG :: PCIE_CAPABILITIES :: CAPABILITY_ID [07:00] */ #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_MASK 0x000000ff #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_ALIGN 0 #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_BITS 8 #define PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_SHIFT 0 /**************************************************************************** * PCIE_CFG :: DEVICE_CAPABILITIES ***************************************************************************/ /* PCIE_CFG :: DEVICE_CAPABILITIES :: RESERVED_0 [31:28] */ #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_MASK 0xf0000000 #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_BITS 4 #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_SHIFT 28 /* PCIE_CFG :: DEVICE_CAPABILITIES :: CAPTURED_SLOT_POWER_LIMIT_SCALE [27:26] */ #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_MASK 0x0c000000 #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_BITS 2 #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_SHIFT 26 /* PCIE_CFG :: DEVICE_CAPABILITIES :: CAPTURED_SLOT_POWER_LIMIT_VALUE [25:18] */ #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_MASK 0x03fc0000 #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_BITS 8 #define PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_SHIFT 18 /* PCIE_CFG :: DEVICE_CAPABILITIES :: RESERVED_1 [17:16] */ #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_MASK 0x00030000 #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_BITS 2 #define PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_SHIFT 16 /* PCIE_CFG :: DEVICE_CAPABILITIES :: ROLE_BASED_ERROR_SUPPORT [15:15] */ #define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_MASK 0x00008000 #define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_BITS 1 #define PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_SHIFT 15 /* PCIE_CFG :: DEVICE_CAPABILITIES :: POWER_INDICATOR_PRESENT [14:14] */ #define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_MASK 0x00004000 #define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_BITS 1 #define PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_SHIFT 14 /* PCIE_CFG :: DEVICE_CAPABILITIES :: ATTENTION_INDICATOR_PRESENT [13:13] */ #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_MASK 0x00002000 #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_BITS 1 #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_SHIFT 13 /* PCIE_CFG :: DEVICE_CAPABILITIES :: ATTENTION_BUTTON_PRESENT [12:12] */ #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_MASK 0x00001000 #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_BITS 1 #define PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_SHIFT 12 /* PCIE_CFG :: DEVICE_CAPABILITIES :: ENDPOINT_L1_ACCEPTABLE_LATENCY [11:09] */ #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_MASK 0x00000e00 #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_BITS 3 #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_SHIFT 9 /* PCIE_CFG :: DEVICE_CAPABILITIES :: ENDPOINT_L0S_ACCEPTABLE_LATENCY [08:06] */ #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0 #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_BITS 3 #define PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_SHIFT 6 /* PCIE_CFG :: DEVICE_CAPABILITIES :: EXTENDED_TAG_FIELD_SUPPORTED [05:05] */ #define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_MASK 0x00000020 #define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_BITS 1 #define PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_SHIFT 5 /* PCIE_CFG :: DEVICE_CAPABILITIES :: PHANTOM_FUNCTIONS_SUPPORTED [04:03] */ #define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_MASK 0x00000018 #define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_BITS 2 #define PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_SHIFT 3 /* PCIE_CFG :: DEVICE_CAPABILITIES :: MAX_PAYLOAD_SIZE_SUPPORTED [02:00] */ #define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_MASK 0x00000007 #define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_BITS 3 #define PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_SHIFT 0 /**************************************************************************** * PCIE_CFG :: DEVICE_STATUS_CONTROL ***************************************************************************/ /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: RESERVED_0 [31:22] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_MASK 0xffc00000 #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_BITS 10 #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_SHIFT 22 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: TRANSACTION_PENDING [21:21] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_MASK 0x00200000 #define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_SHIFT 21 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: AUX_POWER_DETECTED [20:20] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_MASK 0x00100000 #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_SHIFT 20 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: UNSUPPORTED_REQUEST_DETECTED [19:19] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_MASK 0x00080000 #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_SHIFT 19 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: FATAL_ERROR_DETECTED [18:18] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_MASK 0x00040000 #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_SHIFT 18 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERROR_DETECTED [17:17] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_MASK 0x00020000 #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_SHIFT 17 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: CORRECTABLE_ERROR_DETECTED [16:16] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_MASK 0x00010000 #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_SHIFT 16 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: RESERVED_1 [15:15] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_MASK 0x00008000 #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_SHIFT 15 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: MAX_READ_REQUEST_SIZE [14:12] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_MASK 0x00007000 #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_BITS 3 #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_SHIFT 12 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: ENABLE_NO_SNOOP [11:11] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_MASK 0x00000800 #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_SHIFT 11 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: AUX_POWER_PM_ENABLE [10:10] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_MASK 0x00000400 #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_SHIFT 10 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: PHANTOM_FUNCTIONS_ENABLE [09:09] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_MASK 0x00000200 #define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_SHIFT 9 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: EXTENDED_TAG_FIELD_ENABLE [08:08] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_MASK 0x00000100 #define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_SHIFT 8 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: MAX_PAYLOAD_SIZE [07:05] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_MASK 0x000000e0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_BITS 3 #define PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_SHIFT 5 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: ENABLED_RELAXED_ORDERING [04:04] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_MASK 0x00000010 #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_SHIFT 4 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: UNSUPPORTED_REQUEST_REPORTING_ENABLE [03:03] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_MASK 0x00000008 #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_SHIFT 3 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: FATAL_ERROR_REPORTING_ENABLED [02:02] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_MASK 0x00000004 #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_SHIFT 2 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERROR_REPORTING_ENABLED [01:01] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_MASK 0x00000002 #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_SHIFT 1 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: CORRECTABLE_ERROR_REPORTING_ENABLED [00:00] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_MASK 0x00000001 #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_SHIFT 0 /**************************************************************************** * PCIE_CFG :: LINK_CAPABILITY ***************************************************************************/ /* PCIE_CFG :: LINK_CAPABILITY :: PORT_NUMBER [31:24] */ #define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_MASK 0xff000000 #define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_ALIGN 0 #define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_BITS 8 #define PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_SHIFT 24 /* PCIE_CFG :: LINK_CAPABILITY :: RESERVED_0 [23:19] */ #define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_MASK 0x00f80000 #define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_ALIGN 0 #define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_BITS 5 #define PCIE_CFG_LINK_CAPABILITY_RESERVED_0_SHIFT 19 /* PCIE_CFG :: LINK_CAPABILITY :: CLOCK_POWER_MANAGEMENT [18:18] */ #define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_MASK 0x00040000 #define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_ALIGN 0 #define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_BITS 1 #define PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_SHIFT 18 /* PCIE_CFG :: LINK_CAPABILITY :: L1_EXIT_LATENCY [17:15] */ #define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_MASK 0x00038000 #define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_ALIGN 0 #define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_BITS 3 #define PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_SHIFT 15 /* PCIE_CFG :: LINK_CAPABILITY :: L0S_EXIT_LATENCY [14:12] */ #define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_MASK 0x00007000 #define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_ALIGN 0 #define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_BITS 3 #define PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_SHIFT 12 /* PCIE_CFG :: LINK_CAPABILITY :: ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT [11:10] */ #define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_MASK 0x00000c00 #define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_ALIGN 0 #define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_BITS 2 #define PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_SHIFT 10 /* PCIE_CFG :: LINK_CAPABILITY :: MAXIMUM_LINK_WIDTH [09:04] */ #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_MASK 0x000003f0 #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_ALIGN 0 #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_BITS 6 #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_SHIFT 4 /* PCIE_CFG :: LINK_CAPABILITY :: MAXIMUM_LINK_SPEED [03:00] */ #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_MASK 0x0000000f #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_ALIGN 0 #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_BITS 4 #define PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_SHIFT 0 /**************************************************************************** * PCIE_CFG :: LINK_STATUS_CONTROL ***************************************************************************/ /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_0 [31:29] */ #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_MASK 0xe0000000 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_BITS 3 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_SHIFT 29 /* PCIE_CFG :: LINK_STATUS_CONTROL :: SLOT_CLOCK_CONFIGURATION [28:28] */ #define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_MASK 0x10000000 #define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_BITS 1 #define PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_SHIFT 28 /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_1 [27:26] */ #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_MASK 0x0c000000 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_BITS 2 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_SHIFT 26 /* PCIE_CFG :: LINK_STATUS_CONTROL :: NEGOTIATED_LINK_WIDTH [25:20] */ #define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK 0x03f00000 #define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_BITS 6 #define PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20 /* PCIE_CFG :: LINK_STATUS_CONTROL :: LINK_SPEED [19:16] */ #define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_MASK 0x000f0000 #define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_BITS 4 #define PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_SHIFT 16 /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_2 [15:09] */ #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_MASK 0x0000fe00 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_BITS 7 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_SHIFT 9 /* PCIE_CFG :: LINK_STATUS_CONTROL :: CLOCK_REQUEST_ENABLE [08:08] */ #define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_MASK 0x00000100 #define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_BITS 1 #define PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_SHIFT 8 /* PCIE_CFG :: LINK_STATUS_CONTROL :: EXTENDED_SYNCH [07:07] */ #define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_MASK 0x00000080 #define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_BITS 1 #define PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_SHIFT 7 /* PCIE_CFG :: LINK_STATUS_CONTROL :: COMMON_CLOCK_CONFIGURATION [06:06] */ #define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_MASK 0x00000040 #define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_BITS 1 #define PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_SHIFT 6 /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_3 [05:05] */ #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_MASK 0x00000020 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_BITS 1 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_SHIFT 5 /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_4 [04:04] */ #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_MASK 0x00000010 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_BITS 1 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_SHIFT 4 /* PCIE_CFG :: LINK_STATUS_CONTROL :: READ_COMPLETION_BOUNDARY [03:03] */ #define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_MASK 0x00000008 #define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_BITS 1 #define PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_SHIFT 3 /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_5 [02:02] */ #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_MASK 0x00000004 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_BITS 1 #define PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_SHIFT 2 /* PCIE_CFG :: LINK_STATUS_CONTROL :: ACTIVE_STATE_POWER_MANAGEMENT_CONTROL [01:00] */ #define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_MASK 0x00000003 #define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_BITS 2 #define PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_SHIFT 0 /**************************************************************************** * PCIE_CFG :: DEVICE_CAPABILITIES_2 ***************************************************************************/ /* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: RESERVED_0 [31:05] */ #define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_MASK 0xffffffe0 #define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_BITS 27 #define PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_SHIFT 5 /* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: CPL_DISABLE_SUPPORTED [04:04] */ #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_MASK 0x00000010 #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_BITS 1 #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_SHIFT 4 /* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: CPL_TIMEOUT_RANGE_SUPPORTED [03:00] */ #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000f #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_ALIGN 0 #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_BITS 4 #define PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_SHIFT 0 /**************************************************************************** * PCIE_CFG :: DEVICE_STATUS_CONTROL_2 ***************************************************************************/ /* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: RESERVED_0 [31:05] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_MASK 0xffffffe0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_BITS 27 #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_SHIFT 5 /* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: CPL_TIMEOUT_DISABLE [04:04] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_MASK 0x00000010 #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_BITS 1 #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_SHIFT 4 /* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: CPL_TIMEOUT_VALUE [03:00] */ #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_MASK 0x0000000f #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_ALIGN 0 #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_BITS 4 #define PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_SHIFT 0 /**************************************************************************** * PCIE_CFG :: LINK_CAPABILITIES_2 ***************************************************************************/ /* PCIE_CFG :: LINK_CAPABILITIES_2 :: RESERVED_0 [31:00] */ #define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_MASK 0xffffffff #define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_ALIGN 0 #define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_BITS 32 #define PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_SHIFT 0 /**************************************************************************** * PCIE_CFG :: LINK_STATUS_CONTROL_2 ***************************************************************************/ /* PCIE_CFG :: LINK_STATUS_CONTROL_2 :: RESERVED_0 [31:00] */ #define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_MASK 0xffffffff #define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_ALIGN 0 #define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_BITS 32 #define PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_SHIFT 0 /**************************************************************************** * PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER ***************************************************************************/ /* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 /* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 /* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 #define PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 /**************************************************************************** * PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS ***************************************************************************/ /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_0 [31:21] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_MASK 0xffe00000 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_BITS 11 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_SHIFT 21 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: UNSUPPORTED_REQUEST_ERROR_STATUS [20:20] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_MASK 0x00100000 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_SHIFT 20 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: ECRC_ERROR_STATUS [19:19] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_MASK 0x00080000 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_SHIFT 19 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: MALFORMED_TLP_STATUS [18:18] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_MASK 0x00040000 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_SHIFT 18 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RECEIVER_OVERFLOW_STATUS [17:17] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_MASK 0x00020000 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_SHIFT 17 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: UNEXPECTED_COMPLETION_STATUS [16:16] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_MASK 0x00010000 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_SHIFT 16 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: COMPLETER_ABORT_STATUS [15:15] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_MASK 0x00008000 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_SHIFT 15 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: COMPLETION_TIMEOUT_STATUS [14:14] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_MASK 0x00004000 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_SHIFT 14 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: FLOW_CONTROL_PROTOCOL_ERROR_STATUS [13:13] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_MASK 0x00002000 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_SHIFT 13 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: POISONED_TLP_STATUS [12:12] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_MASK 0x00001000 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_SHIFT 12 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_1 [11:05] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_MASK 0x00000fe0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_BITS 7 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_SHIFT 5 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: DATA_LINK_PROTOCOL_ERROR_STATUS [04:04] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_MASK 0x00000010 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_SHIFT 4 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_2 [03:01] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_MASK 0x0000000e #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_BITS 3 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_SHIFT 1 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: TRAINING_ERROR_STATUS [00:00] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_MASK 0x00000001 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_SHIFT 0 /**************************************************************************** * PCIE_CFG :: UNCORRECTABLE_ERROR_MASK ***************************************************************************/ /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_0 [31:21] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_MASK 0xffe00000 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_BITS 11 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_SHIFT 21 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: UNSUPPORTED_REQUEST_ERROR_MASK [20:20] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_MASK 0x00100000 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_SHIFT 20 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: ECRC_ERROR_MASK [19:19] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_MASK 0x00080000 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_SHIFT 19 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: MALFORMED_TLP_MASK [18:18] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_MASK 0x00040000 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_SHIFT 18 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RECEIVER_OVERFLOW_MASK [17:17] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_MASK 0x00020000 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_SHIFT 17 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: UNEXPECTED_COMPLETION_MASK [16:16] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_MASK 0x00010000 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_SHIFT 16 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: COMPLETER_ABORT_MASK [15:15] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_MASK 0x00008000 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_SHIFT 15 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: COMPLETION_TIMEOUT_MASK [14:14] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_MASK 0x00004000 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_SHIFT 14 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: FLOW_CONTROL_PROTOCOL_ERROR_MASK [13:13] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_MASK 0x00002000 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_SHIFT 13 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: POISONED_TLP_MASK [12:12] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_MASK 0x00001000 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_SHIFT 12 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_1 [11:05] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_MASK 0x00000fe0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_BITS 7 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_SHIFT 5 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: DATA_LINK_PROTOCOL_ERROR_MASK [04:04] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_MASK 0x00000010 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_SHIFT 4 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_2 [03:01] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_MASK 0x0000000e #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_BITS 3 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_SHIFT 1 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: TRAINING_ERROR_MASK [00:00] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_MASK 0x00000001 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_SHIFT 0 /**************************************************************************** * PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY ***************************************************************************/ /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_0 [31:21] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_MASK 0xffe00000 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_BITS 11 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_SHIFT 21 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: UNSUPPORTED_REQUEST_ERROR_SEVERITY [20:20] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_MASK 0x00100000 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_SHIFT 20 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: ECRC_ERROR_SEVERITY [19:19] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_MASK 0x00080000 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_SHIFT 19 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: MALFORMED_TLP_SEVERITY [18:18] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_MASK 0x00040000 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_SHIFT 18 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RECEIVER_OVERFLOW_ERROR_SEVERITY [17:17] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_MASK 0x00020000 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_SHIFT 17 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: UNEXPECTED_COMPLETION_ERROR_SEVERITY [16:16] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_MASK 0x00010000 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_SHIFT 16 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: COMPLETER_ABORT_ERROR_SEVERITY [15:15] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_MASK 0x00008000 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_SHIFT 15 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: COMPLETION_TIMEOUT_ERROR_SEVERITY [14:14] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_MASK 0x00004000 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_SHIFT 14 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY [13:13] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_MASK 0x00002000 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_SHIFT 13 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: POISONED_TLP_SEVERITY [12:12] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_MASK 0x00001000 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_SHIFT 12 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_1 [11:05] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_MASK 0x00000fe0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_BITS 7 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_SHIFT 5 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: DATA_LINK_PROTOCOL_ERROR_SEVERITY [04:04] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_MASK 0x00000010 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_SHIFT 4 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_2 [03:01] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_MASK 0x0000000e #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_BITS 3 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_SHIFT 1 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: TRAINING_ERROR_SEVERITY [00:00] */ #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_MASK 0x00000001 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_ALIGN 0 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_BITS 1 #define PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_SHIFT 0 /**************************************************************************** * PCIE_CFG :: CORRECTABLE_ERROR_STATUS ***************************************************************************/ /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_0 [31:14] */ #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_MASK 0xffffc000 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_BITS 18 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_SHIFT 14 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: ADVISORY_NON_FATAL_ERROR_STATUS [13:13] */ #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_MASK 0x00002000 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_BITS 1 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_SHIFT 13 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: REPLAY_TIMER_TIMEOUT_STATUS [12:12] */ #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_BITS 1 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_SHIFT 12 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_1 [11:09] */ #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_MASK 0x00000e00 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_BITS 3 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_SHIFT 9 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: REPLAY_NUM_ROLLOVER_STATUS [08:08] */ #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_BITS 1 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_SHIFT 8 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: BAD_DLLP_STATUS [07:07] */ #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_MASK 0x00000080 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_BITS 1 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_SHIFT 7 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: BAD_TLP_STATUS [06:06] */ #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_MASK 0x00000040 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_BITS 1 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_SHIFT 6 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_2 [05:01] */ #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_MASK 0x0000003e #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_BITS 5 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_SHIFT 1 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RECEIVER_ERROR_STATUS [00:00] */ #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_MASK 0x00000001 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_BITS 1 #define PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_SHIFT 0 /**************************************************************************** * PCIE_CFG :: CORRECTABLE_ERROR_MASK ***************************************************************************/ /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_0 [31:14] */ #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_MASK 0xffffc000 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_BITS 18 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_SHIFT 14 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: ADVISORY_NON_FATAL_ERROR_MASK [13:13] */ #define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_MASK 0x00002000 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_BITS 1 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_SHIFT 13 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: REPLAY_TIMER_TIMEOUT_MASK [12:12] */ #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_BITS 1 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_SHIFT 12 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_1 [11:09] */ #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_MASK 0x00000e00 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_BITS 3 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_SHIFT 9 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: REPLAY_NUM_ROLLOVER_MASK [08:08] */ #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_BITS 1 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_SHIFT 8 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: BAD_DLLP_MASK [07:07] */ #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_MASK 0x00000080 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_BITS 1 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_SHIFT 7 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: BAD_TLP_MASK [06:06] */ #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_MASK 0x00000040 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_BITS 1 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_SHIFT 6 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_2 [05:01] */ #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_MASK 0x0000003e #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_BITS 5 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_SHIFT 1 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RECEIVER_ERROR_MASK [00:00] */ #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_MASK 0x00000001 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_ALIGN 0 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_BITS 1 #define PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_SHIFT 0 /**************************************************************************** * PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL ***************************************************************************/ /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: RESERVED_0 [31:09] */ #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_MASK 0xfffffe00 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_ALIGN 0 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_BITS 23 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_SHIFT 9 /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_CHECK_ENABLE [08:08] */ #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_MASK 0x00000100 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_ALIGN 0 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_BITS 1 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_SHIFT 8 /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_CHECK_CAPABLE [07:07] */ #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_MASK 0x00000080 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_ALIGN 0 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_BITS 1 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_SHIFT 7 /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_GENERATION_ENABLE [06:06] */ #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_MASK 0x00000040 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_ALIGN 0 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_BITS 1 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_SHIFT 6 /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_GENERATION_CAPABLE [05:05] */ #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_MASK 0x00000020 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_ALIGN 0 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_BITS 1 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_SHIFT 5 /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: FIRST_ERROR_POINTER [04:00] */ #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_MASK 0x0000001f #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_ALIGN 0 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_BITS 5 #define PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_SHIFT 0 /**************************************************************************** * PCIE_CFG :: HEADER_LOG_1 ***************************************************************************/ /* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_0 [31:24] */ #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_MASK 0xff000000 #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_ALIGN 0 #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_BITS 8 #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_SHIFT 24 /* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_1 [23:16] */ #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_MASK 0x00ff0000 #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_ALIGN 0 #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_BITS 8 #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_SHIFT 16 /* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_2 [15:08] */ #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_MASK 0x0000ff00 #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_ALIGN 0 #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_BITS 8 #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_SHIFT 8 /* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_3 [07:00] */ #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_MASK 0x000000ff #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_ALIGN 0 #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_BITS 8 #define PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_SHIFT 0 /**************************************************************************** * PCIE_CFG :: HEADER_LOG_2 ***************************************************************************/ /* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_4 [31:24] */ #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_MASK 0xff000000 #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_ALIGN 0 #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_BITS 8 #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_SHIFT 24 /* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_5 [23:16] */ #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_MASK 0x00ff0000 #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_ALIGN 0 #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_BITS 8 #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_SHIFT 16 /* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_6 [15:08] */ #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_MASK 0x0000ff00 #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_ALIGN 0 #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_BITS 8 #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_SHIFT 8 /* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_7 [07:00] */ #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_MASK 0x000000ff #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_ALIGN 0 #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_BITS 8 #define PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_SHIFT 0 /**************************************************************************** * PCIE_CFG :: HEADER_LOG_3 ***************************************************************************/ /* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_8 [31:24] */ #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_MASK 0xff000000 #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_ALIGN 0 #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_BITS 8 #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_SHIFT 24 /* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_9 [23:16] */ #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_MASK 0x00ff0000 #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_ALIGN 0 #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_BITS 8 #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_SHIFT 16 /* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_10 [15:08] */ #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_MASK 0x0000ff00 #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_ALIGN 0 #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_BITS 8 #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_SHIFT 8 /* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_11 [07:00] */ #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_MASK 0x000000ff #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_ALIGN 0 #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_BITS 8 #define PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_SHIFT 0 /**************************************************************************** * PCIE_CFG :: HEADER_LOG_4 ***************************************************************************/ /* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_12 [31:24] */ #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_MASK 0xff000000 #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_ALIGN 0 #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_BITS 8 #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_SHIFT 24 /* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_13 [23:16] */ #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_MASK 0x00ff0000 #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_ALIGN 0 #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_BITS 8 #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_SHIFT 16 /* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_14 [15:08] */ #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_MASK 0x0000ff00 #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_ALIGN 0 #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_BITS 8 #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_SHIFT 8 /* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_15 [07:00] */ #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_MASK 0x000000ff #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_ALIGN 0 #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_BITS 8 #define PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_SHIFT 0 /**************************************************************************** * PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER ***************************************************************************/ /* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 /* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 /* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 #define PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 /**************************************************************************** * PCIE_CFG :: PORT_VC_CAPABILITY ***************************************************************************/ /* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_0 [31:12] */ #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_MASK 0xfffff000 #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_ALIGN 0 #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_BITS 20 #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_SHIFT 12 /* PCIE_CFG :: PORT_VC_CAPABILITY :: PORT_ARBITRATION_TABLE_ENTRY_SIZE [11:10] */ #define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_MASK 0x00000c00 #define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_ALIGN 0 #define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_BITS 2 #define PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_SHIFT 10 /* PCIE_CFG :: PORT_VC_CAPABILITY :: REFERENCE_CLOCK [09:08] */ #define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_MASK 0x00000300 #define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_ALIGN 0 #define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_BITS 2 #define PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_SHIFT 8 /* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_1 [07:07] */ #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_MASK 0x00000080 #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_ALIGN 0 #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_BITS 1 #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_SHIFT 7 /* PCIE_CFG :: PORT_VC_CAPABILITY :: LOW_PRIORITY_EXTENDED_VC_COUNT [06:04] */ #define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_MASK 0x00000070 #define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_ALIGN 0 #define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_BITS 3 #define PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_SHIFT 4 /* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_2 [03:03] */ #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_MASK 0x00000008 #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_ALIGN 0 #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_BITS 1 #define PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_SHIFT 3 /* PCIE_CFG :: PORT_VC_CAPABILITY :: EXTENDED_VC_COUNT [02:00] */ #define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_MASK 0x00000007 #define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_ALIGN 0 #define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_BITS 3 #define PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_SHIFT 0 /**************************************************************************** * PCIE_CFG :: PORT_VC_CAPABILITY_2 ***************************************************************************/ /* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: VC_ARBITRATION_TABLE_OFFSET [31:24] */ #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_MASK 0xff000000 #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_ALIGN 0 #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_BITS 8 #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_SHIFT 24 /* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: RESERVED_0 [23:08] */ #define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_MASK 0x00ffff00 #define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_ALIGN 0 #define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_BITS 16 #define PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_SHIFT 8 /* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: VC_ARBITRATION_CAPABILITY [07:00] */ #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_MASK 0x000000ff #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_ALIGN 0 #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_BITS 8 #define PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_SHIFT 0 /**************************************************************************** * PCIE_CFG :: PORT_VC_STATUS_CONTROL ***************************************************************************/ /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: RESERVED_0 [31:17] */ #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_MASK 0xfffe0000 #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_ALIGN 0 #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_BITS 15 #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_SHIFT 17 /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: VC_ARBITRATION_TABLE_STATUS [16:16] */ #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_MASK 0x00010000 #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_ALIGN 0 #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_BITS 1 #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_SHIFT 16 /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: RESERVED_1 [15:04] */ #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_MASK 0x0000fff0 #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_ALIGN 0 #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_BITS 12 #define PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_SHIFT 4 /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: VC_ARBITRATION_SELECT [03:01] */ #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_MASK 0x0000000e #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_ALIGN 0 #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_BITS 3 #define PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_SHIFT 1 /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: LOAD_VC_ARBITRATION_TABLE [00:00] */ #define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_MASK 0x00000001 #define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_ALIGN 0 #define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_BITS 1 #define PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_SHIFT 0 /**************************************************************************** * PCIE_CFG :: VC_RESOURCE_CAPABILITY ***************************************************************************/ /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: PORT_ARBITRATION_TABLE_OFFSET [31:24] */ #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_MASK 0xff000000 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_BITS 8 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_SHIFT 24 /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: RESERVED_0 [23:23] */ #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_MASK 0x00800000 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_BITS 1 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_SHIFT 23 /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: MAXIMUM_TIME_SLOTS [22:16] */ #define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_MASK 0x007f0000 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_BITS 7 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_SHIFT 16 /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: REJECT_SNOOP_TRANSACTIONS [15:15] */ #define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_MASK 0x00008000 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_BITS 1 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_SHIFT 15 /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: ADVANCED_PACKET_SWITCHING [14:14] */ #define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_MASK 0x00004000 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_BITS 1 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_SHIFT 14 /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: RESERVED_1 [13:08] */ #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_MASK 0x00003f00 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_BITS 6 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_SHIFT 8 /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: PORT_ARBITRATION_CAPABILITY [07:00] */ #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_MASK 0x000000ff #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_BITS 8 #define PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_SHIFT 0 /**************************************************************************** * PCIE_CFG :: VC_RESOURCE_CONTROL ***************************************************************************/ /* PCIE_CFG :: VC_RESOURCE_CONTROL :: VC_ENABLE [31:31] */ #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_MASK 0x80000000 #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_BITS 1 #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_SHIFT 31 /* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_0 [30:27] */ #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_MASK 0x78000000 #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_BITS 4 #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_SHIFT 27 /* PCIE_CFG :: VC_RESOURCE_CONTROL :: VC_ID [26:24] */ #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_MASK 0x07000000 #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_BITS 3 #define PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_SHIFT 24 /* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_1 [23:20] */ #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_MASK 0x00f00000 #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_BITS 4 #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_SHIFT 20 /* PCIE_CFG :: VC_RESOURCE_CONTROL :: PORT_ARBITRATION_SELECT [19:17] */ #define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_MASK 0x000e0000 #define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_BITS 3 #define PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_SHIFT 17 /* PCIE_CFG :: VC_RESOURCE_CONTROL :: LOAD_PORT_ARBITRATION_TABLE [16:16] */ #define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_MASK 0x00010000 #define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_BITS 1 #define PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_SHIFT 16 /* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_2 [15:08] */ #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_MASK 0x0000ff00 #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_BITS 8 #define PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_SHIFT 8 /* PCIE_CFG :: VC_RESOURCE_CONTROL :: TC_VC_MAP [07:00] */ #define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_MASK 0x000000ff #define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_BITS 8 #define PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_SHIFT 0 /**************************************************************************** * PCIE_CFG :: VC_RESOURCE_STATUS ***************************************************************************/ /* PCIE_CFG :: VC_RESOURCE_STATUS :: RESERVED_0 [31:18] */ #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_MASK 0xfffc0000 #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_BITS 14 #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_SHIFT 18 /* PCIE_CFG :: VC_RESOURCE_STATUS :: VC_NEGOTIATION_PENDING [17:17] */ #define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_MASK 0x00020000 #define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_BITS 1 #define PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_SHIFT 17 /* PCIE_CFG :: VC_RESOURCE_STATUS :: PORT_ARBITRATION_TABLE_STATUS [16:16] */ #define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_MASK 0x00010000 #define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_BITS 1 #define PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_SHIFT 16 /* PCIE_CFG :: VC_RESOURCE_STATUS :: RESERVED_1 [15:00] */ #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_MASK 0x0000ffff #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_ALIGN 0 #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_BITS 16 #define PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_SHIFT 0 /**************************************************************************** * PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER ***************************************************************************/ /* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 /* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 /* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 #define PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 /**************************************************************************** * PCIE_CFG :: DEVICE_SERIAL_NO_LOWER_DW ***************************************************************************/ /* PCIE_CFG :: DEVICE_SERIAL_NO_LOWER_DW :: SERIAL_NO_LOWER [31:00] */ #define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_MASK 0xffffffff #define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_ALIGN 0 #define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_BITS 32 #define PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_SHIFT 0 /**************************************************************************** * PCIE_CFG :: DEVICE_SERIAL_NO_UPPER_DW ***************************************************************************/ /* PCIE_CFG :: DEVICE_SERIAL_NO_UPPER_DW :: SERIAL_NO_UPPER [31:00] */ #define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_MASK 0xffffffff #define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_ALIGN 0 #define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_BITS 32 #define PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_SHIFT 0 /**************************************************************************** * PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER ***************************************************************************/ /* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_ALIGN 0 #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_BITS 12 #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 /* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_ALIGN 0 #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_BITS 4 #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 /* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_ALIGN 0 #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_BITS 16 #define PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 /**************************************************************************** * PCIE_CFG :: POWER_BUDGETING_DATA_SELECT ***************************************************************************/ /* PCIE_CFG :: POWER_BUDGETING_DATA_SELECT :: RESERVED_0 [31:08] */ #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_MASK 0xffffff00 #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_ALIGN 0 #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_BITS 24 #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_SHIFT 8 /* PCIE_CFG :: POWER_BUDGETING_DATA_SELECT :: DATA_SELECT [07:00] */ #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_MASK 0x000000ff #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_ALIGN 0 #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_BITS 8 #define PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_SHIFT 0 /**************************************************************************** * PCIE_CFG :: POWER_BUDGETING_DATA ***************************************************************************/ /* PCIE_CFG :: POWER_BUDGETING_DATA :: RESERVED_0 [31:21] */ #define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_MASK 0xffe00000 #define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_ALIGN 0 #define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_BITS 11 #define PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_SHIFT 21 /* PCIE_CFG :: POWER_BUDGETING_DATA :: POWER_RAIL [20:18] */ #define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_MASK 0x001c0000 #define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_ALIGN 0 #define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_BITS 3 #define PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_SHIFT 18 /* PCIE_CFG :: POWER_BUDGETING_DATA :: TYPE [17:15] */ #define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_MASK 0x00038000 #define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_ALIGN 0 #define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_BITS 3 #define PCIE_CFG_POWER_BUDGETING_DATA_TYPE_SHIFT 15 /* PCIE_CFG :: POWER_BUDGETING_DATA :: PM_STATE [14:13] */ #define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_MASK 0x00006000 #define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_ALIGN 0 #define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_BITS 2 #define PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_SHIFT 13 /* PCIE_CFG :: POWER_BUDGETING_DATA :: PM_SUB_STATE [12:10] */ #define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_MASK 0x00001c00 #define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_ALIGN 0 #define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_BITS 3 #define PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_SHIFT 10 /* PCIE_CFG :: POWER_BUDGETING_DATA :: DATA_SCALE [09:08] */ #define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_MASK 0x00000300 #define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_ALIGN 0 #define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_BITS 2 #define PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_SHIFT 8 /* PCIE_CFG :: POWER_BUDGETING_DATA :: BASE_POWER [07:00] */ #define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_MASK 0x000000ff #define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_ALIGN 0 #define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_BITS 8 #define PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_SHIFT 0 /**************************************************************************** * PCIE_CFG :: POWER_BUDGETING_CAPABILITY ***************************************************************************/ /* PCIE_CFG :: POWER_BUDGETING_CAPABILITY :: RESERVED_0 [31:01] */ #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_MASK 0xfffffffe #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_ALIGN 0 #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_BITS 31 #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_SHIFT 1 /* PCIE_CFG :: POWER_BUDGETING_CAPABILITY :: LOM_CONFIGURATION [00:00] */ #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_MASK 0x00000001 #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_ALIGN 0 #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_BITS 1 #define PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_SHIFT 0 /**************************************************************************** * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 ***************************************************************************/ /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: POWER_RAIL_2 [31:29] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_MASK 0xe0000000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_SHIFT 29 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: TYPE_2 [28:26] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_MASK 0x1c000000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_SHIFT 26 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: PM_STATE_2 [25:24] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_MASK 0x03000000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_BITS 2 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_SHIFT 24 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: BASE_POWER_2 [23:16] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_MASK 0x00ff0000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_BITS 8 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_SHIFT 16 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: POWER_RAIL_1 [15:13] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_MASK 0x0000e000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_SHIFT 13 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: TYPE_1 [12:10] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_MASK 0x00001c00 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_SHIFT 10 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: PM_STATE_1 [09:08] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_MASK 0x00000300 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_BITS 2 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_SHIFT 8 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: BASE_POWER_1 [07:00] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_MASK 0x000000ff #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_BITS 8 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_SHIFT 0 /**************************************************************************** * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 ***************************************************************************/ /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: POWER_RAIL_4 [31:29] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_MASK 0xe0000000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_SHIFT 29 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: TYPE_4 [28:26] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_MASK 0x1c000000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_SHIFT 26 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: PM_STATE_4 [25:24] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_MASK 0x03000000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_BITS 2 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_SHIFT 24 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: BASE_POWER_4 [23:16] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_MASK 0x00ff0000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_BITS 8 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_SHIFT 16 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: POWER_RAIL_3 [15:13] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_MASK 0x0000e000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_SHIFT 13 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: TYPE_3 [12:10] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_MASK 0x00001c00 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_SHIFT 10 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: PM_STATE_3 [09:08] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_MASK 0x00000300 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_BITS 2 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_SHIFT 8 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: BASE_POWER_3 [07:00] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_MASK 0x000000ff #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_BITS 8 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_SHIFT 0 /**************************************************************************** * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 ***************************************************************************/ /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: POWER_RAIL_6 [31:29] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_MASK 0xe0000000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_SHIFT 29 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: TYPE_6 [28:26] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_MASK 0x1c000000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_SHIFT 26 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: PM_STATE_6 [25:24] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_MASK 0x03000000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_BITS 2 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_SHIFT 24 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: BASE_POWER_6 [23:16] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_MASK 0x00ff0000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_BITS 8 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_SHIFT 16 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: POWER_RAIL_5 [15:13] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_MASK 0x0000e000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_SHIFT 13 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: TYPE_5 [12:10] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_MASK 0x00001c00 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_SHIFT 10 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: PM_STATE_5 [09:08] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_MASK 0x00000300 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_BITS 2 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_SHIFT 8 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: BASE_POWER_5 [07:00] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_MASK 0x000000ff #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_BITS 8 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_SHIFT 0 /**************************************************************************** * PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 ***************************************************************************/ /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: POWER_RAIL_8 [31:29] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_MASK 0xe0000000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_SHIFT 29 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: TYPE_8 [28:26] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_MASK 0x1c000000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_SHIFT 26 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: PM_STATE_8 [25:24] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_MASK 0x03000000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_BITS 2 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_SHIFT 24 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: BASE_POWER_8 [23:16] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_MASK 0x00ff0000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_BITS 8 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_SHIFT 16 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: POWER_RAIL_7 [15:13] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_MASK 0x0000e000 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_SHIFT 13 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: TYPE_7 [12:10] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_MASK 0x00001c00 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_BITS 3 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_SHIFT 10 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: PM_STATE_7 [09:08] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_MASK 0x00000300 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_BITS 2 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_SHIFT 8 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: BASE_POWER_7 [07:00] */ #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_MASK 0x000000ff #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_ALIGN 0 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_BITS 8 #define PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_SHIFT 0 /**************************************************************************** * PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING ***************************************************************************/ /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: UNUSED_0 [31:07] */ #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_MASK 0xffffff80 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_ALIGN 0 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_BITS 25 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_SHIFT 7 /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: D3HOT_MEMORY_READ_ADVISORY_NON_FATAL [06:06] */ #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_MASK 0x00000040 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_ALIGN 0 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_BITS 1 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_SHIFT 6 /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: RETRY_POISON_ENABLE [05:05] */ #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_MASK 0x00000020 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_ALIGN 0 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_BITS 1 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_SHIFT 5 /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: POISON_ADVISORY_NON_FATAL_ENABLE [04:04] */ #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000010 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_BITS 1 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_SHIFT 4 /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: UNEXPECTED_ADVISORY_NON_FATAL_ENABLE [03:03] */ #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000008 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_BITS 1 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_SHIFT 3 /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE [02:02] */ #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000004 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_BITS 1 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_SHIFT 2 /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE [01:01] */ #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000002 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_BITS 1 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_SHIFT 1 /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE [00:00] */ #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000001 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_ALIGN 0 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_BITS 1 #define PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_SHIFT 0 /**************************************************************************** * BCM70012_TGT_TOP_PCIE_TL ***************************************************************************/ /**************************************************************************** * PCIE_TL :: TL_CONTROL ***************************************************************************/ /* PCIE_TL :: TL_CONTROL :: RESERVED_0 [31:31] */ #define PCIE_TL_TL_CONTROL_RESERVED_0_MASK 0x80000000 #define PCIE_TL_TL_CONTROL_RESERVED_0_ALIGN 0 #define PCIE_TL_TL_CONTROL_RESERVED_0_BITS 1 #define PCIE_TL_TL_CONTROL_RESERVED_0_SHIFT 31 /* PCIE_TL :: TL_CONTROL :: CQ14298_FIX_ENA_N [30:30] */ #define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_MASK 0x40000000 #define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_ALIGN 0 #define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_BITS 1 #define PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_SHIFT 30 /* PCIE_TL :: TL_CONTROL :: RESERVED_1 [29:29] */ #define PCIE_TL_TL_CONTROL_RESERVED_1_MASK 0x20000000 #define PCIE_TL_TL_CONTROL_RESERVED_1_ALIGN 0 #define PCIE_TL_TL_CONTROL_RESERVED_1_BITS 1 #define PCIE_TL_TL_CONTROL_RESERVED_1_SHIFT 29 /* PCIE_TL :: TL_CONTROL :: INTA_WAKEUP_LINK_CLKREQ_DA [28:28] */ #define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_MASK 0x10000000 #define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_ALIGN 0 #define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_BITS 1 #define PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_SHIFT 28 /* PCIE_TL :: TL_CONTROL :: RESERVED_2 [27:27] */ #define PCIE_TL_TL_CONTROL_RESERVED_2_MASK 0x08000000 #define PCIE_TL_TL_CONTROL_RESERVED_2_ALIGN 0 #define PCIE_TL_TL_CONTROL_RESERVED_2_BITS 1 #define PCIE_TL_TL_CONTROL_RESERVED_2_SHIFT 27 /* PCIE_TL :: TL_CONTROL :: CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX [26:26] */ #define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_MASK 0x04000000 #define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_ALIGN 0 #define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_BITS 1 #define PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_SHIFT 26 /* PCIE_TL :: TL_CONTROL :: RESERVED_3 [25:25] */ #define PCIE_TL_TL_CONTROL_RESERVED_3_MASK 0x02000000 #define PCIE_TL_TL_CONTROL_RESERVED_3_ALIGN 0 #define PCIE_TL_TL_CONTROL_RESERVED_3_BITS 1 #define PCIE_TL_TL_CONTROL_RESERVED_3_SHIFT 25 /* PCIE_TL :: TL_CONTROL :: RESERVED_4 [24:24] */ #define PCIE_TL_TL_CONTROL_RESERVED_4_MASK 0x01000000 #define PCIE_TL_TL_CONTROL_RESERVED_4_ALIGN 0 #define PCIE_TL_TL_CONTROL_RESERVED_4_BITS 1 #define PCIE_TL_TL_CONTROL_RESERVED_4_SHIFT 24 /* PCIE_TL :: TL_CONTROL :: RESERVED_5 [23:23] */ #define PCIE_TL_TL_CONTROL_RESERVED_5_MASK 0x00800000 #define PCIE_TL_TL_CONTROL_RESERVED_5_ALIGN 0 #define PCIE_TL_TL_CONTROL_RESERVED_5_BITS 1 #define PCIE_TL_TL_CONTROL_RESERVED_5_SHIFT 23 /* PCIE_TL :: TL_CONTROL :: CRC_SWAP [22:22] */ #define PCIE_TL_TL_CONTROL_CRC_SWAP_MASK 0x00400000 #define PCIE_TL_TL_CONTROL_CRC_SWAP_ALIGN 0 #define PCIE_TL_TL_CONTROL_CRC_SWAP_BITS 1 #define PCIE_TL_TL_CONTROL_CRC_SWAP_SHIFT 22 /* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_CA_ERROR [21:21] */ #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_MASK 0x00200000 #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_ALIGN 0 #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_BITS 1 #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_SHIFT 21 /* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_UR_ERROR [20:20] */ #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_MASK 0x00100000 #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_ALIGN 0 #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_BITS 1 #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_SHIFT 20 /* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_RSV_ERROR [19:19] */ #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_MASK 0x00080000 #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_ALIGN 0 #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_BITS 1 #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_SHIFT 19 /* PCIE_TL :: TL_CONTROL :: RESERVED_6 [18:18] */ #define PCIE_TL_TL_CONTROL_RESERVED_6_MASK 0x00040000 #define PCIE_TL_TL_CONTROL_RESERVED_6_ALIGN 0 #define PCIE_TL_TL_CONTROL_RESERVED_6_BITS 1 #define PCIE_TL_TL_CONTROL_RESERVED_6_SHIFT 18 /* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_EP_ERROR [17:17] */ #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_MASK 0x00020000 #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_ALIGN 0 #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_BITS 1 #define PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_SHIFT 17 /* PCIE_TL :: TL_CONTROL :: ENABLE_BYTECOUNT_CHECK [16:16] */ #define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_MASK 0x00010000 #define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_ALIGN 0 #define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_BITS 1 #define PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_SHIFT 16 /* PCIE_TL :: TL_CONTROL :: NOT_USED [15:14] */ #define PCIE_TL_TL_CONTROL_NOT_USED_MASK 0x0000c000 #define PCIE_TL_TL_CONTROL_NOT_USED_ALIGN 0 #define PCIE_TL_TL_CONTROL_NOT_USED_BITS 2 #define PCIE_TL_TL_CONTROL_NOT_USED_SHIFT 14 /* PCIE_TL :: TL_CONTROL :: TRAFFIC_CLASS_DR [13:11] */ #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_MASK 0x00003800 #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_ALIGN 0 #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_BITS 3 #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_SHIFT 11 /* PCIE_TL :: TL_CONTROL :: TRAFFIC_CLASS_DW [10:08] */ #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_MASK 0x00000700 #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_ALIGN 0 #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_BITS 3 #define PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_SHIFT 8 /* PCIE_TL :: TL_CONTROL :: NOT_USED_0 [07:06] */ #define PCIE_TL_TL_CONTROL_NOT_USED_0_MASK 0x000000c0 #define PCIE_TL_TL_CONTROL_NOT_USED_0_ALIGN 0 #define PCIE_TL_TL_CONTROL_NOT_USED_0_BITS 2 #define PCIE_TL_TL_CONTROL_NOT_USED_0_SHIFT 6 /* PCIE_TL :: TL_CONTROL :: NOT_USED_1 [05:00] */ #define PCIE_TL_TL_CONTROL_NOT_USED_1_MASK 0x0000003f #define PCIE_TL_TL_CONTROL_NOT_USED_1_ALIGN 0 #define PCIE_TL_TL_CONTROL_NOT_USED_1_BITS 6 #define PCIE_TL_TL_CONTROL_NOT_USED_1_SHIFT 0 /**************************************************************************** * PCIE_TL :: TRANSACTION_CONFIGURATION ***************************************************************************/ /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_RETRY_BUFFER_TIMING_MOD [31:31] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_MASK 0x80000000 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_SHIFT 31 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_0 [30:30] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_MASK 0x40000000 #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_SHIFT 30 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: MSI_SINGLE_SHOT_ENABLE [29:29] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_MASK 0x20000000 #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_SHIFT 29 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_1 [28:28] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_MASK 0x10000000 #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_SHIFT 28 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: SELECT_CORE_CLOCK_OVERRIDE [27:27] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_MASK 0x08000000 #define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_SHIFT 27 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: CQ9139_FIX_ENABLE [26:26] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_MASK 0x04000000 #define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_SHIFT 26 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CMPT_PWR_CHECK [25:25] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_MASK 0x02000000 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_SHIFT 25 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CQ12696_FIX [24:24] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_MASK 0x01000000 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_SHIFT 24 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: DEVICE_SERIAL_NO_OVERRIDE [23:23] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_MASK 0x00800000 #define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_SHIFT 23 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CQ12455_FIX [22:22] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_MASK 0x00400000 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_SHIFT 22 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_TC_VC_FILTERING_CHECK [21:21] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_MASK 0x00200000 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_SHIFT 21 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: DONT_GEN_HOT_PLUG_MSG [20:20] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_MASK 0x00100000 #define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_SHIFT 20 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: IGNORE_HOTPLUG_MSG [19:19] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_MASK 0x00080000 #define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_SHIFT 19 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: MSI_MULTMSG_CAPABLE [18:16] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_MASK 0x00070000 #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_BITS 3 #define PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_SHIFT 16 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: DATA_SELECT_LIMIT [15:12] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_MASK 0x0000f000 #define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_BITS 4 #define PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_SHIFT 12 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_PL [11:11] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_MASK 0x00000800 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_SHIFT 11 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_DL [10:10] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_MASK 0x00000400 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_SHIFT 10 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_TL [09:09] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_MASK 0x00000200 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_SHIFT 9 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_2 [08:07] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_MASK 0x00000180 #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_BITS 2 #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_SHIFT 7 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: PCIE_POWER_BUDGET_CAP_ENABLE [06:06] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_MASK 0x00000040 #define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_SHIFT 6 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: LOM_CONFIGURATION [05:05] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_MASK 0x00000020 #define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_SHIFT 5 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: CONCATE_SELECT [04:04] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_MASK 0x00000010 #define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_SHIFT 4 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_3 [03:03] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_MASK 0x00000008 #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_SHIFT 3 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_9468_FIX [02:02] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_MASK 0x00000004 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_SHIFT 2 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: POWER_STATE_WRITE_MEM_ENABLE [01:01] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_MASK 0x00000002 #define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_SHIFT 1 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_9709_ENABLE [00:00] */ #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_MASK 0x00000001 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_ALIGN 0 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_BITS 1 #define PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_SHIFT 0 /**************************************************************************** * PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC ***************************************************************************/ /* PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC :: RESERVED_0 [31:00] */ #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_MASK 0xffffffff #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_ALIGN 0 #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_BITS 32 #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_SHIFT 0 /**************************************************************************** * PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 ***************************************************************************/ /* PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 :: RESERVED_0 [31:00] */ #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_MASK 0xffffffff #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_ALIGN 0 #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_BITS 32 #define PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_SHIFT 0 /**************************************************************************** * PCIE_TL :: DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC ***************************************************************************/ /* PCIE_TL :: DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC :: REG_MADDR_UPR [31:00] */ #define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_MASK 0xffffffff #define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_ALIGN 0 #define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_BITS 32 #define PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_SHIFT 0 /**************************************************************************** * PCIE_TL :: DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 ***************************************************************************/ /* PCIE_TL :: DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 :: REG_MADDR_LWR [31:00] */ #define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_MASK 0xffffffff #define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_ALIGN 0 #define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_BITS 32 #define PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_SHIFT 0 /**************************************************************************** * PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC ***************************************************************************/ /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: REG_MLEN_BE [31:24] */ #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_MASK 0xff000000 #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_ALIGN 0 #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_BITS 8 #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_SHIFT 24 /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_FIRST_DW_BYTE_ENABLES [23:20] */ #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_MASK 0x00f00000 #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_ALIGN 0 #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_BITS 4 #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_SHIFT 20 /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_LAST_DW_BYTE_ENABLES [19:16] */ #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_MASK 0x000f0000 #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_ALIGN 0 #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_BITS 4 #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_SHIFT 16 /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: RESERVED_0 [15:11] */ #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_MASK 0x0000f800 #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_ALIGN 0 #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_BITS 5 #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_SHIFT 11 /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_DW_LENGTH [10:00] */ #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_MASK 0x000007ff #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_ALIGN 0 #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_BITS 11 #define PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_SHIFT 0 /**************************************************************************** * PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC ***************************************************************************/ /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: REG_MTAG_ATTR [31:19] */ #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_MASK 0xfff80000 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_ALIGN 0 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_BITS 13 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_SHIFT 19 /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_FUNCTION [18:16] */ #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_MASK 0x00070000 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_ALIGN 0 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_BITS 3 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_SHIFT 16 /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: RESERVED_0 [15:13] */ #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_MASK 0x0000e000 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_ALIGN 0 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_BITS 3 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_SHIFT 13 /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_ATTRIBUTES [12:08] */ #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_MASK 0x00001f00 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_ALIGN 0 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_BITS 5 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_SHIFT 8 /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: RESERVED_1 [07:05] */ #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_MASK 0x000000e0 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_ALIGN 0 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_BITS 3 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_SHIFT 5 /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_TAG [04:00] */ #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_MASK 0x0000001f #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_ALIGN 0 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_BITS 5 #define PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_SHIFT 0 /**************************************************************************** * PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC ***************************************************************************/ /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: REG_SPLIT_ID [31:16] */ #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_MASK 0xffff0000 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_ALIGN 0 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_BITS 16 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_SHIFT 16 /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: RESERVED_0 [15:13] */ #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_MASK 0x0000e000 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_ALIGN 0 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_BITS 3 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_SHIFT 13 /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_ATTRIBUTES [12:11] */ #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_MASK 0x00001800 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_ALIGN 0 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_BITS 2 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_SHIFT 11 /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_TC [10:08] */ #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_MASK 0x00000700 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_ALIGN 0 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_BITS 3 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_SHIFT 8 /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: RESERVED_1 [07:05] */ #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_MASK 0x000000e0 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_ALIGN 0 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_BITS 3 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_SHIFT 5 /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_TAG [04:00] */ #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_MASK 0x0000001f #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_ALIGN 0 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_BITS 5 #define PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_SHIFT 0 /**************************************************************************** * PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC ***************************************************************************/ /* PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC :: REG_SPLIT_LEN [31:13] */ #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_MASK 0xffffe000 #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_ALIGN 0 #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_BITS 19 #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_SHIFT 13 /* PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC :: READ_DMA_SPLIT_INITIAL_BYTE_COUNT [12:00] */ #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_MASK 0x00001fff #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_ALIGN 0 #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_BITS 13 #define PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_SHIFT 0 /**************************************************************************** * PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC ***************************************************************************/ /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: REG_SM_R0_R3 [31:31] */ #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_MASK 0x80000000 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_ALIGN 0 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_BITS 1 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_SHIFT 31 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TLP_TRANSMITTER_DATA_STATE_MACHINE [30:28] */ #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_MASK 0x70000000 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_ALIGN 0 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_BITS 3 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_SHIFT 28 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE [27:23] */ #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_MASK 0x0f800000 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_ALIGN 0 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_BITS 5 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_SHIFT 23 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: RESERVED_0 [22:07] */ #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_MASK 0x007fff80 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_ALIGN 0 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_BITS 16 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_SHIFT 7 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: READ_DMA_RAW_REQUEST [06:06] */ #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_MASK 0x00000040 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_ALIGN 0 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_BITS 1 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_SHIFT 6 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: WRITE_DMA_RAW_REQUEST [05:05] */ #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_MASK 0x00000020 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_ALIGN 0 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_BITS 1 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_SHIFT 5 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: INTERRUPT_MSG_GATED_REQUEST [04:04] */ #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_MASK 0x00000010 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_ALIGN 0 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_BITS 1 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_SHIFT 4 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: MSI_DMA_GATED_REQUEST [03:03] */ #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_MASK 0x00000008 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_ALIGN 0 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_BITS 1 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_SHIFT 3 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TARGET_COMPLETION_OR_MSG_GATED_REQUEST [02:02] */ #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_MASK 0x00000004 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_ALIGN 0 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_BITS 1 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_SHIFT 2 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: READ_DMA_GATED_REQUEST [01:01] */ #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_MASK 0x00000002 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_ALIGN 0 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_BITS 1 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_SHIFT 1 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: WRITE_DMA_GATED_REQUEST [00:00] */ #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_MASK 0x00000001 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_ALIGN 0 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_BITS 1 #define PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_SHIFT 0 /**************************************************************************** * PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC ***************************************************************************/ /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: REG_DMA_CMPT_MISC2 [31:29] */ #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_MASK 0xe0000000 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_ALIGN 0 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_BITS 3 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_SHIFT 29 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_BYTE_LENGTH_REMAINING [28:16] */ #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_MASK 0x1fff0000 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_ALIGN 0 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_BITS 13 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_SHIFT 16 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: NOT_USED [15:15] */ #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_MASK 0x00008000 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_ALIGN 0 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_BITS 1 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_SHIFT 15 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED [14:14] */ #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_MASK 0x00004000 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_ALIGN 0 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_BITS 1 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_SHIFT 14 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED [13:13] */ #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_MASK 0x00002000 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_ALIGN 0 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_BITS 1 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_SHIFT 13 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1 [12:12] */ #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_MASK 0x00001000 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_ALIGN 0 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_BITS 1 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_SHIFT 12 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST [11:11] */ #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_MASK 0x00000800 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_ALIGN 0 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_BITS 1 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_SHIFT 11 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS [10:10] */ #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_MASK 0x00000400 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_ALIGN 0 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_BITS 1 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_SHIFT 10 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TLP_MATCHES_REQUEST_FULLY [09:09] */ #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_MASK 0x00000200 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_ALIGN 0 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_BITS 1 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_SHIFT 9 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_DW_DATA_VALID_ADDRESS_ACK [08:08] */ #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_MASK 0x00000100 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_ALIGN 0 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_BITS 1 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_SHIFT 8 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER [07:04] */ #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_MASK 0x000000f0 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_ALIGN 0 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_BITS 4 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_SHIFT 4 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: FRAME_DEAD_TIME_ERROR_COUNTER [03:00] */ #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_MASK 0x0000000f #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_ALIGN 0 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_BITS 4 #define PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_SHIFT 0 /**************************************************************************** * PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC ***************************************************************************/ /* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: REG_SPLITCTL_MISC0 [31:29] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_MASK 0xe0000000 #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_BITS 3 #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_SHIFT 29 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING [28:16] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_MASK 0x1fff0000 #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_BITS 13 #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_SHIFT 16 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID [15:00] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_MASK 0x0000ffff #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_BITS 16 #define PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_SHIFT 0 /**************************************************************************** * PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC ***************************************************************************/ /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: REG_SPLITCTL_MISC1 [31:16] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_MASK 0xffff0000 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_BITS 16 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_SHIFT 16 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: RESERVED_0 [15:15] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_MASK 0x00008000 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_BITS 1 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_SHIFT 15 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS [14:08] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_MASK 0x00007f00 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_BITS 7 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_SHIFT 8 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: RESERVED_1 [07:07] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_MASK 0x00000080 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_BITS 1 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_SHIFT 7 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE [06:05] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_MASK 0x00000060 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_BITS 2 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_SHIFT 5 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_TAG [04:00] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_MASK 0x0000001f #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_BITS 5 #define PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_SHIFT 0 /**************************************************************************** * PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC ***************************************************************************/ /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: REG_SPLITCTL_MISC2 [31:31] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_MASK 0x80000000 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_BITS 1 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_SHIFT 31 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS [30:30] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_MASK 0x40000000 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_BITS 1 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_SHIFT 30 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: COMPLETION_TLP_MATCHES_VALID_TAG [29:29] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_MASK 0x20000000 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_BITS 1 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_SHIFT 29 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: UPDATED_BYTE_COUNT [28:16] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_MASK 0x1fff0000 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_BITS 13 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_SHIFT 16 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: RESERVED_0 [15:08] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_MASK 0x0000ff00 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_BITS 8 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_SHIFT 8 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: SPLIT_TABLE_VALID_ARRAY [07:00] */ #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_MASK 0x000000ff #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_ALIGN 0 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_BITS 8 #define PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_SHIFT 0 /**************************************************************************** * PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO ***************************************************************************/ /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: RESERVED_0 [31:17] */ #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_MASK 0xfffe0000 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_ALIGN 0 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_BITS 15 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_SHIFT 17 /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: CONFIG_WRITE_INDICATER [16:16] */ #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_MASK 0x00010000 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_ALIGN 0 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_BITS 1 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_SHIFT 16 /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: BUS_NUMBER [15:08] */ #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_MASK 0x0000ff00 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_ALIGN 0 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_BITS 8 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_SHIFT 8 /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: DEVICE_NUMBER [07:03] */ #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_MASK 0x000000f8 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_ALIGN 0 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_BITS 5 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_SHIFT 3 /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: FUNCTION_NUMBER [02:00] */ #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_MASK 0x00000007 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_ALIGN 0 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_BITS 3 #define PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_SHIFT 0 /**************************************************************************** * PCIE_TL :: TL_DEBUG ***************************************************************************/ /* PCIE_TL :: TL_DEBUG :: A4_DEVICE_INDICATION_BIT [31:31] */ #define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_MASK 0x80000000 #define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_ALIGN 0 #define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_BITS 1 #define PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_SHIFT 31 /* PCIE_TL :: TL_DEBUG :: B1_DEVICE_INDICATION_BIT [30:30] */ #define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_MASK 0x40000000 #define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_ALIGN 0 #define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_BITS 1 #define PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_SHIFT 30 /* PCIE_TL :: TL_DEBUG :: RESERVED_0 [29:00] */ #define PCIE_TL_TL_DEBUG_RESERVED_0_MASK 0x3fffffff #define PCIE_TL_TL_DEBUG_RESERVED_0_ALIGN 0 #define PCIE_TL_TL_DEBUG_RESERVED_0_BITS 30 #define PCIE_TL_TL_DEBUG_RESERVED_0_SHIFT 0 /**************************************************************************** * BCM70012_TGT_TOP_PCIE_DLL ***************************************************************************/ /**************************************************************************** * PCIE_DLL :: DATA_LINK_CONTROL ***************************************************************************/ /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_0 [31:30] */ #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_MASK 0xc0000000 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_BITS 2 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_SHIFT 30 /* PCIE_DLL :: DATA_LINK_CONTROL :: CQ28001_FIX_ENABLE [29:29] */ #define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_MASK 0x20000000 #define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_SHIFT 29 /* PCIE_DLL :: DATA_LINK_CONTROL :: CQ27820_FIX_ENABLE [28:28] */ #define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_MASK 0x10000000 #define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_SHIFT 28 /* PCIE_DLL :: DATA_LINK_CONTROL :: ASPM_L1_ENABLE [27:27] */ #define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_MASK 0x08000000 #define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_SHIFT 27 /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_1 [26:25] */ #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_MASK 0x06000000 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_BITS 2 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_SHIFT 25 /* PCIE_DLL :: DATA_LINK_CONTROL :: CQ11211 [24:24] */ #define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_MASK 0x01000000 #define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_CQ11211_SHIFT 24 /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_2 [23:23] */ #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_MASK 0x00800000 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_SHIFT 23 /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_3 [22:22] */ #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_MASK 0x00400000 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_SHIFT 22 /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_4 [21:21] */ #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_MASK 0x00200000 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_SHIFT 21 /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_5 [20:20] */ #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_MASK 0x00100000 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_SHIFT 20 /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_6 [19:19] */ #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_MASK 0x00080000 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_SHIFT 19 /* PCIE_DLL :: DATA_LINK_CONTROL :: PLL_REFSEL_SWITCH_CONTROL_CQ11011 [18:18] */ #define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_MASK 0x00040000 #define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_SHIFT 18 /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_7 [17:17] */ #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_MASK 0x00020000 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_SHIFT 17 /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_MANAGEMENT_CONTROL [16:16] */ #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_MASK 0x00010000 #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_SHIFT 16 /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_TRANSMITTER [15:15] */ #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_MASK 0x00008000 #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_SHIFT 15 /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_PLL [14:14] */ #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_MASK 0x00004000 #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_SHIFT 14 /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_RECEIVER [13:13] */ #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_MASK 0x00002000 #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_SHIFT 13 /* PCIE_DLL :: DATA_LINK_CONTROL :: ENABLE_BEACON [12:12] */ #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_MASK 0x00001000 #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_SHIFT 12 /* PCIE_DLL :: DATA_LINK_CONTROL :: AUTOMATIC_TIMER_THRESHOLD_ENABLE [11:11] */ #define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_MASK 0x00000800 #define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_SHIFT 11 /* PCIE_DLL :: DATA_LINK_CONTROL :: ENABLE_DLLP_TIMEOUT_MECHANISM [10:10] */ #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_MASK 0x00000400 #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_SHIFT 10 /* PCIE_DLL :: DATA_LINK_CONTROL :: CHECK_RECEIVE_FLOW_CONTROL_CREDITS [09:09] */ #define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_MASK 0x00000200 #define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_SHIFT 9 /* PCIE_DLL :: DATA_LINK_CONTROL :: LINK_ENABLE [08:08] */ #define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_MASK 0x00000100 #define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_BITS 1 #define PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_SHIFT 8 /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_MANAGEMENT_CONTROL_2 [07:00] */ #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_MASK 0x000000ff #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_ALIGN 0 #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_BITS 8 #define PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_SHIFT 0 /**************************************************************************** * PCIE_DLL :: DATA_LINK_STATUS ***************************************************************************/ /* PCIE_DLL :: DATA_LINK_STATUS :: RESERVED_0 [31:26] */ #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_MASK 0xfc000000 #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_BITS 6 #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_SHIFT 26 /* PCIE_DLL :: DATA_LINK_STATUS :: PHY_LINK_STATE [25:23] */ #define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_MASK 0x03800000 #define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_BITS 3 #define PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_SHIFT 23 /* PCIE_DLL :: DATA_LINK_STATUS :: POWER_MANAGEMENT_STATE [22:19] */ #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_MASK 0x00780000 #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_BITS 4 #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_SHIFT 19 /* PCIE_DLL :: DATA_LINK_STATUS :: POWER_MANAGEMENT_SUB_STATE [18:17] */ #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_MASK 0x00060000 #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_BITS 2 #define PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_SHIFT 17 /* PCIE_DLL :: DATA_LINK_STATUS :: DATA_LINK_UP [16:16] */ #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_MASK 0x00010000 #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_BITS 1 #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_SHIFT 16 /* PCIE_DLL :: DATA_LINK_STATUS :: RESERVED_1 [15:11] */ #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_MASK 0x0000f800 #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_BITS 5 #define PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_SHIFT 11 /* PCIE_DLL :: DATA_LINK_STATUS :: PME_TURN_OFF_STATUS_IN_D0 [10:10] */ #define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_MASK 0x00000400 #define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_BITS 1 #define PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_SHIFT 10 /* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_UPDATE_TIMEOUT [09:09] */ #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_MASK 0x00000200 #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_BITS 1 #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_SHIFT 9 /* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_RECEIVE_OVERFLOW [08:08] */ #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_MASK 0x00000100 #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_BITS 1 #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_SHIFT 8 /* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_PROTOCOL_ERROR [07:07] */ #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_MASK 0x00000080 #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_BITS 1 #define PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_SHIFT 7 /* PCIE_DLL :: DATA_LINK_STATUS :: DATA_LINK_PROTOCOL_ERROR [06:06] */ #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_MASK 0x00000040 #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_BITS 1 #define PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_SHIFT 6 /* PCIE_DLL :: DATA_LINK_STATUS :: REPLAY_ROLLOVER [05:05] */ #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_MASK 0x00000020 #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_BITS 1 #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_SHIFT 5 /* PCIE_DLL :: DATA_LINK_STATUS :: REPLAY_TIMEOUT [04:04] */ #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_MASK 0x00000010 #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_BITS 1 #define PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_SHIFT 4 /* PCIE_DLL :: DATA_LINK_STATUS :: NAK_RECEIVED [03:03] */ #define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_MASK 0x00000008 #define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_BITS 1 #define PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_SHIFT 3 /* PCIE_DLL :: DATA_LINK_STATUS :: DLLP_ERROR [02:02] */ #define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_MASK 0x00000004 #define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_BITS 1 #define PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_SHIFT 2 /* PCIE_DLL :: DATA_LINK_STATUS :: BAD_TLP_SEQUENCE_NUMBER [01:01] */ #define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_MASK 0x00000002 #define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_BITS 1 #define PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_SHIFT 1 /* PCIE_DLL :: DATA_LINK_STATUS :: TLP_ERROR [00:00] */ #define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_MASK 0x00000001 #define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_ALIGN 0 #define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_BITS 1 #define PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_SHIFT 0 /**************************************************************************** * PCIE_DLL :: DATA_LINK_ATTENTION ***************************************************************************/ /* PCIE_DLL :: DATA_LINK_ATTENTION :: RESERVED_0 [31:06] */ #define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_MASK 0xffffffc0 #define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_BITS 26 #define PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_SHIFT 6 /* PCIE_DLL :: DATA_LINK_ATTENTION :: DATA_LINK_LAYER_PACKET_TEST_INDICATOR [05:05] */ #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_MASK 0x00000020 #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_BITS 1 #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_SHIFT 5 /* PCIE_DLL :: DATA_LINK_ATTENTION :: DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR [04:04] */ #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_MASK 0x00000010 #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_BITS 1 #define PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_SHIFT 4 /* PCIE_DLL :: DATA_LINK_ATTENTION :: NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR [03:03] */ #define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_MASK 0x00000008 #define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_BITS 1 #define PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_SHIFT 3 /* PCIE_DLL :: DATA_LINK_ATTENTION :: DLLP_ERROR_COUNTER_ATTENTION_INDICATOR [02:02] */ #define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_MASK 0x00000004 #define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_BITS 1 #define PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_SHIFT 2 /* PCIE_DLL :: DATA_LINK_ATTENTION :: TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR [01:01] */ #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_MASK 0x00000002 #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_BITS 1 #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_SHIFT 1 /* PCIE_DLL :: DATA_LINK_ATTENTION :: TLP_ERROR_COUNTER_ATTENTION_INDICATOR [00:00] */ #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_MASK 0x00000001 #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_BITS 1 #define PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_SHIFT 0 /**************************************************************************** * PCIE_DLL :: DATA_LINK_ATTENTION_MASK ***************************************************************************/ /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: RESERVED_0 [31:08] */ #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_MASK 0xffffff00 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_BITS 24 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_SHIFT 8 /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: UNUSED_0 [07:06] */ #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_MASK 0x000000c0 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_BITS 2 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_SHIFT 6 /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK [05:05] */ #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_MASK 0x00000020 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_BITS 1 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_SHIFT 5 /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DATA_LINK_LAYER_ERROR_ATTENTION_MASK [04:04] */ #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_MASK 0x00000010 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_BITS 1 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_SHIFT 4 /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: NAK_RECEIVED_COUNTER_ATTENTION_MASK [03:03] */ #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_MASK 0x00000008 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_BITS 1 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_SHIFT 3 /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DLLP_ERROR_COUNTER_ATTENTION_MASK [02:02] */ #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_MASK 0x00000004 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_BITS 1 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_SHIFT 2 /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK [01:01] */ #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_MASK 0x00000002 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_BITS 1 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_SHIFT 1 /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: TLP_ERROR_COUNTER_ATTENTION_MASK [00:00] */ #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_MASK 0x00000001 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_ALIGN 0 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_BITS 1 #define PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_SHIFT 0 /**************************************************************************** * PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG ***************************************************************************/ /* PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 /* PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: NEXT_TRANSMIT_SEQUENCE_NUMBER [11:00] */ #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_BITS 12 #define PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 /**************************************************************************** * PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG ***************************************************************************/ /* PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 /* PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER [11:00] */ #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_BITS 12 #define PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 /**************************************************************************** * PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG ***************************************************************************/ /* PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 /* PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: PURGED_TRANSMIT_SEQUENCE_NUMBER [11:00] */ #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_ALIGN 0 #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_BITS 12 #define PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 /**************************************************************************** * PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG ***************************************************************************/ /* PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_ALIGN 0 #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_BITS 20 #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 /* PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG :: RECEIVE_SEQUENCE_NUMBER [11:00] */ #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_MASK 0x00000fff #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_ALIGN 0 #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_BITS 12 #define PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_SHIFT 0 /**************************************************************************** * PCIE_DLL :: DATA_LINK_REPLAY ***************************************************************************/ /* PCIE_DLL :: DATA_LINK_REPLAY :: RESERVED_0 [31:23] */ #define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_MASK 0xff800000 #define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_ALIGN 0 #define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_BITS 9 #define PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_SHIFT 23 /* PCIE_DLL :: DATA_LINK_REPLAY :: REPLAY_TIMEOUT_VALUE [22:10] */ #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_MASK 0x007ffc00 #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_ALIGN 0 #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_BITS 13 #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_SHIFT 10 /* PCIE_DLL :: DATA_LINK_REPLAY :: REPLAY_BUFFER_SIZE [09:00] */ #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_MASK 0x000003ff #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_ALIGN 0 #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_BITS 10 #define PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_SHIFT 0 /**************************************************************************** * PCIE_DLL :: DATA_LINK_ACK_TIMEOUT ***************************************************************************/ /* PCIE_DLL :: DATA_LINK_ACK_TIMEOUT :: RESERVED_0 [31:11] */ #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_MASK 0xfffff800 #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_ALIGN 0 #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_BITS 21 #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_SHIFT 11 /* PCIE_DLL :: DATA_LINK_ACK_TIMEOUT :: ACK_LATENCY_TIMEOUT_VALUE [10:00] */ #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_MASK 0x000007ff #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_ALIGN 0 #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_BITS 11 #define PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_SHIFT 0 /**************************************************************************** * PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD ***************************************************************************/ /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: RESERVED_0 [31:24] */ #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_MASK 0xff000000 #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_ALIGN 0 #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_BITS 8 #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_SHIFT 24 /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L0_STAY_TIME [23:20] */ #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_MASK 0x00f00000 #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_ALIGN 0 #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_BITS 4 #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_SHIFT 20 /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L1_STAY_TIME [19:16] */ #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_MASK 0x000f0000 #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_ALIGN 0 #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_BITS 4 #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_SHIFT 16 /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L1_THRESHOLD [15:08] */ #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_MASK 0x0000ff00 #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_ALIGN 0 #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_BITS 8 #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_SHIFT 8 /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L0S_THRESHOLD [07:00] */ #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_MASK 0x000000ff #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_ALIGN 0 #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_BITS 8 #define PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_SHIFT 0 /**************************************************************************** * PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG ***************************************************************************/ /* PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG :: RESERVED_0 [31:11] */ #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_ALIGN 0 #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_BITS 21 #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_SHIFT 11 /* PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG :: RETRY_BUFFER_WRITE_POINTER [10:00] */ #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_MASK 0x000007ff #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_ALIGN 0 #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_BITS 11 #define PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_SHIFT 0 /**************************************************************************** * PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG ***************************************************************************/ /* PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG :: RESERVED_0 [31:11] */ #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_ALIGN 0 #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_BITS 21 #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_SHIFT 11 /* PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG :: RETRY_BUFFER_READ_POINTER [10:00] */ #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_MASK 0x000007ff #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_ALIGN 0 #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_BITS 11 #define PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_SHIFT 0 /**************************************************************************** * PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG ***************************************************************************/ /* PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG :: RESERVED_0 [31:11] */ #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_ALIGN 0 #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_BITS 21 #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_SHIFT 11 /* PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG :: RETRY_BUFFER_PURGED_POINTER [10:00] */ #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_MASK 0x000007ff #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_ALIGN 0 #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_BITS 11 #define PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_SHIFT 0 /**************************************************************************** * PCIE_DLL :: RETRY_BUFFER_READ_WRITE_DEBUG_PORT ***************************************************************************/ /* PCIE_DLL :: RETRY_BUFFER_READ_WRITE_DEBUG_PORT :: RETRY_BUFFER_DATA [31:00] */ #define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_MASK 0xffffffff #define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_ALIGN 0 #define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_BITS 32 #define PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_SHIFT 0 /**************************************************************************** * PCIE_DLL :: ERROR_COUNT_THRESHOLD ***************************************************************************/ /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: RESERVED_0 [31:15] */ #define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_MASK 0xffff8000 #define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_ALIGN 0 #define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_BITS 17 #define PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_SHIFT 15 /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD [14:12] */ #define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_MASK 0x00007000 #define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_ALIGN 0 #define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_BITS 3 #define PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_SHIFT 12 /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: NAK_RECEIVED_COUNT_THRESHOLD [11:08] */ #define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_MASK 0x00000f00 #define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_ALIGN 0 #define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_BITS 4 #define PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_SHIFT 8 /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: DLLP_ERROR_COUNT_THRESHOLD [07:04] */ #define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_MASK 0x000000f0 #define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_ALIGN 0 #define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_BITS 4 #define PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_SHIFT 4 /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: TLP_ERROR_COUNT_THRESHOLD [03:00] */ #define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_MASK 0x0000000f #define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_ALIGN 0 #define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_BITS 4 #define PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_SHIFT 0 /**************************************************************************** * PCIE_DLL :: TL_ERROR_COUNTER ***************************************************************************/ /* PCIE_DLL :: TL_ERROR_COUNTER :: RESERVED_0 [31:24] */ #define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_MASK 0xff000000 #define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_ALIGN 0 #define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_BITS 8 #define PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_SHIFT 24 /* PCIE_DLL :: TL_ERROR_COUNTER :: TLP_BAD_SEQUENCE_NUMBER_COUNTER [23:16] */ #define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_MASK 0x00ff0000 #define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_ALIGN 0 #define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_BITS 8 #define PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_SHIFT 16 /* PCIE_DLL :: TL_ERROR_COUNTER :: TLP_ERROR_COUNTER [15:00] */ #define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_MASK 0x0000ffff #define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_ALIGN 0 #define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_BITS 16 #define PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_SHIFT 0 /**************************************************************************** * PCIE_DLL :: DLLP_ERROR_COUNTER ***************************************************************************/ /* PCIE_DLL :: DLLP_ERROR_COUNTER :: RESERVED_0 [31:16] */ #define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_MASK 0xffff0000 #define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_ALIGN 0 #define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_BITS 16 #define PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_SHIFT 16 /* PCIE_DLL :: DLLP_ERROR_COUNTER :: DLLP_ERROR_COUNTER [15:00] */ #define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_MASK 0x0000ffff #define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_ALIGN 0 #define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_BITS 16 #define PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_SHIFT 0 /**************************************************************************** * PCIE_DLL :: NAK_RECEIVED_COUNTER ***************************************************************************/ /* PCIE_DLL :: NAK_RECEIVED_COUNTER :: RESERVED_0 [31:16] */ #define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_MASK 0xffff0000 #define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_ALIGN 0 #define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_BITS 16 #define PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_SHIFT 16 /* PCIE_DLL :: NAK_RECEIVED_COUNTER :: NAK_RECEIVED_COUNTER [15:00] */ #define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_MASK 0x0000ffff #define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_ALIGN 0 #define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_BITS 16 #define PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_SHIFT 0 /**************************************************************************** * PCIE_DLL :: DATA_LINK_TEST ***************************************************************************/ /* PCIE_DLL :: DATA_LINK_TEST :: RESERVED_0 [31:16] */ #define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_MASK 0xffff0000 #define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_BITS 16 #define PCIE_DLL_DATA_LINK_TEST_RESERVED_0_SHIFT 16 /* PCIE_DLL :: DATA_LINK_TEST :: STORE_RECEIVE_TLPS [15:15] */ #define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_MASK 0x00008000 #define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_SHIFT 15 /* PCIE_DLL :: DATA_LINK_TEST :: DISABLE_TLPS [14:14] */ #define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_MASK 0x00004000 #define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_SHIFT 14 /* PCIE_DLL :: DATA_LINK_TEST :: DISABLE_DLLPS [13:13] */ #define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_MASK 0x00002000 #define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_SHIFT 13 /* PCIE_DLL :: DATA_LINK_TEST :: FORCE_PHY_LINK_UP [12:12] */ #define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_MASK 0x00001000 #define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_SHIFT 12 /* PCIE_DLL :: DATA_LINK_TEST :: BYPASS_FLOW_CONTROL [11:11] */ #define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_MASK 0x00000800 #define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_SHIFT 11 /* PCIE_DLL :: DATA_LINK_TEST :: ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE [10:10] */ #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_MASK 0x00000400 #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_SHIFT 10 /* PCIE_DLL :: DATA_LINK_TEST :: ENABLE_RAM_OVERSTRESS_TEST_MODE [09:09] */ #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_MASK 0x00000200 #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_SHIFT 9 /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_SLOW_CLOCK [08:08] */ #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_MASK 0x00000100 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_SHIFT 8 /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_COMPLETION_TIMER [07:07] */ #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_MASK 0x00000080 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_SHIFT 7 /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_REPLAY_TIMER [06:06] */ #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_MASK 0x00000040 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_SHIFT 6 /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_ACK_LATENCY_TIMER [05:05] */ #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_MASK 0x00000020 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_SHIFT 5 /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_PME_SERVICE_TIMER [04:04] */ #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_MASK 0x00000010 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_SHIFT 4 /* PCIE_DLL :: DATA_LINK_TEST :: FORCE_PURGE [03:03] */ #define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_MASK 0x00000008 #define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_SHIFT 3 /* PCIE_DLL :: DATA_LINK_TEST :: FORCE_RETRY [02:02] */ #define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_MASK 0x00000004 #define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_SHIFT 2 /* PCIE_DLL :: DATA_LINK_TEST :: INVERT_CRC [01:01] */ #define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_MASK 0x00000002 #define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_SHIFT 1 /* PCIE_DLL :: DATA_LINK_TEST :: SEND_BAD_CRC_BIT [00:00] */ #define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_MASK 0x00000001 #define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_ALIGN 0 #define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_BITS 1 #define PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_SHIFT 0 /**************************************************************************** * PCIE_DLL :: PACKET_BIST ***************************************************************************/ /* PCIE_DLL :: PACKET_BIST :: RESERVED_0 [31:24] */ #define PCIE_DLL_PACKET_BIST_RESERVED_0_MASK 0xff000000 #define PCIE_DLL_PACKET_BIST_RESERVED_0_ALIGN 0 #define PCIE_DLL_PACKET_BIST_RESERVED_0_BITS 8 #define PCIE_DLL_PACKET_BIST_RESERVED_0_SHIFT 24 /* PCIE_DLL :: PACKET_BIST :: PACKET_CHECKER_LOCKED [23:23] */ #define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_MASK 0x00800000 #define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_ALIGN 0 #define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_BITS 1 #define PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_SHIFT 23 /* PCIE_DLL :: PACKET_BIST :: RECEIVE_MISMATCH [22:22] */ #define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_MASK 0x00400000 #define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_ALIGN 0 #define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_BITS 1 #define PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_SHIFT 22 /* PCIE_DLL :: PACKET_BIST :: ENABLE_RANDOM_TLP_LENGTH [21:21] */ #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_MASK 0x00200000 #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_ALIGN 0 #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_BITS 1 #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_SHIFT 21 /* PCIE_DLL :: PACKET_BIST :: TLP_LENGTH [20:10] */ #define PCIE_DLL_PACKET_BIST_TLP_LENGTH_MASK 0x001ffc00 #define PCIE_DLL_PACKET_BIST_TLP_LENGTH_ALIGN 0 #define PCIE_DLL_PACKET_BIST_TLP_LENGTH_BITS 11 #define PCIE_DLL_PACKET_BIST_TLP_LENGTH_SHIFT 10 /* PCIE_DLL :: PACKET_BIST :: ENABLE_RANDOM_IPG_LENGTH [09:09] */ #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_MASK 0x00000200 #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_ALIGN 0 #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_BITS 1 #define PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_SHIFT 9 /* PCIE_DLL :: PACKET_BIST :: IPG_LENGTH [08:02] */ #define PCIE_DLL_PACKET_BIST_IPG_LENGTH_MASK 0x000001fc #define PCIE_DLL_PACKET_BIST_IPG_LENGTH_ALIGN 0 #define PCIE_DLL_PACKET_BIST_IPG_LENGTH_BITS 7 #define PCIE_DLL_PACKET_BIST_IPG_LENGTH_SHIFT 2 /* PCIE_DLL :: PACKET_BIST :: TRANSMIT_START [01:01] */ #define PCIE_DLL_PACKET_BIST_TRANSMIT_START_MASK 0x00000002 #define PCIE_DLL_PACKET_BIST_TRANSMIT_START_ALIGN 0 #define PCIE_DLL_PACKET_BIST_TRANSMIT_START_BITS 1 #define PCIE_DLL_PACKET_BIST_TRANSMIT_START_SHIFT 1 /* PCIE_DLL :: PACKET_BIST :: ENABLE_PACKET_GENERATOR_TEST_MODE [00:00] */ #define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_MASK 0x00000001 #define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_ALIGN 0 #define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_BITS 1 #define PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_SHIFT 0 /**************************************************************************** * PCIE_DLL :: LINK_PCIE_1_1_CONTROL ***************************************************************************/ /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: RTBF_CT_2_0 [31:29] */ #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_MASK 0xe0000000 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_ALIGN 0 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_BITS 3 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_SHIFT 29 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: RTBF_SAM_1_0 [28:27] */ #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_MASK 0x18000000 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_ALIGN 0 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_BITS 2 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_SHIFT 27 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: UNUSED_0 [26:10] */ #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_MASK 0x07fffc00 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_ALIGN 0 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_BITS 17 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_SHIFT 10 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: SELOCALXTAL [09:09] */ #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_MASK 0x00000200 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_ALIGN 0 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_BITS 1 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_SHIFT 9 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L2_PLL_POWERDOWN_DISABLE [08:08] */ #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_MASK 0x00000100 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_ALIGN 0 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_BITS 1 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_SHIFT 8 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_PLL_POWERDOWN_DISABLE [07:07] */ #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_MASK 0x00000080 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_ALIGN 0 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_BITS 1 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_SHIFT 7 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L2_D3PM_CLKREQ_DISABLE [06:06] */ #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_MASK 0x00000040 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_ALIGN 0 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_BITS 1 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_SHIFT 6 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_D3PM_CLKREQ_DISABLE [05:05] */ #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_MASK 0x00000020 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_ALIGN 0 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_BITS 1 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_SHIFT 5 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_ASPM_CLKREQ_DISABLE [04:04] */ #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_MASK 0x00000010 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_ALIGN 0 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_BITS 1 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_SHIFT 4 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_PLL_PD_W_O_CLKREQ [03:03] */ #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_MASK 0x00000008 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_ALIGN 0 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_BITS 1 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_SHIFT 3 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DASPM10USTIMER [02:02] */ #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_MASK 0x00000004 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_ALIGN 0 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_BITS 1 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_SHIFT 2 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DFFU_EL1 [01:01] */ #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_MASK 0x00000002 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_ALIGN 0 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_BITS 1 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_SHIFT 1 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DFLOWCTLUPDATE1_1 [00:00] */ #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_MASK 0x00000001 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_ALIGN 0 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_BITS 1 #define PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_SHIFT 0 /**************************************************************************** * BCM70012_TGT_TOP_PCIE_PHY ***************************************************************************/ /**************************************************************************** * PCIE_PHY :: PHY_MODE ***************************************************************************/ /* PCIE_PHY :: PHY_MODE :: RESERVED_0 [31:04] */ #define PCIE_PHY_PHY_MODE_RESERVED_0_MASK 0xfffffff0 #define PCIE_PHY_PHY_MODE_RESERVED_0_ALIGN 0 #define PCIE_PHY_PHY_MODE_RESERVED_0_BITS 28 #define PCIE_PHY_PHY_MODE_RESERVED_0_SHIFT 4 /* PCIE_PHY :: PHY_MODE :: UPSTREAM_DEV [03:03] */ #define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_MASK 0x00000008 #define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_ALIGN 0 #define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_BITS 1 #define PCIE_PHY_PHY_MODE_UPSTREAM_DEV_SHIFT 3 /* PCIE_PHY :: PHY_MODE :: SERDES_SA_MODE [02:02] */ #define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_MASK 0x00000004 #define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_ALIGN 0 #define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_BITS 1 #define PCIE_PHY_PHY_MODE_SERDES_SA_MODE_SHIFT 2 /* PCIE_PHY :: PHY_MODE :: LINK_DISABLE [01:01] */ #define PCIE_PHY_PHY_MODE_LINK_DISABLE_MASK 0x00000002 #define PCIE_PHY_PHY_MODE_LINK_DISABLE_ALIGN 0 #define PCIE_PHY_PHY_MODE_LINK_DISABLE_BITS 1 #define PCIE_PHY_PHY_MODE_LINK_DISABLE_SHIFT 1 /* PCIE_PHY :: PHY_MODE :: SOFT_RESET [00:00] */ #define PCIE_PHY_PHY_MODE_SOFT_RESET_MASK 0x00000001 #define PCIE_PHY_PHY_MODE_SOFT_RESET_ALIGN 0 #define PCIE_PHY_PHY_MODE_SOFT_RESET_BITS 1 #define PCIE_PHY_PHY_MODE_SOFT_RESET_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_LINK_STATUS ***************************************************************************/ /* PCIE_PHY :: PHY_LINK_STATUS :: RESERVED_0 [31:10] */ #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_MASK 0xfffffc00 #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_ALIGN 0 #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_BITS 22 #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_SHIFT 10 /* PCIE_PHY :: PHY_LINK_STATUS :: BUFFER_OVERRUN [09:09] */ #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_MASK 0x00000200 #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_ALIGN 0 #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_BITS 1 #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_SHIFT 9 /* PCIE_PHY :: PHY_LINK_STATUS :: BUFFER_UNDERRUN [08:08] */ #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_MASK 0x00000100 #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_ALIGN 0 #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_BITS 1 #define PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_SHIFT 8 /* PCIE_PHY :: PHY_LINK_STATUS :: LINK_PARTNER_REQUEST_LOOPBACK [07:07] */ #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_MASK 0x00000080 #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_ALIGN 0 #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_BITS 1 #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_SHIFT 7 /* PCIE_PHY :: PHY_LINK_STATUS :: LINK_PARTNER_DISABLE_SCRAMBLER [06:06] */ #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_MASK 0x00000040 #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_ALIGN 0 #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_BITS 1 #define PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_SHIFT 6 /* PCIE_PHY :: PHY_LINK_STATUS :: EXTENDED_SYNCH [05:05] */ #define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_MASK 0x00000020 #define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_ALIGN 0 #define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_BITS 1 #define PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_SHIFT 5 /* PCIE_PHY :: PHY_LINK_STATUS :: POLARITY_INVERTED [04:04] */ #define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_MASK 0x00000010 #define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_ALIGN 0 #define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_BITS 1 #define PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_SHIFT 4 /* PCIE_PHY :: PHY_LINK_STATUS :: LINK_UP [03:03] */ #define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_MASK 0x00000008 #define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_ALIGN 0 #define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_BITS 1 #define PCIE_PHY_PHY_LINK_STATUS_LINK_UP_SHIFT 3 /* PCIE_PHY :: PHY_LINK_STATUS :: LINK_TRAINING [02:02] */ #define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_MASK 0x00000004 #define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_ALIGN 0 #define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_BITS 1 #define PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_SHIFT 2 /* PCIE_PHY :: PHY_LINK_STATUS :: RECEIVE_DATA_VALID [01:01] */ #define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_MASK 0x00000002 #define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_ALIGN 0 #define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_BITS 1 #define PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_SHIFT 1 /* PCIE_PHY :: PHY_LINK_STATUS :: RESERVED_1 [00:00] */ #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_MASK 0x00000001 #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_ALIGN 0 #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_BITS 1 #define PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_LINK_LTSSM_CONTROL ***************************************************************************/ /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RESERVED_0 [31:08] */ #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_MASK 0xffffff00 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_ALIGN 0 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_BITS 24 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_SHIFT 8 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DISABLESCRAMBLE [07:07] */ #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_MASK 0x00000080 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_ALIGN 0 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_BITS 1 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_SHIFT 7 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DETECTSTATE [06:06] */ #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_MASK 0x00000040 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_ALIGN 0 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_BITS 1 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_SHIFT 6 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: POLLINGSTATE [05:05] */ #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_MASK 0x00000020 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_ALIGN 0 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_BITS 1 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_SHIFT 5 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: CONFIGSTATE [04:04] */ #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_MASK 0x00000010 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_ALIGN 0 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_BITS 1 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_SHIFT 4 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RECOVSTATE [03:03] */ #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_MASK 0x00000008 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_ALIGN 0 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_BITS 1 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_SHIFT 3 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: EXTLBSTATE [02:02] */ #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_MASK 0x00000004 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_ALIGN 0 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_BITS 1 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_SHIFT 2 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RESETSTATE [01:01] */ #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_MASK 0x00000002 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_ALIGN 0 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_BITS 1 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_SHIFT 1 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DISABLESTATE [00:00] */ #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_MASK 0x00000001 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_ALIGN 0 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_BITS 1 #define PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER ***************************************************************************/ /* PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER :: RESERVED_0 [31:08] */ #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_MASK 0xffffff00 #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_ALIGN 0 #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_BITS 24 #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_SHIFT 8 /* PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER :: LANE_NUMBER [07:00] */ #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_MASK 0x000000ff #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_ALIGN 0 #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_BITS 8 #define PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER ***************************************************************************/ /* PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER :: RESERVED_0 [31:08] */ #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_MASK 0xffffff00 #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_ALIGN 0 #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_BITS 24 #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_SHIFT 8 /* PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER :: LANE_NUMBER [07:00] */ #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_MASK 0x000000ff #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_ALIGN 0 #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_BITS 8 #define PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_LINK_TRAINING_N_FTS ***************************************************************************/ /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: RESERVED_0 [31:25] */ #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_MASK 0xfe000000 #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_ALIGN 0 #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_BITS 7 #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_SHIFT 25 /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS_OVERRIDE [24:24] */ #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_MASK 0x01000000 #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_ALIGN 0 #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_BITS 1 #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_SHIFT 24 /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS_OVERRIDE_VALUE [23:16] */ #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_MASK 0x00ff0000 #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_ALIGN 0 #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_BITS 8 #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_SHIFT 16 /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS [15:08] */ #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_MASK 0x0000ff00 #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_ALIGN 0 #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_BITS 8 #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_SHIFT 8 /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: RECEIVER_N_FTS [07:00] */ #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_MASK 0x000000ff #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_ALIGN 0 #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_BITS 8 #define PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_ATTENTION ***************************************************************************/ /* PCIE_PHY :: PHY_ATTENTION :: RESERVED_0 [31:08] */ #define PCIE_PHY_PHY_ATTENTION_RESERVED_0_MASK 0xffffff00 #define PCIE_PHY_PHY_ATTENTION_RESERVED_0_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_RESERVED_0_BITS 24 #define PCIE_PHY_PHY_ATTENTION_RESERVED_0_SHIFT 8 /* PCIE_PHY :: PHY_ATTENTION :: HOT_RESET [07:07] */ #define PCIE_PHY_PHY_ATTENTION_HOT_RESET_MASK 0x00000080 #define PCIE_PHY_PHY_ATTENTION_HOT_RESET_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_HOT_RESET_BITS 1 #define PCIE_PHY_PHY_ATTENTION_HOT_RESET_SHIFT 7 /* PCIE_PHY :: PHY_ATTENTION :: LINK_DOWN [06:06] */ #define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_MASK 0x00000040 #define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_BITS 1 #define PCIE_PHY_PHY_ATTENTION_LINK_DOWN_SHIFT 6 /* PCIE_PHY :: PHY_ATTENTION :: TRAINING_ERROR [05:05] */ #define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_MASK 0x00000020 #define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_BITS 1 #define PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_SHIFT 5 /* PCIE_PHY :: PHY_ATTENTION :: BUFFER_OVERRUN [04:04] */ #define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_MASK 0x00000010 #define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_BITS 1 #define PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_SHIFT 4 /* PCIE_PHY :: PHY_ATTENTION :: BUFFER_UNDERRUN [03:03] */ #define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_MASK 0x00000008 #define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_BITS 1 #define PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_SHIFT 3 /* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_FRAMING_ERROR [02:02] */ #define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_MASK 0x00000004 #define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_BITS 1 #define PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_SHIFT 2 /* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_DISPARITY_ERROR [01:01] */ #define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_MASK 0x00000002 #define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_BITS 1 #define PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_SHIFT 1 /* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_CODE_ERROR [00:00] */ #define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_MASK 0x00000001 #define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_BITS 1 #define PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_ATTENTION_MASK ***************************************************************************/ /* PCIE_PHY :: PHY_ATTENTION_MASK :: RESERVED_0 [31:08] */ #define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_MASK 0xffffff00 #define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_BITS 24 #define PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_SHIFT 8 /* PCIE_PHY :: PHY_ATTENTION_MASK :: HOT_RESET_MASK [07:07] */ #define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_MASK 0x00000080 #define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_BITS 1 #define PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_SHIFT 7 /* PCIE_PHY :: PHY_ATTENTION_MASK :: LINK_DOWN_MASK [06:06] */ #define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_MASK 0x00000040 #define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_BITS 1 #define PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_SHIFT 6 /* PCIE_PHY :: PHY_ATTENTION_MASK :: TRAINING_ERROR_MASK [05:05] */ #define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_MASK 0x00000020 #define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_BITS 1 #define PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_SHIFT 5 /* PCIE_PHY :: PHY_ATTENTION_MASK :: BUFFER_OVERRUN_MASK [04:04] */ #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_MASK 0x00000010 #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_BITS 1 #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_SHIFT 4 /* PCIE_PHY :: PHY_ATTENTION_MASK :: BUFFER_UNDERRUN_MASK [03:03] */ #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_MASK 0x00000008 #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_BITS 1 #define PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_SHIFT 3 /* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_FRAME_ERROR_MASK [02:02] */ #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_MASK 0x00000004 #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_BITS 1 #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_SHIFT 2 /* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_DISPARITY_ERROR_MASK [01:01] */ #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_MASK 0x00000002 #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_BITS 1 #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_SHIFT 1 /* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_CODE_ERROR_MASK [00:00] */ #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_MASK 0x00000001 #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_ALIGN 0 #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_BITS 1 #define PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER ***************************************************************************/ /* PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER :: DISPARITY_ERROR_COUNT [31:16] */ #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_MASK 0xffff0000 #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_ALIGN 0 #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_BITS 16 #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_SHIFT 16 /* PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER :: CODE_ERROR_COUNT [15:00] */ #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_MASK 0x0000ffff #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_ALIGN 0 #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_BITS 16 #define PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER ***************************************************************************/ /* PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER :: RESERVED_0 [31:16] */ #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_MASK 0xffff0000 #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_ALIGN 0 #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_BITS 16 #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_SHIFT 16 /* PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER :: FRAMING_ERROR_COUNT [15:00] */ #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_MASK 0x0000ffff #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_ALIGN 0 #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_BITS 16 #define PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD ***************************************************************************/ /* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: RESERVED_0 [31:12] */ #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_MASK 0xfffff000 #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_ALIGN 0 #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_BITS 20 #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_SHIFT 12 /* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: FRAME_ERROR_THRESHOLD [11:08] */ #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_MASK 0x00000f00 #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_ALIGN 0 #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_BITS 4 #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_SHIFT 8 /* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: DISPARITY_ERROR_THRESHOLD [07:04] */ #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_MASK 0x000000f0 #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_ALIGN 0 #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_BITS 4 #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_SHIFT 4 /* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: CODE_ERROR_THRESHOLD [03:00] */ #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_MASK 0x0000000f #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_ALIGN 0 #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_BITS 4 #define PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_TEST_CONTROL ***************************************************************************/ /* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_0 [31:31] */ #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_MASK 0x80000000 #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_SHIFT 31 /* PCIE_PHY :: PHY_TEST_CONTROL :: DELAY_HOTRESET_ENABLE [30:30] */ #define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_MASK 0x40000000 #define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_SHIFT 30 /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_TSX_MAJORITY_CHECK [29:29] */ #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_MASK 0x20000000 #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_SHIFT 29 /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_MASK_OFF_BOGUS [28:28] */ #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_MASK 0x10000000 #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_SHIFT 28 /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_POLARITY_CHECK [27:27] */ #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_MASK 0x08000000 #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_SHIFT 27 /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_STICKY_POLARITY_CHECK [26:26] */ #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_MASK 0x04000000 #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_SHIFT 26 /* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_1 [25:23] */ #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_MASK 0x03800000 #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_BITS 3 #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_SHIFT 23 /* PCIE_PHY :: PHY_TEST_CONTROL :: TWO_OS_RULE_RELAXING [22:22] */ #define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_MASK 0x00400000 #define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_SHIFT 22 /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_HOT_RESET [21:21] */ #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_MASK 0x00200000 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_SHIFT 21 /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_LINK_DOWN_RESET [20:20] */ #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_MASK 0x00100000 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_SHIFT 20 /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE [19:19] */ #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_MASK 0x00080000 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_SHIFT 19 /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_EXIT [18:18] */ #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_MASK 0x00040000 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_SHIFT 18 /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_MASK [17:17] */ #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_MASK 0x00020000 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_SHIFT 17 /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_RECOVERY [16:16] */ #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_MASK 0x00010000 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_SHIFT 16 /* PCIE_PHY :: PHY_TEST_CONTROL :: RESERVED_0 [15:08] */ #define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_MASK 0x0000ff00 #define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_BITS 8 #define PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_SHIFT 8 /* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_2 [07:04] */ #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_MASK 0x000000f0 #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_BITS 4 #define PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_SHIFT 4 /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ22100_FIX_DISABLE [03:03] */ #define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_MASK 0x00000008 #define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_SHIFT 3 /* PCIE_PHY :: PHY_TEST_CONTROL :: TRAINING_BYPASS [02:02] */ #define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_MASK 0x00000004 #define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_SHIFT 2 /* PCIE_PHY :: PHY_TEST_CONTROL :: EXTERNAL_LOOPBACK [01:01] */ #define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_MASK 0x00000002 #define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_SHIFT 1 /* PCIE_PHY :: PHY_TEST_CONTROL :: INTERNAL_LOOPBACK [00:00] */ #define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_MASK 0x00000001 #define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_ALIGN 0 #define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_BITS 1 #define PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE ***************************************************************************/ /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RESERVED_0 [31:18] */ #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_MASK 0xfffc0000 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_ALIGN 0 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_BITS 14 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_SHIFT 18 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: OBSVELECIDLEVALUE [17:17] */ #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_MASK 0x00020000 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_ALIGN 0 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_BITS 1 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_SHIFT 17 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: OBSVELECIDLEOVERRIDE [16:16] */ #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_MASK 0x00010000 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_ALIGN 0 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_BITS 1 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_SHIFT 16 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: PLLISUPVALUE [15:15] */ #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_MASK 0x00008000 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_ALIGN 0 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_BITS 1 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_SHIFT 15 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: PLLISUPOVERRIDE [14:14] */ #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_MASK 0x00004000 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_ALIGN 0 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_BITS 1 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_SHIFT 14 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETVALUE [13:13] */ #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_MASK 0x00002000 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_ALIGN 0 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_BITS 1 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_SHIFT 13 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETOVERRIDE [12:12] */ #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_MASK 0x00001000 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_ALIGN 0 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_BITS 1 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_SHIFT 12 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETTIMECONTROL [11:10] */ #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_MASK 0x00000c00 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_ALIGN 0 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_BITS 2 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_SHIFT 10 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETECTIONTIME [09:00] */ #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_MASK 0x000003ff #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_ALIGN 0 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_BITS 10 #define PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE ***************************************************************************/ /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TS1NUMOVERRIDE [31:31] */ #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_MASK 0x80000000 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_ALIGN 0 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_BITS 1 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_SHIFT 31 /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLEMINOVERRIDE [30:30] */ #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_MASK 0x40000000 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_ALIGN 0 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_BITS 1 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_SHIFT 30 /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLE2IDLEOVERRIDE [29:29] */ #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_MASK 0x20000000 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_ALIGN 0 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_BITS 1 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_SHIFT 29 /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: UNUSED_0 [28:28] */ #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_MASK 0x10000000 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_ALIGN 0 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_BITS 1 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_SHIFT 28 /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: N_TS1INPOLLINGACTIVE [27:16] */ #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_MASK 0x0fff0000 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_ALIGN 0 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_BITS 12 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_SHIFT 16 /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLEMINTIME [15:08] */ #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_MASK 0x0000ff00 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_ALIGN 0 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_BITS 8 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_SHIFT 8 /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLESETTOIDLETIME [07:00] */ #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_MASK 0x000000ff #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_ALIGN 0 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_BITS 8 #define PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES ***************************************************************************/ /* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: RESERVED_0 [31:10] */ #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_MASK 0xfffffc00 #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_ALIGN 0 #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_BITS 22 #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_SHIFT 10 /* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: TRANSMIT_STATE_MACHINE_STATE [09:04] */ #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_MASK 0x000003f0 #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_ALIGN 0 #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_BITS 6 #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_SHIFT 4 /* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: RECEIVE_STATE_MACHINE_STATE [03:00] */ #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_MASK 0x0000000f #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_ALIGN 0 #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_BITS 4 #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_SHIFT 0 /**************************************************************************** * PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES ***************************************************************************/ /* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES :: LTSSM_STATE_MACHINE_STATE [31:00] */ #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_MASK 0xffffffff #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_ALIGN 0 #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_BITS 32 #define PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_SHIFT 0 /**************************************************************************** * BCM70012_TGT_TOP_INTR ***************************************************************************/ /**************************************************************************** * INTR :: INTR_STATUS ***************************************************************************/ /* INTR :: INTR_STATUS :: reserved0 [31:26] */ #define INTR_INTR_STATUS_reserved0_MASK 0xfc000000 #define INTR_INTR_STATUS_reserved0_ALIGN 0 #define INTR_INTR_STATUS_reserved0_BITS 6 #define INTR_INTR_STATUS_reserved0_SHIFT 26 /* INTR :: INTR_STATUS :: PCIE_TGT_CA_ATTN [25:25] */ #define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_ALIGN 0 #define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_BITS 1 #define INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: INTR_STATUS :: PCIE_TGT_UR_ATTN [24:24] */ #define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_ALIGN 0 #define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_BITS 1 #define INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: INTR_STATUS :: reserved1 [23:14] */ #define INTR_INTR_STATUS_reserved1_MASK 0x00ffc000 #define INTR_INTR_STATUS_reserved1_ALIGN 0 #define INTR_INTR_STATUS_reserved1_BITS 10 #define INTR_INTR_STATUS_reserved1_SHIFT 14 /* INTR :: INTR_STATUS :: L1_UV_RX_DMA_ERR_INTR [13:13] */ #define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK 0x00002000 #define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_ALIGN 0 #define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_BITS 1 #define INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_SHIFT 13 /* INTR :: INTR_STATUS :: L1_UV_RX_DMA_DONE_INTR [12:12] */ #define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK 0x00001000 #define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_ALIGN 0 #define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_BITS 1 #define INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_SHIFT 12 /* INTR :: INTR_STATUS :: L1_Y_RX_DMA_ERR_INTR [11:11] */ #define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK 0x00000800 #define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_ALIGN 0 #define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_BITS 1 #define INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_SHIFT 11 /* INTR :: INTR_STATUS :: L1_Y_RX_DMA_DONE_INTR [10:10] */ #define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK 0x00000400 #define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_ALIGN 0 #define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_BITS 1 #define INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_SHIFT 10 /* INTR :: INTR_STATUS :: L1_TX_DMA_ERR_INTR [09:09] */ #define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000200 #define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_ALIGN 0 #define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_BITS 1 #define INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 9 /* INTR :: INTR_STATUS :: L1_TX_DMA_DONE_INTR [08:08] */ #define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000100 #define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_ALIGN 0 #define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_BITS 1 #define INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 8 /* INTR :: INTR_STATUS :: reserved2 [07:06] */ #define INTR_INTR_STATUS_reserved2_MASK 0x000000c0 #define INTR_INTR_STATUS_reserved2_ALIGN 0 #define INTR_INTR_STATUS_reserved2_BITS 2 #define INTR_INTR_STATUS_reserved2_SHIFT 6 /* INTR :: INTR_STATUS :: L0_UV_RX_DMA_ERR_INTR [05:05] */ #define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK 0x00000020 #define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_ALIGN 0 #define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_BITS 1 #define INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_SHIFT 5 /* INTR :: INTR_STATUS :: L0_UV_RX_DMA_DONE_INTR [04:04] */ #define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK 0x00000010 #define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_ALIGN 0 #define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_BITS 1 #define INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_SHIFT 4 /* INTR :: INTR_STATUS :: L0_Y_RX_DMA_ERR_INTR [03:03] */ #define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK 0x00000008 #define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_ALIGN 0 #define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_BITS 1 #define INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_SHIFT 3 /* INTR :: INTR_STATUS :: L0_Y_RX_DMA_DONE_INTR [02:02] */ #define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK 0x00000004 #define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_ALIGN 0 #define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_BITS 1 #define INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_SHIFT 2 /* INTR :: INTR_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */ #define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002 #define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_ALIGN 0 #define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_BITS 1 #define INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1 /* INTR :: INTR_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */ #define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001 #define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_ALIGN 0 #define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_BITS 1 #define INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0 /**************************************************************************** * INTR :: INTR_SET ***************************************************************************/ /* INTR :: INTR_SET :: reserved0 [31:26] */ #define INTR_INTR_SET_reserved0_MASK 0xfc000000 #define INTR_INTR_SET_reserved0_ALIGN 0 #define INTR_INTR_SET_reserved0_BITS 6 #define INTR_INTR_SET_reserved0_SHIFT 26 /* INTR :: INTR_SET :: PCIE_TGT_CA_ATTN [25:25] */ #define INTR_INTR_SET_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define INTR_INTR_SET_PCIE_TGT_CA_ATTN_ALIGN 0 #define INTR_INTR_SET_PCIE_TGT_CA_ATTN_BITS 1 #define INTR_INTR_SET_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: INTR_SET :: PCIE_TGT_UR_ATTN [24:24] */ #define INTR_INTR_SET_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define INTR_INTR_SET_PCIE_TGT_UR_ATTN_ALIGN 0 #define INTR_INTR_SET_PCIE_TGT_UR_ATTN_BITS 1 #define INTR_INTR_SET_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: INTR_SET :: reserved1 [23:14] */ #define INTR_INTR_SET_reserved1_MASK 0x00ffc000 #define INTR_INTR_SET_reserved1_ALIGN 0 #define INTR_INTR_SET_reserved1_BITS 10 #define INTR_INTR_SET_reserved1_SHIFT 14 /* INTR :: INTR_SET :: UV_RX_DMA_L1_ERR_INTR [13:13] */ #define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_MASK 0x00002000 #define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_ALIGN 0 #define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_BITS 1 #define INTR_INTR_SET_UV_RX_DMA_L1_ERR_INTR_SHIFT 13 /* INTR :: INTR_SET :: UV_RX_DMA_L1_DONE_INTR [12:12] */ #define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_MASK 0x00001000 #define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_ALIGN 0 #define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_BITS 1 #define INTR_INTR_SET_UV_RX_DMA_L1_DONE_INTR_SHIFT 12 /* INTR :: INTR_SET :: Y_RX_DMA_L1_ERR_INTR [11:11] */ #define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_MASK 0x00000800 #define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_ALIGN 0 #define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_BITS 1 #define INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_SHIFT 11 /* INTR :: INTR_SET :: Y_RX_DMA_L1_DONE_INTR [10:10] */ #define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_MASK 0x00000400 #define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_ALIGN 0 #define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_BITS 1 #define INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_SHIFT 10 /* INTR :: INTR_SET :: TX_DMA_L1_ERR_INTR [09:09] */ #define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_MASK 0x00000200 #define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_ALIGN 0 #define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_BITS 1 #define INTR_INTR_SET_TX_DMA_L1_ERR_INTR_SHIFT 9 /* INTR :: INTR_SET :: TX_DMA_L1_DONE_INTR [08:08] */ #define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_MASK 0x00000100 #define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_ALIGN 0 #define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_BITS 1 #define INTR_INTR_SET_TX_DMA_L1_DONE_INTR_SHIFT 8 /* INTR :: INTR_SET :: reserved2 [07:06] */ #define INTR_INTR_SET_reserved2_MASK 0x000000c0 #define INTR_INTR_SET_reserved2_ALIGN 0 #define INTR_INTR_SET_reserved2_BITS 2 #define INTR_INTR_SET_reserved2_SHIFT 6 /* INTR :: INTR_SET :: UV_RX_DMA_L0_ERR_INTR [05:05] */ #define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_MASK 0x00000020 #define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_ALIGN 0 #define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_BITS 1 #define INTR_INTR_SET_UV_RX_DMA_L0_ERR_INTR_SHIFT 5 /* INTR :: INTR_SET :: UV_RX_DMA_L0_DONE_INTR [04:04] */ #define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_MASK 0x00000010 #define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_ALIGN 0 #define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_BITS 1 #define INTR_INTR_SET_UV_RX_DMA_L0_DONE_INTR_SHIFT 4 /* INTR :: INTR_SET :: Y_RX_DMA_L0_ERR_INTR [03:03] */ #define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_MASK 0x00000008 #define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_ALIGN 0 #define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_BITS 1 #define INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_SHIFT 3 /* INTR :: INTR_SET :: Y_RX_DMA_L0_DONE_INTR [02:02] */ #define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_MASK 0x00000004 #define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_ALIGN 0 #define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_BITS 1 #define INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_SHIFT 2 /* INTR :: INTR_SET :: TX_DMA_L0_ERR_INTR [01:01] */ #define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_MASK 0x00000002 #define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_ALIGN 0 #define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_BITS 1 #define INTR_INTR_SET_TX_DMA_L0_ERR_INTR_SHIFT 1 /* INTR :: INTR_SET :: TX_DMA_L0_DONE_INTR [00:00] */ #define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_MASK 0x00000001 #define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_ALIGN 0 #define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_BITS 1 #define INTR_INTR_SET_TX_DMA_L0_DONE_INTR_SHIFT 0 /**************************************************************************** * INTR :: INTR_CLR_REG ***************************************************************************/ /* INTR :: INTR_CLR_REG :: reserved0 [31:26] */ #define INTR_INTR_CLR_REG_reserved0_MASK 0xfc000000 #define INTR_INTR_CLR_REG_reserved0_ALIGN 0 #define INTR_INTR_CLR_REG_reserved0_BITS 6 #define INTR_INTR_CLR_REG_reserved0_SHIFT 26 /* INTR :: INTR_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ #define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_ALIGN 0 #define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_BITS 1 #define INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: INTR_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ #define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_ALIGN 0 #define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_BITS 1 #define INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: INTR_CLR_REG :: reserved1 [23:14] */ #define INTR_INTR_CLR_REG_reserved1_MASK 0x00ffc000 #define INTR_INTR_CLR_REG_reserved1_ALIGN 0 #define INTR_INTR_CLR_REG_reserved1_BITS 10 #define INTR_INTR_CLR_REG_reserved1_SHIFT 14 /* INTR :: INTR_CLR_REG :: L1_UV_RX_DMA_ERR_INTR_CLR [13:13] */ #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_MASK 0x00002000 #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_ALIGN 0 #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_BITS 1 #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_ERR_INTR_CLR_SHIFT 13 /* INTR :: INTR_CLR_REG :: L1_UV_RX_DMA_DONE_INTR_CLR [12:12] */ #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_MASK 0x00001000 #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_ALIGN 0 #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_BITS 1 #define INTR_INTR_CLR_REG_L1_UV_RX_DMA_DONE_INTR_CLR_SHIFT 12 /* INTR :: INTR_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_CLR [11:11] */ #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000800 #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_ALIGN 0 #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_BITS 1 #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_SHIFT 11 /* INTR :: INTR_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_CLR [10:10] */ #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000400 #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_ALIGN 0 #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_BITS 1 #define INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_SHIFT 10 /* INTR :: INTR_CLR_REG :: L1_TX_DMA_ERR_INTR_CLR [09:09] */ #define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_MASK 0x00000200 #define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_ALIGN 0 #define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_BITS 1 #define INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_SHIFT 9 /* INTR :: INTR_CLR_REG :: L1_TX_DMA_DONE_INTR_CLR [08:08] */ #define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_MASK 0x00000100 #define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_ALIGN 0 #define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_BITS 1 #define INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_SHIFT 8 /* INTR :: INTR_CLR_REG :: reserved2 [07:06] */ #define INTR_INTR_CLR_REG_reserved2_MASK 0x000000c0 #define INTR_INTR_CLR_REG_reserved2_ALIGN 0 #define INTR_INTR_CLR_REG_reserved2_BITS 2 #define INTR_INTR_CLR_REG_reserved2_SHIFT 6 /* INTR :: INTR_CLR_REG :: L0_UV_RX_DMA_ERR_INTR_CLR [05:05] */ #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_MASK 0x00000020 #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_ALIGN 0 #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_BITS 1 #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_ERR_INTR_CLR_SHIFT 5 /* INTR :: INTR_CLR_REG :: L0_UV_RX_DMA_DONE_INTR_CLR [04:04] */ #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_MASK 0x00000010 #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_ALIGN 0 #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_BITS 1 #define INTR_INTR_CLR_REG_L0_UV_RX_DMA_DONE_INTR_CLR_SHIFT 4 /* INTR :: INTR_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_CLR [03:03] */ #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000008 #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_ALIGN 0 #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_BITS 1 #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_SHIFT 3 /* INTR :: INTR_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_CLR [02:02] */ #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000004 #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_ALIGN 0 #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_BITS 1 #define INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_SHIFT 2 /* INTR :: INTR_CLR_REG :: L0_TX_DMA_ERR_INTR_CLR [01:01] */ #define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_MASK 0x00000002 #define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_ALIGN 0 #define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_BITS 1 #define INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_SHIFT 1 /* INTR :: INTR_CLR_REG :: L0_TX_DMA_DONE_INTR_CLR [00:00] */ #define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_MASK 0x00000001 #define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_ALIGN 0 #define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_BITS 1 #define INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_SHIFT 0 /**************************************************************************** * INTR :: INTR_MSK_STS_REG ***************************************************************************/ /* INTR :: INTR_MSK_STS_REG :: reserved0 [31:26] */ #define INTR_INTR_MSK_STS_REG_reserved0_MASK 0xfc000000 #define INTR_INTR_MSK_STS_REG_reserved0_ALIGN 0 #define INTR_INTR_MSK_STS_REG_reserved0_BITS 6 #define INTR_INTR_MSK_STS_REG_reserved0_SHIFT 26 /* INTR :: INTR_MSK_STS_REG :: PCIE_TGT_CA_ATTN [25:25] */ #define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_ALIGN 0 #define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_BITS 1 #define INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: INTR_MSK_STS_REG :: PCIE_TGT_UR_ATTN [24:24] */ #define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_ALIGN 0 #define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_BITS 1 #define INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: INTR_MSK_STS_REG :: reserved1 [23:14] */ #define INTR_INTR_MSK_STS_REG_reserved1_MASK 0x00ffc000 #define INTR_INTR_MSK_STS_REG_reserved1_ALIGN 0 #define INTR_INTR_MSK_STS_REG_reserved1_BITS 10 #define INTR_INTR_MSK_STS_REG_reserved1_SHIFT 14 /* INTR :: INTR_MSK_STS_REG :: L1_UV_RX_DMA_ERR_INTR_MSK [13:13] */ #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_MASK 0x00002000 #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_ALIGN 0 #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_BITS 1 #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SHIFT 13 /* INTR :: INTR_MSK_STS_REG :: L1_UV_RX_DMA_DONE_INTR_MSK [12:12] */ #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_MASK 0x00001000 #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_ALIGN 0 #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_BITS 1 #define INTR_INTR_MSK_STS_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SHIFT 12 /* INTR :: INTR_MSK_STS_REG :: LIST1_Y_RX_DMA_ERR_INTR_MSK [11:11] */ #define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000800 #define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_ALIGN 0 #define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_BITS 1 #define INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_SHIFT 11 /* INTR :: INTR_MSK_STS_REG :: L1_Y_RX_DMA_DONE_INTR_MSK [10:10] */ #define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000400 #define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_ALIGN 0 #define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_BITS 1 #define INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SHIFT 10 /* INTR :: INTR_MSK_STS_REG :: L1_TX_DMA_ERR_INTR_MSK [09:09] */ #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_MASK 0x00000200 #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_ALIGN 0 #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_BITS 1 #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_SHIFT 9 /* INTR :: INTR_MSK_STS_REG :: L1_TX_DMA_DONE_INTR_MSK [08:08] */ #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_MASK 0x00000100 #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_ALIGN 0 #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_BITS 1 #define INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_SHIFT 8 /* INTR :: INTR_MSK_STS_REG :: reserved2 [07:06] */ #define INTR_INTR_MSK_STS_REG_reserved2_MASK 0x000000c0 #define INTR_INTR_MSK_STS_REG_reserved2_ALIGN 0 #define INTR_INTR_MSK_STS_REG_reserved2_BITS 2 #define INTR_INTR_MSK_STS_REG_reserved2_SHIFT 6 /* INTR :: INTR_MSK_STS_REG :: L0_UV_RX_DMA_ERR_INTR_MSK [05:05] */ #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_MASK 0x00000020 #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_ALIGN 0 #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_BITS 1 #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SHIFT 5 /* INTR :: INTR_MSK_STS_REG :: L0_UV_RX_DMA_DONE_INTR_MSK [04:04] */ #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_MASK 0x00000010 #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_ALIGN 0 #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_BITS 1 #define INTR_INTR_MSK_STS_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SHIFT 4 /* INTR :: INTR_MSK_STS_REG :: LIST0_Y_RX_DMA_ERR_INTR_MSK [03:03] */ #define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000008 #define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_ALIGN 0 #define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_BITS 1 #define INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_SHIFT 3 /* INTR :: INTR_MSK_STS_REG :: L0_Y_RX_DMA_DONE_INTR_MSK [02:02] */ #define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000004 #define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_ALIGN 0 #define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_BITS 1 #define INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SHIFT 2 /* INTR :: INTR_MSK_STS_REG :: L0_TX_DMA_ERR_INTR_MSK [01:01] */ #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_MASK 0x00000002 #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_ALIGN 0 #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_BITS 1 #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_SHIFT 1 /* INTR :: INTR_MSK_STS_REG :: L0_TX_DMA_DONE_INTR_MSK [00:00] */ #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_MASK 0x00000001 #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_ALIGN 0 #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_BITS 1 #define INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_SHIFT 0 /**************************************************************************** * INTR :: INTR_MSK_SET_REG ***************************************************************************/ /* INTR :: INTR_MSK_SET_REG :: reserved0 [31:26] */ #define INTR_INTR_MSK_SET_REG_reserved0_MASK 0xfc000000 #define INTR_INTR_MSK_SET_REG_reserved0_ALIGN 0 #define INTR_INTR_MSK_SET_REG_reserved0_BITS 6 #define INTR_INTR_MSK_SET_REG_reserved0_SHIFT 26 /* INTR :: INTR_MSK_SET_REG :: PCIE_TGT_CA_ATTN [25:25] */ #define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_ALIGN 0 #define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_BITS 1 #define INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: INTR_MSK_SET_REG :: PCIE_TGT_UR_ATTN [24:24] */ #define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_ALIGN 0 #define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_BITS 1 #define INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: INTR_MSK_SET_REG :: reserved1 [23:14] */ #define INTR_INTR_MSK_SET_REG_reserved1_MASK 0x00ffc000 #define INTR_INTR_MSK_SET_REG_reserved1_ALIGN 0 #define INTR_INTR_MSK_SET_REG_reserved1_BITS 10 #define INTR_INTR_MSK_SET_REG_reserved1_SHIFT 14 /* INTR :: INTR_MSK_SET_REG :: L1_UV_RX_DMA_ERR_INTR_MSK_SET [13:13] */ #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00002000 #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_BITS 1 #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_ERR_INTR_MSK_SET_SHIFT 13 /* INTR :: INTR_MSK_SET_REG :: L1_UV_RX_DMA_DONE_INTR_MSK_SET [12:12] */ #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00001000 #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_BITS 1 #define INTR_INTR_MSK_SET_REG_L1_UV_RX_DMA_DONE_INTR_MSK_SET_SHIFT 12 /* INTR :: INTR_MSK_SET_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_SET [11:11] */ #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000800 #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_BITS 1 #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 11 /* INTR :: INTR_MSK_SET_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_SET [10:10] */ #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000400 #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_BITS 1 #define INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 10 /* INTR :: INTR_MSK_SET_REG :: L1_TX_DMA_ERR_INTR_MSK_SET [09:09] */ #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000200 #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_ALIGN 0 #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_BITS 1 #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_SHIFT 9 /* INTR :: INTR_MSK_SET_REG :: L1_TX_DMA_DONE_INTR_MSK_SET [08:08] */ #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000100 #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_ALIGN 0 #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_BITS 1 #define INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_SHIFT 8 /* INTR :: INTR_MSK_SET_REG :: reserved2 [07:06] */ #define INTR_INTR_MSK_SET_REG_reserved2_MASK 0x000000c0 #define INTR_INTR_MSK_SET_REG_reserved2_ALIGN 0 #define INTR_INTR_MSK_SET_REG_reserved2_BITS 2 #define INTR_INTR_MSK_SET_REG_reserved2_SHIFT 6 /* INTR :: INTR_MSK_SET_REG :: L0_UV_RX_DMA_ERR_INTR_MSK_SET [05:05] */ #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000020 #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_BITS 1 #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_ERR_INTR_MSK_SET_SHIFT 5 /* INTR :: INTR_MSK_SET_REG :: L0_UV_RX_DMA_DONE_INTR_MSK_SET [04:04] */ #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000010 #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_BITS 1 #define INTR_INTR_MSK_SET_REG_L0_UV_RX_DMA_DONE_INTR_MSK_SET_SHIFT 4 /* INTR :: INTR_MSK_SET_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_SET [03:03] */ #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000008 #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_ALIGN 0 #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_BITS 1 #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 3 /* INTR :: INTR_MSK_SET_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_SET [02:02] */ #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000004 #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_ALIGN 0 #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_BITS 1 #define INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 2 /* INTR :: INTR_MSK_SET_REG :: L0_TX_DMA_ERR_INTR_MSK_SET [01:01] */ #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000002 #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_ALIGN 0 #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_BITS 1 #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_SHIFT 1 /* INTR :: INTR_MSK_SET_REG :: L0_TX_DMA_DONE_INTR_MSK_SET [00:00] */ #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000001 #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_ALIGN 0 #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_BITS 1 #define INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_SHIFT 0 /**************************************************************************** * INTR :: INTR_MSK_CLR_REG ***************************************************************************/ /* INTR :: INTR_MSK_CLR_REG :: reserved0 [31:26] */ #define INTR_INTR_MSK_CLR_REG_reserved0_MASK 0xfc000000 #define INTR_INTR_MSK_CLR_REG_reserved0_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_reserved0_BITS 6 #define INTR_INTR_MSK_CLR_REG_reserved0_SHIFT 26 /* INTR :: INTR_MSK_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_BITS 1 #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: INTR_MSK_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_BITS 1 #define INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: INTR_MSK_CLR_REG :: reserved1 [23:14] */ #define INTR_INTR_MSK_CLR_REG_reserved1_MASK 0x00ffc000 #define INTR_INTR_MSK_CLR_REG_reserved1_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_reserved1_BITS 10 #define INTR_INTR_MSK_CLR_REG_reserved1_SHIFT 14 /* INTR :: INTR_MSK_CLR_REG :: L1_UV_RX_DMA_ERR_INTR_MSK_CLR [13:13] */ #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00002000 #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 13 /* INTR :: INTR_MSK_CLR_REG :: L1_UV_RX_DMA_DONE_INTR_MSK_CLR [12:12] */ #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00001000 #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 #define INTR_INTR_MSK_CLR_REG_L1_UV_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 12 /* INTR :: INTR_MSK_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_CLR [11:11] */ #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000800 #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 11 /* INTR :: INTR_MSK_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_CLR [10:10] */ #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000400 #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 #define INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 10 /* INTR :: INTR_MSK_CLR_REG :: L1_TX_DMA_ERR_INTR_MSK_CLR [09:09] */ #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000200 #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_BITS 1 #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 9 /* INTR :: INTR_MSK_CLR_REG :: L1_TX_DMA_DONE_INTR_MSK_CLR [08:08] */ #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000100 #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_BITS 1 #define INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 8 /* INTR :: INTR_MSK_CLR_REG :: reserved2 [07:06] */ #define INTR_INTR_MSK_CLR_REG_reserved2_MASK 0x000000c0 #define INTR_INTR_MSK_CLR_REG_reserved2_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_reserved2_BITS 2 #define INTR_INTR_MSK_CLR_REG_reserved2_SHIFT 6 /* INTR :: INTR_MSK_CLR_REG :: L0_UV_RX_DMA_ERR_INTR_MSK_CLR [05:05] */ #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000020 #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 5 /* INTR :: INTR_MSK_CLR_REG :: L0_UV_RX_DMA_DONE_INTR_MSK_CLR [04:04] */ #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000010 #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 #define INTR_INTR_MSK_CLR_REG_L0_UV_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 4 /* INTR :: INTR_MSK_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_CLR [03:03] */ #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000008 #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_BITS 1 #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 3 /* INTR :: INTR_MSK_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_CLR [02:02] */ #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000004 #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_BITS 1 #define INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 2 /* INTR :: INTR_MSK_CLR_REG :: L0_TX_DMA_ERR_INTR_MSK_CLR [01:01] */ #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000002 #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_BITS 1 #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 1 /* INTR :: INTR_MSK_CLR_REG :: L0_TX_DMA_DONE_INTR_MSK_CLR [00:00] */ #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000001 #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_ALIGN 0 #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_BITS 1 #define INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 0 /**************************************************************************** * INTR :: EOI_CTRL ***************************************************************************/ /* INTR :: EOI_CTRL :: reserved0 [31:01] */ #define INTR_EOI_CTRL_reserved0_MASK 0xfffffffe #define INTR_EOI_CTRL_reserved0_ALIGN 0 #define INTR_EOI_CTRL_reserved0_BITS 31 #define INTR_EOI_CTRL_reserved0_SHIFT 1 /* INTR :: EOI_CTRL :: EOI [00:00] */ #define INTR_EOI_CTRL_EOI_MASK 0x00000001 #define INTR_EOI_CTRL_EOI_ALIGN 0 #define INTR_EOI_CTRL_EOI_BITS 1 #define INTR_EOI_CTRL_EOI_SHIFT 0 /**************************************************************************** * BCM70012_TGT_TOP_MDIO ***************************************************************************/ /**************************************************************************** * MDIO :: CTRL0 ***************************************************************************/ /* MDIO :: CTRL0 :: reserved0 [31:22] */ #define MDIO_CTRL0_reserved0_MASK 0xffc00000 #define MDIO_CTRL0_reserved0_ALIGN 0 #define MDIO_CTRL0_reserved0_BITS 10 #define MDIO_CTRL0_reserved0_SHIFT 22 /* MDIO :: CTRL0 :: WRITE_READ_COMMAND [21:21] */ #define MDIO_CTRL0_WRITE_READ_COMMAND_MASK 0x00200000 #define MDIO_CTRL0_WRITE_READ_COMMAND_ALIGN 0 #define MDIO_CTRL0_WRITE_READ_COMMAND_BITS 1 #define MDIO_CTRL0_WRITE_READ_COMMAND_SHIFT 21 /* MDIO :: CTRL0 :: PHYAD [20:16] */ #define MDIO_CTRL0_PHYAD_MASK 0x001f0000 #define MDIO_CTRL0_PHYAD_ALIGN 0 #define MDIO_CTRL0_PHYAD_BITS 5 #define MDIO_CTRL0_PHYAD_SHIFT 16 /* MDIO :: CTRL0 :: reserved1 [15:05] */ #define MDIO_CTRL0_reserved1_MASK 0x0000ffe0 #define MDIO_CTRL0_reserved1_ALIGN 0 #define MDIO_CTRL0_reserved1_BITS 11 #define MDIO_CTRL0_reserved1_SHIFT 5 /* MDIO :: CTRL0 :: REGAD [04:00] */ #define MDIO_CTRL0_REGAD_MASK 0x0000001f #define MDIO_CTRL0_REGAD_ALIGN 0 #define MDIO_CTRL0_REGAD_BITS 5 #define MDIO_CTRL0_REGAD_SHIFT 0 /**************************************************************************** * MDIO :: CTRL1 ***************************************************************************/ /* MDIO :: CTRL1 :: WR_STATUS [31:31] */ #define MDIO_CTRL1_WR_STATUS_MASK 0x80000000 #define MDIO_CTRL1_WR_STATUS_ALIGN 0 #define MDIO_CTRL1_WR_STATUS_BITS 1 #define MDIO_CTRL1_WR_STATUS_SHIFT 31 /* MDIO :: CTRL1 :: reserved0 [30:16] */ #define MDIO_CTRL1_reserved0_MASK 0x7fff0000 #define MDIO_CTRL1_reserved0_ALIGN 0 #define MDIO_CTRL1_reserved0_BITS 15 #define MDIO_CTRL1_reserved0_SHIFT 16 /* MDIO :: CTRL1 :: Write_Data [15:00] */ #define MDIO_CTRL1_Write_Data_MASK 0x0000ffff #define MDIO_CTRL1_Write_Data_ALIGN 0 #define MDIO_CTRL1_Write_Data_BITS 16 #define MDIO_CTRL1_Write_Data_SHIFT 0 /**************************************************************************** * MDIO :: CTRL2 ***************************************************************************/ /* MDIO :: CTRL2 :: RD_STATUS [31:31] */ #define MDIO_CTRL2_RD_STATUS_MASK 0x80000000 #define MDIO_CTRL2_RD_STATUS_ALIGN 0 #define MDIO_CTRL2_RD_STATUS_BITS 1 #define MDIO_CTRL2_RD_STATUS_SHIFT 31 /* MDIO :: CTRL2 :: reserved0 [30:16] */ #define MDIO_CTRL2_reserved0_MASK 0x7fff0000 #define MDIO_CTRL2_reserved0_ALIGN 0 #define MDIO_CTRL2_reserved0_BITS 15 #define MDIO_CTRL2_reserved0_SHIFT 16 /* MDIO :: CTRL2 :: Read_Data [15:00] */ #define MDIO_CTRL2_Read_Data_MASK 0x0000ffff #define MDIO_CTRL2_Read_Data_ALIGN 0 #define MDIO_CTRL2_Read_Data_BITS 16 #define MDIO_CTRL2_Read_Data_SHIFT 0 /**************************************************************************** * BCM70012_TGT_TOP_TGT_RGR_BRIDGE ***************************************************************************/ /**************************************************************************** * TGT_RGR_BRIDGE :: REVISION ***************************************************************************/ /* TGT_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define TGT_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define TGT_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 #define TGT_RGR_BRIDGE_REVISION_reserved0_BITS 16 #define TGT_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 /* TGT_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define TGT_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define TGT_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 #define TGT_RGR_BRIDGE_REVISION_MAJOR_BITS 8 #define TGT_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* TGT_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ #define TGT_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define TGT_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 #define TGT_RGR_BRIDGE_REVISION_MINOR_BITS 8 #define TGT_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 /**************************************************************************** * TGT_RGR_BRIDGE :: CTRL ***************************************************************************/ /* TGT_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ #define TGT_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc #define TGT_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 #define TGT_RGR_BRIDGE_CTRL_reserved0_BITS 30 #define TGT_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 /* TGT_RGR_BRIDGE :: CTRL :: RBUS_ERROR_INTR [01:01] */ #define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_MASK 0x00000002 #define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_ALIGN 0 #define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_BITS 1 #define TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_SHIFT 1 /* TGT_RGR_BRIDGE :: CTRL :: GISB_ERROR_INTR [00:00] */ #define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_MASK 0x00000001 #define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_ALIGN 0 #define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_BITS 1 #define TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_SHIFT 0 /**************************************************************************** * TGT_RGR_BRIDGE :: RBUS_TIMER ***************************************************************************/ /* TGT_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ #define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 #define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 #define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 #define TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 /* TGT_RGR_BRIDGE :: RBUS_TIMER :: RBUS_TO_RBUS_TRANS_TIMER_CNT [15:00] */ #define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_MASK 0x0000ffff #define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_ALIGN 0 #define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_BITS 16 #define TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_SHIFT 0 /**************************************************************************** * TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 ***************************************************************************/ /* TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 /* TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 #define TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 /**************************************************************************** * TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 ***************************************************************************/ /* TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 /* TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 #define TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 /**************************************************************************** * BCM70012_I2C_TOP_I2C ***************************************************************************/ /**************************************************************************** * I2C :: CHIP_ADDRESS ***************************************************************************/ /* I2C :: CHIP_ADDRESS :: reserved0 [31:08] */ #define I2C_CHIP_ADDRESS_reserved0_MASK 0xffffff00 #define I2C_CHIP_ADDRESS_reserved0_ALIGN 0 #define I2C_CHIP_ADDRESS_reserved0_BITS 24 #define I2C_CHIP_ADDRESS_reserved0_SHIFT 8 /* I2C :: CHIP_ADDRESS :: CHIP_ADDRESS [07:01] */ #define I2C_CHIP_ADDRESS_CHIP_ADDRESS_MASK 0x000000fe #define I2C_CHIP_ADDRESS_CHIP_ADDRESS_ALIGN 0 #define I2C_CHIP_ADDRESS_CHIP_ADDRESS_BITS 7 #define I2C_CHIP_ADDRESS_CHIP_ADDRESS_SHIFT 1 /* I2C :: CHIP_ADDRESS :: RESERVED [00:00] */ #define I2C_CHIP_ADDRESS_RESERVED_MASK 0x00000001 #define I2C_CHIP_ADDRESS_RESERVED_ALIGN 0 #define I2C_CHIP_ADDRESS_RESERVED_BITS 1 #define I2C_CHIP_ADDRESS_RESERVED_SHIFT 0 /**************************************************************************** * I2C :: DATA_IN0 ***************************************************************************/ /* I2C :: DATA_IN0 :: reserved0 [31:08] */ #define I2C_DATA_IN0_reserved0_MASK 0xffffff00 #define I2C_DATA_IN0_reserved0_ALIGN 0 #define I2C_DATA_IN0_reserved0_BITS 24 #define I2C_DATA_IN0_reserved0_SHIFT 8 /* I2C :: DATA_IN0 :: DATA_IN0 [07:00] */ #define I2C_DATA_IN0_DATA_IN0_MASK 0x000000ff #define I2C_DATA_IN0_DATA_IN0_ALIGN 0 #define I2C_DATA_IN0_DATA_IN0_BITS 8 #define I2C_DATA_IN0_DATA_IN0_SHIFT 0 /**************************************************************************** * I2C :: DATA_IN1 ***************************************************************************/ /* I2C :: DATA_IN1 :: reserved0 [31:08] */ #define I2C_DATA_IN1_reserved0_MASK 0xffffff00 #define I2C_DATA_IN1_reserved0_ALIGN 0 #define I2C_DATA_IN1_reserved0_BITS 24 #define I2C_DATA_IN1_reserved0_SHIFT 8 /* I2C :: DATA_IN1 :: DATA_IN1 [07:00] */ #define I2C_DATA_IN1_DATA_IN1_MASK 0x000000ff #define I2C_DATA_IN1_DATA_IN1_ALIGN 0 #define I2C_DATA_IN1_DATA_IN1_BITS 8 #define I2C_DATA_IN1_DATA_IN1_SHIFT 0 /**************************************************************************** * I2C :: DATA_IN2 ***************************************************************************/ /* I2C :: DATA_IN2 :: reserved0 [31:08] */ #define I2C_DATA_IN2_reserved0_MASK 0xffffff00 #define I2C_DATA_IN2_reserved0_ALIGN 0 #define I2C_DATA_IN2_reserved0_BITS 24 #define I2C_DATA_IN2_reserved0_SHIFT 8 /* I2C :: DATA_IN2 :: DATA_IN2 [07:00] */ #define I2C_DATA_IN2_DATA_IN2_MASK 0x000000ff #define I2C_DATA_IN2_DATA_IN2_ALIGN 0 #define I2C_DATA_IN2_DATA_IN2_BITS 8 #define I2C_DATA_IN2_DATA_IN2_SHIFT 0 /**************************************************************************** * I2C :: DATA_IN3 ***************************************************************************/ /* I2C :: DATA_IN3 :: reserved0 [31:08] */ #define I2C_DATA_IN3_reserved0_MASK 0xffffff00 #define I2C_DATA_IN3_reserved0_ALIGN 0 #define I2C_DATA_IN3_reserved0_BITS 24 #define I2C_DATA_IN3_reserved0_SHIFT 8 /* I2C :: DATA_IN3 :: DATA_IN3 [07:00] */ #define I2C_DATA_IN3_DATA_IN3_MASK 0x000000ff #define I2C_DATA_IN3_DATA_IN3_ALIGN 0 #define I2C_DATA_IN3_DATA_IN3_BITS 8 #define I2C_DATA_IN3_DATA_IN3_SHIFT 0 /**************************************************************************** * I2C :: DATA_IN4 ***************************************************************************/ /* I2C :: DATA_IN4 :: reserved0 [31:08] */ #define I2C_DATA_IN4_reserved0_MASK 0xffffff00 #define I2C_DATA_IN4_reserved0_ALIGN 0 #define I2C_DATA_IN4_reserved0_BITS 24 #define I2C_DATA_IN4_reserved0_SHIFT 8 /* I2C :: DATA_IN4 :: DATA_IN4 [07:00] */ #define I2C_DATA_IN4_DATA_IN4_MASK 0x000000ff #define I2C_DATA_IN4_DATA_IN4_ALIGN 0 #define I2C_DATA_IN4_DATA_IN4_BITS 8 #define I2C_DATA_IN4_DATA_IN4_SHIFT 0 /**************************************************************************** * I2C :: DATA_IN5 ***************************************************************************/ /* I2C :: DATA_IN5 :: reserved0 [31:08] */ #define I2C_DATA_IN5_reserved0_MASK 0xffffff00 #define I2C_DATA_IN5_reserved0_ALIGN 0 #define I2C_DATA_IN5_reserved0_BITS 24 #define I2C_DATA_IN5_reserved0_SHIFT 8 /* I2C :: DATA_IN5 :: DATA_IN5 [07:00] */ #define I2C_DATA_IN5_DATA_IN5_MASK 0x000000ff #define I2C_DATA_IN5_DATA_IN5_ALIGN 0 #define I2C_DATA_IN5_DATA_IN5_BITS 8 #define I2C_DATA_IN5_DATA_IN5_SHIFT 0 /**************************************************************************** * I2C :: DATA_IN6 ***************************************************************************/ /* I2C :: DATA_IN6 :: reserved0 [31:08] */ #define I2C_DATA_IN6_reserved0_MASK 0xffffff00 #define I2C_DATA_IN6_reserved0_ALIGN 0 #define I2C_DATA_IN6_reserved0_BITS 24 #define I2C_DATA_IN6_reserved0_SHIFT 8 /* I2C :: DATA_IN6 :: DATA_IN6 [07:00] */ #define I2C_DATA_IN6_DATA_IN6_MASK 0x000000ff #define I2C_DATA_IN6_DATA_IN6_ALIGN 0 #define I2C_DATA_IN6_DATA_IN6_BITS 8 #define I2C_DATA_IN6_DATA_IN6_SHIFT 0 /**************************************************************************** * I2C :: DATA_IN7 ***************************************************************************/ /* I2C :: DATA_IN7 :: reserved0 [31:08] */ #define I2C_DATA_IN7_reserved0_MASK 0xffffff00 #define I2C_DATA_IN7_reserved0_ALIGN 0 #define I2C_DATA_IN7_reserved0_BITS 24 #define I2C_DATA_IN7_reserved0_SHIFT 8 /* I2C :: DATA_IN7 :: DATA_IN7 [07:00] */ #define I2C_DATA_IN7_DATA_IN7_MASK 0x000000ff #define I2C_DATA_IN7_DATA_IN7_ALIGN 0 #define I2C_DATA_IN7_DATA_IN7_BITS 8 #define I2C_DATA_IN7_DATA_IN7_SHIFT 0 /**************************************************************************** * I2C :: CNT_REG ***************************************************************************/ /* I2C :: CNT_REG :: reserved0 [31:08] */ #define I2C_CNT_REG_reserved0_MASK 0xffffff00 #define I2C_CNT_REG_reserved0_ALIGN 0 #define I2C_CNT_REG_reserved0_BITS 24 #define I2C_CNT_REG_reserved0_SHIFT 8 /* I2C :: CNT_REG :: CNT_REG2 [07:04] */ #define I2C_CNT_REG_CNT_REG2_MASK 0x000000f0 #define I2C_CNT_REG_CNT_REG2_ALIGN 0 #define I2C_CNT_REG_CNT_REG2_BITS 4 #define I2C_CNT_REG_CNT_REG2_SHIFT 4 /* I2C :: CNT_REG :: CNT_REG1 [03:00] */ #define I2C_CNT_REG_CNT_REG1_MASK 0x0000000f #define I2C_CNT_REG_CNT_REG1_ALIGN 0 #define I2C_CNT_REG_CNT_REG1_BITS 4 #define I2C_CNT_REG_CNT_REG1_SHIFT 0 /**************************************************************************** * I2C :: CTL_REG ***************************************************************************/ /* I2C :: CTL_REG :: reserved0 [31:08] */ #define I2C_CTL_REG_reserved0_MASK 0xffffff00 #define I2C_CTL_REG_reserved0_ALIGN 0 #define I2C_CTL_REG_reserved0_BITS 24 #define I2C_CTL_REG_reserved0_SHIFT 8 /* I2C :: CTL_REG :: DIV_CLK [07:07] */ #define I2C_CTL_REG_DIV_CLK_MASK 0x00000080 #define I2C_CTL_REG_DIV_CLK_ALIGN 0 #define I2C_CTL_REG_DIV_CLK_BITS 1 #define I2C_CTL_REG_DIV_CLK_SHIFT 7 /* I2C :: CTL_REG :: INT_EN [06:06] */ #define I2C_CTL_REG_INT_EN_MASK 0x00000040 #define I2C_CTL_REG_INT_EN_ALIGN 0 #define I2C_CTL_REG_INT_EN_BITS 1 #define I2C_CTL_REG_INT_EN_SHIFT 6 /* I2C :: CTL_REG :: SCL_SEL [05:04] */ #define I2C_CTL_REG_SCL_SEL_MASK 0x00000030 #define I2C_CTL_REG_SCL_SEL_ALIGN 0 #define I2C_CTL_REG_SCL_SEL_BITS 2 #define I2C_CTL_REG_SCL_SEL_SHIFT 4 /* I2C :: CTL_REG :: DELAY_DIS [03:03] */ #define I2C_CTL_REG_DELAY_DIS_MASK 0x00000008 #define I2C_CTL_REG_DELAY_DIS_ALIGN 0 #define I2C_CTL_REG_DELAY_DIS_BITS 1 #define I2C_CTL_REG_DELAY_DIS_SHIFT 3 /* I2C :: CTL_REG :: DEGLITCH_DIS [02:02] */ #define I2C_CTL_REG_DEGLITCH_DIS_MASK 0x00000004 #define I2C_CTL_REG_DEGLITCH_DIS_ALIGN 0 #define I2C_CTL_REG_DEGLITCH_DIS_BITS 1 #define I2C_CTL_REG_DEGLITCH_DIS_SHIFT 2 /* I2C :: CTL_REG :: DTF [01:00] */ #define I2C_CTL_REG_DTF_MASK 0x00000003 #define I2C_CTL_REG_DTF_ALIGN 0 #define I2C_CTL_REG_DTF_BITS 2 #define I2C_CTL_REG_DTF_SHIFT 0 /**************************************************************************** * I2C :: IIC_ENABLE ***************************************************************************/ /* I2C :: IIC_ENABLE :: reserved0 [31:07] */ #define I2C_IIC_ENABLE_reserved0_MASK 0xffffff80 #define I2C_IIC_ENABLE_reserved0_ALIGN 0 #define I2C_IIC_ENABLE_reserved0_BITS 25 #define I2C_IIC_ENABLE_reserved0_SHIFT 7 /* I2C :: IIC_ENABLE :: RESTART [06:06] */ #define I2C_IIC_ENABLE_RESTART_MASK 0x00000040 #define I2C_IIC_ENABLE_RESTART_ALIGN 0 #define I2C_IIC_ENABLE_RESTART_BITS 1 #define I2C_IIC_ENABLE_RESTART_SHIFT 6 /* I2C :: IIC_ENABLE :: NO_START [05:05] */ #define I2C_IIC_ENABLE_NO_START_MASK 0x00000020 #define I2C_IIC_ENABLE_NO_START_ALIGN 0 #define I2C_IIC_ENABLE_NO_START_BITS 1 #define I2C_IIC_ENABLE_NO_START_SHIFT 5 /* I2C :: IIC_ENABLE :: NO_STOP [04:04] */ #define I2C_IIC_ENABLE_NO_STOP_MASK 0x00000010 #define I2C_IIC_ENABLE_NO_STOP_ALIGN 0 #define I2C_IIC_ENABLE_NO_STOP_BITS 1 #define I2C_IIC_ENABLE_NO_STOP_SHIFT 4 /* I2C :: IIC_ENABLE :: reserved1 [03:03] */ #define I2C_IIC_ENABLE_reserved1_MASK 0x00000008 #define I2C_IIC_ENABLE_reserved1_ALIGN 0 #define I2C_IIC_ENABLE_reserved1_BITS 1 #define I2C_IIC_ENABLE_reserved1_SHIFT 3 /* I2C :: IIC_ENABLE :: NO_ACK [02:02] */ #define I2C_IIC_ENABLE_NO_ACK_MASK 0x00000004 #define I2C_IIC_ENABLE_NO_ACK_ALIGN 0 #define I2C_IIC_ENABLE_NO_ACK_BITS 1 #define I2C_IIC_ENABLE_NO_ACK_SHIFT 2 /* I2C :: IIC_ENABLE :: INTRP [01:01] */ #define I2C_IIC_ENABLE_INTRP_MASK 0x00000002 #define I2C_IIC_ENABLE_INTRP_ALIGN 0 #define I2C_IIC_ENABLE_INTRP_BITS 1 #define I2C_IIC_ENABLE_INTRP_SHIFT 1 /* I2C :: IIC_ENABLE :: ENABLE [00:00] */ #define I2C_IIC_ENABLE_ENABLE_MASK 0x00000001 #define I2C_IIC_ENABLE_ENABLE_ALIGN 0 #define I2C_IIC_ENABLE_ENABLE_BITS 1 #define I2C_IIC_ENABLE_ENABLE_SHIFT 0 /**************************************************************************** * I2C :: DATA_OUT0 ***************************************************************************/ /* I2C :: DATA_OUT0 :: reserved0 [31:08] */ #define I2C_DATA_OUT0_reserved0_MASK 0xffffff00 #define I2C_DATA_OUT0_reserved0_ALIGN 0 #define I2C_DATA_OUT0_reserved0_BITS 24 #define I2C_DATA_OUT0_reserved0_SHIFT 8 /* I2C :: DATA_OUT0 :: DATA_OUT0 [07:00] */ #define I2C_DATA_OUT0_DATA_OUT0_MASK 0x000000ff #define I2C_DATA_OUT0_DATA_OUT0_ALIGN 0 #define I2C_DATA_OUT0_DATA_OUT0_BITS 8 #define I2C_DATA_OUT0_DATA_OUT0_SHIFT 0 /**************************************************************************** * I2C :: DATA_OUT1 ***************************************************************************/ /* I2C :: DATA_OUT1 :: reserved0 [31:08] */ #define I2C_DATA_OUT1_reserved0_MASK 0xffffff00 #define I2C_DATA_OUT1_reserved0_ALIGN 0 #define I2C_DATA_OUT1_reserved0_BITS 24 #define I2C_DATA_OUT1_reserved0_SHIFT 8 /* I2C :: DATA_OUT1 :: DATA_OUT1 [07:00] */ #define I2C_DATA_OUT1_DATA_OUT1_MASK 0x000000ff #define I2C_DATA_OUT1_DATA_OUT1_ALIGN 0 #define I2C_DATA_OUT1_DATA_OUT1_BITS 8 #define I2C_DATA_OUT1_DATA_OUT1_SHIFT 0 /**************************************************************************** * I2C :: DATA_OUT2 ***************************************************************************/ /* I2C :: DATA_OUT2 :: reserved0 [31:08] */ #define I2C_DATA_OUT2_reserved0_MASK 0xffffff00 #define I2C_DATA_OUT2_reserved0_ALIGN 0 #define I2C_DATA_OUT2_reserved0_BITS 24 #define I2C_DATA_OUT2_reserved0_SHIFT 8 /* I2C :: DATA_OUT2 :: DATA_OUT2 [07:00] */ #define I2C_DATA_OUT2_DATA_OUT2_MASK 0x000000ff #define I2C_DATA_OUT2_DATA_OUT2_ALIGN 0 #define I2C_DATA_OUT2_DATA_OUT2_BITS 8 #define I2C_DATA_OUT2_DATA_OUT2_SHIFT 0 /**************************************************************************** * I2C :: DATA_OUT3 ***************************************************************************/ /* I2C :: DATA_OUT3 :: reserved0 [31:08] */ #define I2C_DATA_OUT3_reserved0_MASK 0xffffff00 #define I2C_DATA_OUT3_reserved0_ALIGN 0 #define I2C_DATA_OUT3_reserved0_BITS 24 #define I2C_DATA_OUT3_reserved0_SHIFT 8 /* I2C :: DATA_OUT3 :: DATA_OUT3 [07:00] */ #define I2C_DATA_OUT3_DATA_OUT3_MASK 0x000000ff #define I2C_DATA_OUT3_DATA_OUT3_ALIGN 0 #define I2C_DATA_OUT3_DATA_OUT3_BITS 8 #define I2C_DATA_OUT3_DATA_OUT3_SHIFT 0 /**************************************************************************** * I2C :: DATA_OUT4 ***************************************************************************/ /* I2C :: DATA_OUT4 :: reserved0 [31:08] */ #define I2C_DATA_OUT4_reserved0_MASK 0xffffff00 #define I2C_DATA_OUT4_reserved0_ALIGN 0 #define I2C_DATA_OUT4_reserved0_BITS 24 #define I2C_DATA_OUT4_reserved0_SHIFT 8 /* I2C :: DATA_OUT4 :: DATA_OUT4 [07:00] */ #define I2C_DATA_OUT4_DATA_OUT4_MASK 0x000000ff #define I2C_DATA_OUT4_DATA_OUT4_ALIGN 0 #define I2C_DATA_OUT4_DATA_OUT4_BITS 8 #define I2C_DATA_OUT4_DATA_OUT4_SHIFT 0 /**************************************************************************** * I2C :: DATA_OUT5 ***************************************************************************/ /* I2C :: DATA_OUT5 :: reserved0 [31:08] */ #define I2C_DATA_OUT5_reserved0_MASK 0xffffff00 #define I2C_DATA_OUT5_reserved0_ALIGN 0 #define I2C_DATA_OUT5_reserved0_BITS 24 #define I2C_DATA_OUT5_reserved0_SHIFT 8 /* I2C :: DATA_OUT5 :: DATA_OUT5 [07:00] */ #define I2C_DATA_OUT5_DATA_OUT5_MASK 0x000000ff #define I2C_DATA_OUT5_DATA_OUT5_ALIGN 0 #define I2C_DATA_OUT5_DATA_OUT5_BITS 8 #define I2C_DATA_OUT5_DATA_OUT5_SHIFT 0 /**************************************************************************** * I2C :: DATA_OUT6 ***************************************************************************/ /* I2C :: DATA_OUT6 :: reserved0 [31:08] */ #define I2C_DATA_OUT6_reserved0_MASK 0xffffff00 #define I2C_DATA_OUT6_reserved0_ALIGN 0 #define I2C_DATA_OUT6_reserved0_BITS 24 #define I2C_DATA_OUT6_reserved0_SHIFT 8 /* I2C :: DATA_OUT6 :: DATA_OUT6 [07:00] */ #define I2C_DATA_OUT6_DATA_OUT6_MASK 0x000000ff #define I2C_DATA_OUT6_DATA_OUT6_ALIGN 0 #define I2C_DATA_OUT6_DATA_OUT6_BITS 8 #define I2C_DATA_OUT6_DATA_OUT6_SHIFT 0 /**************************************************************************** * I2C :: DATA_OUT7 ***************************************************************************/ /* I2C :: DATA_OUT7 :: reserved0 [31:08] */ #define I2C_DATA_OUT7_reserved0_MASK 0xffffff00 #define I2C_DATA_OUT7_reserved0_ALIGN 0 #define I2C_DATA_OUT7_reserved0_BITS 24 #define I2C_DATA_OUT7_reserved0_SHIFT 8 /* I2C :: DATA_OUT7 :: DATA_OUT7 [07:00] */ #define I2C_DATA_OUT7_DATA_OUT7_MASK 0x000000ff #define I2C_DATA_OUT7_DATA_OUT7_ALIGN 0 #define I2C_DATA_OUT7_DATA_OUT7_BITS 8 #define I2C_DATA_OUT7_DATA_OUT7_SHIFT 0 /**************************************************************************** * I2C :: CTLHI_REG ***************************************************************************/ /* I2C :: CTLHI_REG :: reserved0 [31:02] */ #define I2C_CTLHI_REG_reserved0_MASK 0xfffffffc #define I2C_CTLHI_REG_reserved0_ALIGN 0 #define I2C_CTLHI_REG_reserved0_BITS 30 #define I2C_CTLHI_REG_reserved0_SHIFT 2 /* I2C :: CTLHI_REG :: IGNORE_ACK [01:01] */ #define I2C_CTLHI_REG_IGNORE_ACK_MASK 0x00000002 #define I2C_CTLHI_REG_IGNORE_ACK_ALIGN 0 #define I2C_CTLHI_REG_IGNORE_ACK_BITS 1 #define I2C_CTLHI_REG_IGNORE_ACK_SHIFT 1 /* I2C :: CTLHI_REG :: WAIT_DIS [00:00] */ #define I2C_CTLHI_REG_WAIT_DIS_MASK 0x00000001 #define I2C_CTLHI_REG_WAIT_DIS_ALIGN 0 #define I2C_CTLHI_REG_WAIT_DIS_BITS 1 #define I2C_CTLHI_REG_WAIT_DIS_SHIFT 0 /**************************************************************************** * I2C :: SCL_PARAM ***************************************************************************/ /* I2C :: SCL_PARAM :: reserved0 [31:00] */ #define I2C_SCL_PARAM_reserved0_MASK 0xffffffff #define I2C_SCL_PARAM_reserved0_ALIGN 0 #define I2C_SCL_PARAM_reserved0_BITS 32 #define I2C_SCL_PARAM_reserved0_SHIFT 0 /**************************************************************************** * BCM70012_I2C_TOP_I2C_GR_BRIDGE ***************************************************************************/ /**************************************************************************** * I2C_GR_BRIDGE :: REVISION ***************************************************************************/ /* I2C_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define I2C_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define I2C_GR_BRIDGE_REVISION_reserved0_ALIGN 0 #define I2C_GR_BRIDGE_REVISION_reserved0_BITS 16 #define I2C_GR_BRIDGE_REVISION_reserved0_SHIFT 16 /* I2C_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define I2C_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define I2C_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 #define I2C_GR_BRIDGE_REVISION_MAJOR_BITS 8 #define I2C_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* I2C_GR_BRIDGE :: REVISION :: MINOR [07:00] */ #define I2C_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define I2C_GR_BRIDGE_REVISION_MINOR_ALIGN 0 #define I2C_GR_BRIDGE_REVISION_MINOR_BITS 8 #define I2C_GR_BRIDGE_REVISION_MINOR_SHIFT 0 /**************************************************************************** * I2C_GR_BRIDGE :: CTRL ***************************************************************************/ /* I2C_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ #define I2C_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe #define I2C_GR_BRIDGE_CTRL_reserved0_ALIGN 0 #define I2C_GR_BRIDGE_CTRL_reserved0_BITS 31 #define I2C_GR_BRIDGE_CTRL_reserved0_SHIFT 1 /* I2C_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ #define I2C_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 #define I2C_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 #define I2C_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 #define I2C_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 #define I2C_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 #define I2C_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 /**************************************************************************** * I2C_GR_BRIDGE :: SPARE_SW_RESET_0 ***************************************************************************/ /* I2C_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 /* I2C_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 #define I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 /**************************************************************************** * I2C_GR_BRIDGE :: SPARE_SW_RESET_1 ***************************************************************************/ /* I2C_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 /* I2C_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 #define I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 /**************************************************************************** * BCM70012_MISC_TOP_MISC1 ***************************************************************************/ /**************************************************************************** * MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 ***************************************************************************/ /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: TX_DESC_LIST0_VALID [00:00] */ #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_MASK 0x00000001 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_ALIGN 0 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_BITS 1 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_SHIFT 0 /**************************************************************************** * MISC1 :: TX_FIRST_DESC_U_ADDR_LIST0 ***************************************************************************/ /* MISC1 :: TX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ #define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff #define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 #define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 #define MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 /**************************************************************************** * MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 ***************************************************************************/ /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: TX_DESC_LIST1_VALID [00:00] */ #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_MASK 0x00000001 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_ALIGN 0 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_BITS 1 #define MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_SHIFT 0 /**************************************************************************** * MISC1 :: TX_FIRST_DESC_U_ADDR_LIST1 ***************************************************************************/ /* MISC1 :: TX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ #define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff #define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 #define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 #define MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 /**************************************************************************** * MISC1 :: TX_SW_DESC_LIST_CTRL_STS ***************************************************************************/ /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ #define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_HALT_ON_ERROR [01:01] */ #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_MASK 0x00000002 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_ALIGN 0 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_BITS 1 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_SHIFT 1 /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */ #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_ALIGN 0 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_BITS 1 #define MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0 /**************************************************************************** * MISC1 :: TX_DMA_ERROR_STATUS ***************************************************************************/ /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved0 [31:10] */ #define MISC1_TX_DMA_ERROR_STATUS_reserved0_MASK 0xfffffc00 #define MISC1_TX_DMA_ERROR_STATUS_reserved0_ALIGN 0 #define MISC1_TX_DMA_ERROR_STATUS_reserved0_BITS 22 #define MISC1_TX_DMA_ERROR_STATUS_reserved0_SHIFT 10 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */ #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_BITS 1 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved1 [08:08] */ #define MISC1_TX_DMA_ERROR_STATUS_reserved1_MASK 0x00000100 #define MISC1_TX_DMA_ERROR_STATUS_reserved1_ALIGN 0 #define MISC1_TX_DMA_ERROR_STATUS_reserved1_BITS 1 #define MISC1_TX_DMA_ERROR_STATUS_reserved1_SHIFT 8 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */ #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_BITS 1 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved2 [06:06] */ #define MISC1_TX_DMA_ERROR_STATUS_reserved2_MASK 0x00000040 #define MISC1_TX_DMA_ERROR_STATUS_reserved2_ALIGN 0 #define MISC1_TX_DMA_ERROR_STATUS_reserved2_BITS 1 #define MISC1_TX_DMA_ERROR_STATUS_reserved2_SHIFT 6 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DMA_DATA_TX_ABORT_ERRORS [05:05] */ #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000020 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_BITS 1 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_SHIFT 5 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_FIFO_FULL_ERRORS [04:04] */ #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_ALIGN 0 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_BITS 1 #define MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_SHIFT 4 /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved3 [03:03] */ #define MISC1_TX_DMA_ERROR_STATUS_reserved3_MASK 0x00000008 #define MISC1_TX_DMA_ERROR_STATUS_reserved3_ALIGN 0 #define MISC1_TX_DMA_ERROR_STATUS_reserved3_BITS 1 #define MISC1_TX_DMA_ERROR_STATUS_reserved3_SHIFT 3 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DMA_DATA_TX_ABORT_ERRORS [02:02] */ #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000004 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_ALIGN 0 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_BITS 1 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_SHIFT 2 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_FIFO_FULL_ERRORS [01:01] */ #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_ALIGN 0 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_BITS 1 #define MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_SHIFT 1 /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved4 [00:00] */ #define MISC1_TX_DMA_ERROR_STATUS_reserved4_MASK 0x00000001 #define MISC1_TX_DMA_ERROR_STATUS_reserved4_ALIGN 0 #define MISC1_TX_DMA_ERROR_STATUS_reserved4_BITS 1 #define MISC1_TX_DMA_ERROR_STATUS_reserved4_SHIFT 0 /**************************************************************************** * MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR ***************************************************************************/ /* MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR :: TX_DMA_L0_CUR_DESC_L_ADDR [31:05] */ #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_ALIGN 0 #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_BITS 27 #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_SHIFT 5 /* MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 #define MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 /**************************************************************************** * MISC1 :: TX_DMA_LIST0_CUR_DESC_U_ADDR ***************************************************************************/ /* MISC1 :: TX_DMA_LIST0_CUR_DESC_U_ADDR :: TX_DMA_L0_CUR_DESC_U_ADDR [31:00] */ #define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_MASK 0xffffffff #define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_ALIGN 0 #define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_BITS 32 #define MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_SHIFT 0 /**************************************************************************** * MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM ***************************************************************************/ /* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: reserved0 [31:24] */ #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_MASK 0xff000000 #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_ALIGN 0 #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_BITS 8 #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_SHIFT 24 /* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: TX_DMA_L0_CUR_BYTE_CNT_REM [23:02] */ #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_MASK 0x00fffffc #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_ALIGN 0 #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_BITS 22 #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_SHIFT 2 /* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: reserved1 [01:00] */ #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_MASK 0x00000003 #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_ALIGN 0 #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_BITS 2 #define MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_SHIFT 0 /**************************************************************************** * MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR ***************************************************************************/ /* MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR :: TX_DMA_L1_CUR_DESC_L_ADDR [31:05] */ #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_ALIGN 0 #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_BITS 27 #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_SHIFT 5 /* MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 #define MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 /**************************************************************************** * MISC1 :: TX_DMA_LIST1_CUR_DESC_U_ADDR ***************************************************************************/ /* MISC1 :: TX_DMA_LIST1_CUR_DESC_U_ADDR :: TX_DMA_L1_CUR_DESC_U_ADDR [31:00] */ #define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_MASK 0xffffffff #define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_ALIGN 0 #define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_BITS 32 #define MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_SHIFT 0 /**************************************************************************** * MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM ***************************************************************************/ /* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: reserved0 [31:24] */ #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_MASK 0xff000000 #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_ALIGN 0 #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_BITS 8 #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_SHIFT 24 /* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: TX_DMA_L1_CUR_BYTE_CNT_REM [23:02] */ #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_MASK 0x00fffffc #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_ALIGN 0 #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_BITS 22 #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_SHIFT 2 /* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: reserved1 [01:00] */ #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_MASK 0x00000003 #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_ALIGN 0 #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_BITS 2 #define MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_SHIFT 0 /**************************************************************************** * MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 ***************************************************************************/ /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */ #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_ALIGN 0 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_BITS 1 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0 /**************************************************************************** * MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST0 ***************************************************************************/ /* MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 /**************************************************************************** * MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 ***************************************************************************/ /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */ #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_ALIGN 0 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_BITS 1 #define MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0 /**************************************************************************** * MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST1 ***************************************************************************/ /* MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 #define MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 /**************************************************************************** * MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS ***************************************************************************/ /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: RX_HALT_ON_ERROR [01:01] */ #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_MASK 0x00000002 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_ALIGN 0 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_BITS 1 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_SHIFT 1 /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: RX_RUN_STOP [00:00] */ #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_MASK 0x00000001 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_ALIGN 0 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_BITS 1 #define MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_SHIFT 0 /**************************************************************************** * MISC1 :: Y_RX_ERROR_STATUS ***************************************************************************/ /* MISC1 :: Y_RX_ERROR_STATUS :: reserved0 [31:14] */ #define MISC1_Y_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 #define MISC1_Y_RX_ERROR_STATUS_reserved0_ALIGN 0 #define MISC1_Y_RX_ERROR_STATUS_reserved0_BITS 18 #define MISC1_Y_RX_ERROR_STATUS_reserved0_SHIFT 14 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ #define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ #define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ #define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ #define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 /* MISC1 :: Y_RX_ERROR_STATUS :: reserved1 [08:08] */ #define MISC1_Y_RX_ERROR_STATUS_reserved1_MASK 0x00000100 #define MISC1_Y_RX_ERROR_STATUS_reserved1_ALIGN 0 #define MISC1_Y_RX_ERROR_STATUS_reserved1_BITS 1 #define MISC1_Y_RX_ERROR_STATUS_reserved1_SHIFT 8 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ #define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 /* MISC1 :: Y_RX_ERROR_STATUS :: reserved2 [06:05] */ #define MISC1_Y_RX_ERROR_STATUS_reserved2_MASK 0x00000060 #define MISC1_Y_RX_ERROR_STATUS_reserved2_ALIGN 0 #define MISC1_Y_RX_ERROR_STATUS_reserved2_BITS 2 #define MISC1_Y_RX_ERROR_STATUS_reserved2_SHIFT 5 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ #define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 #define MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 /* MISC1 :: Y_RX_ERROR_STATUS :: reserved3 [03:02] */ #define MISC1_Y_RX_ERROR_STATUS_reserved3_MASK 0x0000000c #define MISC1_Y_RX_ERROR_STATUS_reserved3_ALIGN 0 #define MISC1_Y_RX_ERROR_STATUS_reserved3_BITS 2 #define MISC1_Y_RX_ERROR_STATUS_reserved3_SHIFT 2 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ #define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 #define MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 /* MISC1 :: Y_RX_ERROR_STATUS :: reserved4 [00:00] */ #define MISC1_Y_RX_ERROR_STATUS_reserved4_MASK 0x00000001 #define MISC1_Y_RX_ERROR_STATUS_reserved4_ALIGN 0 #define MISC1_Y_RX_ERROR_STATUS_reserved4_BITS 1 #define MISC1_Y_RX_ERROR_STATUS_reserved4_SHIFT 0 /**************************************************************************** * MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR ***************************************************************************/ /* MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */ #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_ALIGN 0 #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_BITS 27 #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5 /* MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 #define MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 /**************************************************************************** * MISC1 :: Y_RX_LIST0_CUR_DESC_U_ADDR ***************************************************************************/ /* MISC1 :: Y_RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */ #define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff #define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_ALIGN 0 #define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_BITS 32 #define MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0 /**************************************************************************** * MISC1 :: Y_RX_LIST0_CUR_BYTE_CNT ***************************************************************************/ /* MISC1 :: Y_RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */ #define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff #define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_ALIGN 0 #define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_BITS 32 #define MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0 /**************************************************************************** * MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR ***************************************************************************/ /* MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */ #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_ALIGN 0 #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_BITS 27 #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5 /* MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 #define MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 /**************************************************************************** * MISC1 :: Y_RX_LIST1_CUR_DESC_U_ADDR ***************************************************************************/ /* MISC1 :: Y_RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */ #define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff #define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_ALIGN 0 #define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_BITS 32 #define MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0 /**************************************************************************** * MISC1 :: Y_RX_LIST1_CUR_BYTE_CNT ***************************************************************************/ /* MISC1 :: Y_RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */ #define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff #define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_ALIGN 0 #define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_BITS 32 #define MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0 /**************************************************************************** * MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 ***************************************************************************/ /* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_ALIGN 0 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_BITS 27 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 /* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_ALIGN 0 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_BITS 4 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 /* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */ #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_ALIGN 0 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_BITS 1 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0 /**************************************************************************** * MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST0 ***************************************************************************/ /* MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_ALIGN 0 #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_BITS 32 #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 /**************************************************************************** * MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 ***************************************************************************/ /* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_ALIGN 0 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_BITS 27 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 /* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_ALIGN 0 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_BITS 4 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 /* MISC1 :: UV_RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */ #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_ALIGN 0 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_BITS 1 #define MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0 /**************************************************************************** * MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST1 ***************************************************************************/ /* MISC1 :: UV_RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_ALIGN 0 #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_BITS 32 #define MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 /**************************************************************************** * MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS ***************************************************************************/ /* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_ALIGN 0 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_BITS 28 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 /* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_ALIGN 0 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_BITS 1 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 /* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_ALIGN 0 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_BITS 1 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 /* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: RX_HALT_ON_ERROR [01:01] */ #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_MASK 0x00000002 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_ALIGN 0 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_BITS 1 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_SHIFT 1 /* MISC1 :: UV_RX_SW_DESC_LIST_CTRL_STS :: RX_RUN_STOP [00:00] */ #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_MASK 0x00000001 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_ALIGN 0 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_BITS 1 #define MISC1_UV_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_SHIFT 0 /**************************************************************************** * MISC1 :: UV_RX_ERROR_STATUS ***************************************************************************/ /* MISC1 :: UV_RX_ERROR_STATUS :: reserved0 [31:14] */ #define MISC1_UV_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 #define MISC1_UV_RX_ERROR_STATUS_reserved0_ALIGN 0 #define MISC1_UV_RX_ERROR_STATUS_reserved0_BITS 18 #define MISC1_UV_RX_ERROR_STATUS_reserved0_SHIFT 14 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ #define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_ALIGN 0 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_BITS 1 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ #define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_ALIGN 0 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_BITS 1 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ #define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_ALIGN 0 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_BITS 1 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ #define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_ALIGN 0 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_BITS 1 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ #define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_ALIGN 0 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_BITS 1 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 /* MISC1 :: UV_RX_ERROR_STATUS :: reserved1 [08:08] */ #define MISC1_UV_RX_ERROR_STATUS_reserved1_MASK 0x00000100 #define MISC1_UV_RX_ERROR_STATUS_reserved1_ALIGN 0 #define MISC1_UV_RX_ERROR_STATUS_reserved1_BITS 1 #define MISC1_UV_RX_ERROR_STATUS_reserved1_SHIFT 8 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ #define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_ALIGN 0 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_BITS 1 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 /* MISC1 :: UV_RX_ERROR_STATUS :: reserved2 [06:05] */ #define MISC1_UV_RX_ERROR_STATUS_reserved2_MASK 0x00000060 #define MISC1_UV_RX_ERROR_STATUS_reserved2_ALIGN 0 #define MISC1_UV_RX_ERROR_STATUS_reserved2_BITS 2 #define MISC1_UV_RX_ERROR_STATUS_reserved2_SHIFT 5 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ #define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_ALIGN 0 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_BITS 1 #define MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 /* MISC1 :: UV_RX_ERROR_STATUS :: reserved3 [03:02] */ #define MISC1_UV_RX_ERROR_STATUS_reserved3_MASK 0x0000000c #define MISC1_UV_RX_ERROR_STATUS_reserved3_ALIGN 0 #define MISC1_UV_RX_ERROR_STATUS_reserved3_BITS 2 #define MISC1_UV_RX_ERROR_STATUS_reserved3_SHIFT 2 /* MISC1 :: UV_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ #define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_ALIGN 0 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_BITS 1 #define MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 /* MISC1 :: UV_RX_ERROR_STATUS :: reserved4 [00:00] */ #define MISC1_UV_RX_ERROR_STATUS_reserved4_MASK 0x00000001 #define MISC1_UV_RX_ERROR_STATUS_reserved4_ALIGN 0 #define MISC1_UV_RX_ERROR_STATUS_reserved4_BITS 1 #define MISC1_UV_RX_ERROR_STATUS_reserved4_SHIFT 0 /**************************************************************************** * MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR ***************************************************************************/ /* MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */ #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_ALIGN 0 #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_BITS 27 #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5 /* MISC1 :: UV_RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_ALIGN 0 #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_BITS 5 #define MISC1_UV_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 /**************************************************************************** * MISC1 :: UV_RX_LIST0_CUR_DESC_U_ADDR ***************************************************************************/ /* MISC1 :: UV_RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */ #define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff #define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_ALIGN 0 #define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_BITS 32 #define MISC1_UV_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0 /**************************************************************************** * MISC1 :: UV_RX_LIST0_CUR_BYTE_CNT ***************************************************************************/ /* MISC1 :: UV_RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */ #define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff #define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_ALIGN 0 #define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_BITS 32 #define MISC1_UV_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0 /**************************************************************************** * MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR ***************************************************************************/ /* MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */ #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_ALIGN 0 #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_BITS 27 #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5 /* MISC1 :: UV_RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_ALIGN 0 #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_BITS 5 #define MISC1_UV_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 /**************************************************************************** * MISC1 :: UV_RX_LIST1_CUR_DESC_U_ADDR ***************************************************************************/ /* MISC1 :: UV_RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */ #define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff #define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_ALIGN 0 #define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_BITS 32 #define MISC1_UV_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0 /**************************************************************************** * MISC1 :: UV_RX_LIST1_CUR_BYTE_CNT ***************************************************************************/ /* MISC1 :: UV_RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */ #define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff #define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_ALIGN 0 #define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_BITS 32 #define MISC1_UV_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0 /**************************************************************************** * MISC1 :: DMA_DEBUG_OPTIONS_REG ***************************************************************************/ /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_SOFT_RST [31:31] */ #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_MASK 0x80000000 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_ALIGN 0 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_BITS 1 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_SHIFT 31 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_SOFT_RST [30:30] */ #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_MASK 0x40000000 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_ALIGN 0 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_BITS 1 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_SHIFT 30 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST [29:29] */ #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_MASK 0x20000000 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_ALIGN 0 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_BITS 1 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_SHIFT 29 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST [28:28] */ #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_MASK 0x10000000 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_ALIGN 0 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_BITS 1 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_SHIFT 28 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_0 [27:05] */ #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_MASK 0x0fffffe0 #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_ALIGN 0 #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_BITS 23 #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_SHIFT 5 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_EN_RX_DMA_XFER_CNT [04:04] */ #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_MASK 0x00000010 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_ALIGN 0 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_BITS 1 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_SHIFT 4 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_1 [03:03] */ #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_MASK 0x00000008 #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_ALIGN 0 #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_BITS 1 #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_SHIFT 3 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_RD_Q [02:02] */ #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_MASK 0x00000004 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_ALIGN 0 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_BITS 1 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_SHIFT 2 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_WR_Q [01:01] */ #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_MASK 0x00000002 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_ALIGN 0 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_BITS 1 #define MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_SHIFT 1 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_2 [00:00] */ #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_MASK 0x00000001 #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_ALIGN 0 #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_BITS 1 #define MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_SHIFT 0 /**************************************************************************** * MISC1 :: READ_CHANNEL_ERROR_STATUS ***************************************************************************/ /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_7 [31:28] */ #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_MASK 0xf0000000 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_ALIGN 0 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_BITS 4 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_SHIFT 28 /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_6 [27:24] */ #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_MASK 0x0f000000 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_ALIGN 0 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_BITS 4 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_SHIFT 24 /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_5 [23:20] */ #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_MASK 0x00f00000 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_ALIGN 0 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_BITS 4 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_SHIFT 20 /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_4 [19:16] */ #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_MASK 0x000f0000 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_ALIGN 0 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_BITS 4 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_SHIFT 16 /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_3 [15:12] */ #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_MASK 0x0000f000 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_ALIGN 0 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_BITS 4 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_SHIFT 12 /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_2 [11:08] */ #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_MASK 0x00000f00 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_ALIGN 0 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_BITS 4 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_SHIFT 8 /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_1 [07:04] */ #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_MASK 0x000000f0 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_ALIGN 0 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_BITS 4 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_SHIFT 4 /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_0 [03:00] */ #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_MASK 0x0000000f #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_ALIGN 0 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_BITS 4 #define MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_SHIFT 0 /**************************************************************************** * MISC1 :: PCIE_DMA_CTRL ***************************************************************************/ /* MISC1 :: PCIE_DMA_CTRL :: reserved0 [31:18] */ #define MISC1_PCIE_DMA_CTRL_reserved0_MASK 0xfffc0000 #define MISC1_PCIE_DMA_CTRL_reserved0_ALIGN 0 #define MISC1_PCIE_DMA_CTRL_reserved0_BITS 14 #define MISC1_PCIE_DMA_CTRL_reserved0_SHIFT 18 /* MISC1 :: PCIE_DMA_CTRL :: DESC_ENDIAN_MODE [17:16] */ #define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_MASK 0x00030000 #define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_ALIGN 0 #define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_BITS 2 #define MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_SHIFT 16 /* MISC1 :: PCIE_DMA_CTRL :: reserved1 [15:10] */ #define MISC1_PCIE_DMA_CTRL_reserved1_MASK 0x0000fc00 #define MISC1_PCIE_DMA_CTRL_reserved1_ALIGN 0 #define MISC1_PCIE_DMA_CTRL_reserved1_BITS 6 #define MISC1_PCIE_DMA_CTRL_reserved1_SHIFT 10 /* MISC1 :: PCIE_DMA_CTRL :: EN_WEIGHTED_RR [09:09] */ #define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_MASK 0x00000200 #define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_ALIGN 0 #define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_BITS 1 #define MISC1_PCIE_DMA_CTRL_EN_WEIGHTED_RR_SHIFT 9 /* MISC1 :: PCIE_DMA_CTRL :: EN_ROUND_ROBIN [08:08] */ #define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_MASK 0x00000100 #define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_ALIGN 0 #define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_BITS 1 #define MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_SHIFT 8 /* MISC1 :: PCIE_DMA_CTRL :: reserved2 [07:05] */ #define MISC1_PCIE_DMA_CTRL_reserved2_MASK 0x000000e0 #define MISC1_PCIE_DMA_CTRL_reserved2_ALIGN 0 #define MISC1_PCIE_DMA_CTRL_reserved2_BITS 3 #define MISC1_PCIE_DMA_CTRL_reserved2_SHIFT 5 /* MISC1 :: PCIE_DMA_CTRL :: RELAXED_ORDERING [04:04] */ #define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_MASK 0x00000010 #define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_ALIGN 0 #define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_BITS 1 #define MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_SHIFT 4 /* MISC1 :: PCIE_DMA_CTRL :: NO_SNOOP [03:03] */ #define MISC1_PCIE_DMA_CTRL_NO_SNOOP_MASK 0x00000008 #define MISC1_PCIE_DMA_CTRL_NO_SNOOP_ALIGN 0 #define MISC1_PCIE_DMA_CTRL_NO_SNOOP_BITS 1 #define MISC1_PCIE_DMA_CTRL_NO_SNOOP_SHIFT 3 /* MISC1 :: PCIE_DMA_CTRL :: TRAFFIC_CLASS [02:00] */ #define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_MASK 0x00000007 #define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_ALIGN 0 #define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_BITS 3 #define MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_SHIFT 0 /**************************************************************************** * BCM70012_MISC_TOP_MISC2 ***************************************************************************/ /**************************************************************************** * MISC2 :: GLOBAL_CTRL ***************************************************************************/ /* MISC2 :: GLOBAL_CTRL :: reserved0 [31:21] */ #define MISC2_GLOBAL_CTRL_reserved0_MASK 0xffe00000 #define MISC2_GLOBAL_CTRL_reserved0_ALIGN 0 #define MISC2_GLOBAL_CTRL_reserved0_BITS 11 #define MISC2_GLOBAL_CTRL_reserved0_SHIFT 21 /* MISC2 :: GLOBAL_CTRL :: EN_WRITE_ALL [20:20] */ #define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_MASK 0x00100000 #define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_ALIGN 0 #define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_BITS 1 #define MISC2_GLOBAL_CTRL_EN_WRITE_ALL_SHIFT 20 /* MISC2 :: GLOBAL_CTRL :: reserved1 [19:17] */ #define MISC2_GLOBAL_CTRL_reserved1_MASK 0x000e0000 #define MISC2_GLOBAL_CTRL_reserved1_ALIGN 0 #define MISC2_GLOBAL_CTRL_reserved1_BITS 3 #define MISC2_GLOBAL_CTRL_reserved1_SHIFT 17 /* MISC2 :: GLOBAL_CTRL :: EN_SINGLE_DMA [16:16] */ #define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_MASK 0x00010000 #define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_ALIGN 0 #define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_BITS 1 #define MISC2_GLOBAL_CTRL_EN_SINGLE_DMA_SHIFT 16 /* MISC2 :: GLOBAL_CTRL :: reserved2 [15:11] */ #define MISC2_GLOBAL_CTRL_reserved2_MASK 0x0000f800 #define MISC2_GLOBAL_CTRL_reserved2_ALIGN 0 #define MISC2_GLOBAL_CTRL_reserved2_BITS 5 #define MISC2_GLOBAL_CTRL_reserved2_SHIFT 11 /* MISC2 :: GLOBAL_CTRL :: Y_UV_FIFO_LEN_SEL [10:10] */ #define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_MASK 0x00000400 #define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_ALIGN 0 #define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_BITS 1 #define MISC2_GLOBAL_CTRL_Y_UV_FIFO_LEN_SEL_SHIFT 10 /* MISC2 :: GLOBAL_CTRL :: ODD_DE_EOFRST_DIS [09:09] */ #define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_MASK 0x00000200 #define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_ALIGN 0 #define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_BITS 1 #define MISC2_GLOBAL_CTRL_ODD_DE_EOFRST_DIS_SHIFT 9 /* MISC2 :: GLOBAL_CTRL :: DIS_BIT_STUFFING [08:08] */ #define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_MASK 0x00000100 #define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_ALIGN 0 #define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_BITS 1 #define MISC2_GLOBAL_CTRL_DIS_BIT_STUFFING_SHIFT 8 /* MISC2 :: GLOBAL_CTRL :: reserved3 [07:05] */ #define MISC2_GLOBAL_CTRL_reserved3_MASK 0x000000e0 #define MISC2_GLOBAL_CTRL_reserved3_ALIGN 0 #define MISC2_GLOBAL_CTRL_reserved3_BITS 3 #define MISC2_GLOBAL_CTRL_reserved3_SHIFT 5 /* MISC2 :: GLOBAL_CTRL :: EN_PROG_MODE [04:04] */ #define MISC2_GLOBAL_CTRL_EN_PROG_MODE_MASK 0x00000010 #define MISC2_GLOBAL_CTRL_EN_PROG_MODE_ALIGN 0 #define MISC2_GLOBAL_CTRL_EN_PROG_MODE_BITS 1 #define MISC2_GLOBAL_CTRL_EN_PROG_MODE_SHIFT 4 /* MISC2 :: GLOBAL_CTRL :: reserved4 [03:01] */ #define MISC2_GLOBAL_CTRL_reserved4_MASK 0x0000000e #define MISC2_GLOBAL_CTRL_reserved4_ALIGN 0 #define MISC2_GLOBAL_CTRL_reserved4_BITS 3 #define MISC2_GLOBAL_CTRL_reserved4_SHIFT 1 /* MISC2 :: GLOBAL_CTRL :: EN_188B [00:00] */ #define MISC2_GLOBAL_CTRL_EN_188B_MASK 0x00000001 #define MISC2_GLOBAL_CTRL_EN_188B_ALIGN 0 #define MISC2_GLOBAL_CTRL_EN_188B_BITS 1 #define MISC2_GLOBAL_CTRL_EN_188B_SHIFT 0 /**************************************************************************** * MISC2 :: INTERNAL_STATUS ***************************************************************************/ /* MISC2 :: INTERNAL_STATUS :: reserved0 [31:12] */ #define MISC2_INTERNAL_STATUS_reserved0_MASK 0xfffff000 #define MISC2_INTERNAL_STATUS_reserved0_ALIGN 0 #define MISC2_INTERNAL_STATUS_reserved0_BITS 20 #define MISC2_INTERNAL_STATUS_reserved0_SHIFT 12 /* MISC2 :: INTERNAL_STATUS :: UV_BYTE_COUNT_FIFO_FULL [11:11] */ #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_MASK 0x00000800 #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_ALIGN 0 #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_BITS 1 #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_FULL_SHIFT 11 /* MISC2 :: INTERNAL_STATUS :: UV_DATA_FIFO_FULL [10:10] */ #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_MASK 0x00000400 #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_ALIGN 0 #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_BITS 1 #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_FULL_SHIFT 10 /* MISC2 :: INTERNAL_STATUS :: Y_BYTE_COUNT_FIFO_FULL [09:09] */ #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_MASK 0x00000200 #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_ALIGN 0 #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_BITS 1 #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_FULL_SHIFT 9 /* MISC2 :: INTERNAL_STATUS :: Y_DATA_FIFO_FULL [08:08] */ #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_MASK 0x00000100 #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_ALIGN 0 #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_BITS 1 #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_FULL_SHIFT 8 /* MISC2 :: INTERNAL_STATUS :: UV_BYTE_COUNT_FIFO_EMPTY [07:07] */ #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_MASK 0x00000080 #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_ALIGN 0 #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_BITS 1 #define MISC2_INTERNAL_STATUS_UV_BYTE_COUNT_FIFO_EMPTY_SHIFT 7 /* MISC2 :: INTERNAL_STATUS :: UV_DATA_FIFO_EMPTY [06:06] */ #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_MASK 0x00000040 #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_ALIGN 0 #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_BITS 1 #define MISC2_INTERNAL_STATUS_UV_DATA_FIFO_EMPTY_SHIFT 6 /* MISC2 :: INTERNAL_STATUS :: Y_BYTE_COUNT_FIFO_EMPTY [05:05] */ #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_MASK 0x00000020 #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_ALIGN 0 #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_BITS 1 #define MISC2_INTERNAL_STATUS_Y_BYTE_COUNT_FIFO_EMPTY_SHIFT 5 /* MISC2 :: INTERNAL_STATUS :: Y_DATA_FIFO_EMPTY [04:04] */ #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_MASK 0x00000010 #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_ALIGN 0 #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_BITS 1 #define MISC2_INTERNAL_STATUS_Y_DATA_FIFO_EMPTY_SHIFT 4 /* MISC2 :: INTERNAL_STATUS :: reserved1 [03:00] */ #define MISC2_INTERNAL_STATUS_reserved1_MASK 0x0000000f #define MISC2_INTERNAL_STATUS_reserved1_ALIGN 0 #define MISC2_INTERNAL_STATUS_reserved1_BITS 4 #define MISC2_INTERNAL_STATUS_reserved1_SHIFT 0 /**************************************************************************** * MISC2 :: INTERNAL_STATUS_MUX_CTRL ***************************************************************************/ /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: reserved0 [31:16] */ #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_MASK 0xffff0000 #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_ALIGN 0 #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_BITS 16 #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_SHIFT 16 /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: CLK_OUT_ALT_SRC [15:15] */ #define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_MASK 0x00008000 #define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_ALIGN 0 #define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_BITS 1 #define MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_SHIFT 15 /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_CLK_SEL [14:12] */ #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_MASK 0x00007000 #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_ALIGN 0 #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_BITS 3 #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_SHIFT 12 /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: reserved1 [11:09] */ #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_MASK 0x00000e00 #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_ALIGN 0 #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_BITS 3 #define MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_SHIFT 9 /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_TOP_CORE_SEL [08:08] */ #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_MASK 0x00000100 #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_ALIGN 0 #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_BITS 1 #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_SHIFT 8 /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_CORE_BLK_SEL [07:04] */ #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_MASK 0x000000f0 #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_ALIGN 0 #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_BITS 4 #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_SHIFT 4 /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_VECTOR_SEL [03:00] */ #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_MASK 0x0000000f #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_ALIGN 0 #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_BITS 4 #define MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_SHIFT 0 /**************************************************************************** * MISC2 :: DEBUG_FIFO_LENGTH ***************************************************************************/ /* MISC2 :: DEBUG_FIFO_LENGTH :: reserved0 [31:21] */ #define MISC2_DEBUG_FIFO_LENGTH_reserved0_MASK 0xffe00000 #define MISC2_DEBUG_FIFO_LENGTH_reserved0_ALIGN 0 #define MISC2_DEBUG_FIFO_LENGTH_reserved0_BITS 11 #define MISC2_DEBUG_FIFO_LENGTH_reserved0_SHIFT 21 /* MISC2 :: DEBUG_FIFO_LENGTH :: FIFO_LENGTH [20:00] */ #define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_MASK 0x001fffff #define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_ALIGN 0 #define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_BITS 21 #define MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_SHIFT 0 /**************************************************************************** * BCM70012_MISC_TOP_MISC3 ***************************************************************************/ /**************************************************************************** * MISC3 :: RESET_CTRL ***************************************************************************/ /* MISC3 :: RESET_CTRL :: reserved0 [31:09] */ #define MISC3_RESET_CTRL_reserved0_MASK 0xfffffe00 #define MISC3_RESET_CTRL_reserved0_ALIGN 0 #define MISC3_RESET_CTRL_reserved0_BITS 23 #define MISC3_RESET_CTRL_reserved0_SHIFT 9 /* MISC3 :: RESET_CTRL :: PLL_RESET [08:08] */ #define MISC3_RESET_CTRL_PLL_RESET_MASK 0x00000100 #define MISC3_RESET_CTRL_PLL_RESET_ALIGN 0 #define MISC3_RESET_CTRL_PLL_RESET_BITS 1 #define MISC3_RESET_CTRL_PLL_RESET_SHIFT 8 /* MISC3 :: RESET_CTRL :: reserved1 [07:02] */ #define MISC3_RESET_CTRL_reserved1_MASK 0x000000fc #define MISC3_RESET_CTRL_reserved1_ALIGN 0 #define MISC3_RESET_CTRL_reserved1_BITS 6 #define MISC3_RESET_CTRL_reserved1_SHIFT 2 /* MISC3 :: RESET_CTRL :: POR_RESET [01:01] */ #define MISC3_RESET_CTRL_POR_RESET_MASK 0x00000002 #define MISC3_RESET_CTRL_POR_RESET_ALIGN 0 #define MISC3_RESET_CTRL_POR_RESET_BITS 1 #define MISC3_RESET_CTRL_POR_RESET_SHIFT 1 /* MISC3 :: RESET_CTRL :: CORE_RESET [00:00] */ #define MISC3_RESET_CTRL_CORE_RESET_MASK 0x00000001 #define MISC3_RESET_CTRL_CORE_RESET_ALIGN 0 #define MISC3_RESET_CTRL_CORE_RESET_BITS 1 #define MISC3_RESET_CTRL_CORE_RESET_SHIFT 0 /**************************************************************************** * MISC3 :: BIST_CTRL ***************************************************************************/ /* MISC3 :: BIST_CTRL :: MBIST_OVERRIDE [31:31] */ #define MISC3_BIST_CTRL_MBIST_OVERRIDE_MASK 0x80000000 #define MISC3_BIST_CTRL_MBIST_OVERRIDE_ALIGN 0 #define MISC3_BIST_CTRL_MBIST_OVERRIDE_BITS 1 #define MISC3_BIST_CTRL_MBIST_OVERRIDE_SHIFT 31 /* MISC3 :: BIST_CTRL :: reserved0 [30:15] */ #define MISC3_BIST_CTRL_reserved0_MASK 0x7fff8000 #define MISC3_BIST_CTRL_reserved0_ALIGN 0 #define MISC3_BIST_CTRL_reserved0_BITS 16 #define MISC3_BIST_CTRL_reserved0_SHIFT 15 /* MISC3 :: BIST_CTRL :: MBIST_EN_2 [14:14] */ #define MISC3_BIST_CTRL_MBIST_EN_2_MASK 0x00004000 #define MISC3_BIST_CTRL_MBIST_EN_2_ALIGN 0 #define MISC3_BIST_CTRL_MBIST_EN_2_BITS 1 #define MISC3_BIST_CTRL_MBIST_EN_2_SHIFT 14 /* MISC3 :: BIST_CTRL :: MBIST_EN_1 [13:13] */ #define MISC3_BIST_CTRL_MBIST_EN_1_MASK 0x00002000 #define MISC3_BIST_CTRL_MBIST_EN_1_ALIGN 0 #define MISC3_BIST_CTRL_MBIST_EN_1_BITS 1 #define MISC3_BIST_CTRL_MBIST_EN_1_SHIFT 13 /* MISC3 :: BIST_CTRL :: MBIST_EN_0 [12:12] */ #define MISC3_BIST_CTRL_MBIST_EN_0_MASK 0x00001000 #define MISC3_BIST_CTRL_MBIST_EN_0_ALIGN 0 #define MISC3_BIST_CTRL_MBIST_EN_0_BITS 1 #define MISC3_BIST_CTRL_MBIST_EN_0_SHIFT 12 /* MISC3 :: BIST_CTRL :: reserved1 [11:06] */ #define MISC3_BIST_CTRL_reserved1_MASK 0x00000fc0 #define MISC3_BIST_CTRL_reserved1_ALIGN 0 #define MISC3_BIST_CTRL_reserved1_BITS 6 #define MISC3_BIST_CTRL_reserved1_SHIFT 6 /* MISC3 :: BIST_CTRL :: MBIST_SETUP [05:04] */ #define MISC3_BIST_CTRL_MBIST_SETUP_MASK 0x00000030 #define MISC3_BIST_CTRL_MBIST_SETUP_ALIGN 0 #define MISC3_BIST_CTRL_MBIST_SETUP_BITS 2 #define MISC3_BIST_CTRL_MBIST_SETUP_SHIFT 4 /* MISC3 :: BIST_CTRL :: reserved2 [03:01] */ #define MISC3_BIST_CTRL_reserved2_MASK 0x0000000e #define MISC3_BIST_CTRL_reserved2_ALIGN 0 #define MISC3_BIST_CTRL_reserved2_BITS 3 #define MISC3_BIST_CTRL_reserved2_SHIFT 1 /* MISC3 :: BIST_CTRL :: MBIST_ASYNC_RESET [00:00] */ #define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_MASK 0x00000001 #define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_ALIGN 0 #define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_BITS 1 #define MISC3_BIST_CTRL_MBIST_ASYNC_RESET_SHIFT 0 /**************************************************************************** * MISC3 :: BIST_STATUS ***************************************************************************/ /* MISC3 :: BIST_STATUS :: reserved0 [31:31] */ #define MISC3_BIST_STATUS_reserved0_MASK 0x80000000 #define MISC3_BIST_STATUS_reserved0_ALIGN 0 #define MISC3_BIST_STATUS_reserved0_BITS 1 #define MISC3_BIST_STATUS_reserved0_SHIFT 31 /* MISC3 :: BIST_STATUS :: MBIST_GO_2 [30:30] */ #define MISC3_BIST_STATUS_MBIST_GO_2_MASK 0x40000000 #define MISC3_BIST_STATUS_MBIST_GO_2_ALIGN 0 #define MISC3_BIST_STATUS_MBIST_GO_2_BITS 1 #define MISC3_BIST_STATUS_MBIST_GO_2_SHIFT 30 /* MISC3 :: BIST_STATUS :: MBIST_GO_1 [29:29] */ #define MISC3_BIST_STATUS_MBIST_GO_1_MASK 0x20000000 #define MISC3_BIST_STATUS_MBIST_GO_1_ALIGN 0 #define MISC3_BIST_STATUS_MBIST_GO_1_BITS 1 #define MISC3_BIST_STATUS_MBIST_GO_1_SHIFT 29 /* MISC3 :: BIST_STATUS :: MBIST_GO_0 [28:28] */ #define MISC3_BIST_STATUS_MBIST_GO_0_MASK 0x10000000 #define MISC3_BIST_STATUS_MBIST_GO_0_ALIGN 0 #define MISC3_BIST_STATUS_MBIST_GO_0_BITS 1 #define MISC3_BIST_STATUS_MBIST_GO_0_SHIFT 28 /* MISC3 :: BIST_STATUS :: reserved1 [27:27] */ #define MISC3_BIST_STATUS_reserved1_MASK 0x08000000 #define MISC3_BIST_STATUS_reserved1_ALIGN 0 #define MISC3_BIST_STATUS_reserved1_BITS 1 #define MISC3_BIST_STATUS_reserved1_SHIFT 27 /* MISC3 :: BIST_STATUS :: MBIST_DONE_2 [26:26] */ #define MISC3_BIST_STATUS_MBIST_DONE_2_MASK 0x04000000 #define MISC3_BIST_STATUS_MBIST_DONE_2_ALIGN 0 #define MISC3_BIST_STATUS_MBIST_DONE_2_BITS 1 #define MISC3_BIST_STATUS_MBIST_DONE_2_SHIFT 26 /* MISC3 :: BIST_STATUS :: MBIST_DONE_1 [25:25] */ #define MISC3_BIST_STATUS_MBIST_DONE_1_MASK 0x02000000 #define MISC3_BIST_STATUS_MBIST_DONE_1_ALIGN 0 #define MISC3_BIST_STATUS_MBIST_DONE_1_BITS 1 #define MISC3_BIST_STATUS_MBIST_DONE_1_SHIFT 25 /* MISC3 :: BIST_STATUS :: MBIST_DONE_0 [24:24] */ #define MISC3_BIST_STATUS_MBIST_DONE_0_MASK 0x01000000 #define MISC3_BIST_STATUS_MBIST_DONE_0_ALIGN 0 #define MISC3_BIST_STATUS_MBIST_DONE_0_BITS 1 #define MISC3_BIST_STATUS_MBIST_DONE_0_SHIFT 24 /* MISC3 :: BIST_STATUS :: reserved2 [23:06] */ #define MISC3_BIST_STATUS_reserved2_MASK 0x00ffffc0 #define MISC3_BIST_STATUS_reserved2_ALIGN 0 #define MISC3_BIST_STATUS_reserved2_BITS 18 #define MISC3_BIST_STATUS_reserved2_SHIFT 6 /* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_2 [05:04] */ #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_MASK 0x00000030 #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_ALIGN 0 #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_BITS 2 #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_2_SHIFT 4 /* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_1 [03:02] */ #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_MASK 0x0000000c #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_ALIGN 0 #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_BITS 2 #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_1_SHIFT 2 /* MISC3 :: BIST_STATUS :: MBIST_MBIST_MEMORY_GO_0 [01:00] */ #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_MASK 0x00000003 #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_ALIGN 0 #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_BITS 2 #define MISC3_BIST_STATUS_MBIST_MBIST_MEMORY_GO_0_SHIFT 0 /**************************************************************************** * MISC3 :: RX_CHECKSUM ***************************************************************************/ /* MISC3 :: RX_CHECKSUM :: RX_CHECKSUM [31:00] */ #define MISC3_RX_CHECKSUM_RX_CHECKSUM_MASK 0xffffffff #define MISC3_RX_CHECKSUM_RX_CHECKSUM_ALIGN 0 #define MISC3_RX_CHECKSUM_RX_CHECKSUM_BITS 32 #define MISC3_RX_CHECKSUM_RX_CHECKSUM_SHIFT 0 /**************************************************************************** * MISC3 :: TX_CHECKSUM ***************************************************************************/ /* MISC3 :: TX_CHECKSUM :: TX_CHECKSUM [31:00] */ #define MISC3_TX_CHECKSUM_TX_CHECKSUM_MASK 0xffffffff #define MISC3_TX_CHECKSUM_TX_CHECKSUM_ALIGN 0 #define MISC3_TX_CHECKSUM_TX_CHECKSUM_BITS 32 #define MISC3_TX_CHECKSUM_TX_CHECKSUM_SHIFT 0 /**************************************************************************** * MISC3 :: ECO_CTRL_CORE ***************************************************************************/ /* MISC3 :: ECO_CTRL_CORE :: reserved0 [31:16] */ #define MISC3_ECO_CTRL_CORE_reserved0_MASK 0xffff0000 #define MISC3_ECO_CTRL_CORE_reserved0_ALIGN 0 #define MISC3_ECO_CTRL_CORE_reserved0_BITS 16 #define MISC3_ECO_CTRL_CORE_reserved0_SHIFT 16 /* MISC3 :: ECO_CTRL_CORE :: ECO_CORE_RST_N [15:00] */ #define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_MASK 0x0000ffff #define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_ALIGN 0 #define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_BITS 16 #define MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_SHIFT 0 /**************************************************************************** * MISC3 :: CSI_TEST_CTRL ***************************************************************************/ /* MISC3 :: CSI_TEST_CTRL :: ENABLE_CSI_TEST [31:31] */ #define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_MASK 0x80000000 #define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_ALIGN 0 #define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_BITS 1 #define MISC3_CSI_TEST_CTRL_ENABLE_CSI_TEST_SHIFT 31 /* MISC3 :: CSI_TEST_CTRL :: reserved0 [30:24] */ #define MISC3_CSI_TEST_CTRL_reserved0_MASK 0x7f000000 #define MISC3_CSI_TEST_CTRL_reserved0_ALIGN 0 #define MISC3_CSI_TEST_CTRL_reserved0_BITS 7 #define MISC3_CSI_TEST_CTRL_reserved0_SHIFT 24 /* MISC3 :: CSI_TEST_CTRL :: CSI_CLOCK_ENABLE [23:16] */ #define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_MASK 0x00ff0000 #define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_ALIGN 0 #define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_BITS 8 #define MISC3_CSI_TEST_CTRL_CSI_CLOCK_ENABLE_SHIFT 16 /* MISC3 :: CSI_TEST_CTRL :: CSI_SYNC [15:08] */ #define MISC3_CSI_TEST_CTRL_CSI_SYNC_MASK 0x0000ff00 #define MISC3_CSI_TEST_CTRL_CSI_SYNC_ALIGN 0 #define MISC3_CSI_TEST_CTRL_CSI_SYNC_BITS 8 #define MISC3_CSI_TEST_CTRL_CSI_SYNC_SHIFT 8 /* MISC3 :: CSI_TEST_CTRL :: CSI_DATA [07:00] */ #define MISC3_CSI_TEST_CTRL_CSI_DATA_MASK 0x000000ff #define MISC3_CSI_TEST_CTRL_CSI_DATA_ALIGN 0 #define MISC3_CSI_TEST_CTRL_CSI_DATA_BITS 8 #define MISC3_CSI_TEST_CTRL_CSI_DATA_SHIFT 0 /**************************************************************************** * MISC3 :: HD_DVI_TEST_CTRL ***************************************************************************/ /* MISC3 :: HD_DVI_TEST_CTRL :: reserved0 [31:25] */ #define MISC3_HD_DVI_TEST_CTRL_reserved0_MASK 0xfe000000 #define MISC3_HD_DVI_TEST_CTRL_reserved0_ALIGN 0 #define MISC3_HD_DVI_TEST_CTRL_reserved0_BITS 7 #define MISC3_HD_DVI_TEST_CTRL_reserved0_SHIFT 25 /* MISC3 :: HD_DVI_TEST_CTRL :: POS_VIDO_VBLANK_N [24:24] */ #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_MASK 0x01000000 #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_ALIGN 0 #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_BITS 1 #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_VBLANK_N_SHIFT 24 /* MISC3 :: HD_DVI_TEST_CTRL :: NEG_VIDO_DVI_DATA [23:12] */ #define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_MASK 0x00fff000 #define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_ALIGN 0 #define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_BITS 12 #define MISC3_HD_DVI_TEST_CTRL_NEG_VIDO_DVI_DATA_SHIFT 12 /* MISC3 :: HD_DVI_TEST_CTRL :: POS_VIDO_DVI_DATA [11:00] */ #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_MASK 0x00000fff #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_ALIGN 0 #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_BITS 12 #define MISC3_HD_DVI_TEST_CTRL_POS_VIDO_DVI_DATA_SHIFT 0 /**************************************************************************** * BCM70012_MISC_TOP_MISC_PERST ***************************************************************************/ /**************************************************************************** * MISC_PERST :: ECO_CTRL_PERST ***************************************************************************/ /* MISC_PERST :: ECO_CTRL_PERST :: reserved0 [31:16] */ #define MISC_PERST_ECO_CTRL_PERST_reserved0_MASK 0xffff0000 #define MISC_PERST_ECO_CTRL_PERST_reserved0_ALIGN 0 #define MISC_PERST_ECO_CTRL_PERST_reserved0_BITS 16 #define MISC_PERST_ECO_CTRL_PERST_reserved0_SHIFT 16 /* MISC_PERST :: ECO_CTRL_PERST :: ECO_PERST_N [15:00] */ #define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_MASK 0x0000ffff #define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_ALIGN 0 #define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_BITS 16 #define MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_SHIFT 0 /**************************************************************************** * MISC_PERST :: DECODER_CTRL ***************************************************************************/ /* MISC_PERST :: DECODER_CTRL :: reserved0 [31:05] */ #define MISC_PERST_DECODER_CTRL_reserved0_MASK 0xffffffe0 #define MISC_PERST_DECODER_CTRL_reserved0_ALIGN 0 #define MISC_PERST_DECODER_CTRL_reserved0_BITS 27 #define MISC_PERST_DECODER_CTRL_reserved0_SHIFT 5 /* MISC_PERST :: DECODER_CTRL :: STOP_BCM7412_CLK [04:04] */ #define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_MASK 0x00000010 #define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_ALIGN 0 #define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_BITS 1 #define MISC_PERST_DECODER_CTRL_STOP_BCM7412_CLK_SHIFT 4 /* MISC_PERST :: DECODER_CTRL :: reserved1 [03:01] */ #define MISC_PERST_DECODER_CTRL_reserved1_MASK 0x0000000e #define MISC_PERST_DECODER_CTRL_reserved1_ALIGN 0 #define MISC_PERST_DECODER_CTRL_reserved1_BITS 3 #define MISC_PERST_DECODER_CTRL_reserved1_SHIFT 1 /* MISC_PERST :: DECODER_CTRL :: BCM7412_RESET [00:00] */ #define MISC_PERST_DECODER_CTRL_BCM7412_RESET_MASK 0x00000001 #define MISC_PERST_DECODER_CTRL_BCM7412_RESET_ALIGN 0 #define MISC_PERST_DECODER_CTRL_BCM7412_RESET_BITS 1 #define MISC_PERST_DECODER_CTRL_BCM7412_RESET_SHIFT 0 /**************************************************************************** * MISC_PERST :: CCE_STATUS ***************************************************************************/ /* MISC_PERST :: CCE_STATUS :: CCE_DONE [31:31] */ #define MISC_PERST_CCE_STATUS_CCE_DONE_MASK 0x80000000 #define MISC_PERST_CCE_STATUS_CCE_DONE_ALIGN 0 #define MISC_PERST_CCE_STATUS_CCE_DONE_BITS 1 #define MISC_PERST_CCE_STATUS_CCE_DONE_SHIFT 31 /* MISC_PERST :: CCE_STATUS :: reserved0 [30:03] */ #define MISC_PERST_CCE_STATUS_reserved0_MASK 0x7ffffff8 #define MISC_PERST_CCE_STATUS_reserved0_ALIGN 0 #define MISC_PERST_CCE_STATUS_reserved0_BITS 28 #define MISC_PERST_CCE_STATUS_reserved0_SHIFT 3 /* MISC_PERST :: CCE_STATUS :: CCE_BAD_GISB_ACCESS [02:02] */ #define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_MASK 0x00000004 #define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_ALIGN 0 #define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_BITS 1 #define MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_SHIFT 2 /* MISC_PERST :: CCE_STATUS :: CCE_BAD_I2C_ACCESS [01:01] */ #define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_MASK 0x00000002 #define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_ALIGN 0 #define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_BITS 1 #define MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_SHIFT 1 /* MISC_PERST :: CCE_STATUS :: CCE_BAD_SECTION_ID [00:00] */ #define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_MASK 0x00000001 #define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_ALIGN 0 #define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_BITS 1 #define MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_SHIFT 0 /**************************************************************************** * MISC_PERST :: PCIE_DEBUG ***************************************************************************/ /* MISC_PERST :: PCIE_DEBUG :: SERDES_TERM_CNT [31:16] */ #define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_MASK 0xffff0000 #define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_ALIGN 0 #define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_BITS 16 #define MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_SHIFT 16 /* MISC_PERST :: PCIE_DEBUG :: reserved0 [15:11] */ #define MISC_PERST_PCIE_DEBUG_reserved0_MASK 0x0000f800 #define MISC_PERST_PCIE_DEBUG_reserved0_ALIGN 0 #define MISC_PERST_PCIE_DEBUG_reserved0_BITS 5 #define MISC_PERST_PCIE_DEBUG_reserved0_SHIFT 11 /* MISC_PERST :: PCIE_DEBUG :: PLL_VCO_RESCUE [10:10] */ #define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_MASK 0x00000400 #define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_ALIGN 0 #define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_BITS 1 #define MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_SHIFT 10 /* MISC_PERST :: PCIE_DEBUG :: PLL_PDN_OVERRIDE [09:09] */ #define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_MASK 0x00000200 #define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_ALIGN 0 #define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_BITS 1 #define MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_SHIFT 9 /* MISC_PERST :: PCIE_DEBUG :: CORE_CLOCK_OVR [08:08] */ #define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_MASK 0x00000100 #define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_ALIGN 0 #define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_BITS 1 #define MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_SHIFT 8 /* MISC_PERST :: PCIE_DEBUG :: reserved1 [07:04] */ #define MISC_PERST_PCIE_DEBUG_reserved1_MASK 0x000000f0 #define MISC_PERST_PCIE_DEBUG_reserved1_ALIGN 0 #define MISC_PERST_PCIE_DEBUG_reserved1_BITS 4 #define MISC_PERST_PCIE_DEBUG_reserved1_SHIFT 4 /* MISC_PERST :: PCIE_DEBUG :: PCIE_TMUX_SEL [03:00] */ #define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_MASK 0x0000000f #define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_ALIGN 0 #define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_BITS 4 #define MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_SHIFT 0 /**************************************************************************** * MISC_PERST :: PCIE_DEBUG_STATUS ***************************************************************************/ /* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved0 [31:06] */ #define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_MASK 0xffffffc0 #define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_ALIGN 0 #define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_BITS 26 #define MISC_PERST_PCIE_DEBUG_STATUS_reserved0_SHIFT 6 /* MISC_PERST :: PCIE_DEBUG_STATUS :: DATALINKATTN [05:05] */ #define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_MASK 0x00000020 #define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_ALIGN 0 #define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_BITS 1 #define MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_SHIFT 5 /* MISC_PERST :: PCIE_DEBUG_STATUS :: PHYLINKATTN [04:04] */ #define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_MASK 0x00000010 #define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_ALIGN 0 #define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_BITS 1 #define MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_SHIFT 4 /* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved1 [03:02] */ #define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_MASK 0x0000000c #define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_ALIGN 0 #define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_BITS 2 #define MISC_PERST_PCIE_DEBUG_STATUS_reserved1_SHIFT 2 /* MISC_PERST :: PCIE_DEBUG_STATUS :: DATA_LINKUP [01:01] */ #define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_MASK 0x00000002 #define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_ALIGN 0 #define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_BITS 1 #define MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_SHIFT 1 /* MISC_PERST :: PCIE_DEBUG_STATUS :: PHY_LINKUP [00:00] */ #define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_MASK 0x00000001 #define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_ALIGN 0 #define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_BITS 1 #define MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_SHIFT 0 /**************************************************************************** * MISC_PERST :: VREG_CTRL ***************************************************************************/ /* MISC_PERST :: VREG_CTRL :: reserved0 [31:08] */ #define MISC_PERST_VREG_CTRL_reserved0_MASK 0xffffff00 #define MISC_PERST_VREG_CTRL_reserved0_ALIGN 0 #define MISC_PERST_VREG_CTRL_reserved0_BITS 24 #define MISC_PERST_VREG_CTRL_reserved0_SHIFT 8 /* MISC_PERST :: VREG_CTRL :: VREG1P2_SEL [07:04] */ #define MISC_PERST_VREG_CTRL_VREG1P2_SEL_MASK 0x000000f0 #define MISC_PERST_VREG_CTRL_VREG1P2_SEL_ALIGN 0 #define MISC_PERST_VREG_CTRL_VREG1P2_SEL_BITS 4 #define MISC_PERST_VREG_CTRL_VREG1P2_SEL_SHIFT 4 /* MISC_PERST :: VREG_CTRL :: VREG2P5_SEL [03:00] */ #define MISC_PERST_VREG_CTRL_VREG2P5_SEL_MASK 0x0000000f #define MISC_PERST_VREG_CTRL_VREG2P5_SEL_ALIGN 0 #define MISC_PERST_VREG_CTRL_VREG2P5_SEL_BITS 4 #define MISC_PERST_VREG_CTRL_VREG2P5_SEL_SHIFT 0 /**************************************************************************** * MISC_PERST :: MEM_CTRL ***************************************************************************/ /* MISC_PERST :: MEM_CTRL :: reserved0 [31:04] */ #define MISC_PERST_MEM_CTRL_reserved0_MASK 0xfffffff0 #define MISC_PERST_MEM_CTRL_reserved0_ALIGN 0 #define MISC_PERST_MEM_CTRL_reserved0_BITS 28 #define MISC_PERST_MEM_CTRL_reserved0_SHIFT 4 /* MISC_PERST :: MEM_CTRL :: Y_RM [03:03] */ #define MISC_PERST_MEM_CTRL_Y_RM_MASK 0x00000008 #define MISC_PERST_MEM_CTRL_Y_RM_ALIGN 0 #define MISC_PERST_MEM_CTRL_Y_RM_BITS 1 #define MISC_PERST_MEM_CTRL_Y_RM_SHIFT 3 /* MISC_PERST :: MEM_CTRL :: Y_CCM [02:02] */ #define MISC_PERST_MEM_CTRL_Y_CCM_MASK 0x00000004 #define MISC_PERST_MEM_CTRL_Y_CCM_ALIGN 0 #define MISC_PERST_MEM_CTRL_Y_CCM_BITS 1 #define MISC_PERST_MEM_CTRL_Y_CCM_SHIFT 2 /* MISC_PERST :: MEM_CTRL :: UV_RM [01:01] */ #define MISC_PERST_MEM_CTRL_UV_RM_MASK 0x00000002 #define MISC_PERST_MEM_CTRL_UV_RM_ALIGN 0 #define MISC_PERST_MEM_CTRL_UV_RM_BITS 1 #define MISC_PERST_MEM_CTRL_UV_RM_SHIFT 1 /* MISC_PERST :: MEM_CTRL :: UV_CCM [00:00] */ #define MISC_PERST_MEM_CTRL_UV_CCM_MASK 0x00000001 #define MISC_PERST_MEM_CTRL_UV_CCM_ALIGN 0 #define MISC_PERST_MEM_CTRL_UV_CCM_BITS 1 #define MISC_PERST_MEM_CTRL_UV_CCM_SHIFT 0 /**************************************************************************** * MISC_PERST :: CLOCK_CTRL ***************************************************************************/ /* MISC_PERST :: CLOCK_CTRL :: reserved0 [31:20] */ #define MISC_PERST_CLOCK_CTRL_reserved0_MASK 0xfff00000 #define MISC_PERST_CLOCK_CTRL_reserved0_ALIGN 0 #define MISC_PERST_CLOCK_CTRL_reserved0_BITS 12 #define MISC_PERST_CLOCK_CTRL_reserved0_SHIFT 20 /* MISC_PERST :: CLOCK_CTRL :: PLL_DIV [19:16] */ #define MISC_PERST_CLOCK_CTRL_PLL_DIV_MASK 0x000f0000 #define MISC_PERST_CLOCK_CTRL_PLL_DIV_ALIGN 0 #define MISC_PERST_CLOCK_CTRL_PLL_DIV_BITS 4 #define MISC_PERST_CLOCK_CTRL_PLL_DIV_SHIFT 16 /* MISC_PERST :: CLOCK_CTRL :: PLL_MULT [15:08] */ #define MISC_PERST_CLOCK_CTRL_PLL_MULT_MASK 0x0000ff00 #define MISC_PERST_CLOCK_CTRL_PLL_MULT_ALIGN 0 #define MISC_PERST_CLOCK_CTRL_PLL_MULT_BITS 8 #define MISC_PERST_CLOCK_CTRL_PLL_MULT_SHIFT 8 /* MISC_PERST :: CLOCK_CTRL :: reserved1 [07:03] */ #define MISC_PERST_CLOCK_CTRL_reserved1_MASK 0x000000f8 #define MISC_PERST_CLOCK_CTRL_reserved1_ALIGN 0 #define MISC_PERST_CLOCK_CTRL_reserved1_BITS 5 #define MISC_PERST_CLOCK_CTRL_reserved1_SHIFT 3 /* MISC_PERST :: CLOCK_CTRL :: PLL_PWRDOWN [02:02] */ #define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_MASK 0x00000004 #define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_ALIGN 0 #define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_BITS 1 #define MISC_PERST_CLOCK_CTRL_PLL_PWRDOWN_SHIFT 2 /* MISC_PERST :: CLOCK_CTRL :: STOP_CORE_CLK [01:01] */ #define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_MASK 0x00000002 #define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_ALIGN 0 #define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_BITS 1 #define MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_SHIFT 1 /* MISC_PERST :: CLOCK_CTRL :: SEL_ALT_CLK [00:00] */ #define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_MASK 0x00000001 #define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_ALIGN 0 #define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_BITS 1 #define MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_SHIFT 0 /**************************************************************************** * BCM70012_MISC_TOP_GISB_ARBITER ***************************************************************************/ /**************************************************************************** * GISB_ARBITER :: REVISION ***************************************************************************/ /* GISB_ARBITER :: REVISION :: reserved0 [31:16] */ #define GISB_ARBITER_REVISION_reserved0_MASK 0xffff0000 #define GISB_ARBITER_REVISION_reserved0_ALIGN 0 #define GISB_ARBITER_REVISION_reserved0_BITS 16 #define GISB_ARBITER_REVISION_reserved0_SHIFT 16 /* GISB_ARBITER :: REVISION :: MAJOR [15:08] */ #define GISB_ARBITER_REVISION_MAJOR_MASK 0x0000ff00 #define GISB_ARBITER_REVISION_MAJOR_ALIGN 0 #define GISB_ARBITER_REVISION_MAJOR_BITS 8 #define GISB_ARBITER_REVISION_MAJOR_SHIFT 8 /* GISB_ARBITER :: REVISION :: MINOR [07:00] */ #define GISB_ARBITER_REVISION_MINOR_MASK 0x000000ff #define GISB_ARBITER_REVISION_MINOR_ALIGN 0 #define GISB_ARBITER_REVISION_MINOR_BITS 8 #define GISB_ARBITER_REVISION_MINOR_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: SCRATCH ***************************************************************************/ /* GISB_ARBITER :: SCRATCH :: scratch_bit [31:00] */ #define GISB_ARBITER_SCRATCH_scratch_bit_MASK 0xffffffff #define GISB_ARBITER_SCRATCH_scratch_bit_ALIGN 0 #define GISB_ARBITER_SCRATCH_scratch_bit_BITS 32 #define GISB_ARBITER_SCRATCH_scratch_bit_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: REQ_MASK ***************************************************************************/ /* GISB_ARBITER :: REQ_MASK :: reserved0 [31:06] */ #define GISB_ARBITER_REQ_MASK_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_REQ_MASK_reserved0_ALIGN 0 #define GISB_ARBITER_REQ_MASK_reserved0_BITS 26 #define GISB_ARBITER_REQ_MASK_reserved0_SHIFT 6 /* GISB_ARBITER :: REQ_MASK :: bsp [05:05] */ #define GISB_ARBITER_REQ_MASK_bsp_MASK 0x00000020 #define GISB_ARBITER_REQ_MASK_bsp_ALIGN 0 #define GISB_ARBITER_REQ_MASK_bsp_BITS 1 #define GISB_ARBITER_REQ_MASK_bsp_SHIFT 5 #define GISB_ARBITER_REQ_MASK_bsp_UNMASK 0 /* GISB_ARBITER :: REQ_MASK :: tgt [04:04] */ #define GISB_ARBITER_REQ_MASK_tgt_MASK 0x00000010 #define GISB_ARBITER_REQ_MASK_tgt_ALIGN 0 #define GISB_ARBITER_REQ_MASK_tgt_BITS 1 #define GISB_ARBITER_REQ_MASK_tgt_SHIFT 4 #define GISB_ARBITER_REQ_MASK_tgt_UNMASK 0 /* GISB_ARBITER :: REQ_MASK :: aes [03:03] */ #define GISB_ARBITER_REQ_MASK_aes_MASK 0x00000008 #define GISB_ARBITER_REQ_MASK_aes_ALIGN 0 #define GISB_ARBITER_REQ_MASK_aes_BITS 1 #define GISB_ARBITER_REQ_MASK_aes_SHIFT 3 #define GISB_ARBITER_REQ_MASK_aes_UNMASK 0 /* GISB_ARBITER :: REQ_MASK :: dci [02:02] */ #define GISB_ARBITER_REQ_MASK_dci_MASK 0x00000004 #define GISB_ARBITER_REQ_MASK_dci_ALIGN 0 #define GISB_ARBITER_REQ_MASK_dci_BITS 1 #define GISB_ARBITER_REQ_MASK_dci_SHIFT 2 #define GISB_ARBITER_REQ_MASK_dci_UNMASK 0 /* GISB_ARBITER :: REQ_MASK :: cce [01:01] */ #define GISB_ARBITER_REQ_MASK_cce_MASK 0x00000002 #define GISB_ARBITER_REQ_MASK_cce_ALIGN 0 #define GISB_ARBITER_REQ_MASK_cce_BITS 1 #define GISB_ARBITER_REQ_MASK_cce_SHIFT 1 #define GISB_ARBITER_REQ_MASK_cce_UNMASK 0 /* GISB_ARBITER :: REQ_MASK :: dbu [00:00] */ #define GISB_ARBITER_REQ_MASK_dbu_MASK 0x00000001 #define GISB_ARBITER_REQ_MASK_dbu_ALIGN 0 #define GISB_ARBITER_REQ_MASK_dbu_BITS 1 #define GISB_ARBITER_REQ_MASK_dbu_SHIFT 0 #define GISB_ARBITER_REQ_MASK_dbu_UNMASK 0 /**************************************************************************** * GISB_ARBITER :: TIMER ***************************************************************************/ /* GISB_ARBITER :: TIMER :: hi_count [31:16] */ #define GISB_ARBITER_TIMER_hi_count_MASK 0xffff0000 #define GISB_ARBITER_TIMER_hi_count_ALIGN 0 #define GISB_ARBITER_TIMER_hi_count_BITS 16 #define GISB_ARBITER_TIMER_hi_count_SHIFT 16 /* GISB_ARBITER :: TIMER :: lo_count [15:00] */ #define GISB_ARBITER_TIMER_lo_count_MASK 0x0000ffff #define GISB_ARBITER_TIMER_lo_count_ALIGN 0 #define GISB_ARBITER_TIMER_lo_count_BITS 16 #define GISB_ARBITER_TIMER_lo_count_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_CTRL ***************************************************************************/ /* GISB_ARBITER :: BP_CTRL :: reserved0 [31:02] */ #define GISB_ARBITER_BP_CTRL_reserved0_MASK 0xfffffffc #define GISB_ARBITER_BP_CTRL_reserved0_ALIGN 0 #define GISB_ARBITER_BP_CTRL_reserved0_BITS 30 #define GISB_ARBITER_BP_CTRL_reserved0_SHIFT 2 /* GISB_ARBITER :: BP_CTRL :: breakpoint_tea [01:01] */ #define GISB_ARBITER_BP_CTRL_breakpoint_tea_MASK 0x00000002 #define GISB_ARBITER_BP_CTRL_breakpoint_tea_ALIGN 0 #define GISB_ARBITER_BP_CTRL_breakpoint_tea_BITS 1 #define GISB_ARBITER_BP_CTRL_breakpoint_tea_SHIFT 1 #define GISB_ARBITER_BP_CTRL_breakpoint_tea_DISABLE 0 #define GISB_ARBITER_BP_CTRL_breakpoint_tea_ENABLE 1 /* GISB_ARBITER :: BP_CTRL :: repeat_capture [00:00] */ #define GISB_ARBITER_BP_CTRL_repeat_capture_MASK 0x00000001 #define GISB_ARBITER_BP_CTRL_repeat_capture_ALIGN 0 #define GISB_ARBITER_BP_CTRL_repeat_capture_BITS 1 #define GISB_ARBITER_BP_CTRL_repeat_capture_SHIFT 0 #define GISB_ARBITER_BP_CTRL_repeat_capture_DISABLE 0 #define GISB_ARBITER_BP_CTRL_repeat_capture_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_CAP_CLR ***************************************************************************/ /* GISB_ARBITER :: BP_CAP_CLR :: reserved0 [31:01] */ #define GISB_ARBITER_BP_CAP_CLR_reserved0_MASK 0xfffffffe #define GISB_ARBITER_BP_CAP_CLR_reserved0_ALIGN 0 #define GISB_ARBITER_BP_CAP_CLR_reserved0_BITS 31 #define GISB_ARBITER_BP_CAP_CLR_reserved0_SHIFT 1 /* GISB_ARBITER :: BP_CAP_CLR :: clear [00:00] */ #define GISB_ARBITER_BP_CAP_CLR_clear_MASK 0x00000001 #define GISB_ARBITER_BP_CAP_CLR_clear_ALIGN 0 #define GISB_ARBITER_BP_CAP_CLR_clear_BITS 1 #define GISB_ARBITER_BP_CAP_CLR_clear_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_START_ADDR_0 ***************************************************************************/ /* GISB_ARBITER :: BP_START_ADDR_0 :: start [31:00] */ #define GISB_ARBITER_BP_START_ADDR_0_start_MASK 0xffffffff #define GISB_ARBITER_BP_START_ADDR_0_start_ALIGN 0 #define GISB_ARBITER_BP_START_ADDR_0_start_BITS 32 #define GISB_ARBITER_BP_START_ADDR_0_start_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_END_ADDR_0 ***************************************************************************/ /* GISB_ARBITER :: BP_END_ADDR_0 :: end [31:00] */ #define GISB_ARBITER_BP_END_ADDR_0_end_MASK 0xffffffff #define GISB_ARBITER_BP_END_ADDR_0_end_ALIGN 0 #define GISB_ARBITER_BP_END_ADDR_0_end_BITS 32 #define GISB_ARBITER_BP_END_ADDR_0_end_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_READ_0 ***************************************************************************/ /* GISB_ARBITER :: BP_READ_0 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_READ_0_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_READ_0_reserved0_ALIGN 0 #define GISB_ARBITER_BP_READ_0_reserved0_BITS 26 #define GISB_ARBITER_BP_READ_0_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_READ_0 :: bsp [05:05] */ #define GISB_ARBITER_BP_READ_0_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_READ_0_bsp_ALIGN 0 #define GISB_ARBITER_BP_READ_0_bsp_BITS 1 #define GISB_ARBITER_BP_READ_0_bsp_SHIFT 5 #define GISB_ARBITER_BP_READ_0_bsp_DISABLE 0 #define GISB_ARBITER_BP_READ_0_bsp_ENABLE 1 /* GISB_ARBITER :: BP_READ_0 :: aes [04:04] */ #define GISB_ARBITER_BP_READ_0_aes_MASK 0x00000010 #define GISB_ARBITER_BP_READ_0_aes_ALIGN 0 #define GISB_ARBITER_BP_READ_0_aes_BITS 1 #define GISB_ARBITER_BP_READ_0_aes_SHIFT 4 #define GISB_ARBITER_BP_READ_0_aes_DISABLE 0 #define GISB_ARBITER_BP_READ_0_aes_ENABLE 1 /* GISB_ARBITER :: BP_READ_0 :: fve [03:03] */ #define GISB_ARBITER_BP_READ_0_fve_MASK 0x00000008 #define GISB_ARBITER_BP_READ_0_fve_ALIGN 0 #define GISB_ARBITER_BP_READ_0_fve_BITS 1 #define GISB_ARBITER_BP_READ_0_fve_SHIFT 3 #define GISB_ARBITER_BP_READ_0_fve_DISABLE 0 #define GISB_ARBITER_BP_READ_0_fve_ENABLE 1 /* GISB_ARBITER :: BP_READ_0 :: tgt [02:02] */ #define GISB_ARBITER_BP_READ_0_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_READ_0_tgt_ALIGN 0 #define GISB_ARBITER_BP_READ_0_tgt_BITS 1 #define GISB_ARBITER_BP_READ_0_tgt_SHIFT 2 #define GISB_ARBITER_BP_READ_0_tgt_DISABLE 0 #define GISB_ARBITER_BP_READ_0_tgt_ENABLE 1 /* GISB_ARBITER :: BP_READ_0 :: dbu [01:01] */ #define GISB_ARBITER_BP_READ_0_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_READ_0_dbu_ALIGN 0 #define GISB_ARBITER_BP_READ_0_dbu_BITS 1 #define GISB_ARBITER_BP_READ_0_dbu_SHIFT 1 #define GISB_ARBITER_BP_READ_0_dbu_DISABLE 0 #define GISB_ARBITER_BP_READ_0_dbu_ENABLE 1 /* GISB_ARBITER :: BP_READ_0 :: cce [00:00] */ #define GISB_ARBITER_BP_READ_0_cce_MASK 0x00000001 #define GISB_ARBITER_BP_READ_0_cce_ALIGN 0 #define GISB_ARBITER_BP_READ_0_cce_BITS 1 #define GISB_ARBITER_BP_READ_0_cce_SHIFT 0 #define GISB_ARBITER_BP_READ_0_cce_DISABLE 0 #define GISB_ARBITER_BP_READ_0_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_WRITE_0 ***************************************************************************/ /* GISB_ARBITER :: BP_WRITE_0 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_WRITE_0_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_WRITE_0_reserved0_ALIGN 0 #define GISB_ARBITER_BP_WRITE_0_reserved0_BITS 26 #define GISB_ARBITER_BP_WRITE_0_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_WRITE_0 :: bsp [05:05] */ #define GISB_ARBITER_BP_WRITE_0_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_WRITE_0_bsp_ALIGN 0 #define GISB_ARBITER_BP_WRITE_0_bsp_BITS 1 #define GISB_ARBITER_BP_WRITE_0_bsp_SHIFT 5 #define GISB_ARBITER_BP_WRITE_0_bsp_DISABLE 0 #define GISB_ARBITER_BP_WRITE_0_bsp_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_0 :: aes [04:04] */ #define GISB_ARBITER_BP_WRITE_0_aes_MASK 0x00000010 #define GISB_ARBITER_BP_WRITE_0_aes_ALIGN 0 #define GISB_ARBITER_BP_WRITE_0_aes_BITS 1 #define GISB_ARBITER_BP_WRITE_0_aes_SHIFT 4 #define GISB_ARBITER_BP_WRITE_0_aes_DISABLE 0 #define GISB_ARBITER_BP_WRITE_0_aes_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_0 :: fve [03:03] */ #define GISB_ARBITER_BP_WRITE_0_fve_MASK 0x00000008 #define GISB_ARBITER_BP_WRITE_0_fve_ALIGN 0 #define GISB_ARBITER_BP_WRITE_0_fve_BITS 1 #define GISB_ARBITER_BP_WRITE_0_fve_SHIFT 3 #define GISB_ARBITER_BP_WRITE_0_fve_DISABLE 0 #define GISB_ARBITER_BP_WRITE_0_fve_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_0 :: tgt [02:02] */ #define GISB_ARBITER_BP_WRITE_0_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_WRITE_0_tgt_ALIGN 0 #define GISB_ARBITER_BP_WRITE_0_tgt_BITS 1 #define GISB_ARBITER_BP_WRITE_0_tgt_SHIFT 2 #define GISB_ARBITER_BP_WRITE_0_tgt_DISABLE 0 #define GISB_ARBITER_BP_WRITE_0_tgt_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_0 :: dbu [01:01] */ #define GISB_ARBITER_BP_WRITE_0_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_WRITE_0_dbu_ALIGN 0 #define GISB_ARBITER_BP_WRITE_0_dbu_BITS 1 #define GISB_ARBITER_BP_WRITE_0_dbu_SHIFT 1 #define GISB_ARBITER_BP_WRITE_0_dbu_DISABLE 0 #define GISB_ARBITER_BP_WRITE_0_dbu_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_0 :: cce [00:00] */ #define GISB_ARBITER_BP_WRITE_0_cce_MASK 0x00000001 #define GISB_ARBITER_BP_WRITE_0_cce_ALIGN 0 #define GISB_ARBITER_BP_WRITE_0_cce_BITS 1 #define GISB_ARBITER_BP_WRITE_0_cce_SHIFT 0 #define GISB_ARBITER_BP_WRITE_0_cce_DISABLE 0 #define GISB_ARBITER_BP_WRITE_0_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_ENABLE_0 ***************************************************************************/ /* GISB_ARBITER :: BP_ENABLE_0 :: reserved0 [31:03] */ #define GISB_ARBITER_BP_ENABLE_0_reserved0_MASK 0xfffffff8 #define GISB_ARBITER_BP_ENABLE_0_reserved0_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_0_reserved0_BITS 29 #define GISB_ARBITER_BP_ENABLE_0_reserved0_SHIFT 3 /* GISB_ARBITER :: BP_ENABLE_0 :: block [02:02] */ #define GISB_ARBITER_BP_ENABLE_0_block_MASK 0x00000004 #define GISB_ARBITER_BP_ENABLE_0_block_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_0_block_BITS 1 #define GISB_ARBITER_BP_ENABLE_0_block_SHIFT 2 #define GISB_ARBITER_BP_ENABLE_0_block_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_0_block_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_0 :: address [01:01] */ #define GISB_ARBITER_BP_ENABLE_0_address_MASK 0x00000002 #define GISB_ARBITER_BP_ENABLE_0_address_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_0_address_BITS 1 #define GISB_ARBITER_BP_ENABLE_0_address_SHIFT 1 #define GISB_ARBITER_BP_ENABLE_0_address_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_0_address_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_0 :: access [00:00] */ #define GISB_ARBITER_BP_ENABLE_0_access_MASK 0x00000001 #define GISB_ARBITER_BP_ENABLE_0_access_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_0_access_BITS 1 #define GISB_ARBITER_BP_ENABLE_0_access_SHIFT 0 #define GISB_ARBITER_BP_ENABLE_0_access_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_0_access_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_START_ADDR_1 ***************************************************************************/ /* GISB_ARBITER :: BP_START_ADDR_1 :: start [31:00] */ #define GISB_ARBITER_BP_START_ADDR_1_start_MASK 0xffffffff #define GISB_ARBITER_BP_START_ADDR_1_start_ALIGN 0 #define GISB_ARBITER_BP_START_ADDR_1_start_BITS 32 #define GISB_ARBITER_BP_START_ADDR_1_start_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_END_ADDR_1 ***************************************************************************/ /* GISB_ARBITER :: BP_END_ADDR_1 :: end [31:00] */ #define GISB_ARBITER_BP_END_ADDR_1_end_MASK 0xffffffff #define GISB_ARBITER_BP_END_ADDR_1_end_ALIGN 0 #define GISB_ARBITER_BP_END_ADDR_1_end_BITS 32 #define GISB_ARBITER_BP_END_ADDR_1_end_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_READ_1 ***************************************************************************/ /* GISB_ARBITER :: BP_READ_1 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_READ_1_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_READ_1_reserved0_ALIGN 0 #define GISB_ARBITER_BP_READ_1_reserved0_BITS 26 #define GISB_ARBITER_BP_READ_1_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_READ_1 :: bsp [05:05] */ #define GISB_ARBITER_BP_READ_1_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_READ_1_bsp_ALIGN 0 #define GISB_ARBITER_BP_READ_1_bsp_BITS 1 #define GISB_ARBITER_BP_READ_1_bsp_SHIFT 5 #define GISB_ARBITER_BP_READ_1_bsp_DISABLE 0 #define GISB_ARBITER_BP_READ_1_bsp_ENABLE 1 /* GISB_ARBITER :: BP_READ_1 :: aes [04:04] */ #define GISB_ARBITER_BP_READ_1_aes_MASK 0x00000010 #define GISB_ARBITER_BP_READ_1_aes_ALIGN 0 #define GISB_ARBITER_BP_READ_1_aes_BITS 1 #define GISB_ARBITER_BP_READ_1_aes_SHIFT 4 #define GISB_ARBITER_BP_READ_1_aes_DISABLE 0 #define GISB_ARBITER_BP_READ_1_aes_ENABLE 1 /* GISB_ARBITER :: BP_READ_1 :: fve [03:03] */ #define GISB_ARBITER_BP_READ_1_fve_MASK 0x00000008 #define GISB_ARBITER_BP_READ_1_fve_ALIGN 0 #define GISB_ARBITER_BP_READ_1_fve_BITS 1 #define GISB_ARBITER_BP_READ_1_fve_SHIFT 3 #define GISB_ARBITER_BP_READ_1_fve_DISABLE 0 #define GISB_ARBITER_BP_READ_1_fve_ENABLE 1 /* GISB_ARBITER :: BP_READ_1 :: tgt [02:02] */ #define GISB_ARBITER_BP_READ_1_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_READ_1_tgt_ALIGN 0 #define GISB_ARBITER_BP_READ_1_tgt_BITS 1 #define GISB_ARBITER_BP_READ_1_tgt_SHIFT 2 #define GISB_ARBITER_BP_READ_1_tgt_DISABLE 0 #define GISB_ARBITER_BP_READ_1_tgt_ENABLE 1 /* GISB_ARBITER :: BP_READ_1 :: dbu [01:01] */ #define GISB_ARBITER_BP_READ_1_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_READ_1_dbu_ALIGN 0 #define GISB_ARBITER_BP_READ_1_dbu_BITS 1 #define GISB_ARBITER_BP_READ_1_dbu_SHIFT 1 #define GISB_ARBITER_BP_READ_1_dbu_DISABLE 0 #define GISB_ARBITER_BP_READ_1_dbu_ENABLE 1 /* GISB_ARBITER :: BP_READ_1 :: cce [00:00] */ #define GISB_ARBITER_BP_READ_1_cce_MASK 0x00000001 #define GISB_ARBITER_BP_READ_1_cce_ALIGN 0 #define GISB_ARBITER_BP_READ_1_cce_BITS 1 #define GISB_ARBITER_BP_READ_1_cce_SHIFT 0 #define GISB_ARBITER_BP_READ_1_cce_DISABLE 0 #define GISB_ARBITER_BP_READ_1_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_WRITE_1 ***************************************************************************/ /* GISB_ARBITER :: BP_WRITE_1 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_WRITE_1_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_WRITE_1_reserved0_ALIGN 0 #define GISB_ARBITER_BP_WRITE_1_reserved0_BITS 26 #define GISB_ARBITER_BP_WRITE_1_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_WRITE_1 :: bsp [05:05] */ #define GISB_ARBITER_BP_WRITE_1_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_WRITE_1_bsp_ALIGN 0 #define GISB_ARBITER_BP_WRITE_1_bsp_BITS 1 #define GISB_ARBITER_BP_WRITE_1_bsp_SHIFT 5 #define GISB_ARBITER_BP_WRITE_1_bsp_DISABLE 0 #define GISB_ARBITER_BP_WRITE_1_bsp_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_1 :: aes [04:04] */ #define GISB_ARBITER_BP_WRITE_1_aes_MASK 0x00000010 #define GISB_ARBITER_BP_WRITE_1_aes_ALIGN 0 #define GISB_ARBITER_BP_WRITE_1_aes_BITS 1 #define GISB_ARBITER_BP_WRITE_1_aes_SHIFT 4 #define GISB_ARBITER_BP_WRITE_1_aes_DISABLE 0 #define GISB_ARBITER_BP_WRITE_1_aes_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_1 :: fve [03:03] */ #define GISB_ARBITER_BP_WRITE_1_fve_MASK 0x00000008 #define GISB_ARBITER_BP_WRITE_1_fve_ALIGN 0 #define GISB_ARBITER_BP_WRITE_1_fve_BITS 1 #define GISB_ARBITER_BP_WRITE_1_fve_SHIFT 3 #define GISB_ARBITER_BP_WRITE_1_fve_DISABLE 0 #define GISB_ARBITER_BP_WRITE_1_fve_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_1 :: tgt [02:02] */ #define GISB_ARBITER_BP_WRITE_1_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_WRITE_1_tgt_ALIGN 0 #define GISB_ARBITER_BP_WRITE_1_tgt_BITS 1 #define GISB_ARBITER_BP_WRITE_1_tgt_SHIFT 2 #define GISB_ARBITER_BP_WRITE_1_tgt_DISABLE 0 #define GISB_ARBITER_BP_WRITE_1_tgt_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_1 :: dbu [01:01] */ #define GISB_ARBITER_BP_WRITE_1_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_WRITE_1_dbu_ALIGN 0 #define GISB_ARBITER_BP_WRITE_1_dbu_BITS 1 #define GISB_ARBITER_BP_WRITE_1_dbu_SHIFT 1 #define GISB_ARBITER_BP_WRITE_1_dbu_DISABLE 0 #define GISB_ARBITER_BP_WRITE_1_dbu_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_1 :: cce [00:00] */ #define GISB_ARBITER_BP_WRITE_1_cce_MASK 0x00000001 #define GISB_ARBITER_BP_WRITE_1_cce_ALIGN 0 #define GISB_ARBITER_BP_WRITE_1_cce_BITS 1 #define GISB_ARBITER_BP_WRITE_1_cce_SHIFT 0 #define GISB_ARBITER_BP_WRITE_1_cce_DISABLE 0 #define GISB_ARBITER_BP_WRITE_1_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_ENABLE_1 ***************************************************************************/ /* GISB_ARBITER :: BP_ENABLE_1 :: reserved0 [31:03] */ #define GISB_ARBITER_BP_ENABLE_1_reserved0_MASK 0xfffffff8 #define GISB_ARBITER_BP_ENABLE_1_reserved0_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_1_reserved0_BITS 29 #define GISB_ARBITER_BP_ENABLE_1_reserved0_SHIFT 3 /* GISB_ARBITER :: BP_ENABLE_1 :: block [02:02] */ #define GISB_ARBITER_BP_ENABLE_1_block_MASK 0x00000004 #define GISB_ARBITER_BP_ENABLE_1_block_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_1_block_BITS 1 #define GISB_ARBITER_BP_ENABLE_1_block_SHIFT 2 #define GISB_ARBITER_BP_ENABLE_1_block_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_1_block_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_1 :: address [01:01] */ #define GISB_ARBITER_BP_ENABLE_1_address_MASK 0x00000002 #define GISB_ARBITER_BP_ENABLE_1_address_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_1_address_BITS 1 #define GISB_ARBITER_BP_ENABLE_1_address_SHIFT 1 #define GISB_ARBITER_BP_ENABLE_1_address_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_1_address_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_1 :: access [00:00] */ #define GISB_ARBITER_BP_ENABLE_1_access_MASK 0x00000001 #define GISB_ARBITER_BP_ENABLE_1_access_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_1_access_BITS 1 #define GISB_ARBITER_BP_ENABLE_1_access_SHIFT 0 #define GISB_ARBITER_BP_ENABLE_1_access_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_1_access_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_START_ADDR_2 ***************************************************************************/ /* GISB_ARBITER :: BP_START_ADDR_2 :: start [31:00] */ #define GISB_ARBITER_BP_START_ADDR_2_start_MASK 0xffffffff #define GISB_ARBITER_BP_START_ADDR_2_start_ALIGN 0 #define GISB_ARBITER_BP_START_ADDR_2_start_BITS 32 #define GISB_ARBITER_BP_START_ADDR_2_start_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_END_ADDR_2 ***************************************************************************/ /* GISB_ARBITER :: BP_END_ADDR_2 :: end [31:00] */ #define GISB_ARBITER_BP_END_ADDR_2_end_MASK 0xffffffff #define GISB_ARBITER_BP_END_ADDR_2_end_ALIGN 0 #define GISB_ARBITER_BP_END_ADDR_2_end_BITS 32 #define GISB_ARBITER_BP_END_ADDR_2_end_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_READ_2 ***************************************************************************/ /* GISB_ARBITER :: BP_READ_2 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_READ_2_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_READ_2_reserved0_ALIGN 0 #define GISB_ARBITER_BP_READ_2_reserved0_BITS 26 #define GISB_ARBITER_BP_READ_2_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_READ_2 :: bsp [05:05] */ #define GISB_ARBITER_BP_READ_2_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_READ_2_bsp_ALIGN 0 #define GISB_ARBITER_BP_READ_2_bsp_BITS 1 #define GISB_ARBITER_BP_READ_2_bsp_SHIFT 5 #define GISB_ARBITER_BP_READ_2_bsp_DISABLE 0 #define GISB_ARBITER_BP_READ_2_bsp_ENABLE 1 /* GISB_ARBITER :: BP_READ_2 :: aes [04:04] */ #define GISB_ARBITER_BP_READ_2_aes_MASK 0x00000010 #define GISB_ARBITER_BP_READ_2_aes_ALIGN 0 #define GISB_ARBITER_BP_READ_2_aes_BITS 1 #define GISB_ARBITER_BP_READ_2_aes_SHIFT 4 #define GISB_ARBITER_BP_READ_2_aes_DISABLE 0 #define GISB_ARBITER_BP_READ_2_aes_ENABLE 1 /* GISB_ARBITER :: BP_READ_2 :: fve [03:03] */ #define GISB_ARBITER_BP_READ_2_fve_MASK 0x00000008 #define GISB_ARBITER_BP_READ_2_fve_ALIGN 0 #define GISB_ARBITER_BP_READ_2_fve_BITS 1 #define GISB_ARBITER_BP_READ_2_fve_SHIFT 3 #define GISB_ARBITER_BP_READ_2_fve_DISABLE 0 #define GISB_ARBITER_BP_READ_2_fve_ENABLE 1 /* GISB_ARBITER :: BP_READ_2 :: tgt [02:02] */ #define GISB_ARBITER_BP_READ_2_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_READ_2_tgt_ALIGN 0 #define GISB_ARBITER_BP_READ_2_tgt_BITS 1 #define GISB_ARBITER_BP_READ_2_tgt_SHIFT 2 #define GISB_ARBITER_BP_READ_2_tgt_DISABLE 0 #define GISB_ARBITER_BP_READ_2_tgt_ENABLE 1 /* GISB_ARBITER :: BP_READ_2 :: dbu [01:01] */ #define GISB_ARBITER_BP_READ_2_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_READ_2_dbu_ALIGN 0 #define GISB_ARBITER_BP_READ_2_dbu_BITS 1 #define GISB_ARBITER_BP_READ_2_dbu_SHIFT 1 #define GISB_ARBITER_BP_READ_2_dbu_DISABLE 0 #define GISB_ARBITER_BP_READ_2_dbu_ENABLE 1 /* GISB_ARBITER :: BP_READ_2 :: cce [00:00] */ #define GISB_ARBITER_BP_READ_2_cce_MASK 0x00000001 #define GISB_ARBITER_BP_READ_2_cce_ALIGN 0 #define GISB_ARBITER_BP_READ_2_cce_BITS 1 #define GISB_ARBITER_BP_READ_2_cce_SHIFT 0 #define GISB_ARBITER_BP_READ_2_cce_DISABLE 0 #define GISB_ARBITER_BP_READ_2_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_WRITE_2 ***************************************************************************/ /* GISB_ARBITER :: BP_WRITE_2 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_WRITE_2_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_WRITE_2_reserved0_ALIGN 0 #define GISB_ARBITER_BP_WRITE_2_reserved0_BITS 26 #define GISB_ARBITER_BP_WRITE_2_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_WRITE_2 :: bsp [05:05] */ #define GISB_ARBITER_BP_WRITE_2_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_WRITE_2_bsp_ALIGN 0 #define GISB_ARBITER_BP_WRITE_2_bsp_BITS 1 #define GISB_ARBITER_BP_WRITE_2_bsp_SHIFT 5 #define GISB_ARBITER_BP_WRITE_2_bsp_DISABLE 0 #define GISB_ARBITER_BP_WRITE_2_bsp_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_2 :: aes [04:04] */ #define GISB_ARBITER_BP_WRITE_2_aes_MASK 0x00000010 #define GISB_ARBITER_BP_WRITE_2_aes_ALIGN 0 #define GISB_ARBITER_BP_WRITE_2_aes_BITS 1 #define GISB_ARBITER_BP_WRITE_2_aes_SHIFT 4 #define GISB_ARBITER_BP_WRITE_2_aes_DISABLE 0 #define GISB_ARBITER_BP_WRITE_2_aes_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_2 :: fve [03:03] */ #define GISB_ARBITER_BP_WRITE_2_fve_MASK 0x00000008 #define GISB_ARBITER_BP_WRITE_2_fve_ALIGN 0 #define GISB_ARBITER_BP_WRITE_2_fve_BITS 1 #define GISB_ARBITER_BP_WRITE_2_fve_SHIFT 3 #define GISB_ARBITER_BP_WRITE_2_fve_DISABLE 0 #define GISB_ARBITER_BP_WRITE_2_fve_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_2 :: tgt [02:02] */ #define GISB_ARBITER_BP_WRITE_2_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_WRITE_2_tgt_ALIGN 0 #define GISB_ARBITER_BP_WRITE_2_tgt_BITS 1 #define GISB_ARBITER_BP_WRITE_2_tgt_SHIFT 2 #define GISB_ARBITER_BP_WRITE_2_tgt_DISABLE 0 #define GISB_ARBITER_BP_WRITE_2_tgt_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_2 :: dbu [01:01] */ #define GISB_ARBITER_BP_WRITE_2_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_WRITE_2_dbu_ALIGN 0 #define GISB_ARBITER_BP_WRITE_2_dbu_BITS 1 #define GISB_ARBITER_BP_WRITE_2_dbu_SHIFT 1 #define GISB_ARBITER_BP_WRITE_2_dbu_DISABLE 0 #define GISB_ARBITER_BP_WRITE_2_dbu_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_2 :: cce [00:00] */ #define GISB_ARBITER_BP_WRITE_2_cce_MASK 0x00000001 #define GISB_ARBITER_BP_WRITE_2_cce_ALIGN 0 #define GISB_ARBITER_BP_WRITE_2_cce_BITS 1 #define GISB_ARBITER_BP_WRITE_2_cce_SHIFT 0 #define GISB_ARBITER_BP_WRITE_2_cce_DISABLE 0 #define GISB_ARBITER_BP_WRITE_2_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_ENABLE_2 ***************************************************************************/ /* GISB_ARBITER :: BP_ENABLE_2 :: reserved0 [31:03] */ #define GISB_ARBITER_BP_ENABLE_2_reserved0_MASK 0xfffffff8 #define GISB_ARBITER_BP_ENABLE_2_reserved0_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_2_reserved0_BITS 29 #define GISB_ARBITER_BP_ENABLE_2_reserved0_SHIFT 3 /* GISB_ARBITER :: BP_ENABLE_2 :: block [02:02] */ #define GISB_ARBITER_BP_ENABLE_2_block_MASK 0x00000004 #define GISB_ARBITER_BP_ENABLE_2_block_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_2_block_BITS 1 #define GISB_ARBITER_BP_ENABLE_2_block_SHIFT 2 #define GISB_ARBITER_BP_ENABLE_2_block_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_2_block_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_2 :: address [01:01] */ #define GISB_ARBITER_BP_ENABLE_2_address_MASK 0x00000002 #define GISB_ARBITER_BP_ENABLE_2_address_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_2_address_BITS 1 #define GISB_ARBITER_BP_ENABLE_2_address_SHIFT 1 #define GISB_ARBITER_BP_ENABLE_2_address_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_2_address_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_2 :: access [00:00] */ #define GISB_ARBITER_BP_ENABLE_2_access_MASK 0x00000001 #define GISB_ARBITER_BP_ENABLE_2_access_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_2_access_BITS 1 #define GISB_ARBITER_BP_ENABLE_2_access_SHIFT 0 #define GISB_ARBITER_BP_ENABLE_2_access_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_2_access_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_START_ADDR_3 ***************************************************************************/ /* GISB_ARBITER :: BP_START_ADDR_3 :: start [31:00] */ #define GISB_ARBITER_BP_START_ADDR_3_start_MASK 0xffffffff #define GISB_ARBITER_BP_START_ADDR_3_start_ALIGN 0 #define GISB_ARBITER_BP_START_ADDR_3_start_BITS 32 #define GISB_ARBITER_BP_START_ADDR_3_start_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_END_ADDR_3 ***************************************************************************/ /* GISB_ARBITER :: BP_END_ADDR_3 :: end [31:00] */ #define GISB_ARBITER_BP_END_ADDR_3_end_MASK 0xffffffff #define GISB_ARBITER_BP_END_ADDR_3_end_ALIGN 0 #define GISB_ARBITER_BP_END_ADDR_3_end_BITS 32 #define GISB_ARBITER_BP_END_ADDR_3_end_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_READ_3 ***************************************************************************/ /* GISB_ARBITER :: BP_READ_3 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_READ_3_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_READ_3_reserved0_ALIGN 0 #define GISB_ARBITER_BP_READ_3_reserved0_BITS 26 #define GISB_ARBITER_BP_READ_3_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_READ_3 :: bsp [05:05] */ #define GISB_ARBITER_BP_READ_3_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_READ_3_bsp_ALIGN 0 #define GISB_ARBITER_BP_READ_3_bsp_BITS 1 #define GISB_ARBITER_BP_READ_3_bsp_SHIFT 5 #define GISB_ARBITER_BP_READ_3_bsp_DISABLE 0 #define GISB_ARBITER_BP_READ_3_bsp_ENABLE 1 /* GISB_ARBITER :: BP_READ_3 :: aes [04:04] */ #define GISB_ARBITER_BP_READ_3_aes_MASK 0x00000010 #define GISB_ARBITER_BP_READ_3_aes_ALIGN 0 #define GISB_ARBITER_BP_READ_3_aes_BITS 1 #define GISB_ARBITER_BP_READ_3_aes_SHIFT 4 #define GISB_ARBITER_BP_READ_3_aes_DISABLE 0 #define GISB_ARBITER_BP_READ_3_aes_ENABLE 1 /* GISB_ARBITER :: BP_READ_3 :: fve [03:03] */ #define GISB_ARBITER_BP_READ_3_fve_MASK 0x00000008 #define GISB_ARBITER_BP_READ_3_fve_ALIGN 0 #define GISB_ARBITER_BP_READ_3_fve_BITS 1 #define GISB_ARBITER_BP_READ_3_fve_SHIFT 3 #define GISB_ARBITER_BP_READ_3_fve_DISABLE 0 #define GISB_ARBITER_BP_READ_3_fve_ENABLE 1 /* GISB_ARBITER :: BP_READ_3 :: tgt [02:02] */ #define GISB_ARBITER_BP_READ_3_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_READ_3_tgt_ALIGN 0 #define GISB_ARBITER_BP_READ_3_tgt_BITS 1 #define GISB_ARBITER_BP_READ_3_tgt_SHIFT 2 #define GISB_ARBITER_BP_READ_3_tgt_DISABLE 0 #define GISB_ARBITER_BP_READ_3_tgt_ENABLE 1 /* GISB_ARBITER :: BP_READ_3 :: dbu [01:01] */ #define GISB_ARBITER_BP_READ_3_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_READ_3_dbu_ALIGN 0 #define GISB_ARBITER_BP_READ_3_dbu_BITS 1 #define GISB_ARBITER_BP_READ_3_dbu_SHIFT 1 #define GISB_ARBITER_BP_READ_3_dbu_DISABLE 0 #define GISB_ARBITER_BP_READ_3_dbu_ENABLE 1 /* GISB_ARBITER :: BP_READ_3 :: cce [00:00] */ #define GISB_ARBITER_BP_READ_3_cce_MASK 0x00000001 #define GISB_ARBITER_BP_READ_3_cce_ALIGN 0 #define GISB_ARBITER_BP_READ_3_cce_BITS 1 #define GISB_ARBITER_BP_READ_3_cce_SHIFT 0 #define GISB_ARBITER_BP_READ_3_cce_DISABLE 0 #define GISB_ARBITER_BP_READ_3_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_WRITE_3 ***************************************************************************/ /* GISB_ARBITER :: BP_WRITE_3 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_WRITE_3_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_WRITE_3_reserved0_ALIGN 0 #define GISB_ARBITER_BP_WRITE_3_reserved0_BITS 26 #define GISB_ARBITER_BP_WRITE_3_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_WRITE_3 :: bsp [05:05] */ #define GISB_ARBITER_BP_WRITE_3_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_WRITE_3_bsp_ALIGN 0 #define GISB_ARBITER_BP_WRITE_3_bsp_BITS 1 #define GISB_ARBITER_BP_WRITE_3_bsp_SHIFT 5 #define GISB_ARBITER_BP_WRITE_3_bsp_DISABLE 0 #define GISB_ARBITER_BP_WRITE_3_bsp_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_3 :: aes [04:04] */ #define GISB_ARBITER_BP_WRITE_3_aes_MASK 0x00000010 #define GISB_ARBITER_BP_WRITE_3_aes_ALIGN 0 #define GISB_ARBITER_BP_WRITE_3_aes_BITS 1 #define GISB_ARBITER_BP_WRITE_3_aes_SHIFT 4 #define GISB_ARBITER_BP_WRITE_3_aes_DISABLE 0 #define GISB_ARBITER_BP_WRITE_3_aes_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_3 :: fve [03:03] */ #define GISB_ARBITER_BP_WRITE_3_fve_MASK 0x00000008 #define GISB_ARBITER_BP_WRITE_3_fve_ALIGN 0 #define GISB_ARBITER_BP_WRITE_3_fve_BITS 1 #define GISB_ARBITER_BP_WRITE_3_fve_SHIFT 3 #define GISB_ARBITER_BP_WRITE_3_fve_DISABLE 0 #define GISB_ARBITER_BP_WRITE_3_fve_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_3 :: tgt [02:02] */ #define GISB_ARBITER_BP_WRITE_3_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_WRITE_3_tgt_ALIGN 0 #define GISB_ARBITER_BP_WRITE_3_tgt_BITS 1 #define GISB_ARBITER_BP_WRITE_3_tgt_SHIFT 2 #define GISB_ARBITER_BP_WRITE_3_tgt_DISABLE 0 #define GISB_ARBITER_BP_WRITE_3_tgt_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_3 :: dbu [01:01] */ #define GISB_ARBITER_BP_WRITE_3_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_WRITE_3_dbu_ALIGN 0 #define GISB_ARBITER_BP_WRITE_3_dbu_BITS 1 #define GISB_ARBITER_BP_WRITE_3_dbu_SHIFT 1 #define GISB_ARBITER_BP_WRITE_3_dbu_DISABLE 0 #define GISB_ARBITER_BP_WRITE_3_dbu_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_3 :: cce [00:00] */ #define GISB_ARBITER_BP_WRITE_3_cce_MASK 0x00000001 #define GISB_ARBITER_BP_WRITE_3_cce_ALIGN 0 #define GISB_ARBITER_BP_WRITE_3_cce_BITS 1 #define GISB_ARBITER_BP_WRITE_3_cce_SHIFT 0 #define GISB_ARBITER_BP_WRITE_3_cce_DISABLE 0 #define GISB_ARBITER_BP_WRITE_3_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_ENABLE_3 ***************************************************************************/ /* GISB_ARBITER :: BP_ENABLE_3 :: reserved0 [31:03] */ #define GISB_ARBITER_BP_ENABLE_3_reserved0_MASK 0xfffffff8 #define GISB_ARBITER_BP_ENABLE_3_reserved0_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_3_reserved0_BITS 29 #define GISB_ARBITER_BP_ENABLE_3_reserved0_SHIFT 3 /* GISB_ARBITER :: BP_ENABLE_3 :: block [02:02] */ #define GISB_ARBITER_BP_ENABLE_3_block_MASK 0x00000004 #define GISB_ARBITER_BP_ENABLE_3_block_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_3_block_BITS 1 #define GISB_ARBITER_BP_ENABLE_3_block_SHIFT 2 #define GISB_ARBITER_BP_ENABLE_3_block_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_3_block_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_3 :: address [01:01] */ #define GISB_ARBITER_BP_ENABLE_3_address_MASK 0x00000002 #define GISB_ARBITER_BP_ENABLE_3_address_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_3_address_BITS 1 #define GISB_ARBITER_BP_ENABLE_3_address_SHIFT 1 #define GISB_ARBITER_BP_ENABLE_3_address_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_3_address_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_3 :: access [00:00] */ #define GISB_ARBITER_BP_ENABLE_3_access_MASK 0x00000001 #define GISB_ARBITER_BP_ENABLE_3_access_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_3_access_BITS 1 #define GISB_ARBITER_BP_ENABLE_3_access_SHIFT 0 #define GISB_ARBITER_BP_ENABLE_3_access_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_3_access_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_START_ADDR_4 ***************************************************************************/ /* GISB_ARBITER :: BP_START_ADDR_4 :: start [31:00] */ #define GISB_ARBITER_BP_START_ADDR_4_start_MASK 0xffffffff #define GISB_ARBITER_BP_START_ADDR_4_start_ALIGN 0 #define GISB_ARBITER_BP_START_ADDR_4_start_BITS 32 #define GISB_ARBITER_BP_START_ADDR_4_start_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_END_ADDR_4 ***************************************************************************/ /* GISB_ARBITER :: BP_END_ADDR_4 :: end [31:00] */ #define GISB_ARBITER_BP_END_ADDR_4_end_MASK 0xffffffff #define GISB_ARBITER_BP_END_ADDR_4_end_ALIGN 0 #define GISB_ARBITER_BP_END_ADDR_4_end_BITS 32 #define GISB_ARBITER_BP_END_ADDR_4_end_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_READ_4 ***************************************************************************/ /* GISB_ARBITER :: BP_READ_4 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_READ_4_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_READ_4_reserved0_ALIGN 0 #define GISB_ARBITER_BP_READ_4_reserved0_BITS 26 #define GISB_ARBITER_BP_READ_4_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_READ_4 :: bsp [05:05] */ #define GISB_ARBITER_BP_READ_4_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_READ_4_bsp_ALIGN 0 #define GISB_ARBITER_BP_READ_4_bsp_BITS 1 #define GISB_ARBITER_BP_READ_4_bsp_SHIFT 5 #define GISB_ARBITER_BP_READ_4_bsp_DISABLE 0 #define GISB_ARBITER_BP_READ_4_bsp_ENABLE 1 /* GISB_ARBITER :: BP_READ_4 :: aes [04:04] */ #define GISB_ARBITER_BP_READ_4_aes_MASK 0x00000010 #define GISB_ARBITER_BP_READ_4_aes_ALIGN 0 #define GISB_ARBITER_BP_READ_4_aes_BITS 1 #define GISB_ARBITER_BP_READ_4_aes_SHIFT 4 #define GISB_ARBITER_BP_READ_4_aes_DISABLE 0 #define GISB_ARBITER_BP_READ_4_aes_ENABLE 1 /* GISB_ARBITER :: BP_READ_4 :: fve [03:03] */ #define GISB_ARBITER_BP_READ_4_fve_MASK 0x00000008 #define GISB_ARBITER_BP_READ_4_fve_ALIGN 0 #define GISB_ARBITER_BP_READ_4_fve_BITS 1 #define GISB_ARBITER_BP_READ_4_fve_SHIFT 3 #define GISB_ARBITER_BP_READ_4_fve_DISABLE 0 #define GISB_ARBITER_BP_READ_4_fve_ENABLE 1 /* GISB_ARBITER :: BP_READ_4 :: tgt [02:02] */ #define GISB_ARBITER_BP_READ_4_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_READ_4_tgt_ALIGN 0 #define GISB_ARBITER_BP_READ_4_tgt_BITS 1 #define GISB_ARBITER_BP_READ_4_tgt_SHIFT 2 #define GISB_ARBITER_BP_READ_4_tgt_DISABLE 0 #define GISB_ARBITER_BP_READ_4_tgt_ENABLE 1 /* GISB_ARBITER :: BP_READ_4 :: dbu [01:01] */ #define GISB_ARBITER_BP_READ_4_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_READ_4_dbu_ALIGN 0 #define GISB_ARBITER_BP_READ_4_dbu_BITS 1 #define GISB_ARBITER_BP_READ_4_dbu_SHIFT 1 #define GISB_ARBITER_BP_READ_4_dbu_DISABLE 0 #define GISB_ARBITER_BP_READ_4_dbu_ENABLE 1 /* GISB_ARBITER :: BP_READ_4 :: cce [00:00] */ #define GISB_ARBITER_BP_READ_4_cce_MASK 0x00000001 #define GISB_ARBITER_BP_READ_4_cce_ALIGN 0 #define GISB_ARBITER_BP_READ_4_cce_BITS 1 #define GISB_ARBITER_BP_READ_4_cce_SHIFT 0 #define GISB_ARBITER_BP_READ_4_cce_DISABLE 0 #define GISB_ARBITER_BP_READ_4_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_WRITE_4 ***************************************************************************/ /* GISB_ARBITER :: BP_WRITE_4 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_WRITE_4_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_WRITE_4_reserved0_ALIGN 0 #define GISB_ARBITER_BP_WRITE_4_reserved0_BITS 26 #define GISB_ARBITER_BP_WRITE_4_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_WRITE_4 :: bsp [05:05] */ #define GISB_ARBITER_BP_WRITE_4_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_WRITE_4_bsp_ALIGN 0 #define GISB_ARBITER_BP_WRITE_4_bsp_BITS 1 #define GISB_ARBITER_BP_WRITE_4_bsp_SHIFT 5 #define GISB_ARBITER_BP_WRITE_4_bsp_DISABLE 0 #define GISB_ARBITER_BP_WRITE_4_bsp_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_4 :: aes [04:04] */ #define GISB_ARBITER_BP_WRITE_4_aes_MASK 0x00000010 #define GISB_ARBITER_BP_WRITE_4_aes_ALIGN 0 #define GISB_ARBITER_BP_WRITE_4_aes_BITS 1 #define GISB_ARBITER_BP_WRITE_4_aes_SHIFT 4 #define GISB_ARBITER_BP_WRITE_4_aes_DISABLE 0 #define GISB_ARBITER_BP_WRITE_4_aes_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_4 :: fve [03:03] */ #define GISB_ARBITER_BP_WRITE_4_fve_MASK 0x00000008 #define GISB_ARBITER_BP_WRITE_4_fve_ALIGN 0 #define GISB_ARBITER_BP_WRITE_4_fve_BITS 1 #define GISB_ARBITER_BP_WRITE_4_fve_SHIFT 3 #define GISB_ARBITER_BP_WRITE_4_fve_DISABLE 0 #define GISB_ARBITER_BP_WRITE_4_fve_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_4 :: tgt [02:02] */ #define GISB_ARBITER_BP_WRITE_4_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_WRITE_4_tgt_ALIGN 0 #define GISB_ARBITER_BP_WRITE_4_tgt_BITS 1 #define GISB_ARBITER_BP_WRITE_4_tgt_SHIFT 2 #define GISB_ARBITER_BP_WRITE_4_tgt_DISABLE 0 #define GISB_ARBITER_BP_WRITE_4_tgt_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_4 :: dbu [01:01] */ #define GISB_ARBITER_BP_WRITE_4_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_WRITE_4_dbu_ALIGN 0 #define GISB_ARBITER_BP_WRITE_4_dbu_BITS 1 #define GISB_ARBITER_BP_WRITE_4_dbu_SHIFT 1 #define GISB_ARBITER_BP_WRITE_4_dbu_DISABLE 0 #define GISB_ARBITER_BP_WRITE_4_dbu_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_4 :: cce [00:00] */ #define GISB_ARBITER_BP_WRITE_4_cce_MASK 0x00000001 #define GISB_ARBITER_BP_WRITE_4_cce_ALIGN 0 #define GISB_ARBITER_BP_WRITE_4_cce_BITS 1 #define GISB_ARBITER_BP_WRITE_4_cce_SHIFT 0 #define GISB_ARBITER_BP_WRITE_4_cce_DISABLE 0 #define GISB_ARBITER_BP_WRITE_4_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_ENABLE_4 ***************************************************************************/ /* GISB_ARBITER :: BP_ENABLE_4 :: reserved0 [31:03] */ #define GISB_ARBITER_BP_ENABLE_4_reserved0_MASK 0xfffffff8 #define GISB_ARBITER_BP_ENABLE_4_reserved0_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_4_reserved0_BITS 29 #define GISB_ARBITER_BP_ENABLE_4_reserved0_SHIFT 3 /* GISB_ARBITER :: BP_ENABLE_4 :: block [02:02] */ #define GISB_ARBITER_BP_ENABLE_4_block_MASK 0x00000004 #define GISB_ARBITER_BP_ENABLE_4_block_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_4_block_BITS 1 #define GISB_ARBITER_BP_ENABLE_4_block_SHIFT 2 #define GISB_ARBITER_BP_ENABLE_4_block_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_4_block_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_4 :: address [01:01] */ #define GISB_ARBITER_BP_ENABLE_4_address_MASK 0x00000002 #define GISB_ARBITER_BP_ENABLE_4_address_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_4_address_BITS 1 #define GISB_ARBITER_BP_ENABLE_4_address_SHIFT 1 #define GISB_ARBITER_BP_ENABLE_4_address_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_4_address_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_4 :: access [00:00] */ #define GISB_ARBITER_BP_ENABLE_4_access_MASK 0x00000001 #define GISB_ARBITER_BP_ENABLE_4_access_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_4_access_BITS 1 #define GISB_ARBITER_BP_ENABLE_4_access_SHIFT 0 #define GISB_ARBITER_BP_ENABLE_4_access_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_4_access_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_START_ADDR_5 ***************************************************************************/ /* GISB_ARBITER :: BP_START_ADDR_5 :: start [31:00] */ #define GISB_ARBITER_BP_START_ADDR_5_start_MASK 0xffffffff #define GISB_ARBITER_BP_START_ADDR_5_start_ALIGN 0 #define GISB_ARBITER_BP_START_ADDR_5_start_BITS 32 #define GISB_ARBITER_BP_START_ADDR_5_start_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_END_ADDR_5 ***************************************************************************/ /* GISB_ARBITER :: BP_END_ADDR_5 :: end [31:00] */ #define GISB_ARBITER_BP_END_ADDR_5_end_MASK 0xffffffff #define GISB_ARBITER_BP_END_ADDR_5_end_ALIGN 0 #define GISB_ARBITER_BP_END_ADDR_5_end_BITS 32 #define GISB_ARBITER_BP_END_ADDR_5_end_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_READ_5 ***************************************************************************/ /* GISB_ARBITER :: BP_READ_5 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_READ_5_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_READ_5_reserved0_ALIGN 0 #define GISB_ARBITER_BP_READ_5_reserved0_BITS 26 #define GISB_ARBITER_BP_READ_5_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_READ_5 :: bsp [05:05] */ #define GISB_ARBITER_BP_READ_5_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_READ_5_bsp_ALIGN 0 #define GISB_ARBITER_BP_READ_5_bsp_BITS 1 #define GISB_ARBITER_BP_READ_5_bsp_SHIFT 5 #define GISB_ARBITER_BP_READ_5_bsp_DISABLE 0 #define GISB_ARBITER_BP_READ_5_bsp_ENABLE 1 /* GISB_ARBITER :: BP_READ_5 :: aes [04:04] */ #define GISB_ARBITER_BP_READ_5_aes_MASK 0x00000010 #define GISB_ARBITER_BP_READ_5_aes_ALIGN 0 #define GISB_ARBITER_BP_READ_5_aes_BITS 1 #define GISB_ARBITER_BP_READ_5_aes_SHIFT 4 #define GISB_ARBITER_BP_READ_5_aes_DISABLE 0 #define GISB_ARBITER_BP_READ_5_aes_ENABLE 1 /* GISB_ARBITER :: BP_READ_5 :: fve [03:03] */ #define GISB_ARBITER_BP_READ_5_fve_MASK 0x00000008 #define GISB_ARBITER_BP_READ_5_fve_ALIGN 0 #define GISB_ARBITER_BP_READ_5_fve_BITS 1 #define GISB_ARBITER_BP_READ_5_fve_SHIFT 3 #define GISB_ARBITER_BP_READ_5_fve_DISABLE 0 #define GISB_ARBITER_BP_READ_5_fve_ENABLE 1 /* GISB_ARBITER :: BP_READ_5 :: tgt [02:02] */ #define GISB_ARBITER_BP_READ_5_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_READ_5_tgt_ALIGN 0 #define GISB_ARBITER_BP_READ_5_tgt_BITS 1 #define GISB_ARBITER_BP_READ_5_tgt_SHIFT 2 #define GISB_ARBITER_BP_READ_5_tgt_DISABLE 0 #define GISB_ARBITER_BP_READ_5_tgt_ENABLE 1 /* GISB_ARBITER :: BP_READ_5 :: dbu [01:01] */ #define GISB_ARBITER_BP_READ_5_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_READ_5_dbu_ALIGN 0 #define GISB_ARBITER_BP_READ_5_dbu_BITS 1 #define GISB_ARBITER_BP_READ_5_dbu_SHIFT 1 #define GISB_ARBITER_BP_READ_5_dbu_DISABLE 0 #define GISB_ARBITER_BP_READ_5_dbu_ENABLE 1 /* GISB_ARBITER :: BP_READ_5 :: cce [00:00] */ #define GISB_ARBITER_BP_READ_5_cce_MASK 0x00000001 #define GISB_ARBITER_BP_READ_5_cce_ALIGN 0 #define GISB_ARBITER_BP_READ_5_cce_BITS 1 #define GISB_ARBITER_BP_READ_5_cce_SHIFT 0 #define GISB_ARBITER_BP_READ_5_cce_DISABLE 0 #define GISB_ARBITER_BP_READ_5_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_WRITE_5 ***************************************************************************/ /* GISB_ARBITER :: BP_WRITE_5 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_WRITE_5_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_WRITE_5_reserved0_ALIGN 0 #define GISB_ARBITER_BP_WRITE_5_reserved0_BITS 26 #define GISB_ARBITER_BP_WRITE_5_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_WRITE_5 :: bsp [05:05] */ #define GISB_ARBITER_BP_WRITE_5_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_WRITE_5_bsp_ALIGN 0 #define GISB_ARBITER_BP_WRITE_5_bsp_BITS 1 #define GISB_ARBITER_BP_WRITE_5_bsp_SHIFT 5 #define GISB_ARBITER_BP_WRITE_5_bsp_DISABLE 0 #define GISB_ARBITER_BP_WRITE_5_bsp_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_5 :: aes [04:04] */ #define GISB_ARBITER_BP_WRITE_5_aes_MASK 0x00000010 #define GISB_ARBITER_BP_WRITE_5_aes_ALIGN 0 #define GISB_ARBITER_BP_WRITE_5_aes_BITS 1 #define GISB_ARBITER_BP_WRITE_5_aes_SHIFT 4 #define GISB_ARBITER_BP_WRITE_5_aes_DISABLE 0 #define GISB_ARBITER_BP_WRITE_5_aes_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_5 :: fve [03:03] */ #define GISB_ARBITER_BP_WRITE_5_fve_MASK 0x00000008 #define GISB_ARBITER_BP_WRITE_5_fve_ALIGN 0 #define GISB_ARBITER_BP_WRITE_5_fve_BITS 1 #define GISB_ARBITER_BP_WRITE_5_fve_SHIFT 3 #define GISB_ARBITER_BP_WRITE_5_fve_DISABLE 0 #define GISB_ARBITER_BP_WRITE_5_fve_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_5 :: tgt [02:02] */ #define GISB_ARBITER_BP_WRITE_5_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_WRITE_5_tgt_ALIGN 0 #define GISB_ARBITER_BP_WRITE_5_tgt_BITS 1 #define GISB_ARBITER_BP_WRITE_5_tgt_SHIFT 2 #define GISB_ARBITER_BP_WRITE_5_tgt_DISABLE 0 #define GISB_ARBITER_BP_WRITE_5_tgt_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_5 :: dbu [01:01] */ #define GISB_ARBITER_BP_WRITE_5_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_WRITE_5_dbu_ALIGN 0 #define GISB_ARBITER_BP_WRITE_5_dbu_BITS 1 #define GISB_ARBITER_BP_WRITE_5_dbu_SHIFT 1 #define GISB_ARBITER_BP_WRITE_5_dbu_DISABLE 0 #define GISB_ARBITER_BP_WRITE_5_dbu_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_5 :: cce [00:00] */ #define GISB_ARBITER_BP_WRITE_5_cce_MASK 0x00000001 #define GISB_ARBITER_BP_WRITE_5_cce_ALIGN 0 #define GISB_ARBITER_BP_WRITE_5_cce_BITS 1 #define GISB_ARBITER_BP_WRITE_5_cce_SHIFT 0 #define GISB_ARBITER_BP_WRITE_5_cce_DISABLE 0 #define GISB_ARBITER_BP_WRITE_5_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_ENABLE_5 ***************************************************************************/ /* GISB_ARBITER :: BP_ENABLE_5 :: reserved0 [31:03] */ #define GISB_ARBITER_BP_ENABLE_5_reserved0_MASK 0xfffffff8 #define GISB_ARBITER_BP_ENABLE_5_reserved0_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_5_reserved0_BITS 29 #define GISB_ARBITER_BP_ENABLE_5_reserved0_SHIFT 3 /* GISB_ARBITER :: BP_ENABLE_5 :: block [02:02] */ #define GISB_ARBITER_BP_ENABLE_5_block_MASK 0x00000004 #define GISB_ARBITER_BP_ENABLE_5_block_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_5_block_BITS 1 #define GISB_ARBITER_BP_ENABLE_5_block_SHIFT 2 #define GISB_ARBITER_BP_ENABLE_5_block_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_5_block_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_5 :: address [01:01] */ #define GISB_ARBITER_BP_ENABLE_5_address_MASK 0x00000002 #define GISB_ARBITER_BP_ENABLE_5_address_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_5_address_BITS 1 #define GISB_ARBITER_BP_ENABLE_5_address_SHIFT 1 #define GISB_ARBITER_BP_ENABLE_5_address_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_5_address_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_5 :: access [00:00] */ #define GISB_ARBITER_BP_ENABLE_5_access_MASK 0x00000001 #define GISB_ARBITER_BP_ENABLE_5_access_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_5_access_BITS 1 #define GISB_ARBITER_BP_ENABLE_5_access_SHIFT 0 #define GISB_ARBITER_BP_ENABLE_5_access_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_5_access_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_START_ADDR_6 ***************************************************************************/ /* GISB_ARBITER :: BP_START_ADDR_6 :: start [31:00] */ #define GISB_ARBITER_BP_START_ADDR_6_start_MASK 0xffffffff #define GISB_ARBITER_BP_START_ADDR_6_start_ALIGN 0 #define GISB_ARBITER_BP_START_ADDR_6_start_BITS 32 #define GISB_ARBITER_BP_START_ADDR_6_start_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_END_ADDR_6 ***************************************************************************/ /* GISB_ARBITER :: BP_END_ADDR_6 :: end [31:00] */ #define GISB_ARBITER_BP_END_ADDR_6_end_MASK 0xffffffff #define GISB_ARBITER_BP_END_ADDR_6_end_ALIGN 0 #define GISB_ARBITER_BP_END_ADDR_6_end_BITS 32 #define GISB_ARBITER_BP_END_ADDR_6_end_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_READ_6 ***************************************************************************/ /* GISB_ARBITER :: BP_READ_6 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_READ_6_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_READ_6_reserved0_ALIGN 0 #define GISB_ARBITER_BP_READ_6_reserved0_BITS 26 #define GISB_ARBITER_BP_READ_6_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_READ_6 :: bsp [05:05] */ #define GISB_ARBITER_BP_READ_6_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_READ_6_bsp_ALIGN 0 #define GISB_ARBITER_BP_READ_6_bsp_BITS 1 #define GISB_ARBITER_BP_READ_6_bsp_SHIFT 5 #define GISB_ARBITER_BP_READ_6_bsp_DISABLE 0 #define GISB_ARBITER_BP_READ_6_bsp_ENABLE 1 /* GISB_ARBITER :: BP_READ_6 :: aes [04:04] */ #define GISB_ARBITER_BP_READ_6_aes_MASK 0x00000010 #define GISB_ARBITER_BP_READ_6_aes_ALIGN 0 #define GISB_ARBITER_BP_READ_6_aes_BITS 1 #define GISB_ARBITER_BP_READ_6_aes_SHIFT 4 #define GISB_ARBITER_BP_READ_6_aes_DISABLE 0 #define GISB_ARBITER_BP_READ_6_aes_ENABLE 1 /* GISB_ARBITER :: BP_READ_6 :: fve [03:03] */ #define GISB_ARBITER_BP_READ_6_fve_MASK 0x00000008 #define GISB_ARBITER_BP_READ_6_fve_ALIGN 0 #define GISB_ARBITER_BP_READ_6_fve_BITS 1 #define GISB_ARBITER_BP_READ_6_fve_SHIFT 3 #define GISB_ARBITER_BP_READ_6_fve_DISABLE 0 #define GISB_ARBITER_BP_READ_6_fve_ENABLE 1 /* GISB_ARBITER :: BP_READ_6 :: tgt [02:02] */ #define GISB_ARBITER_BP_READ_6_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_READ_6_tgt_ALIGN 0 #define GISB_ARBITER_BP_READ_6_tgt_BITS 1 #define GISB_ARBITER_BP_READ_6_tgt_SHIFT 2 #define GISB_ARBITER_BP_READ_6_tgt_DISABLE 0 #define GISB_ARBITER_BP_READ_6_tgt_ENABLE 1 /* GISB_ARBITER :: BP_READ_6 :: dbu [01:01] */ #define GISB_ARBITER_BP_READ_6_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_READ_6_dbu_ALIGN 0 #define GISB_ARBITER_BP_READ_6_dbu_BITS 1 #define GISB_ARBITER_BP_READ_6_dbu_SHIFT 1 #define GISB_ARBITER_BP_READ_6_dbu_DISABLE 0 #define GISB_ARBITER_BP_READ_6_dbu_ENABLE 1 /* GISB_ARBITER :: BP_READ_6 :: cce [00:00] */ #define GISB_ARBITER_BP_READ_6_cce_MASK 0x00000001 #define GISB_ARBITER_BP_READ_6_cce_ALIGN 0 #define GISB_ARBITER_BP_READ_6_cce_BITS 1 #define GISB_ARBITER_BP_READ_6_cce_SHIFT 0 #define GISB_ARBITER_BP_READ_6_cce_DISABLE 0 #define GISB_ARBITER_BP_READ_6_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_WRITE_6 ***************************************************************************/ /* GISB_ARBITER :: BP_WRITE_6 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_WRITE_6_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_WRITE_6_reserved0_ALIGN 0 #define GISB_ARBITER_BP_WRITE_6_reserved0_BITS 26 #define GISB_ARBITER_BP_WRITE_6_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_WRITE_6 :: bsp [05:05] */ #define GISB_ARBITER_BP_WRITE_6_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_WRITE_6_bsp_ALIGN 0 #define GISB_ARBITER_BP_WRITE_6_bsp_BITS 1 #define GISB_ARBITER_BP_WRITE_6_bsp_SHIFT 5 #define GISB_ARBITER_BP_WRITE_6_bsp_DISABLE 0 #define GISB_ARBITER_BP_WRITE_6_bsp_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_6 :: aes [04:04] */ #define GISB_ARBITER_BP_WRITE_6_aes_MASK 0x00000010 #define GISB_ARBITER_BP_WRITE_6_aes_ALIGN 0 #define GISB_ARBITER_BP_WRITE_6_aes_BITS 1 #define GISB_ARBITER_BP_WRITE_6_aes_SHIFT 4 #define GISB_ARBITER_BP_WRITE_6_aes_DISABLE 0 #define GISB_ARBITER_BP_WRITE_6_aes_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_6 :: fve [03:03] */ #define GISB_ARBITER_BP_WRITE_6_fve_MASK 0x00000008 #define GISB_ARBITER_BP_WRITE_6_fve_ALIGN 0 #define GISB_ARBITER_BP_WRITE_6_fve_BITS 1 #define GISB_ARBITER_BP_WRITE_6_fve_SHIFT 3 #define GISB_ARBITER_BP_WRITE_6_fve_DISABLE 0 #define GISB_ARBITER_BP_WRITE_6_fve_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_6 :: tgt [02:02] */ #define GISB_ARBITER_BP_WRITE_6_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_WRITE_6_tgt_ALIGN 0 #define GISB_ARBITER_BP_WRITE_6_tgt_BITS 1 #define GISB_ARBITER_BP_WRITE_6_tgt_SHIFT 2 #define GISB_ARBITER_BP_WRITE_6_tgt_DISABLE 0 #define GISB_ARBITER_BP_WRITE_6_tgt_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_6 :: dbu [01:01] */ #define GISB_ARBITER_BP_WRITE_6_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_WRITE_6_dbu_ALIGN 0 #define GISB_ARBITER_BP_WRITE_6_dbu_BITS 1 #define GISB_ARBITER_BP_WRITE_6_dbu_SHIFT 1 #define GISB_ARBITER_BP_WRITE_6_dbu_DISABLE 0 #define GISB_ARBITER_BP_WRITE_6_dbu_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_6 :: cce [00:00] */ #define GISB_ARBITER_BP_WRITE_6_cce_MASK 0x00000001 #define GISB_ARBITER_BP_WRITE_6_cce_ALIGN 0 #define GISB_ARBITER_BP_WRITE_6_cce_BITS 1 #define GISB_ARBITER_BP_WRITE_6_cce_SHIFT 0 #define GISB_ARBITER_BP_WRITE_6_cce_DISABLE 0 #define GISB_ARBITER_BP_WRITE_6_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_ENABLE_6 ***************************************************************************/ /* GISB_ARBITER :: BP_ENABLE_6 :: reserved0 [31:03] */ #define GISB_ARBITER_BP_ENABLE_6_reserved0_MASK 0xfffffff8 #define GISB_ARBITER_BP_ENABLE_6_reserved0_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_6_reserved0_BITS 29 #define GISB_ARBITER_BP_ENABLE_6_reserved0_SHIFT 3 /* GISB_ARBITER :: BP_ENABLE_6 :: block [02:02] */ #define GISB_ARBITER_BP_ENABLE_6_block_MASK 0x00000004 #define GISB_ARBITER_BP_ENABLE_6_block_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_6_block_BITS 1 #define GISB_ARBITER_BP_ENABLE_6_block_SHIFT 2 #define GISB_ARBITER_BP_ENABLE_6_block_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_6_block_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_6 :: address [01:01] */ #define GISB_ARBITER_BP_ENABLE_6_address_MASK 0x00000002 #define GISB_ARBITER_BP_ENABLE_6_address_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_6_address_BITS 1 #define GISB_ARBITER_BP_ENABLE_6_address_SHIFT 1 #define GISB_ARBITER_BP_ENABLE_6_address_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_6_address_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_6 :: access [00:00] */ #define GISB_ARBITER_BP_ENABLE_6_access_MASK 0x00000001 #define GISB_ARBITER_BP_ENABLE_6_access_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_6_access_BITS 1 #define GISB_ARBITER_BP_ENABLE_6_access_SHIFT 0 #define GISB_ARBITER_BP_ENABLE_6_access_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_6_access_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_START_ADDR_7 ***************************************************************************/ /* GISB_ARBITER :: BP_START_ADDR_7 :: start [31:00] */ #define GISB_ARBITER_BP_START_ADDR_7_start_MASK 0xffffffff #define GISB_ARBITER_BP_START_ADDR_7_start_ALIGN 0 #define GISB_ARBITER_BP_START_ADDR_7_start_BITS 32 #define GISB_ARBITER_BP_START_ADDR_7_start_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_END_ADDR_7 ***************************************************************************/ /* GISB_ARBITER :: BP_END_ADDR_7 :: end [31:00] */ #define GISB_ARBITER_BP_END_ADDR_7_end_MASK 0xffffffff #define GISB_ARBITER_BP_END_ADDR_7_end_ALIGN 0 #define GISB_ARBITER_BP_END_ADDR_7_end_BITS 32 #define GISB_ARBITER_BP_END_ADDR_7_end_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_READ_7 ***************************************************************************/ /* GISB_ARBITER :: BP_READ_7 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_READ_7_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_READ_7_reserved0_ALIGN 0 #define GISB_ARBITER_BP_READ_7_reserved0_BITS 26 #define GISB_ARBITER_BP_READ_7_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_READ_7 :: bsp [05:05] */ #define GISB_ARBITER_BP_READ_7_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_READ_7_bsp_ALIGN 0 #define GISB_ARBITER_BP_READ_7_bsp_BITS 1 #define GISB_ARBITER_BP_READ_7_bsp_SHIFT 5 #define GISB_ARBITER_BP_READ_7_bsp_DISABLE 0 #define GISB_ARBITER_BP_READ_7_bsp_ENABLE 1 /* GISB_ARBITER :: BP_READ_7 :: aes [04:04] */ #define GISB_ARBITER_BP_READ_7_aes_MASK 0x00000010 #define GISB_ARBITER_BP_READ_7_aes_ALIGN 0 #define GISB_ARBITER_BP_READ_7_aes_BITS 1 #define GISB_ARBITER_BP_READ_7_aes_SHIFT 4 #define GISB_ARBITER_BP_READ_7_aes_DISABLE 0 #define GISB_ARBITER_BP_READ_7_aes_ENABLE 1 /* GISB_ARBITER :: BP_READ_7 :: fve [03:03] */ #define GISB_ARBITER_BP_READ_7_fve_MASK 0x00000008 #define GISB_ARBITER_BP_READ_7_fve_ALIGN 0 #define GISB_ARBITER_BP_READ_7_fve_BITS 1 #define GISB_ARBITER_BP_READ_7_fve_SHIFT 3 #define GISB_ARBITER_BP_READ_7_fve_DISABLE 0 #define GISB_ARBITER_BP_READ_7_fve_ENABLE 1 /* GISB_ARBITER :: BP_READ_7 :: tgt [02:02] */ #define GISB_ARBITER_BP_READ_7_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_READ_7_tgt_ALIGN 0 #define GISB_ARBITER_BP_READ_7_tgt_BITS 1 #define GISB_ARBITER_BP_READ_7_tgt_SHIFT 2 #define GISB_ARBITER_BP_READ_7_tgt_DISABLE 0 #define GISB_ARBITER_BP_READ_7_tgt_ENABLE 1 /* GISB_ARBITER :: BP_READ_7 :: dbu [01:01] */ #define GISB_ARBITER_BP_READ_7_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_READ_7_dbu_ALIGN 0 #define GISB_ARBITER_BP_READ_7_dbu_BITS 1 #define GISB_ARBITER_BP_READ_7_dbu_SHIFT 1 #define GISB_ARBITER_BP_READ_7_dbu_DISABLE 0 #define GISB_ARBITER_BP_READ_7_dbu_ENABLE 1 /* GISB_ARBITER :: BP_READ_7 :: cce [00:00] */ #define GISB_ARBITER_BP_READ_7_cce_MASK 0x00000001 #define GISB_ARBITER_BP_READ_7_cce_ALIGN 0 #define GISB_ARBITER_BP_READ_7_cce_BITS 1 #define GISB_ARBITER_BP_READ_7_cce_SHIFT 0 #define GISB_ARBITER_BP_READ_7_cce_DISABLE 0 #define GISB_ARBITER_BP_READ_7_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_WRITE_7 ***************************************************************************/ /* GISB_ARBITER :: BP_WRITE_7 :: reserved0 [31:06] */ #define GISB_ARBITER_BP_WRITE_7_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_WRITE_7_reserved0_ALIGN 0 #define GISB_ARBITER_BP_WRITE_7_reserved0_BITS 26 #define GISB_ARBITER_BP_WRITE_7_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_WRITE_7 :: bsp [05:05] */ #define GISB_ARBITER_BP_WRITE_7_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_WRITE_7_bsp_ALIGN 0 #define GISB_ARBITER_BP_WRITE_7_bsp_BITS 1 #define GISB_ARBITER_BP_WRITE_7_bsp_SHIFT 5 #define GISB_ARBITER_BP_WRITE_7_bsp_DISABLE 0 #define GISB_ARBITER_BP_WRITE_7_bsp_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_7 :: aes [04:04] */ #define GISB_ARBITER_BP_WRITE_7_aes_MASK 0x00000010 #define GISB_ARBITER_BP_WRITE_7_aes_ALIGN 0 #define GISB_ARBITER_BP_WRITE_7_aes_BITS 1 #define GISB_ARBITER_BP_WRITE_7_aes_SHIFT 4 #define GISB_ARBITER_BP_WRITE_7_aes_DISABLE 0 #define GISB_ARBITER_BP_WRITE_7_aes_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_7 :: fve [03:03] */ #define GISB_ARBITER_BP_WRITE_7_fve_MASK 0x00000008 #define GISB_ARBITER_BP_WRITE_7_fve_ALIGN 0 #define GISB_ARBITER_BP_WRITE_7_fve_BITS 1 #define GISB_ARBITER_BP_WRITE_7_fve_SHIFT 3 #define GISB_ARBITER_BP_WRITE_7_fve_DISABLE 0 #define GISB_ARBITER_BP_WRITE_7_fve_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_7 :: tgt [02:02] */ #define GISB_ARBITER_BP_WRITE_7_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_WRITE_7_tgt_ALIGN 0 #define GISB_ARBITER_BP_WRITE_7_tgt_BITS 1 #define GISB_ARBITER_BP_WRITE_7_tgt_SHIFT 2 #define GISB_ARBITER_BP_WRITE_7_tgt_DISABLE 0 #define GISB_ARBITER_BP_WRITE_7_tgt_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_7 :: dbu [01:01] */ #define GISB_ARBITER_BP_WRITE_7_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_WRITE_7_dbu_ALIGN 0 #define GISB_ARBITER_BP_WRITE_7_dbu_BITS 1 #define GISB_ARBITER_BP_WRITE_7_dbu_SHIFT 1 #define GISB_ARBITER_BP_WRITE_7_dbu_DISABLE 0 #define GISB_ARBITER_BP_WRITE_7_dbu_ENABLE 1 /* GISB_ARBITER :: BP_WRITE_7 :: cce [00:00] */ #define GISB_ARBITER_BP_WRITE_7_cce_MASK 0x00000001 #define GISB_ARBITER_BP_WRITE_7_cce_ALIGN 0 #define GISB_ARBITER_BP_WRITE_7_cce_BITS 1 #define GISB_ARBITER_BP_WRITE_7_cce_SHIFT 0 #define GISB_ARBITER_BP_WRITE_7_cce_DISABLE 0 #define GISB_ARBITER_BP_WRITE_7_cce_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_ENABLE_7 ***************************************************************************/ /* GISB_ARBITER :: BP_ENABLE_7 :: reserved0 [31:03] */ #define GISB_ARBITER_BP_ENABLE_7_reserved0_MASK 0xfffffff8 #define GISB_ARBITER_BP_ENABLE_7_reserved0_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_7_reserved0_BITS 29 #define GISB_ARBITER_BP_ENABLE_7_reserved0_SHIFT 3 /* GISB_ARBITER :: BP_ENABLE_7 :: block [02:02] */ #define GISB_ARBITER_BP_ENABLE_7_block_MASK 0x00000004 #define GISB_ARBITER_BP_ENABLE_7_block_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_7_block_BITS 1 #define GISB_ARBITER_BP_ENABLE_7_block_SHIFT 2 #define GISB_ARBITER_BP_ENABLE_7_block_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_7_block_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_7 :: address [01:01] */ #define GISB_ARBITER_BP_ENABLE_7_address_MASK 0x00000002 #define GISB_ARBITER_BP_ENABLE_7_address_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_7_address_BITS 1 #define GISB_ARBITER_BP_ENABLE_7_address_SHIFT 1 #define GISB_ARBITER_BP_ENABLE_7_address_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_7_address_ENABLE 1 /* GISB_ARBITER :: BP_ENABLE_7 :: access [00:00] */ #define GISB_ARBITER_BP_ENABLE_7_access_MASK 0x00000001 #define GISB_ARBITER_BP_ENABLE_7_access_ALIGN 0 #define GISB_ARBITER_BP_ENABLE_7_access_BITS 1 #define GISB_ARBITER_BP_ENABLE_7_access_SHIFT 0 #define GISB_ARBITER_BP_ENABLE_7_access_DISABLE 0 #define GISB_ARBITER_BP_ENABLE_7_access_ENABLE 1 /**************************************************************************** * GISB_ARBITER :: BP_CAP_ADDR ***************************************************************************/ /* GISB_ARBITER :: BP_CAP_ADDR :: address [31:00] */ #define GISB_ARBITER_BP_CAP_ADDR_address_MASK 0xffffffff #define GISB_ARBITER_BP_CAP_ADDR_address_ALIGN 0 #define GISB_ARBITER_BP_CAP_ADDR_address_BITS 32 #define GISB_ARBITER_BP_CAP_ADDR_address_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_CAP_DATA ***************************************************************************/ /* GISB_ARBITER :: BP_CAP_DATA :: data [31:00] */ #define GISB_ARBITER_BP_CAP_DATA_data_MASK 0xffffffff #define GISB_ARBITER_BP_CAP_DATA_data_ALIGN 0 #define GISB_ARBITER_BP_CAP_DATA_data_BITS 32 #define GISB_ARBITER_BP_CAP_DATA_data_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_CAP_STATUS ***************************************************************************/ /* GISB_ARBITER :: BP_CAP_STATUS :: reserved0 [31:06] */ #define GISB_ARBITER_BP_CAP_STATUS_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_CAP_STATUS_reserved0_ALIGN 0 #define GISB_ARBITER_BP_CAP_STATUS_reserved0_BITS 26 #define GISB_ARBITER_BP_CAP_STATUS_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_CAP_STATUS :: bs_b [05:02] */ #define GISB_ARBITER_BP_CAP_STATUS_bs_b_MASK 0x0000003c #define GISB_ARBITER_BP_CAP_STATUS_bs_b_ALIGN 0 #define GISB_ARBITER_BP_CAP_STATUS_bs_b_BITS 4 #define GISB_ARBITER_BP_CAP_STATUS_bs_b_SHIFT 2 /* GISB_ARBITER :: BP_CAP_STATUS :: write [01:01] */ #define GISB_ARBITER_BP_CAP_STATUS_write_MASK 0x00000002 #define GISB_ARBITER_BP_CAP_STATUS_write_ALIGN 0 #define GISB_ARBITER_BP_CAP_STATUS_write_BITS 1 #define GISB_ARBITER_BP_CAP_STATUS_write_SHIFT 1 /* GISB_ARBITER :: BP_CAP_STATUS :: valid [00:00] */ #define GISB_ARBITER_BP_CAP_STATUS_valid_MASK 0x00000001 #define GISB_ARBITER_BP_CAP_STATUS_valid_ALIGN 0 #define GISB_ARBITER_BP_CAP_STATUS_valid_BITS 1 #define GISB_ARBITER_BP_CAP_STATUS_valid_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: BP_CAP_MASTER ***************************************************************************/ /* GISB_ARBITER :: BP_CAP_MASTER :: reserved0 [31:06] */ #define GISB_ARBITER_BP_CAP_MASTER_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_BP_CAP_MASTER_reserved0_ALIGN 0 #define GISB_ARBITER_BP_CAP_MASTER_reserved0_BITS 26 #define GISB_ARBITER_BP_CAP_MASTER_reserved0_SHIFT 6 /* GISB_ARBITER :: BP_CAP_MASTER :: bsp [05:05] */ #define GISB_ARBITER_BP_CAP_MASTER_bsp_MASK 0x00000020 #define GISB_ARBITER_BP_CAP_MASTER_bsp_ALIGN 0 #define GISB_ARBITER_BP_CAP_MASTER_bsp_BITS 1 #define GISB_ARBITER_BP_CAP_MASTER_bsp_SHIFT 5 /* GISB_ARBITER :: BP_CAP_MASTER :: aes [04:04] */ #define GISB_ARBITER_BP_CAP_MASTER_aes_MASK 0x00000010 #define GISB_ARBITER_BP_CAP_MASTER_aes_ALIGN 0 #define GISB_ARBITER_BP_CAP_MASTER_aes_BITS 1 #define GISB_ARBITER_BP_CAP_MASTER_aes_SHIFT 4 /* GISB_ARBITER :: BP_CAP_MASTER :: fve [03:03] */ #define GISB_ARBITER_BP_CAP_MASTER_fve_MASK 0x00000008 #define GISB_ARBITER_BP_CAP_MASTER_fve_ALIGN 0 #define GISB_ARBITER_BP_CAP_MASTER_fve_BITS 1 #define GISB_ARBITER_BP_CAP_MASTER_fve_SHIFT 3 /* GISB_ARBITER :: BP_CAP_MASTER :: tgt [02:02] */ #define GISB_ARBITER_BP_CAP_MASTER_tgt_MASK 0x00000004 #define GISB_ARBITER_BP_CAP_MASTER_tgt_ALIGN 0 #define GISB_ARBITER_BP_CAP_MASTER_tgt_BITS 1 #define GISB_ARBITER_BP_CAP_MASTER_tgt_SHIFT 2 /* GISB_ARBITER :: BP_CAP_MASTER :: dbu [01:01] */ #define GISB_ARBITER_BP_CAP_MASTER_dbu_MASK 0x00000002 #define GISB_ARBITER_BP_CAP_MASTER_dbu_ALIGN 0 #define GISB_ARBITER_BP_CAP_MASTER_dbu_BITS 1 #define GISB_ARBITER_BP_CAP_MASTER_dbu_SHIFT 1 /* GISB_ARBITER :: BP_CAP_MASTER :: cce [00:00] */ #define GISB_ARBITER_BP_CAP_MASTER_cce_MASK 0x00000001 #define GISB_ARBITER_BP_CAP_MASTER_cce_ALIGN 0 #define GISB_ARBITER_BP_CAP_MASTER_cce_BITS 1 #define GISB_ARBITER_BP_CAP_MASTER_cce_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: ERR_CAP_CLR ***************************************************************************/ /* GISB_ARBITER :: ERR_CAP_CLR :: reserved0 [31:01] */ #define GISB_ARBITER_ERR_CAP_CLR_reserved0_MASK 0xfffffffe #define GISB_ARBITER_ERR_CAP_CLR_reserved0_ALIGN 0 #define GISB_ARBITER_ERR_CAP_CLR_reserved0_BITS 31 #define GISB_ARBITER_ERR_CAP_CLR_reserved0_SHIFT 1 /* GISB_ARBITER :: ERR_CAP_CLR :: clear [00:00] */ #define GISB_ARBITER_ERR_CAP_CLR_clear_MASK 0x00000001 #define GISB_ARBITER_ERR_CAP_CLR_clear_ALIGN 0 #define GISB_ARBITER_ERR_CAP_CLR_clear_BITS 1 #define GISB_ARBITER_ERR_CAP_CLR_clear_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: ERR_CAP_ADDR ***************************************************************************/ /* GISB_ARBITER :: ERR_CAP_ADDR :: address [31:00] */ #define GISB_ARBITER_ERR_CAP_ADDR_address_MASK 0xffffffff #define GISB_ARBITER_ERR_CAP_ADDR_address_ALIGN 0 #define GISB_ARBITER_ERR_CAP_ADDR_address_BITS 32 #define GISB_ARBITER_ERR_CAP_ADDR_address_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: ERR_CAP_DATA ***************************************************************************/ /* GISB_ARBITER :: ERR_CAP_DATA :: data [31:00] */ #define GISB_ARBITER_ERR_CAP_DATA_data_MASK 0xffffffff #define GISB_ARBITER_ERR_CAP_DATA_data_ALIGN 0 #define GISB_ARBITER_ERR_CAP_DATA_data_BITS 32 #define GISB_ARBITER_ERR_CAP_DATA_data_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: ERR_CAP_STATUS ***************************************************************************/ /* GISB_ARBITER :: ERR_CAP_STATUS :: reserved0 [31:13] */ #define GISB_ARBITER_ERR_CAP_STATUS_reserved0_MASK 0xffffe000 #define GISB_ARBITER_ERR_CAP_STATUS_reserved0_ALIGN 0 #define GISB_ARBITER_ERR_CAP_STATUS_reserved0_BITS 19 #define GISB_ARBITER_ERR_CAP_STATUS_reserved0_SHIFT 13 /* GISB_ARBITER :: ERR_CAP_STATUS :: timeout [12:12] */ #define GISB_ARBITER_ERR_CAP_STATUS_timeout_MASK 0x00001000 #define GISB_ARBITER_ERR_CAP_STATUS_timeout_ALIGN 0 #define GISB_ARBITER_ERR_CAP_STATUS_timeout_BITS 1 #define GISB_ARBITER_ERR_CAP_STATUS_timeout_SHIFT 12 /* GISB_ARBITER :: ERR_CAP_STATUS :: tea [11:11] */ #define GISB_ARBITER_ERR_CAP_STATUS_tea_MASK 0x00000800 #define GISB_ARBITER_ERR_CAP_STATUS_tea_ALIGN 0 #define GISB_ARBITER_ERR_CAP_STATUS_tea_BITS 1 #define GISB_ARBITER_ERR_CAP_STATUS_tea_SHIFT 11 /* GISB_ARBITER :: ERR_CAP_STATUS :: reserved1 [10:06] */ #define GISB_ARBITER_ERR_CAP_STATUS_reserved1_MASK 0x000007c0 #define GISB_ARBITER_ERR_CAP_STATUS_reserved1_ALIGN 0 #define GISB_ARBITER_ERR_CAP_STATUS_reserved1_BITS 5 #define GISB_ARBITER_ERR_CAP_STATUS_reserved1_SHIFT 6 /* GISB_ARBITER :: ERR_CAP_STATUS :: bs_b [05:02] */ #define GISB_ARBITER_ERR_CAP_STATUS_bs_b_MASK 0x0000003c #define GISB_ARBITER_ERR_CAP_STATUS_bs_b_ALIGN 0 #define GISB_ARBITER_ERR_CAP_STATUS_bs_b_BITS 4 #define GISB_ARBITER_ERR_CAP_STATUS_bs_b_SHIFT 2 /* GISB_ARBITER :: ERR_CAP_STATUS :: write [01:01] */ #define GISB_ARBITER_ERR_CAP_STATUS_write_MASK 0x00000002 #define GISB_ARBITER_ERR_CAP_STATUS_write_ALIGN 0 #define GISB_ARBITER_ERR_CAP_STATUS_write_BITS 1 #define GISB_ARBITER_ERR_CAP_STATUS_write_SHIFT 1 /* GISB_ARBITER :: ERR_CAP_STATUS :: valid [00:00] */ #define GISB_ARBITER_ERR_CAP_STATUS_valid_MASK 0x00000001 #define GISB_ARBITER_ERR_CAP_STATUS_valid_ALIGN 0 #define GISB_ARBITER_ERR_CAP_STATUS_valid_BITS 1 #define GISB_ARBITER_ERR_CAP_STATUS_valid_SHIFT 0 /**************************************************************************** * GISB_ARBITER :: ERR_CAP_MASTER ***************************************************************************/ /* GISB_ARBITER :: ERR_CAP_MASTER :: reserved0 [31:06] */ #define GISB_ARBITER_ERR_CAP_MASTER_reserved0_MASK 0xffffffc0 #define GISB_ARBITER_ERR_CAP_MASTER_reserved0_ALIGN 0 #define GISB_ARBITER_ERR_CAP_MASTER_reserved0_BITS 26 #define GISB_ARBITER_ERR_CAP_MASTER_reserved0_SHIFT 6 /* GISB_ARBITER :: ERR_CAP_MASTER :: bsp [05:05] */ #define GISB_ARBITER_ERR_CAP_MASTER_bsp_MASK 0x00000020 #define GISB_ARBITER_ERR_CAP_MASTER_bsp_ALIGN 0 #define GISB_ARBITER_ERR_CAP_MASTER_bsp_BITS 1 #define GISB_ARBITER_ERR_CAP_MASTER_bsp_SHIFT 5 /* GISB_ARBITER :: ERR_CAP_MASTER :: aes [04:04] */ #define GISB_ARBITER_ERR_CAP_MASTER_aes_MASK 0x00000010 #define GISB_ARBITER_ERR_CAP_MASTER_aes_ALIGN 0 #define GISB_ARBITER_ERR_CAP_MASTER_aes_BITS 1 #define GISB_ARBITER_ERR_CAP_MASTER_aes_SHIFT 4 /* GISB_ARBITER :: ERR_CAP_MASTER :: fve [03:03] */ #define GISB_ARBITER_ERR_CAP_MASTER_fve_MASK 0x00000008 #define GISB_ARBITER_ERR_CAP_MASTER_fve_ALIGN 0 #define GISB_ARBITER_ERR_CAP_MASTER_fve_BITS 1 #define GISB_ARBITER_ERR_CAP_MASTER_fve_SHIFT 3 /* GISB_ARBITER :: ERR_CAP_MASTER :: tgt [02:02] */ #define GISB_ARBITER_ERR_CAP_MASTER_tgt_MASK 0x00000004 #define GISB_ARBITER_ERR_CAP_MASTER_tgt_ALIGN 0 #define GISB_ARBITER_ERR_CAP_MASTER_tgt_BITS 1 #define GISB_ARBITER_ERR_CAP_MASTER_tgt_SHIFT 2 /* GISB_ARBITER :: ERR_CAP_MASTER :: dbu [01:01] */ #define GISB_ARBITER_ERR_CAP_MASTER_dbu_MASK 0x00000002 #define GISB_ARBITER_ERR_CAP_MASTER_dbu_ALIGN 0 #define GISB_ARBITER_ERR_CAP_MASTER_dbu_BITS 1 #define GISB_ARBITER_ERR_CAP_MASTER_dbu_SHIFT 1 /* GISB_ARBITER :: ERR_CAP_MASTER :: cce [00:00] */ #define GISB_ARBITER_ERR_CAP_MASTER_cce_MASK 0x00000001 #define GISB_ARBITER_ERR_CAP_MASTER_cce_ALIGN 0 #define GISB_ARBITER_ERR_CAP_MASTER_cce_BITS 1 #define GISB_ARBITER_ERR_CAP_MASTER_cce_SHIFT 0 /**************************************************************************** * BCM70012_MISC_TOP_MISC_GR_BRIDGE ***************************************************************************/ /**************************************************************************** * MISC_GR_BRIDGE :: REVISION ***************************************************************************/ /* MISC_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define MISC_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define MISC_GR_BRIDGE_REVISION_reserved0_ALIGN 0 #define MISC_GR_BRIDGE_REVISION_reserved0_BITS 16 #define MISC_GR_BRIDGE_REVISION_reserved0_SHIFT 16 /* MISC_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define MISC_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define MISC_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 #define MISC_GR_BRIDGE_REVISION_MAJOR_BITS 8 #define MISC_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* MISC_GR_BRIDGE :: REVISION :: MINOR [07:00] */ #define MISC_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define MISC_GR_BRIDGE_REVISION_MINOR_ALIGN 0 #define MISC_GR_BRIDGE_REVISION_MINOR_BITS 8 #define MISC_GR_BRIDGE_REVISION_MINOR_SHIFT 0 /**************************************************************************** * MISC_GR_BRIDGE :: CTRL ***************************************************************************/ /* MISC_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ #define MISC_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe #define MISC_GR_BRIDGE_CTRL_reserved0_ALIGN 0 #define MISC_GR_BRIDGE_CTRL_reserved0_BITS 31 #define MISC_GR_BRIDGE_CTRL_reserved0_SHIFT 1 /* MISC_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ #define MISC_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 #define MISC_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 #define MISC_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 #define MISC_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 #define MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 #define MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 /**************************************************************************** * MISC_GR_BRIDGE :: SPARE_SW_RESET_0 ***************************************************************************/ /* MISC_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 /* MISC_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 #define MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 /**************************************************************************** * MISC_GR_BRIDGE :: SPARE_SW_RESET_1 ***************************************************************************/ /* MISC_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 /* MISC_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 #define MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 /**************************************************************************** * BCM70012_DBU_TOP_DBU ***************************************************************************/ /**************************************************************************** * DBU :: DBU_CMD ***************************************************************************/ /* DBU :: DBU_CMD :: reserved0 [31:03] */ #define DBU_DBU_CMD_reserved0_MASK 0xfffffff8 #define DBU_DBU_CMD_reserved0_ALIGN 0 #define DBU_DBU_CMD_reserved0_BITS 29 #define DBU_DBU_CMD_reserved0_SHIFT 3 /* DBU :: DBU_CMD :: RX_OVERFLOW [02:02] */ #define DBU_DBU_CMD_RX_OVERFLOW_MASK 0x00000004 #define DBU_DBU_CMD_RX_OVERFLOW_ALIGN 0 #define DBU_DBU_CMD_RX_OVERFLOW_BITS 1 #define DBU_DBU_CMD_RX_OVERFLOW_SHIFT 2 /* DBU :: DBU_CMD :: RX_ERROR [01:01] */ #define DBU_DBU_CMD_RX_ERROR_MASK 0x00000002 #define DBU_DBU_CMD_RX_ERROR_ALIGN 0 #define DBU_DBU_CMD_RX_ERROR_BITS 1 #define DBU_DBU_CMD_RX_ERROR_SHIFT 1 /* DBU :: DBU_CMD :: ENABLE [00:00] */ #define DBU_DBU_CMD_ENABLE_MASK 0x00000001 #define DBU_DBU_CMD_ENABLE_ALIGN 0 #define DBU_DBU_CMD_ENABLE_BITS 1 #define DBU_DBU_CMD_ENABLE_SHIFT 0 /**************************************************************************** * DBU :: DBU_STATUS ***************************************************************************/ /* DBU :: DBU_STATUS :: reserved0 [31:02] */ #define DBU_DBU_STATUS_reserved0_MASK 0xfffffffc #define DBU_DBU_STATUS_reserved0_ALIGN 0 #define DBU_DBU_STATUS_reserved0_BITS 30 #define DBU_DBU_STATUS_reserved0_SHIFT 2 /* DBU :: DBU_STATUS :: TXDATA_OCCUPIED [01:01] */ #define DBU_DBU_STATUS_TXDATA_OCCUPIED_MASK 0x00000002 #define DBU_DBU_STATUS_TXDATA_OCCUPIED_ALIGN 0 #define DBU_DBU_STATUS_TXDATA_OCCUPIED_BITS 1 #define DBU_DBU_STATUS_TXDATA_OCCUPIED_SHIFT 1 /* DBU :: DBU_STATUS :: RXDATA_VALID [00:00] */ #define DBU_DBU_STATUS_RXDATA_VALID_MASK 0x00000001 #define DBU_DBU_STATUS_RXDATA_VALID_ALIGN 0 #define DBU_DBU_STATUS_RXDATA_VALID_BITS 1 #define DBU_DBU_STATUS_RXDATA_VALID_SHIFT 0 /**************************************************************************** * DBU :: DBU_CONFIG ***************************************************************************/ /* DBU :: DBU_CONFIG :: reserved0 [31:03] */ #define DBU_DBU_CONFIG_reserved0_MASK 0xfffffff8 #define DBU_DBU_CONFIG_reserved0_ALIGN 0 #define DBU_DBU_CONFIG_reserved0_BITS 29 #define DBU_DBU_CONFIG_reserved0_SHIFT 3 /* DBU :: DBU_CONFIG :: CRLF_ENABLE [02:02] */ #define DBU_DBU_CONFIG_CRLF_ENABLE_MASK 0x00000004 #define DBU_DBU_CONFIG_CRLF_ENABLE_ALIGN 0 #define DBU_DBU_CONFIG_CRLF_ENABLE_BITS 1 #define DBU_DBU_CONFIG_CRLF_ENABLE_SHIFT 2 /* DBU :: DBU_CONFIG :: DEBUGSM_ENABLE [01:01] */ #define DBU_DBU_CONFIG_DEBUGSM_ENABLE_MASK 0x00000002 #define DBU_DBU_CONFIG_DEBUGSM_ENABLE_ALIGN 0 #define DBU_DBU_CONFIG_DEBUGSM_ENABLE_BITS 1 #define DBU_DBU_CONFIG_DEBUGSM_ENABLE_SHIFT 1 /* DBU :: DBU_CONFIG :: TIMING_OVERRIDE [00:00] */ #define DBU_DBU_CONFIG_TIMING_OVERRIDE_MASK 0x00000001 #define DBU_DBU_CONFIG_TIMING_OVERRIDE_ALIGN 0 #define DBU_DBU_CONFIG_TIMING_OVERRIDE_BITS 1 #define DBU_DBU_CONFIG_TIMING_OVERRIDE_SHIFT 0 /**************************************************************************** * DBU :: DBU_TIMING ***************************************************************************/ /* DBU :: DBU_TIMING :: BIT_INTERVAL [31:16] */ #define DBU_DBU_TIMING_BIT_INTERVAL_MASK 0xffff0000 #define DBU_DBU_TIMING_BIT_INTERVAL_ALIGN 0 #define DBU_DBU_TIMING_BIT_INTERVAL_BITS 16 #define DBU_DBU_TIMING_BIT_INTERVAL_SHIFT 16 /* DBU :: DBU_TIMING :: FB_SMPL_OFFSET [15:00] */ #define DBU_DBU_TIMING_FB_SMPL_OFFSET_MASK 0x0000ffff #define DBU_DBU_TIMING_FB_SMPL_OFFSET_ALIGN 0 #define DBU_DBU_TIMING_FB_SMPL_OFFSET_BITS 16 #define DBU_DBU_TIMING_FB_SMPL_OFFSET_SHIFT 0 /**************************************************************************** * DBU :: DBU_RXDATA ***************************************************************************/ /* DBU :: DBU_RXDATA :: reserved0 [31:09] */ #define DBU_DBU_RXDATA_reserved0_MASK 0xfffffe00 #define DBU_DBU_RXDATA_reserved0_ALIGN 0 #define DBU_DBU_RXDATA_reserved0_BITS 23 #define DBU_DBU_RXDATA_reserved0_SHIFT 9 /* DBU :: DBU_RXDATA :: ERROR [08:08] */ #define DBU_DBU_RXDATA_ERROR_MASK 0x00000100 #define DBU_DBU_RXDATA_ERROR_ALIGN 0 #define DBU_DBU_RXDATA_ERROR_BITS 1 #define DBU_DBU_RXDATA_ERROR_SHIFT 8 /* DBU :: DBU_RXDATA :: VALUE [07:00] */ #define DBU_DBU_RXDATA_VALUE_MASK 0x000000ff #define DBU_DBU_RXDATA_VALUE_ALIGN 0 #define DBU_DBU_RXDATA_VALUE_BITS 8 #define DBU_DBU_RXDATA_VALUE_SHIFT 0 /**************************************************************************** * DBU :: DBU_TXDATA ***************************************************************************/ /* DBU :: DBU_TXDATA :: reserved0 [31:08] */ #define DBU_DBU_TXDATA_reserved0_MASK 0xffffff00 #define DBU_DBU_TXDATA_reserved0_ALIGN 0 #define DBU_DBU_TXDATA_reserved0_BITS 24 #define DBU_DBU_TXDATA_reserved0_SHIFT 8 /* DBU :: DBU_TXDATA :: VALUE [07:00] */ #define DBU_DBU_TXDATA_VALUE_MASK 0x000000ff #define DBU_DBU_TXDATA_VALUE_ALIGN 0 #define DBU_DBU_TXDATA_VALUE_BITS 8 #define DBU_DBU_TXDATA_VALUE_SHIFT 0 /**************************************************************************** * BCM70012_DBU_TOP_DBU_RGR_BRIDGE ***************************************************************************/ /**************************************************************************** * DBU_RGR_BRIDGE :: REVISION ***************************************************************************/ /* DBU_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define DBU_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define DBU_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 #define DBU_RGR_BRIDGE_REVISION_reserved0_BITS 16 #define DBU_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 /* DBU_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define DBU_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define DBU_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 #define DBU_RGR_BRIDGE_REVISION_MAJOR_BITS 8 #define DBU_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* DBU_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ #define DBU_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define DBU_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 #define DBU_RGR_BRIDGE_REVISION_MINOR_BITS 8 #define DBU_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 /**************************************************************************** * DBU_RGR_BRIDGE :: CTRL ***************************************************************************/ /* DBU_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ #define DBU_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc #define DBU_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 #define DBU_RGR_BRIDGE_CTRL_reserved0_BITS 30 #define DBU_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 /* DBU_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ #define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 #define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 #define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 #define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 #define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 #define DBU_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 /* DBU_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ #define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 #define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 #define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 #define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 #define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 #define DBU_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 /**************************************************************************** * DBU_RGR_BRIDGE :: RBUS_TIMER ***************************************************************************/ /* DBU_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ #define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 #define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 #define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 #define DBU_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 /* DBU_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ #define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff #define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 #define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 #define DBU_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 /**************************************************************************** * DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 ***************************************************************************/ /* DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 /* DBU_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 #define DBU_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 /**************************************************************************** * DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 ***************************************************************************/ /* DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 /* DBU_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 #define DBU_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 /**************************************************************************** * BCM70012_OTP_TOP_OTP ***************************************************************************/ /**************************************************************************** * OTP :: CONFIG_INFO ***************************************************************************/ /* OTP :: CONFIG_INFO :: reserved0 [31:22] */ #define OTP_CONFIG_INFO_reserved0_MASK 0xffc00000 #define OTP_CONFIG_INFO_reserved0_ALIGN 0 #define OTP_CONFIG_INFO_reserved0_BITS 10 #define OTP_CONFIG_INFO_reserved0_SHIFT 22 /* OTP :: CONFIG_INFO :: SELVL [21:20] */ #define OTP_CONFIG_INFO_SELVL_MASK 0x00300000 #define OTP_CONFIG_INFO_SELVL_ALIGN 0 #define OTP_CONFIG_INFO_SELVL_BITS 2 #define OTP_CONFIG_INFO_SELVL_SHIFT 20 /* OTP :: CONFIG_INFO :: reserved1 [19:17] */ #define OTP_CONFIG_INFO_reserved1_MASK 0x000e0000 #define OTP_CONFIG_INFO_reserved1_ALIGN 0 #define OTP_CONFIG_INFO_reserved1_BITS 3 #define OTP_CONFIG_INFO_reserved1_SHIFT 17 /* OTP :: CONFIG_INFO :: PTEST [16:16] */ #define OTP_CONFIG_INFO_PTEST_MASK 0x00010000 #define OTP_CONFIG_INFO_PTEST_ALIGN 0 #define OTP_CONFIG_INFO_PTEST_BITS 1 #define OTP_CONFIG_INFO_PTEST_SHIFT 16 /* OTP :: CONFIG_INFO :: reserved2 [15:13] */ #define OTP_CONFIG_INFO_reserved2_MASK 0x0000e000 #define OTP_CONFIG_INFO_reserved2_ALIGN 0 #define OTP_CONFIG_INFO_reserved2_BITS 3 #define OTP_CONFIG_INFO_reserved2_SHIFT 13 /* OTP :: CONFIG_INFO :: MAX_REDUNDANT_ROWS [12:08] */ #define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_MASK 0x00001f00 #define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_ALIGN 0 #define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_BITS 5 #define OTP_CONFIG_INFO_MAX_REDUNDANT_ROWS_SHIFT 8 /* OTP :: CONFIG_INFO :: MAX_RETRY [07:04] */ #define OTP_CONFIG_INFO_MAX_RETRY_MASK 0x000000f0 #define OTP_CONFIG_INFO_MAX_RETRY_ALIGN 0 #define OTP_CONFIG_INFO_MAX_RETRY_BITS 4 #define OTP_CONFIG_INFO_MAX_RETRY_SHIFT 4 /* OTP :: CONFIG_INFO :: reserved3 [03:01] */ #define OTP_CONFIG_INFO_reserved3_MASK 0x0000000e #define OTP_CONFIG_INFO_reserved3_ALIGN 0 #define OTP_CONFIG_INFO_reserved3_BITS 3 #define OTP_CONFIG_INFO_reserved3_SHIFT 1 /* OTP :: CONFIG_INFO :: PROG_MODE [00:00] */ #define OTP_CONFIG_INFO_PROG_MODE_MASK 0x00000001 #define OTP_CONFIG_INFO_PROG_MODE_ALIGN 0 #define OTP_CONFIG_INFO_PROG_MODE_BITS 1 #define OTP_CONFIG_INFO_PROG_MODE_SHIFT 0 /**************************************************************************** * OTP :: CMD ***************************************************************************/ /* OTP :: CMD :: reserved0 [31:02] */ #define OTP_CMD_reserved0_MASK 0xfffffffc #define OTP_CMD_reserved0_ALIGN 0 #define OTP_CMD_reserved0_BITS 30 #define OTP_CMD_reserved0_SHIFT 2 /* OTP :: CMD :: KEYS_AVAIL [01:01] */ #define OTP_CMD_KEYS_AVAIL_MASK 0x00000002 #define OTP_CMD_KEYS_AVAIL_ALIGN 0 #define OTP_CMD_KEYS_AVAIL_BITS 1 #define OTP_CMD_KEYS_AVAIL_SHIFT 1 /* OTP :: CMD :: PROGRAM_OTP [00:00] */ #define OTP_CMD_PROGRAM_OTP_MASK 0x00000001 #define OTP_CMD_PROGRAM_OTP_ALIGN 0 #define OTP_CMD_PROGRAM_OTP_BITS 1 #define OTP_CMD_PROGRAM_OTP_SHIFT 0 /**************************************************************************** * OTP :: STATUS ***************************************************************************/ /* OTP :: STATUS :: reserved0 [31:30] */ #define OTP_STATUS_reserved0_MASK 0xc0000000 #define OTP_STATUS_reserved0_ALIGN 0 #define OTP_STATUS_reserved0_BITS 2 #define OTP_STATUS_reserved0_SHIFT 30 /* OTP :: STATUS :: TOTAL_RETRIES [29:17] */ #define OTP_STATUS_TOTAL_RETRIES_MASK 0x3ffe0000 #define OTP_STATUS_TOTAL_RETRIES_ALIGN 0 #define OTP_STATUS_TOTAL_RETRIES_BITS 13 #define OTP_STATUS_TOTAL_RETRIES_SHIFT 17 /* OTP :: STATUS :: ROWS_USED [16:12] */ #define OTP_STATUS_ROWS_USED_MASK 0x0001f000 #define OTP_STATUS_ROWS_USED_ALIGN 0 #define OTP_STATUS_ROWS_USED_BITS 5 #define OTP_STATUS_ROWS_USED_SHIFT 12 /* OTP :: STATUS :: MAX_RETRIES [11:08] */ #define OTP_STATUS_MAX_RETRIES_MASK 0x00000f00 #define OTP_STATUS_MAX_RETRIES_ALIGN 0 #define OTP_STATUS_MAX_RETRIES_BITS 4 #define OTP_STATUS_MAX_RETRIES_SHIFT 8 /* OTP :: STATUS :: PROG_STATUS [07:04] */ #define OTP_STATUS_PROG_STATUS_MASK 0x000000f0 #define OTP_STATUS_PROG_STATUS_ALIGN 0 #define OTP_STATUS_PROG_STATUS_BITS 4 #define OTP_STATUS_PROG_STATUS_SHIFT 4 /* OTP :: STATUS :: reserved1 [03:03] */ #define OTP_STATUS_reserved1_MASK 0x00000008 #define OTP_STATUS_reserved1_ALIGN 0 #define OTP_STATUS_reserved1_BITS 1 #define OTP_STATUS_reserved1_SHIFT 3 /* OTP :: STATUS :: CHECKSUM_MISMATCH [02:02] */ #define OTP_STATUS_CHECKSUM_MISMATCH_MASK 0x00000004 #define OTP_STATUS_CHECKSUM_MISMATCH_ALIGN 0 #define OTP_STATUS_CHECKSUM_MISMATCH_BITS 1 #define OTP_STATUS_CHECKSUM_MISMATCH_SHIFT 2 /* OTP :: STATUS :: INSUFFICIENT_ROWS [01:01] */ #define OTP_STATUS_INSUFFICIENT_ROWS_MASK 0x00000002 #define OTP_STATUS_INSUFFICIENT_ROWS_ALIGN 0 #define OTP_STATUS_INSUFFICIENT_ROWS_BITS 1 #define OTP_STATUS_INSUFFICIENT_ROWS_SHIFT 1 /* OTP :: STATUS :: PROGRAMMED [00:00] */ #define OTP_STATUS_PROGRAMMED_MASK 0x00000001 #define OTP_STATUS_PROGRAMMED_ALIGN 0 #define OTP_STATUS_PROGRAMMED_BITS 1 #define OTP_STATUS_PROGRAMMED_SHIFT 0 /**************************************************************************** * OTP :: CONTENT_MISC ***************************************************************************/ /* OTP :: CONTENT_MISC :: reserved0 [31:06] */ #define OTP_CONTENT_MISC_reserved0_MASK 0xffffffc0 #define OTP_CONTENT_MISC_reserved0_ALIGN 0 #define OTP_CONTENT_MISC_reserved0_BITS 26 #define OTP_CONTENT_MISC_reserved0_SHIFT 6 /* OTP :: CONTENT_MISC :: DCI_SECURITY_ENABLE [05:05] */ #define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_MASK 0x00000020 #define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_ALIGN 0 #define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_BITS 1 #define OTP_CONTENT_MISC_DCI_SECURITY_ENABLE_SHIFT 5 /* OTP :: CONTENT_MISC :: AES_SECURITY_ENABLE [04:04] */ #define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_MASK 0x00000010 #define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_ALIGN 0 #define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_BITS 1 #define OTP_CONTENT_MISC_AES_SECURITY_ENABLE_SHIFT 4 /* OTP :: CONTENT_MISC :: DISABLE_JTAG [03:03] */ #define OTP_CONTENT_MISC_DISABLE_JTAG_MASK 0x00000008 #define OTP_CONTENT_MISC_DISABLE_JTAG_ALIGN 0 #define OTP_CONTENT_MISC_DISABLE_JTAG_BITS 1 #define OTP_CONTENT_MISC_DISABLE_JTAG_SHIFT 3 /* OTP :: CONTENT_MISC :: DISABLE_UART [02:02] */ #define OTP_CONTENT_MISC_DISABLE_UART_MASK 0x00000004 #define OTP_CONTENT_MISC_DISABLE_UART_ALIGN 0 #define OTP_CONTENT_MISC_DISABLE_UART_BITS 1 #define OTP_CONTENT_MISC_DISABLE_UART_SHIFT 2 /* OTP :: CONTENT_MISC :: ENABLE_RANDOMIZATION [01:01] */ #define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_MASK 0x00000002 #define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_ALIGN 0 #define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_BITS 1 #define OTP_CONTENT_MISC_ENABLE_RANDOMIZATION_SHIFT 1 /* OTP :: CONTENT_MISC :: OTP_SECURITY_ENABLE [00:00] */ #define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_MASK 0x00000001 #define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_ALIGN 0 #define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_BITS 1 #define OTP_CONTENT_MISC_OTP_SECURITY_ENABLE_SHIFT 0 /**************************************************************************** * OTP :: CONTENT_AES_0 ***************************************************************************/ /* OTP :: CONTENT_AES_0 :: AES_KEY_0 [31:00] */ #define OTP_CONTENT_AES_0_AES_KEY_0_MASK 0xffffffff #define OTP_CONTENT_AES_0_AES_KEY_0_ALIGN 0 #define OTP_CONTENT_AES_0_AES_KEY_0_BITS 32 #define OTP_CONTENT_AES_0_AES_KEY_0_SHIFT 0 /**************************************************************************** * OTP :: CONTENT_AES_1 ***************************************************************************/ /* OTP :: CONTENT_AES_1 :: AES_KEY_1 [31:00] */ #define OTP_CONTENT_AES_1_AES_KEY_1_MASK 0xffffffff #define OTP_CONTENT_AES_1_AES_KEY_1_ALIGN 0 #define OTP_CONTENT_AES_1_AES_KEY_1_BITS 32 #define OTP_CONTENT_AES_1_AES_KEY_1_SHIFT 0 /**************************************************************************** * OTP :: CONTENT_AES_2 ***************************************************************************/ /* OTP :: CONTENT_AES_2 :: AES_KEY_2 [31:00] */ #define OTP_CONTENT_AES_2_AES_KEY_2_MASK 0xffffffff #define OTP_CONTENT_AES_2_AES_KEY_2_ALIGN 0 #define OTP_CONTENT_AES_2_AES_KEY_2_BITS 32 #define OTP_CONTENT_AES_2_AES_KEY_2_SHIFT 0 /**************************************************************************** * OTP :: CONTENT_AES_3 ***************************************************************************/ /* OTP :: CONTENT_AES_3 :: AES_KEY_3 [31:00] */ #define OTP_CONTENT_AES_3_AES_KEY_3_MASK 0xffffffff #define OTP_CONTENT_AES_3_AES_KEY_3_ALIGN 0 #define OTP_CONTENT_AES_3_AES_KEY_3_BITS 32 #define OTP_CONTENT_AES_3_AES_KEY_3_SHIFT 0 /**************************************************************************** * OTP :: CONTENT_SHA_0 ***************************************************************************/ /* OTP :: CONTENT_SHA_0 :: SHA_KEY_0 [31:00] */ #define OTP_CONTENT_SHA_0_SHA_KEY_0_MASK 0xffffffff #define OTP_CONTENT_SHA_0_SHA_KEY_0_ALIGN 0 #define OTP_CONTENT_SHA_0_SHA_KEY_0_BITS 32 #define OTP_CONTENT_SHA_0_SHA_KEY_0_SHIFT 0 /**************************************************************************** * OTP :: CONTENT_SHA_1 ***************************************************************************/ /* OTP :: CONTENT_SHA_1 :: SHA_KEY_1 [31:00] */ #define OTP_CONTENT_SHA_1_SHA_KEY_1_MASK 0xffffffff #define OTP_CONTENT_SHA_1_SHA_KEY_1_ALIGN 0 #define OTP_CONTENT_SHA_1_SHA_KEY_1_BITS 32 #define OTP_CONTENT_SHA_1_SHA_KEY_1_SHIFT 0 /**************************************************************************** * OTP :: CONTENT_SHA_2 ***************************************************************************/ /* OTP :: CONTENT_SHA_2 :: SHA_KEY_2 [31:00] */ #define OTP_CONTENT_SHA_2_SHA_KEY_2_MASK 0xffffffff #define OTP_CONTENT_SHA_2_SHA_KEY_2_ALIGN 0 #define OTP_CONTENT_SHA_2_SHA_KEY_2_BITS 32 #define OTP_CONTENT_SHA_2_SHA_KEY_2_SHIFT 0 /**************************************************************************** * OTP :: CONTENT_SHA_3 ***************************************************************************/ /* OTP :: CONTENT_SHA_3 :: SHA_KEY_3 [31:00] */ #define OTP_CONTENT_SHA_3_SHA_KEY_3_MASK 0xffffffff #define OTP_CONTENT_SHA_3_SHA_KEY_3_ALIGN 0 #define OTP_CONTENT_SHA_3_SHA_KEY_3_BITS 32 #define OTP_CONTENT_SHA_3_SHA_KEY_3_SHIFT 0 /**************************************************************************** * OTP :: CONTENT_SHA_4 ***************************************************************************/ /* OTP :: CONTENT_SHA_4 :: SHA_KEY_4 [31:00] */ #define OTP_CONTENT_SHA_4_SHA_KEY_4_MASK 0xffffffff #define OTP_CONTENT_SHA_4_SHA_KEY_4_ALIGN 0 #define OTP_CONTENT_SHA_4_SHA_KEY_4_BITS 32 #define OTP_CONTENT_SHA_4_SHA_KEY_4_SHIFT 0 /**************************************************************************** * OTP :: CONTENT_SHA_5 ***************************************************************************/ /* OTP :: CONTENT_SHA_5 :: SHA_KEY_5 [31:00] */ #define OTP_CONTENT_SHA_5_SHA_KEY_5_MASK 0xffffffff #define OTP_CONTENT_SHA_5_SHA_KEY_5_ALIGN 0 #define OTP_CONTENT_SHA_5_SHA_KEY_5_BITS 32 #define OTP_CONTENT_SHA_5_SHA_KEY_5_SHIFT 0 /**************************************************************************** * OTP :: CONTENT_SHA_6 ***************************************************************************/ /* OTP :: CONTENT_SHA_6 :: SHA_KEY_6 [31:00] */ #define OTP_CONTENT_SHA_6_SHA_KEY_6_MASK 0xffffffff #define OTP_CONTENT_SHA_6_SHA_KEY_6_ALIGN 0 #define OTP_CONTENT_SHA_6_SHA_KEY_6_BITS 32 #define OTP_CONTENT_SHA_6_SHA_KEY_6_SHIFT 0 /**************************************************************************** * OTP :: CONTENT_SHA_7 ***************************************************************************/ /* OTP :: CONTENT_SHA_7 :: SHA_KEY_7 [31:00] */ #define OTP_CONTENT_SHA_7_SHA_KEY_7_MASK 0xffffffff #define OTP_CONTENT_SHA_7_SHA_KEY_7_ALIGN 0 #define OTP_CONTENT_SHA_7_SHA_KEY_7_BITS 32 #define OTP_CONTENT_SHA_7_SHA_KEY_7_SHIFT 0 /**************************************************************************** * OTP :: CONTENT_CHECKSUM ***************************************************************************/ /* OTP :: CONTENT_CHECKSUM :: reserved0 [31:16] */ #define OTP_CONTENT_CHECKSUM_reserved0_MASK 0xffff0000 #define OTP_CONTENT_CHECKSUM_reserved0_ALIGN 0 #define OTP_CONTENT_CHECKSUM_reserved0_BITS 16 #define OTP_CONTENT_CHECKSUM_reserved0_SHIFT 16 /* OTP :: CONTENT_CHECKSUM :: CHECKSUM [15:00] */ #define OTP_CONTENT_CHECKSUM_CHECKSUM_MASK 0x0000ffff #define OTP_CONTENT_CHECKSUM_CHECKSUM_ALIGN 0 #define OTP_CONTENT_CHECKSUM_CHECKSUM_BITS 16 #define OTP_CONTENT_CHECKSUM_CHECKSUM_SHIFT 0 /**************************************************************************** * OTP :: PROG_CTRL ***************************************************************************/ /* OTP :: PROG_CTRL :: reserved0 [31:02] */ #define OTP_PROG_CTRL_reserved0_MASK 0xfffffffc #define OTP_PROG_CTRL_reserved0_ALIGN 0 #define OTP_PROG_CTRL_reserved0_BITS 30 #define OTP_PROG_CTRL_reserved0_SHIFT 2 /* OTP :: PROG_CTRL :: ENABLE [01:01] */ #define OTP_PROG_CTRL_ENABLE_MASK 0x00000002 #define OTP_PROG_CTRL_ENABLE_ALIGN 0 #define OTP_PROG_CTRL_ENABLE_BITS 1 #define OTP_PROG_CTRL_ENABLE_SHIFT 1 /* OTP :: PROG_CTRL :: RST [00:00] */ #define OTP_PROG_CTRL_RST_MASK 0x00000001 #define OTP_PROG_CTRL_RST_ALIGN 0 #define OTP_PROG_CTRL_RST_BITS 1 #define OTP_PROG_CTRL_RST_SHIFT 0 /**************************************************************************** * OTP :: PROG_STATUS ***************************************************************************/ /* OTP :: PROG_STATUS :: reserved0 [31:02] */ #define OTP_PROG_STATUS_reserved0_MASK 0xfffffffc #define OTP_PROG_STATUS_reserved0_ALIGN 0 #define OTP_PROG_STATUS_reserved0_BITS 30 #define OTP_PROG_STATUS_reserved0_SHIFT 2 /* OTP :: PROG_STATUS :: ORDY [01:01] */ #define OTP_PROG_STATUS_ORDY_MASK 0x00000002 #define OTP_PROG_STATUS_ORDY_ALIGN 0 #define OTP_PROG_STATUS_ORDY_BITS 1 #define OTP_PROG_STATUS_ORDY_SHIFT 1 /* OTP :: PROG_STATUS :: IRDY [00:00] */ #define OTP_PROG_STATUS_IRDY_MASK 0x00000001 #define OTP_PROG_STATUS_IRDY_ALIGN 0 #define OTP_PROG_STATUS_IRDY_BITS 1 #define OTP_PROG_STATUS_IRDY_SHIFT 0 /**************************************************************************** * OTP :: PROG_PULSE ***************************************************************************/ /* OTP :: PROG_PULSE :: PROG_HI [31:00] */ #define OTP_PROG_PULSE_PROG_HI_MASK 0xffffffff #define OTP_PROG_PULSE_PROG_HI_ALIGN 0 #define OTP_PROG_PULSE_PROG_HI_BITS 32 #define OTP_PROG_PULSE_PROG_HI_SHIFT 0 /**************************************************************************** * OTP :: VERIFY_PULSE ***************************************************************************/ /* OTP :: VERIFY_PULSE :: PROG_LOW [31:16] */ #define OTP_VERIFY_PULSE_PROG_LOW_MASK 0xffff0000 #define OTP_VERIFY_PULSE_PROG_LOW_ALIGN 0 #define OTP_VERIFY_PULSE_PROG_LOW_BITS 16 #define OTP_VERIFY_PULSE_PROG_LOW_SHIFT 16 /* OTP :: VERIFY_PULSE :: VERIFY [15:00] */ #define OTP_VERIFY_PULSE_VERIFY_MASK 0x0000ffff #define OTP_VERIFY_PULSE_VERIFY_ALIGN 0 #define OTP_VERIFY_PULSE_VERIFY_BITS 16 #define OTP_VERIFY_PULSE_VERIFY_SHIFT 0 /**************************************************************************** * OTP :: PROG_MASK ***************************************************************************/ /* OTP :: PROG_MASK :: reserved0 [31:17] */ #define OTP_PROG_MASK_reserved0_MASK 0xfffe0000 #define OTP_PROG_MASK_reserved0_ALIGN 0 #define OTP_PROG_MASK_reserved0_BITS 15 #define OTP_PROG_MASK_reserved0_SHIFT 17 /* OTP :: PROG_MASK :: PROG_MASK [16:00] */ #define OTP_PROG_MASK_PROG_MASK_MASK 0x0001ffff #define OTP_PROG_MASK_PROG_MASK_ALIGN 0 #define OTP_PROG_MASK_PROG_MASK_BITS 17 #define OTP_PROG_MASK_PROG_MASK_SHIFT 0 /**************************************************************************** * OTP :: DATA_INPUT ***************************************************************************/ /* OTP :: DATA_INPUT :: reserved0 [31:31] */ #define OTP_DATA_INPUT_reserved0_MASK 0x80000000 #define OTP_DATA_INPUT_reserved0_ALIGN 0 #define OTP_DATA_INPUT_reserved0_BITS 1 #define OTP_DATA_INPUT_reserved0_SHIFT 31 /* OTP :: DATA_INPUT :: CMD [30:28] */ #define OTP_DATA_INPUT_CMD_MASK 0x70000000 #define OTP_DATA_INPUT_CMD_ALIGN 0 #define OTP_DATA_INPUT_CMD_BITS 3 #define OTP_DATA_INPUT_CMD_SHIFT 28 /* OTP :: DATA_INPUT :: reserved1 [27:26] */ #define OTP_DATA_INPUT_reserved1_MASK 0x0c000000 #define OTP_DATA_INPUT_reserved1_ALIGN 0 #define OTP_DATA_INPUT_reserved1_BITS 2 #define OTP_DATA_INPUT_reserved1_SHIFT 26 /* OTP :: DATA_INPUT :: ADDR [25:20] */ #define OTP_DATA_INPUT_ADDR_MASK 0x03f00000 #define OTP_DATA_INPUT_ADDR_ALIGN 0 #define OTP_DATA_INPUT_ADDR_BITS 6 #define OTP_DATA_INPUT_ADDR_SHIFT 20 /* OTP :: DATA_INPUT :: reserved2 [19:18] */ #define OTP_DATA_INPUT_reserved2_MASK 0x000c0000 #define OTP_DATA_INPUT_reserved2_ALIGN 0 #define OTP_DATA_INPUT_reserved2_BITS 2 #define OTP_DATA_INPUT_reserved2_SHIFT 18 /* OTP :: DATA_INPUT :: WRCOL [17:17] */ #define OTP_DATA_INPUT_WRCOL_MASK 0x00020000 #define OTP_DATA_INPUT_WRCOL_ALIGN 0 #define OTP_DATA_INPUT_WRCOL_BITS 1 #define OTP_DATA_INPUT_WRCOL_SHIFT 17 /* OTP :: DATA_INPUT :: DIN [16:00] */ #define OTP_DATA_INPUT_DIN_MASK 0x0001ffff #define OTP_DATA_INPUT_DIN_ALIGN 0 #define OTP_DATA_INPUT_DIN_BITS 17 #define OTP_DATA_INPUT_DIN_SHIFT 0 /**************************************************************************** * OTP :: DATA_OUTPUT ***************************************************************************/ /* OTP :: DATA_OUTPUT :: reserved0 [31:17] */ #define OTP_DATA_OUTPUT_reserved0_MASK 0xfffe0000 #define OTP_DATA_OUTPUT_reserved0_ALIGN 0 #define OTP_DATA_OUTPUT_reserved0_BITS 15 #define OTP_DATA_OUTPUT_reserved0_SHIFT 17 /* OTP :: DATA_OUTPUT :: DOUT [16:00] */ #define OTP_DATA_OUTPUT_DOUT_MASK 0x0001ffff #define OTP_DATA_OUTPUT_DOUT_ALIGN 0 #define OTP_DATA_OUTPUT_DOUT_BITS 17 #define OTP_DATA_OUTPUT_DOUT_SHIFT 0 /**************************************************************************** * BCM70012_OTP_TOP_OTP_GR_BRIDGE ***************************************************************************/ /**************************************************************************** * OTP_GR_BRIDGE :: REVISION ***************************************************************************/ /* OTP_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define OTP_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define OTP_GR_BRIDGE_REVISION_reserved0_ALIGN 0 #define OTP_GR_BRIDGE_REVISION_reserved0_BITS 16 #define OTP_GR_BRIDGE_REVISION_reserved0_SHIFT 16 /* OTP_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define OTP_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define OTP_GR_BRIDGE_REVISION_MAJOR_ALIGN 0 #define OTP_GR_BRIDGE_REVISION_MAJOR_BITS 8 #define OTP_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* OTP_GR_BRIDGE :: REVISION :: MINOR [07:00] */ #define OTP_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define OTP_GR_BRIDGE_REVISION_MINOR_ALIGN 0 #define OTP_GR_BRIDGE_REVISION_MINOR_BITS 8 #define OTP_GR_BRIDGE_REVISION_MINOR_SHIFT 0 /**************************************************************************** * OTP_GR_BRIDGE :: CTRL ***************************************************************************/ /* OTP_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ #define OTP_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe #define OTP_GR_BRIDGE_CTRL_reserved0_ALIGN 0 #define OTP_GR_BRIDGE_CTRL_reserved0_BITS 31 #define OTP_GR_BRIDGE_CTRL_reserved0_SHIFT 1 /* OTP_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ #define OTP_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 #define OTP_GR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 #define OTP_GR_BRIDGE_CTRL_gisb_error_intr_BITS 1 #define OTP_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 #define OTP_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 #define OTP_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 /**************************************************************************** * OTP_GR_BRIDGE :: SPARE_SW_RESET_0 ***************************************************************************/ /* OTP_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 /* OTP_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 #define OTP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 /**************************************************************************** * OTP_GR_BRIDGE :: SPARE_SW_RESET_1 ***************************************************************************/ /* OTP_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 /* OTP_GR_BRIDGE :: SPARE_SW_RESET_1 :: OTP_00_SW_RESET [00:00] */ #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_MASK 0x00000001 #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_ALIGN 0 #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_BITS 1 #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_SHIFT 0 #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_DEASSERT 0 #define OTP_GR_BRIDGE_SPARE_SW_RESET_1_OTP_00_SW_RESET_ASSERT 1 /**************************************************************************** * BCM70012_AES_TOP_AES ***************************************************************************/ /**************************************************************************** * AES :: CONFIG_INFO ***************************************************************************/ /* AES :: CONFIG_INFO :: SWAP [31:31] */ #define AES_CONFIG_INFO_SWAP_MASK 0x80000000 #define AES_CONFIG_INFO_SWAP_ALIGN 0 #define AES_CONFIG_INFO_SWAP_BITS 1 #define AES_CONFIG_INFO_SWAP_SHIFT 31 /* AES :: CONFIG_INFO :: reserved0 [30:19] */ #define AES_CONFIG_INFO_reserved0_MASK 0x7ff80000 #define AES_CONFIG_INFO_reserved0_ALIGN 0 #define AES_CONFIG_INFO_reserved0_BITS 12 #define AES_CONFIG_INFO_reserved0_SHIFT 19 /* AES :: CONFIG_INFO :: OFFSET [18:02] */ #define AES_CONFIG_INFO_OFFSET_MASK 0x0007fffc #define AES_CONFIG_INFO_OFFSET_ALIGN 0 #define AES_CONFIG_INFO_OFFSET_BITS 17 #define AES_CONFIG_INFO_OFFSET_SHIFT 2 /* AES :: CONFIG_INFO :: reserved1 [01:00] */ #define AES_CONFIG_INFO_reserved1_MASK 0x00000003 #define AES_CONFIG_INFO_reserved1_ALIGN 0 #define AES_CONFIG_INFO_reserved1_BITS 2 #define AES_CONFIG_INFO_reserved1_SHIFT 0 /**************************************************************************** * AES :: CMD ***************************************************************************/ /* AES :: CMD :: reserved0 [31:13] */ #define AES_CMD_reserved0_MASK 0xffffe000 #define AES_CMD_reserved0_ALIGN 0 #define AES_CMD_reserved0_BITS 19 #define AES_CMD_reserved0_SHIFT 13 /* AES :: CMD :: WRITE_EEPROM [12:12] */ #define AES_CMD_WRITE_EEPROM_MASK 0x00001000 #define AES_CMD_WRITE_EEPROM_ALIGN 0 #define AES_CMD_WRITE_EEPROM_BITS 1 #define AES_CMD_WRITE_EEPROM_SHIFT 12 /* AES :: CMD :: reserved1 [11:09] */ #define AES_CMD_reserved1_MASK 0x00000e00 #define AES_CMD_reserved1_ALIGN 0 #define AES_CMD_reserved1_BITS 3 #define AES_CMD_reserved1_SHIFT 9 /* AES :: CMD :: START_EEPROM_COPY [08:08] */ #define AES_CMD_START_EEPROM_COPY_MASK 0x00000100 #define AES_CMD_START_EEPROM_COPY_ALIGN 0 #define AES_CMD_START_EEPROM_COPY_BITS 1 #define AES_CMD_START_EEPROM_COPY_SHIFT 8 /* AES :: CMD :: reserved2 [07:05] */ #define AES_CMD_reserved2_MASK 0x000000e0 #define AES_CMD_reserved2_ALIGN 0 #define AES_CMD_reserved2_BITS 3 #define AES_CMD_reserved2_SHIFT 5 /* AES :: CMD :: PREPARE_ENCRYPTION [04:04] */ #define AES_CMD_PREPARE_ENCRYPTION_MASK 0x00000010 #define AES_CMD_PREPARE_ENCRYPTION_ALIGN 0 #define AES_CMD_PREPARE_ENCRYPTION_BITS 1 #define AES_CMD_PREPARE_ENCRYPTION_SHIFT 4 /* AES :: CMD :: reserved3 [03:01] */ #define AES_CMD_reserved3_MASK 0x0000000e #define AES_CMD_reserved3_ALIGN 0 #define AES_CMD_reserved3_BITS 3 #define AES_CMD_reserved3_SHIFT 1 /* AES :: CMD :: START_KEY_LOAD [00:00] */ #define AES_CMD_START_KEY_LOAD_MASK 0x00000001 #define AES_CMD_START_KEY_LOAD_ALIGN 0 #define AES_CMD_START_KEY_LOAD_BITS 1 #define AES_CMD_START_KEY_LOAD_SHIFT 0 /**************************************************************************** * AES :: STATUS ***************************************************************************/ /* AES :: STATUS :: reserved0 [31:23] */ #define AES_STATUS_reserved0_MASK 0xff800000 #define AES_STATUS_reserved0_ALIGN 0 #define AES_STATUS_reserved0_BITS 9 #define AES_STATUS_reserved0_SHIFT 23 /* AES :: STATUS :: STUCK_AT_ZERO [22:22] */ #define AES_STATUS_STUCK_AT_ZERO_MASK 0x00400000 #define AES_STATUS_STUCK_AT_ZERO_ALIGN 0 #define AES_STATUS_STUCK_AT_ZERO_BITS 1 #define AES_STATUS_STUCK_AT_ZERO_SHIFT 22 /* AES :: STATUS :: STUCK_AT_ONE [21:21] */ #define AES_STATUS_STUCK_AT_ONE_MASK 0x00200000 #define AES_STATUS_STUCK_AT_ONE_ALIGN 0 #define AES_STATUS_STUCK_AT_ONE_BITS 1 #define AES_STATUS_STUCK_AT_ONE_SHIFT 21 /* AES :: STATUS :: RANDOM_READY [20:20] */ #define AES_STATUS_RANDOM_READY_MASK 0x00100000 #define AES_STATUS_RANDOM_READY_ALIGN 0 #define AES_STATUS_RANDOM_READY_BITS 1 #define AES_STATUS_RANDOM_READY_SHIFT 20 /* AES :: STATUS :: reserved1 [19:16] */ #define AES_STATUS_reserved1_MASK 0x000f0000 #define AES_STATUS_reserved1_ALIGN 0 #define AES_STATUS_reserved1_BITS 4 #define AES_STATUS_reserved1_SHIFT 16 /* AES :: STATUS :: WRITE_EEPROM_TIMEOUT [15:15] */ #define AES_STATUS_WRITE_EEPROM_TIMEOUT_MASK 0x00008000 #define AES_STATUS_WRITE_EEPROM_TIMEOUT_ALIGN 0 #define AES_STATUS_WRITE_EEPROM_TIMEOUT_BITS 1 #define AES_STATUS_WRITE_EEPROM_TIMEOUT_SHIFT 15 /* AES :: STATUS :: WRITE_DATA_MISMATCH [14:14] */ #define AES_STATUS_WRITE_DATA_MISMATCH_MASK 0x00004000 #define AES_STATUS_WRITE_DATA_MISMATCH_ALIGN 0 #define AES_STATUS_WRITE_DATA_MISMATCH_BITS 1 #define AES_STATUS_WRITE_DATA_MISMATCH_SHIFT 14 /* AES :: STATUS :: WRITE_GISB_ERROR [13:13] */ #define AES_STATUS_WRITE_GISB_ERROR_MASK 0x00002000 #define AES_STATUS_WRITE_GISB_ERROR_ALIGN 0 #define AES_STATUS_WRITE_GISB_ERROR_BITS 1 #define AES_STATUS_WRITE_GISB_ERROR_SHIFT 13 /* AES :: STATUS :: WRITE_DONE [12:12] */ #define AES_STATUS_WRITE_DONE_MASK 0x00001000 #define AES_STATUS_WRITE_DONE_ALIGN 0 #define AES_STATUS_WRITE_DONE_BITS 1 #define AES_STATUS_WRITE_DONE_SHIFT 12 /* AES :: STATUS :: reserved2 [11:11] */ #define AES_STATUS_reserved2_MASK 0x00000800 #define AES_STATUS_reserved2_ALIGN 0 #define AES_STATUS_reserved2_BITS 1 #define AES_STATUS_reserved2_SHIFT 11 /* AES :: STATUS :: COPY_EEPROM_ERROR [10:10] */ #define AES_STATUS_COPY_EEPROM_ERROR_MASK 0x00000400 #define AES_STATUS_COPY_EEPROM_ERROR_ALIGN 0 #define AES_STATUS_COPY_EEPROM_ERROR_BITS 1 #define AES_STATUS_COPY_EEPROM_ERROR_SHIFT 10 /* AES :: STATUS :: COPY_GISB_ERROR [09:09] */ #define AES_STATUS_COPY_GISB_ERROR_MASK 0x00000200 #define AES_STATUS_COPY_GISB_ERROR_ALIGN 0 #define AES_STATUS_COPY_GISB_ERROR_BITS 1 #define AES_STATUS_COPY_GISB_ERROR_SHIFT 9 /* AES :: STATUS :: COPY_DONE [08:08] */ #define AES_STATUS_COPY_DONE_MASK 0x00000100 #define AES_STATUS_COPY_DONE_ALIGN 0 #define AES_STATUS_COPY_DONE_BITS 1 #define AES_STATUS_COPY_DONE_SHIFT 8 /* AES :: STATUS :: PREPARE_EEPROM_TIMEOUT [07:07] */ #define AES_STATUS_PREPARE_EEPROM_TIMEOUT_MASK 0x00000080 #define AES_STATUS_PREPARE_EEPROM_TIMEOUT_ALIGN 0 #define AES_STATUS_PREPARE_EEPROM_TIMEOUT_BITS 1 #define AES_STATUS_PREPARE_EEPROM_TIMEOUT_SHIFT 7 /* AES :: STATUS :: PREPARE_DATA_MISMATCH [06:06] */ #define AES_STATUS_PREPARE_DATA_MISMATCH_MASK 0x00000040 #define AES_STATUS_PREPARE_DATA_MISMATCH_ALIGN 0 #define AES_STATUS_PREPARE_DATA_MISMATCH_BITS 1 #define AES_STATUS_PREPARE_DATA_MISMATCH_SHIFT 6 /* AES :: STATUS :: PREPARE_GISB_ERROR [05:05] */ #define AES_STATUS_PREPARE_GISB_ERROR_MASK 0x00000020 #define AES_STATUS_PREPARE_GISB_ERROR_ALIGN 0 #define AES_STATUS_PREPARE_GISB_ERROR_BITS 1 #define AES_STATUS_PREPARE_GISB_ERROR_SHIFT 5 /* AES :: STATUS :: PREPARE_DONE [04:04] */ #define AES_STATUS_PREPARE_DONE_MASK 0x00000010 #define AES_STATUS_PREPARE_DONE_ALIGN 0 #define AES_STATUS_PREPARE_DONE_BITS 1 #define AES_STATUS_PREPARE_DONE_SHIFT 4 /* AES :: STATUS :: reserved3 [03:02] */ #define AES_STATUS_reserved3_MASK 0x0000000c #define AES_STATUS_reserved3_ALIGN 0 #define AES_STATUS_reserved3_BITS 2 #define AES_STATUS_reserved3_SHIFT 2 /* AES :: STATUS :: KEY_LOAD_GISB_ERROR [01:01] */ #define AES_STATUS_KEY_LOAD_GISB_ERROR_MASK 0x00000002 #define AES_STATUS_KEY_LOAD_GISB_ERROR_ALIGN 0 #define AES_STATUS_KEY_LOAD_GISB_ERROR_BITS 1 #define AES_STATUS_KEY_LOAD_GISB_ERROR_SHIFT 1 /* AES :: STATUS :: KEY_LOAD_DONE [00:00] */ #define AES_STATUS_KEY_LOAD_DONE_MASK 0x00000001 #define AES_STATUS_KEY_LOAD_DONE_ALIGN 0 #define AES_STATUS_KEY_LOAD_DONE_BITS 1 #define AES_STATUS_KEY_LOAD_DONE_SHIFT 0 /**************************************************************************** * AES :: EEPROM_CONFIG ***************************************************************************/ /* AES :: EEPROM_CONFIG :: LENGTH [31:20] */ #define AES_EEPROM_CONFIG_LENGTH_MASK 0xfff00000 #define AES_EEPROM_CONFIG_LENGTH_ALIGN 0 #define AES_EEPROM_CONFIG_LENGTH_BITS 12 #define AES_EEPROM_CONFIG_LENGTH_SHIFT 20 /* AES :: EEPROM_CONFIG :: reserved0 [19:16] */ #define AES_EEPROM_CONFIG_reserved0_MASK 0x000f0000 #define AES_EEPROM_CONFIG_reserved0_ALIGN 0 #define AES_EEPROM_CONFIG_reserved0_BITS 4 #define AES_EEPROM_CONFIG_reserved0_SHIFT 16 /* AES :: EEPROM_CONFIG :: START_ADDR [15:02] */ #define AES_EEPROM_CONFIG_START_ADDR_MASK 0x0000fffc #define AES_EEPROM_CONFIG_START_ADDR_ALIGN 0 #define AES_EEPROM_CONFIG_START_ADDR_BITS 14 #define AES_EEPROM_CONFIG_START_ADDR_SHIFT 2 /* AES :: EEPROM_CONFIG :: reserved1 [01:00] */ #define AES_EEPROM_CONFIG_reserved1_MASK 0x00000003 #define AES_EEPROM_CONFIG_reserved1_ALIGN 0 #define AES_EEPROM_CONFIG_reserved1_BITS 2 #define AES_EEPROM_CONFIG_reserved1_SHIFT 0 /**************************************************************************** * AES :: EEPROM_DATA_0 ***************************************************************************/ /* AES :: EEPROM_DATA_0 :: DATA [31:00] */ #define AES_EEPROM_DATA_0_DATA_MASK 0xffffffff #define AES_EEPROM_DATA_0_DATA_ALIGN 0 #define AES_EEPROM_DATA_0_DATA_BITS 32 #define AES_EEPROM_DATA_0_DATA_SHIFT 0 /**************************************************************************** * AES :: EEPROM_DATA_1 ***************************************************************************/ /* AES :: EEPROM_DATA_1 :: DATA [31:00] */ #define AES_EEPROM_DATA_1_DATA_MASK 0xffffffff #define AES_EEPROM_DATA_1_DATA_ALIGN 0 #define AES_EEPROM_DATA_1_DATA_BITS 32 #define AES_EEPROM_DATA_1_DATA_SHIFT 0 /**************************************************************************** * AES :: EEPROM_DATA_2 ***************************************************************************/ /* AES :: EEPROM_DATA_2 :: DATA [31:00] */ #define AES_EEPROM_DATA_2_DATA_MASK 0xffffffff #define AES_EEPROM_DATA_2_DATA_ALIGN 0 #define AES_EEPROM_DATA_2_DATA_BITS 32 #define AES_EEPROM_DATA_2_DATA_SHIFT 0 /**************************************************************************** * AES :: EEPROM_DATA_3 ***************************************************************************/ /* AES :: EEPROM_DATA_3 :: DATA [31:00] */ #define AES_EEPROM_DATA_3_DATA_MASK 0xffffffff #define AES_EEPROM_DATA_3_DATA_ALIGN 0 #define AES_EEPROM_DATA_3_DATA_BITS 32 #define AES_EEPROM_DATA_3_DATA_SHIFT 0 /**************************************************************************** * BCM70012_AES_TOP_AES_RGR_BRIDGE ***************************************************************************/ /**************************************************************************** * AES_RGR_BRIDGE :: REVISION ***************************************************************************/ /* AES_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define AES_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define AES_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 #define AES_RGR_BRIDGE_REVISION_reserved0_BITS 16 #define AES_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 /* AES_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define AES_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define AES_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 #define AES_RGR_BRIDGE_REVISION_MAJOR_BITS 8 #define AES_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* AES_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ #define AES_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define AES_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 #define AES_RGR_BRIDGE_REVISION_MINOR_BITS 8 #define AES_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 /**************************************************************************** * AES_RGR_BRIDGE :: CTRL ***************************************************************************/ /* AES_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ #define AES_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc #define AES_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 #define AES_RGR_BRIDGE_CTRL_reserved0_BITS 30 #define AES_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 /* AES_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ #define AES_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 #define AES_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 #define AES_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 #define AES_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 #define AES_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 #define AES_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 /* AES_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ #define AES_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 #define AES_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 #define AES_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 #define AES_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 #define AES_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 #define AES_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 /**************************************************************************** * AES_RGR_BRIDGE :: RBUS_TIMER ***************************************************************************/ /* AES_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ #define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 #define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 #define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 #define AES_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 /* AES_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ #define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff #define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 #define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 #define AES_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 /**************************************************************************** * AES_RGR_BRIDGE :: SPARE_SW_RESET_0 ***************************************************************************/ /* AES_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 /* AES_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 #define AES_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 /**************************************************************************** * AES_RGR_BRIDGE :: SPARE_SW_RESET_1 ***************************************************************************/ /* AES_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 /* AES_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 #define AES_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 /**************************************************************************** * BCM70012_DCI_TOP_DCI ***************************************************************************/ /**************************************************************************** * DCI :: CMD ***************************************************************************/ /* DCI :: CMD :: reserved0 [31:09] */ #define DCI_CMD_reserved0_MASK 0xfffffe00 #define DCI_CMD_reserved0_ALIGN 0 #define DCI_CMD_reserved0_BITS 23 #define DCI_CMD_reserved0_SHIFT 9 /* DCI :: CMD :: FORCE_FW_VALIDATED [08:08] */ #define DCI_CMD_FORCE_FW_VALIDATED_MASK 0x00000100 #define DCI_CMD_FORCE_FW_VALIDATED_ALIGN 0 #define DCI_CMD_FORCE_FW_VALIDATED_BITS 1 #define DCI_CMD_FORCE_FW_VALIDATED_SHIFT 8 /* DCI :: CMD :: reserved1 [07:05] */ #define DCI_CMD_reserved1_MASK 0x000000e0 #define DCI_CMD_reserved1_ALIGN 0 #define DCI_CMD_reserved1_BITS 3 #define DCI_CMD_reserved1_SHIFT 5 /* DCI :: CMD :: START_PROCESSOR [04:04] */ #define DCI_CMD_START_PROCESSOR_MASK 0x00000010 #define DCI_CMD_START_PROCESSOR_ALIGN 0 #define DCI_CMD_START_PROCESSOR_BITS 1 #define DCI_CMD_START_PROCESSOR_SHIFT 4 /* DCI :: CMD :: reserved2 [03:02] */ #define DCI_CMD_reserved2_MASK 0x0000000c #define DCI_CMD_reserved2_ALIGN 0 #define DCI_CMD_reserved2_BITS 2 #define DCI_CMD_reserved2_SHIFT 2 /* DCI :: CMD :: DOWNLOAD_COMPLETE [01:01] */ #define DCI_CMD_DOWNLOAD_COMPLETE_MASK 0x00000002 #define DCI_CMD_DOWNLOAD_COMPLETE_ALIGN 0 #define DCI_CMD_DOWNLOAD_COMPLETE_BITS 1 #define DCI_CMD_DOWNLOAD_COMPLETE_SHIFT 1 /* DCI :: CMD :: INITIATE_FW_DOWNLOAD [00:00] */ #define DCI_CMD_INITIATE_FW_DOWNLOAD_MASK 0x00000001 #define DCI_CMD_INITIATE_FW_DOWNLOAD_ALIGN 0 #define DCI_CMD_INITIATE_FW_DOWNLOAD_BITS 1 #define DCI_CMD_INITIATE_FW_DOWNLOAD_SHIFT 0 /**************************************************************************** * DCI :: STATUS ***************************************************************************/ /* DCI :: STATUS :: reserved0 [31:10] */ #define DCI_STATUS_reserved0_MASK 0xfffffc00 #define DCI_STATUS_reserved0_ALIGN 0 #define DCI_STATUS_reserved0_BITS 22 #define DCI_STATUS_reserved0_SHIFT 10 /* DCI :: STATUS :: SIGNATURE_MATCHED [09:09] */ #define DCI_STATUS_SIGNATURE_MATCHED_MASK 0x00000200 #define DCI_STATUS_SIGNATURE_MATCHED_ALIGN 0 #define DCI_STATUS_SIGNATURE_MATCHED_BITS 1 #define DCI_STATUS_SIGNATURE_MATCHED_SHIFT 9 /* DCI :: STATUS :: SIGNATURE_MISMATCH [08:08] */ #define DCI_STATUS_SIGNATURE_MISMATCH_MASK 0x00000100 #define DCI_STATUS_SIGNATURE_MISMATCH_ALIGN 0 #define DCI_STATUS_SIGNATURE_MISMATCH_BITS 1 #define DCI_STATUS_SIGNATURE_MISMATCH_SHIFT 8 /* DCI :: STATUS :: reserved1 [07:06] */ #define DCI_STATUS_reserved1_MASK 0x000000c0 #define DCI_STATUS_reserved1_ALIGN 0 #define DCI_STATUS_reserved1_BITS 2 #define DCI_STATUS_reserved1_SHIFT 6 /* DCI :: STATUS :: GISB_ERROR [05:05] */ #define DCI_STATUS_GISB_ERROR_MASK 0x00000020 #define DCI_STATUS_GISB_ERROR_ALIGN 0 #define DCI_STATUS_GISB_ERROR_BITS 1 #define DCI_STATUS_GISB_ERROR_SHIFT 5 /* DCI :: STATUS :: DOWNLOAD_READY [04:04] */ #define DCI_STATUS_DOWNLOAD_READY_MASK 0x00000010 #define DCI_STATUS_DOWNLOAD_READY_ALIGN 0 #define DCI_STATUS_DOWNLOAD_READY_BITS 1 #define DCI_STATUS_DOWNLOAD_READY_SHIFT 4 /* DCI :: STATUS :: reserved2 [03:01] */ #define DCI_STATUS_reserved2_MASK 0x0000000e #define DCI_STATUS_reserved2_ALIGN 0 #define DCI_STATUS_reserved2_BITS 3 #define DCI_STATUS_reserved2_SHIFT 1 /* DCI :: STATUS :: FIRMWARE_VALIDATED [00:00] */ #define DCI_STATUS_FIRMWARE_VALIDATED_MASK 0x00000001 #define DCI_STATUS_FIRMWARE_VALIDATED_ALIGN 0 #define DCI_STATUS_FIRMWARE_VALIDATED_BITS 1 #define DCI_STATUS_FIRMWARE_VALIDATED_SHIFT 0 /**************************************************************************** * DCI :: DRAM_BASE_ADDR ***************************************************************************/ /* DCI :: DRAM_BASE_ADDR :: reserved0 [31:13] */ #define DCI_DRAM_BASE_ADDR_reserved0_MASK 0xffffe000 #define DCI_DRAM_BASE_ADDR_reserved0_ALIGN 0 #define DCI_DRAM_BASE_ADDR_reserved0_BITS 19 #define DCI_DRAM_BASE_ADDR_reserved0_SHIFT 13 /* DCI :: DRAM_BASE_ADDR :: BASE_ADDR [12:00] */ #define DCI_DRAM_BASE_ADDR_BASE_ADDR_MASK 0x00001fff #define DCI_DRAM_BASE_ADDR_BASE_ADDR_ALIGN 0 #define DCI_DRAM_BASE_ADDR_BASE_ADDR_BITS 13 #define DCI_DRAM_BASE_ADDR_BASE_ADDR_SHIFT 0 /**************************************************************************** * DCI :: FIRMWARE_ADDR ***************************************************************************/ /* DCI :: FIRMWARE_ADDR :: reserved0 [31:19] */ #define DCI_FIRMWARE_ADDR_reserved0_MASK 0xfff80000 #define DCI_FIRMWARE_ADDR_reserved0_ALIGN 0 #define DCI_FIRMWARE_ADDR_reserved0_BITS 13 #define DCI_FIRMWARE_ADDR_reserved0_SHIFT 19 /* DCI :: FIRMWARE_ADDR :: FW_ADDR [18:02] */ #define DCI_FIRMWARE_ADDR_FW_ADDR_MASK 0x0007fffc #define DCI_FIRMWARE_ADDR_FW_ADDR_ALIGN 0 #define DCI_FIRMWARE_ADDR_FW_ADDR_BITS 17 #define DCI_FIRMWARE_ADDR_FW_ADDR_SHIFT 2 /* DCI :: FIRMWARE_ADDR :: reserved1 [01:00] */ #define DCI_FIRMWARE_ADDR_reserved1_MASK 0x00000003 #define DCI_FIRMWARE_ADDR_reserved1_ALIGN 0 #define DCI_FIRMWARE_ADDR_reserved1_BITS 2 #define DCI_FIRMWARE_ADDR_reserved1_SHIFT 0 /**************************************************************************** * DCI :: FIRMWARE_DATA ***************************************************************************/ /* DCI :: FIRMWARE_DATA :: FW_DATA [31:00] */ #define DCI_FIRMWARE_DATA_FW_DATA_MASK 0xffffffff #define DCI_FIRMWARE_DATA_FW_DATA_ALIGN 0 #define DCI_FIRMWARE_DATA_FW_DATA_BITS 32 #define DCI_FIRMWARE_DATA_FW_DATA_SHIFT 0 /**************************************************************************** * DCI :: SIGNATURE_DATA_0 ***************************************************************************/ /* DCI :: SIGNATURE_DATA_0 :: SIG_DATA_0 [31:00] */ #define DCI_SIGNATURE_DATA_0_SIG_DATA_0_MASK 0xffffffff #define DCI_SIGNATURE_DATA_0_SIG_DATA_0_ALIGN 0 #define DCI_SIGNATURE_DATA_0_SIG_DATA_0_BITS 32 #define DCI_SIGNATURE_DATA_0_SIG_DATA_0_SHIFT 0 /**************************************************************************** * DCI :: SIGNATURE_DATA_1 ***************************************************************************/ /* DCI :: SIGNATURE_DATA_1 :: SIG_DATA_1 [31:00] */ #define DCI_SIGNATURE_DATA_1_SIG_DATA_1_MASK 0xffffffff #define DCI_SIGNATURE_DATA_1_SIG_DATA_1_ALIGN 0 #define DCI_SIGNATURE_DATA_1_SIG_DATA_1_BITS 32 #define DCI_SIGNATURE_DATA_1_SIG_DATA_1_SHIFT 0 /**************************************************************************** * DCI :: SIGNATURE_DATA_2 ***************************************************************************/ /* DCI :: SIGNATURE_DATA_2 :: SIG_DATA_2 [31:00] */ #define DCI_SIGNATURE_DATA_2_SIG_DATA_2_MASK 0xffffffff #define DCI_SIGNATURE_DATA_2_SIG_DATA_2_ALIGN 0 #define DCI_SIGNATURE_DATA_2_SIG_DATA_2_BITS 32 #define DCI_SIGNATURE_DATA_2_SIG_DATA_2_SHIFT 0 /**************************************************************************** * DCI :: SIGNATURE_DATA_3 ***************************************************************************/ /* DCI :: SIGNATURE_DATA_3 :: SIG_DATA_3 [31:00] */ #define DCI_SIGNATURE_DATA_3_SIG_DATA_3_MASK 0xffffffff #define DCI_SIGNATURE_DATA_3_SIG_DATA_3_ALIGN 0 #define DCI_SIGNATURE_DATA_3_SIG_DATA_3_BITS 32 #define DCI_SIGNATURE_DATA_3_SIG_DATA_3_SHIFT 0 /**************************************************************************** * DCI :: SIGNATURE_DATA_4 ***************************************************************************/ /* DCI :: SIGNATURE_DATA_4 :: SIG_DATA_4 [31:00] */ #define DCI_SIGNATURE_DATA_4_SIG_DATA_4_MASK 0xffffffff #define DCI_SIGNATURE_DATA_4_SIG_DATA_4_ALIGN 0 #define DCI_SIGNATURE_DATA_4_SIG_DATA_4_BITS 32 #define DCI_SIGNATURE_DATA_4_SIG_DATA_4_SHIFT 0 /**************************************************************************** * DCI :: SIGNATURE_DATA_5 ***************************************************************************/ /* DCI :: SIGNATURE_DATA_5 :: SIG_DATA_5 [31:00] */ #define DCI_SIGNATURE_DATA_5_SIG_DATA_5_MASK 0xffffffff #define DCI_SIGNATURE_DATA_5_SIG_DATA_5_ALIGN 0 #define DCI_SIGNATURE_DATA_5_SIG_DATA_5_BITS 32 #define DCI_SIGNATURE_DATA_5_SIG_DATA_5_SHIFT 0 /**************************************************************************** * DCI :: SIGNATURE_DATA_6 ***************************************************************************/ /* DCI :: SIGNATURE_DATA_6 :: SIG_DATA_6 [31:00] */ #define DCI_SIGNATURE_DATA_6_SIG_DATA_6_MASK 0xffffffff #define DCI_SIGNATURE_DATA_6_SIG_DATA_6_ALIGN 0 #define DCI_SIGNATURE_DATA_6_SIG_DATA_6_BITS 32 #define DCI_SIGNATURE_DATA_6_SIG_DATA_6_SHIFT 0 /**************************************************************************** * DCI :: SIGNATURE_DATA_7 ***************************************************************************/ /* DCI :: SIGNATURE_DATA_7 :: SIG_DATA_7 [31:00] */ #define DCI_SIGNATURE_DATA_7_SIG_DATA_7_MASK 0xffffffff #define DCI_SIGNATURE_DATA_7_SIG_DATA_7_ALIGN 0 #define DCI_SIGNATURE_DATA_7_SIG_DATA_7_BITS 32 #define DCI_SIGNATURE_DATA_7_SIG_DATA_7_SHIFT 0 /**************************************************************************** * BCM70012_DCI_TOP_DCI_RGR_BRIDGE ***************************************************************************/ /**************************************************************************** * DCI_RGR_BRIDGE :: REVISION ***************************************************************************/ /* DCI_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define DCI_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define DCI_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 #define DCI_RGR_BRIDGE_REVISION_reserved0_BITS 16 #define DCI_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 /* DCI_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define DCI_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define DCI_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 #define DCI_RGR_BRIDGE_REVISION_MAJOR_BITS 8 #define DCI_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* DCI_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ #define DCI_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define DCI_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 #define DCI_RGR_BRIDGE_REVISION_MINOR_BITS 8 #define DCI_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 /**************************************************************************** * DCI_RGR_BRIDGE :: CTRL ***************************************************************************/ /* DCI_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ #define DCI_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc #define DCI_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 #define DCI_RGR_BRIDGE_CTRL_reserved0_BITS 30 #define DCI_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 /* DCI_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ #define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 #define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 #define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 #define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 #define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 #define DCI_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 /* DCI_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ #define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 #define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 #define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 #define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 #define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 #define DCI_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 /**************************************************************************** * DCI_RGR_BRIDGE :: RBUS_TIMER ***************************************************************************/ /* DCI_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ #define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 #define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 #define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 #define DCI_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 /* DCI_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ #define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff #define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 #define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 #define DCI_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 /**************************************************************************** * DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 ***************************************************************************/ /* DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 /* DCI_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 #define DCI_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 /**************************************************************************** * DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 ***************************************************************************/ /* DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 /* DCI_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 #define DCI_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 /**************************************************************************** * BCM70012_CCE_TOP_CCE_RGR_BRIDGE ***************************************************************************/ /**************************************************************************** * CCE_RGR_BRIDGE :: REVISION ***************************************************************************/ /* CCE_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define CCE_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define CCE_RGR_BRIDGE_REVISION_reserved0_ALIGN 0 #define CCE_RGR_BRIDGE_REVISION_reserved0_BITS 16 #define CCE_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 /* CCE_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define CCE_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define CCE_RGR_BRIDGE_REVISION_MAJOR_ALIGN 0 #define CCE_RGR_BRIDGE_REVISION_MAJOR_BITS 8 #define CCE_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* CCE_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ #define CCE_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define CCE_RGR_BRIDGE_REVISION_MINOR_ALIGN 0 #define CCE_RGR_BRIDGE_REVISION_MINOR_BITS 8 #define CCE_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 /**************************************************************************** * CCE_RGR_BRIDGE :: CTRL ***************************************************************************/ /* CCE_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ #define CCE_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc #define CCE_RGR_BRIDGE_CTRL_reserved0_ALIGN 0 #define CCE_RGR_BRIDGE_CTRL_reserved0_BITS 30 #define CCE_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 /* CCE_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ #define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 #define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_ALIGN 0 #define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_BITS 1 #define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 #define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 #define CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 /* CCE_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ #define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 #define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_ALIGN 0 #define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_BITS 1 #define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 #define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 #define CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 /**************************************************************************** * CCE_RGR_BRIDGE :: RBUS_TIMER ***************************************************************************/ /* CCE_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ #define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 #define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_ALIGN 0 #define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_BITS 16 #define CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 /* CCE_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ #define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff #define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_ALIGN 0 #define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_BITS 16 #define CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 /**************************************************************************** * CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 ***************************************************************************/ /* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_ALIGN 0 #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_BITS 31 #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 /* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ALIGN 0 #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_BITS 1 #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 #define CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 /**************************************************************************** * CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 ***************************************************************************/ /* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_ALIGN 0 #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_BITS 31 #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 /* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ALIGN 0 #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_BITS 1 #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 #define CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 /**************************************************************************** * Datatype Definitions. ***************************************************************************/ #endif /* #ifndef MACFILE_H__ */ /* End of File */ crystalhd-0.0~git20110715.fdd2f19/include/vdec_info.h0000644000175000017500000003337211610313111021265 0ustar andresandres/******************************************************************** * Copyright (c) 2004-2009 Broadcom Corporation. * * Common Video Decoder Information * ******************************************************************** * This header is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This header is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this header. If not, see . ***************************************************************************/ #ifndef __INC_VDEC_INFO_H__ #define __INC_VDEC_INFO_H__ #include "bc_dts_types.h" #pragma pack (1) /* User Data Header */ typedef struct user_data { struct user_data* next; uint32_t type; uint32_t size; } UD_HDR; /*------------------------------------------------------* * MPEG Extension to the PPB * *------------------------------------------------------*/ #define MPEG_VALID_PANSCAN (1) #define MPEG_VALID_USER_DATA (2) #define MPEG_USER_DATA_OVERFLOW (4) #define MPEG_USER_DATA_TYPE_SEQ (1) #define MPEG_USER_DATA_TYPE_GOP (2) #define MPEG_USER_DATA_TYPE_PIC (4) #define MPEG_USER_DATA_TYPE_TOP (8) #define MPEG_USER_DATA_TYPE_BTM (16) #define MPEG_USER_DATA_TYPE_I (32) #define MPEG_USER_DATA_TYPE_P (64) #define MPEG_USER_DATA_TYPE_B (128) typedef struct { uint32_t to_be_defined; uint32_t valid; /* Always valid, defaults to picture size if no sequence display extension in the stream. */ uint32_t display_horizontal_size; uint32_t display_vertical_size; /* MPEG_VALID_PANSCAN Offsets are a copy values from the MPEG stream. */ uint32_t offset_count; int32_t horizontal_offset[3]; int32_t vertical_offset[3]; /* MPEG_VALID_USERDATA User data is in the form of a linked list. */ int32_t userDataSize; UD_HDR* userData; } PPB_MPEG; /*------------------------------------------------------* * VC1 Extension to the PPB * *------------------------------------------------------*/ #define VC1_VALID_PANSCAN (1) #define VC1_VALID_USER_DATA (2) #define VC1_USER_DATA_OVERFLOW (4) #define VC1_USER_DATA_TYPE_SEQ (1) #define VC1_USER_DATA_TYPE_ENTRYPOINT (2) #define VC1_USER_DATA_TYPE_FRM (4) #define VC1_USER_DATA_TYPE_FLD (8) #define VC1_USER_DATA_TYPE_SLICE (16) typedef struct { uint32_t to_be_defined; uint32_t valid; /* Always valid, defaults to picture size if no sequence display extension in the stream. */ uint32_t display_horizontal_size; uint32_t display_vertical_size; /* VC1 pan scan windows */ uint32_t num_panscan_windows; int32_t ps_horiz_offset[4]; int32_t ps_vert_offset[4]; int32_t ps_width[4]; int32_t ps_height[4]; /* VC1_VALID_USERDATA User data is in the form of a linked list. */ int32_t userDataSize; UD_HDR* userData; } PPB_VC1; /*------------------------------------------------------* * H.264 Extension to the PPB * *------------------------------------------------------*/ /** * @brief Film grain SEI message. * * Content of the film grain SEI message. */ //maximum number of model-values as for Thomson spec(standard says 5) #define MAX_FGT_MODEL_VALUE (3) //maximum number of intervals(as many as 256 intervals?) #define MAX_FGT_VALUE_INTERVAL (256) typedef struct FGT_SEI { struct FGT_SEI* next; unsigned char model_values[3][MAX_FGT_VALUE_INTERVAL][MAX_FGT_MODEL_VALUE]; unsigned char upper_bound[3][MAX_FGT_VALUE_INTERVAL]; unsigned char lower_bound[3][MAX_FGT_VALUE_INTERVAL]; unsigned char cancel_flag; /**< Cancel flag: 1 no film grain. */ unsigned char model_id; /**< Model id. */ //+unused SE based on Thomson spec unsigned char color_desc_flag; /**< Separate color descrition flag. */ unsigned char bit_depth_luma; /**< Bit depth luma minus 8. */ unsigned char bit_depth_chroma; /**< Bit depth chroma minus 8. */ unsigned char full_range_flag; /**< Full range flag. */ unsigned char color_primaries; /**< Color primaries. */ unsigned char transfer_charact; /**< Transfer characteristics. */ unsigned char matrix_coeff; /**< Matrix coefficients. */ //-unused SE based on Thomson spec unsigned char blending_mode_id; /**< Blending mode. */ unsigned char log2_scale_factor; /**< Log2 scale factor (2-7). */ unsigned char comp_flag[3]; /**< Components [0,2] parameters present flag. */ unsigned char num_intervals_minus1[3]; /**< Number of intensity level intervals. */ unsigned char num_model_values[3]; /**< Number of model values. */ uint16_t repetition_period; /**< Repetition period (0-16384) */ } FGT_SEI; /* Bit definitions for H.264 user data type field */ #define AVC_USERDATA_TYPE_REGISTERED 4 #define AVC_USERDATA_TYPE_TOP 8 #define AVC_USERDATA_TYPE_BOT 16 /* Bit definitions for 'other.h264.valid' field */ #define H264_VALID_PANSCAN (1) #define H264_VALID_SPS_CROP (2) #define H264_VALID_VUI (4) #define H264_VALID_USER (8) #define H264_VALID_CT_TYPE (16) #define H264_USER_OVERFLOW (32) #define H264_FILM_GRAIN_MSG (64) typedef struct { /* 'valid' specifies which fields (or sets of * fields) below are valid. If the corresponding * bit in 'valid' is NOT set then that field(s) * is (are) not initialized. */ uint32_t valid; int32_t poc_top; /* POC for Top Field/Frame */ int32_t poc_bottom; /* POC for Bottom Field */ uint32_t idr_pic_id; /* H264_VALID_PANSCAN */ uint32_t pan_scan_count; int32_t pan_scan_left [3]; int32_t pan_scan_right [3]; int32_t pan_scan_top [3]; int32_t pan_scan_bottom[3]; /* H264_VALID_CT_TYPE */ uint32_t ct_type_count; uint32_t ct_type[3]; /* H264_VALID_SPS_CROP */ int32_t sps_crop_left; int32_t sps_crop_right; int32_t sps_crop_top; int32_t sps_crop_bottom; /* H264_VALID_VUI */ uint32_t chroma_top; uint32_t chroma_bottom; /* H264_VALID_USER */ uint32_t user_data_size; UD_HDR* user_data; /* H264 VALID FGT */ FGT_SEI* pfgt; } PPB_H264; /*------------------------------------------------------* * Picture Parameter Block * *------------------------------------------------------*/ /* Bit definitions for 'flags' field */ #define VDEC_FLAG_PTS_PRESENT (0x0001) #define VDEC_FLAG_PTS_MSB (0x0002) #define VDEC_FLAG_EOS (0x0004) #define VDEC_FLAG_FRAME (0x0000) #define VDEC_FLAG_FIELDPAIR (0x0008) #define VDEC_FLAG_TOPFIELD (0x0010) #define VDEC_FLAG_BOTTOMFIELD (0x0018) #define VDEC_FLAG_PROGRESSIVE_SRC (0x0000) #define VDEC_FLAG_INTERLACED_SRC (0x0020) #define VDEC_FLAG_UNKNOWN_SRC (0x0040) #define VDEC_FLAG_BOTTOM_FIRST (0x0080) #define VDEC_FLAG_LAST_PICTURE (0x0100) #define VDEC_FLAG_STC_IS_CRAP (0x0200) #define VDEC_FLAG_PCR_OFFSET_PRESENT (0x0400) #define VDEC_FLAG_REF_CNTR_TYPE_PCR (0x0800) #define VDEC_FLAG_DISCONT_PCR_OFFSET (0x1000) #define VDEC_FLAG_PICTURE_TAG_VALID (0x2000) #define VDEC_FLAG_PICTURE_DONE_MARKER_PRESENT (0x20000) #define VDEC_FLAG_PICTURE_META_DATA_PRESENT (0x40000) #define VDEC_FLAG_RESOLUTION_CHANGE (0x80000) /* Values for the 'chroma_format' field. */ enum { vdecChroma420 = 0x420, vdecChroma422 = 0x422, vdecChroma444 = 0x444, }; #if !defined(_WIN32) && !defined(_WIN64) && !defined(__LINUX_USER__) ////////////////////////////////////////////////////////////////////// /////// Moved to bc_dts_defs.h file for external Exports ///////////// ////////////////////////////////////////////////////////////////////// /* Values for 'pulldown' field. '0' means no pulldown information * was present for this picture. */ enum { vdecNoPulldownInfo = 0, vdecTop = 1, vdecBottom = 2, vdecTopBottom = 3, vdecBottomTop = 4, vdecTopBottomTop = 5, vdecBottomTopBottom = 6, vdecFrame_X2 = 7, vdecFrame_X3 = 8, vdecFrame_X1 = 9, vdecFrame_X4 = 10, }; /* Values for 'protocol' field. */ enum { protocolH264 = 0, protocolMPEG2, protocolH261, protocolH263, protocolVC1, protocolMPEG1, protocolMPEG2DTV, protocolVC1ASF, }; /* Values for the 'frame_rate' field. */ enum { vdecFrameRateUnknown = 0, vdecFrameRate23_97, vdecFrameRate24, vdecFrameRate25, vdecFrameRate29_97, vdecFrameRate30, vdecFrameRate50, vdecFrameRate59_94, vdecFrameRate60, }; /* Values for the 'matrix_coeff' field. */ enum { vdecMatrixCoeffUnknown = 0, vdecMatrixCoeffBT709, vdecMatrixCoeffUnspecified, vdecMatrixCoeffReserved, vdecMatrixCoeffFCC = 4, vdecMatrixCoeffBT740_2BG, vdecMatrixCoeffSMPTE170M, vdecMatrixCoeffSMPTE240M, vdecMatrixCoeffSMPTE293M, }; /* Values for the 'aspect_ratio' field. */ enum { vdecAspectRatioUnknown = 0, vdecAspectRatioSquare, vdecAspectRatio12_11, vdecAspectRatio10_11, vdecAspectRatio16_11, vdecAspectRatio40_33, vdecAspectRatio24_11, vdecAspectRatio20_11, vdecAspectRatio32_11, vdecAspectRatio80_33, vdecAspectRatio18_11, vdecAspectRatio15_11, vdecAspectRatio64_33, vdecAspectRatio160_99, vdecAspectRatio4_3, vdecAspectRatio16_9, vdecAspectRatio221_1, vdecAspectRatioOther = 255, }; /* Values for the 'colour_primaries' field. */ enum { vdecColourPrimariesUnknown = 0, vdecColourPrimariesBT709, vdecColourPrimariesUnspecified, vdecColourPrimariesReserved, vdecColourPrimariesBT470_2M = 4, vdecColourPrimariesBT470_2BG, vdecColourPrimariesSMPTE170M, vdecColourPrimariesSMPTE240M, vdecColourPrimariesGenericFilm, }; /* Values for the 'transfer_char' field. */ enum { vdecTransferCharUnknown = 0, vdecTransferCharBT709, vdecTransferCharUnspecified, vdecTransferCharReserved, vdecTransferCharBT479_2M = 4, vdecTransferCharBT479_2BG, vdecTransferCharSMPTE170M, vdecTransferCharSMPTE240M, vdecTransferCharLinear, vdecTransferCharLog100_1, vdecTransferCharLog31622777_1, vdecColourPrimariesBT1361, }; #endif // _WIN32 typedef struct { /* Common fields. */ uint32_t picture_number; /* Ordinal display number */ uint32_t video_buffer; /* Video (picbuf) number */ uint32_t video_address; /* Address of picbuf Y */ uint32_t video_address_uv; /* Address of picbuf UV */ uint32_t video_stripe; /* Picbuf stripe */ uint32_t video_width; /* Picbuf width */ uint32_t video_height; /* Picbuf height */ uint32_t channel_id; /* Decoder channel ID */ uint32_t status; /* reserved */ uint32_t width; /* pixels */ uint32_t height; /* pixels */ uint32_t chroma_format; /* see above */ uint32_t pulldown; /* see above */ uint32_t flags; /* see above */ uint32_t pts; /* 32 LSBs of PTS */ uint32_t protocol; /* protocolXXX (above) */ uint32_t frame_rate; /* see above */ uint32_t matrix_coeff; /* see above */ uint32_t aspect_ratio; /* see above */ uint32_t colour_primaries; /* see above */ uint32_t transfer_char; /* see above */ uint32_t pcr_offset; /* 45kHz if PCR type; else 27MHz */ uint32_t n_drop; /* Number of pictures to be dropped */ uint32_t custom_aspect_ratio_width_height; /* upper 16-bits is Y and lower 16-bits is X */ uint32_t picture_tag; /* Indexing tag from BUD packets */ uint32_t picture_done_payload; uint32_t picture_meta_payload; uint32_t reserved[1]; /* Protocol-specific extensions. */ union { PPB_H264 h264; PPB_MPEG mpeg; PPB_VC1 vc1; } other; } PPB; typedef struct { /* Approximate number of pictures in * the CPB */ uint32_t codein_picture_count; /* GOP time code */ uint32_t time_code_hours; uint32_t time_code_minutes; uint32_t time_code_seconds; uint32_t time_code_pictures; uint32_t pic_done_marker_btp_payload; uint32_t start_decode_time; uint32_t chan_open_time; uint32_t chan_close_start_time; uint32_t chan_close_end_time; uint32_t first_pic_delivery_time; uint32_t first_code_in_packet_time; uint32_t ts_fifo_byte_non_zero_time; uint32_t ts_video_packet_count_non_zero_time; } VdecStatusBlock; #if defined(CHIP_7401A) /* Display Manager: STC and Parity Information in DRAM for host to use */ typedef struct { uint32_t stc_snapshot; uint32_t vsync_parity; uint32_t vsync_count; /* used only for debug */ } DisplayInfo; /* Parameters passed from Display Manager (host) to DMS */ typedef struct { uint32_t write_offset; uint32_t drop_count; } DMS_Info; /* Picture Delivery parameters required by Display Manager */ typedef struct { uint32_t queue_read_offset; /* offset is w.r.t base of this data struct so value of 0-1 prohibited */ uint32_t queue_write_offset; /* offset is w.r.t base of this data struct so value of 0-1 prohibited */ /* queue if full if (write_offset+1 == read_offset) */ /* write_offset modified by firmware and read_offset modified by Display Manager in host */ PPB* display_elements[62]; } PictureDeliveryQueue; /* Picture Release parameters returned by Display Manager to firmware */ typedef struct { uint32_t queue_read_offset; /* offset is w.r.t base of this data struct so value of 0-1 prohibited */ uint32_t queue_write_offset; /* offset is w.r.t base of this data struct so value of 0-1 prohibited */ /* queue if full if (write_offset+1 == read_offset) */ /* read_offset modified by firmware and write_offset modified by Display Manager in host */ PPB* display_elements[62]; } PictureReleaseQueue; #endif #pragma pack () #endif // __INC_VDEC_INFO_H__ crystalhd-0.0~git20110715.fdd2f19/include/flea/0000755000175000017500000000000011610313111020057 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/include/flea/DriverFwShare.h0000644000175000017500000000605511610313111022751 0ustar andresandres#ifndef _DRIVER_FW_SHARE_ #define _DRIVER_FW_SHARE_ #ifndef USE_MULTI_DECODE_DEFINES #define HOST_TO_FW_PIC_DEL_INFO_ADDR 0x400 /*Original single Decode Offset*/ #else #if 0 #define HOST_TO_FW_PIC_DEL_INFO_ADDR 0x200 /*New offset that we plan to use eventually*/ #endif #define HOST_TO_FW_PIC_DEL_INFO_ADDR 0x400 /*This is just for testing..remove this once tested */ #endif /* * The TX address does not change between the * single decode and multiple decode. */ #define TX_BUFF_UPDATE_ADDR 0x300 /*This is relative to BORCH */ typedef struct _PIC_DELIVERY_HOST_INFO_ { /* -- The list ping-pong code is already there in the driver -- to save from re-inventing the code, the driver will indicate -- to firmware on which list the command should be posted. */ unsigned int ListIndex; unsigned int HostDescMemLowAddr_Y; unsigned int HostDescMemHighAddr_Y; unsigned int HostDescMemLowAddr_UV; unsigned int HostDescMemHighAddr_UV; unsigned int RxSeqNumber; unsigned int ChannelID; unsigned int Reserved[1]; }PIC_DELIVERY_HOST_INFO, *PPIC_DELIVERY_HOST_INFO; /* -- We write the driver's FLL to this memory location. -- This is the array for FLL of all the channels. */ #define HOST_TO_FW_FLL_ADDR (HOST_TO_FW_PIC_DEL_INFO_ADDR + sizeof(PIC_DELIVERY_HOST_INFO)) typedef enum _DRIVER_FW_FLAGS_{ DFW_FLAGS_CLEAR =0, DFW_FLAGS_TX_ABORT =BC_BIT(0), /*Firmware is stopped and will not give anymore buffers. */ DFW_FLAGS_WRAP =BC_BIT(1) /*Instruct the Firmware to WRAP the input buffer pointer */ }DRIVER_FW_FLAGS; typedef struct _TX_INPUT_BUFFER_INFO_ { unsigned int DramBuffAdd; /* Address of the DRAM buffer where the data can be pushed*/ unsigned int DramBuffSzInBytes; /* Size of the available DRAM buffer, in bytes*/ unsigned int HostXferSzInBytes; /* Actual Transfer Done By Host, In Bytes*/ unsigned int Flags; /* DRIVER_FW_FLAGS Written By Firmware to handle Stop of TX*/ unsigned int SeqNum; /* Sequence number of the tranfer that is done. Read-Modify-Write*/ unsigned int ChannelID; /* To which Channel this buffer belongs to*/ unsigned int Reserved[2]; }TX_INPUT_BUFFER_INFO, *PTX_INPUT_BUFFER_INFO; /* -- Out of band firmware handshake. ===================================== -- The driver writes the SCRATCH-8 register with a Error code. -- The driver then writes a mailbox register with 0x01. -- The driver then polls for the ACK. This ack is if the value of the SCRATCH-8 becomes zero. */ #define OOB_ERR_CODE_BASE 70015 typedef enum _OUT_OF_BAND_ERR_CODE_ { OOB_INVALID = 0, OOB_CODE_ACK = OOB_ERR_CODE_BASE, OOB_CODE_STOPRX = OOB_ERR_CODE_BASE + 1, }OUT_OF_BAND_ERR_CODE; #define OOB_CMD_RESPONSE_REGISTER BCHP_ARMCR4_BRIDGE_REG_SCRATCH_8 #define OOB_PCI_TO_ARM_MBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM3 #define TX_BUFFER_AVAILABLE_INTR BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI3 #define HEART_BEAT_REGISTER BCHP_ARMCR4_BRIDGE_REG_SCRATCH_1 #define HEART_BEAT_POLL_CNT 5 #define FLEA_WORK_AROUND_SIG 0xF1EA #define RX_PIC_Q_STS_WRKARND BC_BIT(0) #define RX_DRAM_WRITE_WRKARND BC_BIT(1) #define RX_MBOX_WRITE_WRKARND BC_BIT(2) #endif crystalhd-0.0~git20110715.fdd2f19/include/flea/bcm_70015_regs.h0000644000175000017500000017763711610313111022572 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_misc1.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:11p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:40 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc1.h $ * * Hydra_Software_Devel/1 7/17/09 8:11p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_MISC1_H__ #define BCHP_MISC1_H__ /*************************************************************************** *MISC1 - Registers for DMA List Control ***************************************************************************/ #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0 0x00502000 /* Tx DMA Descriptor List0 First Descriptor lower Address */ #define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST0 0x00502004 /* Tx DMA Descriptor List0 First Descriptor Upper Address */ #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1 0x00502008 /* Tx DMA Descriptor List1 First Descriptor Lower Address */ #define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST1 0x0050200c /* Tx DMA Descriptor List1 First Descriptor Upper Address */ #define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS 0x00502010 /* Tx DMA Software Descriptor List Control and Status */ #define BCHP_MISC1_TX_DMA_ERROR_STATUS 0x00502018 /* Tx DMA Engine Error Status */ #define BCHP_MISC1_TX_DMA_CTRL 0x00502034 /* Tx DMA Flea Interface Control */ #define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS 0x00502050 /* Y Rx Software Descriptor List Control and Status */ #define BCHP_MISC1_Y_RX_ERROR_STATUS 0x00502054 /* Y Rx Engine Error Status */ #define BCHP_MISC1_Y_RX_LIST0_CUR_BYTE_CNT 0x00502060 /* Y Rx List0 Current Descriptor Byte Count */ #define BCHP_MISC1_Y_RX_LIST1_CUR_BYTE_CNT 0x0050206c /* Y Rx List1 Current Descriptor Byte Count */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS 0x00502094 /* HIF Rx Engine Error Status */ #define BCHP_MISC1_HIF_RX_LIST0_CUR_BYTE_CNT 0x005020a0 /* HIF Rx List0 Current Descriptor Byte Count */ #define BCHP_MISC1_HIF_RX_LIST1_CUR_BYTE_CNT 0x005020ac /* HIF Rx List1 Current Descriptor Byte Count */ #define BCHP_MISC1_HIF_DMA_CTRL 0x005020b0 /* HIF Rx DMA Flea Interface Control */ #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG 0x005020c0 /* DMA Debug Options Register */ /*************************************************************************** *TX_SW_DESC_LIST_CTRL_STS - Tx DMA Software Descriptor List Control and Status ***************************************************************************/ /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */ #define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001 #endif /* #ifndef BCHP_MISC1_H__ */ /********************************************************************** * * $brcm_Workfile: bchp_misc2.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:11p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:37 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc2.h $ * * Hydra_Software_Devel/1 7/17/09 8:11p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_MISC2_H__ #define BCHP_MISC2_H__ /*************************************************************************** *MISC2 - Registers for Meta DMA, Direct DRAM Access, Global Controls ***************************************************************************/ #define BCHP_MISC2_DIRECT_WINDOW_CONTROL 0x00502120 /* Direct DRAM Access Window Control */ /*************************************************************************** *DIRECT_WINDOW_CONTROL - Direct DRAM Access Window Control ***************************************************************************/ /* MISC2 :: DIRECT_WINDOW_CONTROL :: DIRECT_WINDOW_BASE_ADDR [31:16] */ #define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK 0xffff0000 /* MISC2 :: DIRECT_WINDOW_CONTROL :: DIRECT_WINDOW_ENABLE [00:00] */ #define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK 0x00000001 #endif /* #ifndef BCHP_MISC2_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_misc3.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:11p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:19 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc3.h $ * * Hydra_Software_Devel/1 7/17/09 8:11p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_MISC3_H__ #define BCHP_MISC3_H__ /*************************************************************************** *MISC3 - Registers for Reset, Options, DMA Checksums ***************************************************************************/ #define BCHP_MISC3_RESET_CTRL 0x00502200 /* Reset Control Register */ #endif /* #ifndef BCHP_MISC3_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_scrub_ctrl.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:18p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:19 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_scrub_ctrl.h $ * * Hydra_Software_Devel/1 7/17/09 8:18p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_SCRUB_CTRL_H__ #define BCHP_SCRUB_CTRL_H__ /*************************************************************************** *SCRUB_CTRL - Scrub Control Registers ***************************************************************************/ #define BCHP_SCRUB_CTRL_SCRUB_ENABLE 0x000f6000 /* Secure Sequencer Enable */ #define BCHP_SCRUB_CTRL_BORCH_END_ADDRESS 0x000f6004 /* ARM Bridge Out-of-Range Checker End Address */ #define BCHP_SCRUB_CTRL_STARCH_END_ADDRESS 0x000f6008 /* Static ARCH End Address */ #define BCHP_SCRUB_CTRL_BI_CMAC_31_0 0x000f600c /* Boot Image CMAC value[31:0] */ #define BCHP_SCRUB_CTRL_BI_CMAC_63_32 0x000f6010 /* Boot Image CMAC value[63:32] */ #define BCHP_SCRUB_CTRL_BI_CMAC_95_64 0x000f6014 /* Boot Image CMAC value[95:64] */ #define BCHP_SCRUB_CTRL_BI_CMAC_127_96 0x000f6018 /* Boot Image CMAC value[127:96] */ /*************************************************************************** *SCRUB_ENABLE - Secure Sequencer Enable ***************************************************************************/ /* SCRUB_CTRL :: SCRUB_ENABLE :: DSCRAM_EN [01:01] */ #define BCHP_SCRUB_CTRL_SCRUB_ENABLE_DSCRAM_EN_SHIFT 1 /* SCRUB_CTRL :: SCRUB_ENABLE :: SCRUB_EN [00:00] */ #define BCHP_SCRUB_CTRL_SCRUB_ENABLE_SCRUB_EN_SHIFT 0 /*************************************************************************** *BORCH_END_ADDRESS - ARM Bridge Out-of-Range Checker End Address ***************************************************************************/ /* SCRUB_CTRL :: BORCH_END_ADDRESS :: BORCH_END_ADDR [26:00] */ #define BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_BORCH_END_ADDR_MASK 0x07ffffff #endif /* #ifndef BCHP_SCRUB_CTRL_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_wrap_misc_intr2.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:23p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:21 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_intr2.h $ * * Hydra_Software_Devel/1 7/17/09 8:23p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_WRAP_MISC_INTR2_H__ #define BCHP_WRAP_MISC_INTR2_H__ /*************************************************************************** *WRAP_MISC_INTR2 - MISC block Level 2 Interrupt Controller ***************************************************************************/ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS 0x000f2000 /* CPU interrupt Status Register */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS 0x000f2018 /* PCI interrupt Status Register */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR 0x000f2020 /* PCI interrupt Clear Register */ /*************************************************************************** *CPU_STATUS - CPU interrupt Status Register ***************************************************************************/ /* WRAP_MISC_INTR2 :: CPU_STATUS :: BOOT_VER_FAIL_INTR [23:23] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_FAIL_INTR_SHIFT 23 /* WRAP_MISC_INTR2 :: CPU_STATUS :: BOOT_VER_DONE_INTR [22:22] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_DONE_INTR_SHIFT 22 /* WRAP_MISC_INTR2 :: CPU_STATUS :: SCRM_KEY_DONE_INTR [19:19] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SCRM_KEY_DONE_INTR_SHIFT 19 /* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_ERR_INTR [04:04] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_ERR_INTR_SHIFT 4 #endif /* #ifndef BCHP_WRAP_MISC_INTR2_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_armcr4_bridge.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:28p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:56 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge.h $ * * Hydra_Software_Devel/1 7/17/09 8:28p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_ARMCR4_BRIDGE_H__ #define BCHP_ARMCR4_BRIDGE_H__ /*************************************************************************** *ARMCR4_BRIDGE - ARM Cortex R4 Bridge control registers ***************************************************************************/ #define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID 0x000e0000 /* ARM Cortex R4 bridge revision ID */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL 0x000e0004 /* Bridge interface and buffer configuration */ #define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL 0x000e0008 /* ARM core configuration */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS 0x000e0014 /* Bridge interface and buffer status */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI1 0x000e0018 /* PCI mailbox #1 */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1 0x000e001c /* ARM mailbox #1 */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI2 0x000e0020 /* PCI mailbox #2 */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM2 0x000e0024 /* ARM mailbox #2 */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI3 0x000e0028 /* PCI mailbox #3 */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM3 0x000e002c /* ARM mailbox #3 */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI4 0x000e0030 /* PCI mailbox #4 */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM4 0x000e0034 /* ARM mailbox #4 */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_1 0x000e0038 /* CPU semaphore #1 */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_2 0x000e003c /* CPU semaphore #2 */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_3 0x000e0040 /* CPU semaphore #3 */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_4 0x000e0044 /* CPU semaphore #4 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_1 0x000e0048 /* CPU scratchpad #1 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_2 0x000e004c /* CPU scratchpad #2 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_3 0x000e0050 /* CPU scratchpad #3 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_4 0x000e0054 /* CPU scratchpad #4 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_5 0x000e0058 /* CPU scratchpad #5 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_6 0x000e005c /* CPU scratchpad #6 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_7 0x000e0060 /* CPU scratchpad #7 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_8 0x000e0064 /* CPU scratchpad #8 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_9 0x000e0068 /* CPU scratchpad #9 */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_CONFIG 0x000e006c /* Performance monitor configuration */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_LIMIT 0x000e0070 /* Performance monitor count threshold */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_CNT 0x000e0074 /* Counts the number of merge buffer updates (hits + misses) */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_MISS 0x000e0078 /* Counts the number of merge buffer misses */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_CNT 0x000e007c /* Counts the number of prefetch buffer accesses (hits + misses) */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_MISS 0x000e0080 /* Counts the number of prefetch buffer misses */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1 0x000e0084 /* ARM memory TM1 control register */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2 0x000e0088 /* ARM memory TM2 control register */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3 0x000e008c /* ARM memory TM3 control register */ #define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS 0x000e0090 /* Fifo Status */ #define BCHP_ARMCR4_BRIDGE_REG_BORCH_STATUS 0x000e0094 /* Bridge Out-of-range Checker Status */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM4 0x000e0098 /* ARM memory TM4 control register */ /*************************************************************************** *REG_BRIDGE_CTL - Bridge interface and buffer configuration ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: arm_run_request [01:01] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_arm_run_request_SHIFT 1 #endif /* #ifndef BCHP_ARMCR4_BRIDGE_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_intr.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:09p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:44 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_intr.h $ * * Hydra_Software_Devel/1 7/17/09 8:09p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_INTR_H__ #define BCHP_INTR_H__ /*************************************************************************** *INTR - TGT L2 Interrupt Controller Registers ***************************************************************************/ #define BCHP_INTR_INTR_STATUS 0x00500700 /* Interrupt Status Register */ #define BCHP_INTR_INTR_CLR_REG 0x00500708 /* Interrupt Clear Register */ #define BCHP_INTR_INTR_MSK_SET_REG 0x00500710 /* Interrupt Mask Set Register */ #define BCHP_INTR_INTR_MSK_CLR_REG 0x00500714 /* Interrupt Mask Clear Register */ #define BCHP_INTR_EOI_CTRL 0x00500718 /* End of interrupt control register */ #endif /* #ifndef BCHP_INTR_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_pri_arb_control_regs.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:14p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:12 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_control_regs.h $ * * Hydra_Software_Devel/1 7/17/09 8:14p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_ARB_CONTROL_REGS_H__ #define BCHP_PRI_ARB_CONTROL_REGS_H__ /*************************************************************************** *PRI_ARB_CONTROL_REGS - PRIMARY_ARB control registers ***************************************************************************/ #define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0 0x0040cb00 /* Refresh client control for ddr interface #0 */ #define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL 0x0040cb30 /* Master Control */ /*************************************************************************** *REFRESH_CTL_0 - Refresh client control for ddr interface #0 ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: REFRESH_CTL_0 :: enable [12:12] */ #define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_enable_MASK 0x00001000 /*************************************************************************** *MASTER_CTL - Master Control ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: MASTER_CTL :: arb_disable [00:00] */ #define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Enable 0 #define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Disable 1 #endif /* #ifndef BCHP_PRI_ARB_CONTROL_REGS_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_ddr23_ctl_regs_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:59p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:08 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_ctl_regs_0.h $ * * Hydra_Software_Devel/1 7/17/09 7:59p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DDR23_CTL_REGS_0_H__ #define BCHP_DDR23_CTL_REGS_0_H__ /*************************************************************************** *DDR23_CTL_REGS_0 - DDR23 controller registers ***************************************************************************/ #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS 0x01800004 /* DDR23 Controller status register */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1 0x01800010 /* DDR23 Controller Configuration Set #1 */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2 0x01800014 /* DDR23 Controller Configuration Set #2 */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3 0x01800018 /* DDR23 Controller Configuration Set #3 */ #define BCHP_DDR23_CTL_REGS_0_REFRESH 0x0180001c /* DDR23 Controller Automated Refresh Configuration */ #define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD 0x01800020 /* Host Initiated Refresh Control */ #define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD 0x01800024 /* Host Initiated Precharge Control */ #define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD 0x01800028 /* Host Initiated Load Mode Control */ #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD 0x0180002c /* Host Initiated Load Extended Mode Control */ #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD 0x01800030 /* Host Initiated Load Extended Mode #2 Control */ #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD 0x01800034 /* Host Initiated Load Extended Mode #3 Control */ #define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE 0x01800038 /* Host Initiated ZQ Calibration Cycle */ #define BCHP_DDR23_CTL_REGS_0_LATENCY 0x01800040 /* DDR2 Controller Access Latency Control */ #define BCHP_DDR23_CTL_REGS_0_SCRATCH 0x01800058 /* Scratch Register */ #define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL 0x018000f0 /* RAM Macro TM Control */ /*************************************************************************** *CTL_STATUS - DDR23 Controller status register ***************************************************************************/ /* DDR23_CTL_REGS_0 :: CTL_STATUS :: clke [01:01] */ #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_MASK 0x00000002 /* DDR23_CTL_REGS_0 :: CTL_STATUS :: idle [00:00] */ #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_MASK 0x00000001 /*************************************************************************** *PARAMS1 - DDR23 Controller Configuration Set #1 ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PARAMS1 :: trtp [31:28] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trtp_MASK 0xf0000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trtp_SHIFT 28 /* DDR23_CTL_REGS_0 :: PARAMS1 :: twl [27:24] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_twl_MASK 0x0f000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS1_twl_SHIFT 24 /* DDR23_CTL_REGS_0 :: PARAMS1 :: tcas [23:20] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_tcas_MASK 0x00f00000 #define BCHP_DDR23_CTL_REGS_0_PARAMS1_tcas_SHIFT 20 /* DDR23_CTL_REGS_0 :: PARAMS1 :: twtr [19:16] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_twtr_MASK 0x000f0000 #define BCHP_DDR23_CTL_REGS_0_PARAMS1_twtr_SHIFT 16 /* DDR23_CTL_REGS_0 :: PARAMS1 :: twr [15:12] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_twr_MASK 0x0000f000 #define BCHP_DDR23_CTL_REGS_0_PARAMS1_twr_SHIFT 12 /* DDR23_CTL_REGS_0 :: PARAMS1 :: trrd [11:08] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trrd_MASK 0x00000f00 #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trrd_SHIFT 8 /* DDR23_CTL_REGS_0 :: PARAMS1 :: trp [07:04] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trp_MASK 0x000000f0 #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trp_SHIFT 4 /* DDR23_CTL_REGS_0 :: PARAMS1 :: trcd [03:00] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trcd_MASK 0x0000000f #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trcd_SHIFT 0 /*************************************************************************** *PARAMS2 - DDR23 Controller Configuration Set #2 ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PARAMS2 :: auto_idle [31:31] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_auto_idle_MASK 0x80000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_auto_idle_SHIFT 31 /* DDR23_CTL_REGS_0 :: PARAMS2 :: row_bits [30:30] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_row_bits_MASK 0x40000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_row_bits_SHIFT 30 /* DDR23_CTL_REGS_0 :: PARAMS2 :: use_chr_hgt [29:29] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_use_chr_hgt_MASK 0x20000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_use_chr_hgt_SHIFT 29 /* DDR23_CTL_REGS_0 :: PARAMS2 :: clke [28:28] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_MASK 0x10000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_SHIFT 28 /* DDR23_CTL_REGS_0 :: PARAMS2 :: sd_col_bits [27:26] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_sd_col_bits_MASK 0x0c000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_sd_col_bits_SHIFT 26 /* DDR23_CTL_REGS_0 :: PARAMS2 :: il_sel [25:25] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_il_sel_MASK 0x02000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_il_sel_SHIFT 25 /* DDR23_CTL_REGS_0 :: PARAMS2 :: dis_itlv [24:24] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_dis_itlv_MASK 0x01000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_dis_itlv_SHIFT 24 /* DDR23_CTL_REGS_0 :: PARAMS2 :: reserved0 [23:23] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_reserved0_MASK 0x00800000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_reserved0_SHIFT 23 /* DDR23_CTL_REGS_0 :: PARAMS2 :: cs0_only [22:22] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_cs0_only_MASK 0x00400000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_cs0_only_SHIFT 22 /* DDR23_CTL_REGS_0 :: PARAMS2 :: allow_pictmem_rd [21:21] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_allow_pictmem_rd_MASK 0x00200000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_allow_pictmem_rd_SHIFT 21 /* DDR23_CTL_REGS_0 :: PARAMS2 :: bank_bits [20:20] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_bank_bits_MASK 0x00100000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_bank_bits_SHIFT 20 /* DDR23_CTL_REGS_0 :: PARAMS2 :: trfc [19:12] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_trfc_MASK 0x000ff000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_trfc_SHIFT 12 /* DDR23_CTL_REGS_0 :: PARAMS2 :: tfaw [11:06] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_tfaw_MASK 0x00000fc0 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_tfaw_SHIFT 6 /* DDR23_CTL_REGS_0 :: PARAMS2 :: tras [05:00] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_tras_MASK 0x0000003f #define BCHP_DDR23_CTL_REGS_0_PARAMS2_tras_SHIFT 0 /*************************************************************************** *PARAMS3 - DDR23 Controller Configuration Set #3 ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PARAMS3 :: ddr3_reset [31:31] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr3_reset_MASK 0x80000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr3_reset_SHIFT 31 /* DDR23_CTL_REGS_0 :: PARAMS3 :: reserved0 [30:06] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved0_MASK 0x7fffffc0 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved0_SHIFT 6 /* DDR23_CTL_REGS_0 :: PARAMS3 :: ddr_bl [05:05] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr_bl_MASK 0x00000020 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr_bl_SHIFT 5 /* DDR23_CTL_REGS_0 :: PARAMS3 :: cmd_2t [04:04] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_cmd_2t_MASK 0x00000010 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_cmd_2t_SHIFT 4 /* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_mode [03:03] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_mode_MASK 0x00000008 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_mode_SHIFT 3 /* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_te_adj [02:02] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_te_adj_MASK 0x00000004 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_te_adj_SHIFT 2 /* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_le_adj [01:01] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_le_adj_MASK 0x00000002 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_le_adj_SHIFT 1 /* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_en [00:00] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_MASK 0x00000001 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_SHIFT 0 /*************************************************************************** *UPDATE_VDL - RAM Macro TM Control ***************************************************************************/ /* DDR23_CTL_REGS_0 :: UPDATE_VDL :: refresh [00:00] */ #define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_refresh_MASK 0x00000001 #endif /* #ifndef BCHP_DDR23_CTL_REGS_0_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_ddr23_phy_byte_lane_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:59p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:18 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_0.h $ * * Hydra_Software_Devel/1 7/17/09 7:59p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DDR23_PHY_BYTE_LANE_0_H__ #define BCHP_DDR23_PHY_BYTE_LANE_0_H__ /*************************************************************************** *DDR23_PHY_BYTE_LANE_0 - DDR23 DDR23 byte lane #0 control registers ***************************************************************************/ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE 0x01801204 /* Byte lane VDL calibration control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS 0x01801208 /* Byte lane VDL calibration status register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0 0x01801210 /* Read DQSP VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1 0x01801214 /* Read DQSN VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2 0x01801218 /* Read Enable VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3 0x0180121c /* Write data and mask VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL 0x01801230 /* Byte Lane read channel control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x0180123c /* Idle mode SSTL pad control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL 0x01801240 /* SSTL pad drive characteristics control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE 0x01801248 /* Write cycle preamble control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL 0x0180124c /* Clock Regulator control register */ /*************************************************************************** *READ_CONTROL - Byte Lane read channel control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_data_dly [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: dq_odt_enable [03:03] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_MASK 0x00000008 #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_SHIFT 3 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: dq_odt_adj [02:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_MASK 0x00000004 #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_SHIFT 2 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_enb_odt_enable [01:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_MASK 0x00000002 #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_enb_odt_adj [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_SHIFT 0 /*************************************************************************** *IDLE_PAD_CONTROL - Idle mode SSTL pad control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: idle [31:31] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_MASK 0x80000000 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_iddq [18:18] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_iddq_MASK 0x00040000 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_iddq [14:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00004000 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_iddq [10:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00000400 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_iddq [06:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000040 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_iddq [02:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_iddq_MASK 0x00000004 /*************************************************************************** *DRIVE_PAD_CTL - SSTL pad drive characteristics control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_seltxdrv_ci_MASK 0x00000004 /*************************************************************************** *CLOCK_REG_CONTROL - Clock Regulator control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_MASK 0x00000001 #endif /* #ifndef BCHP_DDR23_PHY_BYTE_LANE_0_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_ddr23_phy_byte_lane_1.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:59p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:17 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_1.h $ * * Hydra_Software_Devel/1 7/17/09 7:59p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DDR23_PHY_BYTE_LANE_1_H__ #define BCHP_DDR23_PHY_BYTE_LANE_1_H__ /*************************************************************************** *DDR23_PHY_BYTE_LANE_1 - DDR23 DDR23 byte lane #1 control registers ***************************************************************************/ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE 0x01801104 /* Byte lane VDL calibration control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS 0x01801108 /* Byte lane VDL calibration status register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0 0x01801110 /* Read DQSP VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1 0x01801114 /* Read DQSN VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2 0x01801118 /* Read Enable VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3 0x0180111c /* Write data and mask VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL 0x01801130 /* Byte Lane read channel control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x0180113c /* Idle mode SSTL pad control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL 0x01801140 /* SSTL pad drive characteristics control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE 0x01801144 /* Clock pad disable register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE 0x01801148 /* Write cycle preamble control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL 0x0180114c /* Clock Regulator control register */ /*************************************************************************** *READ_CONTROL - Byte Lane read channel control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: dq_odt_enable [03:03] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_dq_odt_enable_MASK 0x00000008 /*************************************************************************** *IDLE_PAD_CONTROL - Idle mode SSTL pad control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: idle [31:31] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_MASK 0x80000000 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_iddq [18:18] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_iddq_MASK 0x00040000 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_iddq [14:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00004000 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_iddq [10:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00000400 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_iddq [06:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000040 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_iddq [02:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_iddq_MASK 0x00000004 /*************************************************************************** *DRIVE_PAD_CTL - SSTL pad drive characteristics control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: reserved0 [31:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffffc0 #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_reserved0_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: rt60b_ddr_read_enb [05:05] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_ddr_read_enb_MASK 0x00000020 #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_ddr_read_enb_SHIFT 5 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: rt60b [04:04] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_MASK 0x00000010 #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_SHIFT 4 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_sel_sstl18_MASK 0x00000008 #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_sel_sstl18_SHIFT 3 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_seltxdrv_ci_MASK 0x00000004 #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_seltxdrv_ci_SHIFT 2 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: selrxdrv [01:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_selrxdrv_MASK 0x00000002 #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_selrxdrv_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: slew [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_slew_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_slew_SHIFT 0 /*************************************************************************** *CLOCK_PAD_DISABLE - Clock pad disable register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: CLOCK_PAD_DISABLE :: clk_pad_dis [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE_clk_pad_dis_MASK 0x00000001 /*************************************************************************** *CLOCK_REG_CONTROL - Clock Regulator control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_MASK 0x00000001 #endif /* #ifndef BCHP_DDR23_PHY_BYTE_LANE_1_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_ddr23_phy_control_regs.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:59p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:21 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_control_regs.h $ * * Hydra_Software_Devel/1 7/17/09 7:59p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DDR23_PHY_CONTROL_REGS_H__ #define BCHP_DDR23_PHY_CONTROL_REGS_H__ /*************************************************************************** *DDR23_PHY_CONTROL_REGS - DDR23 DDR23 physical interface control registers ***************************************************************************/ #define BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL 0x01801004 /* PHY clock power management control register */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS 0x01801010 /* PHY PLL status register */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG 0x01801014 /* PHY PLL configuration register */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER 0x01801018 /* PHY PLL pre-divider control register */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER 0x0180101c /* PHY PLL divider control register */ #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE 0x01801030 /* Address & Control VDL static override control register */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x01801038 /* Idle mode SSTL pad control register */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL 0x0180103c /* PVT Compensation control and status register */ #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL 0x01801040 /* SSTL pad drive characteristics control register */ #define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL 0x01801044 /* Clock Regulator control register */ /*************************************************************************** *CLK_PM_CTRL - PHY clock power management control register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001 /*************************************************************************** *PLL_CONFIG - PHY PLL configuration register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: ENB_CLKOUT [04:04] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_ENB_CLKOUT_MASK 0x00000010 /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: PWRDN [00:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK 0x00000001 /*************************************************************************** *IDLE_PAD_CONTROL - Idle mode SSTL pad control register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: idle [31:31] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_MASK 0x80000000 /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: rxenb [08:08] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_rxenb_MASK 0x00000100 /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040 /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: cke_reb [01:01] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002 /*************************************************************************** *DRIVE_PAD_CTL - SSTL pad drive characteristics control register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: reserved0 [31:05] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_MASK 0xffffffe0 #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_SHIFT 5 /* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: rt60b [04:04] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt60b_MASK 0x00000010 #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt60b_SHIFT 4 /* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_sel_sstl18_MASK 0x00000008 #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_sel_sstl18_SHIFT 3 /* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_seltxdrv_ci_MASK 0x00000004 #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_seltxdrv_ci_SHIFT 2 /* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: selrxdrv [01:01] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_selrxdrv_MASK 0x00000002 #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_selrxdrv_SHIFT 1 /* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: slew [00:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_slew_MASK 0x00000001 #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_slew_SHIFT 0 /*************************************************************************** *ZQ_PVT_COMP_CTL - PVT Compensation control and status register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: sample_done [28:28] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_done_MASK 0x10000000 /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: sample_en [26:26] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_en_MASK 0x04000000 /*************************************************************************** *CLOCK_REG_CONTROL - Clock Regulator control register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_MASK 0x00000001 #endif /* #ifndef BCHP_DDR23_PHY_CONTROL_REGS_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_clk.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:58p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:39 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_clk.h $ * * Hydra_Software_Devel/1 7/17/09 7:58p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_CLK_H__ #define BCHP_CLK_H__ /*************************************************************************** *CLK - CLOCK_GEN Registers ***************************************************************************/ #define BCHP_CLK_PM_CTRL 0x00070004 /* Software power management control to turn off clocks */ #define BCHP_CLK_TEMP_MON_CTRL 0x00070040 /* Temperature monitor control. */ #define BCHP_CLK_TEMP_MON_STATUS 0x00070044 /* Temperature monitor status. */ #define BCHP_CLK_PLL0_ARM_DIV 0x00070110 /* Main PLL0 channel 3 ARM clock divider settings */ #define BCHP_CLK_PLL1_CTRL 0x00070120 /* Main PLL1 reset, enable, powerdown, and control */ /*************************************************************************** *PM_CTRL - Software power management control to turn off clocks ***************************************************************************/ /* CLK :: PM_CTRL :: DIS_SUN_27_LOW_PWR [25:25] */ #define BCHP_CLK_PM_CTRL_DIS_SUN_27_LOW_PWR_MASK 0x02000000 /* CLK :: PM_CTRL :: DIS_SUN_108_LOW_PWR [24:24] */ #define BCHP_CLK_PM_CTRL_DIS_SUN_108_LOW_PWR_MASK 0x01000000 /* CLK :: PM_CTRL :: DIS_MISC_OTP_9_CLK [19:19] */ #define BCHP_CLK_PM_CTRL_DIS_MISC_OTP_9_CLK_MASK 0x00080000 /* CLK :: PM_CTRL :: DIS_ARM_CLK [18:18] */ #define BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK 0x00040000 /* CLK :: PM_CTRL :: DIS_AVD_CLK [17:17] */ #define BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK 0x00020000 /* CLK :: PM_CTRL :: DIS_BLINK_108_CLK [12:12] */ #define BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK 0x00001000 /* CLK :: PM_CTRL :: DIS_DDR_108_CLK [11:11] */ #define BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_MASK 0x00000800 /* CLK :: PM_CTRL :: DIS_AVD_108_CLK [10:10] */ #define BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK 0x00000400 /* CLK :: PM_CTRL :: DIS_MISC_108_CLK [09:09] */ #define BCHP_CLK_PM_CTRL_DIS_MISC_108_CLK_MASK 0x00000200 /* CLK :: PM_CTRL :: DIS_BLINK_216_CLK [04:04] */ #define BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK 0x00000010 /* CLK :: PM_CTRL :: DIS_DDR_216_CLK [03:03] */ #define BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_MASK 0x00000008 /* CLK :: PM_CTRL :: DIS_AVD_216_CLK [02:02] */ #define BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK 0x00000004 /* CLK :: PM_CTRL :: DIS_MISC_216_CLK [01:01] */ #define BCHP_CLK_PM_CTRL_DIS_MISC_216_CLK_MASK 0x00000002 /* CLK :: PM_CTRL :: DIS_SUN_216_CLK [00:00] */ #define BCHP_CLK_PM_CTRL_DIS_SUN_216_CLK_MASK 0x00000001 /*************************************************************************** *PLL1_CTRL - Main PLL1 reset, enable, powerdown, and control ***************************************************************************/ /* CLK :: PLL1_CTRL :: POWERDOWN [03:03] */ #define BCHP_CLK_PLL1_CTRL_POWERDOWN_MASK 0x00000008 #endif /* #ifndef BCHP_CLK_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_pcie_tl.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:13p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:28 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_tl.h $ * * Hydra_Software_Devel/1 7/17/09 8:13p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PCIE_TL_H__ #define BCHP_PCIE_TL_H__ /*************************************************************************** *PCIE_TL - PCIE TL related registers ***************************************************************************/ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION 0x00500404 /* TRANSACTION_CONFIGURATION Register */ #endif /* #ifndef BCHP_PCIE_TL_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_sun_gisb_arb.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:19p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:30 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb.h $ * * Hydra_Software_Devel/1 7/17/09 8:19p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_SUN_GISB_ARB_H__ #define BCHP_SUN_GISB_ARB_H__ /*************************************************************************** *SUN_GISB_ARB - GISB Arbiter registers ***************************************************************************/ #define BCHP_SUN_GISB_ARB_TIMER 0x0040000c /* GISB ARBITER Timer Value Register */ #endif /* #ifndef BCHP_SUN_GISB_ARB_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_misc_perst.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:12p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:23 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc_perst.h $ * * Hydra_Software_Devel/1 7/17/09 8:12p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_MISC_PERST_H__ #define BCHP_MISC_PERST_H__ /*************************************************************************** *MISC_PERST - Registers for Link reset on PERST_N ***************************************************************************/ #define BCHP_MISC_PERST_CLOCK_CTRL 0x0050229c /* Clock Control Register */ /*************************************************************************** *CLOCK_CTRL - Clock Control Register ***************************************************************************/ /* MISC_PERST :: CLOCK_CTRL :: EARLY_L1_EXIT [02:02] */ #define BCHP_MISC_PERST_CLOCK_CTRL_EARLY_L1_EXIT_MASK 0x00000004 #endif /* #ifndef BCHP_MISC_PERST_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_sun_top_ctrl.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:20p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:07 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_top_ctrl.h $ * * Hydra_Software_Devel/1 7/17/09 8:20p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_SUN_TOP_CTRL_H__ #define BCHP_SUN_TOP_CTRL_H__ /*************************************************************************** *SUN_TOP_CTRL - Top Control registers ***************************************************************************/ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0 0x00404100 /* Pinmux control register 0 */ #endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_gio.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:07p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:13 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_gio.h $ * * Hydra_Software_Devel/1 7/17/09 8:07p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_GIO_H__ #define BCHP_GIO_H__ /*************************************************************************** *GIO - GPIO ***************************************************************************/ #define BCHP_GIO_DATA_LO 0x00406004 /* GENERAL PURPOSE I/O DATA [31:0] */ #define BCHP_GIO_IODIR_LO 0x00406008 /* GENERAL PURPOSE I/O DIRECTION [31:0] */ #endif /* #ifndef BCHP_GIO_H__ */ /*************************************************************************** * * $brcm_Workfile: bchp_pri_client_regs.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:16p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:12 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_client_regs.h $ * * Hydra_Software_Devel/1 7/17/09 8:16p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_CLIENT_REGS_H__ #define BCHP_PRI_CLIENT_REGS_H__ /*************************************************************************** *PRI_CLIENT_REGS - PRIMARY_ARB_CLIENTS client configuration registers ***************************************************************************/ #define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT 0x0040c000 /* Arbiter Client DEBLOCK Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL 0x0040c004 /* Arbiter Client DEBLOCK Configuration Register */ #endif /* #ifndef BCHP_PRI_CLIENT_REGS_H__ */ crystalhd-0.0~git20110715.fdd2f19/include/flea/crystalhd_flea_rdb.h0000644000175000017500000001173711610313111024054 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: crystalhd_flea_rdb.h * * Description: common include for flea register definition. * * AU * * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ // 70015\magnum\basemodules\chp\70015\rdb\a0 #include "bchp_armcr4_bridge.h" #include "bchp_armcr4_bridge_axi_slave.h" #include "bchp_arm_uart.h" #include "bchp_avd_block_avg_regs_0.h" #include "bchp_avd_cache_0.h" #include "bchp_avd_gr_0.h" #include "bchp_avd_intr2_0.h" #include "bchp_bop_aes.h" #include "bchp_bop_gr_bridge.h" #include "bchp_bvnt_gr_bridge.h" #include "bchp_bvnt_intr2.h" #include "bchp_cce_rgr_bridge.h" #include "bchp_clk.h" #include "bchp_clk_gr.h" #include "bchp_common.h" #include "bchp_csc.h" #include "bchp_ddr23_ctl_regs_0.h" #include "bchp_ddr23_phy_byte_lane_0.h" #include "bchp_ddr23_phy_byte_lane_1.h" #include "bchp_ddr23_phy_control_regs.h" #include "bchp_decode_cpuaux2_0.h" #include "bchp_decode_cpuaux_0.h" #include "bchp_decode_cpucore2_0.h" #include "bchp_decode_cpucore_0.h" #include "bchp_decode_cpudma2_0.h" #include "bchp_decode_cpudma_0.h" #include "bchp_decode_cpudmem2_0.h" #include "bchp_decode_cpudmem_0.h" #include "bchp_decode_cpuimem2_0.h" #include "bchp_decode_cpuimem_0.h" #include "bchp_decode_cpuregs2_0.h" #include "bchp_decode_cpuregs_0.h" #include "bchp_decode_dblk_0.h" #include "bchp_decode_dmamem2_0.h" #include "bchp_decode_dmamem_0.h" #include "bchp_decode_dqnt_0.h" #include "bchp_decode_dqnt_8x8_0.h" #include "bchp_decode_ind_sdram_regs2_0.h" #include "bchp_decode_ind_sdram_regs_0.h" #include "bchp_decode_ip_shim_0.h" #include "bchp_decode_main_0.h" #include "bchp_decode_mb_0.h" #include "bchp_decode_mcom_0.h" #include "bchp_decode_rvc_0.h" #include "bchp_decode_sint_0.h" #include "bchp_decode_sint_oloop_0.h" #include "bchp_decode_spre_0.h" #include "bchp_decode_wprd_0.h" #include "bchp_decode_wptbl_0.h" #include "bchp_decode_xfrm_0.h" #include "bchp_dnr.h" #include "bchp_gio.h" #include "bchp_i2c.h" #include "bchp_i2c_gr_bridge.h" #include "bchp_intr.h" #include "bchp_int_id_irq0.h" #include "bchp_int_id_timer.h" #include "bchp_int_id_xpt_pb0.h" #include "bchp_int_id_xpt_pb1.h" #include "bchp_int_id_xpt_pb2.h" #include "bchp_int_id_xpt_rave.h" #include "bchp_irq0.h" #include "bchp_irq1.h" #include "bchp_l1_intr.h" #include "bchp_mdio.h" #include "bchp_mem_dma.h" #include "bchp_mem_dma_secure.h" #include "bchp_mfd.h" #include "bchp_misc1.h" #include "bchp_misc2.h" #include "bchp_misc3.h" #include "bchp_misc_gr_bridge.h" #include "bchp_misc_perst.h" #include "bchp_mmscram.h" #include "bchp_pcie_cfg.h" #include "bchp_pcie_dll.h" #include "bchp_pcie_phy.h" #include "bchp_pcie_tl.h" #include "bchp_pm_l2.h" #include "bchp_pri_arb_arch_regs.h" #include "bchp_pri_arb_arc_l1_regs.h" #include "bchp_pri_arb_control_regs.h" #include "bchp_pri_arb_mips_l2_regs.h" #include "bchp_pri_arb_msa_regs.h" #include "bchp_pri_arb_sarch_regs.h" #include "bchp_pri_arb_starch_regs.h" #include "bchp_pri_arb_trace_regs.h" #include "bchp_pri_arb_wrch_regs.h" #include "bchp_pri_client_regs.h" #include "bchp_pri_crit_l2_regs_1.h" #include "bchp_pri_crit_l2_regs_2.h" #include "bchp_pri_crit_l2_regs_3.h" #include "bchp_pri_rts_l2_regs_1.h" #include "bchp_pri_rts_l2_regs_2.h" #include "bchp_pri_rts_l2_regs_3.h" #include "bchp_reg_cabac2bins2_0.h" #include "bchp_reg_cabac2bins_0.h" #include "bchp_scl_hd.h" #include "bchp_scrub_ctrl.h" #include "bchp_sentinel.h" #include "bchp_sharf_mem_dma0.h" #include "bchp_sharf_top.h" #include "bchp_sun_gisb_arb.h" #include "bchp_sun_gisb_arb_sec.h" #include "bchp_sun_l2.h" #include "bchp_sun_rg.h" #include "bchp_sun_rgr.h" #include "bchp_sun_top_ctrl.h" #include "bchp_tgt_rgr_bridge.h" #include "bchp_timer.h" #include "bchp_tmisc.h" #include "bchp_trb_top.h" #include "bchp_triple_sec.h" #include "bchp_vich_0.h" #include "bchp_wakeup_ctrl2.h" #include "bchp_wrap_misc_gr_bridge.h" #include "bchp_wrap_misc_intr2.h" #include "bchp_wrap_misc_secure_intr2.h" #include "bchp_xpt_bus_if.h" #include "bchp_xpt_fe.h" #include "bchp_xpt_gr.h" #include "bchp_xpt_pb0.h" #include "bchp_xpt_pb1.h" #include "bchp_xpt_pb2.h" #include "bchp_xpt_pcroffset.h" #include "bchp_xpt_rave.h" #include "bchp_xpt_xmemif.h" #include "bchp_xpt_xpu.h" crystalhd-0.0~git20110715.fdd2f19/include/flea/70015/0000755000175000017500000000000011610313111020533 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/0000755000175000017500000000000011610313111022017 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/0000755000175000017500000000000011610313111024322 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/0000755000175000017500000000000011610313111025074 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/0000755000175000017500000000000011610313111025550 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/0000755000175000017500000000000011610313111026317 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/0000755000175000017500000000000011610313111026617 5ustar andresandres././@LongLink0000000000000000000000000000015700000000000011570 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_wptbl_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000523111610313111030762 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_wptbl_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:06p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:05 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_wptbl_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:06p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_WPTBL_0_H__ #define BCHP_DECODE_WPTBL_0_H__ /*************************************************************************** *DECODE_WPTBL_0 ***************************************************************************/ #define BCHP_DECODE_WPTBL_0_WPTBL_END 0x008031fc /* DECODE_WPTBL_END */ /*************************************************************************** *WPTBL_END - DECODE_WPTBL_END ***************************************************************************/ /* DECODE_WPTBL_0 :: WPTBL_END :: reserved0 [31:00] */ #define BCHP_DECODE_WPTBL_0_WPTBL_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_WPTBL_0_WPTBL_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_WPTBL_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016100000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuimem_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000616011610313111030764 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_cpuimem_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:02p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:14 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuimem_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:02p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_CPUIMEM_0_H__ #define BCHP_DECODE_CPUIMEM_0_H__ /*************************************************************************** *DECODE_CPUIMEM_0 ***************************************************************************/ #define BCHP_DECODE_CPUIMEM_0_CPUIMEM_REG 0x00846000 /* CPUIMEM_REG */ #define BCHP_DECODE_CPUIMEM_0_CPUIMEM_END 0x00847ffc /* CPUIMEM_END */ /*************************************************************************** *CPUIMEM_REG - CPUIMEM_REG ***************************************************************************/ /* DECODE_CPUIMEM_0 :: CPUIMEM_REG :: Addr [31:00] */ #define BCHP_DECODE_CPUIMEM_0_CPUIMEM_REG_Addr_MASK 0xffffffff #define BCHP_DECODE_CPUIMEM_0_CPUIMEM_REG_Addr_SHIFT 0 /*************************************************************************** *CPUIMEM_END - CPUIMEM_END ***************************************************************************/ /* DECODE_CPUIMEM_0 :: CPUIMEM_END :: reserved0 [31:00] */ #define BCHP_DECODE_CPUIMEM_0_CPUIMEM_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_CPUIMEM_0_CPUIMEM_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_CPUIMEM_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016200000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpucore2_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000455711610313111030774 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_cpucore2_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:00p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:08 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpucore2_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:00p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_CPUCORE2_0_H__ #define BCHP_DECODE_CPUCORE2_0_H__ /*************************************************************************** *DECODE_CPUCORE2_0 ***************************************************************************/ #define BCHP_DECODE_CPUCORE2_0_CPUCORE_REG 0x00854000 /* CPUCORE_REG */ #define BCHP_DECODE_CPUCORE2_0_CPUCORE_END 0x00854ffc /* CPUCORE_END */ #endif /* #ifndef BCHP_DECODE_CPUCORE2_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015200000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_top.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_0000644000175000017500000005566211610313111031016 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_sharf_top.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:19p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:02 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_top.h $ * * Hydra_Software_Devel/1 7/17/09 8:19p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_SHARF_TOP_H__ #define BCHP_SHARF_TOP_H__ /*************************************************************************** *SHARF_TOP - SHARF Control Registers ***************************************************************************/ #define BCHP_SHARF_TOP_REVISION 0x000f4000 /* SHARF REVISION */ #define BCHP_SHARF_TOP_STATUS 0x000f4004 /* SHARF Status */ #define BCHP_SHARF_TOP_SHA0_31_00 0x000f4008 /* SHA Context0 State[31:0] */ #define BCHP_SHARF_TOP_SHA0_63_32 0x000f400c /* SHA Context0 State[63:32] */ #define BCHP_SHARF_TOP_SHA0_95_64 0x000f4010 /* SHA Context0 State[95:64] */ #define BCHP_SHARF_TOP_SHA0_127_96 0x000f4014 /* SHA Context0 State[127:96] */ #define BCHP_SHARF_TOP_SHA0_159_128 0x000f4018 /* SHA Context0 State[159:128] */ #define BCHP_SHARF_TOP_SHA0_191_160 0x000f401c /* SHA Context0 State[191:160] */ #define BCHP_SHARF_TOP_SHA0_223_192 0x000f4020 /* SHA Context0 State[223:192] */ #define BCHP_SHARF_TOP_SHA0_255_224 0x000f4024 /* SHA Context0 State[255:224] */ #define BCHP_SHARF_TOP_SHA1_31_00 0x000f4028 /* SHA Context1 State[31:0] */ #define BCHP_SHARF_TOP_SHA1_63_32 0x000f402c /* SHA Context1 State[63:32] */ #define BCHP_SHARF_TOP_SHA1_95_64 0x000f4030 /* SHA Context1 State[95:64] */ #define BCHP_SHARF_TOP_SHA1_127_96 0x000f4034 /* SHA Context1 State[127:96] */ #define BCHP_SHARF_TOP_SHA1_159_128 0x000f4038 /* SHA Context1 State[159:128] */ #define BCHP_SHARF_TOP_SHA1_191_160 0x000f403c /* SHA Context1 State[191:160] */ #define BCHP_SHARF_TOP_SHA1_223_192 0x000f4040 /* SHA Context1 State[223:192] */ #define BCHP_SHARF_TOP_SHA1_255_224 0x000f4044 /* SHA Context1 State[255:224] */ #define BCHP_SHARF_TOP_SHA2_31_00 0x000f4048 /* SHA Context2 State[31:0] */ #define BCHP_SHARF_TOP_SHA2_63_32 0x000f404c /* SHA Context2 State[63:32] */ #define BCHP_SHARF_TOP_SHA2_95_64 0x000f4050 /* SHA Context2 State[95:64] */ #define BCHP_SHARF_TOP_SHA2_127_96 0x000f4054 /* SHA Context2 State[127:96] */ #define BCHP_SHARF_TOP_SHA2_159_128 0x000f4058 /* SHA Context2 State[159:128] */ #define BCHP_SHARF_TOP_SHA2_191_160 0x000f405c /* SHA Context2 State[191:160] */ #define BCHP_SHARF_TOP_SHA2_223_192 0x000f4060 /* SHA Context2 State[223:192] */ #define BCHP_SHARF_TOP_SHA2_255_224 0x000f4064 /* SHA Context2 State[255:224] */ #define BCHP_SHARF_TOP_CMAC0_31_00 0x000f4068 /* CMAC Context0 State[31:0] */ #define BCHP_SHARF_TOP_CMAC0_63_32 0x000f406c /* CMAC Context0 State[63:32] */ #define BCHP_SHARF_TOP_CMAC0_95_64 0x000f4070 /* CMAC Context0 State[95:64] */ #define BCHP_SHARF_TOP_CMAC0_127_96 0x000f4074 /* CMAC Context0 State[127:96] */ #define BCHP_SHARF_TOP_CMAC1_31_00 0x000f4078 /* CMAC Context1 State[31:0] */ #define BCHP_SHARF_TOP_CMAC1_63_32 0x000f407c /* CMAC Context1 State[63:32] */ #define BCHP_SHARF_TOP_CMAC1_95_64 0x000f4080 /* CMAC Context1 State[95:64] */ #define BCHP_SHARF_TOP_CMAC1_127_96 0x000f4084 /* CMAC Context1 State[127:96] */ #define BCHP_SHARF_TOP_CTXT0_FAIL_ID 0x000f4088 /* Context 0 Fail ID register */ #define BCHP_SHARF_TOP_CTXT1_FAIL_ID 0x000f408c /* Context 1 Fail ID register */ #define BCHP_SHARF_TOP_CTXT2_FAIL_ID 0x000f4090 /* Context 2 Fail ID register (SHA only) */ #define BCHP_SHARF_TOP_ERR_STATUS 0x000f4094 /* SHARF Error Status */ /*************************************************************************** *REVISION - SHARF REVISION ***************************************************************************/ /* SHARF_TOP :: REVISION :: reserved0 [31:16] */ #define BCHP_SHARF_TOP_REVISION_reserved0_MASK 0xffff0000 #define BCHP_SHARF_TOP_REVISION_reserved0_SHIFT 16 /* SHARF_TOP :: REVISION :: MAJOR [15:08] */ #define BCHP_SHARF_TOP_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_SHARF_TOP_REVISION_MAJOR_SHIFT 8 /* SHARF_TOP :: REVISION :: MINOR [07:00] */ #define BCHP_SHARF_TOP_REVISION_MINOR_MASK 0x000000ff #define BCHP_SHARF_TOP_REVISION_MINOR_SHIFT 0 /*************************************************************************** *STATUS - SHARF Status ***************************************************************************/ /* SHARF_TOP :: STATUS :: reserved0 [31:04] */ #define BCHP_SHARF_TOP_STATUS_reserved0_MASK 0xfffffff0 #define BCHP_SHARF_TOP_STATUS_reserved0_SHIFT 4 /* SHARF_TOP :: STATUS :: FAIL2 [03:03] */ #define BCHP_SHARF_TOP_STATUS_FAIL2_MASK 0x00000008 #define BCHP_SHARF_TOP_STATUS_FAIL2_SHIFT 3 /* SHARF_TOP :: STATUS :: FAIL1 [02:02] */ #define BCHP_SHARF_TOP_STATUS_FAIL1_MASK 0x00000004 #define BCHP_SHARF_TOP_STATUS_FAIL1_SHIFT 2 /* SHARF_TOP :: STATUS :: FAIL0 [01:01] */ #define BCHP_SHARF_TOP_STATUS_FAIL0_MASK 0x00000002 #define BCHP_SHARF_TOP_STATUS_FAIL0_SHIFT 1 /* SHARF_TOP :: STATUS :: ACTIVE [00:00] */ #define BCHP_SHARF_TOP_STATUS_ACTIVE_MASK 0x00000001 #define BCHP_SHARF_TOP_STATUS_ACTIVE_SHIFT 0 /*************************************************************************** *SHA0_31_00 - SHA Context0 State[31:0] ***************************************************************************/ /* SHARF_TOP :: SHA0_31_00 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA0_31_00_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA0_31_00_STATE_SHIFT 0 /*************************************************************************** *SHA0_63_32 - SHA Context0 State[63:32] ***************************************************************************/ /* SHARF_TOP :: SHA0_63_32 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA0_63_32_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA0_63_32_STATE_SHIFT 0 /*************************************************************************** *SHA0_95_64 - SHA Context0 State[95:64] ***************************************************************************/ /* SHARF_TOP :: SHA0_95_64 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA0_95_64_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA0_95_64_STATE_SHIFT 0 /*************************************************************************** *SHA0_127_96 - SHA Context0 State[127:96] ***************************************************************************/ /* SHARF_TOP :: SHA0_127_96 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA0_127_96_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA0_127_96_STATE_SHIFT 0 /*************************************************************************** *SHA0_159_128 - SHA Context0 State[159:128] ***************************************************************************/ /* SHARF_TOP :: SHA0_159_128 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA0_159_128_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA0_159_128_STATE_SHIFT 0 /*************************************************************************** *SHA0_191_160 - SHA Context0 State[191:160] ***************************************************************************/ /* SHARF_TOP :: SHA0_191_160 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA0_191_160_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA0_191_160_STATE_SHIFT 0 /*************************************************************************** *SHA0_223_192 - SHA Context0 State[223:192] ***************************************************************************/ /* SHARF_TOP :: SHA0_223_192 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA0_223_192_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA0_223_192_STATE_SHIFT 0 /*************************************************************************** *SHA0_255_224 - SHA Context0 State[255:224] ***************************************************************************/ /* SHARF_TOP :: SHA0_255_224 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA0_255_224_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA0_255_224_STATE_SHIFT 0 /*************************************************************************** *SHA1_31_00 - SHA Context1 State[31:0] ***************************************************************************/ /* SHARF_TOP :: SHA1_31_00 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA1_31_00_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA1_31_00_STATE_SHIFT 0 /*************************************************************************** *SHA1_63_32 - SHA Context1 State[63:32] ***************************************************************************/ /* SHARF_TOP :: SHA1_63_32 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA1_63_32_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA1_63_32_STATE_SHIFT 0 /*************************************************************************** *SHA1_95_64 - SHA Context1 State[95:64] ***************************************************************************/ /* SHARF_TOP :: SHA1_95_64 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA1_95_64_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA1_95_64_STATE_SHIFT 0 /*************************************************************************** *SHA1_127_96 - SHA Context1 State[127:96] ***************************************************************************/ /* SHARF_TOP :: SHA1_127_96 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA1_127_96_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA1_127_96_STATE_SHIFT 0 /*************************************************************************** *SHA1_159_128 - SHA Context1 State[159:128] ***************************************************************************/ /* SHARF_TOP :: SHA1_159_128 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA1_159_128_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA1_159_128_STATE_SHIFT 0 /*************************************************************************** *SHA1_191_160 - SHA Context1 State[191:160] ***************************************************************************/ /* SHARF_TOP :: SHA1_191_160 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA1_191_160_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA1_191_160_STATE_SHIFT 0 /*************************************************************************** *SHA1_223_192 - SHA Context1 State[223:192] ***************************************************************************/ /* SHARF_TOP :: SHA1_223_192 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA1_223_192_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA1_223_192_STATE_SHIFT 0 /*************************************************************************** *SHA1_255_224 - SHA Context1 State[255:224] ***************************************************************************/ /* SHARF_TOP :: SHA1_255_224 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA1_255_224_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA1_255_224_STATE_SHIFT 0 /*************************************************************************** *SHA2_31_00 - SHA Context2 State[31:0] ***************************************************************************/ /* SHARF_TOP :: SHA2_31_00 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA2_31_00_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA2_31_00_STATE_SHIFT 0 /*************************************************************************** *SHA2_63_32 - SHA Context2 State[63:32] ***************************************************************************/ /* SHARF_TOP :: SHA2_63_32 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA2_63_32_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA2_63_32_STATE_SHIFT 0 /*************************************************************************** *SHA2_95_64 - SHA Context2 State[95:64] ***************************************************************************/ /* SHARF_TOP :: SHA2_95_64 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA2_95_64_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA2_95_64_STATE_SHIFT 0 /*************************************************************************** *SHA2_127_96 - SHA Context2 State[127:96] ***************************************************************************/ /* SHARF_TOP :: SHA2_127_96 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA2_127_96_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA2_127_96_STATE_SHIFT 0 /*************************************************************************** *SHA2_159_128 - SHA Context2 State[159:128] ***************************************************************************/ /* SHARF_TOP :: SHA2_159_128 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA2_159_128_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA2_159_128_STATE_SHIFT 0 /*************************************************************************** *SHA2_191_160 - SHA Context2 State[191:160] ***************************************************************************/ /* SHARF_TOP :: SHA2_191_160 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA2_191_160_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA2_191_160_STATE_SHIFT 0 /*************************************************************************** *SHA2_223_192 - SHA Context2 State[223:192] ***************************************************************************/ /* SHARF_TOP :: SHA2_223_192 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA2_223_192_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA2_223_192_STATE_SHIFT 0 /*************************************************************************** *SHA2_255_224 - SHA Context2 State[255:224] ***************************************************************************/ /* SHARF_TOP :: SHA2_255_224 :: STATE [31:00] */ #define BCHP_SHARF_TOP_SHA2_255_224_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_SHA2_255_224_STATE_SHIFT 0 /*************************************************************************** *CMAC0_31_00 - CMAC Context0 State[31:0] ***************************************************************************/ /* SHARF_TOP :: CMAC0_31_00 :: STATE [31:00] */ #define BCHP_SHARF_TOP_CMAC0_31_00_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_CMAC0_31_00_STATE_SHIFT 0 /*************************************************************************** *CMAC0_63_32 - CMAC Context0 State[63:32] ***************************************************************************/ /* SHARF_TOP :: CMAC0_63_32 :: STATE [31:00] */ #define BCHP_SHARF_TOP_CMAC0_63_32_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_CMAC0_63_32_STATE_SHIFT 0 /*************************************************************************** *CMAC0_95_64 - CMAC Context0 State[95:64] ***************************************************************************/ /* SHARF_TOP :: CMAC0_95_64 :: STATE [31:00] */ #define BCHP_SHARF_TOP_CMAC0_95_64_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_CMAC0_95_64_STATE_SHIFT 0 /*************************************************************************** *CMAC0_127_96 - CMAC Context0 State[127:96] ***************************************************************************/ /* SHARF_TOP :: CMAC0_127_96 :: STATE [31:00] */ #define BCHP_SHARF_TOP_CMAC0_127_96_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_CMAC0_127_96_STATE_SHIFT 0 /*************************************************************************** *CMAC1_31_00 - CMAC Context1 State[31:0] ***************************************************************************/ /* SHARF_TOP :: CMAC1_31_00 :: STATE [31:00] */ #define BCHP_SHARF_TOP_CMAC1_31_00_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_CMAC1_31_00_STATE_SHIFT 0 /*************************************************************************** *CMAC1_63_32 - CMAC Context1 State[63:32] ***************************************************************************/ /* SHARF_TOP :: CMAC1_63_32 :: STATE [31:00] */ #define BCHP_SHARF_TOP_CMAC1_63_32_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_CMAC1_63_32_STATE_SHIFT 0 /*************************************************************************** *CMAC1_95_64 - CMAC Context1 State[95:64] ***************************************************************************/ /* SHARF_TOP :: CMAC1_95_64 :: STATE [31:00] */ #define BCHP_SHARF_TOP_CMAC1_95_64_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_CMAC1_95_64_STATE_SHIFT 0 /*************************************************************************** *CMAC1_127_96 - CMAC Context1 State[127:96] ***************************************************************************/ /* SHARF_TOP :: CMAC1_127_96 :: STATE [31:00] */ #define BCHP_SHARF_TOP_CMAC1_127_96_STATE_MASK 0xffffffff #define BCHP_SHARF_TOP_CMAC1_127_96_STATE_SHIFT 0 /*************************************************************************** *CTXT0_FAIL_ID - Context 0 Fail ID register ***************************************************************************/ /* SHARF_TOP :: CTXT0_FAIL_ID :: ID [31:00] */ #define BCHP_SHARF_TOP_CTXT0_FAIL_ID_ID_MASK 0xffffffff #define BCHP_SHARF_TOP_CTXT0_FAIL_ID_ID_SHIFT 0 /*************************************************************************** *CTXT1_FAIL_ID - Context 1 Fail ID register ***************************************************************************/ /* SHARF_TOP :: CTXT1_FAIL_ID :: ID [31:00] */ #define BCHP_SHARF_TOP_CTXT1_FAIL_ID_ID_MASK 0xffffffff #define BCHP_SHARF_TOP_CTXT1_FAIL_ID_ID_SHIFT 0 /*************************************************************************** *CTXT2_FAIL_ID - Context 2 Fail ID register (SHA only) ***************************************************************************/ /* SHARF_TOP :: CTXT2_FAIL_ID :: ID [31:00] */ #define BCHP_SHARF_TOP_CTXT2_FAIL_ID_ID_MASK 0xffffffff #define BCHP_SHARF_TOP_CTXT2_FAIL_ID_ID_SHIFT 0 /*************************************************************************** *ERR_STATUS - SHARF Error Status ***************************************************************************/ /* SHARF_TOP :: ERR_STATUS :: reserved0 [31:08] */ #define BCHP_SHARF_TOP_ERR_STATUS_reserved0_MASK 0xffffff00 #define BCHP_SHARF_TOP_ERR_STATUS_reserved0_SHIFT 8 /* SHARF_TOP :: ERR_STATUS :: FRAME_ERR1 [07:07] */ #define BCHP_SHARF_TOP_ERR_STATUS_FRAME_ERR1_MASK 0x00000080 #define BCHP_SHARF_TOP_ERR_STATUS_FRAME_ERR1_SHIFT 7 /* SHARF_TOP :: ERR_STATUS :: FRAME_ERR0 [06:06] */ #define BCHP_SHARF_TOP_ERR_STATUS_FRAME_ERR0_MASK 0x00000040 #define BCHP_SHARF_TOP_ERR_STATUS_FRAME_ERR0_SHIFT 6 /* SHARF_TOP :: ERR_STATUS :: AES_ALIGN_ERR1 [05:05] */ #define BCHP_SHARF_TOP_ERR_STATUS_AES_ALIGN_ERR1_MASK 0x00000020 #define BCHP_SHARF_TOP_ERR_STATUS_AES_ALIGN_ERR1_SHIFT 5 /* SHARF_TOP :: ERR_STATUS :: AES_ALIGN_ERR0 [04:04] */ #define BCHP_SHARF_TOP_ERR_STATUS_AES_ALIGN_ERR0_MASK 0x00000010 #define BCHP_SHARF_TOP_ERR_STATUS_AES_ALIGN_ERR0_SHIFT 4 /* SHARF_TOP :: ERR_STATUS :: SIZE_ERR1 [03:03] */ #define BCHP_SHARF_TOP_ERR_STATUS_SIZE_ERR1_MASK 0x00000008 #define BCHP_SHARF_TOP_ERR_STATUS_SIZE_ERR1_SHIFT 3 /* SHARF_TOP :: ERR_STATUS :: SIZE_ERR0 [02:02] */ #define BCHP_SHARF_TOP_ERR_STATUS_SIZE_ERR0_MASK 0x00000004 #define BCHP_SHARF_TOP_ERR_STATUS_SIZE_ERR0_SHIFT 2 /* SHARF_TOP :: ERR_STATUS :: AES_BSP_KEY_ERR1 [01:01] */ #define BCHP_SHARF_TOP_ERR_STATUS_AES_BSP_KEY_ERR1_MASK 0x00000002 #define BCHP_SHARF_TOP_ERR_STATUS_AES_BSP_KEY_ERR1_SHIFT 1 /* SHARF_TOP :: ERR_STATUS :: AES_BSP_KEY_ERR0 [00:00] */ #define BCHP_SHARF_TOP_ERR_STATUS_AES_BSP_KEY_ERR0_MASK 0x00000001 #define BCHP_SHARF_TOP_ERR_STATUS_AES_BSP_KEY_ERR0_SHIFT 0 #endif /* #ifndef BCHP_SHARF_TOP_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000014700000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_common.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_common0000644000175000017500000012646711610313111031046 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_common.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:58p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:41:59 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_common.h $ * * Hydra_Software_Devel/1 7/17/09 7:58p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_COMMON_H__ #define BCHP_COMMON_H__ /*************************************************************************** *BCM70015_A0 ***************************************************************************/ #define BCHP_PHYSICAL_OFFSET 0x10000000 #define BCHP_REGISTER_START 0x00070000 /* CLK is first */ #define BCHP_REGISTER_END 0x01801250 /* DDR23_PHY_BYTE_LANE_0 is last */ #define BCHP_REGISTER_SIZE 0x005e4494 /* Number of registers */ /**************************************************************************** * Core instance register start address. ***************************************************************************/ #define BCHP_CLK_REG_START 0x00070000 #define BCHP_CLK_REG_END 0x00070304 #define BCHP_CLK_GR_REG_START 0x00072000 #define BCHP_CLK_GR_REG_END 0x0007200c #define BCHP_ARMCR4_BRIDGE_REG_START 0x000e0000 #define BCHP_ARMCR4_BRIDGE_REG_END 0x000e0098 #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_START 0x000e1000 #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_END 0x000e1004 #define BCHP_TRB_TOP_REG_START 0x000f0000 #define BCHP_TRB_TOP_REG_END 0x000f0008 #define BCHP_WRAP_MISC_GR_BRIDGE_REG_START 0x000f1000 #define BCHP_WRAP_MISC_GR_BRIDGE_REG_END 0x000f100c #define BCHP_WRAP_MISC_INTR2_REG_START 0x000f2000 #define BCHP_WRAP_MISC_INTR2_REG_END 0x000f202c #define BCHP_ARM_UART_REG_START 0x000f3000 #define BCHP_ARM_UART_REG_END 0x000f3008 #define BCHP_SHARF_TOP_REG_START 0x000f4000 #define BCHP_SHARF_TOP_REG_END 0x000f4094 #define BCHP_SHARF_MEM_DMA0_REG_START 0x000f4100 #define BCHP_SHARF_MEM_DMA0_REG_END 0x000f411c #define BCHP_MEM_DMA_REG_START 0x000f5000 #define BCHP_MEM_DMA_REG_END 0x000f5024 #define BCHP_SCRUB_CTRL_REG_START 0x000f6000 #define BCHP_SCRUB_CTRL_REG_END 0x000f6078 #define BCHP_MEM_DMA_SECURE_REG_START 0x000fc000 #define BCHP_MEM_DMA_SECURE_REG_END 0x000fc00c #define BCHP_MMSCRAM_REG_START 0x000fd000 #define BCHP_MMSCRAM_REG_END 0x000feffc #define BCHP_TRIPLE_SEC_REG_START 0x000ff000 #define BCHP_TRIPLE_SEC_REG_END 0x000ff4fc #define BCHP_WRAP_MISC_SECURE_INTR2_REG_START 0x000ff500 #define BCHP_WRAP_MISC_SECURE_INTR2_REG_END 0x000ff52c #define BCHP_XPT_BUS_IF_REG_START 0x00200000 #define BCHP_XPT_BUS_IF_REG_END 0x00200074 #define BCHP_XPT_XMEMIF_REG_START 0x00202000 #define BCHP_XPT_XMEMIF_REG_END 0x00202064 #define BCHP_XPT_FE_REG_START 0x00208000 #define BCHP_XPT_FE_REG_END 0x00208dfc #define BCHP_XPT_PB0_REG_START 0x0020b000 #define BCHP_XPT_PB0_REG_END 0x0020b048 #define BCHP_XPT_PB1_REG_START 0x0020b080 #define BCHP_XPT_PB1_REG_END 0x0020b0c8 #define BCHP_XPT_PB2_REG_START 0x0020b100 #define BCHP_XPT_PB2_REG_END 0x0020b148 #define BCHP_XPT_RAVE_REG_START 0x00210000 #define BCHP_XPT_RAVE_REG_END 0x0021a50c #define BCHP_XPT_XPU_REG_START 0x00220000 #define BCHP_XPT_XPU_REG_END 0x002227fc #define BCHP_XPT_PCROFFSET_REG_START 0x00227000 #define BCHP_XPT_PCROFFSET_REG_END 0x00227ffc #define BCHP_XPT_GR_REG_START 0x00230000 #define BCHP_XPT_GR_REG_END 0x0023000c #define BCHP_SUN_GISB_ARB_REG_START 0x00400000 #define BCHP_SUN_GISB_ARB_REG_END 0x004000d8 #define BCHP_SUN_RGR_REG_START 0x00400800 #define BCHP_SUN_RGR_REG_END 0x00400810 #define BCHP_SUN_RG_REG_START 0x00401000 #define BCHP_SUN_RG_REG_END 0x0040100c #define BCHP_SUN_L2_REG_START 0x00401800 #define BCHP_SUN_L2_REG_END 0x0040182c #define BCHP_PM_L2_REG_START 0x00401c00 #define BCHP_PM_L2_REG_END 0x00401c2c #define BCHP_SUN_TOP_CTRL_REG_START 0x00404000 #define BCHP_SUN_TOP_CTRL_REG_END 0x00404608 #define BCHP_GIO_REG_START 0x00406000 #define BCHP_GIO_REG_END 0x0040601c #define BCHP_IRQ0_REG_START 0x00406080 #define BCHP_IRQ0_REG_END 0x00406084 #define BCHP_TIMER_REG_START 0x004060c0 #define BCHP_TIMER_REG_END 0x004060fc #define BCHP_IRQ1_REG_START 0x00406788 #define BCHP_IRQ1_REG_END 0x0040678c #define BCHP_WAKEUP_CTRL2_REG_START 0x00406c00 #define BCHP_WAKEUP_CTRL2_REG_END 0x00406c14 #define BCHP_PRI_CLIENT_REGS_REG_START 0x0040c000 #define BCHP_PRI_CLIENT_REGS_REG_END 0x0040c27c #define BCHP_PRI_CRIT_L2_REGS_1_REG_START 0x0040c400 #define BCHP_PRI_CRIT_L2_REGS_1_REG_END 0x0040c42c #define BCHP_PRI_CRIT_L2_REGS_2_REG_START 0x0040c440 #define BCHP_PRI_CRIT_L2_REGS_2_REG_END 0x0040c46c #define BCHP_PRI_CRIT_L2_REGS_3_REG_START 0x0040c480 #define BCHP_PRI_CRIT_L2_REGS_3_REG_END 0x0040c4ac #define BCHP_PRI_RTS_L2_REGS_1_REG_START 0x0040c4c0 #define BCHP_PRI_RTS_L2_REGS_1_REG_END 0x0040c4ec #define BCHP_PRI_RTS_L2_REGS_2_REG_START 0x0040c500 #define BCHP_PRI_RTS_L2_REGS_2_REG_END 0x0040c52c #define BCHP_PRI_RTS_L2_REGS_3_REG_START 0x0040c540 #define BCHP_PRI_RTS_L2_REGS_3_REG_END 0x0040c56c #define BCHP_PRI_ARB_TRACE_REGS_REG_START 0x0040c600 #define BCHP_PRI_ARB_TRACE_REGS_REG_END 0x0040c7ec #define BCHP_PRI_ARB_MSA_REGS_REG_START 0x0040c800 #define BCHP_PRI_ARB_MSA_REGS_REG_END 0x0040ca0c #define BCHP_PRI_ARB_CONTROL_REGS_REG_START 0x0040cb00 #define BCHP_PRI_ARB_CONTROL_REGS_REG_END 0x0040cb30 #define BCHP_PRI_ARB_ARCH_REGS_REG_START 0x0040cc00 #define BCHP_PRI_ARB_ARCH_REGS_REG_END 0x0040cdac #define BCHP_PRI_ARB_MIPS_L2_REGS_REG_START 0x0040ce00 #define BCHP_PRI_ARB_MIPS_L2_REGS_REG_END 0x0040ce2c #define BCHP_PRI_ARB_ARC_L1_REGS_REG_START 0x0040cf00 #define BCHP_PRI_ARB_ARC_L1_REGS_REG_END 0x0040cf1c #define BCHP_SENTINEL_REG_START 0x00410000 #define BCHP_SENTINEL_REG_END 0x00413ffc #define BCHP_SUN_GISB_ARB_SEC_REG_START 0x00460000 #define BCHP_SUN_GISB_ARB_SEC_REG_END 0x00460064 #define BCHP_PRI_ARB_WRCH_REGS_REG_START 0x00461000 #define BCHP_PRI_ARB_WRCH_REGS_REG_END 0x004610fc #define BCHP_PRI_ARB_STARCH_REGS_REG_START 0x00461200 #define BCHP_PRI_ARB_STARCH_REGS_REG_END 0x004613c0 #define BCHP_PRI_ARB_SARCH_REGS_REG_START 0x00461400 #define BCHP_PRI_ARB_SARCH_REGS_REG_END 0x0046159c #define BCHP_PCIE_CFG_REG_START 0x00500000 #define BCHP_PCIE_CFG_REG_END 0x0050018c #define BCHP_PCIE_TL_REG_START 0x00500400 #define BCHP_PCIE_TL_REG_END 0x0050046c #define BCHP_PCIE_DLL_REG_START 0x00500500 #define BCHP_PCIE_DLL_REG_END 0x00500554 #define BCHP_PCIE_PHY_REG_START 0x00500600 #define BCHP_PCIE_PHY_REG_END 0x0050063c #define BCHP_INTR_REG_START 0x00500700 #define BCHP_INTR_REG_END 0x00500734 #define BCHP_L1_INTR_REG_START 0x00500740 #define BCHP_L1_INTR_REG_END 0x0050075c #define BCHP_MDIO_REG_START 0x00500760 #define BCHP_MDIO_REG_END 0x00500768 #define BCHP_TGT_RGR_BRIDGE_REG_START 0x00500780 #define BCHP_TGT_RGR_BRIDGE_REG_END 0x00500790 #define BCHP_I2C_REG_START 0x00501000 #define BCHP_I2C_REG_END 0x00501054 #define BCHP_I2C_GR_BRIDGE_REG_START 0x005013e0 #define BCHP_I2C_GR_BRIDGE_REG_END 0x005013ec #define BCHP_MISC1_REG_START 0x00502000 #define BCHP_MISC1_REG_END 0x005020d0 #define BCHP_MISC2_REG_START 0x00502100 #define BCHP_MISC2_REG_END 0x00502120 #define BCHP_MISC3_REG_START 0x00502200 #define BCHP_MISC3_REG_END 0x0050222c #define BCHP_MISC_PERST_REG_START 0x00502280 #define BCHP_MISC_PERST_REG_END 0x0050229c #define BCHP_MISC_GR_BRIDGE_REG_START 0x005023e0 #define BCHP_MISC_GR_BRIDGE_REG_END 0x005023ec #define BCHP_CCE_RGR_BRIDGE_REG_START 0x005033e0 #define BCHP_CCE_RGR_BRIDGE_REG_END 0x005033f0 #define BCHP_BOP_AES_REG_START 0x00510000 #define BCHP_BOP_AES_REG_END 0x00510034 #define BCHP_BOP_GR_BRIDGE_REG_START 0x00511000 #define BCHP_BOP_GR_BRIDGE_REG_END 0x0051100c #define BCHP_MFD_REG_START 0x00540000 #define BCHP_MFD_REG_END 0x005400fc #define BCHP_DNR_REG_START 0x00540400 #define BCHP_DNR_REG_END 0x005404a0 #define BCHP_SCL_HD_REG_START 0x00540800 #define BCHP_SCL_HD_REG_END 0x00540bfc #define BCHP_CSC_REG_START 0x00541000 #define BCHP_CSC_REG_END 0x0054103c #define BCHP_BVNT_INTR2_REG_START 0x00541200 #define BCHP_BVNT_INTR2_REG_END 0x0054122c #define BCHP_TMISC_REG_START 0x00541400 #define BCHP_TMISC_REG_END 0x0054143c #define BCHP_BVNT_GR_BRIDGE_REG_START 0x00541800 #define BCHP_BVNT_GR_BRIDGE_REG_END 0x0054180c #define BCHP_DECODE_MAIN_0_REG_START 0x00800100 #define BCHP_DECODE_MAIN_0_REG_END 0x008001fc #define BCHP_DECODE_MCOM_0_REG_START 0x00800300 #define BCHP_DECODE_MCOM_0_REG_END 0x0080031c #define BCHP_DECODE_SPRE_0_REG_START 0x00800320 #define BCHP_DECODE_SPRE_0_REG_END 0x0080033c #define BCHP_DECODE_WPRD_0_REG_START 0x00800340 #define BCHP_DECODE_WPRD_0_REG_END 0x0080035c #define BCHP_DECODE_DQNT_0_REG_START 0x00800400 #define BCHP_DECODE_DQNT_0_REG_END 0x0080045c #define BCHP_DECODE_DQNT_8X8_0_REG_START 0x00800500 #define BCHP_DECODE_DQNT_8X8_0_REG_END 0x0080057c #define BCHP_DECODE_XFRM_0_REG_START 0x00800700 #define BCHP_DECODE_XFRM_0_REG_END 0x0080071c #define BCHP_DECODE_DBLK_0_REG_START 0x00800720 #define BCHP_DECODE_DBLK_0_REG_END 0x0080073c #define BCHP_DECODE_MB_0_REG_START 0x00800740 #define BCHP_DECODE_MB_0_REG_END 0x0080075c #define BCHP_REG_CABAC2BINS_0_REG_START 0x00800b00 #define BCHP_REG_CABAC2BINS_0_REG_END 0x00800bfc #define BCHP_DECODE_SINT_0_REG_START 0x00800c00 #define BCHP_DECODE_SINT_0_REG_END 0x00800dfc #define BCHP_DECODE_RVC_0_REG_START 0x00800e00 #define BCHP_DECODE_RVC_0_REG_END 0x00800efc #define BCHP_DECODE_CPUREGS_0_REG_START 0x00800f00 #define BCHP_DECODE_CPUREGS_0_REG_END 0x00800f7c #define BCHP_DECODE_CPUREGS2_0_REG_START 0x00800f80 #define BCHP_DECODE_CPUREGS2_0_REG_END 0x00800ffc #define BCHP_DECODE_CPUDMA_0_REG_START 0x00801800 #define BCHP_DECODE_CPUDMA_0_REG_END 0x008018fc #define BCHP_DECODE_DMAMEM_0_REG_START 0x00801a00 #define BCHP_DECODE_DMAMEM_0_REG_END 0x008021fc #define BCHP_REG_CABAC2BINS2_0_REG_START 0x00802400 #define BCHP_REG_CABAC2BINS2_0_REG_END 0x008027fc #define BCHP_DECODE_WPTBL_0_REG_START 0x00803000 #define BCHP_DECODE_WPTBL_0_REG_END 0x008031fc #define BCHP_DECODE_SINT_OLOOP_0_REG_START 0x0080cc00 #define BCHP_DECODE_SINT_OLOOP_0_REG_END 0x0080ccfc #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_START 0x00841000 #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_END 0x0084107c #define BCHP_DECODE_CPUCORE_0_REG_START 0x00844000 #define BCHP_DECODE_CPUCORE_0_REG_END 0x00844ffc #define BCHP_DECODE_CPUAUX_0_REG_START 0x00845000 #define BCHP_DECODE_CPUAUX_0_REG_END 0x00845ffc #define BCHP_DECODE_CPUIMEM_0_REG_START 0x00846000 #define BCHP_DECODE_CPUIMEM_0_REG_END 0x00847ffc #define BCHP_DECODE_CPUDMEM_0_REG_START 0x00848000 #define BCHP_DECODE_CPUDMEM_0_REG_END 0x0084fffc #define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_START 0x00851000 #define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_END 0x0085107c #define BCHP_DECODE_CPUDMA2_0_REG_START 0x00851800 #define BCHP_DECODE_CPUDMA2_0_REG_END 0x008518fc #define BCHP_DECODE_DMAMEM2_0_REG_START 0x00851a00 #define BCHP_DECODE_DMAMEM2_0_REG_END 0x008521fc #define BCHP_DECODE_CPUCORE2_0_REG_START 0x00854000 #define BCHP_DECODE_CPUCORE2_0_REG_END 0x00854ffc #define BCHP_DECODE_CPUAUX2_0_REG_START 0x00855000 #define BCHP_DECODE_CPUAUX2_0_REG_END 0x00855ffc #define BCHP_DECODE_CPUIMEM2_0_REG_START 0x00856000 #define BCHP_DECODE_CPUIMEM2_0_REG_END 0x00857ffc #define BCHP_DECODE_CPUDMEM2_0_REG_START 0x00858000 #define BCHP_DECODE_CPUDMEM2_0_REG_END 0x0085fffc #define BCHP_DECODE_IP_SHIM_0_REG_START 0x00860000 #define BCHP_DECODE_IP_SHIM_0_REG_END 0x0086007c #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_START 0x00861000 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_END 0x0086103c #define BCHP_AVD_CACHE_0_REG_START 0x00862000 #define BCHP_AVD_CACHE_0_REG_END 0x0086203c #define BCHP_AVD_INTR2_0_REG_START 0x00900000 #define BCHP_AVD_INTR2_0_REG_END 0x0090002c #define BCHP_AVD_GR_0_REG_START 0x00900400 #define BCHP_AVD_GR_0_REG_END 0x0090040c #define BCHP_VICH_0_REG_START 0x00b00000 #define BCHP_VICH_0_REG_END 0x00b0004c #define BCHP_DDR23_CTL_REGS_0_REG_START 0x01800000 #define BCHP_DDR23_CTL_REGS_0_REG_END 0x018001fc #define BCHP_DDR23_PHY_CONTROL_REGS_REG_START 0x01801000 #define BCHP_DDR23_PHY_CONTROL_REGS_REG_END 0x01801044 #define BCHP_DDR23_PHY_BYTE_LANE_1_REG_START 0x01801100 #define BCHP_DDR23_PHY_BYTE_LANE_1_REG_END 0x0180114c #define BCHP_DDR23_PHY_BYTE_LANE_0_REG_START 0x01801200 #define BCHP_DDR23_PHY_BYTE_LANE_0_REG_END 0x0180124c /*************************************************************************** *BVN_MFD ***************************************************************************/ /*************************************************************************** *DRAM_DATA_STRUCTURE - DRAM Data Structure ***************************************************************************/ /* BVN_MFD :: DRAM_DATA_STRUCTURE :: DRAM_DATA_STRUCTURE [31:00] */ #define BCHP_BVN_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_MASK 0xffffffff #define BCHP_BVN_MFD_DRAM_DATA_STRUCTURE_DRAM_DATA_STRUCTURE_SHIFT 0 /*************************************************************************** *MEM_DMA ***************************************************************************/ /*************************************************************************** *DESC_WORD0 - MEM DMA Descriptor Word 0 ***************************************************************************/ /* MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */ #define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_MASK 0xffffffff #define BCHP_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT 0 /*************************************************************************** *DESC_WORD1 - MEM DMA Descriptor Word 1 ***************************************************************************/ /* MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */ #define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK 0xffffffff #define BCHP_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT 0 /*************************************************************************** *DESC_WORD2 - MEM DMA Descriptor Word 2 ***************************************************************************/ /* MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */ #define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK 0x80000000 #define BCHP_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT 31 /* MEM_DMA :: DESC_WORD2 :: LAST [30:30] */ #define BCHP_MEM_DMA_DESC_WORD2_LAST_MASK 0x40000000 #define BCHP_MEM_DMA_DESC_WORD2_LAST_SHIFT 30 /* MEM_DMA :: DESC_WORD2 :: AUTO_APPEND [29:29] */ #define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_MASK 0x20000000 #define BCHP_MEM_DMA_DESC_WORD2_AUTO_APPEND_SHIFT 29 /* MEM_DMA :: DESC_WORD2 :: reserved0 [28:25] */ #define BCHP_MEM_DMA_DESC_WORD2_reserved0_MASK 0x1e000000 #define BCHP_MEM_DMA_DESC_WORD2_reserved0_SHIFT 25 /* MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [24:00] */ #define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK 0x01ffffff #define BCHP_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT 0 /*************************************************************************** *DESC_WORD3 - MEM DMA Descriptor Word 3 ***************************************************************************/ /* MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */ #define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK 0xffffffe0 #define BCHP_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT 5 /* MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */ #define BCHP_MEM_DMA_DESC_WORD3_reserved0_MASK 0x00000018 #define BCHP_MEM_DMA_DESC_WORD3_reserved0_SHIFT 3 /* MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */ #define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK 0x00000004 #define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT 2 #define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN 0 #define BCHP_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN 1 /* MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */ #define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK 0x00000003 #define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT 0 #define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0 #define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1 #define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2 #define BCHP_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved 3 /*************************************************************************** *DESC_WORD4 - MEM DMA Descriptor Word 4 ***************************************************************************/ /* MEM_DMA :: DESC_WORD4 :: reserved0 [31:16] */ #define BCHP_MEM_DMA_DESC_WORD4_reserved0_MASK 0xffff0000 #define BCHP_MEM_DMA_DESC_WORD4_reserved0_SHIFT 16 /* MEM_DMA :: DESC_WORD4 :: SCRAM_CTRL_RSV [15:14] */ #define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_MASK 0x0000c000 #define BCHP_MEM_DMA_DESC_WORD4_SCRAM_CTRL_RSV_SHIFT 14 /* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */ #define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK 0x00002000 #define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT 13 /* MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */ #define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK 0x00001000 #define BCHP_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT 12 /* MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */ #define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK 0x00000800 #define BCHP_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT 11 /* MEM_DMA :: DESC_WORD4 :: ENC_DEC_INIT [10:10] */ #define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_MASK 0x00000400 #define BCHP_MEM_DMA_DESC_WORD4_ENC_DEC_INIT_SHIFT 10 /* MEM_DMA :: DESC_WORD4 :: MODE_SEL [09:08] */ #define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_MASK 0x00000300 #define BCHP_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT 8 /* MEM_DMA :: DESC_WORD4 :: KEY_SELECT [07:00] */ #define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_MASK 0x000000ff #define BCHP_MEM_DMA_DESC_WORD4_KEY_SELECT_SHIFT 0 /*************************************************************************** *DESC_WORD5 - MEM DMA Descriptor Word 5 ***************************************************************************/ /* MEM_DMA :: DESC_WORD5 :: reserved0 [31:00] */ #define BCHP_MEM_DMA_DESC_WORD5_reserved0_MASK 0xffffffff #define BCHP_MEM_DMA_DESC_WORD5_reserved0_SHIFT 0 /*************************************************************************** *DESC_WORD6 - MEM DMA Descriptor Word 6 ***************************************************************************/ /* MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */ #define BCHP_MEM_DMA_DESC_WORD6_reserved0_MASK 0xffffffff #define BCHP_MEM_DMA_DESC_WORD6_reserved0_SHIFT 0 /*************************************************************************** *DESC_WORD7 - MEM DMA Descriptor Word 7 ***************************************************************************/ /* MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */ #define BCHP_MEM_DMA_DESC_WORD7_reserved0_MASK 0xffffffff #define BCHP_MEM_DMA_DESC_WORD7_reserved0_SHIFT 0 /*************************************************************************** *SHARF_MEM_DMA ***************************************************************************/ /*************************************************************************** *DESC_WORD0 - SHARF DMA Descriptor Word 0 ***************************************************************************/ /* SHARF_MEM_DMA :: DESC_WORD0 :: READ_ADDR [31:00] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD0_READ_ADDR_MASK 0xffffffff #define BCHP_SHARF_MEM_DMA_DESC_WORD0_READ_ADDR_SHIFT 0 /*************************************************************************** *DESC_WORD1 - SHARF DMA Descriptor Word 1 ***************************************************************************/ /* SHARF_MEM_DMA :: DESC_WORD1 :: WRITE_ADDR [31:00] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD1_WRITE_ADDR_MASK 0xffffffff #define BCHP_SHARF_MEM_DMA_DESC_WORD1_WRITE_ADDR_SHIFT 0 /*************************************************************************** *DESC_WORD2 - SHARF DMA Descriptor Word 2 ***************************************************************************/ /* SHARF_MEM_DMA :: DESC_WORD2 :: INTR_ENABLE [31:31] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD2_INTR_ENABLE_MASK 0x80000000 #define BCHP_SHARF_MEM_DMA_DESC_WORD2_INTR_ENABLE_SHIFT 31 /* SHARF_MEM_DMA :: DESC_WORD2 :: LAST [30:30] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD2_LAST_MASK 0x40000000 #define BCHP_SHARF_MEM_DMA_DESC_WORD2_LAST_SHIFT 30 /* SHARF_MEM_DMA :: DESC_WORD2 :: reserved0 [29:27] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD2_reserved0_MASK 0x38000000 #define BCHP_SHARF_MEM_DMA_DESC_WORD2_reserved0_SHIFT 27 /* SHARF_MEM_DMA :: DESC_WORD2 :: TRANSFER_SIZE [26:00] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_MASK 0x07ffffff #define BCHP_SHARF_MEM_DMA_DESC_WORD2_TRANSFER_SIZE_SHIFT 0 /*************************************************************************** *DESC_WORD3 - SHARF DMA Descriptor Word 3 ***************************************************************************/ /* SHARF_MEM_DMA :: DESC_WORD3 :: NEXT_DESC_ADDR [31:05] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_MASK 0xffffffe0 #define BCHP_SHARF_MEM_DMA_DESC_WORD3_NEXT_DESC_ADDR_SHIFT 5 /* SHARF_MEM_DMA :: DESC_WORD3 :: reserved0 [04:03] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD3_reserved0_MASK 0x00000018 #define BCHP_SHARF_MEM_DMA_DESC_WORD3_reserved0_SHIFT 3 /* SHARF_MEM_DMA :: DESC_WORD3 :: READ_ENDIAN_MODE [02:02] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_MASK 0x00000004 #define BCHP_SHARF_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_SHIFT 2 #define BCHP_SHARF_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_BIG_ENDIAN 0 #define BCHP_SHARF_MEM_DMA_DESC_WORD3_READ_ENDIAN_MODE_LITTLE_ENDIAN 1 /* SHARF_MEM_DMA :: DESC_WORD3 :: WRITE_ENDIAN_XLATE_MODE [01:00] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_MASK 0x00000003 #define BCHP_SHARF_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_SHIFT 0 #define BCHP_SHARF_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_WORD_ALIGNED 0 #define BCHP_SHARF_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_HALF_WORD_ALIGNED 1 #define BCHP_SHARF_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_BYTE_ALIGNED 2 #define BCHP_SHARF_MEM_DMA_DESC_WORD3_WRITE_ENDIAN_XLATE_MODE_reserved 3 /*************************************************************************** *DESC_WORD4 - SHARF DMA Descriptor Word 4 ***************************************************************************/ /* SHARF_MEM_DMA :: DESC_WORD4 :: reserved0 [31:20] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_reserved0_MASK 0xfff00000 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_reserved0_SHIFT 20 /* SHARF_MEM_DMA :: DESC_WORD4 :: KEY_UNWRAP_MODE [19:18] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_KEY_UNWRAP_MODE_MASK 0x000c0000 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_KEY_UNWRAP_MODE_SHIFT 18 /* SHARF_MEM_DMA :: DESC_WORD4 :: CONTEXT_NUM [17:16] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_CONTEXT_NUM_MASK 0x00030000 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_CONTEXT_NUM_SHIFT 16 /* SHARF_MEM_DMA :: DESC_WORD4 :: SECURE_FAIL_INTR_ENABLE [15:15] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_SECURE_FAIL_INTR_ENABLE_MASK 0x00008000 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_SECURE_FAIL_INTR_ENABLE_SHIFT 15 /* SHARF_MEM_DMA :: DESC_WORD4 :: FAIL_INTR_ENABLE [14:14] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_FAIL_INTR_ENABLE_MASK 0x00004000 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_FAIL_INTR_ENABLE_SHIFT 14 /* SHARF_MEM_DMA :: DESC_WORD4 :: SG_SCRAM_END [13:13] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_SG_SCRAM_END_MASK 0x00002000 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_SG_SCRAM_END_SHIFT 13 /* SHARF_MEM_DMA :: DESC_WORD4 :: SG_SCRAM_START [12:12] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_SG_SCRAM_START_MASK 0x00001000 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_SG_SCRAM_START_SHIFT 12 /* SHARF_MEM_DMA :: DESC_WORD4 :: SG_ENABLE [11:11] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_SG_ENABLE_MASK 0x00000800 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_SG_ENABLE_SHIFT 11 /* SHARF_MEM_DMA :: DESC_WORD4 :: CMP_8_LSBYTES [10:10] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_CMP_8_LSBYTES_MASK 0x00000400 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_CMP_8_LSBYTES_SHIFT 10 /* SHARF_MEM_DMA :: DESC_WORD4 :: reserved1 [09:08] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_reserved1_MASK 0x00000300 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_reserved1_SHIFT 8 /* SHARF_MEM_DMA :: DESC_WORD4 :: MODE_SEL [07:04] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_MODE_SEL_MASK 0x000000f0 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_MODE_SEL_SHIFT 4 /* SHARF_MEM_DMA :: DESC_WORD4 :: USE_BSP_KEY [03:03] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_USE_BSP_KEY_MASK 0x00000008 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_USE_BSP_KEY_SHIFT 3 /* SHARF_MEM_DMA :: DESC_WORD4 :: reserved2 [02:02] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_reserved2_MASK 0x00000004 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_reserved2_SHIFT 2 /* SHARF_MEM_DMA :: DESC_WORD4 :: DIGEST_PRESENT [01:01] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_DIGEST_PRESENT_MASK 0x00000002 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_DIGEST_PRESENT_SHIFT 1 /* SHARF_MEM_DMA :: DESC_WORD4 :: KEY_PRESENT [00:00] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD4_KEY_PRESENT_MASK 0x00000001 #define BCHP_SHARF_MEM_DMA_DESC_WORD4_KEY_PRESENT_SHIFT 0 /*************************************************************************** *DESC_WORD5 - SHARF DMA Descriptor Word 5 ***************************************************************************/ /* SHARF_MEM_DMA :: DESC_WORD5 :: INDEX [31:00] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD5_INDEX_MASK 0xffffffff #define BCHP_SHARF_MEM_DMA_DESC_WORD5_INDEX_SHIFT 0 /*************************************************************************** *DESC_WORD6 - SHARF DMA Descriptor Word 6 ***************************************************************************/ /* SHARF_MEM_DMA :: DESC_WORD6 :: reserved0 [31:00] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD6_reserved0_MASK 0xffffffff #define BCHP_SHARF_MEM_DMA_DESC_WORD6_reserved0_SHIFT 0 /*************************************************************************** *DESC_WORD7 - SHARF DMA Descriptor Word 7 ***************************************************************************/ /* SHARF_MEM_DMA :: DESC_WORD7 :: reserved0 [31:00] */ #define BCHP_SHARF_MEM_DMA_DESC_WORD7_reserved0_MASK 0xffffffff #define BCHP_SHARF_MEM_DMA_DESC_WORD7_reserved0_SHIFT 0 /*************************************************************************** *XPT_PB ***************************************************************************/ /*************************************************************************** *DESCRIPTOR_ABSTRACT - Playback Linked-List Descriptor Abstract ***************************************************************************/ /* XPT_PB :: DESCRIPTOR_ABSTRACT :: DESCRIPTOR_FORMAT [31:00] */ #define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_MASK 0xffffffff #define BCHP_XPT_PB_DESCRIPTOR_ABSTRACT_DESCRIPTOR_FORMAT_SHIFT 0 /*************************************************************************** *DESC_0 - Playback Linked-List Descriptor Word 0 ***************************************************************************/ /* XPT_PB :: DESC_0 :: PB_BUFFER_START_ADDR [31:00] */ #define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_MASK 0xffffffff #define BCHP_XPT_PB_DESC_0_PB_BUFFER_START_ADDR_SHIFT 0 /*************************************************************************** *DESC_1 - Playback Linked-List Descriptor Word 1 ***************************************************************************/ /* XPT_PB :: DESC_1 :: PB_BUFFER_LENGTH [31:00] */ #define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_MASK 0xffffffff #define BCHP_XPT_PB_DESC_1_PB_BUFFER_LENGTH_SHIFT 0 /*************************************************************************** *DESC_2 - Playback Linked-List Descriptor Word 2 ***************************************************************************/ /* XPT_PB :: DESC_2 :: PB_INTERRUPT_ENABLE [31:31] */ #define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_MASK 0x80000000 #define BCHP_XPT_PB_DESC_2_PB_INTERRUPT_ENABLE_SHIFT 31 /* XPT_PB :: DESC_2 :: PB_FORCE_RESYNC [30:30] */ #define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_MASK 0x40000000 #define BCHP_XPT_PB_DESC_2_PB_FORCE_RESYNC_SHIFT 30 /* XPT_PB :: DESC_2 :: reserved0 [29:28] */ #define BCHP_XPT_PB_DESC_2_reserved0_MASK 0x30000000 #define BCHP_XPT_PB_DESC_2_reserved0_SHIFT 28 /* XPT_PB :: DESC_2 :: PB_DESC_TAG_ID [27:24] */ #define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_MASK 0x0f000000 #define BCHP_XPT_PB_DESC_2_PB_DESC_TAG_ID_SHIFT 24 /* XPT_PB :: DESC_2 :: reserved1 [23:00] */ #define BCHP_XPT_PB_DESC_2_reserved1_MASK 0x00ffffff #define BCHP_XPT_PB_DESC_2_reserved1_SHIFT 0 /*************************************************************************** *DESC_3 - Playback Linked-List Descriptor Word 3 ***************************************************************************/ /* XPT_PB :: DESC_3 :: PB_NEXT_DESC_ADDR [31:04] */ #define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_MASK 0xfffffff0 #define BCHP_XPT_PB_DESC_3_PB_NEXT_DESC_ADDR_SHIFT 4 /* XPT_PB :: DESC_3 :: reserved0 [03:01] */ #define BCHP_XPT_PB_DESC_3_reserved0_MASK 0x0000000e #define BCHP_XPT_PB_DESC_3_reserved0_SHIFT 1 /* XPT_PB :: DESC_3 :: PB_LAST_DESC_IND [00:00] */ #define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_MASK 0x00000001 #define BCHP_XPT_PB_DESC_3_PB_LAST_DESC_IND_SHIFT 0 /*************************************************************************** *XPT_RAVE ***************************************************************************/ /*************************************************************************** *NOTEA_CONTEXT_SETUP_EXAMPLES - Context Setup Examples ***************************************************************************/ /* XPT_RAVE :: NOTEA_CONTEXT_SETUP_EXAMPLES :: CONTEXT_EXAMPLES [31:00] */ #define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_MASK 0xffffffff #define BCHP_XPT_RAVE_NOTEA_CONTEXT_SETUP_EXAMPLES_CONTEXT_EXAMPLES_SHIFT 0 /*************************************************************************** *NOTEB_STREAM_TYPE_SETUP - Stream Type Setup ***************************************************************************/ /* XPT_RAVE :: NOTEB_STREAM_TYPE_SETUP :: STREAM_TYPE_SETUP [31:00] */ #define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_MASK 0xffffffff #define BCHP_XPT_RAVE_NOTEB_STREAM_TYPE_SETUP_STREAM_TYPE_SETUP_SHIFT 0 /*************************************************************************** *NOTEC_PES_LAYER_SELECTION - PES Layer Selection ***************************************************************************/ /* XPT_RAVE :: NOTEC_PES_LAYER_SELECTION :: PES_LAYER_SELECTION [31:00] */ #define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_MASK 0xffffffff #define BCHP_XPT_RAVE_NOTEC_PES_LAYER_SELECTION_PES_LAYER_SELECTION_SHIFT 0 /*************************************************************************** *NOTED_ES_FORMAT_SELECTION_GENERAL - ES Format Selection - general ***************************************************************************/ /* XPT_RAVE :: NOTED_ES_FORMAT_SELECTION_GENERAL :: GENERAL_ES_FORMAT_SELECTION [31:00] */ #define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_MASK 0xffffffff #define BCHP_XPT_RAVE_NOTED_ES_FORMAT_SELECTION_GENERAL_GENERAL_ES_FORMAT_SELECTION_SHIFT 0 /*************************************************************************** *NOTEE_MPEG2_VIDEO_ES_SETUP - ES Setup - MPEG2 Video ***************************************************************************/ /* XPT_RAVE :: NOTEE_MPEG2_VIDEO_ES_SETUP :: MPEG2_VIDEO_ES_FORMAT [31:00] */ #define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_MASK 0xffffffff #define BCHP_XPT_RAVE_NOTEE_MPEG2_VIDEO_ES_SETUP_MPEG2_VIDEO_ES_FORMAT_SHIFT 0 /*************************************************************************** *NOTEF_AVC_VC1_VIDEO_ES_SETUP - ES Setup - AVC and VC1 Video ***************************************************************************/ /* XPT_RAVE :: NOTEF_AVC_VC1_VIDEO_ES_SETUP :: AVC_VC1_VIDEO_ES_FORMAT [31:00] */ #define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_MASK 0xffffffff #define BCHP_XPT_RAVE_NOTEF_AVC_VC1_VIDEO_ES_SETUP_AVC_VC1_VIDEO_ES_FORMAT_SHIFT 0 /*************************************************************************** *NOTEG_MPEG_AUDIO_ES_SETUP - ES Setup - MPEG Audio ***************************************************************************/ /* XPT_RAVE :: NOTEG_MPEG_AUDIO_ES_SETUP :: AUDIO_MPEG_ES_FORMAT [31:00] */ #define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_MASK 0xffffffff #define BCHP_XPT_RAVE_NOTEG_MPEG_AUDIO_ES_SETUP_AUDIO_MPEG_ES_FORMAT_SHIFT 0 /*************************************************************************** *NOTEH_AAC_AUDIO_ES_SETUP - ES Setup - AAC Audio ***************************************************************************/ /* XPT_RAVE :: NOTEH_AAC_AUDIO_ES_SETUP :: AUDIO_AAC_ES_FORMAT [31:00] */ #define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_MASK 0xffffffff #define BCHP_XPT_RAVE_NOTEH_AAC_AUDIO_ES_SETUP_AUDIO_AAC_ES_FORMAT_SHIFT 0 /*************************************************************************** *NOTEH_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio ***************************************************************************/ /* XPT_RAVE :: NOTEH_AC3_AUDIO_ES_SETUP :: AUDIO_AC3_ES_FORMAT [31:00] */ #define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff #define BCHP_XPT_RAVE_NOTEH_AC3_AUDIO_ES_SETUP_AUDIO_AC3_ES_FORMAT_SHIFT 0 /*************************************************************************** *NOTEH_DVD_AC3_AUDIO_ES_SETUP - ES Setup - DVD_AC3 Audio ***************************************************************************/ /* XPT_RAVE :: NOTEH_DVD_AC3_AUDIO_ES_SETUP :: DVD_AUDIO_AC3_ES_FORMAT [31:00] */ #define BCHP_XPT_RAVE_NOTEH_DVD_AC3_AUDIO_ES_SETUP_DVD_AUDIO_AC3_ES_FORMAT_MASK 0xffffffff #define BCHP_XPT_RAVE_NOTEH_DVD_AC3_AUDIO_ES_SETUP_DVD_AUDIO_AC3_ES_FORMAT_SHIFT 0 /*************************************************************************** *NOTEI_DVD_LPCM_AUDIO_ES_SETUP - ES Setup - DVD_LPCM Audio ***************************************************************************/ /* XPT_RAVE :: NOTEI_DVD_LPCM_AUDIO_ES_SETUP :: DVD_AUDIO_LPCM_ES_FORMAT [31:00] */ #define BCHP_XPT_RAVE_NOTEI_DVD_LPCM_AUDIO_ES_SETUP_DVD_AUDIO_LPCM_ES_FORMAT_MASK 0xffffffff #define BCHP_XPT_RAVE_NOTEI_DVD_LPCM_AUDIO_ES_SETUP_DVD_AUDIO_LPCM_ES_FORMAT_SHIFT 0 /*************************************************************************** *NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP - ES Setup - AC3 Audio ***************************************************************************/ /* XPT_RAVE :: NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP :: AUDIO_ENHANCED_AC3_ES_FORMAT [31:00] */ #define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_MASK 0xffffffff #define BCHP_XPT_RAVE_NOTEJ_ENHANCED_AC3_AUDIO_ES_SETUP_AUDIO_ENHANCED_AC3_ES_FORMAT_SHIFT 0 /*************************************************************************** *NOTEK_AAC_HE_AUDIO_ES_SETUP - ES Setup - AAC HE Audio ***************************************************************************/ /* XPT_RAVE :: NOTEK_AAC_HE_AUDIO_ES_SETUP :: AUDIO_AAC_HE_ES_FORMAT [31:00] */ #define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_MASK 0xffffffff #define BCHP_XPT_RAVE_NOTEK_AAC_HE_AUDIO_ES_SETUP_AUDIO_AAC_HE_ES_FORMAT_SHIFT 0 #endif /* #ifndef BCHP_COMMON_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015400000000000011565 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_cache_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_ca0000644000175000017500000003322411610313111030757 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_avd_cache_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:56p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:03 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_avd_cache_0.h $ * * Hydra_Software_Devel/1 7/17/09 7:56p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_AVD_CACHE_0_H__ #define BCHP_AVD_CACHE_0_H__ /*************************************************************************** *AVD_CACHE_0 - Mocomp Cache Registers 0 ***************************************************************************/ #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0 0x00862000 /* REG_PCACHE_MODE0 */ #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE1 0x00862004 /* REG_PCACHE_MODE1 */ #define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL 0x00862008 /* REG_PCACHE_CTRL */ #define BCHP_AVD_CACHE_0_REG_PCACHE_HIT_COUNT 0x0086200c /* REG_PCACHE_HIT_COUNT */ #define BCHP_AVD_CACHE_0_REG_PCACHE_MISS_COUNT 0x00862010 /* REG_PCACHE_MISS_COUNT */ #define BCHP_AVD_CACHE_0_REG_PCACHE_MISS1_COUNT 0x00862014 /* REG_PCACHE_MISS1_COUNT */ #define BCHP_AVD_CACHE_0_REG_PCACHE_BLOCK_FLAGS 0x00862018 /* REG_PCACHE_BLOCK_FLAGS */ #define BCHP_AVD_CACHE_0_REG_PCACHE_DATA 0x0086201c /* REG_PCACHE_DATA */ #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS 0x00862020 /* REG_PCACHE_TAG_CONTENTS */ #define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT 0x00862024 /* REG_PCACHE_FLAG_SELECT */ #define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL 0x00862028 /* REG_PCACHE_DEBUG_CTRL */ #define BCHP_AVD_CACHE_0_REG_PCACHE_LFSR_DATA 0x0086202c /* REG_PCACHE_LFSR_DATA */ #define BCHP_AVD_CACHE_0_REG_PCACHE_END 0x0086203c /* REG_PCACHE_END */ /*************************************************************************** *REG_PCACHE_MODE0 - REG_PCACHE_MODE0 ***************************************************************************/ /* AVD_CACHE_0 :: REG_PCACHE_MODE0 :: reserved0 [31:06] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_reserved0_MASK 0xffffffc0 #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_reserved0_SHIFT 6 /* AVD_CACHE_0 :: REG_PCACHE_MODE0 :: Bypass [05:05] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Bypass_MASK 0x00000020 #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Bypass_SHIFT 5 /* AVD_CACHE_0 :: REG_PCACHE_MODE0 :: Disable [04:04] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Disable_MASK 0x00000010 #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Disable_SHIFT 4 /* AVD_CACHE_0 :: REG_PCACHE_MODE0 :: Ygran [03:02] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Ygran_MASK 0x0000000c #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Ygran_SHIFT 2 /* AVD_CACHE_0 :: REG_PCACHE_MODE0 :: Xgran [01:00] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Xgran_MASK 0x00000003 #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE0_Xgran_SHIFT 0 /*************************************************************************** *REG_PCACHE_MODE1 - REG_PCACHE_MODE1 ***************************************************************************/ /* AVD_CACHE_0 :: REG_PCACHE_MODE1 :: reserved0 [31:01] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE1_reserved0_MASK 0xfffffffe #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE1_reserved0_SHIFT 1 /* AVD_CACHE_0 :: REG_PCACHE_MODE1 :: Mbaff_disable [00:00] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE1_Mbaff_disable_MASK 0x00000001 #define BCHP_AVD_CACHE_0_REG_PCACHE_MODE1_Mbaff_disable_SHIFT 0 /*************************************************************************** *REG_PCACHE_CTRL - REG_PCACHE_CTRL ***************************************************************************/ /* AVD_CACHE_0 :: REG_PCACHE_CTRL :: reserved0 [31:03] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_reserved0_MASK 0xfffffff8 #define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_reserved0_SHIFT 3 /* AVD_CACHE_0 :: REG_PCACHE_CTRL :: soft_reset [02:02] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_soft_reset_MASK 0x00000004 #define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_soft_reset_SHIFT 2 /* AVD_CACHE_0 :: REG_PCACHE_CTRL :: Counter_reset [01:01] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_Counter_reset_MASK 0x00000002 #define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_Counter_reset_SHIFT 1 /* AVD_CACHE_0 :: REG_PCACHE_CTRL :: Flush [00:00] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_Flush_MASK 0x00000001 #define BCHP_AVD_CACHE_0_REG_PCACHE_CTRL_Flush_SHIFT 0 /*************************************************************************** *REG_PCACHE_HIT_COUNT - REG_PCACHE_HIT_COUNT ***************************************************************************/ /* AVD_CACHE_0 :: REG_PCACHE_HIT_COUNT :: hit_count [31:00] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_HIT_COUNT_hit_count_MASK 0xffffffff #define BCHP_AVD_CACHE_0_REG_PCACHE_HIT_COUNT_hit_count_SHIFT 0 /*************************************************************************** *REG_PCACHE_MISS_COUNT - REG_PCACHE_MISS_COUNT ***************************************************************************/ /* AVD_CACHE_0 :: REG_PCACHE_MISS_COUNT :: miss_count [31:00] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_MISS_COUNT_miss_count_MASK 0xffffffff #define BCHP_AVD_CACHE_0_REG_PCACHE_MISS_COUNT_miss_count_SHIFT 0 /*************************************************************************** *REG_PCACHE_MISS1_COUNT - REG_PCACHE_MISS1_COUNT ***************************************************************************/ /* AVD_CACHE_0 :: REG_PCACHE_MISS1_COUNT :: miss1_count [31:00] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_MISS1_COUNT_miss1_count_MASK 0xffffffff #define BCHP_AVD_CACHE_0_REG_PCACHE_MISS1_COUNT_miss1_count_SHIFT 0 /*************************************************************************** *REG_PCACHE_BLOCK_FLAGS - REG_PCACHE_BLOCK_FLAGS ***************************************************************************/ /* AVD_CACHE_0 :: REG_PCACHE_BLOCK_FLAGS :: block_flags [31:00] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_BLOCK_FLAGS_block_flags_MASK 0xffffffff #define BCHP_AVD_CACHE_0_REG_PCACHE_BLOCK_FLAGS_block_flags_SHIFT 0 /*************************************************************************** *REG_PCACHE_DATA - REG_PCACHE_DATA ***************************************************************************/ /* AVD_CACHE_0 :: REG_PCACHE_DATA :: data_word [31:00] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_DATA_data_word_MASK 0xffffffff #define BCHP_AVD_CACHE_0_REG_PCACHE_DATA_data_word_SHIFT 0 /*************************************************************************** *REG_PCACHE_TAG_CONTENTS - REG_PCACHE_TAG_CONTENTS ***************************************************************************/ /* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: reserved0 [31:25] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved0_MASK 0xfe000000 #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved0_SHIFT 25 /* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: Valid [24:24] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Valid_MASK 0x01000000 #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Valid_SHIFT 24 /* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: Picture_Base_ID [23:20] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Picture_Base_ID_MASK 0x00f00000 #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Picture_Base_ID_SHIFT 20 /* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: reserved1 [19:18] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved1_MASK 0x000c0000 #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved1_SHIFT 18 /* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: Component [17:17] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Component_MASK 0x00020000 #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Component_SHIFT 17 /* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: Field_Frame [16:16] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Field_Frame_MASK 0x00010000 #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Field_Frame_SHIFT 16 /* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: reserved2 [15:14] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved2_MASK 0x0000c000 #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved2_SHIFT 14 /* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: X_origin [13:08] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_X_origin_MASK 0x00003f00 #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_X_origin_SHIFT 8 /* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: reserved3 [07:06] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved3_MASK 0x000000c0 #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_reserved3_SHIFT 6 /* AVD_CACHE_0 :: REG_PCACHE_TAG_CONTENTS :: Y_origin [05:00] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Y_origin_MASK 0x0000003f #define BCHP_AVD_CACHE_0_REG_PCACHE_TAG_CONTENTS_Y_origin_SHIFT 0 /*************************************************************************** *REG_PCACHE_FLAG_SELECT - REG_PCACHE_FLAG_SELECT ***************************************************************************/ /* AVD_CACHE_0 :: REG_PCACHE_FLAG_SELECT :: reserved0 [31:16] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_reserved0_MASK 0xffff0000 #define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_reserved0_SHIFT 16 /* AVD_CACHE_0 :: REG_PCACHE_FLAG_SELECT :: Index [15:08] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_Index_MASK 0x0000ff00 #define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_Index_SHIFT 8 /* AVD_CACHE_0 :: REG_PCACHE_FLAG_SELECT :: reserved1 [07:06] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_reserved1_MASK 0x000000c0 #define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_reserved1_SHIFT 6 /* AVD_CACHE_0 :: REG_PCACHE_FLAG_SELECT :: Sub_block [05:04] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_Sub_block_MASK 0x00000030 #define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_Sub_block_SHIFT 4 /* AVD_CACHE_0 :: REG_PCACHE_FLAG_SELECT :: blk [03:00] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_blk_MASK 0x0000000f #define BCHP_AVD_CACHE_0_REG_PCACHE_FLAG_SELECT_blk_SHIFT 0 /*************************************************************************** *REG_PCACHE_DEBUG_CTRL - REG_PCACHE_DEBUG_CTRL ***************************************************************************/ /* AVD_CACHE_0 :: REG_PCACHE_DEBUG_CTRL :: reserved0 [31:04] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_reserved0_MASK 0xfffffff0 #define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_reserved0_SHIFT 4 /* AVD_CACHE_0 :: REG_PCACHE_DEBUG_CTRL :: dly_fixed [03:03] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_fixed_MASK 0x00000008 #define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_fixed_SHIFT 3 /* AVD_CACHE_0 :: REG_PCACHE_DEBUG_CTRL :: dly_cmds [02:02] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_cmds_MASK 0x00000004 #define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_cmds_SHIFT 2 /* AVD_CACHE_0 :: REG_PCACHE_DEBUG_CTRL :: dly_qpel_fifo [01:01] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_qpel_fifo_MASK 0x00000002 #define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_qpel_fifo_SHIFT 1 /* AVD_CACHE_0 :: REG_PCACHE_DEBUG_CTRL :: dly_mctrl [00:00] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_mctrl_MASK 0x00000001 #define BCHP_AVD_CACHE_0_REG_PCACHE_DEBUG_CTRL_dly_mctrl_SHIFT 0 /*************************************************************************** *REG_PCACHE_LFSR_DATA - REG_PCACHE_LFSR_DATA ***************************************************************************/ /* AVD_CACHE_0 :: REG_PCACHE_LFSR_DATA :: data_word [31:00] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_LFSR_DATA_data_word_MASK 0xffffffff #define BCHP_AVD_CACHE_0_REG_PCACHE_LFSR_DATA_data_word_SHIFT 0 /*************************************************************************** *REG_PCACHE_END - REG_PCACHE_END ***************************************************************************/ /* AVD_CACHE_0 :: REG_PCACHE_END :: reserved0 [31:00] */ #define BCHP_AVD_CACHE_0_REG_PCACHE_END_reserved0_MASK 0xffffffff #define BCHP_AVD_CACHE_0_REG_PCACHE_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_AVD_CACHE_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016200000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_reg_cabac2bins2_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_reg_ca0000644000175000017500000005534011610313111030765 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_reg_cabac2bins2_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:17p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:59 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_reg_cabac2bins2_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:17p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_REG_CABAC2BINS2_0_H__ #define BCHP_REG_CABAC2BINS2_0_H__ /*************************************************************************** *REG_CABAC2BINS2_0 ***************************************************************************/ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_ADDR 0x00802588 /* REG_CABAC2BINS_RD_BUFF_ADDR */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL 0x0080258c /* REG_CABAC2BINS_RD_BUFF_CTL */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_START_ADDR 0x00802594 /* REG_CABAC2BINS_RD_BUFF_START_ADDR */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_END_ADDR 0x00802598 /* REG_CABAC2BINS_RD_BUFF_END_ADDR */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_STALL_CNT 0x0080259c /* REG_CABAC2BINS_RD_BUFF_STALL_CNT */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_START_ADDR 0x008025a8 /* REG_CABAC2BINS_WR_BUFF_START_ADDR */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL 0x008025ac /* REG_CABAC2BINS_WR_BUFF_CTL */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_END_ADDR 0x008025b0 /* REG_CABAC2BINS_WR_BUFF_END_ADDR */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_MARK_ADDR 0x008025b4 /* REG_CABAC2BINS_WR_BUFF_MARK_ADDR */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_STALL_CNT 0x008025b8 /* REG_CABAC2BINS_WR_BUFF_STALL_CNT */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_ADDR 0x008025bc /* REG_CABAC2BINS_WR_BUFF_ADDR */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_ID 0x008025c0 /* REG_CABAC2BINS_CHANNEL_ID */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_NOT_IDLE_CYCLES 0x00802620 /* REG_CABAC2BINS_NOT_IDLE_CYCLES */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE0 0x00802630 /* REG_CABAC2BINS_STATE0 */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE1 0x00802634 /* REG_CABAC2BINS_STATE1 */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_INIT_TBL_CTL 0x00802640 /* REG_CABAC2BINS_INIT_TBL_CTL */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_COMMAND_ADDR 0x00802710 /* REG_CABAC2BINS_PICTURE_COMMAND_ADDR */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_LITTLE_ENDIAN 0x00802714 /* REG_CABAC2BINS_LITTLE_ENDIAN */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS 0x00802718 /* REG_CABAC2BINS_PICTURE_STATUS */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL 0x0080272c /* REG_CABAC2BINS_CTL */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_END_END_1 0x008027fc /* REG_CABAC2BINS_END_END_1 */ /*************************************************************************** *REG_CABAC2BINS_CHANNEL_WR_POSITION_%i - REG_CABAC2BINS_CHANNEL_WR_POSITION_0..31 ***************************************************************************/ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_WR_POSITION_i_ARRAY_BASE 0x00802400 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_WR_POSITION_i_ARRAY_START 0 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_WR_POSITION_i_ARRAY_END 31 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_WR_POSITION_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *REG_CABAC2BINS_CHANNEL_WR_POSITION_%i - REG_CABAC2BINS_CHANNEL_WR_POSITION_0..31 ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CHANNEL_WR_POSITION_i :: Addr [31:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_WR_POSITION_i_Addr_MASK 0xffffffff #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_WR_POSITION_i_Addr_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_RD_BUFF_ADDR - REG_CABAC2BINS_RD_BUFF_ADDR ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_ADDR :: Addr [31:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_ADDR_Addr_MASK 0xffffffff #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_ADDR_Addr_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_RD_BUFF_CTL - REG_CABAC2BINS_RD_BUFF_CTL ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_CTL :: reserved0 [31:05] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_reserved0_MASK 0xffffffe0 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_reserved0_SHIFT 5 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_CTL :: At_mark [04:04] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_At_mark_MASK 0x00000010 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_At_mark_SHIFT 4 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_CTL :: Not_Rdy [03:03] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Not_Rdy_MASK 0x00000008 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Not_Rdy_SHIFT 3 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_CTL :: Wrap_En [02:02] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Wrap_En_MASK 0x00000004 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Wrap_En_SHIFT 2 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_CTL :: Init [01:01] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Init_MASK 0x00000002 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Init_SHIFT 1 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_CTL :: Buff_En [00:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Buff_En_MASK 0x00000001 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_CTL_Buff_En_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_RD_BUFF_START_ADDR - REG_CABAC2BINS_RD_BUFF_START_ADDR ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_START_ADDR :: Addr [31:07] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_START_ADDR_Addr_MASK 0xffffff80 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_START_ADDR_Addr_SHIFT 7 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_START_ADDR :: reserved0 [06:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_START_ADDR_reserved0_MASK 0x0000007f #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_START_ADDR_reserved0_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_RD_BUFF_END_ADDR - REG_CABAC2BINS_RD_BUFF_END_ADDR ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_END_ADDR :: Addr [31:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_END_ADDR_Addr_MASK 0xffffffff #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_END_ADDR_Addr_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_RD_BUFF_STALL_CNT - REG_CABAC2BINS_RD_BUFF_STALL_CNT ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_RD_BUFF_STALL_CNT :: Count [31:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_STALL_CNT_Count_MASK 0xffffffff #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_RD_BUFF_STALL_CNT_Count_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_WR_BUFF_START_ADDR - REG_CABAC2BINS_WR_BUFF_START_ADDR ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_START_ADDR :: Addr [31:07] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_START_ADDR_Addr_MASK 0xffffff80 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_START_ADDR_Addr_SHIFT 7 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_START_ADDR :: reserved0 [06:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_START_ADDR_reserved0_MASK 0x0000007f #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_START_ADDR_reserved0_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_WR_BUFF_CTL - REG_CABAC2BINS_WR_BUFF_CTL ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_CTL :: reserved0 [31:05] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_reserved0_MASK 0xffffffe0 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_reserved0_SHIFT 5 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_CTL :: At_mark [04:04] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_At_mark_MASK 0x00000010 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_At_mark_SHIFT 4 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_CTL :: Not_Rdy [03:03] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Not_Rdy_MASK 0x00000008 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Not_Rdy_SHIFT 3 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_CTL :: Buff_close [02:02] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Buff_close_MASK 0x00000004 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Buff_close_SHIFT 2 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_CTL :: Init [01:01] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Init_MASK 0x00000002 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Init_SHIFT 1 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_CTL :: Buff_En [00:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Buff_En_MASK 0x00000001 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_CTL_Buff_En_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_WR_BUFF_END_ADDR - REG_CABAC2BINS_WR_BUFF_END_ADDR ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_END_ADDR :: Addr [31:07] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_END_ADDR_Addr_MASK 0xffffff80 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_END_ADDR_Addr_SHIFT 7 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_END_ADDR :: reserved0 [06:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_END_ADDR_reserved0_MASK 0x0000007f #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_END_ADDR_reserved0_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_WR_BUFF_MARK_ADDR - REG_CABAC2BINS_WR_BUFF_MARK_ADDR ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_MARK_ADDR :: Addr [31:07] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_MARK_ADDR_Addr_MASK 0xffffff80 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_MARK_ADDR_Addr_SHIFT 7 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_MARK_ADDR :: reserved0 [06:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_MARK_ADDR_reserved0_MASK 0x0000007f #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_MARK_ADDR_reserved0_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_WR_BUFF_STALL_CNT - REG_CABAC2BINS_WR_BUFF_STALL_CNT ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_STALL_CNT :: Count [31:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_STALL_CNT_Count_MASK 0xffffffff #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_STALL_CNT_Count_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_WR_BUFF_ADDR - REG_CABAC2BINS_WR_BUFF_ADDR ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_WR_BUFF_ADDR :: Addr [31:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_ADDR_Addr_MASK 0xffffffff #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_WR_BUFF_ADDR_Addr_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_CHANNEL_ID - REG_CABAC2BINS_CHANNEL_ID ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CHANNEL_ID :: reserved0 [31:05] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_ID_reserved0_MASK 0xffffffe0 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_ID_reserved0_SHIFT 5 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CHANNEL_ID :: ID [04:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_ID_ID_MASK 0x0000001f #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CHANNEL_ID_ID_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_NOT_IDLE_CYCLES - REG_CABAC2BINS_NOT_IDLE_CYCLES ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_NOT_IDLE_CYCLES :: Cycle_Count [31:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_NOT_IDLE_CYCLES_Cycle_Count_MASK 0xffffffff #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_NOT_IDLE_CYCLES_Cycle_Count_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_STATE0 - REG_CABAC2BINS_STATE0 ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_STATE0 :: reserved0 [31:10] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE0_reserved0_MASK 0xfffffc00 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE0_reserved0_SHIFT 10 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_STATE0 :: State [09:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE0_State_MASK 0x000003ff #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE0_State_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_STATE1 - REG_CABAC2BINS_STATE1 ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_STATE1 :: reserved0 [31:10] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE1_reserved0_MASK 0xfffffc00 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE1_reserved0_SHIFT 10 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_STATE1 :: State [09:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE1_State_MASK 0x000003ff #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_STATE1_State_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_INIT_TBL_CTL - REG_CABAC2BINS_INIT_TBL_CTL ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_INIT_TBL_CTL :: reserved0 [31:13] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_INIT_TBL_CTL_reserved0_MASK 0xffffe000 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_INIT_TBL_CTL_reserved0_SHIFT 13 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_INIT_TBL_CTL :: Enable [12:12] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_INIT_TBL_CTL_Enable_MASK 0x00001000 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_INIT_TBL_CTL_Enable_SHIFT 12 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_INIT_TBL_CTL :: reserved1 [11:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_INIT_TBL_CTL_reserved1_MASK 0x00000fff #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_INIT_TBL_CTL_reserved1_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_PICTURE_COMMAND_ADDR - REG_CABAC2BINS_PICTURE_COMMAND_ADDR ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_PICTURE_COMMAND_ADDR :: Addr [31:02] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_COMMAND_ADDR_Addr_MASK 0xfffffffc #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_COMMAND_ADDR_Addr_SHIFT 2 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_PICTURE_COMMAND_ADDR :: reserved0 [01:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_COMMAND_ADDR_reserved0_MASK 0x00000003 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_COMMAND_ADDR_reserved0_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_LITTLE_ENDIAN - REG_CABAC2BINS_LITTLE_ENDIAN ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_LITTLE_ENDIAN :: reserved0 [31:01] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_LITTLE_ENDIAN_reserved0_MASK 0xfffffffe #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_LITTLE_ENDIAN_reserved0_SHIFT 1 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_LITTLE_ENDIAN :: Little_Endian [00:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_LITTLE_ENDIAN_Little_Endian_MASK 0x00000001 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_LITTLE_ENDIAN_Little_Endian_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_PICTURE_STATUS - REG_CABAC2BINS_PICTURE_STATUS ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_PICTURE_STATUS :: reserved0 [31:04] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_reserved0_MASK 0xfffffff0 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_reserved0_SHIFT 4 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_PICTURE_STATUS :: Picture_Cmd_Count [03:02] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_Picture_Cmd_Count_MASK 0x0000000c #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_Picture_Cmd_Count_SHIFT 2 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_PICTURE_STATUS :: Full [01:01] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_Full_MASK 0x00000002 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_Full_SHIFT 1 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_PICTURE_STATUS :: Busy [00:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_Busy_MASK 0x00000001 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_PICTURE_STATUS_Busy_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_CTL - REG_CABAC2BINS_CTL ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: reserved0 [31:12] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_reserved0_MASK 0xfffff000 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_reserved0_SHIFT 12 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: Int [11:11] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_Int_MASK 0x00000800 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_Int_SHIFT 11 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: Active [10:10] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_Active_MASK 0x00000400 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_Active_SHIFT 10 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: WrNR [09:09] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_WrNR_MASK 0x00000200 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_WrNR_SHIFT 9 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: RdNR [08:08] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_RdNR_MASK 0x00000100 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_RdNR_SHIFT 8 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: WrMk [07:07] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_WrMk_MASK 0x00000080 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_WrMk_SHIFT 7 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: RdMk [06:06] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_RdMk_MASK 0x00000040 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_RdMk_SHIFT 6 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: reserved1 [05:05] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_reserved1_MASK 0x00000020 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_reserved1_SHIFT 5 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: SdQ [04:04] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdQ_MASK 0x00000010 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdQ_SHIFT 4 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: SdWr [03:03] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdWr_MASK 0x00000008 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdWr_SHIFT 3 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: SdAct [02:02] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdAct_MASK 0x00000004 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdAct_SHIFT 2 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: SdReq [01:01] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdReq_MASK 0x00000002 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_SdReq_SHIFT 1 /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_CTL :: Reset [00:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_Reset_MASK 0x00000001 #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_CTL_Reset_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_END_END_1 - REG_CABAC2BINS_END_END_1 ***************************************************************************/ /* REG_CABAC2BINS2_0 :: REG_CABAC2BINS_END_END_1 :: reserved0 [31:00] */ #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_END_END_1_reserved0_MASK 0xffffffff #define BCHP_REG_CABAC2BINS2_0_REG_CABAC2BINS_END_END_1_reserved0_SHIFT 0 #endif /* #ifndef BCHP_REG_CABAC2BINS2_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000014600000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_timer.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_timer.0000644000175000017500000003712511610313111030744 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_timer.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:21p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:31 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_timer.h $ * * Hydra_Software_Devel/1 7/17/09 8:21p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_TIMER_H__ #define BCHP_TIMER_H__ /*************************************************************************** *TIMER - Watchdog & Programmable Timers ***************************************************************************/ #define BCHP_TIMER_TIMER_IS 0x004060c0 /* TIMER INTERRUPT STATUS REGISTER */ #define BCHP_TIMER_TIMER_IE0 0x004060c4 /* TIMER CPU INTERRUPT ENABLE REGISTER */ #define BCHP_TIMER_TIMER0_CTRL 0x004060c8 /* TIMER0 CONTROL REGISTER */ #define BCHP_TIMER_TIMER1_CTRL 0x004060cc /* TIMER1 CONTROL REGISTER */ #define BCHP_TIMER_TIMER2_CTRL 0x004060d0 /* TIMER2 CONTROL REGISTER */ #define BCHP_TIMER_TIMER3_CTRL 0x004060d4 /* TIMER3 CONTROL REGISTER */ #define BCHP_TIMER_TIMER0_STAT 0x004060d8 /* TIMER0 STATUS REGISTER */ #define BCHP_TIMER_TIMER1_STAT 0x004060dc /* TIMER1 STATUS REGISTER */ #define BCHP_TIMER_TIMER2_STAT 0x004060e0 /* TIMER2 STATUS REGISTER */ #define BCHP_TIMER_TIMER3_STAT 0x004060e4 /* TIMER3 STATUS REGISTER */ #define BCHP_TIMER_WDTIMEOUT 0x004060e8 /* WATCHDOG TIMEOUT REGISTER */ #define BCHP_TIMER_WDCMD 0x004060ec /* WATCHDOG COMMAND REGISTER */ #define BCHP_TIMER_WDCHIPRST_CNT 0x004060f0 /* WATCHDOG CHIP RESET COUNT REGISTER */ #define BCHP_TIMER_WDCRS 0x004060f4 /* WATCHDOG CHIP RESET STATUS REGISTER */ #define BCHP_TIMER_TIMER_IE1 0x004060f8 /* TIMER PCI INTERRUPT ENABLE REGISTER */ #define BCHP_TIMER_WDCTRL 0x004060fc /* WATCHDOG CONTROL REGISTER */ /*************************************************************************** *TIMER_IS - TIMER INTERRUPT STATUS REGISTER ***************************************************************************/ /* TIMER :: TIMER_IS :: reserved0 [31:05] */ #define BCHP_TIMER_TIMER_IS_reserved0_MASK 0xffffffe0 #define BCHP_TIMER_TIMER_IS_reserved0_SHIFT 5 /* TIMER :: TIMER_IS :: WDINT [04:04] */ #define BCHP_TIMER_TIMER_IS_WDINT_MASK 0x00000010 #define BCHP_TIMER_TIMER_IS_WDINT_SHIFT 4 /* TIMER :: TIMER_IS :: TMR3TO [03:03] */ #define BCHP_TIMER_TIMER_IS_TMR3TO_MASK 0x00000008 #define BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT 3 /* TIMER :: TIMER_IS :: TMR2TO [02:02] */ #define BCHP_TIMER_TIMER_IS_TMR2TO_MASK 0x00000004 #define BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT 2 /* TIMER :: TIMER_IS :: TMR1TO [01:01] */ #define BCHP_TIMER_TIMER_IS_TMR1TO_MASK 0x00000002 #define BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT 1 /* TIMER :: TIMER_IS :: TMR0TO [00:00] */ #define BCHP_TIMER_TIMER_IS_TMR0TO_MASK 0x00000001 #define BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT 0 /*************************************************************************** *TIMER_IE0 - TIMER CPU INTERRUPT ENABLE REGISTER ***************************************************************************/ /* TIMER :: TIMER_IE0 :: reserved0 [31:05] */ #define BCHP_TIMER_TIMER_IE0_reserved0_MASK 0xffffffe0 #define BCHP_TIMER_TIMER_IE0_reserved0_SHIFT 5 /* TIMER :: TIMER_IE0 :: WDINTMASK [04:04] */ #define BCHP_TIMER_TIMER_IE0_WDINTMASK_MASK 0x00000010 #define BCHP_TIMER_TIMER_IE0_WDINTMASK_SHIFT 4 /* TIMER :: TIMER_IE0 :: TMR3TO [03:03] */ #define BCHP_TIMER_TIMER_IE0_TMR3TO_MASK 0x00000008 #define BCHP_TIMER_TIMER_IE0_TMR3TO_SHIFT 3 /* TIMER :: TIMER_IE0 :: TMR2TO [02:02] */ #define BCHP_TIMER_TIMER_IE0_TMR2TO_MASK 0x00000004 #define BCHP_TIMER_TIMER_IE0_TMR2TO_SHIFT 2 /* TIMER :: TIMER_IE0 :: TMR1TO [01:01] */ #define BCHP_TIMER_TIMER_IE0_TMR1TO_MASK 0x00000002 #define BCHP_TIMER_TIMER_IE0_TMR1TO_SHIFT 1 /* TIMER :: TIMER_IE0 :: TMR0TO [00:00] */ #define BCHP_TIMER_TIMER_IE0_TMR0TO_MASK 0x00000001 #define BCHP_TIMER_TIMER_IE0_TMR0TO_SHIFT 0 /*************************************************************************** *TIMER0_CTRL - TIMER0 CONTROL REGISTER ***************************************************************************/ /* TIMER :: TIMER0_CTRL :: ENA [31:31] */ #define BCHP_TIMER_TIMER0_CTRL_ENA_MASK 0x80000000 #define BCHP_TIMER_TIMER0_CTRL_ENA_SHIFT 31 /* TIMER :: TIMER0_CTRL :: MODE [30:30] */ #define BCHP_TIMER_TIMER0_CTRL_MODE_MASK 0x40000000 #define BCHP_TIMER_TIMER0_CTRL_MODE_SHIFT 30 /* TIMER :: TIMER0_CTRL :: TIMEOUT_VAL [29:00] */ #define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_MASK 0x3fffffff #define BCHP_TIMER_TIMER0_CTRL_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *TIMER1_CTRL - TIMER1 CONTROL REGISTER ***************************************************************************/ /* TIMER :: TIMER1_CTRL :: ENA [31:31] */ #define BCHP_TIMER_TIMER1_CTRL_ENA_MASK 0x80000000 #define BCHP_TIMER_TIMER1_CTRL_ENA_SHIFT 31 /* TIMER :: TIMER1_CTRL :: MODE [30:30] */ #define BCHP_TIMER_TIMER1_CTRL_MODE_MASK 0x40000000 #define BCHP_TIMER_TIMER1_CTRL_MODE_SHIFT 30 /* TIMER :: TIMER1_CTRL :: TIMEOUT_VAL [29:00] */ #define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_MASK 0x3fffffff #define BCHP_TIMER_TIMER1_CTRL_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *TIMER2_CTRL - TIMER2 CONTROL REGISTER ***************************************************************************/ /* TIMER :: TIMER2_CTRL :: ENA [31:31] */ #define BCHP_TIMER_TIMER2_CTRL_ENA_MASK 0x80000000 #define BCHP_TIMER_TIMER2_CTRL_ENA_SHIFT 31 /* TIMER :: TIMER2_CTRL :: MODE [30:30] */ #define BCHP_TIMER_TIMER2_CTRL_MODE_MASK 0x40000000 #define BCHP_TIMER_TIMER2_CTRL_MODE_SHIFT 30 /* TIMER :: TIMER2_CTRL :: TIMEOUT_VAL [29:00] */ #define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_MASK 0x3fffffff #define BCHP_TIMER_TIMER2_CTRL_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *TIMER3_CTRL - TIMER3 CONTROL REGISTER ***************************************************************************/ /* TIMER :: TIMER3_CTRL :: ENA [31:31] */ #define BCHP_TIMER_TIMER3_CTRL_ENA_MASK 0x80000000 #define BCHP_TIMER_TIMER3_CTRL_ENA_SHIFT 31 /* TIMER :: TIMER3_CTRL :: MODE [30:30] */ #define BCHP_TIMER_TIMER3_CTRL_MODE_MASK 0x40000000 #define BCHP_TIMER_TIMER3_CTRL_MODE_SHIFT 30 /* TIMER :: TIMER3_CTRL :: TIMEOUT_VAL [29:00] */ #define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_MASK 0x3fffffff #define BCHP_TIMER_TIMER3_CTRL_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *TIMER0_STAT - TIMER0 STATUS REGISTER ***************************************************************************/ /* TIMER :: TIMER0_STAT :: RESERVED [31:30] */ #define BCHP_TIMER_TIMER0_STAT_RESERVED_MASK 0xc0000000 #define BCHP_TIMER_TIMER0_STAT_RESERVED_SHIFT 30 /* TIMER :: TIMER0_STAT :: COUNTER_VAL [29:00] */ #define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_MASK 0x3fffffff #define BCHP_TIMER_TIMER0_STAT_COUNTER_VAL_SHIFT 0 /*************************************************************************** *TIMER1_STAT - TIMER1 STATUS REGISTER ***************************************************************************/ /* TIMER :: TIMER1_STAT :: RESERVED [31:30] */ #define BCHP_TIMER_TIMER1_STAT_RESERVED_MASK 0xc0000000 #define BCHP_TIMER_TIMER1_STAT_RESERVED_SHIFT 30 /* TIMER :: TIMER1_STAT :: COUNTER_VAL [29:00] */ #define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_MASK 0x3fffffff #define BCHP_TIMER_TIMER1_STAT_COUNTER_VAL_SHIFT 0 /*************************************************************************** *TIMER2_STAT - TIMER2 STATUS REGISTER ***************************************************************************/ /* TIMER :: TIMER2_STAT :: RESERVED [31:30] */ #define BCHP_TIMER_TIMER2_STAT_RESERVED_MASK 0xc0000000 #define BCHP_TIMER_TIMER2_STAT_RESERVED_SHIFT 30 /* TIMER :: TIMER2_STAT :: COUNTER_VAL [29:00] */ #define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_MASK 0x3fffffff #define BCHP_TIMER_TIMER2_STAT_COUNTER_VAL_SHIFT 0 /*************************************************************************** *TIMER3_STAT - TIMER3 STATUS REGISTER ***************************************************************************/ /* TIMER :: TIMER3_STAT :: RESERVED [31:30] */ #define BCHP_TIMER_TIMER3_STAT_RESERVED_MASK 0xc0000000 #define BCHP_TIMER_TIMER3_STAT_RESERVED_SHIFT 30 /* TIMER :: TIMER3_STAT :: COUNTER_VAL [29:00] */ #define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_MASK 0x3fffffff #define BCHP_TIMER_TIMER3_STAT_COUNTER_VAL_SHIFT 0 /*************************************************************************** *WDTIMEOUT - WATCHDOG TIMEOUT REGISTER ***************************************************************************/ /* TIMER :: WDTIMEOUT :: WDTIMEOUT_VAL [31:00] */ #define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_MASK 0xffffffff #define BCHP_TIMER_WDTIMEOUT_WDTIMEOUT_VAL_SHIFT 0 /*************************************************************************** *WDCMD - WATCHDOG COMMAND REGISTER ***************************************************************************/ /* TIMER :: WDCMD :: WDCMD [31:00] */ #define BCHP_TIMER_WDCMD_WDCMD_MASK 0xffffffff #define BCHP_TIMER_WDCMD_WDCMD_SHIFT 0 /*************************************************************************** *WDCHIPRST_CNT - WATCHDOG CHIP RESET COUNT REGISTER ***************************************************************************/ /* TIMER :: WDCHIPRST_CNT :: reserved0 [31:26] */ #define BCHP_TIMER_WDCHIPRST_CNT_reserved0_MASK 0xfc000000 #define BCHP_TIMER_WDCHIPRST_CNT_reserved0_SHIFT 26 /* TIMER :: WDCHIPRST_CNT :: WDCHIPRST_CNT [25:00] */ #define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_MASK 0x03ffffff #define BCHP_TIMER_WDCHIPRST_CNT_WDCHIPRST_CNT_SHIFT 0 /*************************************************************************** *WDCRS - WATCHDOG CHIP RESET STATUS REGISTER ***************************************************************************/ /* TIMER :: WDCRS :: reserved0 [31:01] */ #define BCHP_TIMER_WDCRS_reserved0_MASK 0xfffffffe #define BCHP_TIMER_WDCRS_reserved0_SHIFT 1 /* TIMER :: WDCRS :: WDCR [00:00] */ #define BCHP_TIMER_WDCRS_WDCR_MASK 0x00000001 #define BCHP_TIMER_WDCRS_WDCR_SHIFT 0 /*************************************************************************** *TIMER_IE1 - TIMER PCI INTERRUPT ENABLE REGISTER ***************************************************************************/ /* TIMER :: TIMER_IE1 :: reserved0 [31:05] */ #define BCHP_TIMER_TIMER_IE1_reserved0_MASK 0xffffffe0 #define BCHP_TIMER_TIMER_IE1_reserved0_SHIFT 5 /* TIMER :: TIMER_IE1 :: WDINTMASK [04:04] */ #define BCHP_TIMER_TIMER_IE1_WDINTMASK_MASK 0x00000010 #define BCHP_TIMER_TIMER_IE1_WDINTMASK_SHIFT 4 /* TIMER :: TIMER_IE1 :: TMR3TO [03:03] */ #define BCHP_TIMER_TIMER_IE1_TMR3TO_MASK 0x00000008 #define BCHP_TIMER_TIMER_IE1_TMR3TO_SHIFT 3 /* TIMER :: TIMER_IE1 :: TMR2TO [02:02] */ #define BCHP_TIMER_TIMER_IE1_TMR2TO_MASK 0x00000004 #define BCHP_TIMER_TIMER_IE1_TMR2TO_SHIFT 2 /* TIMER :: TIMER_IE1 :: TMR1TO [01:01] */ #define BCHP_TIMER_TIMER_IE1_TMR1TO_MASK 0x00000002 #define BCHP_TIMER_TIMER_IE1_TMR1TO_SHIFT 1 /* TIMER :: TIMER_IE1 :: TMR0TO [00:00] */ #define BCHP_TIMER_TIMER_IE1_TMR0TO_MASK 0x00000001 #define BCHP_TIMER_TIMER_IE1_TMR0TO_SHIFT 0 /*************************************************************************** *WDCTRL - WATCHDOG CONTROL REGISTER ***************************************************************************/ /* TIMER :: WDCTRL :: reserved0 [31:03] */ #define BCHP_TIMER_WDCTRL_reserved0_MASK 0xfffffff8 #define BCHP_TIMER_WDCTRL_reserved0_SHIFT 3 /* TIMER :: WDCTRL :: WD_COUNT_MODE [02:02] */ #define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_MASK 0x00000004 #define BCHP_TIMER_WDCTRL_WD_COUNT_MODE_SHIFT 2 /* TIMER :: WDCTRL :: WD_EVENT_MODE [01:00] */ #define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_MASK 0x00000003 #define BCHP_TIMER_WDCTRL_WD_EVENT_MODE_SHIFT 0 #endif /* #ifndef BCHP_TIMER_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015600000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_armcr40000644000175000017500000007515711610313111030745 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_armcr4_bridge.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:28p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:56 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge.h $ * * Hydra_Software_Devel/1 7/17/09 8:28p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_ARMCR4_BRIDGE_H__ #define BCHP_ARMCR4_BRIDGE_H__ /*************************************************************************** *ARMCR4_BRIDGE - ARM Cortex R4 Bridge control registers ***************************************************************************/ #define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID 0x000e0000 /* ARM Cortex R4 bridge revision ID */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL 0x000e0004 /* Bridge interface and buffer configuration */ #define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL 0x000e0008 /* ARM core configuration */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS 0x000e0014 /* Bridge interface and buffer status */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI1 0x000e0018 /* PCI mailbox #1 */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1 0x000e001c /* ARM mailbox #1 */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI2 0x000e0020 /* PCI mailbox #2 */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM2 0x000e0024 /* ARM mailbox #2 */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI3 0x000e0028 /* PCI mailbox #3 */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM3 0x000e002c /* ARM mailbox #3 */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI4 0x000e0030 /* PCI mailbox #4 */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM4 0x000e0034 /* ARM mailbox #4 */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_1 0x000e0038 /* CPU semaphore #1 */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_2 0x000e003c /* CPU semaphore #2 */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_3 0x000e0040 /* CPU semaphore #3 */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_4 0x000e0044 /* CPU semaphore #4 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_1 0x000e0048 /* CPU scratchpad #1 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_2 0x000e004c /* CPU scratchpad #2 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_3 0x000e0050 /* CPU scratchpad #3 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_4 0x000e0054 /* CPU scratchpad #4 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_5 0x000e0058 /* CPU scratchpad #5 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_6 0x000e005c /* CPU scratchpad #6 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_7 0x000e0060 /* CPU scratchpad #7 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_8 0x000e0064 /* CPU scratchpad #8 */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_9 0x000e0068 /* CPU scratchpad #9 */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_CONFIG 0x000e006c /* Performance monitor configuration */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_LIMIT 0x000e0070 /* Performance monitor count threshold */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_CNT 0x000e0074 /* Counts the number of merge buffer updates (hits + misses) */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_MISS 0x000e0078 /* Counts the number of merge buffer misses */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_CNT 0x000e007c /* Counts the number of prefetch buffer accesses (hits + misses) */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_MISS 0x000e0080 /* Counts the number of prefetch buffer misses */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1 0x000e0084 /* ARM memory TM1 control register */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2 0x000e0088 /* ARM memory TM2 control register */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3 0x000e008c /* ARM memory TM3 control register */ #define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS 0x000e0090 /* Fifo Status */ #define BCHP_ARMCR4_BRIDGE_REG_BORCH_STATUS 0x000e0094 /* Bridge Out-of-range Checker Status */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM4 0x000e0098 /* ARM memory TM4 control register */ /*************************************************************************** *REG_CORE_REV_ID - ARM Cortex R4 bridge revision ID ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_CORE_REV_ID :: reserved0 [31:16] */ #define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID_reserved0_MASK 0xffff0000 #define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID_reserved0_SHIFT 16 /* ARMCR4_BRIDGE :: REG_CORE_REV_ID :: MAJOR [15:08] */ #define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID_MAJOR_MASK 0x0000ff00 #define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID_MAJOR_SHIFT 8 /* ARMCR4_BRIDGE :: REG_CORE_REV_ID :: MINOR [07:00] */ #define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID_MINOR_MASK 0x000000ff #define BCHP_ARMCR4_BRIDGE_REG_CORE_REV_ID_MINOR_SHIFT 0 /*************************************************************************** *REG_BRIDGE_CTL - Bridge interface and buffer configuration ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: reserved0 [31:24] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_reserved0_MASK 0xff000000 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_reserved0_SHIFT 24 /* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: timeout [23:12] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_timeout_MASK 0x00fff000 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_timeout_SHIFT 12 /* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: reserved1 [11:09] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_reserved1_MASK 0x00000e00 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_reserved1_SHIFT 9 /* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: ccb_space_alias_en [08:08] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_ccb_space_alias_en_MASK 0x00000100 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_ccb_space_alias_en_SHIFT 8 /* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: timeout_en [07:07] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_timeout_en_MASK 0x00000080 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_timeout_en_SHIFT 7 /* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: io_sync_en [06:06] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_io_sync_en_MASK 0x00000040 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_io_sync_en_SHIFT 6 /* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: prefetch_en [05:05] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_prefetch_en_MASK 0x00000020 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_prefetch_en_SHIFT 5 /* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: gather_en [04:04] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_gather_en_MASK 0x00000010 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_gather_en_SHIFT 4 /* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: reserved2 [03:02] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_reserved2_MASK 0x0000000c #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_reserved2_SHIFT 2 /* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: arm_run_request [01:01] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_arm_run_request_MASK 0x00000002 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_arm_run_request_SHIFT 1 /* ARMCR4_BRIDGE :: REG_BRIDGE_CTL :: bridge_soft_rst [00:00] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_bridge_soft_rst_MASK 0x00000001 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_bridge_soft_rst_SHIFT 0 /*************************************************************************** *REG_ARM_CTL - ARM core configuration ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_ARM_CTL :: reserved0 [31:05] */ #define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_reserved0_MASK 0xffffffe0 #define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_reserved0_SHIFT 5 /* ARMCR4_BRIDGE :: REG_ARM_CTL :: DAP_DBGEN [04:04] */ #define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_DAP_DBGEN_MASK 0x00000010 #define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_DAP_DBGEN_SHIFT 4 /* ARMCR4_BRIDGE :: REG_ARM_CTL :: CR4_DBGEN [03:03] */ #define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_CR4_DBGEN_MASK 0x00000008 #define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_CR4_DBGEN_SHIFT 3 /* ARMCR4_BRIDGE :: REG_ARM_CTL :: CFGNMFI [02:02] */ #define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_CFGNMFI_MASK 0x00000004 #define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_CFGNMFI_SHIFT 2 /* ARMCR4_BRIDGE :: REG_ARM_CTL :: TEINIT [01:01] */ #define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_TEINIT_MASK 0x00000002 #define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_TEINIT_SHIFT 1 /* ARMCR4_BRIDGE :: REG_ARM_CTL :: CFGEE [00:00] */ #define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_CFGEE_MASK 0x00000001 #define BCHP_ARMCR4_BRIDGE_REG_ARM_CTL_CFGEE_SHIFT 0 /*************************************************************************** *REG_BRIDGE_STS - Bridge interface and buffer status ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_BRIDGE_STS :: reserved0 [31:06] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_reserved0_MASK 0xffffffc0 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_reserved0_SHIFT 6 /* ARMCR4_BRIDGE :: REG_BRIDGE_STS :: BRIDGE_RESET_DONE [05:05] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_BRIDGE_RESET_DONE_MASK 0x00000020 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_BRIDGE_RESET_DONE_SHIFT 5 /* ARMCR4_BRIDGE :: REG_BRIDGE_STS :: ARM_STANDBYWFI [04:04] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_ARM_STANDBYWFI_MASK 0x00000010 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_ARM_STANDBYWFI_SHIFT 4 /* ARMCR4_BRIDGE :: REG_BRIDGE_STS :: prefetch_buff_idle [03:03] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_prefetch_buff_idle_MASK 0x00000008 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_prefetch_buff_idle_SHIFT 3 /* ARMCR4_BRIDGE :: REG_BRIDGE_STS :: prefetch_buff_valid [02:02] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_prefetch_buff_valid_MASK 0x00000004 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_prefetch_buff_valid_SHIFT 2 /* ARMCR4_BRIDGE :: REG_BRIDGE_STS :: merge_buff_idle [01:01] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_merge_buff_idle_MASK 0x00000002 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_merge_buff_idle_SHIFT 1 /* ARMCR4_BRIDGE :: REG_BRIDGE_STS :: merge_buff_valid [00:00] */ #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_merge_buff_valid_MASK 0x00000001 #define BCHP_ARMCR4_BRIDGE_REG_BRIDGE_STS_merge_buff_valid_SHIFT 0 /*************************************************************************** *REG_MBOX_PCI1 - PCI mailbox #1 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_MBOX_PCI1 :: mbox [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI1_mbox_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI1_mbox_SHIFT 0 /*************************************************************************** *REG_MBOX_ARM1 - ARM mailbox #1 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_MBOX_ARM1 :: mbox [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1_mbox_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1_mbox_SHIFT 0 /*************************************************************************** *REG_MBOX_PCI2 - PCI mailbox #2 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_MBOX_PCI2 :: mbox [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI2_mbox_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI2_mbox_SHIFT 0 /*************************************************************************** *REG_MBOX_ARM2 - ARM mailbox #2 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_MBOX_ARM2 :: mbox [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM2_mbox_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM2_mbox_SHIFT 0 /*************************************************************************** *REG_MBOX_PCI3 - PCI mailbox #3 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_MBOX_PCI3 :: mbox [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI3_mbox_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI3_mbox_SHIFT 0 /*************************************************************************** *REG_MBOX_ARM3 - ARM mailbox #3 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_MBOX_ARM3 :: mbox [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM3_mbox_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM3_mbox_SHIFT 0 /*************************************************************************** *REG_MBOX_PCI4 - PCI mailbox #4 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_MBOX_PCI4 :: mbox [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI4_mbox_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI4_mbox_SHIFT 0 /*************************************************************************** *REG_MBOX_ARM4 - ARM mailbox #4 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_MBOX_ARM4 :: mbox [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM4_mbox_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM4_mbox_SHIFT 0 /*************************************************************************** *REG_SEMAPHORE_1 - CPU semaphore #1 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_SEMAPHORE_1 :: reserved0 [31:08] */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_1_reserved0_MASK 0xffffff00 #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_1_reserved0_SHIFT 8 /* ARMCR4_BRIDGE :: REG_SEMAPHORE_1 :: semaphore [07:00] */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_1_semaphore_MASK 0x000000ff #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_1_semaphore_SHIFT 0 /*************************************************************************** *REG_SEMAPHORE_2 - CPU semaphore #2 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_SEMAPHORE_2 :: reserved0 [31:08] */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_2_reserved0_MASK 0xffffff00 #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_2_reserved0_SHIFT 8 /* ARMCR4_BRIDGE :: REG_SEMAPHORE_2 :: semaphore [07:00] */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_2_semaphore_MASK 0x000000ff #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_2_semaphore_SHIFT 0 /*************************************************************************** *REG_SEMAPHORE_3 - CPU semaphore #3 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_SEMAPHORE_3 :: reserved0 [31:08] */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_3_reserved0_MASK 0xffffff00 #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_3_reserved0_SHIFT 8 /* ARMCR4_BRIDGE :: REG_SEMAPHORE_3 :: semaphore [07:00] */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_3_semaphore_MASK 0x000000ff #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_3_semaphore_SHIFT 0 /*************************************************************************** *REG_SEMAPHORE_4 - CPU semaphore #4 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_SEMAPHORE_4 :: reserved0 [31:08] */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_4_reserved0_MASK 0xffffff00 #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_4_reserved0_SHIFT 8 /* ARMCR4_BRIDGE :: REG_SEMAPHORE_4 :: semaphore [07:00] */ #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_4_semaphore_MASK 0x000000ff #define BCHP_ARMCR4_BRIDGE_REG_SEMAPHORE_4_semaphore_SHIFT 0 /*************************************************************************** *REG_SCRATCH_1 - CPU scratchpad #1 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_SCRATCH_1 :: data [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_1_data_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_1_data_SHIFT 0 /*************************************************************************** *REG_SCRATCH_2 - CPU scratchpad #2 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_SCRATCH_2 :: data [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_2_data_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_2_data_SHIFT 0 /*************************************************************************** *REG_SCRATCH_3 - CPU scratchpad #3 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_SCRATCH_3 :: data [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_3_data_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_3_data_SHIFT 0 /*************************************************************************** *REG_SCRATCH_4 - CPU scratchpad #4 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_SCRATCH_4 :: data [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_4_data_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_4_data_SHIFT 0 /*************************************************************************** *REG_SCRATCH_5 - CPU scratchpad #5 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_SCRATCH_5 :: data [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_5_data_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_5_data_SHIFT 0 /*************************************************************************** *REG_SCRATCH_6 - CPU scratchpad #6 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_SCRATCH_6 :: data [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_6_data_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_6_data_SHIFT 0 /*************************************************************************** *REG_SCRATCH_7 - CPU scratchpad #7 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_SCRATCH_7 :: data [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_7_data_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_7_data_SHIFT 0 /*************************************************************************** *REG_SCRATCH_8 - CPU scratchpad #8 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_SCRATCH_8 :: data [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_8_data_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_8_data_SHIFT 0 /*************************************************************************** *REG_SCRATCH_9 - CPU scratchpad #9 ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_SCRATCH_9 :: data [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_9_data_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_SCRATCH_9_data_SHIFT 0 /*************************************************************************** *REG_PERF_CONFIG - Performance monitor configuration ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_PERF_CONFIG :: reserved0 [31:01] */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_CONFIG_reserved0_MASK 0xfffffffe #define BCHP_ARMCR4_BRIDGE_REG_PERF_CONFIG_reserved0_SHIFT 1 /* ARMCR4_BRIDGE :: REG_PERF_CONFIG :: enable [00:00] */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_CONFIG_enable_MASK 0x00000001 #define BCHP_ARMCR4_BRIDGE_REG_PERF_CONFIG_enable_SHIFT 0 /*************************************************************************** *REG_PERF_LIMIT - Performance monitor count threshold ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_PERF_LIMIT :: count [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_LIMIT_count_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_PERF_LIMIT_count_SHIFT 0 /*************************************************************************** *REG_PERF_WR_CNT - Counts the number of merge buffer updates (hits + misses) ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_PERF_WR_CNT :: count [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_CNT_count_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_CNT_count_SHIFT 0 /*************************************************************************** *REG_PERF_WR_MISS - Counts the number of merge buffer misses ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_PERF_WR_MISS :: count [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_MISS_count_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_PERF_WR_MISS_count_SHIFT 0 /*************************************************************************** *REG_PERF_RD_CNT - Counts the number of prefetch buffer accesses (hits + misses) ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_PERF_RD_CNT :: count [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_CNT_count_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_CNT_count_SHIFT 0 /*************************************************************************** *REG_PERF_RD_MISS - Counts the number of prefetch buffer misses ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_PERF_RD_MISS :: count [31:00] */ #define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_MISS_count_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_REG_PERF_RD_MISS_count_SHIFT 0 /*************************************************************************** *REG_MEMORY_TM1 - ARM memory TM1 control register ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc7 [31:28] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc7_MASK 0xf0000000 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc7_SHIFT 28 /* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc6 [27:24] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc6_MASK 0x0f000000 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc6_SHIFT 24 /* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc5 [23:20] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc5_MASK 0x00f00000 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc5_SHIFT 20 /* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc4 [19:16] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc4_MASK 0x000f0000 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc4_SHIFT 16 /* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc3 [15:12] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc3_MASK 0x0000f000 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc3_SHIFT 12 /* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc2 [11:08] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc2_MASK 0x00000f00 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc2_SHIFT 8 /* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc1 [07:04] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc1_MASK 0x000000f0 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc1_SHIFT 4 /* ARMCR4_BRIDGE :: REG_MEMORY_TM1 :: tm_dc0 [03:00] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc0_MASK 0x0000000f #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM1_tm_dc0_SHIFT 0 /*************************************************************************** *REG_MEMORY_TM2 - ARM memory TM2 control register ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_MEMORY_TM2 :: reserved0 [31:18] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_reserved0_MASK 0xfffc0000 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_reserved0_SHIFT 18 /* ARMCR4_BRIDGE :: REG_MEMORY_TM2 :: tm_dirty [17:16] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_dirty_MASK 0x00030000 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_dirty_SHIFT 16 /* ARMCR4_BRIDGE :: REG_MEMORY_TM2 :: tm_ic6 [15:12] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic6_MASK 0x0000f000 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic6_SHIFT 12 /* ARMCR4_BRIDGE :: REG_MEMORY_TM2 :: tm_ic4 [11:08] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic4_MASK 0x00000f00 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic4_SHIFT 8 /* ARMCR4_BRIDGE :: REG_MEMORY_TM2 :: tm_ic2 [07:04] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic2_MASK 0x000000f0 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic2_SHIFT 4 /* ARMCR4_BRIDGE :: REG_MEMORY_TM2 :: tm_ic0 [03:00] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic0_MASK 0x0000000f #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM2_tm_ic0_SHIFT 0 /*************************************************************************** *REG_MEMORY_TM3 - ARM memory TM3 control register ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: reserved0 [31:16] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_reserved0_MASK 0xffff0000 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_reserved0_SHIFT 16 /* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_it3 [15:14] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it3_MASK 0x0000c000 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it3_SHIFT 14 /* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_it2 [13:12] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it2_MASK 0x00003000 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it2_SHIFT 12 /* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_it1 [11:10] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it1_MASK 0x00000c00 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it1_SHIFT 10 /* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_it0 [09:08] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it0_MASK 0x00000300 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_it0_SHIFT 8 /* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_dt3 [07:06] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt3_MASK 0x000000c0 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt3_SHIFT 6 /* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_dt2 [05:04] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt2_MASK 0x00000030 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt2_SHIFT 4 /* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_dt1 [03:02] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt1_MASK 0x0000000c #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt1_SHIFT 2 /* ARMCR4_BRIDGE :: REG_MEMORY_TM3 :: tm_dt0 [01:00] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt0_MASK 0x00000003 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM3_tm_dt0_SHIFT 0 /*************************************************************************** *REG_FIFO_STATUS - Fifo Status ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_FIFO_STATUS :: reserved0 [31:02] */ #define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS_reserved0_MASK 0xfffffffc #define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS_reserved0_SHIFT 2 /* ARMCR4_BRIDGE :: REG_FIFO_STATUS :: CCB_RD_FULL [01:01] */ #define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS_CCB_RD_FULL_MASK 0x00000002 #define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS_CCB_RD_FULL_SHIFT 1 /* ARMCR4_BRIDGE :: REG_FIFO_STATUS :: CCB_WR_FULL [00:00] */ #define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS_CCB_WR_FULL_MASK 0x00000001 #define BCHP_ARMCR4_BRIDGE_REG_FIFO_STATUS_CCB_WR_FULL_SHIFT 0 /*************************************************************************** *REG_BORCH_STATUS - Bridge Out-of-range Checker Status ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_BORCH_STATUS :: reserved0 [31:01] */ #define BCHP_ARMCR4_BRIDGE_REG_BORCH_STATUS_reserved0_MASK 0xfffffffe #define BCHP_ARMCR4_BRIDGE_REG_BORCH_STATUS_reserved0_SHIFT 1 /* ARMCR4_BRIDGE :: REG_BORCH_STATUS :: BORCH_ERROR_STATUS [00:00] */ #define BCHP_ARMCR4_BRIDGE_REG_BORCH_STATUS_BORCH_ERROR_STATUS_MASK 0x00000001 #define BCHP_ARMCR4_BRIDGE_REG_BORCH_STATUS_BORCH_ERROR_STATUS_SHIFT 0 /*************************************************************************** *REG_MEMORY_TM4 - ARM memory TM4 control register ***************************************************************************/ /* ARMCR4_BRIDGE :: REG_MEMORY_TM4 :: reserved0 [31:02] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM4_reserved0_MASK 0xfffffffc #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM4_reserved0_SHIFT 2 /* ARMCR4_BRIDGE :: REG_MEMORY_TM4 :: tm_pref [01:00] */ #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM4_tm_pref_MASK 0x00000003 #define BCHP_ARMCR4_BRIDGE_REG_MEMORY_TM4_tm_pref_SHIFT 0 #endif /* #ifndef BCHP_ARMCR4_BRIDGE_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015400000000000011565 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_intr2_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_in0000644000175000017500000017774111610313111031017 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_avd_intr2_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:57p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:50 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_avd_intr2_0.h $ * * Hydra_Software_Devel/1 7/17/09 7:57p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_AVD_INTR2_0_H__ #define BCHP_AVD_INTR2_0_H__ /*************************************************************************** *AVD_INTR2_0 ***************************************************************************/ #define BCHP_AVD_INTR2_0_CPU_STATUS 0x00900000 /* CPU interrupt Status Register */ #define BCHP_AVD_INTR2_0_CPU_SET 0x00900004 /* CPU interrupt Set Register */ #define BCHP_AVD_INTR2_0_CPU_CLEAR 0x00900008 /* CPU interrupt Clear Register */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS 0x0090000c /* CPU interrupt Mask Status Register */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET 0x00900010 /* CPU interrupt Mask Set Register */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR 0x00900014 /* CPU interrupt Mask Clear Register */ #define BCHP_AVD_INTR2_0_PCI_STATUS 0x00900018 /* PCI interrupt Status Register */ #define BCHP_AVD_INTR2_0_PCI_SET 0x0090001c /* PCI interrupt Set Register */ #define BCHP_AVD_INTR2_0_PCI_CLEAR 0x00900020 /* PCI interrupt Clear Register */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS 0x00900024 /* PCI interrupt Mask Status Register */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET 0x00900028 /* PCI interrupt Mask Set Register */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR 0x0090002c /* PCI interrupt Mask Clear Register */ /*************************************************************************** *CPU_STATUS - CPU interrupt Status Register ***************************************************************************/ /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR15 [31:31] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR15_MASK 0x80000000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR15_SHIFT 31 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR14 [30:30] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR14_MASK 0x40000000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR14_SHIFT 30 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR13 [29:29] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR13_MASK 0x20000000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR13_SHIFT 29 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR12 [28:28] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR12_MASK 0x10000000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR12_SHIFT 28 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR11 [27:27] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR11_MASK 0x08000000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR11_SHIFT 27 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR10 [26:26] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR10_MASK 0x04000000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR10_SHIFT 26 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR9 [25:25] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR9_MASK 0x02000000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR9_SHIFT 25 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR8 [24:24] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR8_MASK 0x01000000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR8_SHIFT 24 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR7 [23:23] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR7_MASK 0x00800000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR7_SHIFT 23 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR6 [22:22] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR6_MASK 0x00400000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR6_SHIFT 22 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR5 [21:21] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR5_MASK 0x00200000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR5_SHIFT 21 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR4 [20:20] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR4_MASK 0x00100000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR4_SHIFT 20 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR3 [19:19] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR3_MASK 0x00080000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR3_SHIFT 19 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR2 [18:18] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR2_MASK 0x00040000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR2_SHIFT 18 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR1 [17:17] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR1_MASK 0x00020000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR1_SHIFT 17 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_SW_INTR0 [16:16] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR0_MASK 0x00010000 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_SW_INTR0_SHIFT 16 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_RSVD_HW_INTR [15:07] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_RSVD_HW_INTR_MASK 0x0000ff80 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_RSVD_HW_INTR_SHIFT 7 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_WATCHDOG_INTR [06:06] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_WATCHDOG_INTR_MASK 0x00000040 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_WATCHDOG_INTR_SHIFT 6 /* AVD_INTR2_0 :: CPU_STATUS :: VICH_REG_INTR [05:05] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_REG_INTR_MASK 0x00000020 #define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_REG_INTR_SHIFT 5 /* AVD_INTR2_0 :: CPU_STATUS :: VICH_SCB_WR_INTR [04:04] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_SCB_WR_INTR_MASK 0x00000010 #define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_SCB_WR_INTR_SHIFT 4 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_PFRI_INTR [03:03] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_PFRI_INTR_MASK 0x00000008 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_PFRI_INTR_SHIFT 3 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_MBOX_INTR [02:02] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_MBOX_INTR_MASK 0x00000004 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_MBOX_INTR_SHIFT 2 /* AVD_INTR2_0 :: CPU_STATUS :: VICH_INST_RD_INTR [01:01] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_INST_RD_INTR_MASK 0x00000002 #define BCHP_AVD_INTR2_0_CPU_STATUS_VICH_INST_RD_INTR_SHIFT 1 /* AVD_INTR2_0 :: CPU_STATUS :: AVD_RGR_BRIDGE_INTR [00:00] */ #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 #define BCHP_AVD_INTR2_0_CPU_STATUS_AVD_RGR_BRIDGE_INTR_SHIFT 0 /*************************************************************************** *CPU_SET - CPU interrupt Set Register ***************************************************************************/ /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR15 [31:31] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR15_MASK 0x80000000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR15_SHIFT 31 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR14 [30:30] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR14_MASK 0x40000000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR14_SHIFT 30 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR13 [29:29] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR13_MASK 0x20000000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR13_SHIFT 29 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR12 [28:28] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR12_MASK 0x10000000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR12_SHIFT 28 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR11 [27:27] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR11_MASK 0x08000000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR11_SHIFT 27 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR10 [26:26] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR10_MASK 0x04000000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR10_SHIFT 26 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR9 [25:25] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR9_MASK 0x02000000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR9_SHIFT 25 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR8 [24:24] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR8_MASK 0x01000000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR8_SHIFT 24 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR7 [23:23] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR7_MASK 0x00800000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR7_SHIFT 23 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR6 [22:22] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR6_MASK 0x00400000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR6_SHIFT 22 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR5 [21:21] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR5_MASK 0x00200000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR5_SHIFT 21 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR4 [20:20] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR4_MASK 0x00100000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR4_SHIFT 20 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR3 [19:19] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR3_MASK 0x00080000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR3_SHIFT 19 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR2 [18:18] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR2_MASK 0x00040000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR2_SHIFT 18 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR1 [17:17] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR1_MASK 0x00020000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR1_SHIFT 17 /* AVD_INTR2_0 :: CPU_SET :: AVD_SW_INTR0 [16:16] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR0_MASK 0x00010000 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_SW_INTR0_SHIFT 16 /* AVD_INTR2_0 :: CPU_SET :: AVD_RSVD_HW_INTR [15:07] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_RSVD_HW_INTR_MASK 0x0000ff80 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_RSVD_HW_INTR_SHIFT 7 /* AVD_INTR2_0 :: CPU_SET :: AVD_WATCHDOG_INTR [06:06] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_WATCHDOG_INTR_MASK 0x00000040 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_WATCHDOG_INTR_SHIFT 6 /* AVD_INTR2_0 :: CPU_SET :: VICH_REG_INTR [05:05] */ #define BCHP_AVD_INTR2_0_CPU_SET_VICH_REG_INTR_MASK 0x00000020 #define BCHP_AVD_INTR2_0_CPU_SET_VICH_REG_INTR_SHIFT 5 /* AVD_INTR2_0 :: CPU_SET :: VICH_SCB_WR_INTR [04:04] */ #define BCHP_AVD_INTR2_0_CPU_SET_VICH_SCB_WR_INTR_MASK 0x00000010 #define BCHP_AVD_INTR2_0_CPU_SET_VICH_SCB_WR_INTR_SHIFT 4 /* AVD_INTR2_0 :: CPU_SET :: AVD_PFRI_INTR [03:03] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_PFRI_INTR_MASK 0x00000008 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_PFRI_INTR_SHIFT 3 /* AVD_INTR2_0 :: CPU_SET :: AVD_MBOX_INTR [02:02] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_MBOX_INTR_MASK 0x00000004 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_MBOX_INTR_SHIFT 2 /* AVD_INTR2_0 :: CPU_SET :: VICH_INST_RD_INTR [01:01] */ #define BCHP_AVD_INTR2_0_CPU_SET_VICH_INST_RD_INTR_MASK 0x00000002 #define BCHP_AVD_INTR2_0_CPU_SET_VICH_INST_RD_INTR_SHIFT 1 /* AVD_INTR2_0 :: CPU_SET :: AVD_RGR_BRIDGE_INTR [00:00] */ #define BCHP_AVD_INTR2_0_CPU_SET_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 #define BCHP_AVD_INTR2_0_CPU_SET_AVD_RGR_BRIDGE_INTR_SHIFT 0 /*************************************************************************** *CPU_CLEAR - CPU interrupt Clear Register ***************************************************************************/ /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR15 [31:31] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR15_MASK 0x80000000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR15_SHIFT 31 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR14 [30:30] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR14_MASK 0x40000000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR14_SHIFT 30 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR13 [29:29] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR13_MASK 0x20000000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR13_SHIFT 29 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR12 [28:28] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR12_MASK 0x10000000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR12_SHIFT 28 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR11 [27:27] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR11_MASK 0x08000000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR11_SHIFT 27 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR10 [26:26] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR10_MASK 0x04000000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR10_SHIFT 26 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR9 [25:25] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR9_MASK 0x02000000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR9_SHIFT 25 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR8 [24:24] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR8_MASK 0x01000000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR8_SHIFT 24 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR7 [23:23] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR7_MASK 0x00800000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR7_SHIFT 23 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR6 [22:22] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR6_MASK 0x00400000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR6_SHIFT 22 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR5 [21:21] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR5_MASK 0x00200000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR5_SHIFT 21 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR4 [20:20] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR4_MASK 0x00100000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR4_SHIFT 20 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR3 [19:19] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR3_MASK 0x00080000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR3_SHIFT 19 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR2 [18:18] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR2_MASK 0x00040000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR2_SHIFT 18 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR1 [17:17] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR1_MASK 0x00020000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR1_SHIFT 17 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_SW_INTR0 [16:16] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR0_MASK 0x00010000 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_SW_INTR0_SHIFT 16 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_RSVD_HW_INTR [15:07] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_RSVD_HW_INTR_MASK 0x0000ff80 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_RSVD_HW_INTR_SHIFT 7 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_WATCHDOG_INTR [06:06] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_WATCHDOG_INTR_MASK 0x00000040 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_WATCHDOG_INTR_SHIFT 6 /* AVD_INTR2_0 :: CPU_CLEAR :: VICH_REG_INTR [05:05] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_REG_INTR_MASK 0x00000020 #define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_REG_INTR_SHIFT 5 /* AVD_INTR2_0 :: CPU_CLEAR :: VICH_SCB_WR_INTR [04:04] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_SCB_WR_INTR_MASK 0x00000010 #define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_SCB_WR_INTR_SHIFT 4 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_PFRI_INTR [03:03] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_PFRI_INTR_MASK 0x00000008 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_PFRI_INTR_SHIFT 3 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_MBOX_INTR [02:02] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_MBOX_INTR_MASK 0x00000004 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_MBOX_INTR_SHIFT 2 /* AVD_INTR2_0 :: CPU_CLEAR :: VICH_INST_RD_INTR [01:01] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_INST_RD_INTR_MASK 0x00000002 #define BCHP_AVD_INTR2_0_CPU_CLEAR_VICH_INST_RD_INTR_SHIFT 1 /* AVD_INTR2_0 :: CPU_CLEAR :: AVD_RGR_BRIDGE_INTR [00:00] */ #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 #define BCHP_AVD_INTR2_0_CPU_CLEAR_AVD_RGR_BRIDGE_INTR_SHIFT 0 /*************************************************************************** *CPU_MASK_STATUS - CPU interrupt Mask Status Register ***************************************************************************/ /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR15 [31:31] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR15_MASK 0x80000000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR15_SHIFT 31 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR14 [30:30] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR14_MASK 0x40000000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR14_SHIFT 30 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR13 [29:29] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR13_MASK 0x20000000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR13_SHIFT 29 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR12 [28:28] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR12_MASK 0x10000000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR12_SHIFT 28 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR11 [27:27] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR11_MASK 0x08000000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR11_SHIFT 27 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR10 [26:26] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR10_MASK 0x04000000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR10_SHIFT 26 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR9 [25:25] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR9_MASK 0x02000000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR9_SHIFT 25 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR8 [24:24] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR8_MASK 0x01000000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR8_SHIFT 24 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR7 [23:23] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR7_MASK 0x00800000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR7_SHIFT 23 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR6 [22:22] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR6_MASK 0x00400000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR6_SHIFT 22 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR5 [21:21] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR5_MASK 0x00200000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR5_SHIFT 21 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR4 [20:20] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR4_MASK 0x00100000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR4_SHIFT 20 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR3 [19:19] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR3_MASK 0x00080000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR3_SHIFT 19 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR2 [18:18] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR2_MASK 0x00040000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR2_SHIFT 18 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR1 [17:17] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR1_MASK 0x00020000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR1_SHIFT 17 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_SW_INTR0 [16:16] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR0_MASK 0x00010000 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_SW_INTR0_SHIFT 16 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_RSVD_HW_INTR [15:07] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_RSVD_HW_INTR_MASK 0x0000ff80 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_RSVD_HW_INTR_SHIFT 7 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_WATCHDOG_INTR [06:06] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_WATCHDOG_INTR_MASK 0x00000040 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_WATCHDOG_INTR_SHIFT 6 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: VICH_REG_INTR [05:05] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_REG_INTR_MASK 0x00000020 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_REG_INTR_SHIFT 5 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: VICH_SCB_WR_INTR [04:04] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_SCB_WR_INTR_MASK 0x00000010 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_SCB_WR_INTR_SHIFT 4 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_PFRI_INTR [03:03] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_PFRI_INTR_MASK 0x00000008 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_PFRI_INTR_SHIFT 3 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_MBOX_INTR [02:02] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_MBOX_INTR_MASK 0x00000004 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_MBOX_INTR_SHIFT 2 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: VICH_INST_RD_INTR [01:01] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_INST_RD_INTR_MASK 0x00000002 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_VICH_INST_RD_INTR_SHIFT 1 /* AVD_INTR2_0 :: CPU_MASK_STATUS :: AVD_RGR_BRIDGE_INTR [00:00] */ #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 #define BCHP_AVD_INTR2_0_CPU_MASK_STATUS_AVD_RGR_BRIDGE_INTR_SHIFT 0 /*************************************************************************** *CPU_MASK_SET - CPU interrupt Mask Set Register ***************************************************************************/ /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR15 [31:31] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR15_MASK 0x80000000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR15_SHIFT 31 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR14 [30:30] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR14_MASK 0x40000000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR14_SHIFT 30 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR13 [29:29] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR13_MASK 0x20000000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR13_SHIFT 29 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR12 [28:28] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR12_MASK 0x10000000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR12_SHIFT 28 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR11 [27:27] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR11_MASK 0x08000000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR11_SHIFT 27 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR10 [26:26] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR10_MASK 0x04000000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR10_SHIFT 26 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR9 [25:25] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR9_MASK 0x02000000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR9_SHIFT 25 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR8 [24:24] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR8_MASK 0x01000000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR8_SHIFT 24 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR7 [23:23] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR7_MASK 0x00800000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR7_SHIFT 23 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR6 [22:22] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR6_MASK 0x00400000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR6_SHIFT 22 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR5 [21:21] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR5_MASK 0x00200000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR5_SHIFT 21 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR4 [20:20] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR4_MASK 0x00100000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR4_SHIFT 20 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR3 [19:19] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR3_MASK 0x00080000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR3_SHIFT 19 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR2 [18:18] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR2_MASK 0x00040000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR2_SHIFT 18 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR1 [17:17] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR1_MASK 0x00020000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR1_SHIFT 17 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_SW_INTR0 [16:16] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR0_MASK 0x00010000 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_SW_INTR0_SHIFT 16 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_RSVD_HW_INTR [15:07] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_RSVD_HW_INTR_MASK 0x0000ff80 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_RSVD_HW_INTR_SHIFT 7 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_WATCHDOG_INTR [06:06] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_WATCHDOG_INTR_MASK 0x00000040 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_WATCHDOG_INTR_SHIFT 6 /* AVD_INTR2_0 :: CPU_MASK_SET :: VICH_REG_INTR [05:05] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_REG_INTR_MASK 0x00000020 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_REG_INTR_SHIFT 5 /* AVD_INTR2_0 :: CPU_MASK_SET :: VICH_SCB_WR_INTR [04:04] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_SCB_WR_INTR_MASK 0x00000010 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_SCB_WR_INTR_SHIFT 4 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_PFRI_INTR [03:03] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_PFRI_INTR_MASK 0x00000008 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_PFRI_INTR_SHIFT 3 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_MBOX_INTR [02:02] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_MBOX_INTR_MASK 0x00000004 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_MBOX_INTR_SHIFT 2 /* AVD_INTR2_0 :: CPU_MASK_SET :: VICH_INST_RD_INTR [01:01] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_INST_RD_INTR_MASK 0x00000002 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_VICH_INST_RD_INTR_SHIFT 1 /* AVD_INTR2_0 :: CPU_MASK_SET :: AVD_RGR_BRIDGE_INTR [00:00] */ #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 #define BCHP_AVD_INTR2_0_CPU_MASK_SET_AVD_RGR_BRIDGE_INTR_SHIFT 0 /*************************************************************************** *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register ***************************************************************************/ /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR15 [31:31] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR15_MASK 0x80000000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR15_SHIFT 31 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR14 [30:30] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR14_MASK 0x40000000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR14_SHIFT 30 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR13 [29:29] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR13_MASK 0x20000000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR13_SHIFT 29 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR12 [28:28] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR12_MASK 0x10000000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR12_SHIFT 28 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR11 [27:27] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR11_MASK 0x08000000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR11_SHIFT 27 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR10 [26:26] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR10_MASK 0x04000000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR10_SHIFT 26 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR9 [25:25] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR9_MASK 0x02000000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR9_SHIFT 25 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR8 [24:24] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR8_MASK 0x01000000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR8_SHIFT 24 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR7 [23:23] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR7_MASK 0x00800000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR7_SHIFT 23 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR6 [22:22] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR6_MASK 0x00400000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR6_SHIFT 22 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR5 [21:21] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR5_MASK 0x00200000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR5_SHIFT 21 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR4 [20:20] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR4_MASK 0x00100000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR4_SHIFT 20 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR3 [19:19] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR3_MASK 0x00080000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR3_SHIFT 19 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR2 [18:18] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR2_MASK 0x00040000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR2_SHIFT 18 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR1 [17:17] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR1_MASK 0x00020000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR1_SHIFT 17 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_SW_INTR0 [16:16] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR0_MASK 0x00010000 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_SW_INTR0_SHIFT 16 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_RSVD_HW_INTR [15:07] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_RSVD_HW_INTR_MASK 0x0000ff80 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_RSVD_HW_INTR_SHIFT 7 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_WATCHDOG_INTR [06:06] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_WATCHDOG_INTR_MASK 0x00000040 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_WATCHDOG_INTR_SHIFT 6 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: VICH_REG_INTR [05:05] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_REG_INTR_MASK 0x00000020 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_REG_INTR_SHIFT 5 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: VICH_SCB_WR_INTR [04:04] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_SCB_WR_INTR_MASK 0x00000010 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_SCB_WR_INTR_SHIFT 4 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_PFRI_INTR [03:03] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_PFRI_INTR_MASK 0x00000008 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_PFRI_INTR_SHIFT 3 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_MBOX_INTR [02:02] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_MBOX_INTR_MASK 0x00000004 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_MBOX_INTR_SHIFT 2 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: VICH_INST_RD_INTR [01:01] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_INST_RD_INTR_MASK 0x00000002 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_VICH_INST_RD_INTR_SHIFT 1 /* AVD_INTR2_0 :: CPU_MASK_CLEAR :: AVD_RGR_BRIDGE_INTR [00:00] */ #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 #define BCHP_AVD_INTR2_0_CPU_MASK_CLEAR_AVD_RGR_BRIDGE_INTR_SHIFT 0 /*************************************************************************** *PCI_STATUS - PCI interrupt Status Register ***************************************************************************/ /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR15 [31:31] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR15_MASK 0x80000000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR15_SHIFT 31 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR14 [30:30] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR14_MASK 0x40000000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR14_SHIFT 30 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR13 [29:29] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR13_MASK 0x20000000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR13_SHIFT 29 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR12 [28:28] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR12_MASK 0x10000000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR12_SHIFT 28 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR11 [27:27] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR11_MASK 0x08000000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR11_SHIFT 27 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR10 [26:26] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR10_MASK 0x04000000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR10_SHIFT 26 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR9 [25:25] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR9_MASK 0x02000000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR9_SHIFT 25 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR8 [24:24] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR8_MASK 0x01000000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR8_SHIFT 24 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR7 [23:23] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR7_MASK 0x00800000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR7_SHIFT 23 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR6 [22:22] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR6_MASK 0x00400000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR6_SHIFT 22 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR5 [21:21] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR5_MASK 0x00200000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR5_SHIFT 21 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR4 [20:20] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR4_MASK 0x00100000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR4_SHIFT 20 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR3 [19:19] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR3_MASK 0x00080000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR3_SHIFT 19 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR2 [18:18] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR2_MASK 0x00040000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR2_SHIFT 18 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR1 [17:17] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR1_MASK 0x00020000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR1_SHIFT 17 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_SW_INTR0 [16:16] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR0_MASK 0x00010000 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_SW_INTR0_SHIFT 16 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_RSVD_HW_INTR [15:07] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_RSVD_HW_INTR_MASK 0x0000ff80 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_RSVD_HW_INTR_SHIFT 7 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_WATCHDOG_INTR [06:06] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_WATCHDOG_INTR_MASK 0x00000040 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_WATCHDOG_INTR_SHIFT 6 /* AVD_INTR2_0 :: PCI_STATUS :: VICH_REG_INTR [05:05] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_REG_INTR_MASK 0x00000020 #define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_REG_INTR_SHIFT 5 /* AVD_INTR2_0 :: PCI_STATUS :: VICH_SCB_WR_INTR [04:04] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_SCB_WR_INTR_MASK 0x00000010 #define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_SCB_WR_INTR_SHIFT 4 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_PFRI_INTR [03:03] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_PFRI_INTR_MASK 0x00000008 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_PFRI_INTR_SHIFT 3 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_MBOX_INTR [02:02] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_MBOX_INTR_MASK 0x00000004 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_MBOX_INTR_SHIFT 2 /* AVD_INTR2_0 :: PCI_STATUS :: VICH_INST_RD_INTR [01:01] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_INST_RD_INTR_MASK 0x00000002 #define BCHP_AVD_INTR2_0_PCI_STATUS_VICH_INST_RD_INTR_SHIFT 1 /* AVD_INTR2_0 :: PCI_STATUS :: AVD_RGR_BRIDGE_INTR [00:00] */ #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 #define BCHP_AVD_INTR2_0_PCI_STATUS_AVD_RGR_BRIDGE_INTR_SHIFT 0 /*************************************************************************** *PCI_SET - PCI interrupt Set Register ***************************************************************************/ /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR15 [31:31] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR15_MASK 0x80000000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR15_SHIFT 31 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR14 [30:30] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR14_MASK 0x40000000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR14_SHIFT 30 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR13 [29:29] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR13_MASK 0x20000000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR13_SHIFT 29 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR12 [28:28] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR12_MASK 0x10000000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR12_SHIFT 28 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR11 [27:27] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR11_MASK 0x08000000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR11_SHIFT 27 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR10 [26:26] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR10_MASK 0x04000000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR10_SHIFT 26 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR9 [25:25] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR9_MASK 0x02000000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR9_SHIFT 25 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR8 [24:24] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR8_MASK 0x01000000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR8_SHIFT 24 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR7 [23:23] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR7_MASK 0x00800000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR7_SHIFT 23 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR6 [22:22] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR6_MASK 0x00400000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR6_SHIFT 22 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR5 [21:21] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR5_MASK 0x00200000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR5_SHIFT 21 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR4 [20:20] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR4_MASK 0x00100000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR4_SHIFT 20 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR3 [19:19] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR3_MASK 0x00080000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR3_SHIFT 19 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR2 [18:18] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR2_MASK 0x00040000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR2_SHIFT 18 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR1 [17:17] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR1_MASK 0x00020000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR1_SHIFT 17 /* AVD_INTR2_0 :: PCI_SET :: AVD_SW_INTR0 [16:16] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR0_MASK 0x00010000 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_SW_INTR0_SHIFT 16 /* AVD_INTR2_0 :: PCI_SET :: AVD_RSVD_HW_INTR [15:07] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_RSVD_HW_INTR_MASK 0x0000ff80 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_RSVD_HW_INTR_SHIFT 7 /* AVD_INTR2_0 :: PCI_SET :: AVD_WATCHDOG_INTR [06:06] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_WATCHDOG_INTR_MASK 0x00000040 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_WATCHDOG_INTR_SHIFT 6 /* AVD_INTR2_0 :: PCI_SET :: VICH_REG_INTR [05:05] */ #define BCHP_AVD_INTR2_0_PCI_SET_VICH_REG_INTR_MASK 0x00000020 #define BCHP_AVD_INTR2_0_PCI_SET_VICH_REG_INTR_SHIFT 5 /* AVD_INTR2_0 :: PCI_SET :: VICH_SCB_WR_INTR [04:04] */ #define BCHP_AVD_INTR2_0_PCI_SET_VICH_SCB_WR_INTR_MASK 0x00000010 #define BCHP_AVD_INTR2_0_PCI_SET_VICH_SCB_WR_INTR_SHIFT 4 /* AVD_INTR2_0 :: PCI_SET :: AVD_PFRI_INTR [03:03] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_PFRI_INTR_MASK 0x00000008 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_PFRI_INTR_SHIFT 3 /* AVD_INTR2_0 :: PCI_SET :: AVD_MBOX_INTR [02:02] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_MBOX_INTR_MASK 0x00000004 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_MBOX_INTR_SHIFT 2 /* AVD_INTR2_0 :: PCI_SET :: VICH_INST_RD_INTR [01:01] */ #define BCHP_AVD_INTR2_0_PCI_SET_VICH_INST_RD_INTR_MASK 0x00000002 #define BCHP_AVD_INTR2_0_PCI_SET_VICH_INST_RD_INTR_SHIFT 1 /* AVD_INTR2_0 :: PCI_SET :: AVD_RGR_BRIDGE_INTR [00:00] */ #define BCHP_AVD_INTR2_0_PCI_SET_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 #define BCHP_AVD_INTR2_0_PCI_SET_AVD_RGR_BRIDGE_INTR_SHIFT 0 /*************************************************************************** *PCI_CLEAR - PCI interrupt Clear Register ***************************************************************************/ /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR15 [31:31] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR15_MASK 0x80000000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR15_SHIFT 31 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR14 [30:30] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR14_MASK 0x40000000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR14_SHIFT 30 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR13 [29:29] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR13_MASK 0x20000000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR13_SHIFT 29 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR12 [28:28] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR12_MASK 0x10000000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR12_SHIFT 28 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR11 [27:27] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR11_MASK 0x08000000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR11_SHIFT 27 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR10 [26:26] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR10_MASK 0x04000000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR10_SHIFT 26 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR9 [25:25] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR9_MASK 0x02000000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR9_SHIFT 25 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR8 [24:24] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR8_MASK 0x01000000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR8_SHIFT 24 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR7 [23:23] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR7_MASK 0x00800000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR7_SHIFT 23 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR6 [22:22] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR6_MASK 0x00400000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR6_SHIFT 22 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR5 [21:21] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR5_MASK 0x00200000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR5_SHIFT 21 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR4 [20:20] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR4_MASK 0x00100000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR4_SHIFT 20 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR3 [19:19] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR3_MASK 0x00080000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR3_SHIFT 19 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR2 [18:18] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR2_MASK 0x00040000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR2_SHIFT 18 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR1 [17:17] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR1_MASK 0x00020000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR1_SHIFT 17 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_SW_INTR0 [16:16] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR0_MASK 0x00010000 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_SW_INTR0_SHIFT 16 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_RSVD_HW_INTR [15:07] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_RSVD_HW_INTR_MASK 0x0000ff80 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_RSVD_HW_INTR_SHIFT 7 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_WATCHDOG_INTR [06:06] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_WATCHDOG_INTR_MASK 0x00000040 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_WATCHDOG_INTR_SHIFT 6 /* AVD_INTR2_0 :: PCI_CLEAR :: VICH_REG_INTR [05:05] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_REG_INTR_MASK 0x00000020 #define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_REG_INTR_SHIFT 5 /* AVD_INTR2_0 :: PCI_CLEAR :: VICH_SCB_WR_INTR [04:04] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_SCB_WR_INTR_MASK 0x00000010 #define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_SCB_WR_INTR_SHIFT 4 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_PFRI_INTR [03:03] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_PFRI_INTR_MASK 0x00000008 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_PFRI_INTR_SHIFT 3 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_MBOX_INTR [02:02] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_MBOX_INTR_MASK 0x00000004 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_MBOX_INTR_SHIFT 2 /* AVD_INTR2_0 :: PCI_CLEAR :: VICH_INST_RD_INTR [01:01] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_INST_RD_INTR_MASK 0x00000002 #define BCHP_AVD_INTR2_0_PCI_CLEAR_VICH_INST_RD_INTR_SHIFT 1 /* AVD_INTR2_0 :: PCI_CLEAR :: AVD_RGR_BRIDGE_INTR [00:00] */ #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 #define BCHP_AVD_INTR2_0_PCI_CLEAR_AVD_RGR_BRIDGE_INTR_SHIFT 0 /*************************************************************************** *PCI_MASK_STATUS - PCI interrupt Mask Status Register ***************************************************************************/ /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR15 [31:31] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR15_MASK 0x80000000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR15_SHIFT 31 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR14 [30:30] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR14_MASK 0x40000000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR14_SHIFT 30 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR13 [29:29] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR13_MASK 0x20000000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR13_SHIFT 29 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR12 [28:28] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR12_MASK 0x10000000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR12_SHIFT 28 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR11 [27:27] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR11_MASK 0x08000000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR11_SHIFT 27 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR10 [26:26] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR10_MASK 0x04000000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR10_SHIFT 26 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR9 [25:25] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR9_MASK 0x02000000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR9_SHIFT 25 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR8 [24:24] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR8_MASK 0x01000000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR8_SHIFT 24 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR7 [23:23] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR7_MASK 0x00800000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR7_SHIFT 23 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR6 [22:22] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR6_MASK 0x00400000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR6_SHIFT 22 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR5 [21:21] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR5_MASK 0x00200000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR5_SHIFT 21 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR4 [20:20] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR4_MASK 0x00100000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR4_SHIFT 20 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR3 [19:19] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR3_MASK 0x00080000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR3_SHIFT 19 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR2 [18:18] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR2_MASK 0x00040000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR2_SHIFT 18 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR1 [17:17] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR1_MASK 0x00020000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR1_SHIFT 17 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_SW_INTR0 [16:16] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR0_MASK 0x00010000 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_SW_INTR0_SHIFT 16 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_RSVD_HW_INTR [15:07] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_RSVD_HW_INTR_MASK 0x0000ff80 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_RSVD_HW_INTR_SHIFT 7 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_WATCHDOG_INTR [06:06] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_WATCHDOG_INTR_MASK 0x00000040 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_WATCHDOG_INTR_SHIFT 6 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: VICH_REG_INTR [05:05] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_REG_INTR_MASK 0x00000020 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_REG_INTR_SHIFT 5 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: VICH_SCB_WR_INTR [04:04] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_SCB_WR_INTR_MASK 0x00000010 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_SCB_WR_INTR_SHIFT 4 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_PFRI_INTR [03:03] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_PFRI_INTR_MASK 0x00000008 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_PFRI_INTR_SHIFT 3 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_MBOX_INTR [02:02] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_MBOX_INTR_MASK 0x00000004 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_MBOX_INTR_SHIFT 2 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: VICH_INST_RD_INTR [01:01] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_INST_RD_INTR_MASK 0x00000002 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_VICH_INST_RD_INTR_SHIFT 1 /* AVD_INTR2_0 :: PCI_MASK_STATUS :: AVD_RGR_BRIDGE_INTR [00:00] */ #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 #define BCHP_AVD_INTR2_0_PCI_MASK_STATUS_AVD_RGR_BRIDGE_INTR_SHIFT 0 /*************************************************************************** *PCI_MASK_SET - PCI interrupt Mask Set Register ***************************************************************************/ /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR15 [31:31] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR15_MASK 0x80000000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR15_SHIFT 31 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR14 [30:30] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR14_MASK 0x40000000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR14_SHIFT 30 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR13 [29:29] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR13_MASK 0x20000000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR13_SHIFT 29 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR12 [28:28] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR12_MASK 0x10000000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR12_SHIFT 28 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR11 [27:27] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR11_MASK 0x08000000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR11_SHIFT 27 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR10 [26:26] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR10_MASK 0x04000000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR10_SHIFT 26 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR9 [25:25] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR9_MASK 0x02000000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR9_SHIFT 25 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR8 [24:24] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR8_MASK 0x01000000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR8_SHIFT 24 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR7 [23:23] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR7_MASK 0x00800000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR7_SHIFT 23 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR6 [22:22] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR6_MASK 0x00400000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR6_SHIFT 22 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR5 [21:21] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR5_MASK 0x00200000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR5_SHIFT 21 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR4 [20:20] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR4_MASK 0x00100000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR4_SHIFT 20 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR3 [19:19] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR3_MASK 0x00080000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR3_SHIFT 19 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR2 [18:18] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR2_MASK 0x00040000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR2_SHIFT 18 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR1 [17:17] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR1_MASK 0x00020000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR1_SHIFT 17 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_SW_INTR0 [16:16] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR0_MASK 0x00010000 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_SW_INTR0_SHIFT 16 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_RSVD_HW_INTR [15:07] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_RSVD_HW_INTR_MASK 0x0000ff80 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_RSVD_HW_INTR_SHIFT 7 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_WATCHDOG_INTR [06:06] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_WATCHDOG_INTR_MASK 0x00000040 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_WATCHDOG_INTR_SHIFT 6 /* AVD_INTR2_0 :: PCI_MASK_SET :: VICH_REG_INTR [05:05] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_REG_INTR_MASK 0x00000020 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_REG_INTR_SHIFT 5 /* AVD_INTR2_0 :: PCI_MASK_SET :: VICH_SCB_WR_INTR [04:04] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_SCB_WR_INTR_MASK 0x00000010 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_SCB_WR_INTR_SHIFT 4 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_PFRI_INTR [03:03] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_PFRI_INTR_MASK 0x00000008 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_PFRI_INTR_SHIFT 3 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_MBOX_INTR [02:02] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_MBOX_INTR_MASK 0x00000004 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_MBOX_INTR_SHIFT 2 /* AVD_INTR2_0 :: PCI_MASK_SET :: VICH_INST_RD_INTR [01:01] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_INST_RD_INTR_MASK 0x00000002 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_VICH_INST_RD_INTR_SHIFT 1 /* AVD_INTR2_0 :: PCI_MASK_SET :: AVD_RGR_BRIDGE_INTR [00:00] */ #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 #define BCHP_AVD_INTR2_0_PCI_MASK_SET_AVD_RGR_BRIDGE_INTR_SHIFT 0 /*************************************************************************** *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register ***************************************************************************/ /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR15 [31:31] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR15_MASK 0x80000000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR15_SHIFT 31 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR14 [30:30] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR14_MASK 0x40000000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR14_SHIFT 30 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR13 [29:29] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR13_MASK 0x20000000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR13_SHIFT 29 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR12 [28:28] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR12_MASK 0x10000000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR12_SHIFT 28 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR11 [27:27] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR11_MASK 0x08000000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR11_SHIFT 27 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR10 [26:26] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR10_MASK 0x04000000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR10_SHIFT 26 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR9 [25:25] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR9_MASK 0x02000000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR9_SHIFT 25 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR8 [24:24] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR8_MASK 0x01000000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR8_SHIFT 24 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR7 [23:23] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR7_MASK 0x00800000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR7_SHIFT 23 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR6 [22:22] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR6_MASK 0x00400000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR6_SHIFT 22 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR5 [21:21] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR5_MASK 0x00200000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR5_SHIFT 21 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR4 [20:20] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR4_MASK 0x00100000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR4_SHIFT 20 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR3 [19:19] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR3_MASK 0x00080000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR3_SHIFT 19 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR2 [18:18] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR2_MASK 0x00040000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR2_SHIFT 18 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR1 [17:17] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR1_MASK 0x00020000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR1_SHIFT 17 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_SW_INTR0 [16:16] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR0_MASK 0x00010000 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_SW_INTR0_SHIFT 16 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_RSVD_HW_INTR [15:07] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_RSVD_HW_INTR_MASK 0x0000ff80 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_RSVD_HW_INTR_SHIFT 7 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_WATCHDOG_INTR [06:06] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_WATCHDOG_INTR_MASK 0x00000040 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_WATCHDOG_INTR_SHIFT 6 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: VICH_REG_INTR [05:05] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_REG_INTR_MASK 0x00000020 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_REG_INTR_SHIFT 5 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: VICH_SCB_WR_INTR [04:04] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_SCB_WR_INTR_MASK 0x00000010 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_SCB_WR_INTR_SHIFT 4 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_PFRI_INTR [03:03] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_PFRI_INTR_MASK 0x00000008 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_PFRI_INTR_SHIFT 3 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_MBOX_INTR [02:02] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_MBOX_INTR_MASK 0x00000004 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_MBOX_INTR_SHIFT 2 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: VICH_INST_RD_INTR [01:01] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_INST_RD_INTR_MASK 0x00000002 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_VICH_INST_RD_INTR_SHIFT 1 /* AVD_INTR2_0 :: PCI_MASK_CLEAR :: AVD_RGR_BRIDGE_INTR [00:00] */ #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_RGR_BRIDGE_INTR_MASK 0x00000001 #define BCHP_AVD_INTR2_0_PCI_MASK_CLEAR_AVD_RGR_BRIDGE_INTR_SHIFT 0 #endif /* #ifndef BCHP_AVD_INTR2_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015000000000000011561 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_trb_top.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_trb_to0000644000175000017500000001064511610313111031035 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_trb_top.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:21p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:24 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_trb_top.h $ * * Hydra_Software_Devel/1 7/17/09 8:21p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_TRB_TOP_H__ #define BCHP_TRB_TOP_H__ /*************************************************************************** *TRB_TOP - TRB Control Registers ***************************************************************************/ #define BCHP_TRB_TOP_CTL 0x000f0000 /* TRB Control */ #define BCHP_TRB_TOP_STATUS 0x000f0004 /* TRB Status */ #define BCHP_TRB_TOP_REVISION 0x000f0008 /* TRB REVISION */ /*************************************************************************** *CTL - TRB Control ***************************************************************************/ /* TRB_TOP :: CTL :: reserved0 [31:02] */ #define BCHP_TRB_TOP_CTL_reserved0_MASK 0xfffffffc #define BCHP_TRB_TOP_CTL_reserved0_SHIFT 2 /* TRB_TOP :: CTL :: TRBOver [01:01] */ #define BCHP_TRB_TOP_CTL_TRBOver_MASK 0x00000002 #define BCHP_TRB_TOP_CTL_TRBOver_SHIFT 1 /* TRB_TOP :: CTL :: TRBEna [00:00] */ #define BCHP_TRB_TOP_CTL_TRBEna_MASK 0x00000001 #define BCHP_TRB_TOP_CTL_TRBEna_SHIFT 0 /*************************************************************************** *STATUS - TRB Status ***************************************************************************/ /* TRB_TOP :: STATUS :: reserved0 [31:01] */ #define BCHP_TRB_TOP_STATUS_reserved0_MASK 0xfffffffe #define BCHP_TRB_TOP_STATUS_reserved0_SHIFT 1 /* TRB_TOP :: STATUS :: ErrSeen [00:00] */ #define BCHP_TRB_TOP_STATUS_ErrSeen_MASK 0x00000001 #define BCHP_TRB_TOP_STATUS_ErrSeen_SHIFT 0 /*************************************************************************** *REVISION - TRB REVISION ***************************************************************************/ /* TRB_TOP :: REVISION :: reserved0 [31:16] */ #define BCHP_TRB_TOP_REVISION_reserved0_MASK 0xffff0000 #define BCHP_TRB_TOP_REVISION_reserved0_SHIFT 16 /* TRB_TOP :: REVISION :: MAJOR [15:08] */ #define BCHP_TRB_TOP_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_TRB_TOP_REVISION_MAJOR_SHIFT 8 /* TRB_TOP :: REVISION :: MINOR [07:00] */ #define BCHP_TRB_TOP_REVISION_MINOR_MASK 0x000000ff #define BCHP_TRB_TOP_REVISION_MINOR_SHIFT 0 #endif /* #ifndef BCHP_TRB_TOP_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016200000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_2.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rt0000644000175000017500000000664611610313111031051 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_rts_l2_regs_2.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:17p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:20 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_2.h $ * * Hydra_Software_Devel/1 7/17/09 8:17p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_RTS_L2_REGS_2_H__ #define BCHP_PRI_RTS_L2_REGS_2_H__ /*************************************************************************** *PRI_RTS_L2_REGS_2 - PRIMARY_ARB_CLIENTS L2 (Mips) rts interrupt controller 2 registers ***************************************************************************/ #define BCHP_PRI_RTS_L2_REGS_2_CPU_STATUS 0x0040c500 /* CPU interrupt Status Register */ #define BCHP_PRI_RTS_L2_REGS_2_CPU_SET 0x0040c504 /* CPU interrupt Set Register */ #define BCHP_PRI_RTS_L2_REGS_2_CPU_CLEAR 0x0040c508 /* CPU interrupt Clear Register */ #define BCHP_PRI_RTS_L2_REGS_2_CPU_MASK_STATUS 0x0040c50c /* CPU interrupt Mask Status Register */ #define BCHP_PRI_RTS_L2_REGS_2_CPU_MASK_SET 0x0040c510 /* CPU interrupt Mask Set Register */ #define BCHP_PRI_RTS_L2_REGS_2_CPU_MASK_CLEAR 0x0040c514 /* CPU interrupt Mask Clear Register */ #define BCHP_PRI_RTS_L2_REGS_2_PCI_STATUS 0x0040c518 /* PCI interrupt Status Register */ #define BCHP_PRI_RTS_L2_REGS_2_PCI_SET 0x0040c51c /* PCI interrupt Set Register */ #define BCHP_PRI_RTS_L2_REGS_2_PCI_CLEAR 0x0040c520 /* PCI interrupt Clear Register */ #define BCHP_PRI_RTS_L2_REGS_2_PCI_MASK_STATUS 0x0040c524 /* PCI interrupt Mask Status Register */ #define BCHP_PRI_RTS_L2_REGS_2_PCI_MASK_SET 0x0040c528 /* PCI interrupt Mask Set Register */ #define BCHP_PRI_RTS_L2_REGS_2_PCI_MASK_CLEAR 0x0040c52c /* PCI interrupt Mask Clear Register */ #endif /* #ifndef BCHP_PRI_RTS_L2_REGS_2_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015400000000000011565 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_irq0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id0000644000175000017500000001010511610313111031001 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_int_id_irq0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:08p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:38 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility unknown * RDB Parser 3.0 * generate_int_id.pl 1.0 * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_irq0.h $ * * Hydra_Software_Devel/1 7/17/09 8:08p albertl * PR56880: Initial revision. * ***************************************************************************/ #include "bchp.h" #include "bchp_irq0.h" #ifndef BCHP_INT_ID_IRQ0_H__ #define BCHP_INT_ID_IRQ0_H__ #define BCHP_INT_ID_gio_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_gio_irqen_SHIFT) #define BCHP_INT_ID_icap_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_icap_irqen_SHIFT) #define BCHP_INT_ID_iica_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_iica_irqen_SHIFT) #define BCHP_INT_ID_iicb_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT) #define BCHP_INT_ID_iicc_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT) #define BCHP_INT_ID_iicd_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT) #define BCHP_INT_ID_iice_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_iice_irqen_SHIFT) #define BCHP_INT_ID_kbd1_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_kbd1_irqen_SHIFT) #define BCHP_INT_ID_ldk_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_ldk_irqen_SHIFT) #define BCHP_INT_ID_spi_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_spi_irqen_SHIFT) #define BCHP_INT_ID_ua_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_ua_irqen_SHIFT) #define BCHP_INT_ID_uarta_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT) #define BCHP_INT_ID_uartb_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT) #define BCHP_INT_ID_uartc_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT) #define BCHP_INT_ID_uartd_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uartd_irqen_SHIFT) #define BCHP_INT_ID_ub_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_ub_irqen_SHIFT) #define BCHP_INT_ID_uc_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_uc_irqen_SHIFT) #define BCHP_INT_ID_ud_irqen BCHP_INT_ID_CREATE(BCHP_IRQ0_IRQEN, BCHP_IRQ0_IRQEN_ud_irqen_SHIFT) #endif /* #ifndef BCHP_INT_ID_IRQ0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015000000000000011561 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dma.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dm0000644000175000017500000001707211610313111031003 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_mem_dma.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:10p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:25 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dma.h $ * * Hydra_Software_Devel/1 7/17/09 8:10p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_MEM_DMA_H__ #define BCHP_MEM_DMA_H__ /*************************************************************************** *MEM_DMA - MEM_DMA Registers ***************************************************************************/ #define BCHP_MEM_DMA_REVISION 0x000f5000 /* MEM_DMA REVISION */ #define BCHP_MEM_DMA_FIRST_DESC 0x000f5004 /* MEM_DMA First Descriptor Address Register */ #define BCHP_MEM_DMA_CTRL 0x000f5008 /* MEM_DMA Control Register */ #define BCHP_MEM_DMA_WAKE_CTRL 0x000f500c /* MEM_DMA Wake Control Register */ #define BCHP_MEM_DMA_STATUS 0x000f5014 /* MEM_DMA Status Register */ #define BCHP_MEM_DMA_CUR_DESC 0x000f5018 /* MEM_DMA Current Descriptor Address Register */ #define BCHP_MEM_DMA_CUR_BYTE 0x000f501c /* MEM_DMA Current Byte Count Register */ #define BCHP_MEM_DMA_SCRATCH 0x000f5024 /* MEM_DMA Scratch Register */ /*************************************************************************** *REVISION - MEM_DMA REVISION ***************************************************************************/ /* MEM_DMA :: REVISION :: reserved0 [31:16] */ #define BCHP_MEM_DMA_REVISION_reserved0_MASK 0xffff0000 #define BCHP_MEM_DMA_REVISION_reserved0_SHIFT 16 /* MEM_DMA :: REVISION :: MAJOR [15:08] */ #define BCHP_MEM_DMA_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_MEM_DMA_REVISION_MAJOR_SHIFT 8 /* MEM_DMA :: REVISION :: MINOR [07:00] */ #define BCHP_MEM_DMA_REVISION_MINOR_MASK 0x000000ff #define BCHP_MEM_DMA_REVISION_MINOR_SHIFT 0 /*************************************************************************** *FIRST_DESC - MEM_DMA First Descriptor Address Register ***************************************************************************/ /* MEM_DMA :: FIRST_DESC :: ADDR [31:00] */ #define BCHP_MEM_DMA_FIRST_DESC_ADDR_MASK 0xffffffff #define BCHP_MEM_DMA_FIRST_DESC_ADDR_SHIFT 0 /*************************************************************************** *CTRL - MEM_DMA Control Register ***************************************************************************/ /* MEM_DMA :: CTRL :: reserved0 [31:01] */ #define BCHP_MEM_DMA_CTRL_reserved0_MASK 0xfffffffe #define BCHP_MEM_DMA_CTRL_reserved0_SHIFT 1 /* MEM_DMA :: CTRL :: RUN [00:00] */ #define BCHP_MEM_DMA_CTRL_RUN_MASK 0x00000001 #define BCHP_MEM_DMA_CTRL_RUN_SHIFT 0 /*************************************************************************** *WAKE_CTRL - MEM_DMA Wake Control Register ***************************************************************************/ /* MEM_DMA :: WAKE_CTRL :: reserved0 [31:02] */ #define BCHP_MEM_DMA_WAKE_CTRL_reserved0_MASK 0xfffffffc #define BCHP_MEM_DMA_WAKE_CTRL_reserved0_SHIFT 2 /* MEM_DMA :: WAKE_CTRL :: WAKE_MODE [01:01] */ #define BCHP_MEM_DMA_WAKE_CTRL_WAKE_MODE_MASK 0x00000002 #define BCHP_MEM_DMA_WAKE_CTRL_WAKE_MODE_SHIFT 1 /* MEM_DMA :: WAKE_CTRL :: WAKE [00:00] */ #define BCHP_MEM_DMA_WAKE_CTRL_WAKE_MASK 0x00000001 #define BCHP_MEM_DMA_WAKE_CTRL_WAKE_SHIFT 0 /*************************************************************************** *STATUS - MEM_DMA Status Register ***************************************************************************/ /* MEM_DMA :: STATUS :: reserved0 [31:02] */ #define BCHP_MEM_DMA_STATUS_reserved0_MASK 0xfffffffc #define BCHP_MEM_DMA_STATUS_reserved0_SHIFT 2 /* MEM_DMA :: STATUS :: DMA_STATUS [01:00] */ #define BCHP_MEM_DMA_STATUS_DMA_STATUS_MASK 0x00000003 #define BCHP_MEM_DMA_STATUS_DMA_STATUS_SHIFT 0 #define BCHP_MEM_DMA_STATUS_DMA_STATUS_Idle 0 #define BCHP_MEM_DMA_STATUS_DMA_STATUS_Busy 1 #define BCHP_MEM_DMA_STATUS_DMA_STATUS_Sleep 2 #define BCHP_MEM_DMA_STATUS_DMA_STATUS_Reserved 3 /*************************************************************************** *CUR_DESC - MEM_DMA Current Descriptor Address Register ***************************************************************************/ /* MEM_DMA :: CUR_DESC :: ADDR [31:00] */ #define BCHP_MEM_DMA_CUR_DESC_ADDR_MASK 0xffffffff #define BCHP_MEM_DMA_CUR_DESC_ADDR_SHIFT 0 /*************************************************************************** *CUR_BYTE - MEM_DMA Current Byte Count Register ***************************************************************************/ /* MEM_DMA :: CUR_BYTE :: reserved0 [31:25] */ #define BCHP_MEM_DMA_CUR_BYTE_reserved0_MASK 0xfe000000 #define BCHP_MEM_DMA_CUR_BYTE_reserved0_SHIFT 25 /* MEM_DMA :: CUR_BYTE :: COUNT [24:00] */ #define BCHP_MEM_DMA_CUR_BYTE_COUNT_MASK 0x01ffffff #define BCHP_MEM_DMA_CUR_BYTE_COUNT_SHIFT 0 /*************************************************************************** *SCRATCH - MEM_DMA Scratch Register ***************************************************************************/ /* MEM_DMA :: SCRATCH :: SCRATCH_BIT [31:00] */ #define BCHP_MEM_DMA_SCRATCH_SCRATCH_BIT_MASK 0xffffffff #define BCHP_MEM_DMA_SCRATCH_SCRATCH_BIT_SHIFT 0 #endif /* #ifndef BCHP_MEM_DMA_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015600000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_wprd_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000001020711610313111030761 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_wprd_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:06p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:10 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_wprd_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:06p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_WPRD_0_H__ #define BCHP_DECODE_WPRD_0_H__ /*************************************************************************** *DECODE_WPRD_0 ***************************************************************************/ #define BCHP_DECODE_WPRD_0_REG_WPRD_CTL 0x00800340 /* Weighted Prediction Control */ #define BCHP_DECODE_WPRD_0_REG_WPRD_END 0x0080035c /* REG_WPRD_END */ /*************************************************************************** *REG_WPRD_CTL - Weighted Prediction Control ***************************************************************************/ /* DECODE_WPRD_0 :: REG_WPRD_CTL :: reserved0 [31:15] */ #define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_reserved0_MASK 0xffff8000 #define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_reserved0_SHIFT 15 /* DECODE_WPRD_0 :: REG_WPRD_CTL :: ChromaDenom [14:12] */ #define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_ChromaDenom_MASK 0x00007000 #define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_ChromaDenom_SHIFT 12 /* DECODE_WPRD_0 :: REG_WPRD_CTL :: reserved1 [11:11] */ #define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_reserved1_MASK 0x00000800 #define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_reserved1_SHIFT 11 /* DECODE_WPRD_0 :: REG_WPRD_CTL :: LumDenom [10:08] */ #define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_LumDenom_MASK 0x00000700 #define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_LumDenom_SHIFT 8 /* DECODE_WPRD_0 :: REG_WPRD_CTL :: reserved2 [07:02] */ #define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_reserved2_MASK 0x000000fc #define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_reserved2_SHIFT 2 /* DECODE_WPRD_0 :: REG_WPRD_CTL :: PredType [01:00] */ #define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_PredType_MASK 0x00000003 #define BCHP_DECODE_WPRD_0_REG_WPRD_CTL_PredType_SHIFT 0 /*************************************************************************** *REG_WPRD_END - REG_WPRD_END ***************************************************************************/ /* DECODE_WPRD_0 :: REG_WPRD_END :: reserved0 [31:00] */ #define BCHP_DECODE_WPRD_0_REG_WPRD_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_WPRD_0_REG_WPRD_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_WPRD_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016200000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudmem2_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000455711610313111030774 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_cpudmem2_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:01p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:29 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudmem2_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:01p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_CPUDMEM2_0_H__ #define BCHP_DECODE_CPUDMEM2_0_H__ /*************************************************************************** *DECODE_CPUDMEM2_0 ***************************************************************************/ #define BCHP_DECODE_CPUDMEM2_0_CPUDMEM_REG 0x00858000 /* CPUDMEM_REG */ #define BCHP_DECODE_CPUDMEM2_0_CPUDMEM_END 0x0085fffc /* CPUDMEM_END */ #endif /* #ifndef BCHP_DECODE_CPUDMEM2_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016000000000000011562 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dmamem_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000612611610313111030766 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_dmamem_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:03p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:13 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dmamem_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:03p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_DMAMEM_0_H__ #define BCHP_DECODE_DMAMEM_0_H__ /*************************************************************************** *DECODE_DMAMEM_0 ***************************************************************************/ #define BCHP_DECODE_DMAMEM_0_DMA_MEM 0x00801a00 /* DMA_MEM */ #define BCHP_DECODE_DMAMEM_0_DMA_MEM_END 0x008021fc /* REGION_END */ /*************************************************************************** *DMA_MEM - DMA_MEM ***************************************************************************/ /* DECODE_DMAMEM_0 :: DMA_MEM :: Data [31:00] */ #define BCHP_DECODE_DMAMEM_0_DMA_MEM_Data_MASK 0xffffffff #define BCHP_DECODE_DMAMEM_0_DMA_MEM_Data_SHIFT 0 /*************************************************************************** *DMA_MEM_END - REGION_END ***************************************************************************/ /* DECODE_DMAMEM_0 :: DMA_MEM_END :: reserved0 [31:00] */ #define BCHP_DECODE_DMAMEM_0_DMA_MEM_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_DMAMEM_0_DMA_MEM_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_DMAMEM_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015500000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_timer.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id0000644000175000017500000000520111610313111031002 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_int_id_timer.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:08p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:39 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility unknown * RDB Parser 3.0 * generate_int_id.pl 1.0 * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_timer.h $ * * Hydra_Software_Devel/1 7/17/09 8:08p albertl * PR56880: Initial revision. * ***************************************************************************/ #include "bchp.h" #include "bchp_timer.h" #ifndef BCHP_INT_ID_TIMER_H__ #define BCHP_INT_ID_TIMER_H__ #define BCHP_INT_ID_TMR0TO BCHP_INT_ID_CREATE(BCHP_TIMER_TIMER_IS, BCHP_TIMER_TIMER_IS_TMR0TO_SHIFT) #define BCHP_INT_ID_TMR1TO BCHP_INT_ID_CREATE(BCHP_TIMER_TIMER_IS, BCHP_TIMER_TIMER_IS_TMR1TO_SHIFT) #define BCHP_INT_ID_TMR2TO BCHP_INT_ID_CREATE(BCHP_TIMER_TIMER_IS, BCHP_TIMER_TIMER_IS_TMR2TO_SHIFT) #define BCHP_INT_ID_TMR3TO BCHP_INT_ID_CREATE(BCHP_TIMER_TIMER_IS, BCHP_TIMER_TIMER_IS_TMR3TO_SHIFT) #define BCHP_INT_ID_WDINT BCHP_INT_ID_CREATE(BCHP_TIMER_TIMER_IS, BCHP_TIMER_TIMER_IS_WDINT_SHIFT) #endif /* #ifndef BCHP_INT_ID_TIMER_H__ */ /* End of File */ crystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mfd.h0000644000175000017500000016003411610313111030536 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_mfd.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:11p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:31 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_mfd.h $ * * Hydra_Software_Devel/1 7/17/09 8:11p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_MFD_H__ #define BCHP_MFD_H__ /*************************************************************************** *MFD - MPEG Feeder Registers ***************************************************************************/ #define BCHP_MFD_REVISION_ID 0x00540000 /* MPEG/Video Feeder Revision Register */ #define BCHP_MFD_FEEDER_CNTL 0x00540004 /* MPEG/Video Feeder Control Register */ #define BCHP_MFD_FIXED_COLOUR 0x00540008 /* MPEG/Video Feeder Fixed Colour Value Register */ #define BCHP_MFD_LAC_CNTL 0x0054000c /* MPEG/Video Feeder LAC Control Register */ #define BCHP_MFD_STRIDE 0x00540010 /* MPEG/Video Feeder Stride Register */ #define BCHP_MFD_DISP_HSIZE 0x00540014 /* MPEG/Video Feeder Horizontal Display Size Register */ #define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW 0x00540018 /* MPEG/Video Feeder Display Vertical Window Register */ #define BCHP_MFD_PICTURE0_LINE_ADDR_0 0x0054001c /* MPEG/Video Feeder Line Address0 Register */ #define BCHP_MFD_PICTURE0_LINE_ADDR_1 0x00540020 /* MPEG/Video Feeder Line Address1 Register */ #define BCHP_MFD_CHROMA_SAMPLING_CNTL 0x00540024 /* MPEG Feeder Chroma Sampling Control Register */ #define BCHP_MFD_LUMA_NMBY 0x00540028 /* MPEG Feeder Luma NMBY Size Register */ #define BCHP_MFD_CHROMA_NMBY 0x0054002c /* MPEG Feeder Chroma NMBY Size Register */ #define BCHP_MFD_PIC_FEED_CMD 0x00540030 /* MPEG/Video Feeder Picture Feed Command Register */ #define BCHP_MFD_CRC_CTRL 0x00540034 /* MPEG/Video Feeder CRC Control Register */ #define BCHP_MFD_CRC_SEED 0x00540038 /* MPEG/Video Feeder CRC Seed Register */ #define BCHP_MFD_LUMA_CRC 0x0054003c /* MPEG/Video Feeder Luma CRC Register */ #define BCHP_MFD_CHROMA_CRC 0x00540040 /* MPEG/Video Feeder Chroma CRC Register */ #define BCHP_MFD_DATA_MODE 0x00540044 /* MPEG/Video Feeder Data Mode Register */ #define BCHP_MFD_PIC_OFFSET 0x00540048 /* MPEG/Video Feeder Picture Offset Register */ #define BCHP_MFD_RANGE_EXP_REMAP_CNTL 0x0054004c /* MPEG/Video Feeder Range Expansion / Remapping Control Register */ #define BCHP_MFD_FEED_STATUS 0x00540050 /* MPEG/Video Feeder Feed Status Register */ #define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_0 0x00540054 /* MPEG/Video Feeder Line Address Computer Line Address0 Register */ #define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_1 0x00540058 /* MPEG/Video Feeder Line Address Computer Line Address1 Register */ #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG 0x0054005c /* MPEG/Video Feeder Line Address Computer Chroma Vertical Filter Configuration Register */ #define BCHP_MFD_LAC_LINE_FEED_CNTL 0x00540060 /* MPEG/Video Feeder Line Address Computer Line Feed Control Register */ #define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL 0x00540064 /* MPEG/Video Feeder Timeout and Repeat Picture Control Register */ #define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL 0x00540068 /* MPEG/Video Feeder BVB Receiver Stall Timeout Control Register */ #define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS 0x0054006c /* MPEG/Video Feeder Error Interrupt Status Register */ #define BCHP_MFD_FEEDER_BVB_STATUS 0x00540070 /* MPEG/Video Feeder BVB Status Register */ #define BCHP_MFD_TEST_MODE_CNTL 0x00540074 /* MPEG/Video Feeder Test Mode Control Register */ #define BCHP_MFD_BVB_SAMPLE_DATA 0x00540078 /* MPEG/Video Feeder BVB Output Sample Data Register */ #define BCHP_MFD_TEST_PORT_CNTL 0x0054007c /* MPEG/Video Feeder Test port Control Register */ #define BCHP_MFD_TEST_PORT_DATA 0x00540080 /* MPEG/Video Feeder Test port Data Register */ #define BCHP_MFD_SCRATCH_REGISTER_0 0x005400f8 /* MPEG/Video Feeder Scratch 0 Register */ #define BCHP_MFD_SCRATCH_REGISTER_1 0x005400fc /* MPEG/Video Feeder Scratch 1 Register */ /*************************************************************************** *REVISION_ID - MPEG/Video Feeder Revision Register ***************************************************************************/ /* MFD :: REVISION_ID :: reserved0 [31:16] */ #define BCHP_MFD_REVISION_ID_reserved0_MASK 0xffff0000 #define BCHP_MFD_REVISION_ID_reserved0_SHIFT 16 /* MFD :: REVISION_ID :: MAJOR [15:08] */ #define BCHP_MFD_REVISION_ID_MAJOR_MASK 0x0000ff00 #define BCHP_MFD_REVISION_ID_MAJOR_SHIFT 8 /* MFD :: REVISION_ID :: MINOR [07:00] */ #define BCHP_MFD_REVISION_ID_MINOR_MASK 0x000000ff #define BCHP_MFD_REVISION_ID_MINOR_SHIFT 0 /*************************************************************************** *FEEDER_CNTL - MPEG/Video Feeder Control Register ***************************************************************************/ /* MFD :: FEEDER_CNTL :: reserved0 [31:04] */ #define BCHP_MFD_FEEDER_CNTL_reserved0_MASK 0xfffffff0 #define BCHP_MFD_FEEDER_CNTL_reserved0_SHIFT 4 /* MFD :: FEEDER_CNTL :: FIXED_COLOUR_ENABLE [03:03] */ #define BCHP_MFD_FEEDER_CNTL_FIXED_COLOUR_ENABLE_MASK 0x00000008 #define BCHP_MFD_FEEDER_CNTL_FIXED_COLOUR_ENABLE_SHIFT 3 #define BCHP_MFD_FEEDER_CNTL_FIXED_COLOUR_ENABLE_OFF 0 #define BCHP_MFD_FEEDER_CNTL_FIXED_COLOUR_ENABLE_ON 1 /* MFD :: FEEDER_CNTL :: PACKING_TYPE [02:01] */ #define BCHP_MFD_FEEDER_CNTL_PACKING_TYPE_MASK 0x00000006 #define BCHP_MFD_FEEDER_CNTL_PACKING_TYPE_SHIFT 1 #define BCHP_MFD_FEEDER_CNTL_PACKING_TYPE_U0_Y0_V0_Y1 0 #define BCHP_MFD_FEEDER_CNTL_PACKING_TYPE_V0_Y0_U0_Y1 1 #define BCHP_MFD_FEEDER_CNTL_PACKING_TYPE_Y0_U0_Y1_V0 2 #define BCHP_MFD_FEEDER_CNTL_PACKING_TYPE_Y0_V0_Y1_U0 3 /* MFD :: FEEDER_CNTL :: IMAGE_FORMAT [00:00] */ #define BCHP_MFD_FEEDER_CNTL_IMAGE_FORMAT_MASK 0x00000001 #define BCHP_MFD_FEEDER_CNTL_IMAGE_FORMAT_SHIFT 0 #define BCHP_MFD_FEEDER_CNTL_IMAGE_FORMAT_AVC_MPEG 0 #define BCHP_MFD_FEEDER_CNTL_IMAGE_FORMAT_PACKED 1 /*************************************************************************** *FIXED_COLOUR - MPEG/Video Feeder Fixed Colour Value Register ***************************************************************************/ /* MFD :: FIXED_COLOUR :: reserved0 [31:24] */ #define BCHP_MFD_FIXED_COLOUR_reserved0_MASK 0xff000000 #define BCHP_MFD_FIXED_COLOUR_reserved0_SHIFT 24 /* MFD :: FIXED_COLOUR :: LUMA [23:16] */ #define BCHP_MFD_FIXED_COLOUR_LUMA_MASK 0x00ff0000 #define BCHP_MFD_FIXED_COLOUR_LUMA_SHIFT 16 /* MFD :: FIXED_COLOUR :: CB [15:08] */ #define BCHP_MFD_FIXED_COLOUR_CB_MASK 0x0000ff00 #define BCHP_MFD_FIXED_COLOUR_CB_SHIFT 8 /* MFD :: FIXED_COLOUR :: CR [07:00] */ #define BCHP_MFD_FIXED_COLOUR_CR_MASK 0x000000ff #define BCHP_MFD_FIXED_COLOUR_CR_SHIFT 0 /*************************************************************************** *LAC_CNTL - MPEG/Video Feeder LAC Control Register ***************************************************************************/ /* MFD :: LAC_CNTL :: reserved0 [31:11] */ #define BCHP_MFD_LAC_CNTL_reserved0_MASK 0xfffff800 #define BCHP_MFD_LAC_CNTL_reserved0_SHIFT 11 /* MFD :: LAC_CNTL :: STRIPE_WIDTH_SEL [10:10] */ #define BCHP_MFD_LAC_CNTL_STRIPE_WIDTH_SEL_MASK 0x00000400 #define BCHP_MFD_LAC_CNTL_STRIPE_WIDTH_SEL_SHIFT 10 #define BCHP_MFD_LAC_CNTL_STRIPE_WIDTH_SEL_BYTES_64 0 #define BCHP_MFD_LAC_CNTL_STRIPE_WIDTH_SEL_BYTES_128 1 /* MFD :: LAC_CNTL :: SKIP_LINE_SIZE [09:06] */ #define BCHP_MFD_LAC_CNTL_SKIP_LINE_SIZE_MASK 0x000003c0 #define BCHP_MFD_LAC_CNTL_SKIP_LINE_SIZE_SHIFT 6 /* MFD :: LAC_CNTL :: reserved1 [05:05] */ #define BCHP_MFD_LAC_CNTL_reserved1_MASK 0x00000020 #define BCHP_MFD_LAC_CNTL_reserved1_SHIFT 5 /* MFD :: LAC_CNTL :: CHROMA_VERT_POSITION [04:04] */ #define BCHP_MFD_LAC_CNTL_CHROMA_VERT_POSITION_MASK 0x00000010 #define BCHP_MFD_LAC_CNTL_CHROMA_VERT_POSITION_SHIFT 4 #define BCHP_MFD_LAC_CNTL_CHROMA_VERT_POSITION_COLOCATED_WITH_LUMA 0 #define BCHP_MFD_LAC_CNTL_CHROMA_VERT_POSITION_HALF_PIXEL_GRID_BETWEEN_LUMA 1 /* MFD :: LAC_CNTL :: CHROMA_INTERPOLATION [03:03] */ #define BCHP_MFD_LAC_CNTL_CHROMA_INTERPOLATION_MASK 0x00000008 #define BCHP_MFD_LAC_CNTL_CHROMA_INTERPOLATION_SHIFT 3 #define BCHP_MFD_LAC_CNTL_CHROMA_INTERPOLATION_FIELD 0 #define BCHP_MFD_LAC_CNTL_CHROMA_INTERPOLATION_FRAME 1 /* MFD :: LAC_CNTL :: OUTPUT_FIELD_POLARITY [02:02] */ #define BCHP_MFD_LAC_CNTL_OUTPUT_FIELD_POLARITY_MASK 0x00000004 #define BCHP_MFD_LAC_CNTL_OUTPUT_FIELD_POLARITY_SHIFT 2 #define BCHP_MFD_LAC_CNTL_OUTPUT_FIELD_POLARITY_TOP 0 #define BCHP_MFD_LAC_CNTL_OUTPUT_FIELD_POLARITY_BOTTOM 1 /* MFD :: LAC_CNTL :: OUTPUT_TYPE [01:01] */ #define BCHP_MFD_LAC_CNTL_OUTPUT_TYPE_MASK 0x00000002 #define BCHP_MFD_LAC_CNTL_OUTPUT_TYPE_SHIFT 1 #define BCHP_MFD_LAC_CNTL_OUTPUT_TYPE_INTERLACED 0 #define BCHP_MFD_LAC_CNTL_OUTPUT_TYPE_PROGRESSIVE 1 /* MFD :: LAC_CNTL :: CHROMA_TYPE [00:00] */ #define BCHP_MFD_LAC_CNTL_CHROMA_TYPE_MASK 0x00000001 #define BCHP_MFD_LAC_CNTL_CHROMA_TYPE_SHIFT 0 #define BCHP_MFD_LAC_CNTL_CHROMA_TYPE_CHROMA_420 0 #define BCHP_MFD_LAC_CNTL_CHROMA_TYPE_CHROMA_422 1 /*************************************************************************** *STRIDE - MPEG/Video Feeder Stride Register ***************************************************************************/ /* union - case AVC_MPEG [31:00] */ /* MFD :: STRIDE :: AVC_MPEG :: CHROMA_LINE_STRIDE [31:16] */ #define BCHP_MFD_STRIDE_AVC_MPEG_CHROMA_LINE_STRIDE_MASK 0xffff0000 #define BCHP_MFD_STRIDE_AVC_MPEG_CHROMA_LINE_STRIDE_SHIFT 16 /* MFD :: STRIDE :: AVC_MPEG :: LUMA_LINE_STRIDE [15:00] */ #define BCHP_MFD_STRIDE_AVC_MPEG_LUMA_LINE_STRIDE_MASK 0x0000ffff #define BCHP_MFD_STRIDE_AVC_MPEG_LUMA_LINE_STRIDE_SHIFT 0 /* union - case PACKED [31:00] */ /* MFD :: STRIDE :: PACKED :: reserved0 [31:16] */ #define BCHP_MFD_STRIDE_PACKED_reserved0_MASK 0xffff0000 #define BCHP_MFD_STRIDE_PACKED_reserved0_SHIFT 16 /* MFD :: STRIDE :: PACKED :: LINE_STRIDE [15:00] */ #define BCHP_MFD_STRIDE_PACKED_LINE_STRIDE_MASK 0x0000ffff #define BCHP_MFD_STRIDE_PACKED_LINE_STRIDE_SHIFT 0 /*************************************************************************** *DISP_HSIZE - MPEG/Video Feeder Horizontal Display Size Register ***************************************************************************/ /* MFD :: DISP_HSIZE :: reserved0 [31:13] */ #define BCHP_MFD_DISP_HSIZE_reserved0_MASK 0xffffe000 #define BCHP_MFD_DISP_HSIZE_reserved0_SHIFT 13 /* MFD :: DISP_HSIZE :: VALUE [12:00] */ #define BCHP_MFD_DISP_HSIZE_VALUE_MASK 0x00001fff #define BCHP_MFD_DISP_HSIZE_VALUE_SHIFT 0 /*************************************************************************** *PICTURE0_DISP_VERT_WINDOW - MPEG/Video Feeder Display Vertical Window Register ***************************************************************************/ /* MFD :: PICTURE0_DISP_VERT_WINDOW :: reserved0 [31:29] */ #define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_reserved0_MASK 0xe0000000 #define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_reserved0_SHIFT 29 /* MFD :: PICTURE0_DISP_VERT_WINDOW :: START [28:16] */ #define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_START_MASK 0x1fff0000 #define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_START_SHIFT 16 /* MFD :: PICTURE0_DISP_VERT_WINDOW :: reserved1 [15:13] */ #define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_reserved1_MASK 0x0000e000 #define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_reserved1_SHIFT 13 /* MFD :: PICTURE0_DISP_VERT_WINDOW :: END [12:00] */ #define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_END_MASK 0x00001fff #define BCHP_MFD_PICTURE0_DISP_VERT_WINDOW_END_SHIFT 0 /*************************************************************************** *PICTURE0_LINE_ADDR_0 - MPEG/Video Feeder Line Address0 Register ***************************************************************************/ /* union - case AVC_MPEG [31:00] */ /* MFD :: PICTURE0_LINE_ADDR_0 :: AVC_MPEG :: LUMA_ADDR [31:00] */ #define BCHP_MFD_PICTURE0_LINE_ADDR_0_AVC_MPEG_LUMA_ADDR_MASK 0xffffffff #define BCHP_MFD_PICTURE0_LINE_ADDR_0_AVC_MPEG_LUMA_ADDR_SHIFT 0 /* union - case PACKED [31:00] */ /* MFD :: PICTURE0_LINE_ADDR_0 :: PACKED :: LUMA_CHROMA_ADDR [31:00] */ #define BCHP_MFD_PICTURE0_LINE_ADDR_0_PACKED_LUMA_CHROMA_ADDR_MASK 0xffffffff #define BCHP_MFD_PICTURE0_LINE_ADDR_0_PACKED_LUMA_CHROMA_ADDR_SHIFT 0 /*************************************************************************** *PICTURE0_LINE_ADDR_1 - MPEG/Video Feeder Line Address1 Register ***************************************************************************/ /* union - case AVC_MPEG [31:00] */ /* MFD :: PICTURE0_LINE_ADDR_1 :: AVC_MPEG :: CHROMA_ADDR [31:00] */ #define BCHP_MFD_PICTURE0_LINE_ADDR_1_AVC_MPEG_CHROMA_ADDR_MASK 0xffffffff #define BCHP_MFD_PICTURE0_LINE_ADDR_1_AVC_MPEG_CHROMA_ADDR_SHIFT 0 /* union - case PACKED [31:00] */ /* MFD :: PICTURE0_LINE_ADDR_1 :: PACKED :: reserved0 [31:00] */ #define BCHP_MFD_PICTURE0_LINE_ADDR_1_PACKED_reserved0_MASK 0xffffffff #define BCHP_MFD_PICTURE0_LINE_ADDR_1_PACKED_reserved0_SHIFT 0 /*************************************************************************** *CHROMA_SAMPLING_CNTL - MPEG Feeder Chroma Sampling Control Register ***************************************************************************/ /* MFD :: CHROMA_SAMPLING_CNTL :: reserved0 [31:01] */ #define BCHP_MFD_CHROMA_SAMPLING_CNTL_reserved0_MASK 0xfffffffe #define BCHP_MFD_CHROMA_SAMPLING_CNTL_reserved0_SHIFT 1 /* MFD :: CHROMA_SAMPLING_CNTL :: CHROMA_REPOSITION_ENABLE [00:00] */ #define BCHP_MFD_CHROMA_SAMPLING_CNTL_CHROMA_REPOSITION_ENABLE_MASK 0x00000001 #define BCHP_MFD_CHROMA_SAMPLING_CNTL_CHROMA_REPOSITION_ENABLE_SHIFT 0 #define BCHP_MFD_CHROMA_SAMPLING_CNTL_CHROMA_REPOSITION_ENABLE_OFF 0 #define BCHP_MFD_CHROMA_SAMPLING_CNTL_CHROMA_REPOSITION_ENABLE_ON 1 /*************************************************************************** *LUMA_NMBY - MPEG Feeder Luma NMBY Size Register ***************************************************************************/ /* MFD :: LUMA_NMBY :: reserved0 [31:10] */ #define BCHP_MFD_LUMA_NMBY_reserved0_MASK 0xfffffc00 #define BCHP_MFD_LUMA_NMBY_reserved0_SHIFT 10 /* MFD :: LUMA_NMBY :: VALUE [09:00] */ #define BCHP_MFD_LUMA_NMBY_VALUE_MASK 0x000003ff #define BCHP_MFD_LUMA_NMBY_VALUE_SHIFT 0 /*************************************************************************** *CHROMA_NMBY - MPEG Feeder Chroma NMBY Size Register ***************************************************************************/ /* MFD :: CHROMA_NMBY :: reserved0 [31:10] */ #define BCHP_MFD_CHROMA_NMBY_reserved0_MASK 0xfffffc00 #define BCHP_MFD_CHROMA_NMBY_reserved0_SHIFT 10 /* MFD :: CHROMA_NMBY :: VALUE [09:00] */ #define BCHP_MFD_CHROMA_NMBY_VALUE_MASK 0x000003ff #define BCHP_MFD_CHROMA_NMBY_VALUE_SHIFT 0 /*************************************************************************** *PIC_FEED_CMD - MPEG/Video Feeder Picture Feed Command Register ***************************************************************************/ /* MFD :: PIC_FEED_CMD :: reserved0 [31:01] */ #define BCHP_MFD_PIC_FEED_CMD_reserved0_MASK 0xfffffffe #define BCHP_MFD_PIC_FEED_CMD_reserved0_SHIFT 1 /* MFD :: PIC_FEED_CMD :: START_FEED [00:00] */ #define BCHP_MFD_PIC_FEED_CMD_START_FEED_MASK 0x00000001 #define BCHP_MFD_PIC_FEED_CMD_START_FEED_SHIFT 0 /*************************************************************************** *CRC_CTRL - MPEG/Video Feeder CRC Control Register ***************************************************************************/ /* MFD :: CRC_CTRL :: reserved0 [31:03] */ #define BCHP_MFD_CRC_CTRL_reserved0_MASK 0xfffffff8 #define BCHP_MFD_CRC_CTRL_reserved0_SHIFT 3 /* MFD :: CRC_CTRL :: ENABLE [02:02] */ #define BCHP_MFD_CRC_CTRL_ENABLE_MASK 0x00000004 #define BCHP_MFD_CRC_CTRL_ENABLE_SHIFT 2 #define BCHP_MFD_CRC_CTRL_ENABLE_OFF 0 #define BCHP_MFD_CRC_CTRL_ENABLE_ON 1 /* MFD :: CRC_CTRL :: MODE [01:01] */ #define BCHP_MFD_CRC_CTRL_MODE_MASK 0x00000002 #define BCHP_MFD_CRC_CTRL_MODE_SHIFT 1 #define BCHP_MFD_CRC_CTRL_MODE_DISPLAY 0 #define BCHP_MFD_CRC_CTRL_MODE_DEBUG 1 /* MFD :: CRC_CTRL :: LOAD_CRC_SEED [00:00] */ #define BCHP_MFD_CRC_CTRL_LOAD_CRC_SEED_MASK 0x00000001 #define BCHP_MFD_CRC_CTRL_LOAD_CRC_SEED_SHIFT 0 #define BCHP_MFD_CRC_CTRL_LOAD_CRC_SEED_AT_SOF 0 #define BCHP_MFD_CRC_CTRL_LOAD_CRC_SEED_ONCE 1 /*************************************************************************** *CRC_SEED - MPEG/Video Feeder CRC Seed Register ***************************************************************************/ /* MFD :: CRC_SEED :: VALUE [31:00] */ #define BCHP_MFD_CRC_SEED_VALUE_MASK 0xffffffff #define BCHP_MFD_CRC_SEED_VALUE_SHIFT 0 /*************************************************************************** *LUMA_CRC - MPEG/Video Feeder Luma CRC Register ***************************************************************************/ /* MFD :: LUMA_CRC :: VALUE [31:00] */ #define BCHP_MFD_LUMA_CRC_VALUE_MASK 0xffffffff #define BCHP_MFD_LUMA_CRC_VALUE_SHIFT 0 /*************************************************************************** *CHROMA_CRC - MPEG/Video Feeder Chroma CRC Register ***************************************************************************/ /* MFD :: CHROMA_CRC :: VALUE [31:00] */ #define BCHP_MFD_CHROMA_CRC_VALUE_MASK 0xffffffff #define BCHP_MFD_CHROMA_CRC_VALUE_SHIFT 0 /*************************************************************************** *DATA_MODE - MPEG/Video Feeder Data Mode Register ***************************************************************************/ /* MFD :: DATA_MODE :: reserved0 [31:01] */ #define BCHP_MFD_DATA_MODE_reserved0_MASK 0xfffffffe #define BCHP_MFD_DATA_MODE_reserved0_SHIFT 1 /* MFD :: DATA_MODE :: PIXEL_WIDTH [00:00] */ #define BCHP_MFD_DATA_MODE_PIXEL_WIDTH_MASK 0x00000001 #define BCHP_MFD_DATA_MODE_PIXEL_WIDTH_SHIFT 0 #define BCHP_MFD_DATA_MODE_PIXEL_WIDTH_MODE_8_BIT 0 #define BCHP_MFD_DATA_MODE_PIXEL_WIDTH_MODE_10_BIT 1 /*************************************************************************** *PIC_OFFSET - MPEG/Video Feeder Picture Offset Register ***************************************************************************/ /* MFD :: PIC_OFFSET :: reserved0 [31:03] */ #define BCHP_MFD_PIC_OFFSET_reserved0_MASK 0xfffffff8 #define BCHP_MFD_PIC_OFFSET_reserved0_SHIFT 3 /* MFD :: PIC_OFFSET :: H_OFFSET [02:00] */ #define BCHP_MFD_PIC_OFFSET_H_OFFSET_MASK 0x00000007 #define BCHP_MFD_PIC_OFFSET_H_OFFSET_SHIFT 0 /*************************************************************************** *RANGE_EXP_REMAP_CNTL - MPEG/Video Feeder Range Expansion / Remapping Control Register ***************************************************************************/ /* MFD :: RANGE_EXP_REMAP_CNTL :: reserved0 [31:10] */ #define BCHP_MFD_RANGE_EXP_REMAP_CNTL_reserved0_MASK 0xfffffc00 #define BCHP_MFD_RANGE_EXP_REMAP_CNTL_reserved0_SHIFT 10 /* MFD :: RANGE_EXP_REMAP_CNTL :: SCALE_C [09:05] */ #define BCHP_MFD_RANGE_EXP_REMAP_CNTL_SCALE_C_MASK 0x000003e0 #define BCHP_MFD_RANGE_EXP_REMAP_CNTL_SCALE_C_SHIFT 5 /* MFD :: RANGE_EXP_REMAP_CNTL :: SCALE_Y [04:00] */ #define BCHP_MFD_RANGE_EXP_REMAP_CNTL_SCALE_Y_MASK 0x0000001f #define BCHP_MFD_RANGE_EXP_REMAP_CNTL_SCALE_Y_SHIFT 0 /*************************************************************************** *FEED_STATUS - MPEG/Video Feeder Feed Status Register ***************************************************************************/ /* MFD :: FEED_STATUS :: reserved0 [31:30] */ #define BCHP_MFD_FEED_STATUS_reserved0_MASK 0xc0000000 #define BCHP_MFD_FEED_STATUS_reserved0_SHIFT 30 /* MFD :: FEED_STATUS :: LAST_LINE [29:29] */ #define BCHP_MFD_FEED_STATUS_LAST_LINE_MASK 0x20000000 #define BCHP_MFD_FEED_STATUS_LAST_LINE_SHIFT 29 /* MFD :: FEED_STATUS :: reserved1 [28:13] */ #define BCHP_MFD_FEED_STATUS_reserved1_MASK 0x1fffe000 #define BCHP_MFD_FEED_STATUS_reserved1_SHIFT 13 /* MFD :: FEED_STATUS :: LINE_COUNT [12:00] */ #define BCHP_MFD_FEED_STATUS_LINE_COUNT_MASK 0x00001fff #define BCHP_MFD_FEED_STATUS_LINE_COUNT_SHIFT 0 /*************************************************************************** *PICTURE0_LAC_LINE_ADDR_0 - MPEG/Video Feeder Line Address Computer Line Address0 Register ***************************************************************************/ /* union - case AVC_MPEG [31:00] */ /* MFD :: PICTURE0_LAC_LINE_ADDR_0 :: AVC_MPEG :: LUMA_ADDR [31:00] */ #define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_0_AVC_MPEG_LUMA_ADDR_MASK 0xffffffff #define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_0_AVC_MPEG_LUMA_ADDR_SHIFT 0 /* union - case PACKED [31:00] */ /* MFD :: PICTURE0_LAC_LINE_ADDR_0 :: PACKED :: LUMA_CHROMA_ADDR [31:00] */ #define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_0_PACKED_LUMA_CHROMA_ADDR_MASK 0xffffffff #define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_0_PACKED_LUMA_CHROMA_ADDR_SHIFT 0 /*************************************************************************** *PICTURE0_LAC_LINE_ADDR_1 - MPEG/Video Feeder Line Address Computer Line Address1 Register ***************************************************************************/ /* union - case AVC_MPEG [31:00] */ /* MFD :: PICTURE0_LAC_LINE_ADDR_1 :: AVC_MPEG :: CHROMA_ADDR [31:00] */ #define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_1_AVC_MPEG_CHROMA_ADDR_MASK 0xffffffff #define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_1_AVC_MPEG_CHROMA_ADDR_SHIFT 0 /* union - case PACKED [31:00] */ /* MFD :: PICTURE0_LAC_LINE_ADDR_1 :: PACKED :: reserved0 [31:00] */ #define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_1_PACKED_reserved0_MASK 0xffffffff #define BCHP_MFD_PICTURE0_LAC_LINE_ADDR_1_PACKED_reserved0_SHIFT 0 /*************************************************************************** *PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG - MPEG/Video Feeder Line Address Computer Chroma Vertical Filter Configuration Register ***************************************************************************/ /* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: reserved0 [31:20] */ #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_reserved0_MASK 0xfff00000 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_reserved0_SHIFT 20 /* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CLB_RD_ADDR_UPDATE_1 [19:19] */ #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_1_MASK 0x00080000 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_1_SHIFT 19 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_1_OFF 0 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_1_ON 1 /* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CLB_RD_ADDR_UPDATE_0 [18:18] */ #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_0_MASK 0x00040000 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_0_SHIFT 18 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_0_OFF 0 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_RD_ADDR_UPDATE_0_ON 1 /* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CLB_WREN_1 [17:17] */ #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_1_MASK 0x00020000 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_1_SHIFT 17 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_1_ENABLE 0 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_1_DISABLE 1 /* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CLB_WREN_0 [16:16] */ #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_0_MASK 0x00010000 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_0_SHIFT 16 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_0_ENABLE 0 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CLB_WREN_0_DISABLE 1 /* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CR_COEFF_TOP [15:12] */ #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CR_COEFF_TOP_MASK 0x0000f000 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CR_COEFF_TOP_SHIFT 12 /* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CR_COEFF_BOT [11:08] */ #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CR_COEFF_BOT_MASK 0x00000f00 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CR_COEFF_BOT_SHIFT 8 /* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CB_COEFF_TOP [07:04] */ #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CB_COEFF_TOP_MASK 0x000000f0 #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CB_COEFF_TOP_SHIFT 4 /* MFD :: PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG :: CB_COEFF_BOT [03:00] */ #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CB_COEFF_BOT_MASK 0x0000000f #define BCHP_MFD_PICTURE0_LAC_CHROMA_VERT_FILTER_CONFIG_CB_COEFF_BOT_SHIFT 0 /*************************************************************************** *LAC_LINE_FEED_CNTL - MPEG/Video Feeder Line Address Computer Line Feed Control Register ***************************************************************************/ /* MFD :: LAC_LINE_FEED_CNTL :: reserved0 [31:02] */ #define BCHP_MFD_LAC_LINE_FEED_CNTL_reserved0_MASK 0xfffffffc #define BCHP_MFD_LAC_LINE_FEED_CNTL_reserved0_SHIFT 2 /* MFD :: LAC_LINE_FEED_CNTL :: FIRST_LINE [01:01] */ #define BCHP_MFD_LAC_LINE_FEED_CNTL_FIRST_LINE_MASK 0x00000002 #define BCHP_MFD_LAC_LINE_FEED_CNTL_FIRST_LINE_SHIFT 1 /* MFD :: LAC_LINE_FEED_CNTL :: START_LINE_FEED [00:00] */ #define BCHP_MFD_LAC_LINE_FEED_CNTL_START_LINE_FEED_MASK 0x00000001 #define BCHP_MFD_LAC_LINE_FEED_CNTL_START_LINE_FEED_SHIFT 0 #define BCHP_MFD_LAC_LINE_FEED_CNTL_START_LINE_FEED_PENDING 0 #define BCHP_MFD_LAC_LINE_FEED_CNTL_START_LINE_FEED_COMPLETE 1 /*************************************************************************** *FEEDER_TIMEOUT_REPEAT_PIC_CNTL - MPEG/Video Feeder Timeout and Repeat Picture Control Register ***************************************************************************/ /* MFD :: FEEDER_TIMEOUT_REPEAT_PIC_CNTL :: reserved0 [31:26] */ #define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_reserved0_MASK 0xfc000000 #define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_reserved0_SHIFT 26 /* MFD :: FEEDER_TIMEOUT_REPEAT_PIC_CNTL :: FEEDER_TIMEOUT_ENABLE [25:25] */ #define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_FEEDER_TIMEOUT_ENABLE_MASK 0x02000000 #define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_FEEDER_TIMEOUT_ENABLE_SHIFT 25 #define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_FEEDER_TIMEOUT_ENABLE_OFF 0 #define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_FEEDER_TIMEOUT_ENABLE_ON 1 /* MFD :: FEEDER_TIMEOUT_REPEAT_PIC_CNTL :: REPEAT_PIC_ENABLE [24:24] */ #define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_REPEAT_PIC_ENABLE_MASK 0x01000000 #define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_REPEAT_PIC_ENABLE_SHIFT 24 #define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_REPEAT_PIC_ENABLE_OFF 0 #define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_REPEAT_PIC_ENABLE_ON 1 /* MFD :: FEEDER_TIMEOUT_REPEAT_PIC_CNTL :: TIMEOUT_COUNT [23:00] */ #define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_TIMEOUT_COUNT_MASK 0x00ffffff #define BCHP_MFD_FEEDER_TIMEOUT_REPEAT_PIC_CNTL_TIMEOUT_COUNT_SHIFT 0 /*************************************************************************** *BVB_RX_STALL_TIMEOUT_CNTL - MPEG/Video Feeder BVB Receiver Stall Timeout Control Register ***************************************************************************/ /* MFD :: BVB_RX_STALL_TIMEOUT_CNTL :: reserved0 [31:25] */ #define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_reserved0_MASK 0xfe000000 #define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_reserved0_SHIFT 25 /* MFD :: BVB_RX_STALL_TIMEOUT_CNTL :: RX_STALL_TIMEOUT_ENABLE [24:24] */ #define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_RX_STALL_TIMEOUT_ENABLE_MASK 0x01000000 #define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_RX_STALL_TIMEOUT_ENABLE_SHIFT 24 #define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_RX_STALL_TIMEOUT_ENABLE_OFF 0 #define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_RX_STALL_TIMEOUT_ENABLE_ON 1 /* MFD :: BVB_RX_STALL_TIMEOUT_CNTL :: TIMEOUT_COUNT [23:00] */ #define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_TIMEOUT_COUNT_MASK 0x00ffffff #define BCHP_MFD_BVB_RX_STALL_TIMEOUT_CNTL_TIMEOUT_COUNT_SHIFT 0 /*************************************************************************** *FEEDER_ERROR_INTERRUPT_STATUS - MPEG/Video Feeder Error Interrupt Status Register ***************************************************************************/ /* MFD :: FEEDER_ERROR_INTERRUPT_STATUS :: reserved0 [31:03] */ #define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_reserved0_MASK 0xfffffff8 #define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_reserved0_SHIFT 3 /* MFD :: FEEDER_ERROR_INTERRUPT_STATUS :: PIC_FEED_CMD_OVER_WR [02:02] */ #define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_PIC_FEED_CMD_OVER_WR_MASK 0x00000004 #define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_PIC_FEED_CMD_OVER_WR_SHIFT 2 /* MFD :: FEEDER_ERROR_INTERRUPT_STATUS :: RX_STALL_TIMEOUT [01:01] */ #define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_RX_STALL_TIMEOUT_MASK 0x00000002 #define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_RX_STALL_TIMEOUT_SHIFT 1 /* MFD :: FEEDER_ERROR_INTERRUPT_STATUS :: FEEDER_TIMEOUT [00:00] */ #define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_FEEDER_TIMEOUT_MASK 0x00000001 #define BCHP_MFD_FEEDER_ERROR_INTERRUPT_STATUS_FEEDER_TIMEOUT_SHIFT 0 /*************************************************************************** *FEEDER_BVB_STATUS - MPEG/Video Feeder BVB Status Register ***************************************************************************/ /* MFD :: FEEDER_BVB_STATUS :: reserved0 [31:02] */ #define BCHP_MFD_FEEDER_BVB_STATUS_reserved0_MASK 0xfffffffc #define BCHP_MFD_FEEDER_BVB_STATUS_reserved0_SHIFT 2 /* MFD :: FEEDER_BVB_STATUS :: EOF [01:01] */ #define BCHP_MFD_FEEDER_BVB_STATUS_EOF_MASK 0x00000002 #define BCHP_MFD_FEEDER_BVB_STATUS_EOF_SHIFT 1 /* MFD :: FEEDER_BVB_STATUS :: EOL [00:00] */ #define BCHP_MFD_FEEDER_BVB_STATUS_EOL_MASK 0x00000001 #define BCHP_MFD_FEEDER_BVB_STATUS_EOL_SHIFT 0 /*************************************************************************** *TEST_MODE_CNTL - MPEG/Video Feeder Test Mode Control Register ***************************************************************************/ /* MFD :: TEST_MODE_CNTL :: reserved0 [31:04] */ #define BCHP_MFD_TEST_MODE_CNTL_reserved0_MASK 0xfffffff0 #define BCHP_MFD_TEST_MODE_CNTL_reserved0_SHIFT 4 /* MFD :: TEST_MODE_CNTL :: BVB_TEST_MODE [03:03] */ #define BCHP_MFD_TEST_MODE_CNTL_BVB_TEST_MODE_MASK 0x00000008 #define BCHP_MFD_TEST_MODE_CNTL_BVB_TEST_MODE_SHIFT 3 /* MFD :: TEST_MODE_CNTL :: PIXEL_SATURATION_ENABLE [02:02] */ #define BCHP_MFD_TEST_MODE_CNTL_PIXEL_SATURATION_ENABLE_MASK 0x00000004 #define BCHP_MFD_TEST_MODE_CNTL_PIXEL_SATURATION_ENABLE_SHIFT 2 #define BCHP_MFD_TEST_MODE_CNTL_PIXEL_SATURATION_ENABLE_OFF 0 #define BCHP_MFD_TEST_MODE_CNTL_PIXEL_SATURATION_ENABLE_ON 1 /* MFD :: TEST_MODE_CNTL :: ACCEPT_STATE [01:01] */ #define BCHP_MFD_TEST_MODE_CNTL_ACCEPT_STATE_MASK 0x00000002 #define BCHP_MFD_TEST_MODE_CNTL_ACCEPT_STATE_SHIFT 1 /* MFD :: TEST_MODE_CNTL :: ACCEPT_PULSE [00:00] */ #define BCHP_MFD_TEST_MODE_CNTL_ACCEPT_PULSE_MASK 0x00000001 #define BCHP_MFD_TEST_MODE_CNTL_ACCEPT_PULSE_SHIFT 0 /*************************************************************************** *BVB_SAMPLE_DATA - MPEG/Video Feeder BVB Output Sample Data Register ***************************************************************************/ /* MFD :: BVB_SAMPLE_DATA :: reserved0 [31:26] */ #define BCHP_MFD_BVB_SAMPLE_DATA_reserved0_MASK 0xfc000000 #define BCHP_MFD_BVB_SAMPLE_DATA_reserved0_SHIFT 26 /* MFD :: BVB_SAMPLE_DATA :: PICTURE_SYNC [25:24] */ #define BCHP_MFD_BVB_SAMPLE_DATA_PICTURE_SYNC_MASK 0x03000000 #define BCHP_MFD_BVB_SAMPLE_DATA_PICTURE_SYNC_SHIFT 24 #define BCHP_MFD_BVB_SAMPLE_DATA_PICTURE_SYNC_NORMAL_PIXEL 0 #define BCHP_MFD_BVB_SAMPLE_DATA_PICTURE_SYNC_FIRST_PIXEL 1 #define BCHP_MFD_BVB_SAMPLE_DATA_PICTURE_SYNC_LAST_PIXEL 2 /* MFD :: BVB_SAMPLE_DATA :: LINE_SYNC [23:22] */ #define BCHP_MFD_BVB_SAMPLE_DATA_LINE_SYNC_MASK 0x00c00000 #define BCHP_MFD_BVB_SAMPLE_DATA_LINE_SYNC_SHIFT 22 #define BCHP_MFD_BVB_SAMPLE_DATA_LINE_SYNC_NORMAL_PIXEL 0 #define BCHP_MFD_BVB_SAMPLE_DATA_LINE_SYNC_FIRST_PIXEL 1 #define BCHP_MFD_BVB_SAMPLE_DATA_LINE_SYNC_LAST_PIXEL 2 /* MFD :: BVB_SAMPLE_DATA :: COLOUR_SYNC [21:20] */ #define BCHP_MFD_BVB_SAMPLE_DATA_COLOUR_SYNC_MASK 0x00300000 #define BCHP_MFD_BVB_SAMPLE_DATA_COLOUR_SYNC_SHIFT 20 #define BCHP_MFD_BVB_SAMPLE_DATA_COLOUR_SYNC_FIRST_BEAT 0 #define BCHP_MFD_BVB_SAMPLE_DATA_COLOUR_SYNC_SECOND_BEAT 1 #define BCHP_MFD_BVB_SAMPLE_DATA_COLOUR_SYNC_THIRD_BEAT 2 #define BCHP_MFD_BVB_SAMPLE_DATA_COLOUR_SYNC_FOURTH_BEAT 3 /* MFD :: BVB_SAMPLE_DATA :: LUMA [19:10] */ #define BCHP_MFD_BVB_SAMPLE_DATA_LUMA_MASK 0x000ffc00 #define BCHP_MFD_BVB_SAMPLE_DATA_LUMA_SHIFT 10 /* MFD :: BVB_SAMPLE_DATA :: CHROMA [09:00] */ #define BCHP_MFD_BVB_SAMPLE_DATA_CHROMA_MASK 0x000003ff #define BCHP_MFD_BVB_SAMPLE_DATA_CHROMA_SHIFT 0 /*************************************************************************** *TEST_PORT_CNTL - MPEG/Video Feeder Test port Control Register ***************************************************************************/ /* MFD :: TEST_PORT_CNTL :: reserved0 [31:04] */ #define BCHP_MFD_TEST_PORT_CNTL_reserved0_MASK 0xfffffff0 #define BCHP_MFD_TEST_PORT_CNTL_reserved0_SHIFT 4 /* MFD :: TEST_PORT_CNTL :: ADDR_SEL [03:03] */ #define BCHP_MFD_TEST_PORT_CNTL_ADDR_SEL_MASK 0x00000008 #define BCHP_MFD_TEST_PORT_CNTL_ADDR_SEL_SHIFT 3 #define BCHP_MFD_TEST_PORT_CNTL_ADDR_SEL_PIN_INPUT 0 #define BCHP_MFD_TEST_PORT_CNTL_ADDR_SEL_SOFT_INPUT 1 /* MFD :: TEST_PORT_CNTL :: TP_ADDR [02:00] */ #define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_MASK 0x00000007 #define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_SHIFT 0 #define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_HAC_0 0 #define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_HAC_1 1 #define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_LAC_HAC_2 2 #define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_PX_RD_SM 3 #define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_PX_RD_BVB 4 #define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_CLB_0 5 #define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_CLB_1 6 #define BCHP_MFD_TEST_PORT_CNTL_TP_ADDR_BVB_OUT 7 /*************************************************************************** *TEST_PORT_DATA - MPEG/Video Feeder Test port Data Register ***************************************************************************/ /* union - case HAC_0 [31:00] */ /* MFD :: TEST_PORT_DATA :: HAC_0 :: HAC_LUMA_ADDR [31:00] */ #define BCHP_MFD_TEST_PORT_DATA_HAC_0_HAC_LUMA_ADDR_MASK 0xffffffff #define BCHP_MFD_TEST_PORT_DATA_HAC_0_HAC_LUMA_ADDR_SHIFT 0 /* union - case HAC_1 [31:00] */ /* MFD :: TEST_PORT_DATA :: HAC_1 :: HAC_CHROMA_ADDR [31:00] */ #define BCHP_MFD_TEST_PORT_DATA_HAC_1_HAC_CHROMA_ADDR_MASK 0xffffffff #define BCHP_MFD_TEST_PORT_DATA_HAC_1_HAC_CHROMA_ADDR_SHIFT 0 /* union - case LAC_HAC_2 [31:00] */ /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: reserved0 [31:30] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_reserved0_MASK 0xc0000000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_reserved0_SHIFT 30 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: FIRST_LINE_TRIG [29:29] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_FIRST_LINE_TRIG_MASK 0x20000000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_FIRST_LINE_TRIG_SHIFT 29 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: LAC_SOL [28:28] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LAC_SOL_MASK 0x10000000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LAC_SOL_SHIFT 28 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: LAC_BUSY [27:27] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LAC_BUSY_MASK 0x08000000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LAC_BUSY_SHIFT 27 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: reserved1 [26:26] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_reserved1_MASK 0x04000000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_reserved1_SHIFT 26 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: LINE_ADDR_SEL [25:25] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_SEL_MASK 0x02000000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_SEL_SHIFT 25 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: LINE_ADDR_INCR [24:23] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_INCR_MASK 0x01800000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_INCR_SHIFT 23 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_INCR_NO_UPDATE 0 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_INCR_PACKED_LINE_STRIDE 1 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_INCR_AVC_MPEG_LUMA_LINE_STRIDE 2 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LINE_ADDR_INCR_AVC_MPEG_CHROMA_LINE_STRIDE 3 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: CSM_TRIG [22:22] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_CSM_TRIG_MASK 0x00400000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_CSM_TRIG_SHIFT 22 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: LUMA_LINE_PHASE [21:21] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LUMA_LINE_PHASE_MASK 0x00200000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LUMA_LINE_PHASE_SHIFT 21 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LUMA_LINE_PHASE_EVEN 0 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LUMA_LINE_PHASE_ODD 1 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: BUF_AVIAL [20:20] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_BUF_AVIAL_MASK 0x00100000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_BUF_AVIAL_SHIFT 20 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: CURRENT_BUF [19:19] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_CURRENT_BUF_MASK 0x00080000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_CURRENT_BUF_SHIFT 19 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: DBUF_DEPTH [18:17] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_DBUF_DEPTH_MASK 0x00060000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_DBUF_DEPTH_SHIFT 17 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_DBUF_DEPTH_EMPTY 0 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_DBUF_DEPTH_HALF_FULL 1 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_DBUF_DEPTH_FULL 2 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: WSM_TRIG [16:16] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_TRIG_MASK 0x00010000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_TRIG_SHIFT 16 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: WSM_WR_DONE [15:15] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_WR_DONE_MASK 0x00008000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_WR_DONE_SHIFT 15 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: WSM_CUR_STATE [14:13] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_CUR_STATE_MASK 0x00006000 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_CUR_STATE_SHIFT 13 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_CUR_STATE_IDLE 0 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_CUR_STATE_DBUF_WRITE 1 #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_WSM_CUR_STATE_BUF_AVAIL 2 /* MFD :: TEST_PORT_DATA :: LAC_HAC_2 :: LUMA_HORZ_CURSOR [12:00] */ #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LUMA_HORZ_CURSOR_MASK 0x00001fff #define BCHP_MFD_TEST_PORT_DATA_LAC_HAC_2_LUMA_HORZ_CURSOR_SHIFT 0 /* union - case PX_RD_SM [31:00] */ /* MFD :: TEST_PORT_DATA :: PX_RD_SM :: reserved0 [31:30] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_reserved0_MASK 0xc0000000 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_reserved0_SHIFT 30 /* MFD :: TEST_PORT_DATA :: PX_RD_SM :: BUF_READY [29:29] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_BUF_READY_MASK 0x20000000 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_BUF_READY_SHIFT 29 /* MFD :: TEST_PORT_DATA :: PX_RD_SM :: NUM_ACTIVE_PIXEL [28:19] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_NUM_ACTIVE_PIXEL_MASK 0x1ff80000 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_NUM_ACTIVE_PIXEL_SHIFT 19 /* MFD :: TEST_PORT_DATA :: PX_RD_SM :: INIT_PIX_OFFSET [18:15] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_INIT_PIX_OFFSET_MASK 0x00078000 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_INIT_PIX_OFFSET_SHIFT 15 /* MFD :: TEST_PORT_DATA :: PX_RD_SM :: RSM_CUR_STATE [14:12] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_MASK 0x00007000 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_SHIFT 12 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_IDLE 0 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_SEND_FIXED_COLOUR 1 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_READ_BUF_CHECK 2 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_PRIME_LUMA_BUF 3 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_PRIME_CHROMA_BUF 4 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_SEND_PIXEL 5 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RSM_CUR_STATE_BUFFER_READ_DONE 6 /* MFD :: TEST_PORT_DATA :: PX_RD_SM :: DBUF_RD_ON [11:11] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_DBUF_RD_ON_MASK 0x00000800 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_DBUF_RD_ON_SHIFT 11 /* MFD :: TEST_PORT_DATA :: PX_RD_SM :: RD_PIXEL_CNT [10:01] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RD_PIXEL_CNT_MASK 0x000007fe #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_RD_PIXEL_CNT_SHIFT 1 /* MFD :: TEST_PORT_DATA :: PX_RD_SM :: BUF_RD_DONE [00:00] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_BUF_RD_DONE_MASK 0x00000001 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_SM_BUF_RD_DONE_SHIFT 0 /* union - case PX_RD_BVB [31:00] */ /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: reserved0 [31:30] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_reserved0_MASK 0xc0000000 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_reserved0_SHIFT 30 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: CSM_CUR_STATE [29:27] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_MASK 0x38000000 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_SHIFT 27 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_IDLE 0 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_BUF_CHECK 1 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_WAIT_ACK_LUMA 2 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_REQ_CHROMA 3 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_WAIT_ACK_CHROMA 4 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CSM_CUR_STATE_WAIT_WSM_DONE_CHROMA 5 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: DBUF_WR_ADDR [26:21] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_DBUF_WR_ADDR_MASK 0x07e00000 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_DBUF_WR_ADDR_SHIFT 21 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: DBUF_RD_ADDR [20:15] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_DBUF_RD_ADDR_MASK 0x001f8000 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_DBUF_RD_ADDR_SHIFT 15 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: FIRST_BUF [14:14] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIRST_BUF_MASK 0x00004000 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIRST_BUF_SHIFT 14 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: LAST_BUF [13:13] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_LAST_BUF_MASK 0x00002000 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_LAST_BUF_SHIFT 13 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: PIXEL_STROBE [12:12] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_PIXEL_STROBE_MASK 0x00001000 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_PIXEL_STROBE_SHIFT 12 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: CHROMA_PHASE [11:11] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CHROMA_PHASE_MASK 0x00000800 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_CHROMA_PHASE_SHIFT 11 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: FIRST_PIXEL [10:10] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIRST_PIXEL_MASK 0x00000400 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIRST_PIXEL_SHIFT 10 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: LAST_PIXEL [09:09] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_LAST_PIXEL_MASK 0x00000200 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_LAST_PIXEL_SHIFT 9 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: FIRST_LINE [08:08] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIRST_LINE_MASK 0x00000100 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIRST_LINE_SHIFT 8 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: LAST_LINE [07:07] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_LAST_LINE_MASK 0x00000080 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_LAST_LINE_SHIFT 7 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: FIFO_FULL [06:06] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIFO_FULL_MASK 0x00000040 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIFO_FULL_SHIFT 6 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: FIFO_EMPTY [05:05] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIFO_EMPTY_MASK 0x00000020 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIFO_EMPTY_SHIFT 5 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: FIFO_DEPTH_CNT [04:03] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIFO_DEPTH_CNT_MASK 0x00000018 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_FIFO_DEPTH_CNT_SHIFT 3 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: PIXEL_STOP [02:02] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_PIXEL_STOP_MASK 0x00000004 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_PIXEL_STOP_SHIFT 2 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: BVB_EOL [01:01] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_BVB_EOL_MASK 0x00000002 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_BVB_EOL_SHIFT 1 /* MFD :: TEST_PORT_DATA :: PX_RD_BVB :: BVB_EOF [00:00] */ #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_BVB_EOF_MASK 0x00000001 #define BCHP_MFD_TEST_PORT_DATA_PX_RD_BVB_BVB_EOF_SHIFT 0 /* union - case CLB_0 [31:00] */ /* MFD :: TEST_PORT_DATA :: CLB_0 :: reserved0 [31:31] */ #define BCHP_MFD_TEST_PORT_DATA_CLB_0_reserved0_MASK 0x80000000 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_reserved0_SHIFT 31 /* MFD :: TEST_PORT_DATA :: CLB_0 :: BURST_SIZE [30:26] */ #define BCHP_MFD_TEST_PORT_DATA_CLB_0_BURST_SIZE_MASK 0x7c000000 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_BURST_SIZE_SHIFT 26 /* MFD :: TEST_PORT_DATA :: CLB_0 :: TOP_TAP_SEL [25:24] */ #define BCHP_MFD_TEST_PORT_DATA_CLB_0_TOP_TAP_SEL_MASK 0x03000000 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_TOP_TAP_SEL_SHIFT 24 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_TOP_TAP_SEL_LIVE_CHROMA 0 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_TOP_TAP_SEL_CLB0_CHROMA 1 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_TOP_TAP_SEL_CLB1_CHROMA 2 /* MFD :: TEST_PORT_DATA :: CLB_0 :: BOT_TAP_SEL [23:22] */ #define BCHP_MFD_TEST_PORT_DATA_CLB_0_BOT_TAP_SEL_MASK 0x00c00000 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_BOT_TAP_SEL_SHIFT 22 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_BOT_TAP_SEL_LIVE_CHROMA 0 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_BOT_TAP_SEL_CLB0_CHROMA 1 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_BOT_TAP_SEL_CLB1_CHROMA 2 /* MFD :: TEST_PORT_DATA :: CLB_0 :: ADDR_A [21:12] */ #define BCHP_MFD_TEST_PORT_DATA_CLB_0_ADDR_A_MASK 0x003ff000 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_ADDR_A_SHIFT 12 /* MFD :: TEST_PORT_DATA :: CLB_0 :: ADDR_B [11:02] */ #define BCHP_MFD_TEST_PORT_DATA_CLB_0_ADDR_B_MASK 0x00000ffc #define BCHP_MFD_TEST_PORT_DATA_CLB_0_ADDR_B_SHIFT 2 /* MFD :: TEST_PORT_DATA :: CLB_0 :: WR_RDB_A [01:01] */ #define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_A_MASK 0x00000002 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_A_SHIFT 1 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_A_READ 0 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_A_WRITE 1 /* MFD :: TEST_PORT_DATA :: CLB_0 :: WR_RDB_B [00:00] */ #define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_B_MASK 0x00000001 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_B_SHIFT 0 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_B_READ 0 #define BCHP_MFD_TEST_PORT_DATA_CLB_0_WR_RDB_B_WRITE 1 /* union - case CLB_1 [31:00] */ /* MFD :: TEST_PORT_DATA :: CLB_1 :: WR_DATA_A [31:16] */ #define BCHP_MFD_TEST_PORT_DATA_CLB_1_WR_DATA_A_MASK 0xffff0000 #define BCHP_MFD_TEST_PORT_DATA_CLB_1_WR_DATA_A_SHIFT 16 /* MFD :: TEST_PORT_DATA :: CLB_1 :: RD_DATA_B [15:00] */ #define BCHP_MFD_TEST_PORT_DATA_CLB_1_RD_DATA_B_MASK 0x0000ffff #define BCHP_MFD_TEST_PORT_DATA_CLB_1_RD_DATA_B_SHIFT 0 /* union - case BVB_OUT [31:00] */ /* MFD :: TEST_PORT_DATA :: BVB_OUT :: reserved0 [31:28] */ #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_reserved0_MASK 0xf0000000 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_reserved0_SHIFT 28 /* MFD :: TEST_PORT_DATA :: BVB_OUT :: ACCEPT [27:27] */ #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_ACCEPT_MASK 0x08000000 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_ACCEPT_SHIFT 27 /* MFD :: TEST_PORT_DATA :: BVB_OUT :: READY [26:26] */ #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_READY_MASK 0x04000000 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_READY_SHIFT 26 /* MFD :: TEST_PORT_DATA :: BVB_OUT :: PICTURE_SYNC [25:24] */ #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_PICTURE_SYNC_MASK 0x03000000 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_PICTURE_SYNC_SHIFT 24 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_PICTURE_SYNC_NORMAL_PIXEL 0 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_PICTURE_SYNC_FIRST_PIXEL 1 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_PICTURE_SYNC_LAST_PIXEL 2 /* MFD :: TEST_PORT_DATA :: BVB_OUT :: LINE_SYNC [23:22] */ #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_LINE_SYNC_MASK 0x00c00000 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_LINE_SYNC_SHIFT 22 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_LINE_SYNC_NORMAL_PIXEL 0 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_LINE_SYNC_FIRST_PIXEL 1 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_LINE_SYNC_LAST_PIXEL 2 /* MFD :: TEST_PORT_DATA :: BVB_OUT :: COLOUR_SYNC [21:20] */ #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_COLOUR_SYNC_MASK 0x00300000 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_COLOUR_SYNC_SHIFT 20 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_COLOUR_SYNC_FIRST_BEAT 0 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_COLOUR_SYNC_SECOND_BEAT 1 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_COLOUR_SYNC_THIRD_BEAT 2 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_COLOUR_SYNC_FOURTH_BEAT 3 /* MFD :: TEST_PORT_DATA :: BVB_OUT :: LUMA_DATA [19:10] */ #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_LUMA_DATA_MASK 0x000ffc00 #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_LUMA_DATA_SHIFT 10 /* MFD :: TEST_PORT_DATA :: BVB_OUT :: CHROMA_DATA [09:00] */ #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_CHROMA_DATA_MASK 0x000003ff #define BCHP_MFD_TEST_PORT_DATA_BVB_OUT_CHROMA_DATA_SHIFT 0 /*************************************************************************** *SCRATCH_REGISTER_0 - MPEG/Video Feeder Scratch 0 Register ***************************************************************************/ /* MFD :: SCRATCH_REGISTER_0 :: VALUE [31:00] */ #define BCHP_MFD_SCRATCH_REGISTER_0_VALUE_MASK 0xffffffff #define BCHP_MFD_SCRATCH_REGISTER_0_VALUE_SHIFT 0 /*************************************************************************** *SCRATCH_REGISTER_1 - MPEG/Video Feeder Scratch 1 Register ***************************************************************************/ /* MFD :: SCRATCH_REGISTER_1 :: VALUE [31:00] */ #define BCHP_MFD_SCRATCH_REGISTER_1_VALUE_MASK 0xffffffff #define BCHP_MFD_SCRATCH_REGISTER_1_VALUE_SHIFT 0 #endif /* #ifndef BCHP_MFD_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015600000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dqnt_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000522011610313111030760 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_dqnt_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:03p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:18 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dqnt_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:03p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_DQNT_0_H__ #define BCHP_DECODE_DQNT_0_H__ /*************************************************************************** *DECODE_DQNT_0 ***************************************************************************/ #define BCHP_DECODE_DQNT_0_REG_DQNT_END 0x0080045c /* REG_DQNT_END */ /*************************************************************************** *REG_DQNT_END - REG_DQNT_END ***************************************************************************/ /* DECODE_DQNT_0 :: REG_DQNT_END :: reserved0 [31:00] */ #define BCHP_DECODE_DQNT_0_REG_DQNT_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_DQNT_0_REG_DQNT_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_DQNT_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015700000000000011570 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_mem_dma0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_0000644000175000017500000001572211610313111031007 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_sharf_mem_dma0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:19p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:19 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sharf_mem_dma0.h $ * * Hydra_Software_Devel/1 7/17/09 8:19p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_SHARF_MEM_DMA0_H__ #define BCHP_SHARF_MEM_DMA0_H__ /*************************************************************************** *SHARF_MEM_DMA0 - SHARF_MEM_DMA Channel 0 Registers ***************************************************************************/ #define BCHP_SHARF_MEM_DMA0_FIRST_DESC 0x000f4100 /* SHARF_MEM_DMA First Descriptor Address Register */ #define BCHP_SHARF_MEM_DMA0_CTRL 0x000f4104 /* SHARF_MEM_DMA Control Register */ #define BCHP_SHARF_MEM_DMA0_WAKE_CTRL 0x000f4108 /* SHARF_MEM_DMA Wake Control Register */ #define BCHP_SHARF_MEM_DMA0_STATUS 0x000f4110 /* SHARF_MEM_DMA Status Register */ #define BCHP_SHARF_MEM_DMA0_CUR_DESC 0x000f4114 /* SHARF_MEM_DMA Current Descriptor Address Register */ #define BCHP_SHARF_MEM_DMA0_CUR_BYTE 0x000f4118 /* SHARF_MEM_DMA Current Byte Count Register */ #define BCHP_SHARF_MEM_DMA0_SCRATCH 0x000f411c /* SHARF_MEM_DMA Scratch Register */ /*************************************************************************** *FIRST_DESC - SHARF_MEM_DMA First Descriptor Address Register ***************************************************************************/ /* SHARF_MEM_DMA0 :: FIRST_DESC :: ADDR [31:00] */ #define BCHP_SHARF_MEM_DMA0_FIRST_DESC_ADDR_MASK 0xffffffff #define BCHP_SHARF_MEM_DMA0_FIRST_DESC_ADDR_SHIFT 0 /*************************************************************************** *CTRL - SHARF_MEM_DMA Control Register ***************************************************************************/ /* SHARF_MEM_DMA0 :: CTRL :: reserved0 [31:01] */ #define BCHP_SHARF_MEM_DMA0_CTRL_reserved0_MASK 0xfffffffe #define BCHP_SHARF_MEM_DMA0_CTRL_reserved0_SHIFT 1 /* SHARF_MEM_DMA0 :: CTRL :: RUN [00:00] */ #define BCHP_SHARF_MEM_DMA0_CTRL_RUN_MASK 0x00000001 #define BCHP_SHARF_MEM_DMA0_CTRL_RUN_SHIFT 0 /*************************************************************************** *WAKE_CTRL - SHARF_MEM_DMA Wake Control Register ***************************************************************************/ /* SHARF_MEM_DMA0 :: WAKE_CTRL :: reserved0 [31:02] */ #define BCHP_SHARF_MEM_DMA0_WAKE_CTRL_reserved0_MASK 0xfffffffc #define BCHP_SHARF_MEM_DMA0_WAKE_CTRL_reserved0_SHIFT 2 /* SHARF_MEM_DMA0 :: WAKE_CTRL :: WAKE_MODE [01:01] */ #define BCHP_SHARF_MEM_DMA0_WAKE_CTRL_WAKE_MODE_MASK 0x00000002 #define BCHP_SHARF_MEM_DMA0_WAKE_CTRL_WAKE_MODE_SHIFT 1 /* SHARF_MEM_DMA0 :: WAKE_CTRL :: WAKE [00:00] */ #define BCHP_SHARF_MEM_DMA0_WAKE_CTRL_WAKE_MASK 0x00000001 #define BCHP_SHARF_MEM_DMA0_WAKE_CTRL_WAKE_SHIFT 0 /*************************************************************************** *STATUS - SHARF_MEM_DMA Status Register ***************************************************************************/ /* SHARF_MEM_DMA0 :: STATUS :: reserved0 [31:02] */ #define BCHP_SHARF_MEM_DMA0_STATUS_reserved0_MASK 0xfffffffc #define BCHP_SHARF_MEM_DMA0_STATUS_reserved0_SHIFT 2 /* SHARF_MEM_DMA0 :: STATUS :: DMA_STATUS [01:00] */ #define BCHP_SHARF_MEM_DMA0_STATUS_DMA_STATUS_MASK 0x00000003 #define BCHP_SHARF_MEM_DMA0_STATUS_DMA_STATUS_SHIFT 0 #define BCHP_SHARF_MEM_DMA0_STATUS_DMA_STATUS_Idle 0 #define BCHP_SHARF_MEM_DMA0_STATUS_DMA_STATUS_Busy 1 #define BCHP_SHARF_MEM_DMA0_STATUS_DMA_STATUS_Sleep 2 #define BCHP_SHARF_MEM_DMA0_STATUS_DMA_STATUS_Reserved 3 /*************************************************************************** *CUR_DESC - SHARF_MEM_DMA Current Descriptor Address Register ***************************************************************************/ /* SHARF_MEM_DMA0 :: CUR_DESC :: ADDR [31:00] */ #define BCHP_SHARF_MEM_DMA0_CUR_DESC_ADDR_MASK 0xffffffff #define BCHP_SHARF_MEM_DMA0_CUR_DESC_ADDR_SHIFT 0 /*************************************************************************** *CUR_BYTE - SHARF_MEM_DMA Current Byte Count Register ***************************************************************************/ /* SHARF_MEM_DMA0 :: CUR_BYTE :: reserved0 [31:25] */ #define BCHP_SHARF_MEM_DMA0_CUR_BYTE_reserved0_MASK 0xfe000000 #define BCHP_SHARF_MEM_DMA0_CUR_BYTE_reserved0_SHIFT 25 /* SHARF_MEM_DMA0 :: CUR_BYTE :: COUNT [24:00] */ #define BCHP_SHARF_MEM_DMA0_CUR_BYTE_COUNT_MASK 0x01ffffff #define BCHP_SHARF_MEM_DMA0_CUR_BYTE_COUNT_SHIFT 0 /*************************************************************************** *SCRATCH - SHARF_MEM_DMA Scratch Register ***************************************************************************/ /* SHARF_MEM_DMA0 :: SCRATCH :: SCRATCH_BIT [31:00] */ #define BCHP_SHARF_MEM_DMA0_SCRATCH_SCRATCH_BIT_MASK 0xffffffff #define BCHP_SHARF_MEM_DMA0_SCRATCH_SCRATCH_BIT_SHIFT 0 #endif /* #ifndef BCHP_SHARF_MEM_DMA0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016000000000000011562 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudma_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000003467511610313111031000 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_cpudma_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:01p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:10 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudma_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:01p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_CPUDMA_0_H__ #define BCHP_DECODE_CPUDMA_0_H__ /*************************************************************************** *DECODE_CPUDMA_0 ***************************************************************************/ #define BCHP_DECODE_CPUDMA_0_REG_DMA0_SD_ADDR 0x00801800 /* SDRAM address */ #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LCL_ADDR 0x00801804 /* Local Memory Address */ #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN 0x00801808 /* Length */ #define BCHP_DECODE_CPUDMA_0_REG_DMA1_SD_ADDR 0x00801810 /* REG_DMA1_SD_ADDR */ #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LCL_ADDR 0x00801814 /* REG_DMA1_LCL_ADDR */ #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN 0x00801818 /* REG_DMA1_LEN */ #define BCHP_DECODE_CPUDMA_0_REG_DMA2_SD_ADDR 0x00801820 /* REG_DMA2_SD_ADDR */ #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LCL_ADDR 0x00801824 /* REG_DMA2_LCL_ADDR */ #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN 0x00801828 /* REG_DMA2_LEN */ #define BCHP_DECODE_CPUDMA_0_REG_DMA3_SD_ADDR 0x00801830 /* REG_DMA3_SD_ADDR */ #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LCL_ADDR 0x00801834 /* REG_DMA3_LCL_ADDR */ #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN 0x00801838 /* REG_DMA3_LEN */ #define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS 0x00801840 /* REG_DMA_STATUS */ #define BCHP_DECODE_CPUDMA_0_REG_CPUDMA_END 0x008018fc /* REG_CPUDMA_END */ /*************************************************************************** *REG_DMA0_SD_ADDR - SDRAM address ***************************************************************************/ /* DECODE_CPUDMA_0 :: REG_DMA0_SD_ADDR :: Sd_Addr [31:02] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA0_SD_ADDR_Sd_Addr_MASK 0xfffffffc #define BCHP_DECODE_CPUDMA_0_REG_DMA0_SD_ADDR_Sd_Addr_SHIFT 2 /* DECODE_CPUDMA_0 :: REG_DMA0_SD_ADDR :: reserved0 [01:00] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA0_SD_ADDR_reserved0_MASK 0x00000003 #define BCHP_DECODE_CPUDMA_0_REG_DMA0_SD_ADDR_reserved0_SHIFT 0 /*************************************************************************** *REG_DMA0_LCL_ADDR - Local Memory Address ***************************************************************************/ /* DECODE_CPUDMA_0 :: REG_DMA0_LCL_ADDR :: reserved0 [31:10] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LCL_ADDR_reserved0_MASK 0xfffffc00 #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LCL_ADDR_reserved0_SHIFT 10 /* DECODE_CPUDMA_0 :: REG_DMA0_LCL_ADDR :: Addr [09:02] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LCL_ADDR_Addr_MASK 0x000003fc #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LCL_ADDR_Addr_SHIFT 2 /* DECODE_CPUDMA_0 :: REG_DMA0_LCL_ADDR :: reserved1 [01:00] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LCL_ADDR_reserved1_MASK 0x00000003 #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LCL_ADDR_reserved1_SHIFT 0 /*************************************************************************** *REG_DMA0_LEN - Length ***************************************************************************/ /* DECODE_CPUDMA_0 :: REG_DMA0_LEN :: Swap [31:31] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_Swap_MASK 0x80000000 #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_Swap_SHIFT 31 /* DECODE_CPUDMA_0 :: REG_DMA0_LEN :: reserved0 [30:11] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_reserved0_MASK 0x7ffff800 #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_reserved0_SHIFT 11 /* DECODE_CPUDMA_0 :: REG_DMA0_LEN :: Length [10:02] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_Length_MASK 0x000007fc #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_Length_SHIFT 2 /* DECODE_CPUDMA_0 :: REG_DMA0_LEN :: reserved1 [01:00] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_reserved1_MASK 0x00000003 #define BCHP_DECODE_CPUDMA_0_REG_DMA0_LEN_reserved1_SHIFT 0 /*************************************************************************** *REG_DMA1_SD_ADDR - REG_DMA1_SD_ADDR ***************************************************************************/ /* DECODE_CPUDMA_0 :: REG_DMA1_SD_ADDR :: Sd_Addr [31:02] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA1_SD_ADDR_Sd_Addr_MASK 0xfffffffc #define BCHP_DECODE_CPUDMA_0_REG_DMA1_SD_ADDR_Sd_Addr_SHIFT 2 /* DECODE_CPUDMA_0 :: REG_DMA1_SD_ADDR :: reserved0 [01:00] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA1_SD_ADDR_reserved0_MASK 0x00000003 #define BCHP_DECODE_CPUDMA_0_REG_DMA1_SD_ADDR_reserved0_SHIFT 0 /*************************************************************************** *REG_DMA1_LCL_ADDR - REG_DMA1_LCL_ADDR ***************************************************************************/ /* DECODE_CPUDMA_0 :: REG_DMA1_LCL_ADDR :: reserved0 [31:10] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LCL_ADDR_reserved0_MASK 0xfffffc00 #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LCL_ADDR_reserved0_SHIFT 10 /* DECODE_CPUDMA_0 :: REG_DMA1_LCL_ADDR :: Addr [09:02] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LCL_ADDR_Addr_MASK 0x000003fc #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LCL_ADDR_Addr_SHIFT 2 /* DECODE_CPUDMA_0 :: REG_DMA1_LCL_ADDR :: reserved1 [01:00] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LCL_ADDR_reserved1_MASK 0x00000003 #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LCL_ADDR_reserved1_SHIFT 0 /*************************************************************************** *REG_DMA1_LEN - REG_DMA1_LEN ***************************************************************************/ /* DECODE_CPUDMA_0 :: REG_DMA1_LEN :: Swap [31:31] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_Swap_MASK 0x80000000 #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_Swap_SHIFT 31 /* DECODE_CPUDMA_0 :: REG_DMA1_LEN :: reserved0 [30:11] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_reserved0_MASK 0x7ffff800 #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_reserved0_SHIFT 11 /* DECODE_CPUDMA_0 :: REG_DMA1_LEN :: Length [10:02] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_Length_MASK 0x000007fc #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_Length_SHIFT 2 /* DECODE_CPUDMA_0 :: REG_DMA1_LEN :: reserved1 [01:00] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_reserved1_MASK 0x00000003 #define BCHP_DECODE_CPUDMA_0_REG_DMA1_LEN_reserved1_SHIFT 0 /*************************************************************************** *REG_DMA2_SD_ADDR - REG_DMA2_SD_ADDR ***************************************************************************/ /* DECODE_CPUDMA_0 :: REG_DMA2_SD_ADDR :: Sd_Addr [31:02] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA2_SD_ADDR_Sd_Addr_MASK 0xfffffffc #define BCHP_DECODE_CPUDMA_0_REG_DMA2_SD_ADDR_Sd_Addr_SHIFT 2 /* DECODE_CPUDMA_0 :: REG_DMA2_SD_ADDR :: reserved0 [01:00] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA2_SD_ADDR_reserved0_MASK 0x00000003 #define BCHP_DECODE_CPUDMA_0_REG_DMA2_SD_ADDR_reserved0_SHIFT 0 /*************************************************************************** *REG_DMA2_LCL_ADDR - REG_DMA2_LCL_ADDR ***************************************************************************/ /* DECODE_CPUDMA_0 :: REG_DMA2_LCL_ADDR :: reserved0 [31:10] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LCL_ADDR_reserved0_MASK 0xfffffc00 #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LCL_ADDR_reserved0_SHIFT 10 /* DECODE_CPUDMA_0 :: REG_DMA2_LCL_ADDR :: Addr [09:02] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LCL_ADDR_Addr_MASK 0x000003fc #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LCL_ADDR_Addr_SHIFT 2 /* DECODE_CPUDMA_0 :: REG_DMA2_LCL_ADDR :: reserved1 [01:00] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LCL_ADDR_reserved1_MASK 0x00000003 #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LCL_ADDR_reserved1_SHIFT 0 /*************************************************************************** *REG_DMA2_LEN - REG_DMA2_LEN ***************************************************************************/ /* DECODE_CPUDMA_0 :: REG_DMA2_LEN :: Swap [31:31] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_Swap_MASK 0x80000000 #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_Swap_SHIFT 31 /* DECODE_CPUDMA_0 :: REG_DMA2_LEN :: reserved0 [30:11] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_reserved0_MASK 0x7ffff800 #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_reserved0_SHIFT 11 /* DECODE_CPUDMA_0 :: REG_DMA2_LEN :: Length [10:02] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_Length_MASK 0x000007fc #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_Length_SHIFT 2 /* DECODE_CPUDMA_0 :: REG_DMA2_LEN :: reserved1 [01:00] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_reserved1_MASK 0x00000003 #define BCHP_DECODE_CPUDMA_0_REG_DMA2_LEN_reserved1_SHIFT 0 /*************************************************************************** *REG_DMA3_SD_ADDR - REG_DMA3_SD_ADDR ***************************************************************************/ /* DECODE_CPUDMA_0 :: REG_DMA3_SD_ADDR :: Sd_Addr [31:02] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA3_SD_ADDR_Sd_Addr_MASK 0xfffffffc #define BCHP_DECODE_CPUDMA_0_REG_DMA3_SD_ADDR_Sd_Addr_SHIFT 2 /* DECODE_CPUDMA_0 :: REG_DMA3_SD_ADDR :: reserved0 [01:00] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA3_SD_ADDR_reserved0_MASK 0x00000003 #define BCHP_DECODE_CPUDMA_0_REG_DMA3_SD_ADDR_reserved0_SHIFT 0 /*************************************************************************** *REG_DMA3_LCL_ADDR - REG_DMA3_LCL_ADDR ***************************************************************************/ /* DECODE_CPUDMA_0 :: REG_DMA3_LCL_ADDR :: reserved0 [31:10] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LCL_ADDR_reserved0_MASK 0xfffffc00 #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LCL_ADDR_reserved0_SHIFT 10 /* DECODE_CPUDMA_0 :: REG_DMA3_LCL_ADDR :: Addr [09:02] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LCL_ADDR_Addr_MASK 0x000003fc #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LCL_ADDR_Addr_SHIFT 2 /* DECODE_CPUDMA_0 :: REG_DMA3_LCL_ADDR :: reserved1 [01:00] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LCL_ADDR_reserved1_MASK 0x00000003 #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LCL_ADDR_reserved1_SHIFT 0 /*************************************************************************** *REG_DMA3_LEN - REG_DMA3_LEN ***************************************************************************/ /* DECODE_CPUDMA_0 :: REG_DMA3_LEN :: Swap [31:31] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_Swap_MASK 0x80000000 #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_Swap_SHIFT 31 /* DECODE_CPUDMA_0 :: REG_DMA3_LEN :: reserved0 [30:11] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_reserved0_MASK 0x7ffff800 #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_reserved0_SHIFT 11 /* DECODE_CPUDMA_0 :: REG_DMA3_LEN :: Length [10:02] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_Length_MASK 0x000007fc #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_Length_SHIFT 2 /* DECODE_CPUDMA_0 :: REG_DMA3_LEN :: reserved1 [01:00] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_reserved1_MASK 0x00000003 #define BCHP_DECODE_CPUDMA_0_REG_DMA3_LEN_reserved1_SHIFT 0 /*************************************************************************** *REG_DMA_STATUS - REG_DMA_STATUS ***************************************************************************/ /* DECODE_CPUDMA_0 :: REG_DMA_STATUS :: reserved0 [31:04] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_reserved0_MASK 0xfffffff0 #define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_reserved0_SHIFT 4 /* DECODE_CPUDMA_0 :: REG_DMA_STATUS :: Act3 [03:03] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act3_MASK 0x00000008 #define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act3_SHIFT 3 /* DECODE_CPUDMA_0 :: REG_DMA_STATUS :: Act2 [02:02] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act2_MASK 0x00000004 #define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act2_SHIFT 2 /* DECODE_CPUDMA_0 :: REG_DMA_STATUS :: Act1 [01:01] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act1_MASK 0x00000002 #define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act1_SHIFT 1 /* DECODE_CPUDMA_0 :: REG_DMA_STATUS :: Act0 [00:00] */ #define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act0_MASK 0x00000001 #define BCHP_DECODE_CPUDMA_0_REG_DMA_STATUS_Act0_SHIFT 0 /*************************************************************************** *REG_CPUDMA_END - REG_CPUDMA_END ***************************************************************************/ /* DECODE_CPUDMA_0 :: REG_CPUDMA_END :: reserved0 [31:00] */ #define BCHP_DECODE_CPUDMA_0_REG_CPUDMA_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_CPUDMA_0_REG_CPUDMA_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_CPUDMA_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015500000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wakeup_ctrl2.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wakeup0000644000175000017500000002764711610313111031052 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_wakeup_ctrl2.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:22p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:03 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_wakeup_ctrl2.h $ * * Hydra_Software_Devel/1 7/17/09 8:22p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_WAKEUP_CTRL2_H__ #define BCHP_WAKEUP_CTRL2_H__ /*************************************************************************** *WAKEUP_CTRL2 - Wakeup Controller Registers ***************************************************************************/ #define BCHP_WAKEUP_CTRL2_STATUS 0x00406c00 /* Wake-Up Status Register */ #define BCHP_WAKEUP_CTRL2_SET 0x00406c04 /* Wake-Up Set Register */ #define BCHP_WAKEUP_CTRL2_CLEAR 0x00406c08 /* Wake-Up Clear Register */ #define BCHP_WAKEUP_CTRL2_MASK_STATUS 0x00406c0c /* Wake-Up Mask Status Register */ #define BCHP_WAKEUP_CTRL2_MASK_SET 0x00406c10 /* Wake-Up Mask Set Register */ #define BCHP_WAKEUP_CTRL2_MASK_CLEAR 0x00406c14 /* Wake-Up Mask Clear Register */ /*************************************************************************** *STATUS - Wake-Up Status Register ***************************************************************************/ /* WAKEUP_CTRL2 :: STATUS :: reserved0 [31:06] */ #define BCHP_WAKEUP_CTRL2_STATUS_reserved0_MASK 0xffffffc0 #define BCHP_WAKEUP_CTRL2_STATUS_reserved0_SHIFT 6 /* WAKEUP_CTRL2 :: STATUS :: GIO [05:05] */ #define BCHP_WAKEUP_CTRL2_STATUS_GIO_MASK 0x00000020 #define BCHP_WAKEUP_CTRL2_STATUS_GIO_SHIFT 5 /* WAKEUP_CTRL2 :: STATUS :: UART2 [04:04] */ #define BCHP_WAKEUP_CTRL2_STATUS_UART2_MASK 0x00000010 #define BCHP_WAKEUP_CTRL2_STATUS_UART2_SHIFT 4 /* WAKEUP_CTRL2 :: STATUS :: UART1 [03:03] */ #define BCHP_WAKEUP_CTRL2_STATUS_UART1_MASK 0x00000008 #define BCHP_WAKEUP_CTRL2_STATUS_UART1_SHIFT 3 /* WAKEUP_CTRL2 :: STATUS :: UART0 [02:02] */ #define BCHP_WAKEUP_CTRL2_STATUS_UART0_MASK 0x00000004 #define BCHP_WAKEUP_CTRL2_STATUS_UART0_SHIFT 2 /* WAKEUP_CTRL2 :: STATUS :: WAKEUP_TIMER [01:01] */ #define BCHP_WAKEUP_CTRL2_STATUS_WAKEUP_TIMER_MASK 0x00000002 #define BCHP_WAKEUP_CTRL2_STATUS_WAKEUP_TIMER_SHIFT 1 /* WAKEUP_CTRL2 :: STATUS :: IRR [00:00] */ #define BCHP_WAKEUP_CTRL2_STATUS_IRR_MASK 0x00000001 #define BCHP_WAKEUP_CTRL2_STATUS_IRR_SHIFT 0 /*************************************************************************** *SET - Wake-Up Set Register ***************************************************************************/ /* WAKEUP_CTRL2 :: SET :: reserved0 [31:06] */ #define BCHP_WAKEUP_CTRL2_SET_reserved0_MASK 0xffffffc0 #define BCHP_WAKEUP_CTRL2_SET_reserved0_SHIFT 6 /* WAKEUP_CTRL2 :: SET :: GIO [05:05] */ #define BCHP_WAKEUP_CTRL2_SET_GIO_MASK 0x00000020 #define BCHP_WAKEUP_CTRL2_SET_GIO_SHIFT 5 /* WAKEUP_CTRL2 :: SET :: UART2 [04:04] */ #define BCHP_WAKEUP_CTRL2_SET_UART2_MASK 0x00000010 #define BCHP_WAKEUP_CTRL2_SET_UART2_SHIFT 4 /* WAKEUP_CTRL2 :: SET :: UART1 [03:03] */ #define BCHP_WAKEUP_CTRL2_SET_UART1_MASK 0x00000008 #define BCHP_WAKEUP_CTRL2_SET_UART1_SHIFT 3 /* WAKEUP_CTRL2 :: SET :: UART0 [02:02] */ #define BCHP_WAKEUP_CTRL2_SET_UART0_MASK 0x00000004 #define BCHP_WAKEUP_CTRL2_SET_UART0_SHIFT 2 /* WAKEUP_CTRL2 :: SET :: WAKEUP_TIMER [01:01] */ #define BCHP_WAKEUP_CTRL2_SET_WAKEUP_TIMER_MASK 0x00000002 #define BCHP_WAKEUP_CTRL2_SET_WAKEUP_TIMER_SHIFT 1 /* WAKEUP_CTRL2 :: SET :: IRR [00:00] */ #define BCHP_WAKEUP_CTRL2_SET_IRR_MASK 0x00000001 #define BCHP_WAKEUP_CTRL2_SET_IRR_SHIFT 0 /*************************************************************************** *CLEAR - Wake-Up Clear Register ***************************************************************************/ /* WAKEUP_CTRL2 :: CLEAR :: reserved0 [31:06] */ #define BCHP_WAKEUP_CTRL2_CLEAR_reserved0_MASK 0xffffffc0 #define BCHP_WAKEUP_CTRL2_CLEAR_reserved0_SHIFT 6 /* WAKEUP_CTRL2 :: CLEAR :: GIO [05:05] */ #define BCHP_WAKEUP_CTRL2_CLEAR_GIO_MASK 0x00000020 #define BCHP_WAKEUP_CTRL2_CLEAR_GIO_SHIFT 5 /* WAKEUP_CTRL2 :: CLEAR :: UART2 [04:04] */ #define BCHP_WAKEUP_CTRL2_CLEAR_UART2_MASK 0x00000010 #define BCHP_WAKEUP_CTRL2_CLEAR_UART2_SHIFT 4 /* WAKEUP_CTRL2 :: CLEAR :: UART1 [03:03] */ #define BCHP_WAKEUP_CTRL2_CLEAR_UART1_MASK 0x00000008 #define BCHP_WAKEUP_CTRL2_CLEAR_UART1_SHIFT 3 /* WAKEUP_CTRL2 :: CLEAR :: UART0 [02:02] */ #define BCHP_WAKEUP_CTRL2_CLEAR_UART0_MASK 0x00000004 #define BCHP_WAKEUP_CTRL2_CLEAR_UART0_SHIFT 2 /* WAKEUP_CTRL2 :: CLEAR :: WAKEUP_TIMER [01:01] */ #define BCHP_WAKEUP_CTRL2_CLEAR_WAKEUP_TIMER_MASK 0x00000002 #define BCHP_WAKEUP_CTRL2_CLEAR_WAKEUP_TIMER_SHIFT 1 /* WAKEUP_CTRL2 :: CLEAR :: IRR [00:00] */ #define BCHP_WAKEUP_CTRL2_CLEAR_IRR_MASK 0x00000001 #define BCHP_WAKEUP_CTRL2_CLEAR_IRR_SHIFT 0 /*************************************************************************** *MASK_STATUS - Wake-Up Mask Status Register ***************************************************************************/ /* WAKEUP_CTRL2 :: MASK_STATUS :: reserved0 [31:06] */ #define BCHP_WAKEUP_CTRL2_MASK_STATUS_reserved0_MASK 0xffffffc0 #define BCHP_WAKEUP_CTRL2_MASK_STATUS_reserved0_SHIFT 6 /* WAKEUP_CTRL2 :: MASK_STATUS :: GIO [05:05] */ #define BCHP_WAKEUP_CTRL2_MASK_STATUS_GIO_MASK 0x00000020 #define BCHP_WAKEUP_CTRL2_MASK_STATUS_GIO_SHIFT 5 /* WAKEUP_CTRL2 :: MASK_STATUS :: UART2 [04:04] */ #define BCHP_WAKEUP_CTRL2_MASK_STATUS_UART2_MASK 0x00000010 #define BCHP_WAKEUP_CTRL2_MASK_STATUS_UART2_SHIFT 4 /* WAKEUP_CTRL2 :: MASK_STATUS :: UART1 [03:03] */ #define BCHP_WAKEUP_CTRL2_MASK_STATUS_UART1_MASK 0x00000008 #define BCHP_WAKEUP_CTRL2_MASK_STATUS_UART1_SHIFT 3 /* WAKEUP_CTRL2 :: MASK_STATUS :: UART0 [02:02] */ #define BCHP_WAKEUP_CTRL2_MASK_STATUS_UART0_MASK 0x00000004 #define BCHP_WAKEUP_CTRL2_MASK_STATUS_UART0_SHIFT 2 /* WAKEUP_CTRL2 :: MASK_STATUS :: WAKEUP_TIMER [01:01] */ #define BCHP_WAKEUP_CTRL2_MASK_STATUS_WAKEUP_TIMER_MASK 0x00000002 #define BCHP_WAKEUP_CTRL2_MASK_STATUS_WAKEUP_TIMER_SHIFT 1 /* WAKEUP_CTRL2 :: MASK_STATUS :: IRR [00:00] */ #define BCHP_WAKEUP_CTRL2_MASK_STATUS_IRR_MASK 0x00000001 #define BCHP_WAKEUP_CTRL2_MASK_STATUS_IRR_SHIFT 0 /*************************************************************************** *MASK_SET - Wake-Up Mask Set Register ***************************************************************************/ /* WAKEUP_CTRL2 :: MASK_SET :: reserved0 [31:06] */ #define BCHP_WAKEUP_CTRL2_MASK_SET_reserved0_MASK 0xffffffc0 #define BCHP_WAKEUP_CTRL2_MASK_SET_reserved0_SHIFT 6 /* WAKEUP_CTRL2 :: MASK_SET :: GIO [05:05] */ #define BCHP_WAKEUP_CTRL2_MASK_SET_GIO_MASK 0x00000020 #define BCHP_WAKEUP_CTRL2_MASK_SET_GIO_SHIFT 5 /* WAKEUP_CTRL2 :: MASK_SET :: UART2 [04:04] */ #define BCHP_WAKEUP_CTRL2_MASK_SET_UART2_MASK 0x00000010 #define BCHP_WAKEUP_CTRL2_MASK_SET_UART2_SHIFT 4 /* WAKEUP_CTRL2 :: MASK_SET :: UART1 [03:03] */ #define BCHP_WAKEUP_CTRL2_MASK_SET_UART1_MASK 0x00000008 #define BCHP_WAKEUP_CTRL2_MASK_SET_UART1_SHIFT 3 /* WAKEUP_CTRL2 :: MASK_SET :: UART0 [02:02] */ #define BCHP_WAKEUP_CTRL2_MASK_SET_UART0_MASK 0x00000004 #define BCHP_WAKEUP_CTRL2_MASK_SET_UART0_SHIFT 2 /* WAKEUP_CTRL2 :: MASK_SET :: WAKEUP_TIMER [01:01] */ #define BCHP_WAKEUP_CTRL2_MASK_SET_WAKEUP_TIMER_MASK 0x00000002 #define BCHP_WAKEUP_CTRL2_MASK_SET_WAKEUP_TIMER_SHIFT 1 /* WAKEUP_CTRL2 :: MASK_SET :: IRR [00:00] */ #define BCHP_WAKEUP_CTRL2_MASK_SET_IRR_MASK 0x00000001 #define BCHP_WAKEUP_CTRL2_MASK_SET_IRR_SHIFT 0 /*************************************************************************** *MASK_CLEAR - Wake-Up Mask Clear Register ***************************************************************************/ /* WAKEUP_CTRL2 :: MASK_CLEAR :: reserved0 [31:06] */ #define BCHP_WAKEUP_CTRL2_MASK_CLEAR_reserved0_MASK 0xffffffc0 #define BCHP_WAKEUP_CTRL2_MASK_CLEAR_reserved0_SHIFT 6 /* WAKEUP_CTRL2 :: MASK_CLEAR :: GIO [05:05] */ #define BCHP_WAKEUP_CTRL2_MASK_CLEAR_GIO_MASK 0x00000020 #define BCHP_WAKEUP_CTRL2_MASK_CLEAR_GIO_SHIFT 5 /* WAKEUP_CTRL2 :: MASK_CLEAR :: UART2 [04:04] */ #define BCHP_WAKEUP_CTRL2_MASK_CLEAR_UART2_MASK 0x00000010 #define BCHP_WAKEUP_CTRL2_MASK_CLEAR_UART2_SHIFT 4 /* WAKEUP_CTRL2 :: MASK_CLEAR :: UART1 [03:03] */ #define BCHP_WAKEUP_CTRL2_MASK_CLEAR_UART1_MASK 0x00000008 #define BCHP_WAKEUP_CTRL2_MASK_CLEAR_UART1_SHIFT 3 /* WAKEUP_CTRL2 :: MASK_CLEAR :: UART0 [02:02] */ #define BCHP_WAKEUP_CTRL2_MASK_CLEAR_UART0_MASK 0x00000004 #define BCHP_WAKEUP_CTRL2_MASK_CLEAR_UART0_SHIFT 2 /* WAKEUP_CTRL2 :: MASK_CLEAR :: WAKEUP_TIMER [01:01] */ #define BCHP_WAKEUP_CTRL2_MASK_CLEAR_WAKEUP_TIMER_MASK 0x00000002 #define BCHP_WAKEUP_CTRL2_MASK_CLEAR_WAKEUP_TIMER_SHIFT 1 /* WAKEUP_CTRL2 :: MASK_CLEAR :: IRR [00:00] */ #define BCHP_WAKEUP_CTRL2_MASK_CLEAR_IRR_MASK 0x00000001 #define BCHP_WAKEUP_CTRL2_MASK_CLEAR_IRR_SHIFT 0 #endif /* #ifndef BCHP_WAKEUP_CTRL2_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015000000000000011561 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb0000644000175000017500000007302211610313111031036 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_xpt_pb0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:24p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:42 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb0.h $ * * Hydra_Software_Devel/1 7/17/09 8:24p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_XPT_PB0_H__ #define BCHP_XPT_PB0_H__ /*************************************************************************** *XPT_PB0 - Playback 0 Control Registers ***************************************************************************/ #define BCHP_XPT_PB0_CTRL1 0x0020b000 /* Playback Control 1 Register */ #define BCHP_XPT_PB0_CTRL2 0x0020b004 /* Playback Control 2 Register */ #define BCHP_XPT_PB0_CTRL3 0x0020b008 /* Playback Control 3 Register */ #define BCHP_XPT_PB0_CTRL4 0x0020b00c /* Playback Control 4 Register */ #define BCHP_XPT_PB0_FIRST_DESC_ADDR 0x0020b010 /* Playback First Descriptor Address Register */ #define BCHP_XPT_PB0_CURR_DESC_ADDR 0x0020b014 /* Playback Current Descriptor Address Register */ #define BCHP_XPT_PB0_CURR_BUFF_ADDR 0x0020b018 /* Playback Current Buffer Address Register */ #define BCHP_XPT_PB0_BLOCKOUT 0x0020b01c /* Data Transport Playback Block Out Control */ #define BCHP_XPT_PB0_PKTZ_CONTEXT0 0x0020b020 /* Data Transport Playback Packetize Mode Context 0 Control */ #define BCHP_XPT_PB0_PKTZ_CONTEXT1 0x0020b024 /* Data Transport Playback Packetize Mode Context 1 Control */ #define BCHP_XPT_PB0_PKTZ_CONTEXT2 0x0020b028 /* Data Transport Playback Packetize Mode Context 2 Control */ #define BCHP_XPT_PB0_PKTZ_CONTEXT3 0x0020b02c /* Data Transport Playback Packetize Mode Context 3 Control */ #define BCHP_XPT_PB0_TS_ERR_BOUND 0x0020b030 /* Data Transport Playback Timestamp Error Bound Register */ #define BCHP_XPT_PB0_PARSER_CTRL1 0x0020b034 /* Data Transport Playback Parser Control Register */ #define BCHP_XPT_PB0_PARSER_CTRL2 0x0020b038 /* Data Transport Playback Parser Control Register 2 */ #define BCHP_XPT_PB0_PARSER_TIMESTAMP 0x0020b03c /* Data Transport Playback Parser Local Timestamp */ #define BCHP_XPT_PB0_INTR 0x0020b040 /* Playback Processing Error and Status Interrupt Register */ #define BCHP_XPT_PB0_INTR_EN 0x0020b044 /* Playback Processing Error and Status Interrupt Enable Register */ #define BCHP_XPT_PB0_INTR_TAGS 0x0020b048 /* Playback Interrupt Tag Register */ /*************************************************************************** *CTRL1 - Playback Control 1 Register ***************************************************************************/ /* XPT_PB0 :: CTRL1 :: reserved0 [31:06] */ #define BCHP_XPT_PB0_CTRL1_reserved0_MASK 0xffffffc0 #define BCHP_XPT_PB0_CTRL1_reserved0_SHIFT 6 /* XPT_PB0 :: CTRL1 :: WAKE_MODE [05:05] */ #define BCHP_XPT_PB0_CTRL1_WAKE_MODE_MASK 0x00000020 #define BCHP_XPT_PB0_CTRL1_WAKE_MODE_SHIFT 5 /* XPT_PB0 :: CTRL1 :: OUT_OF_SYNC_STATUS [04:04] */ #define BCHP_XPT_PB0_CTRL1_OUT_OF_SYNC_STATUS_MASK 0x00000010 #define BCHP_XPT_PB0_CTRL1_OUT_OF_SYNC_STATUS_SHIFT 4 /* XPT_PB0 :: CTRL1 :: FINISHED [03:03] */ #define BCHP_XPT_PB0_CTRL1_FINISHED_MASK 0x00000008 #define BCHP_XPT_PB0_CTRL1_FINISHED_SHIFT 3 /* XPT_PB0 :: CTRL1 :: BUSY [02:02] */ #define BCHP_XPT_PB0_CTRL1_BUSY_MASK 0x00000004 #define BCHP_XPT_PB0_CTRL1_BUSY_SHIFT 2 /* XPT_PB0 :: CTRL1 :: RUN [01:01] */ #define BCHP_XPT_PB0_CTRL1_RUN_MASK 0x00000002 #define BCHP_XPT_PB0_CTRL1_RUN_SHIFT 1 /* XPT_PB0 :: CTRL1 :: WAKE [00:00] */ #define BCHP_XPT_PB0_CTRL1_WAKE_MASK 0x00000001 #define BCHP_XPT_PB0_CTRL1_WAKE_SHIFT 0 /*************************************************************************** *CTRL2 - Playback Control 2 Register ***************************************************************************/ /* XPT_PB0 :: CTRL2 :: reserved0 [31:25] */ #define BCHP_XPT_PB0_CTRL2_reserved0_MASK 0xfe000000 #define BCHP_XPT_PB0_CTRL2_reserved0_SHIFT 25 /* XPT_PB0 :: CTRL2 :: REARM_TS_COUNTER [24:24] */ #define BCHP_XPT_PB0_CTRL2_REARM_TS_COUNTER_MASK 0x01000000 #define BCHP_XPT_PB0_CTRL2_REARM_TS_COUNTER_SHIFT 24 /* XPT_PB0 :: CTRL2 :: TIMESTAMP_MODE_32BIT [23:23] */ #define BCHP_XPT_PB0_CTRL2_TIMESTAMP_MODE_32BIT_MASK 0x00800000 #define BCHP_XPT_PB0_CTRL2_TIMESTAMP_MODE_32BIT_SHIFT 23 /* XPT_PB0 :: CTRL2 :: PROGRAM_STREAM_MODE [22:22] */ #define BCHP_XPT_PB0_CTRL2_PROGRAM_STREAM_MODE_MASK 0x00400000 #define BCHP_XPT_PB0_CTRL2_PROGRAM_STREAM_MODE_SHIFT 22 /* XPT_PB0 :: CTRL2 :: TS_PARITY_CHECK_DIS [21:21] */ #define BCHP_XPT_PB0_CTRL2_TS_PARITY_CHECK_DIS_MASK 0x00200000 #define BCHP_XPT_PB0_CTRL2_TS_PARITY_CHECK_DIS_SHIFT 21 /* XPT_PB0 :: CTRL2 :: TIMESTAMP_EN [20:20] */ #define BCHP_XPT_PB0_CTRL2_TIMESTAMP_EN_MASK 0x00100000 #define BCHP_XPT_PB0_CTRL2_TIMESTAMP_EN_SHIFT 20 /* XPT_PB0 :: CTRL2 :: SYNC_EXT_MODE [19:17] */ #define BCHP_XPT_PB0_CTRL2_SYNC_EXT_MODE_MASK 0x000e0000 #define BCHP_XPT_PB0_CTRL2_SYNC_EXT_MODE_SHIFT 17 /* XPT_PB0 :: CTRL2 :: reserved1 [16:09] */ #define BCHP_XPT_PB0_CTRL2_reserved1_MASK 0x0001fe00 #define BCHP_XPT_PB0_CTRL2_reserved1_SHIFT 9 /* XPT_PB0 :: CTRL2 :: MICRO_PAUSE [08:08] */ #define BCHP_XPT_PB0_CTRL2_MICRO_PAUSE_MASK 0x00000100 #define BCHP_XPT_PB0_CTRL2_MICRO_PAUSE_SHIFT 8 /* XPT_PB0 :: CTRL2 :: ENDIAN_CTRL [07:07] */ #define BCHP_XPT_PB0_CTRL2_ENDIAN_CTRL_MASK 0x00000080 #define BCHP_XPT_PB0_CTRL2_ENDIAN_CTRL_SHIFT 7 /* XPT_PB0 :: CTRL2 :: reserved2 [06:06] */ #define BCHP_XPT_PB0_CTRL2_reserved2_MASK 0x00000040 #define BCHP_XPT_PB0_CTRL2_reserved2_SHIFT 6 /* XPT_PB0 :: CTRL2 :: TS_RANGE_MODE [05:05] */ #define BCHP_XPT_PB0_CTRL2_TS_RANGE_MODE_MASK 0x00000020 #define BCHP_XPT_PB0_CTRL2_TS_RANGE_MODE_SHIFT 5 /* XPT_PB0 :: CTRL2 :: PACING_START [04:04] */ #define BCHP_XPT_PB0_CTRL2_PACING_START_MASK 0x00000010 #define BCHP_XPT_PB0_CTRL2_PACING_START_SHIFT 4 /* XPT_PB0 :: CTRL2 :: PACING_EN [03:03] */ #define BCHP_XPT_PB0_CTRL2_PACING_EN_MASK 0x00000008 #define BCHP_XPT_PB0_CTRL2_PACING_EN_SHIFT 3 /* XPT_PB0 :: CTRL2 :: PACING_OFFSET_ADJ_DIS [02:02] */ #define BCHP_XPT_PB0_CTRL2_PACING_OFFSET_ADJ_DIS_MASK 0x00000004 #define BCHP_XPT_PB0_CTRL2_PACING_OFFSET_ADJ_DIS_SHIFT 2 /* XPT_PB0 :: CTRL2 :: PACING_AUTOSTART_EN [01:01] */ #define BCHP_XPT_PB0_CTRL2_PACING_AUTOSTART_EN_MASK 0x00000002 #define BCHP_XPT_PB0_CTRL2_PACING_AUTOSTART_EN_SHIFT 1 /* XPT_PB0 :: CTRL2 :: PROGRAM_STREAM_EN [00:00] */ #define BCHP_XPT_PB0_CTRL2_PROGRAM_STREAM_EN_MASK 0x00000001 #define BCHP_XPT_PB0_CTRL2_PROGRAM_STREAM_EN_SHIFT 0 /*************************************************************************** *CTRL3 - Playback Control 3 Register ***************************************************************************/ /* XPT_PB0 :: CTRL3 :: DIRECTV_SYNC_OUT_CNT [31:28] */ #define BCHP_XPT_PB0_CTRL3_DIRECTV_SYNC_OUT_CNT_MASK 0xf0000000 #define BCHP_XPT_PB0_CTRL3_DIRECTV_SYNC_OUT_CNT_SHIFT 28 /* XPT_PB0 :: CTRL3 :: DIRECTV_SYNC_IN_CNT [27:24] */ #define BCHP_XPT_PB0_CTRL3_DIRECTV_SYNC_IN_CNT_MASK 0x0f000000 #define BCHP_XPT_PB0_CTRL3_DIRECTV_SYNC_IN_CNT_SHIFT 24 /* XPT_PB0 :: CTRL3 :: SYNC_ID_HI [23:16] */ #define BCHP_XPT_PB0_CTRL3_SYNC_ID_HI_MASK 0x00ff0000 #define BCHP_XPT_PB0_CTRL3_SYNC_ID_HI_SHIFT 16 /* XPT_PB0 :: CTRL3 :: SYNC_ID_LO [15:08] */ #define BCHP_XPT_PB0_CTRL3_SYNC_ID_LO_MASK 0x0000ff00 #define BCHP_XPT_PB0_CTRL3_SYNC_ID_LO_SHIFT 8 /* XPT_PB0 :: CTRL3 :: SYNC_LENGTH [07:00] */ #define BCHP_XPT_PB0_CTRL3_SYNC_LENGTH_MASK 0x000000ff #define BCHP_XPT_PB0_CTRL3_SYNC_LENGTH_SHIFT 0 /*************************************************************************** *CTRL4 - Playback Control 4 Register ***************************************************************************/ /* XPT_PB0 :: CTRL4 :: reserved0 [31:31] */ #define BCHP_XPT_PB0_CTRL4_reserved0_MASK 0x80000000 #define BCHP_XPT_PB0_CTRL4_reserved0_SHIFT 31 /* XPT_PB0 :: CTRL4 :: TS_USER_BITS_VALID [30:30] */ #define BCHP_XPT_PB0_CTRL4_TS_USER_BITS_VALID_MASK 0x40000000 #define BCHP_XPT_PB0_CTRL4_TS_USER_BITS_VALID_SHIFT 30 /* XPT_PB0 :: CTRL4 :: PKTZ_PACK_HDR_DROP_MODE [29:29] */ #define BCHP_XPT_PB0_CTRL4_PKTZ_PACK_HDR_DROP_MODE_MASK 0x20000000 #define BCHP_XPT_PB0_CTRL4_PKTZ_PACK_HDR_DROP_MODE_SHIFT 29 /* XPT_PB0 :: CTRL4 :: PKTZ_PACK_HDR_INSERT_EN [28:28] */ #define BCHP_XPT_PB0_CTRL4_PKTZ_PACK_HDR_INSERT_EN_MASK 0x10000000 #define BCHP_XPT_PB0_CTRL4_PKTZ_PACK_HDR_INSERT_EN_SHIFT 28 /* XPT_PB0 :: CTRL4 :: PKTZ_SUB_ID_EN [27:27] */ #define BCHP_XPT_PB0_CTRL4_PKTZ_SUB_ID_EN_MASK 0x08000000 #define BCHP_XPT_PB0_CTRL4_PKTZ_SUB_ID_EN_SHIFT 27 /* XPT_PB0 :: CTRL4 :: PKTZ_STREAM_ID_EXT_EN [26:26] */ #define BCHP_XPT_PB0_CTRL4_PKTZ_STREAM_ID_EXT_EN_MASK 0x04000000 #define BCHP_XPT_PB0_CTRL4_PKTZ_STREAM_ID_EXT_EN_SHIFT 26 /* XPT_PB0 :: CTRL4 :: PKTZ_PT_EN [25:25] */ #define BCHP_XPT_PB0_CTRL4_PKTZ_PT_EN_MASK 0x02000000 #define BCHP_XPT_PB0_CTRL4_PKTZ_PT_EN_SHIFT 25 /* XPT_PB0 :: CTRL4 :: PKTZ_PUSI_SET_DIS [24:24] */ #define BCHP_XPT_PB0_CTRL4_PKTZ_PUSI_SET_DIS_MASK 0x01000000 #define BCHP_XPT_PB0_CTRL4_PKTZ_PUSI_SET_DIS_SHIFT 24 /* XPT_PB0 :: CTRL4 :: PKTZ_CONTEXT_EN [23:23] */ #define BCHP_XPT_PB0_CTRL4_PKTZ_CONTEXT_EN_MASK 0x00800000 #define BCHP_XPT_PB0_CTRL4_PKTZ_CONTEXT_EN_SHIFT 23 /* XPT_PB0 :: CTRL4 :: PACKETIZE_EN [22:22] */ #define BCHP_XPT_PB0_CTRL4_PACKETIZE_EN_MASK 0x00400000 #define BCHP_XPT_PB0_CTRL4_PACKETIZE_EN_SHIFT 22 /* XPT_PB0 :: CTRL4 :: HW_PAUSE [21:21] */ #define BCHP_XPT_PB0_CTRL4_HW_PAUSE_MASK 0x00200000 #define BCHP_XPT_PB0_CTRL4_HW_PAUSE_SHIFT 21 /* XPT_PB0 :: CTRL4 :: MEM_ARB_MODE [20:20] */ #define BCHP_XPT_PB0_CTRL4_MEM_ARB_MODE_MASK 0x00100000 #define BCHP_XPT_PB0_CTRL4_MEM_ARB_MODE_SHIFT 20 /* XPT_PB0 :: CTRL4 :: OUTPUT_PIPE_SEL [19:19] */ #define BCHP_XPT_PB0_CTRL4_OUTPUT_PIPE_SEL_MASK 0x00080000 #define BCHP_XPT_PB0_CTRL4_OUTPUT_PIPE_SEL_SHIFT 19 /* XPT_PB0 :: CTRL4 :: TIMEBASE_SEL_MSB [18:18] */ #define BCHP_XPT_PB0_CTRL4_TIMEBASE_SEL_MSB_MASK 0x00040000 #define BCHP_XPT_PB0_CTRL4_TIMEBASE_SEL_MSB_SHIFT 18 /* XPT_PB0 :: CTRL4 :: TIMESTAMP_USER_BITS [17:16] */ #define BCHP_XPT_PB0_CTRL4_TIMESTAMP_USER_BITS_MASK 0x00030000 #define BCHP_XPT_PB0_CTRL4_TIMESTAMP_USER_BITS_SHIFT 16 /* XPT_PB0 :: CTRL4 :: TIMEBASE_SEL [15:14] */ #define BCHP_XPT_PB0_CTRL4_TIMEBASE_SEL_MASK 0x0000c000 #define BCHP_XPT_PB0_CTRL4_TIMEBASE_SEL_SHIFT 14 /* XPT_PB0 :: CTRL4 :: TIMESTAMP_MODE [13:12] */ #define BCHP_XPT_PB0_CTRL4_TIMESTAMP_MODE_MASK 0x00003000 #define BCHP_XPT_PB0_CTRL4_TIMESTAMP_MODE_SHIFT 12 /* XPT_PB0 :: CTRL4 :: PARSER_FORCE_RESTAMP [11:11] */ #define BCHP_XPT_PB0_CTRL4_PARSER_FORCE_RESTAMP_MASK 0x00000800 #define BCHP_XPT_PB0_CTRL4_PARSER_FORCE_RESTAMP_SHIFT 11 /* XPT_PB0 :: CTRL4 :: reserved_for_eco1 [10:10] */ #define BCHP_XPT_PB0_CTRL4_reserved_for_eco1_MASK 0x00000400 #define BCHP_XPT_PB0_CTRL4_reserved_for_eco1_SHIFT 10 /* XPT_PB0 :: CTRL4 :: reserved2 [09:00] */ #define BCHP_XPT_PB0_CTRL4_reserved2_MASK 0x000003ff #define BCHP_XPT_PB0_CTRL4_reserved2_SHIFT 0 /*************************************************************************** *FIRST_DESC_ADDR - Playback First Descriptor Address Register ***************************************************************************/ /* XPT_PB0 :: FIRST_DESC_ADDR :: FIRST_DESC_ADDR [31:04] */ #define BCHP_XPT_PB0_FIRST_DESC_ADDR_FIRST_DESC_ADDR_MASK 0xfffffff0 #define BCHP_XPT_PB0_FIRST_DESC_ADDR_FIRST_DESC_ADDR_SHIFT 4 /* XPT_PB0 :: FIRST_DESC_ADDR :: reserved0 [03:00] */ #define BCHP_XPT_PB0_FIRST_DESC_ADDR_reserved0_MASK 0x0000000f #define BCHP_XPT_PB0_FIRST_DESC_ADDR_reserved0_SHIFT 0 /*************************************************************************** *CURR_DESC_ADDR - Playback Current Descriptor Address Register ***************************************************************************/ /* XPT_PB0 :: CURR_DESC_ADDR :: CURR_DESC_ADDR [31:04] */ #define BCHP_XPT_PB0_CURR_DESC_ADDR_CURR_DESC_ADDR_MASK 0xfffffff0 #define BCHP_XPT_PB0_CURR_DESC_ADDR_CURR_DESC_ADDR_SHIFT 4 /* XPT_PB0 :: CURR_DESC_ADDR :: FINISHED_SHADOW [03:03] */ #define BCHP_XPT_PB0_CURR_DESC_ADDR_FINISHED_SHADOW_MASK 0x00000008 #define BCHP_XPT_PB0_CURR_DESC_ADDR_FINISHED_SHADOW_SHIFT 3 /* XPT_PB0 :: CURR_DESC_ADDR :: BUSY_SHADOW [02:02] */ #define BCHP_XPT_PB0_CURR_DESC_ADDR_BUSY_SHADOW_MASK 0x00000004 #define BCHP_XPT_PB0_CURR_DESC_ADDR_BUSY_SHADOW_SHIFT 2 /* XPT_PB0 :: CURR_DESC_ADDR :: CURR_DESC_NOT_DONE [01:01] */ #define BCHP_XPT_PB0_CURR_DESC_ADDR_CURR_DESC_NOT_DONE_MASK 0x00000002 #define BCHP_XPT_PB0_CURR_DESC_ADDR_CURR_DESC_NOT_DONE_SHIFT 1 /* XPT_PB0 :: CURR_DESC_ADDR :: reserved0 [00:00] */ #define BCHP_XPT_PB0_CURR_DESC_ADDR_reserved0_MASK 0x00000001 #define BCHP_XPT_PB0_CURR_DESC_ADDR_reserved0_SHIFT 0 /*************************************************************************** *CURR_BUFF_ADDR - Playback Current Buffer Address Register ***************************************************************************/ /* XPT_PB0 :: CURR_BUFF_ADDR :: CURR_BUFF_ADDR [31:00] */ #define BCHP_XPT_PB0_CURR_BUFF_ADDR_CURR_BUFF_ADDR_MASK 0xffffffff #define BCHP_XPT_PB0_CURR_BUFF_ADDR_CURR_BUFF_ADDR_SHIFT 0 /*************************************************************************** *BLOCKOUT - Data Transport Playback Block Out Control ***************************************************************************/ /* XPT_PB0 :: BLOCKOUT :: reserved0 [31:25] */ #define BCHP_XPT_PB0_BLOCKOUT_reserved0_MASK 0xfe000000 #define BCHP_XPT_PB0_BLOCKOUT_reserved0_SHIFT 25 /* XPT_PB0 :: BLOCKOUT :: BO_SPARE_BW_EN [24:24] */ #define BCHP_XPT_PB0_BLOCKOUT_BO_SPARE_BW_EN_MASK 0x01000000 #define BCHP_XPT_PB0_BLOCKOUT_BO_SPARE_BW_EN_SHIFT 24 /* XPT_PB0 :: BLOCKOUT :: BO_COUNT [23:00] */ #define BCHP_XPT_PB0_BLOCKOUT_BO_COUNT_MASK 0x00ffffff #define BCHP_XPT_PB0_BLOCKOUT_BO_COUNT_SHIFT 0 /*************************************************************************** *PKTZ_CONTEXT0 - Data Transport Playback Packetize Mode Context 0 Control ***************************************************************************/ /* XPT_PB0 :: PKTZ_CONTEXT0 :: reserved0 [31:29] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT0_reserved0_MASK 0xe0000000 #define BCHP_XPT_PB0_PKTZ_CONTEXT0_reserved0_SHIFT 29 /* XPT_PB0 :: PKTZ_CONTEXT0 :: PID [28:16] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT0_PID_MASK 0x1fff0000 #define BCHP_XPT_PB0_PKTZ_CONTEXT0_PID_SHIFT 16 /* XPT_PB0 :: PKTZ_CONTEXT0 :: CH_NUM [15:08] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT0_CH_NUM_MASK 0x0000ff00 #define BCHP_XPT_PB0_PKTZ_CONTEXT0_CH_NUM_SHIFT 8 /* XPT_PB0 :: PKTZ_CONTEXT0 :: PES_STREAM_ID [07:00] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT0_PES_STREAM_ID_MASK 0x000000ff #define BCHP_XPT_PB0_PKTZ_CONTEXT0_PES_STREAM_ID_SHIFT 0 /*************************************************************************** *PKTZ_CONTEXT1 - Data Transport Playback Packetize Mode Context 1 Control ***************************************************************************/ /* XPT_PB0 :: PKTZ_CONTEXT1 :: reserved0 [31:29] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT1_reserved0_MASK 0xe0000000 #define BCHP_XPT_PB0_PKTZ_CONTEXT1_reserved0_SHIFT 29 /* XPT_PB0 :: PKTZ_CONTEXT1 :: PID [28:16] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT1_PID_MASK 0x1fff0000 #define BCHP_XPT_PB0_PKTZ_CONTEXT1_PID_SHIFT 16 /* XPT_PB0 :: PKTZ_CONTEXT1 :: CH_NUM [15:08] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT1_CH_NUM_MASK 0x0000ff00 #define BCHP_XPT_PB0_PKTZ_CONTEXT1_CH_NUM_SHIFT 8 /* XPT_PB0 :: PKTZ_CONTEXT1 :: PES_STREAM_ID [07:00] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT1_PES_STREAM_ID_MASK 0x000000ff #define BCHP_XPT_PB0_PKTZ_CONTEXT1_PES_STREAM_ID_SHIFT 0 /*************************************************************************** *PKTZ_CONTEXT2 - Data Transport Playback Packetize Mode Context 2 Control ***************************************************************************/ /* XPT_PB0 :: PKTZ_CONTEXT2 :: reserved0 [31:29] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT2_reserved0_MASK 0xe0000000 #define BCHP_XPT_PB0_PKTZ_CONTEXT2_reserved0_SHIFT 29 /* XPT_PB0 :: PKTZ_CONTEXT2 :: PID [28:16] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT2_PID_MASK 0x1fff0000 #define BCHP_XPT_PB0_PKTZ_CONTEXT2_PID_SHIFT 16 /* XPT_PB0 :: PKTZ_CONTEXT2 :: CH_NUM [15:08] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT2_CH_NUM_MASK 0x0000ff00 #define BCHP_XPT_PB0_PKTZ_CONTEXT2_CH_NUM_SHIFT 8 /* XPT_PB0 :: PKTZ_CONTEXT2 :: PES_STREAM_ID [07:00] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT2_PES_STREAM_ID_MASK 0x000000ff #define BCHP_XPT_PB0_PKTZ_CONTEXT2_PES_STREAM_ID_SHIFT 0 /*************************************************************************** *PKTZ_CONTEXT3 - Data Transport Playback Packetize Mode Context 3 Control ***************************************************************************/ /* XPT_PB0 :: PKTZ_CONTEXT3 :: reserved0 [31:29] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT3_reserved0_MASK 0xe0000000 #define BCHP_XPT_PB0_PKTZ_CONTEXT3_reserved0_SHIFT 29 /* XPT_PB0 :: PKTZ_CONTEXT3 :: PID [28:16] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT3_PID_MASK 0x1fff0000 #define BCHP_XPT_PB0_PKTZ_CONTEXT3_PID_SHIFT 16 /* XPT_PB0 :: PKTZ_CONTEXT3 :: CH_NUM [15:08] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT3_CH_NUM_MASK 0x0000ff00 #define BCHP_XPT_PB0_PKTZ_CONTEXT3_CH_NUM_SHIFT 8 /* XPT_PB0 :: PKTZ_CONTEXT3 :: PES_STREAM_ID [07:00] */ #define BCHP_XPT_PB0_PKTZ_CONTEXT3_PES_STREAM_ID_MASK 0x000000ff #define BCHP_XPT_PB0_PKTZ_CONTEXT3_PES_STREAM_ID_SHIFT 0 /*************************************************************************** *TS_ERR_BOUND - Data Transport Playback Timestamp Error Bound Register ***************************************************************************/ /* XPT_PB0 :: TS_ERR_BOUND :: reserved0 [31:19] */ #define BCHP_XPT_PB0_TS_ERR_BOUND_reserved0_MASK 0xfff80000 #define BCHP_XPT_PB0_TS_ERR_BOUND_reserved0_SHIFT 19 /* XPT_PB0 :: TS_ERR_BOUND :: TS_ERR_BOUND [18:00] */ #define BCHP_XPT_PB0_TS_ERR_BOUND_TS_ERR_BOUND_MASK 0x0007ffff #define BCHP_XPT_PB0_TS_ERR_BOUND_TS_ERR_BOUND_SHIFT 0 /*************************************************************************** *PARSER_CTRL1 - Data Transport Playback Parser Control Register ***************************************************************************/ /* XPT_PB0 :: PARSER_CTRL1 :: PARSER_TIMEBASE_SEL [31:29] */ #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_TIMEBASE_SEL_MASK 0xe0000000 #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_TIMEBASE_SEL_SHIFT 29 /* XPT_PB0 :: PARSER_CTRL1 :: PARSER_TIMESTAMP_MODE [28:27] */ #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_TIMESTAMP_MODE_MASK 0x18000000 #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_TIMESTAMP_MODE_SHIFT 27 /* XPT_PB0 :: PARSER_CTRL1 :: reserved0 [26:21] */ #define BCHP_XPT_PB0_PARSER_CTRL1_reserved0_MASK 0x07e00000 #define BCHP_XPT_PB0_PARSER_CTRL1_reserved0_SHIFT 21 /* XPT_PB0 :: PARSER_CTRL1 :: PARSER_ACCEPT_ADAPT_00 [20:20] */ #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ACCEPT_ADAPT_00_MASK 0x00100000 #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ACCEPT_ADAPT_00_SHIFT 20 /* XPT_PB0 :: PARSER_CTRL1 :: PARSER_PKT_LENGTH [19:12] */ #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_PKT_LENGTH_MASK 0x000ff000 #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_PKT_LENGTH_SHIFT 12 /* XPT_PB0 :: PARSER_CTRL1 :: reserved1 [11:08] */ #define BCHP_XPT_PB0_PARSER_CTRL1_reserved1_MASK 0x00000f00 #define BCHP_XPT_PB0_PARSER_CTRL1_reserved1_SHIFT 8 /* XPT_PB0 :: PARSER_CTRL1 :: PARSER_PACKET_TYPE [07:05] */ #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_PACKET_TYPE_MASK 0x000000e0 #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_PACKET_TYPE_SHIFT 5 /* XPT_PB0 :: PARSER_CTRL1 :: PARSER_ACCEPT_NULL_PKT [04:04] */ #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ACCEPT_NULL_PKT_MASK 0x00000010 #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ACCEPT_NULL_PKT_SHIFT 4 /* XPT_PB0 :: PARSER_CTRL1 :: PARSER_CONT_COUNT_IGNORE [03:03] */ #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_CONT_COUNT_IGNORE_MASK 0x00000008 #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_CONT_COUNT_IGNORE_SHIFT 3 /* XPT_PB0 :: PARSER_CTRL1 :: PARSER_ERROR_INPUT_TEI_IGNORE [02:02] */ #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_MASK 0x00000004 #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ERROR_INPUT_TEI_IGNORE_SHIFT 2 /* XPT_PB0 :: PARSER_CTRL1 :: PARSER_ALL_PASS_CTRL [01:01] */ #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ALL_PASS_CTRL_MASK 0x00000002 #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ALL_PASS_CTRL_SHIFT 1 /* XPT_PB0 :: PARSER_CTRL1 :: PARSER_ENABLE [00:00] */ #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ENABLE_MASK 0x00000001 #define BCHP_XPT_PB0_PARSER_CTRL1_PARSER_ENABLE_SHIFT 0 /*************************************************************************** *PARSER_CTRL2 - Data Transport Playback Parser Control Register 2 ***************************************************************************/ /* XPT_PB0 :: PARSER_CTRL2 :: reserved0 [31:08] */ #define BCHP_XPT_PB0_PARSER_CTRL2_reserved0_MASK 0xffffff00 #define BCHP_XPT_PB0_PARSER_CTRL2_reserved0_SHIFT 8 /* XPT_PB0 :: PARSER_CTRL2 :: RAVE_CX_MODE [07:06] */ #define BCHP_XPT_PB0_PARSER_CTRL2_RAVE_CX_MODE_MASK 0x000000c0 #define BCHP_XPT_PB0_PARSER_CTRL2_RAVE_CX_MODE_SHIFT 6 /* XPT_PB0 :: PARSER_CTRL2 :: PARSER_SEC_CC_IGNORE [05:05] */ #define BCHP_XPT_PB0_PARSER_CTRL2_PARSER_SEC_CC_IGNORE_MASK 0x00000020 #define BCHP_XPT_PB0_PARSER_CTRL2_PARSER_SEC_CC_IGNORE_SHIFT 5 /* XPT_PB0 :: PARSER_CTRL2 :: reserved1 [04:00] */ #define BCHP_XPT_PB0_PARSER_CTRL2_reserved1_MASK 0x0000001f #define BCHP_XPT_PB0_PARSER_CTRL2_reserved1_SHIFT 0 /*************************************************************************** *PARSER_TIMESTAMP - Data Transport Playback Parser Local Timestamp ***************************************************************************/ /* XPT_PB0 :: PARSER_TIMESTAMP :: TIMESTAMP [31:00] */ #define BCHP_XPT_PB0_PARSER_TIMESTAMP_TIMESTAMP_MASK 0xffffffff #define BCHP_XPT_PB0_PARSER_TIMESTAMP_TIMESTAMP_SHIFT 0 /*************************************************************************** *INTR - Playback Processing Error and Status Interrupt Register ***************************************************************************/ /* XPT_PB0 :: INTR :: reserved0 [31:09] */ #define BCHP_XPT_PB0_INTR_reserved0_MASK 0xfffffe00 #define BCHP_XPT_PB0_INTR_reserved0_SHIFT 9 /* XPT_PB0 :: INTR :: PB_COPYRIGHT_CHANGE [08:08] */ #define BCHP_XPT_PB0_INTR_PB_COPYRIGHT_CHANGE_MASK 0x00000100 #define BCHP_XPT_PB0_INTR_PB_COPYRIGHT_CHANGE_SHIFT 8 /* XPT_PB0 :: INTR :: PARSER_TRANSPORT_ERROR [07:07] */ #define BCHP_XPT_PB0_INTR_PARSER_TRANSPORT_ERROR_MASK 0x00000080 #define BCHP_XPT_PB0_INTR_PARSER_TRANSPORT_ERROR_SHIFT 7 /* XPT_PB0 :: INTR :: PARSER_LENGTH_ERROR [06:06] */ #define BCHP_XPT_PB0_INTR_PARSER_LENGTH_ERROR_MASK 0x00000040 #define BCHP_XPT_PB0_INTR_PARSER_LENGTH_ERROR_SHIFT 6 /* XPT_PB0 :: INTR :: PARSER_SEC_CC_ERROR [05:05] */ #define BCHP_XPT_PB0_INTR_PARSER_SEC_CC_ERROR_MASK 0x00000020 #define BCHP_XPT_PB0_INTR_PARSER_SEC_CC_ERROR_SHIFT 5 /* XPT_PB0 :: INTR :: PARSER_CONTINUITY_ERROR [04:04] */ #define BCHP_XPT_PB0_INTR_PARSER_CONTINUITY_ERROR_MASK 0x00000010 #define BCHP_XPT_PB0_INTR_PARSER_CONTINUITY_ERROR_SHIFT 4 /* XPT_PB0 :: INTR :: TS_RANGE_ERROR [03:03] */ #define BCHP_XPT_PB0_INTR_TS_RANGE_ERROR_MASK 0x00000008 #define BCHP_XPT_PB0_INTR_TS_RANGE_ERROR_SHIFT 3 /* XPT_PB0 :: INTR :: TS_PARITY_ERROR [02:02] */ #define BCHP_XPT_PB0_INTR_TS_PARITY_ERROR_MASK 0x00000004 #define BCHP_XPT_PB0_INTR_TS_PARITY_ERROR_SHIFT 2 /* XPT_PB0 :: INTR :: SE_OUT_OF_SYNC_INT [01:01] */ #define BCHP_XPT_PB0_INTR_SE_OUT_OF_SYNC_INT_MASK 0x00000002 #define BCHP_XPT_PB0_INTR_SE_OUT_OF_SYNC_INT_SHIFT 1 /* XPT_PB0 :: INTR :: DONE_INT [00:00] */ #define BCHP_XPT_PB0_INTR_DONE_INT_MASK 0x00000001 #define BCHP_XPT_PB0_INTR_DONE_INT_SHIFT 0 /*************************************************************************** *INTR_EN - Playback Processing Error and Status Interrupt Enable Register ***************************************************************************/ /* XPT_PB0 :: INTR_EN :: reserved0 [31:09] */ #define BCHP_XPT_PB0_INTR_EN_reserved0_MASK 0xfffffe00 #define BCHP_XPT_PB0_INTR_EN_reserved0_SHIFT 9 /* XPT_PB0 :: INTR_EN :: INTR_EN [08:00] */ #define BCHP_XPT_PB0_INTR_EN_INTR_EN_MASK 0x000001ff #define BCHP_XPT_PB0_INTR_EN_INTR_EN_SHIFT 0 /*************************************************************************** *INTR_TAGS - Playback Interrupt Tag Register ***************************************************************************/ /* XPT_PB0 :: INTR_TAGS :: reserved0 [31:04] */ #define BCHP_XPT_PB0_INTR_TAGS_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PB0_INTR_TAGS_reserved0_SHIFT 4 /* XPT_PB0 :: INTR_TAGS :: PB_DESC_TAG_ID [03:00] */ #define BCHP_XPT_PB0_INTR_TAGS_PB_DESC_TAG_ID_MASK 0x0000000f #define BCHP_XPT_PB0_INTR_TAGS_PB_DESC_TAG_ID_SHIFT 0 #endif /* #ifndef BCHP_XPT_PB0_H__ */ /* End of File */ crystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_i2c.h0000644000175000017500000004552711610313111030456 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_i2c.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:07p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:05 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_i2c.h $ * * Hydra_Software_Devel/1 7/17/09 8:07p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_I2C_H__ #define BCHP_I2C_H__ /*************************************************************************** *I2C - I2C related registers ***************************************************************************/ #define BCHP_I2C_CHIP_ADDRESS 0x00501000 /* I2C Chip Address And Read/Write Control */ #define BCHP_I2C_DATA_IN0 0x00501004 /* I2C Write Data Byte 0 */ #define BCHP_I2C_DATA_IN1 0x00501008 /* I2C Write Data Byte 1 */ #define BCHP_I2C_DATA_IN2 0x0050100c /* I2C Write Data Byte 2 */ #define BCHP_I2C_DATA_IN3 0x00501010 /* I2C Write Data Byte 3 */ #define BCHP_I2C_DATA_IN4 0x00501014 /* I2C Write Data Byte 4 */ #define BCHP_I2C_DATA_IN5 0x00501018 /* I2C Write Data Byte 5 */ #define BCHP_I2C_DATA_IN6 0x0050101c /* I2C Write Data Byte 6 */ #define BCHP_I2C_DATA_IN7 0x00501020 /* I2C Write Data Byte 7 */ #define BCHP_I2C_CNT_REG 0x00501024 /* I2C Transfer Count Register */ #define BCHP_I2C_CTL_REG 0x00501028 /* I2C Control Register */ #define BCHP_I2C_IIC_ENABLE 0x0050102c /* I2C Read/Write Enable And Interrupt */ #define BCHP_I2C_DATA_OUT0 0x00501030 /* I2C Read Data Byte 0 */ #define BCHP_I2C_DATA_OUT1 0x00501034 /* I2C Read Data Byte 1 */ #define BCHP_I2C_DATA_OUT2 0x00501038 /* I2C Read Data Byte 2 */ #define BCHP_I2C_DATA_OUT3 0x0050103c /* I2C Read Data Byte 3 */ #define BCHP_I2C_DATA_OUT4 0x00501040 /* I2C Read Data Byte 4 */ #define BCHP_I2C_DATA_OUT5 0x00501044 /* I2C Read Data Byte 5 */ #define BCHP_I2C_DATA_OUT6 0x00501048 /* I2C Read Data Byte 6 */ #define BCHP_I2C_DATA_OUT7 0x0050104c /* I2C Read Data Byte 7 */ #define BCHP_I2C_CTLHI_REG 0x00501050 /* I2C Control Register */ #define BCHP_I2C_SCL_PARAM 0x00501054 /* I2C SCL Parameter Register */ /*************************************************************************** *CHIP_ADDRESS - I2C Chip Address And Read/Write Control ***************************************************************************/ /* I2C :: CHIP_ADDRESS :: reserved0 [31:08] */ #define BCHP_I2C_CHIP_ADDRESS_reserved0_MASK 0xffffff00 #define BCHP_I2C_CHIP_ADDRESS_reserved0_SHIFT 8 /* I2C :: CHIP_ADDRESS :: CHIP_ADDRESS [07:01] */ #define BCHP_I2C_CHIP_ADDRESS_CHIP_ADDRESS_MASK 0x000000fe #define BCHP_I2C_CHIP_ADDRESS_CHIP_ADDRESS_SHIFT 1 /* I2C :: CHIP_ADDRESS :: RESERVED [00:00] */ #define BCHP_I2C_CHIP_ADDRESS_RESERVED_MASK 0x00000001 #define BCHP_I2C_CHIP_ADDRESS_RESERVED_SHIFT 0 /*************************************************************************** *DATA_IN0 - I2C Write Data Byte 0 ***************************************************************************/ /* I2C :: DATA_IN0 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_IN0_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_IN0_reserved0_SHIFT 8 /* I2C :: DATA_IN0 :: DATA_IN0 [07:00] */ #define BCHP_I2C_DATA_IN0_DATA_IN0_MASK 0x000000ff #define BCHP_I2C_DATA_IN0_DATA_IN0_SHIFT 0 /*************************************************************************** *DATA_IN1 - I2C Write Data Byte 1 ***************************************************************************/ /* I2C :: DATA_IN1 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_IN1_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_IN1_reserved0_SHIFT 8 /* I2C :: DATA_IN1 :: DATA_IN1 [07:00] */ #define BCHP_I2C_DATA_IN1_DATA_IN1_MASK 0x000000ff #define BCHP_I2C_DATA_IN1_DATA_IN1_SHIFT 0 /*************************************************************************** *DATA_IN2 - I2C Write Data Byte 2 ***************************************************************************/ /* I2C :: DATA_IN2 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_IN2_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_IN2_reserved0_SHIFT 8 /* I2C :: DATA_IN2 :: DATA_IN2 [07:00] */ #define BCHP_I2C_DATA_IN2_DATA_IN2_MASK 0x000000ff #define BCHP_I2C_DATA_IN2_DATA_IN2_SHIFT 0 /*************************************************************************** *DATA_IN3 - I2C Write Data Byte 3 ***************************************************************************/ /* I2C :: DATA_IN3 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_IN3_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_IN3_reserved0_SHIFT 8 /* I2C :: DATA_IN3 :: DATA_IN3 [07:00] */ #define BCHP_I2C_DATA_IN3_DATA_IN3_MASK 0x000000ff #define BCHP_I2C_DATA_IN3_DATA_IN3_SHIFT 0 /*************************************************************************** *DATA_IN4 - I2C Write Data Byte 4 ***************************************************************************/ /* I2C :: DATA_IN4 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_IN4_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_IN4_reserved0_SHIFT 8 /* I2C :: DATA_IN4 :: DATA_IN4 [07:00] */ #define BCHP_I2C_DATA_IN4_DATA_IN4_MASK 0x000000ff #define BCHP_I2C_DATA_IN4_DATA_IN4_SHIFT 0 /*************************************************************************** *DATA_IN5 - I2C Write Data Byte 5 ***************************************************************************/ /* I2C :: DATA_IN5 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_IN5_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_IN5_reserved0_SHIFT 8 /* I2C :: DATA_IN5 :: DATA_IN5 [07:00] */ #define BCHP_I2C_DATA_IN5_DATA_IN5_MASK 0x000000ff #define BCHP_I2C_DATA_IN5_DATA_IN5_SHIFT 0 /*************************************************************************** *DATA_IN6 - I2C Write Data Byte 6 ***************************************************************************/ /* I2C :: DATA_IN6 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_IN6_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_IN6_reserved0_SHIFT 8 /* I2C :: DATA_IN6 :: DATA_IN6 [07:00] */ #define BCHP_I2C_DATA_IN6_DATA_IN6_MASK 0x000000ff #define BCHP_I2C_DATA_IN6_DATA_IN6_SHIFT 0 /*************************************************************************** *DATA_IN7 - I2C Write Data Byte 7 ***************************************************************************/ /* I2C :: DATA_IN7 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_IN7_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_IN7_reserved0_SHIFT 8 /* I2C :: DATA_IN7 :: DATA_IN7 [07:00] */ #define BCHP_I2C_DATA_IN7_DATA_IN7_MASK 0x000000ff #define BCHP_I2C_DATA_IN7_DATA_IN7_SHIFT 0 /*************************************************************************** *CNT_REG - I2C Transfer Count Register ***************************************************************************/ /* I2C :: CNT_REG :: reserved0 [31:08] */ #define BCHP_I2C_CNT_REG_reserved0_MASK 0xffffff00 #define BCHP_I2C_CNT_REG_reserved0_SHIFT 8 /* I2C :: CNT_REG :: CNT_REG2 [07:04] */ #define BCHP_I2C_CNT_REG_CNT_REG2_MASK 0x000000f0 #define BCHP_I2C_CNT_REG_CNT_REG2_SHIFT 4 /* I2C :: CNT_REG :: CNT_REG1 [03:00] */ #define BCHP_I2C_CNT_REG_CNT_REG1_MASK 0x0000000f #define BCHP_I2C_CNT_REG_CNT_REG1_SHIFT 0 /*************************************************************************** *CTL_REG - I2C Control Register ***************************************************************************/ /* I2C :: CTL_REG :: reserved0 [31:08] */ #define BCHP_I2C_CTL_REG_reserved0_MASK 0xffffff00 #define BCHP_I2C_CTL_REG_reserved0_SHIFT 8 /* I2C :: CTL_REG :: DIV_CLK [07:07] */ #define BCHP_I2C_CTL_REG_DIV_CLK_MASK 0x00000080 #define BCHP_I2C_CTL_REG_DIV_CLK_SHIFT 7 /* I2C :: CTL_REG :: INT_EN [06:06] */ #define BCHP_I2C_CTL_REG_INT_EN_MASK 0x00000040 #define BCHP_I2C_CTL_REG_INT_EN_SHIFT 6 /* I2C :: CTL_REG :: SCL_SEL [05:04] */ #define BCHP_I2C_CTL_REG_SCL_SEL_MASK 0x00000030 #define BCHP_I2C_CTL_REG_SCL_SEL_SHIFT 4 /* I2C :: CTL_REG :: DELAY_DIS [03:03] */ #define BCHP_I2C_CTL_REG_DELAY_DIS_MASK 0x00000008 #define BCHP_I2C_CTL_REG_DELAY_DIS_SHIFT 3 /* I2C :: CTL_REG :: DEGLITCH_DIS [02:02] */ #define BCHP_I2C_CTL_REG_DEGLITCH_DIS_MASK 0x00000004 #define BCHP_I2C_CTL_REG_DEGLITCH_DIS_SHIFT 2 /* I2C :: CTL_REG :: DTF [01:00] */ #define BCHP_I2C_CTL_REG_DTF_MASK 0x00000003 #define BCHP_I2C_CTL_REG_DTF_SHIFT 0 /*************************************************************************** *IIC_ENABLE - I2C Read/Write Enable And Interrupt ***************************************************************************/ /* I2C :: IIC_ENABLE :: reserved0 [31:07] */ #define BCHP_I2C_IIC_ENABLE_reserved0_MASK 0xffffff80 #define BCHP_I2C_IIC_ENABLE_reserved0_SHIFT 7 /* I2C :: IIC_ENABLE :: RESTART [06:06] */ #define BCHP_I2C_IIC_ENABLE_RESTART_MASK 0x00000040 #define BCHP_I2C_IIC_ENABLE_RESTART_SHIFT 6 /* I2C :: IIC_ENABLE :: NO_START [05:05] */ #define BCHP_I2C_IIC_ENABLE_NO_START_MASK 0x00000020 #define BCHP_I2C_IIC_ENABLE_NO_START_SHIFT 5 /* I2C :: IIC_ENABLE :: NO_STOP [04:04] */ #define BCHP_I2C_IIC_ENABLE_NO_STOP_MASK 0x00000010 #define BCHP_I2C_IIC_ENABLE_NO_STOP_SHIFT 4 /* I2C :: IIC_ENABLE :: reserved1 [03:03] */ #define BCHP_I2C_IIC_ENABLE_reserved1_MASK 0x00000008 #define BCHP_I2C_IIC_ENABLE_reserved1_SHIFT 3 /* I2C :: IIC_ENABLE :: NO_ACK [02:02] */ #define BCHP_I2C_IIC_ENABLE_NO_ACK_MASK 0x00000004 #define BCHP_I2C_IIC_ENABLE_NO_ACK_SHIFT 2 /* I2C :: IIC_ENABLE :: INTRP [01:01] */ #define BCHP_I2C_IIC_ENABLE_INTRP_MASK 0x00000002 #define BCHP_I2C_IIC_ENABLE_INTRP_SHIFT 1 /* I2C :: IIC_ENABLE :: ENABLE [00:00] */ #define BCHP_I2C_IIC_ENABLE_ENABLE_MASK 0x00000001 #define BCHP_I2C_IIC_ENABLE_ENABLE_SHIFT 0 /*************************************************************************** *DATA_OUT0 - I2C Read Data Byte 0 ***************************************************************************/ /* I2C :: DATA_OUT0 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_OUT0_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_OUT0_reserved0_SHIFT 8 /* I2C :: DATA_OUT0 :: DATA_OUT0 [07:00] */ #define BCHP_I2C_DATA_OUT0_DATA_OUT0_MASK 0x000000ff #define BCHP_I2C_DATA_OUT0_DATA_OUT0_SHIFT 0 /*************************************************************************** *DATA_OUT1 - I2C Read Data Byte 1 ***************************************************************************/ /* I2C :: DATA_OUT1 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_OUT1_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_OUT1_reserved0_SHIFT 8 /* I2C :: DATA_OUT1 :: DATA_OUT1 [07:00] */ #define BCHP_I2C_DATA_OUT1_DATA_OUT1_MASK 0x000000ff #define BCHP_I2C_DATA_OUT1_DATA_OUT1_SHIFT 0 /*************************************************************************** *DATA_OUT2 - I2C Read Data Byte 2 ***************************************************************************/ /* I2C :: DATA_OUT2 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_OUT2_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_OUT2_reserved0_SHIFT 8 /* I2C :: DATA_OUT2 :: DATA_OUT2 [07:00] */ #define BCHP_I2C_DATA_OUT2_DATA_OUT2_MASK 0x000000ff #define BCHP_I2C_DATA_OUT2_DATA_OUT2_SHIFT 0 /*************************************************************************** *DATA_OUT3 - I2C Read Data Byte 3 ***************************************************************************/ /* I2C :: DATA_OUT3 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_OUT3_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_OUT3_reserved0_SHIFT 8 /* I2C :: DATA_OUT3 :: DATA_OUT3 [07:00] */ #define BCHP_I2C_DATA_OUT3_DATA_OUT3_MASK 0x000000ff #define BCHP_I2C_DATA_OUT3_DATA_OUT3_SHIFT 0 /*************************************************************************** *DATA_OUT4 - I2C Read Data Byte 4 ***************************************************************************/ /* I2C :: DATA_OUT4 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_OUT4_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_OUT4_reserved0_SHIFT 8 /* I2C :: DATA_OUT4 :: DATA_OUT4 [07:00] */ #define BCHP_I2C_DATA_OUT4_DATA_OUT4_MASK 0x000000ff #define BCHP_I2C_DATA_OUT4_DATA_OUT4_SHIFT 0 /*************************************************************************** *DATA_OUT5 - I2C Read Data Byte 5 ***************************************************************************/ /* I2C :: DATA_OUT5 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_OUT5_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_OUT5_reserved0_SHIFT 8 /* I2C :: DATA_OUT5 :: DATA_OUT5 [07:00] */ #define BCHP_I2C_DATA_OUT5_DATA_OUT5_MASK 0x000000ff #define BCHP_I2C_DATA_OUT5_DATA_OUT5_SHIFT 0 /*************************************************************************** *DATA_OUT6 - I2C Read Data Byte 6 ***************************************************************************/ /* I2C :: DATA_OUT6 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_OUT6_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_OUT6_reserved0_SHIFT 8 /* I2C :: DATA_OUT6 :: DATA_OUT6 [07:00] */ #define BCHP_I2C_DATA_OUT6_DATA_OUT6_MASK 0x000000ff #define BCHP_I2C_DATA_OUT6_DATA_OUT6_SHIFT 0 /*************************************************************************** *DATA_OUT7 - I2C Read Data Byte 7 ***************************************************************************/ /* I2C :: DATA_OUT7 :: reserved0 [31:08] */ #define BCHP_I2C_DATA_OUT7_reserved0_MASK 0xffffff00 #define BCHP_I2C_DATA_OUT7_reserved0_SHIFT 8 /* I2C :: DATA_OUT7 :: DATA_OUT7 [07:00] */ #define BCHP_I2C_DATA_OUT7_DATA_OUT7_MASK 0x000000ff #define BCHP_I2C_DATA_OUT7_DATA_OUT7_SHIFT 0 /*************************************************************************** *CTLHI_REG - I2C Control Register ***************************************************************************/ /* I2C :: CTLHI_REG :: reserved0 [31:02] */ #define BCHP_I2C_CTLHI_REG_reserved0_MASK 0xfffffffc #define BCHP_I2C_CTLHI_REG_reserved0_SHIFT 2 /* I2C :: CTLHI_REG :: IGNORE_ACK [01:01] */ #define BCHP_I2C_CTLHI_REG_IGNORE_ACK_MASK 0x00000002 #define BCHP_I2C_CTLHI_REG_IGNORE_ACK_SHIFT 1 /* I2C :: CTLHI_REG :: WAIT_DIS [00:00] */ #define BCHP_I2C_CTLHI_REG_WAIT_DIS_MASK 0x00000001 #define BCHP_I2C_CTLHI_REG_WAIT_DIS_SHIFT 0 /*************************************************************************** *SCL_PARAM - I2C SCL Parameter Register ***************************************************************************/ /* I2C :: SCL_PARAM :: reserved0 [31:00] */ #define BCHP_I2C_SCL_PARAM_reserved0_MASK 0xffffffff #define BCHP_I2C_SCL_PARAM_reserved0_SHIFT 0 #endif /* #ifndef BCHP_I2C_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000014700000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rg.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rg0000644000175000017500000001321211610313111031032 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_sun_rg.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:20p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:19 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rg.h $ * * Hydra_Software_Devel/1 7/17/09 8:20p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_SUN_RG_H__ #define BCHP_SUN_RG_H__ /*************************************************************************** *SUN_RG - Registers for the Sundry block's RG bridge ***************************************************************************/ #define BCHP_SUN_RG_REVISION 0x00401000 /* RG Bridge Revision */ #define BCHP_SUN_RG_CTRL 0x00401004 /* RG Bridge Control Register */ #define BCHP_SUN_RG_SW_RESET_0 0x00401008 /* RG Bridge Software Reset 0 Register */ #define BCHP_SUN_RG_SW_RESET_1 0x0040100c /* RG Bridge Software Reset 1 Register */ /*************************************************************************** *REVISION - RG Bridge Revision ***************************************************************************/ /* SUN_RG :: REVISION :: reserved0 [31:16] */ #define BCHP_SUN_RG_REVISION_reserved0_MASK 0xffff0000 #define BCHP_SUN_RG_REVISION_reserved0_SHIFT 16 /* SUN_RG :: REVISION :: MAJOR [15:08] */ #define BCHP_SUN_RG_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_SUN_RG_REVISION_MAJOR_SHIFT 8 /* SUN_RG :: REVISION :: MINOR [07:00] */ #define BCHP_SUN_RG_REVISION_MINOR_MASK 0x000000ff #define BCHP_SUN_RG_REVISION_MINOR_SHIFT 0 /*************************************************************************** *CTRL - RG Bridge Control Register ***************************************************************************/ /* SUN_RG :: CTRL :: reserved0 [31:02] */ #define BCHP_SUN_RG_CTRL_reserved0_MASK 0xfffffffc #define BCHP_SUN_RG_CTRL_reserved0_SHIFT 2 /* SUN_RG :: CTRL :: rbus_error_intr [01:01] */ #define BCHP_SUN_RG_CTRL_rbus_error_intr_MASK 0x00000002 #define BCHP_SUN_RG_CTRL_rbus_error_intr_SHIFT 1 #define BCHP_SUN_RG_CTRL_rbus_error_intr_INTR_DISABLE 0 #define BCHP_SUN_RG_CTRL_rbus_error_intr_INTR_ENABLE 1 /* SUN_RG :: CTRL :: reserved1 [00:00] */ #define BCHP_SUN_RG_CTRL_reserved1_MASK 0x00000001 #define BCHP_SUN_RG_CTRL_reserved1_SHIFT 0 /*************************************************************************** *SW_RESET_0 - RG Bridge Software Reset 0 Register ***************************************************************************/ /* SUN_RG :: SW_RESET_0 :: reserved0 [31:01] */ #define BCHP_SUN_RG_SW_RESET_0_reserved0_MASK 0xfffffffe #define BCHP_SUN_RG_SW_RESET_0_reserved0_SHIFT 1 /* SUN_RG :: SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define BCHP_SUN_RG_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define BCHP_SUN_RG_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 #define BCHP_SUN_RG_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 #define BCHP_SUN_RG_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 /*************************************************************************** *SW_RESET_1 - RG Bridge Software Reset 1 Register ***************************************************************************/ /* SUN_RG :: SW_RESET_1 :: reserved0 [31:01] */ #define BCHP_SUN_RG_SW_RESET_1_reserved0_MASK 0xfffffffe #define BCHP_SUN_RG_SW_RESET_1_reserved0_SHIFT 1 /* SUN_RG :: SW_RESET_1 :: SPARE_SW_RESET [00:00] */ #define BCHP_SUN_RG_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 #define BCHP_SUN_RG_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 #define BCHP_SUN_RG_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 #define BCHP_SUN_RG_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 #endif /* #ifndef BCHP_SUN_RG_H__ */ /* End of File */ crystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mdio.h0000644000175000017500000001212011610313111030710 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_mdio.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:10p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:08 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_mdio.h $ * * Hydra_Software_Devel/1 7/17/09 8:10p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_MDIO_H__ #define BCHP_MDIO_H__ /*************************************************************************** *MDIO - PCIE MDIO Registers ***************************************************************************/ #define BCHP_MDIO_CTRL0 0x00500760 /* PCIE Serdes MDIO Control Register 0 */ #define BCHP_MDIO_CTRL1 0x00500764 /* PCIE Serdes MDIO Control Register 1 */ #define BCHP_MDIO_CTRL2 0x00500768 /* PCIE Serdes MDIO Control Register 2 */ /*************************************************************************** *CTRL0 - PCIE Serdes MDIO Control Register 0 ***************************************************************************/ /* MDIO :: CTRL0 :: reserved0 [31:22] */ #define BCHP_MDIO_CTRL0_reserved0_MASK 0xffc00000 #define BCHP_MDIO_CTRL0_reserved0_SHIFT 22 /* MDIO :: CTRL0 :: WRITE_READ_COMMAND [21:21] */ #define BCHP_MDIO_CTRL0_WRITE_READ_COMMAND_MASK 0x00200000 #define BCHP_MDIO_CTRL0_WRITE_READ_COMMAND_SHIFT 21 /* MDIO :: CTRL0 :: PHYAD [20:16] */ #define BCHP_MDIO_CTRL0_PHYAD_MASK 0x001f0000 #define BCHP_MDIO_CTRL0_PHYAD_SHIFT 16 /* MDIO :: CTRL0 :: reserved1 [15:05] */ #define BCHP_MDIO_CTRL0_reserved1_MASK 0x0000ffe0 #define BCHP_MDIO_CTRL0_reserved1_SHIFT 5 /* MDIO :: CTRL0 :: REGAD [04:00] */ #define BCHP_MDIO_CTRL0_REGAD_MASK 0x0000001f #define BCHP_MDIO_CTRL0_REGAD_SHIFT 0 /*************************************************************************** *CTRL1 - PCIE Serdes MDIO Control Register 1 ***************************************************************************/ /* MDIO :: CTRL1 :: WR_STATUS [31:31] */ #define BCHP_MDIO_CTRL1_WR_STATUS_MASK 0x80000000 #define BCHP_MDIO_CTRL1_WR_STATUS_SHIFT 31 /* MDIO :: CTRL1 :: reserved0 [30:16] */ #define BCHP_MDIO_CTRL1_reserved0_MASK 0x7fff0000 #define BCHP_MDIO_CTRL1_reserved0_SHIFT 16 /* MDIO :: CTRL1 :: Write_Data [15:00] */ #define BCHP_MDIO_CTRL1_Write_Data_MASK 0x0000ffff #define BCHP_MDIO_CTRL1_Write_Data_SHIFT 0 /*************************************************************************** *CTRL2 - PCIE Serdes MDIO Control Register 2 ***************************************************************************/ /* MDIO :: CTRL2 :: RD_STATUS [31:31] */ #define BCHP_MDIO_CTRL2_RD_STATUS_MASK 0x80000000 #define BCHP_MDIO_CTRL2_RD_STATUS_SHIFT 31 /* MDIO :: CTRL2 :: reserved0 [30:16] */ #define BCHP_MDIO_CTRL2_reserved0_MASK 0x7fff0000 #define BCHP_MDIO_CTRL2_reserved0_SHIFT 16 /* MDIO :: CTRL2 :: Read_Data [15:00] */ #define BCHP_MDIO_CTRL2_Read_Data_MASK 0x0000ffff #define BCHP_MDIO_CTRL2_Read_Data_SHIFT 0 #endif /* #ifndef BCHP_MDIO_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015600000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bop_gr_bridge.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bop_gr0000644000175000017500000001310711610313111031010 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_bop_gr_bridge.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:57p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:55 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_bop_gr_bridge.h $ * * Hydra_Software_Devel/1 7/17/09 7:57p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_BOP_GR_BRIDGE_H__ #define BCHP_BOP_GR_BRIDGE_H__ /*************************************************************************** *BOP_GR_BRIDGE - BOP GR Bridge Registers ***************************************************************************/ #define BCHP_BOP_GR_BRIDGE_REVISION 0x00511000 /* GR Bridge Revision */ #define BCHP_BOP_GR_BRIDGE_CTRL 0x00511004 /* GR Bridge Control Register */ #define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_0 0x00511008 /* GR Bridge Software Reset 0 Register */ #define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_1 0x0051100c /* GR Bridge Software Reset 1 Register */ /*************************************************************************** *REVISION - GR Bridge Revision ***************************************************************************/ /* BOP_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define BCHP_BOP_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define BCHP_BOP_GR_BRIDGE_REVISION_reserved0_SHIFT 16 /* BOP_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define BCHP_BOP_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_BOP_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* BOP_GR_BRIDGE :: REVISION :: MINOR [07:00] */ #define BCHP_BOP_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define BCHP_BOP_GR_BRIDGE_REVISION_MINOR_SHIFT 0 /*************************************************************************** *CTRL - GR Bridge Control Register ***************************************************************************/ /* BOP_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ #define BCHP_BOP_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe #define BCHP_BOP_GR_BRIDGE_CTRL_reserved0_SHIFT 1 /* BOP_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ #define BCHP_BOP_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 #define BCHP_BOP_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 #define BCHP_BOP_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 #define BCHP_BOP_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 /*************************************************************************** *SPARE_SW_RESET_0 - GR Bridge Software Reset 0 Register ***************************************************************************/ /* BOP_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ #define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe #define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 /* BOP_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 #define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 #define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 /*************************************************************************** *SPARE_SW_RESET_1 - GR Bridge Software Reset 1 Register ***************************************************************************/ /* BOP_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ #define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe #define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 /* BOP_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ #define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 #define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 #define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 #define BCHP_BOP_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 #endif /* #ifndef BCHP_BOP_GR_BRIDGE_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015700000000000011570 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dma_secure.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dm0000644000175000017500000000613411610313111031000 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_mem_dma_secure.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:10p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:56 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_mem_dma_secure.h $ * * Hydra_Software_Devel/1 7/17/09 8:10p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_MEM_DMA_SECURE_H__ #define BCHP_MEM_DMA_SECURE_H__ /*************************************************************************** *MEM_DMA_SECURE - MEM_DMA Secure Registers ***************************************************************************/ #define BCHP_MEM_DMA_SECURE_RSV_S 0x000fc000 /* RESERVED */ #define BCHP_MEM_DMA_SECURE_RSV_E 0x000fc00c /* RESERVED */ /*************************************************************************** *RSV_S - RESERVED ***************************************************************************/ /* MEM_DMA_SECURE :: RSV_S :: reserved0 [31:00] */ #define BCHP_MEM_DMA_SECURE_RSV_S_reserved0_MASK 0xffffffff #define BCHP_MEM_DMA_SECURE_RSV_S_reserved0_SHIFT 0 /*************************************************************************** *RSV_E - RESERVED ***************************************************************************/ /* MEM_DMA_SECURE :: RSV_E :: reserved0 [31:00] */ #define BCHP_MEM_DMA_SECURE_RSV_E_reserved0_MASK 0xffffffff #define BCHP_MEM_DMA_SECURE_RSV_E_reserved0_SHIFT 0 #endif /* #ifndef BCHP_MEM_DMA_SECURE_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015100000000000011562 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sentinel.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sentin0000644000175000017500000000620411610313111031040 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_sentinel.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:18p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:38 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sentinel.h $ * * Hydra_Software_Devel/1 7/17/09 8:18p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_SENTINEL_H__ #define BCHP_SENTINEL_H__ /*************************************************************************** *SENTINEL - Sentinal ***************************************************************************/ #define BCHP_SENTINEL_SENTINEL_ADDR_START 0x00410000 /* Sentinel Start Address */ #define BCHP_SENTINEL_SENTINEL_ADDR_END 0x00413ffc /* Sentinel Start Address */ /*************************************************************************** *SENTINEL_ADDR_START - Sentinel Start Address ***************************************************************************/ /* SENTINEL :: SENTINEL_ADDR_START :: ADDRESS [31:00] */ #define BCHP_SENTINEL_SENTINEL_ADDR_START_ADDRESS_MASK 0xffffffff #define BCHP_SENTINEL_SENTINEL_ADDR_START_ADDRESS_SHIFT 0 /*************************************************************************** *SENTINEL_ADDR_END - Sentinel Start Address ***************************************************************************/ /* SENTINEL :: SENTINEL_ADDR_END :: ADDRESS [31:00] */ #define BCHP_SENTINEL_SENTINEL_ADDR_END_ADDRESS_MASK 0xffffffff #define BCHP_SENTINEL_SENTINEL_ADDR_END_ADDRESS_SHIFT 0 #endif /* #ifndef BCHP_SENTINEL_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015700000000000011570 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb1.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id0000644000175000017500000000633511610313111031013 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_int_id_xpt_pb1.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:08p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:40 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility unknown * RDB Parser 3.0 * generate_int_id.pl 1.0 * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb1.h $ * * Hydra_Software_Devel/1 7/17/09 8:08p albertl * PR56880: Initial revision. * ***************************************************************************/ #include "bchp.h" #include "bchp_xpt_pb0.h" #include "bchp_xpt_pb1.h" #ifndef BCHP_INT_ID_XPT_PB1_H__ #define BCHP_INT_ID_XPT_PB1_H__ #define BCHP_INT_ID_XPT_PB1_DONE_INT BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_DONE_INT_SHIFT) #define BCHP_INT_ID_XPT_PB1_PARSER_CONTINUITY_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_PARSER_CONTINUITY_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB1_PARSER_LENGTH_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_PARSER_LENGTH_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB1_PARSER_SEC_CC_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_PARSER_SEC_CC_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB1_PARSER_TRANSPORT_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_PARSER_TRANSPORT_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB1_PB_COPYRIGHT_CHANGE BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_PB_COPYRIGHT_CHANGE_SHIFT) #define BCHP_INT_ID_XPT_PB1_SE_OUT_OF_SYNC_INT BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_SE_OUT_OF_SYNC_INT_SHIFT) #define BCHP_INT_ID_XPT_PB1_TS_PARITY_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_TS_PARITY_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB1_TS_RANGE_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB1_INTR, BCHP_XPT_PB0_INTR_TS_RANGE_ERROR_SHIFT) #endif /* #ifndef BCHP_INT_ID_XPT_PB1_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016200000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_3.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rt0000644000175000017500000000664611610313111031051 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_rts_l2_regs_3.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:17p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:26 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_3.h $ * * Hydra_Software_Devel/1 7/17/09 8:17p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_RTS_L2_REGS_3_H__ #define BCHP_PRI_RTS_L2_REGS_3_H__ /*************************************************************************** *PRI_RTS_L2_REGS_3 - PRIMARY_ARB_CLIENTS L2 (Mips) rts interrupt controller 3 registers ***************************************************************************/ #define BCHP_PRI_RTS_L2_REGS_3_CPU_STATUS 0x0040c540 /* CPU interrupt Status Register */ #define BCHP_PRI_RTS_L2_REGS_3_CPU_SET 0x0040c544 /* CPU interrupt Set Register */ #define BCHP_PRI_RTS_L2_REGS_3_CPU_CLEAR 0x0040c548 /* CPU interrupt Clear Register */ #define BCHP_PRI_RTS_L2_REGS_3_CPU_MASK_STATUS 0x0040c54c /* CPU interrupt Mask Status Register */ #define BCHP_PRI_RTS_L2_REGS_3_CPU_MASK_SET 0x0040c550 /* CPU interrupt Mask Set Register */ #define BCHP_PRI_RTS_L2_REGS_3_CPU_MASK_CLEAR 0x0040c554 /* CPU interrupt Mask Clear Register */ #define BCHP_PRI_RTS_L2_REGS_3_PCI_STATUS 0x0040c558 /* PCI interrupt Status Register */ #define BCHP_PRI_RTS_L2_REGS_3_PCI_SET 0x0040c55c /* PCI interrupt Set Register */ #define BCHP_PRI_RTS_L2_REGS_3_PCI_CLEAR 0x0040c560 /* PCI interrupt Clear Register */ #define BCHP_PRI_RTS_L2_REGS_3_PCI_MASK_STATUS 0x0040c564 /* PCI interrupt Mask Status Register */ #define BCHP_PRI_RTS_L2_REGS_3_PCI_MASK_SET 0x0040c568 /* PCI interrupt Mask Set Register */ #define BCHP_PRI_RTS_L2_REGS_3_PCI_MASK_CLEAR 0x0040c56c /* PCI interrupt Mask Clear Register */ #endif /* #ifndef BCHP_PRI_RTS_L2_REGS_3_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015100000000000011562 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_phy.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_p0000644000175000017500000007240311610313111031003 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pcie_phy.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:13p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:28 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_phy.h $ * * Hydra_Software_Devel/1 7/17/09 8:13p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PCIE_PHY_H__ #define BCHP_PCIE_PHY_H__ /*************************************************************************** *PCIE_PHY - PCIE PHY related registers ***************************************************************************/ #define BCHP_PCIE_PHY_PHY_MODE 0x00500600 /* TYPE_PHY_MODE Register */ #define BCHP_PCIE_PHY_PHY_LINK_STATUS 0x00500604 /* TYPE_PHY_LINK_STATUS Register */ #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL 0x00500608 /* TYPE_PHY_LINK_LTSSM_CONTROL Register */ #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER 0x0050060c /* TYPE_PHY_LINK_TRAINING_LINK_NUMBER Register */ #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER 0x00500610 /* TYPE_PHY_LINK_TRAINING_LANE_NUMBER Register */ #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS 0x00500614 /* TYPE_PHY_LINK_TRAINING_N_FTS Register */ #define BCHP_PCIE_PHY_PHY_ATTENTION 0x00500618 /* TYPE_PHY_ATTENTION Register */ #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK 0x0050061c /* TYPE_PHY_ATTENTION_MASK Register */ #define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER 0x00500620 /* TYPE_PHY_RECEIVE_ERROR_COUNTER Register */ #define BCHP_PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER 0x00500624 /* TYPE_PHY_RECEIVE_FRAMING_ERROR_COUNTER Register */ #define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD 0x00500628 /* TYPE_PHY_RECEIVE_ERROR_THRESHOLD Register */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL 0x0050062c /* TYPE_PHY_TEST_CONTROL Register */ #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE 0x00500630 /* TYPE_PHY_SERDES_CONTROL_OVERRIDE Register */ #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE 0x00500634 /* TYPE_PHY_TIMING_PARAMETER_OVERRIDE Register */ #define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES 0x00500638 /* TYPE_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES Register */ #define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES 0x0050063c /* TYPE_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES Register */ /*************************************************************************** *PHY_MODE - TYPE_PHY_MODE Register ***************************************************************************/ /* PCIE_PHY :: PHY_MODE :: RESERVED_0 [31:04] */ #define BCHP_PCIE_PHY_PHY_MODE_RESERVED_0_MASK 0xfffffff0 #define BCHP_PCIE_PHY_PHY_MODE_RESERVED_0_SHIFT 4 /* PCIE_PHY :: PHY_MODE :: UPSTREAM_DEV [03:03] */ #define BCHP_PCIE_PHY_PHY_MODE_UPSTREAM_DEV_MASK 0x00000008 #define BCHP_PCIE_PHY_PHY_MODE_UPSTREAM_DEV_SHIFT 3 /* PCIE_PHY :: PHY_MODE :: SERDES_SA_MODE [02:02] */ #define BCHP_PCIE_PHY_PHY_MODE_SERDES_SA_MODE_MASK 0x00000004 #define BCHP_PCIE_PHY_PHY_MODE_SERDES_SA_MODE_SHIFT 2 /* PCIE_PHY :: PHY_MODE :: LINK_DISABLE [01:01] */ #define BCHP_PCIE_PHY_PHY_MODE_LINK_DISABLE_MASK 0x00000002 #define BCHP_PCIE_PHY_PHY_MODE_LINK_DISABLE_SHIFT 1 /* PCIE_PHY :: PHY_MODE :: SOFT_RESET [00:00] */ #define BCHP_PCIE_PHY_PHY_MODE_SOFT_RESET_MASK 0x00000001 #define BCHP_PCIE_PHY_PHY_MODE_SOFT_RESET_SHIFT 0 /*************************************************************************** *PHY_LINK_STATUS - TYPE_PHY_LINK_STATUS Register ***************************************************************************/ /* PCIE_PHY :: PHY_LINK_STATUS :: RESERVED_0 [31:10] */ #define BCHP_PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_MASK 0xfffffc00 #define BCHP_PCIE_PHY_PHY_LINK_STATUS_RESERVED_0_SHIFT 10 /* PCIE_PHY :: PHY_LINK_STATUS :: BUFFER_OVERRUN [09:09] */ #define BCHP_PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_MASK 0x00000200 #define BCHP_PCIE_PHY_PHY_LINK_STATUS_BUFFER_OVERRUN_SHIFT 9 /* PCIE_PHY :: PHY_LINK_STATUS :: BUFFER_UNDERRUN [08:08] */ #define BCHP_PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_MASK 0x00000100 #define BCHP_PCIE_PHY_PHY_LINK_STATUS_BUFFER_UNDERRUN_SHIFT 8 /* PCIE_PHY :: PHY_LINK_STATUS :: LINK_PARTNER_REQUEST_LOOPBACK [07:07] */ #define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_MASK 0x00000080 #define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_REQUEST_LOOPBACK_SHIFT 7 /* PCIE_PHY :: PHY_LINK_STATUS :: LINK_PARTNER_DISABLE_SCRAMBLER [06:06] */ #define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_MASK 0x00000040 #define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_PARTNER_DISABLE_SCRAMBLER_SHIFT 6 /* PCIE_PHY :: PHY_LINK_STATUS :: EXTENDED_SYNCH [05:05] */ #define BCHP_PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_MASK 0x00000020 #define BCHP_PCIE_PHY_PHY_LINK_STATUS_EXTENDED_SYNCH_SHIFT 5 /* PCIE_PHY :: PHY_LINK_STATUS :: POLARITY_INVERTED [04:04] */ #define BCHP_PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_MASK 0x00000010 #define BCHP_PCIE_PHY_PHY_LINK_STATUS_POLARITY_INVERTED_SHIFT 4 /* PCIE_PHY :: PHY_LINK_STATUS :: LINK_UP [03:03] */ #define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_UP_MASK 0x00000008 #define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_UP_SHIFT 3 /* PCIE_PHY :: PHY_LINK_STATUS :: LINK_TRAINING [02:02] */ #define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_MASK 0x00000004 #define BCHP_PCIE_PHY_PHY_LINK_STATUS_LINK_TRAINING_SHIFT 2 /* PCIE_PHY :: PHY_LINK_STATUS :: RECEIVE_DATA_VALID [01:01] */ #define BCHP_PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_MASK 0x00000002 #define BCHP_PCIE_PHY_PHY_LINK_STATUS_RECEIVE_DATA_VALID_SHIFT 1 /* PCIE_PHY :: PHY_LINK_STATUS :: RESERVED_1 [00:00] */ #define BCHP_PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_MASK 0x00000001 #define BCHP_PCIE_PHY_PHY_LINK_STATUS_RESERVED_1_SHIFT 0 /*************************************************************************** *PHY_LINK_LTSSM_CONTROL - TYPE_PHY_LINK_LTSSM_CONTROL Register ***************************************************************************/ /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RESERVED_0 [31:08] */ #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_MASK 0xffffff00 #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESERVED_0_SHIFT 8 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DISABLESCRAMBLE [07:07] */ #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_MASK 0x00000080 #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESCRAMBLE_SHIFT 7 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DETECTSTATE [06:06] */ #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_MASK 0x00000040 #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DETECTSTATE_SHIFT 6 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: POLLINGSTATE [05:05] */ #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_MASK 0x00000020 #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_POLLINGSTATE_SHIFT 5 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: CONFIGSTATE [04:04] */ #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_MASK 0x00000010 #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_CONFIGSTATE_SHIFT 4 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RECOVSTATE [03:03] */ #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_MASK 0x00000008 #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RECOVSTATE_SHIFT 3 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: EXTLBSTATE [02:02] */ #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_MASK 0x00000004 #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_EXTLBSTATE_SHIFT 2 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: RESETSTATE [01:01] */ #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_MASK 0x00000002 #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_RESETSTATE_SHIFT 1 /* PCIE_PHY :: PHY_LINK_LTSSM_CONTROL :: DISABLESTATE [00:00] */ #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_MASK 0x00000001 #define BCHP_PCIE_PHY_PHY_LINK_LTSSM_CONTROL_DISABLESTATE_SHIFT 0 /*************************************************************************** *PHY_LINK_TRAINING_LINK_NUMBER - TYPE_PHY_LINK_TRAINING_LINK_NUMBER Register ***************************************************************************/ /* PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER :: RESERVED_0 [31:08] */ #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_MASK 0xffffff00 #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_RESERVED_0_SHIFT 8 /* PCIE_PHY :: PHY_LINK_TRAINING_LINK_NUMBER :: LANE_NUMBER [07:00] */ #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_MASK 0x000000ff #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LINK_NUMBER_LANE_NUMBER_SHIFT 0 /*************************************************************************** *PHY_LINK_TRAINING_LANE_NUMBER - TYPE_PHY_LINK_TRAINING_LANE_NUMBER Register ***************************************************************************/ /* PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER :: RESERVED_0 [31:08] */ #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_MASK 0xffffff00 #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_RESERVED_0_SHIFT 8 /* PCIE_PHY :: PHY_LINK_TRAINING_LANE_NUMBER :: LANE_NUMBER [07:00] */ #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_MASK 0x000000ff #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_LANE_NUMBER_LANE_NUMBER_SHIFT 0 /*************************************************************************** *PHY_LINK_TRAINING_N_FTS - TYPE_PHY_LINK_TRAINING_N_FTS Register ***************************************************************************/ /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: RESERVED_0 [31:25] */ #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_MASK 0xfe000000 #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RESERVED_0_SHIFT 25 /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS_OVERRIDE [24:24] */ #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_MASK 0x01000000 #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_SHIFT 24 /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS_OVERRIDE_VALUE [23:16] */ #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_MASK 0x00ff0000 #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_OVERRIDE_VALUE_SHIFT 16 /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: TRANSMITTER_N_FTS [15:08] */ #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_MASK 0x0000ff00 #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_TRANSMITTER_N_FTS_SHIFT 8 /* PCIE_PHY :: PHY_LINK_TRAINING_N_FTS :: RECEIVER_N_FTS [07:00] */ #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_MASK 0x000000ff #define BCHP_PCIE_PHY_PHY_LINK_TRAINING_N_FTS_RECEIVER_N_FTS_SHIFT 0 /*************************************************************************** *PHY_ATTENTION - TYPE_PHY_ATTENTION Register ***************************************************************************/ /* PCIE_PHY :: PHY_ATTENTION :: RESERVED_0 [31:08] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_RESERVED_0_MASK 0xffffff00 #define BCHP_PCIE_PHY_PHY_ATTENTION_RESERVED_0_SHIFT 8 /* PCIE_PHY :: PHY_ATTENTION :: HOT_RESET [07:07] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_HOT_RESET_MASK 0x00000080 #define BCHP_PCIE_PHY_PHY_ATTENTION_HOT_RESET_SHIFT 7 /* PCIE_PHY :: PHY_ATTENTION :: LINK_DOWN [06:06] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_LINK_DOWN_MASK 0x00000040 #define BCHP_PCIE_PHY_PHY_ATTENTION_LINK_DOWN_SHIFT 6 /* PCIE_PHY :: PHY_ATTENTION :: TRAINING_ERROR [05:05] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_MASK 0x00000020 #define BCHP_PCIE_PHY_PHY_ATTENTION_TRAINING_ERROR_SHIFT 5 /* PCIE_PHY :: PHY_ATTENTION :: BUFFER_OVERRUN [04:04] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_MASK 0x00000010 #define BCHP_PCIE_PHY_PHY_ATTENTION_BUFFER_OVERRUN_SHIFT 4 /* PCIE_PHY :: PHY_ATTENTION :: BUFFER_UNDERRUN [03:03] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_MASK 0x00000008 #define BCHP_PCIE_PHY_PHY_ATTENTION_BUFFER_UNDERRUN_SHIFT 3 /* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_FRAMING_ERROR [02:02] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_MASK 0x00000004 #define BCHP_PCIE_PHY_PHY_ATTENTION_RECEIVE_FRAMING_ERROR_SHIFT 2 /* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_DISPARITY_ERROR [01:01] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_MASK 0x00000002 #define BCHP_PCIE_PHY_PHY_ATTENTION_RECEIVE_DISPARITY_ERROR_SHIFT 1 /* PCIE_PHY :: PHY_ATTENTION :: RECEIVE_CODE_ERROR [00:00] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_MASK 0x00000001 #define BCHP_PCIE_PHY_PHY_ATTENTION_RECEIVE_CODE_ERROR_SHIFT 0 /*************************************************************************** *PHY_ATTENTION_MASK - TYPE_PHY_ATTENTION_MASK Register ***************************************************************************/ /* PCIE_PHY :: PHY_ATTENTION_MASK :: RESERVED_0 [31:08] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_MASK 0xffffff00 #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RESERVED_0_SHIFT 8 /* PCIE_PHY :: PHY_ATTENTION_MASK :: HOT_RESET_MASK [07:07] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_MASK 0x00000080 #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_HOT_RESET_MASK_SHIFT 7 /* PCIE_PHY :: PHY_ATTENTION_MASK :: LINK_DOWN_MASK [06:06] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_MASK 0x00000040 #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_LINK_DOWN_MASK_SHIFT 6 /* PCIE_PHY :: PHY_ATTENTION_MASK :: TRAINING_ERROR_MASK [05:05] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_MASK 0x00000020 #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_TRAINING_ERROR_MASK_SHIFT 5 /* PCIE_PHY :: PHY_ATTENTION_MASK :: BUFFER_OVERRUN_MASK [04:04] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_MASK 0x00000010 #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_OVERRUN_MASK_SHIFT 4 /* PCIE_PHY :: PHY_ATTENTION_MASK :: BUFFER_UNDERRUN_MASK [03:03] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_MASK 0x00000008 #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_BUFFER_UNDERRUN_MASK_SHIFT 3 /* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_FRAME_ERROR_MASK [02:02] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_MASK 0x00000004 #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_FRAME_ERROR_MASK_SHIFT 2 /* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_DISPARITY_ERROR_MASK [01:01] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_MASK 0x00000002 #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_DISPARITY_ERROR_MASK_SHIFT 1 /* PCIE_PHY :: PHY_ATTENTION_MASK :: RECEIVE_CODE_ERROR_MASK [00:00] */ #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_MASK 0x00000001 #define BCHP_PCIE_PHY_PHY_ATTENTION_MASK_RECEIVE_CODE_ERROR_MASK_SHIFT 0 /*************************************************************************** *PHY_RECEIVE_ERROR_COUNTER - TYPE_PHY_RECEIVE_ERROR_COUNTER Register ***************************************************************************/ /* PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER :: DISPARITY_ERROR_COUNT [31:16] */ #define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_MASK 0xffff0000 #define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_DISPARITY_ERROR_COUNT_SHIFT 16 /* PCIE_PHY :: PHY_RECEIVE_ERROR_COUNTER :: CODE_ERROR_COUNT [15:00] */ #define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_MASK 0x0000ffff #define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_COUNTER_CODE_ERROR_COUNT_SHIFT 0 /*************************************************************************** *PHY_RECEIVE_FRAMING_ERROR_COUNTER - TYPE_PHY_RECEIVE_FRAMING_ERROR_COUNTER Register ***************************************************************************/ /* PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER :: RESERVED_0 [31:16] */ #define BCHP_PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_MASK 0xffff0000 #define BCHP_PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_RESERVED_0_SHIFT 16 /* PCIE_PHY :: PHY_RECEIVE_FRAMING_ERROR_COUNTER :: FRAMING_ERROR_COUNT [15:00] */ #define BCHP_PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_MASK 0x0000ffff #define BCHP_PCIE_PHY_PHY_RECEIVE_FRAMING_ERROR_COUNTER_FRAMING_ERROR_COUNT_SHIFT 0 /*************************************************************************** *PHY_RECEIVE_ERROR_THRESHOLD - TYPE_PHY_RECEIVE_ERROR_THRESHOLD Register ***************************************************************************/ /* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: RESERVED_0 [31:12] */ #define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_MASK 0xfffff000 #define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_RESERVED_0_SHIFT 12 /* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: FRAME_ERROR_THRESHOLD [11:08] */ #define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_MASK 0x00000f00 #define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_FRAME_ERROR_THRESHOLD_SHIFT 8 /* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: DISPARITY_ERROR_THRESHOLD [07:04] */ #define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_MASK 0x000000f0 #define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_DISPARITY_ERROR_THRESHOLD_SHIFT 4 /* PCIE_PHY :: PHY_RECEIVE_ERROR_THRESHOLD :: CODE_ERROR_THRESHOLD [03:00] */ #define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_MASK 0x0000000f #define BCHP_PCIE_PHY_PHY_RECEIVE_ERROR_THRESHOLD_CODE_ERROR_THRESHOLD_SHIFT 0 /*************************************************************************** *PHY_TEST_CONTROL - TYPE_PHY_TEST_CONTROL Register ***************************************************************************/ /* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_0 [31:31] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_MASK 0x80000000 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_UNUSED_0_SHIFT 31 /* PCIE_PHY :: PHY_TEST_CONTROL :: DELAY_HOTRESET_ENABLE [30:30] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_MASK 0x40000000 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DELAY_HOTRESET_ENABLE_SHIFT 30 /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_TSX_MAJORITY_CHECK [29:29] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_MASK 0x20000000 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_TSX_MAJORITY_CHECK_SHIFT 29 /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_MASK_OFF_BOGUS [28:28] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_MASK 0x10000000 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_MASK_OFF_BOGUS_SHIFT 28 /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_POLARITY_CHECK [27:27] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_MASK 0x08000000 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_POLARITY_CHECK_SHIFT 27 /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ27039_STICKY_POLARITY_CHECK [26:26] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_MASK 0x04000000 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ27039_STICKY_POLARITY_CHECK_SHIFT 26 /* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_1 [25:23] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_MASK 0x03800000 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_UNUSED_1_SHIFT 23 /* PCIE_PHY :: PHY_TEST_CONTROL :: TWO_OS_RULE_RELAXING [22:22] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_MASK 0x00400000 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_TWO_OS_RULE_RELAXING_SHIFT 22 /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_HOT_RESET [21:21] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_MASK 0x00200000 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_HOT_RESET_SHIFT 21 /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_LINK_DOWN_RESET [20:20] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_MASK 0x00100000 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_LINK_DOWN_RESET_SHIFT 20 /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE [19:19] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_MASK 0x00080000 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_EIDLE_SET_TRANSMITTING_AT_TIME_OUT_TO_DETECT_STATE_SHIFT 19 /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_EXIT [18:18] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_MASK 0x00040000 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_EXIT_SHIFT 18 /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_MASK [17:17] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_MASK 0x00020000 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_MASK_SHIFT 17 /* PCIE_PHY :: PHY_TEST_CONTROL :: DISABLE_ERROR_RECOVERY [16:16] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_MASK 0x00010000 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_DISABLE_ERROR_RECOVERY_SHIFT 16 /* PCIE_PHY :: PHY_TEST_CONTROL :: RESERVED_0 [15:08] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_MASK 0x0000ff00 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_RESERVED_0_SHIFT 8 /* PCIE_PHY :: PHY_TEST_CONTROL :: UNUSED_2 [07:04] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_MASK 0x000000f0 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_UNUSED_2_SHIFT 4 /* PCIE_PHY :: PHY_TEST_CONTROL :: CQ22100_FIX_DISABLE [03:03] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_MASK 0x00000008 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_CQ22100_FIX_DISABLE_SHIFT 3 /* PCIE_PHY :: PHY_TEST_CONTROL :: TRAINING_BYPASS [02:02] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_MASK 0x00000004 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_TRAINING_BYPASS_SHIFT 2 /* PCIE_PHY :: PHY_TEST_CONTROL :: EXTERNAL_LOOPBACK [01:01] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_MASK 0x00000002 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_EXTERNAL_LOOPBACK_SHIFT 1 /* PCIE_PHY :: PHY_TEST_CONTROL :: INTERNAL_LOOPBACK [00:00] */ #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_MASK 0x00000001 #define BCHP_PCIE_PHY_PHY_TEST_CONTROL_INTERNAL_LOOPBACK_SHIFT 0 /*************************************************************************** *PHY_SERDES_CONTROL_OVERRIDE - TYPE_PHY_SERDES_CONTROL_OVERRIDE Register ***************************************************************************/ /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RESERVED_0 [31:18] */ #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_MASK 0xfffc0000 #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RESERVED_0_SHIFT 18 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: OBSVELECIDLEVALUE [17:17] */ #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_MASK 0x00020000 #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEVALUE_SHIFT 17 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: OBSVELECIDLEOVERRIDE [16:16] */ #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_MASK 0x00010000 #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_OBSVELECIDLEOVERRIDE_SHIFT 16 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: PLLISUPVALUE [15:15] */ #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_MASK 0x00008000 #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPVALUE_SHIFT 15 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: PLLISUPOVERRIDE [14:14] */ #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_MASK 0x00004000 #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_PLLISUPOVERRIDE_SHIFT 14 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETVALUE [13:13] */ #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_MASK 0x00002000 #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETVALUE_SHIFT 13 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETOVERRIDE [12:12] */ #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_MASK 0x00001000 #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETOVERRIDE_SHIFT 12 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETTIMECONTROL [11:10] */ #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_MASK 0x00000c00 #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETTIMECONTROL_SHIFT 10 /* PCIE_PHY :: PHY_SERDES_CONTROL_OVERRIDE :: RCVRDETECTIONTIME [09:00] */ #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_MASK 0x000003ff #define BCHP_PCIE_PHY_PHY_SERDES_CONTROL_OVERRIDE_RCVRDETECTIONTIME_SHIFT 0 /*************************************************************************** *PHY_TIMING_PARAMETER_OVERRIDE - TYPE_PHY_TIMING_PARAMETER_OVERRIDE Register ***************************************************************************/ /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TS1NUMOVERRIDE [31:31] */ #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_MASK 0x80000000 #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TS1NUMOVERRIDE_SHIFT 31 /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLEMINOVERRIDE [30:30] */ #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_MASK 0x40000000 #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINOVERRIDE_SHIFT 30 /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLE2IDLEOVERRIDE [29:29] */ #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_MASK 0x20000000 #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLE2IDLEOVERRIDE_SHIFT 29 /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: UNUSED_0 [28:28] */ #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_MASK 0x10000000 #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_UNUSED_0_SHIFT 28 /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: N_TS1INPOLLINGACTIVE [27:16] */ #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_MASK 0x0fff0000 #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_N_TS1INPOLLINGACTIVE_SHIFT 16 /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLEMINTIME [15:08] */ #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_MASK 0x0000ff00 #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLEMINTIME_SHIFT 8 /* PCIE_PHY :: PHY_TIMING_PARAMETER_OVERRIDE :: TXIDLESETTOIDLETIME [07:00] */ #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_MASK 0x000000ff #define BCHP_PCIE_PHY_PHY_TIMING_PARAMETER_OVERRIDE_TXIDLESETTOIDLETIME_SHIFT 0 /*************************************************************************** *PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES - TYPE_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES Register ***************************************************************************/ /* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: RESERVED_0 [31:10] */ #define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_MASK 0xfffffc00 #define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RESERVED_0_SHIFT 10 /* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: TRANSMIT_STATE_MACHINE_STATE [09:04] */ #define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_MASK 0x000003f0 #define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_TRANSMIT_STATE_MACHINE_STATE_SHIFT 4 /* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES :: RECEIVE_STATE_MACHINE_STATE [03:00] */ #define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_MASK 0x0000000f #define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC1_TX_RX_SM_STATES_RECEIVE_STATE_MACHINE_STATE_SHIFT 0 /*************************************************************************** *PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES - TYPE_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES Register ***************************************************************************/ /* PCIE_PHY :: PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES :: LTSSM_STATE_MACHINE_STATE [31:00] */ #define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_MASK 0xffffffff #define BCHP_PCIE_PHY_PHY_HARDWARE_DIAGNOSTIC2_LTSSM_STATES_LTSSM_STATE_MACHINE_STATE_SHIFT 0 #endif /* #ifndef BCHP_PCIE_PHY_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015600000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_sint_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000026761411610313111031001 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_sint_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:05p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:58 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_sint_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:05p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_SINT_0_H__ #define BCHP_DECODE_SINT_0_H__ /*************************************************************************** *DECODE_SINT_0 ***************************************************************************/ #define BCHP_DECODE_SINT_0_REG_SINT_DMA_ADDR 0x00800c00 /* REG_SINT_DMA_ADDR */ #define BCHP_DECODE_SINT_0_REG_SINT_DMA_LEN 0x00800c04 /* REG_SINT_DMA_LEN */ #define BCHP_DECODE_SINT_0_REG_SINT_DMA_BASE 0x00800c08 /* REG_SINT_DMA_BASE */ #define BCHP_DECODE_SINT_0_REG_SINT_DMA_END 0x00800c0c /* REG_SINT_DMA_END */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_POS 0x00800c10 /* REG_SINT_STRM_POS */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT 0x00800c14 /* REG_SINT_STRM_STAT */ #define BCHP_DECODE_SINT_0_REG_SINT_IENA 0x00800c18 /* REG_SINT_IENA */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_BITS 0x00800c1c /* REG_SINT_STRM_BITS */ #define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB 0x00800c20 /* REG_SINT_GET_SYMB */ #define BCHP_DECODE_SINT_0_REG_SINT_MPEG_DC 0x00800c24 /* REG_SINT_MPEG_DC */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID 0x00800c28 /* REG_SINT_DO_RESID */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO 0x00800c2c /* REG_SINT_XNZERO */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE 0x00800c30 /* REG_SINT_VEC_MBTYPE */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_RESID 0x00800c34 /* REG_SINT_VEC_RESID */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DMODE 0x00800c38 /* REG_SINT_VEC_DMODE */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOP_LD 0x00800c3c /* REG_SINT_VEC_TOP_LD */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST 0x00800c40 /* REG_SINT_VEC_DO_CONST */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF 0x00800c44 /* Deblocking Motion Vector Difference */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX 0x00800c48 /* REG_SINT_VEC_REFIDX */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF 0x00800c4c /* REG_SINT_VEC_TOPREF */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF 0x00800c50 /* REG_SINT_VEC_TOPTOPREF */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE 0x00800c54 /* REG_SINT_VEC_COL_TYPE */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID 0x00800c58 /* REG_SINT_VEC_COL_REFID */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC 0x00800c5c /* REG_SINT_VEC_TOPPIC */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO 0x00800c60 /* REG_SINT_VEC_VC1_INFO */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC 0x00800c64 /* REG_SINT_VEC_REFPIC - H.264 only */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COUNT 0x00800c68 /* REG_SINT_VEC_COUNT */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVD_FIFO 0x00800c6c /* REG_SINT_VEC_MVD_FIFO */ #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL 0x00800c70 /* REG_SINT_DIVX_TABSEL */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_AUX 0x00800c74 /* REG_SINT_CTL_AUX */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REGEND 0x00800c7c /* REG_SINT_VEC_REGEND */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL 0x00800c80 /* REG_SINT_CTL */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX 0x00800c84 /* REG_SINT_VLC_TOPCTX */ #define BCHP_DECODE_SINT_0_REG_SINT_SLICE_ID 0x00800c88 /* REG_SINT_SLICE_ID */ #define BCHP_DECODE_SINT_0_REG_SINT_QP 0x00800c8c /* REG_SINT_QP */ #define BCHP_DECODE_SINT_0_REG_SINT_TOP_BASE_ADDR 0x00800c90 /* REG_SINT_TOP_BASE_ADDR */ #define BCHP_DECODE_SINT_0_REG_SINT_DIRCTX_WR_ADDR 0x00800c94 /* REG_SINT_DIRCTX_WR_ADDR */ #define BCHP_DECODE_SINT_0_REG_SINT_TOPCTX_DATA 0x00800c98 /* REG_SINT_TOPCTX_DATA */ #define BCHP_DECODE_SINT_0_REG_SINT_XFER_SYMB 0x00800c9c /* REG_SINT_XFER_SYMB */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE 0x00800ca0 /* REG_SINT_SMODE_BASE */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT 0x00800ca4 /* REG_SINT_SMODE_LEFT */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP 0x00800ca8 /* REG_SINT_SMODE_TOP */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_END 0x00800cac /* REG_SINT_SMODE_END */ #define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT 0x00800cb0 /* REG_SINT_CTX_INIT */ #define BCHP_DECODE_SINT_0_REG_SINT_TOP_CTX 0x00800cb4 /* REG_SINT_TOP_CTX */ #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL 0x00800cb8 /* REG_SINT_VC1_TABSEL */ #define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA 0x00800cbc /* REG_SINT_CNST_INTRA */ #define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE 0x00800cc0 /* Outpic Lookup */ #define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_END 0x00800cfc /* REG_SINT_OPIC_MEM_END */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_BASE 0x00800d00 /* Vector Memory */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_END 0x00800dfc /* REG_SINT_VEC_MEM_END */ /*************************************************************************** *REG_SINT_DMA_ADDR - REG_SINT_DMA_ADDR ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_DMA_ADDR :: Addr [31:02] */ #define BCHP_DECODE_SINT_0_REG_SINT_DMA_ADDR_Addr_MASK 0xfffffffc #define BCHP_DECODE_SINT_0_REG_SINT_DMA_ADDR_Addr_SHIFT 2 /* DECODE_SINT_0 :: REG_SINT_DMA_ADDR :: reserved0 [01:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_DMA_ADDR_reserved0_MASK 0x00000003 #define BCHP_DECODE_SINT_0_REG_SINT_DMA_ADDR_reserved0_SHIFT 0 /*************************************************************************** *REG_SINT_DMA_LEN - REG_SINT_DMA_LEN ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_DMA_LEN :: Length [31:05] */ #define BCHP_DECODE_SINT_0_REG_SINT_DMA_LEN_Length_MASK 0xffffffe0 #define BCHP_DECODE_SINT_0_REG_SINT_DMA_LEN_Length_SHIFT 5 /* DECODE_SINT_0 :: REG_SINT_DMA_LEN :: reserved0 [04:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_DMA_LEN_reserved0_MASK 0x0000001f #define BCHP_DECODE_SINT_0_REG_SINT_DMA_LEN_reserved0_SHIFT 0 /*************************************************************************** *REG_SINT_DMA_BASE - REG_SINT_DMA_BASE ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_DMA_BASE :: Base [31:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_DMA_BASE_Base_MASK 0xffffff00 #define BCHP_DECODE_SINT_0_REG_SINT_DMA_BASE_Base_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_DMA_BASE :: reserved0 [07:01] */ #define BCHP_DECODE_SINT_0_REG_SINT_DMA_BASE_reserved0_MASK 0x000000fe #define BCHP_DECODE_SINT_0_REG_SINT_DMA_BASE_reserved0_SHIFT 1 /* DECODE_SINT_0 :: REG_SINT_DMA_BASE :: Endian [00:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_DMA_BASE_Endian_MASK 0x00000001 #define BCHP_DECODE_SINT_0_REG_SINT_DMA_BASE_Endian_SHIFT 0 /*************************************************************************** *REG_SINT_DMA_END - REG_SINT_DMA_END ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_DMA_END :: End [31:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_DMA_END_End_MASK 0xffffffff #define BCHP_DECODE_SINT_0_REG_SINT_DMA_END_End_SHIFT 0 /*************************************************************************** *REG_SINT_STRM_POS - REG_SINT_STRM_POS ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_STRM_POS :: Bit_pos [31:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_POS_Bit_pos_MASK 0xffffffff #define BCHP_DECODE_SINT_0_REG_SINT_STRM_POS_Bit_pos_SHIFT 0 /*************************************************************************** *REG_SINT_STRM_STAT - REG_SINT_STRM_STAT ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: reserved0 [31:19] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_reserved0_MASK 0xfff80000 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_reserved0_SHIFT 19 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: FlushInput [18:18] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_FlushInput_MASK 0x00040000 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_FlushInput_SHIFT 18 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: FlushCTX [17:17] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_FlushCTX_MASK 0x00020000 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_FlushCTX_SHIFT 17 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Rst [16:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Rst_MASK 0x00010000 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Rst_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: reserved1 [15:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_reserved1_MASK 0x0000f000 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_reserved1_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: CtxDmaAct [11:11] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_CtxDmaAct_MASK 0x00000800 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_CtxDmaAct_SHIFT 11 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: MVD_AVAIL [10:10] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_MVD_AVAIL_MASK 0x00000400 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_MVD_AVAIL_SHIFT 10 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Derr [09:09] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Derr_MASK 0x00000200 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Derr_SHIFT 9 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Serr [08:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Serr_MASK 0x00000100 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Serr_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: CgParse [07:07] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_CgParse_MASK 0x00000080 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_CgParse_SHIFT 7 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: CCAc [06:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_CCAc_MASK 0x00000040 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_CCAc_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: VCAc [05:05] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_VCAc_MASK 0x00000020 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_VCAc_SHIFT 5 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Vact [04:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Vact_MASK 0x00000010 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Vact_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Dact [03:03] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Dact_MASK 0x00000008 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Dact_SHIFT 3 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Sact [02:02] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Sact_MASK 0x00000004 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Sact_SHIFT 2 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Cact [01:01] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Cact_MASK 0x00000002 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Cact_SHIFT 1 /* DECODE_SINT_0 :: REG_SINT_STRM_STAT :: Sval [00:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Sval_MASK 0x00000001 #define BCHP_DECODE_SINT_0_REG_SINT_STRM_STAT_Sval_SHIFT 0 /*************************************************************************** *REG_SINT_IENA - REG_SINT_IENA ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_IENA :: reserved0 [31:10] */ #define BCHP_DECODE_SINT_0_REG_SINT_IENA_reserved0_MASK 0xfffffc00 #define BCHP_DECODE_SINT_0_REG_SINT_IENA_reserved0_SHIFT 10 /* DECODE_SINT_0 :: REG_SINT_IENA :: Derr [09:09] */ #define BCHP_DECODE_SINT_0_REG_SINT_IENA_Derr_MASK 0x00000200 #define BCHP_DECODE_SINT_0_REG_SINT_IENA_Derr_SHIFT 9 /* DECODE_SINT_0 :: REG_SINT_IENA :: Serr [08:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_IENA_Serr_MASK 0x00000100 #define BCHP_DECODE_SINT_0_REG_SINT_IENA_Serr_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_IENA :: reserved1 [07:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_IENA_reserved1_MASK 0x000000ff #define BCHP_DECODE_SINT_0_REG_SINT_IENA_reserved1_SHIFT 0 /*************************************************************************** *REG_SINT_STRM_BITS - REG_SINT_STRM_BITS ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_STRM_BITS :: Stream_Bits [31:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_STRM_BITS_Stream_Bits_MASK 0xffffffff #define BCHP_DECODE_SINT_0_REG_SINT_STRM_BITS_Stream_Bits_SHIFT 0 /*************************************************************************** *REG_SINT_GET_SYMB - REG_SINT_GET_SYMB ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_GET_SYMB :: reserved0 [31:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_reserved0_MASK 0xffff0000 #define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_reserved0_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_GET_SYMB :: Type [15:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_Type_MASK 0x0000f000 #define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_Type_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_GET_SYMB :: SubType [11:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_SubType_MASK 0x00000f00 #define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_SubType_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_GET_SYMB :: N [07:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_N_MASK 0x000000ff #define BCHP_DECODE_SINT_0_REG_SINT_GET_SYMB_N_SHIFT 0 /*************************************************************************** *REG_SINT_MPEG_DC - REG_SINT_MPEG_DC ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_MPEG_DC :: reserved0 [31:14] */ #define BCHP_DECODE_SINT_0_REG_SINT_MPEG_DC_reserved0_MASK 0xffffc000 #define BCHP_DECODE_SINT_0_REG_SINT_MPEG_DC_reserved0_SHIFT 14 /* DECODE_SINT_0 :: REG_SINT_MPEG_DC :: Comp [13:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_MPEG_DC_Comp_MASK 0x00003000 #define BCHP_DECODE_SINT_0_REG_SINT_MPEG_DC_Comp_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_MPEG_DC :: DC_Pred [11:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_MPEG_DC_DC_Pred_MASK 0x00000fff #define BCHP_DECODE_SINT_0_REG_SINT_MPEG_DC_DC_Pred_SHIFT 0 /*************************************************************************** *REG_SINT_DO_RESID - REG_SINT_DO_RESID ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: AVS [31:31] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_AVS_MASK 0x80000000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_AVS_SHIFT 31 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: DivX [30:30] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_DivX_MASK 0x40000000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_DivX_SHIFT 30 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Use_intra_dc_vlc [29:29] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Use_intra_dc_vlc_MASK 0x20000000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Use_intra_dc_vlc_SHIFT 29 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Short_Vid_Hdr [28:28] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Short_Vid_Hdr_MASK 0x10000000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Short_Vid_Hdr_SHIFT 28 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Mpeg4 [27:27] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Mpeg4_MASK 0x08000000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Mpeg4_SHIFT 27 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: VC_TTMbf [26:26] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_TTMbf_MASK 0x04000000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_TTMbf_SHIFT 26 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: VC_TTFrmSize [25:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_TTFrmSize_MASK 0x03000000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_TTFrmSize_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: reserved0 [23:22] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_reserved0_MASK 0x00c00000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_reserved0_SHIFT 22 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: VC_DBlkEna [21:21] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_DBlkEna_MASK 0x00200000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_DBlkEna_SHIFT 21 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: VC_OlapEna [20:20] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_OlapEna_MASK 0x00100000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VC_OlapEna_SHIFT 20 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: FastEna [19:19] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_FastEna_MASK 0x00080000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_FastEna_SHIFT 19 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Skip [18:18] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Skip_MASK 0x00040000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Skip_SHIFT 18 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Intra_264 [17:17] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Intra_264_MASK 0x00020000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Intra_264_SHIFT 17 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Fetch_QP [16:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Fetch_QP_MASK 0x00010000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Fetch_QP_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Type [15:14] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Type_MASK 0x0000c000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Type_SHIFT 14 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: SubType [13:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_SubType_MASK 0x00003000 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_SubType_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: SwapCBP [11:11] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_SwapCBP_MASK 0x00000800 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_SwapCBP_SHIFT 11 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: WrXNZero [10:10] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_WrXNZero_MASK 0x00000400 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_WrXNZero_SHIFT 10 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: DCPrecision [09:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_DCPrecision_MASK 0x00000300 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_DCPrecision_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: VLCTable1 [07:07] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VLCTable1_MASK 0x00000080 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_VLCTable1_SHIFT 7 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: Intra [06:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Intra_MASK 0x00000040 #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_Intra_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_DO_RESID :: CBP [05:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_CBP_MASK 0x0000003f #define BCHP_DECODE_SINT_0_REG_SINT_DO_RESID_CBP_SHIFT 0 /*************************************************************************** *REG_SINT_XNZERO - REG_SINT_XNZERO ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_XNZERO :: reserved0 [31:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_reserved0_MASK 0xffff0000 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_reserved0_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B15 [15:15] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B15_MASK 0x00008000 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B15_SHIFT 15 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B14 [14:14] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B14_MASK 0x00004000 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B14_SHIFT 14 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B13 [13:13] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B13_MASK 0x00002000 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B13_SHIFT 13 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B12 [12:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B12_MASK 0x00001000 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B12_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B11 [11:11] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B11_MASK 0x00000800 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B11_SHIFT 11 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B10 [10:10] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B10_MASK 0x00000400 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B10_SHIFT 10 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B9 [09:09] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B9_MASK 0x00000200 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B9_SHIFT 9 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B8 [08:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B8_MASK 0x00000100 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B8_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B7 [07:07] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B7_MASK 0x00000080 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B7_SHIFT 7 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B6 [06:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B6_MASK 0x00000040 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B6_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B5 [05:05] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B5_MASK 0x00000020 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B5_SHIFT 5 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B4 [04:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B4_MASK 0x00000010 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B4_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B3 [03:03] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B3_MASK 0x00000008 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B3_SHIFT 3 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B2 [02:02] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B2_MASK 0x00000004 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B2_SHIFT 2 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B1 [01:01] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B1_MASK 0x00000002 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B1_SHIFT 1 /* DECODE_SINT_0 :: REG_SINT_XNZERO :: B0 [00:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B0_MASK 0x00000001 #define BCHP_DECODE_SINT_0_REG_SINT_XNZERO_B0_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_MBTYPE - REG_SINT_VEC_MBTYPE ***************************************************************************/ /* union - case H264 [31:00] */ /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: reserved0 [31:25] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved0_MASK 0xfe000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved0_SHIFT 25 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: SubMBType3 [24:21] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType3_MASK 0x01e00000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType3_SHIFT 21 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: reserved1 [20:20] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved1_MASK 0x00100000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved1_SHIFT 20 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: SubMBType2 [19:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType2_MASK 0x000f0000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType2_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: reserved2 [15:15] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved2_MASK 0x00008000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved2_SHIFT 15 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: SubMBType1 [14:11] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType1_MASK 0x00007800 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType1_SHIFT 11 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: reserved3 [10:10] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved3_MASK 0x00000400 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_reserved3_SHIFT 10 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: SubMBType0 [09:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType0_MASK 0x000003c0 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_SubMBType0_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: MBType [05:01] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_MBType_MASK 0x0000003e #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_MBType_SHIFT 1 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: H264 :: ISB [00:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_ISB_MASK 0x00000001 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_H264_ISB_SHIFT 0 /* union - case VC1 [31:00] */ /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: reserved0 [31:22] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_reserved0_MASK 0xffc00000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_reserved0_SHIFT 22 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: BlkPat [21:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_BlkPat_MASK 0x003f0000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_BlkPat_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: reserved1 [15:14] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_reserved1_MASK 0x0000c000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_reserved1_SHIFT 14 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: MBMode [13:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_MBMode_MASK 0x00003f00 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_MBMode_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: reserved2 [07:07] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_reserved2_MASK 0x00000080 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_reserved2_SHIFT 7 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: BMVType [06:05] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_BMVType_MASK 0x00000060 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_BMVType_SHIFT 5 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: MVSW [04:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_MVSW_MASK 0x00000010 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_MVSW_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: InterpMVP [03:03] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_InterpMVP_MASK 0x00000008 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_InterpMVP_SHIFT 3 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: Forward [02:02] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_Forward_MASK 0x00000004 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_Forward_SHIFT 2 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: Direct [01:01] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_Direct_MASK 0x00000002 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_Direct_SHIFT 1 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: VC1 :: Skip [00:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_Skip_MASK 0x00000001 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_VC1_Skip_SHIFT 0 /* union - case MPEG4 [31:00] */ /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: reserved0 [31:14] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_reserved0_MASK 0xffffc000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_reserved0_SHIFT 14 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: qpel [13:13] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_qpel_MASK 0x00002000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_qpel_SHIFT 13 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: gmc [12:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_gmc_MASK 0x00001000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_gmc_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: no_mvd [11:11] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_no_mvd_MASK 0x00000800 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_no_mvd_SHIFT 11 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: intra [10:10] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_intra_MASK 0x00000400 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_intra_SHIFT 10 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: fcode_back [09:07] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_fcode_back_MASK 0x00000380 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_fcode_back_SHIFT 7 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: fcode_fwd [06:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_fcode_fwd_MASK 0x00000070 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_fcode_fwd_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: four_mv [03:03] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_four_mv_MASK 0x00000008 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_four_mv_SHIFT 3 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: alt_mv [02:02] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_alt_mv_MASK 0x00000004 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_alt_mv_SHIFT 2 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: direct [01:01] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_direct_MASK 0x00000002 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_direct_SHIFT 1 /* DECODE_SINT_0 :: REG_SINT_VEC_MBTYPE :: MPEG4 :: skip [00:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_skip_MASK 0x00000001 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MBTYPE_MPEG4_skip_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_RESID - REG_SINT_VEC_RESID ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_RESID :: Y_Residual [31:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_RESID_Y_Residual_MASK 0xffff0000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_RESID_Y_Residual_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_RESID :: X_Residual [15:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_RESID_X_Residual_MASK 0x0000ffff #define BCHP_DECODE_SINT_0_REG_SINT_VEC_RESID_X_Residual_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_DMODE - REG_SINT_VEC_DMODE ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_DMODE :: reserved0 [31:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DMODE_reserved0_MASK 0xfffffff0 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DMODE_reserved0_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_VEC_DMODE :: Dmode [03:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DMODE_Dmode_MASK 0x0000000f #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DMODE_Dmode_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_TOP_LD - REG_SINT_VEC_TOP_LD ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_TOP_LD :: reserved0 [31:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOP_LD_reserved0_MASK 0xffffffff #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOP_LD_reserved0_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_DO_CONST - REG_SINT_VEC_DO_CONST ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: reserved0 [31:28] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_reserved0_MASK 0xf0000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_reserved0_SHIFT 28 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: direct_frm2fld [27:27] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_direct_frm2fld_MASK 0x08000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_direct_frm2fld_SHIFT 27 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: wholepel_8x8 [26:26] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_wholepel_8x8_MASK 0x04000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_wholepel_8x8_SHIFT 26 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: wholepel_all [25:25] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_wholepel_all_MASK 0x02000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_wholepel_all_SHIFT 25 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: VC1_1ref_is_bot [24:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_1ref_is_bot_MASK 0x01000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_1ref_is_bot_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: refdist_back [23:22] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_refdist_back_MASK 0x00c00000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_refdist_back_SHIFT 22 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: refdist_fwd [21:20] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_refdist_fwd_MASK 0x00300000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_refdist_fwd_SHIFT 20 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: VC1_2nd_fld [19:19] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_2nd_fld_MASK 0x00080000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_2nd_fld_SHIFT 19 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: Back_is_intl [18:18] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Back_is_intl_MASK 0x00040000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Back_is_intl_SHIFT 18 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: Fwd_is_intl [17:17] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Fwd_is_intl_MASK 0x00020000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Fwd_is_intl_SHIFT 17 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: VC1_2ref [16:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_2ref_MASK 0x00010000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_2ref_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: VC1_bfract_gt_half [15:15] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_bfract_gt_half_MASK 0x00008000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_bfract_gt_half_SHIFT 15 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: VC1_DmvRange [14:13] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_DmvRange_MASK 0x00006000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_DmvRange_SHIFT 13 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: VC1_mvRange [12:11] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_mvRange_MASK 0x00001800 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_mvRange_SHIFT 11 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: VC1_HalfPel [10:10] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_HalfPel_MASK 0x00000400 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_VC1_HalfPel_SHIFT 10 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: MVDiff [09:09] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_MVDiff_MASK 0x00000200 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_MVDiff_SHIFT 9 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: ROLT [08:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_ROLT_MASK 0x00000100 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_ROLT_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: Lcpy [07:07] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Lcpy_MASK 0x00000080 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Lcpy_SHIFT 7 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: reserved1 [06:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_reserved1_MASK 0x00000040 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_reserved1_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: Pskip [05:05] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Pskip_MASK 0x00000020 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Pskip_SHIFT 5 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: Intra [04:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Intra_MASK 0x00000010 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_Intra_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_VEC_DO_CONST :: reserved2 [03:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_reserved2_MASK 0x0000000f #define BCHP_DECODE_SINT_0_REG_SINT_VEC_DO_CONST_reserved2_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_MVDIFF - Deblocking Motion Vector Difference ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V15 [31:31] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V15_MASK 0x80000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V15_SHIFT 31 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V14 [30:30] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V14_MASK 0x40000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V14_SHIFT 30 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V13 [29:29] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V13_MASK 0x20000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V13_SHIFT 29 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V12 [28:28] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V12_MASK 0x10000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V12_SHIFT 28 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V11 [27:27] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V11_MASK 0x08000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V11_SHIFT 27 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V10 [26:26] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V10_MASK 0x04000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V10_SHIFT 26 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V9 [25:25] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V9_MASK 0x02000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V9_SHIFT 25 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V8 [24:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V8_MASK 0x01000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V8_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V7 [23:23] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V7_MASK 0x00800000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V7_SHIFT 23 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V6 [22:22] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V6_MASK 0x00400000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V6_SHIFT 22 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V5 [21:21] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V5_MASK 0x00200000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V5_SHIFT 21 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V4 [20:20] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V4_MASK 0x00100000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V4_SHIFT 20 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V3 [19:19] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V3_MASK 0x00080000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V3_SHIFT 19 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V2 [18:18] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V2_MASK 0x00040000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V2_SHIFT 18 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V1 [17:17] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V1_MASK 0x00020000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V1_SHIFT 17 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: V0 [16:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V0_MASK 0x00010000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_V0_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H15 [15:15] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H15_MASK 0x00008000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H15_SHIFT 15 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H14 [14:14] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H14_MASK 0x00004000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H14_SHIFT 14 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H13 [13:13] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H13_MASK 0x00002000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H13_SHIFT 13 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H12 [12:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H12_MASK 0x00001000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H12_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H11 [11:11] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H11_MASK 0x00000800 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H11_SHIFT 11 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H10 [10:10] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H10_MASK 0x00000400 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H10_SHIFT 10 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H9 [09:09] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H9_MASK 0x00000200 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H9_SHIFT 9 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H8 [08:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H8_MASK 0x00000100 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H8_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H7 [07:07] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H7_MASK 0x00000080 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H7_SHIFT 7 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H6 [06:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H6_MASK 0x00000040 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H6_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H5 [05:05] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H5_MASK 0x00000020 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H5_SHIFT 5 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H4 [04:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H4_MASK 0x00000010 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H4_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H3 [03:03] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H3_MASK 0x00000008 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H3_SHIFT 3 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H2 [02:02] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H2_MASK 0x00000004 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H2_SHIFT 2 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H1 [01:01] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H1_MASK 0x00000002 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H1_SHIFT 1 /* DECODE_SINT_0 :: REG_SINT_VEC_MVDIFF :: H0 [00:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H0_MASK 0x00000001 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVDIFF_H0_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_REFIDX - REG_SINT_VEC_REFIDX ***************************************************************************/ /* union - case WRITE [31:00] */ /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: reserved0 [31:30] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved0_MASK 0xc0000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved0_SHIFT 30 /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: RefIdx3 [29:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx3_MASK 0x3f000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx3_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: reserved1 [23:22] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved1_MASK 0x00c00000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved1_SHIFT 22 /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: RefIdx2 [21:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx2_MASK 0x003f0000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx2_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: reserved2 [15:14] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved2_MASK 0x0000c000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved2_SHIFT 14 /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: RefIdx1 [13:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx1_MASK 0x00003f00 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx1_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: reserved3 [07:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved3_MASK 0x000000c0 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_reserved3_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: WRITE :: RefIdx0 [05:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx0_MASK 0x0000003f #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_WRITE_RefIdx0_SHIFT 0 /* union - case READ [31:00] */ /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: reserved0 [31:30] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved0_MASK 0xc0000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved0_SHIFT 30 /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: Ref1_L1 [29:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref1_L1_MASK 0x3f000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref1_L1_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: reserved1 [23:22] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved1_MASK 0x00c00000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved1_SHIFT 22 /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: Ref1_L0 [21:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref1_L0_MASK 0x003f0000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref1_L0_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: reserved2 [15:14] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved2_MASK 0x0000c000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved2_SHIFT 14 /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: Ref0_L1 [13:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref0_L1_MASK 0x00003f00 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref0_L1_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: reserved3 [07:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved3_MASK 0x000000c0 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_reserved3_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_VEC_REFIDX :: READ :: Ref0_L0 [05:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref0_L0_MASK 0x0000003f #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFIDX_READ_Ref0_L0_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_TOPREF - REG_SINT_VEC_TOPREF ***************************************************************************/ /* union - case H264 [31:00] */ /* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: H264 :: L1RefB1 [31:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L1RefB1_MASK 0xff000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L1RefB1_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: H264 :: L1RefB0 [23:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L1RefB0_MASK 0x00ff0000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L1RefB0_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: H264 :: L0RefB1 [15:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L0RefB1_MASK 0x0000ff00 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L0RefB1_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: H264 :: L0RefB0 [07:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L0RefB0_MASK 0x000000ff #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_H264_L0RefB0_SHIFT 0 /* union - case VC1 [31:00] */ /* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: ChrIntra [31:31] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_ChrIntra_MASK 0x80000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_ChrIntra_SHIFT 31 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: IsField [30:30] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_IsField_MASK 0x40000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_IsField_SHIFT 30 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk3Bac [29:28] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk3Bac_MASK 0x30000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk3Bac_SHIFT 28 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk2Bac [27:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk2Bac_MASK 0x0f000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk2Bac_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk1Back [23:20] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk1Back_MASK 0x00f00000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk1Back_SHIFT 20 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk0Back [19:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk0Back_MASK 0x000f0000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk0Back_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk3Fwd [15:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk3Fwd_MASK 0x0000f000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk3Fwd_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk2Fwd [11:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk2Fwd_MASK 0x00000f00 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk2Fwd_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk1Fwd [07:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk1Fwd_MASK 0x000000f0 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk1Fwd_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPREF :: VC1 :: Blk0Fwd [03:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk0Fwd_MASK 0x0000000f #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPREF_VC1_Blk0Fwd_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_TOPTOPREF - REG_SINT_VEC_TOPTOPREF ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_TOPTOPREF :: L1PicB1 [31:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_L1PicB1_MASK 0xff000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_L1PicB1_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPTOPREF :: reserved0 [23:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_reserved0_MASK 0x00ff0000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_reserved0_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPTOPREF :: L0PicB1 [15:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_L0PicB1_MASK 0x0000ff00 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_L0PicB1_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPTOPREF :: reserved1 [07:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_reserved1_MASK 0x000000ff #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPTOPREF_reserved1_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_COL_TYPE - REG_SINT_VEC_COL_TYPE ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: MBAFF [31:31] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_MBAFF_MASK 0x80000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_MBAFF_SHIFT 31 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: TFld [30:30] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_TFld_MASK 0x40000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_TFld_SHIFT 30 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: Field [29:29] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Field_MASK 0x20000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Field_SHIFT 29 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: reserved0 [28:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_reserved0_MASK 0x1ffff000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_reserved0_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: AvsSpatial1 [11:11] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_AvsSpatial1_MASK 0x00000800 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_AvsSpatial1_SHIFT 11 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: AvsSpatial0 [10:10] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_AvsSpatial0_MASK 0x00000400 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_AvsSpatial0_SHIFT 10 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: Sub3 [09:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub3_MASK 0x00000300 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub3_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: Sub2 [07:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub2_MASK 0x000000c0 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub2_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: Sub1 [05:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub1_MASK 0x00000030 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub1_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: Sub0 [03:02] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub0_MASK 0x0000000c #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Sub0_SHIFT 2 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_TYPE :: Type [01:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Type_MASK 0x00000003 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_TYPE_Type_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_COL_REFID - REG_SINT_VEC_COL_REFID ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: reserved0 [31:29] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved0_MASK 0xe0000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved0_SHIFT 29 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: RefIdx3 [28:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx3_MASK 0x1f000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx3_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: reserved1 [23:21] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved1_MASK 0x00e00000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved1_SHIFT 21 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: RefIdx2 [20:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx2_MASK 0x001f0000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx2_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: reserved2 [15:13] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved2_MASK 0x0000e000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved2_SHIFT 13 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: RefIdx1 [12:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx1_MASK 0x00001f00 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx1_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: reserved3 [07:05] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved3_MASK 0x000000e0 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_reserved3_SHIFT 5 /* DECODE_SINT_0 :: REG_SINT_VEC_COL_REFID :: RefIdx0 [04:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx0_MASK 0x0000001f #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COL_REFID_RefIdx0_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_TOPPIC - REG_SINT_VEC_TOPPIC ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_TOPPIC :: L1PicB1 [31:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L1PicB1_MASK 0xff000000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L1PicB1_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPPIC :: L1PicB0 [23:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L1PicB0_MASK 0x00ff0000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L1PicB0_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPPIC :: L0PicB1 [15:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L0PicB1_MASK 0x0000ff00 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L0PicB1_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_VEC_TOPPIC :: L0PicB0 [07:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L0PicB0_MASK 0x000000ff #define BCHP_DECODE_SINT_0_REG_SINT_VEC_TOPPIC_L0PicB0_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_VC1_INFO - REG_SINT_VEC_VC1_INFO ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: reserved0 [31:22] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_reserved0_MASK 0xffc00000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_reserved0_SHIFT 22 /* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: Intra_Flags [21:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_Intra_Flags_MASK 0x003f0000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_Intra_Flags_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: reserved1 [15:14] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_reserved1_MASK 0x0000c000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_reserved1_SHIFT 14 /* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: CBPCY [13:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_CBPCY_MASK 0x00003f00 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_CBPCY_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: reserved2 [07:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_reserved2_MASK 0x000000c0 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_reserved2_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: BMV_TYPE [05:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_BMV_TYPE_MASK 0x00000030 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_BMV_TYPE_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: field_4MV [03:03] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_field_4MV_MASK 0x00000008 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_field_4MV_SHIFT 3 /* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: GET_AC_PRED [02:02] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_GET_AC_PRED_MASK 0x00000004 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_GET_AC_PRED_SHIFT 2 /* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: COEFS_PRES [01:01] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_COEFS_PRES_MASK 0x00000002 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_COEFS_PRES_SHIFT 1 /* DECODE_SINT_0 :: REG_SINT_VEC_VC1_INFO :: INTRA [00:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_INTRA_MASK 0x00000001 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_VC1_INFO_INTRA_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_REFPIC - REG_SINT_VEC_REFPIC - H.264 only ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_REFPIC :: reserved0 [31:03] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_reserved0_MASK 0xfffffff8 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_reserved0_SHIFT 3 /* DECODE_SINT_0 :: REG_SINT_VEC_REFPIC :: Hwimpiwt [02:02] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_Hwimpiwt_MASK 0x00000004 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_Hwimpiwt_SHIFT 2 /* DECODE_SINT_0 :: REG_SINT_VEC_REFPIC :: UserRev [01:01] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_UserRev_MASK 0x00000002 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_UserRev_SHIFT 1 /* DECODE_SINT_0 :: REG_SINT_VEC_REFPIC :: RamSel [00:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_RamSel_MASK 0x00000001 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REFPIC_RamSel_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_COUNT - REG_SINT_VEC_COUNT ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_COUNT :: Cnt8x8UA [31:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COUNT_Cnt8x8UA_MASK 0xffff0000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COUNT_Cnt8x8UA_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_COUNT :: Cnt8x8 [15:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COUNT_Cnt8x8_MASK 0x0000ffff #define BCHP_DECODE_SINT_0_REG_SINT_VEC_COUNT_Cnt8x8_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_MVD_FIFO - REG_SINT_VEC_MVD_FIFO ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_MVD_FIFO :: Data [31:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVD_FIFO_Data_MASK 0xffffffff #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MVD_FIFO_Data_SHIFT 0 /*************************************************************************** *REG_SINT_DIVX_TABSEL - REG_SINT_DIVX_TABSEL ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: reserved0 [31:09] */ #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_reserved0_MASK 0xfffffe00 #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_reserved0_SHIFT 9 /* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: P_frame [08:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_P_frame_MASK 0x00000100 #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_P_frame_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_I_AC_chrom_DCT [07:07] */ #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_chrom_DCT_MASK 0x00000080 #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_chrom_DCT_SHIFT 7 /* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_I_AC_chrom_DCT_index [06:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_chrom_DCT_index_MASK 0x00000040 #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_chrom_DCT_index_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_I_AC_lum_DCT [05:05] */ #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_lum_DCT_MASK 0x00000020 #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_lum_DCT_SHIFT 5 /* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_I_AC_lum_DCT_index [04:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_lum_DCT_index_MASK 0x00000010 #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_AC_lum_DCT_index_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_I_DC_DCT [03:03] */ #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_DC_DCT_MASK 0x00000008 #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_I_DC_DCT_SHIFT 3 /* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_P_AC_DCT [02:02] */ #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_P_AC_DCT_MASK 0x00000004 #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_P_AC_DCT_SHIFT 2 /* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_P_AC_DCT_index [01:01] */ #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_P_AC_DCT_index_MASK 0x00000002 #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_P_AC_DCT_index_SHIFT 1 /* DECODE_SINT_0 :: REG_SINT_DIVX_TABSEL :: alt_P_DC_DCT [00:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_P_DC_DCT_MASK 0x00000001 #define BCHP_DECODE_SINT_0_REG_SINT_DIVX_TABSEL_alt_P_DC_DCT_SHIFT 0 /*************************************************************************** *REG_SINT_CTL_AUX - REG_SINT_CTL_AUX ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_CTL_AUX :: reserved0 [31:02] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_AUX_reserved0_MASK 0xfffffffc #define BCHP_DECODE_SINT_0_REG_SINT_CTL_AUX_reserved0_SHIFT 2 /* DECODE_SINT_0 :: REG_SINT_CTL_AUX :: ref_ld_2bit [01:01] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_AUX_ref_ld_2bit_MASK 0x00000002 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_AUX_ref_ld_2bit_SHIFT 1 /* DECODE_SINT_0 :: REG_SINT_CTL_AUX :: avs_mode [00:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_AUX_avs_mode_MASK 0x00000001 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_AUX_avs_mode_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_REGEND - REG_SINT_VEC_REGEND ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_REGEND :: reserved0 [31:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REGEND_reserved0_MASK 0xffffffff #define BCHP_DECODE_SINT_0_REG_SINT_VEC_REGEND_reserved0_SHIFT 0 /*************************************************************************** *REG_SINT_CTL - REG_SINT_CTL ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_CTL :: VC1 [31:31] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_VC1_MASK 0x80000000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_VC1_SHIFT 31 /* DECODE_SINT_0 :: REG_SINT_CTL :: regacc_disable [30:30] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_regacc_disable_MASK 0x40000000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_regacc_disable_SHIFT 30 /* DECODE_SINT_0 :: REG_SINT_CTL :: use_qs_table [29:29] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_use_qs_table_MASK 0x20000000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_use_qs_table_SHIFT 29 /* DECODE_SINT_0 :: REG_SINT_CTL :: MPEG4 [28:28] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_MPEG4_MASK 0x10000000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_MPEG4_SHIFT 28 /* DECODE_SINT_0 :: REG_SINT_CTL :: xform_8x8 [27:27] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_xform_8x8_MASK 0x08000000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_xform_8x8_SHIFT 27 /* DECODE_SINT_0 :: REG_SINT_CTL :: mode_8x8 [26:26] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_mode_8x8_MASK 0x04000000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_mode_8x8_SHIFT 26 /* DECODE_SINT_0 :: REG_SINT_CTL :: mono_mode [25:25] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_mono_mode_MASK 0x02000000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_mono_mode_SHIFT 25 /* DECODE_SINT_0 :: REG_SINT_CTL :: DIVX311 [24:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_DIVX311_MASK 0x01000000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_DIVX311_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_CTL :: Profile [23:22] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Profile_MASK 0x00c00000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Profile_SHIFT 22 /* DECODE_SINT_0 :: REG_SINT_CTL :: IWtPred [21:21] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_IWtPred_MASK 0x00200000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_IWtPred_SHIFT 21 /* DECODE_SINT_0 :: REG_SINT_CTL :: WtPred [20:20] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_WtPred_MASK 0x00100000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_WtPred_SHIFT 20 /* DECODE_SINT_0 :: REG_SINT_CTL :: Use_field_pred [19:19] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Use_field_pred_MASK 0x00080000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Use_field_pred_SHIFT 19 /* DECODE_SINT_0 :: REG_SINT_CTL :: bot_field [18:18] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_bot_field_MASK 0x00040000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_bot_field_SHIFT 18 /* DECODE_SINT_0 :: REG_SINT_CTL :: L1_Eq_2 [17:17] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_L1_Eq_2_MASK 0x00020000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_L1_Eq_2_SHIFT 17 /* DECODE_SINT_0 :: REG_SINT_CTL :: L1_Eq_1 [16:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_L1_Eq_1_MASK 0x00010000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_L1_Eq_1_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_CTL :: L0_Eq_2 [15:15] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_L0_Eq_2_MASK 0x00008000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_L0_Eq_2_SHIFT 15 /* DECODE_SINT_0 :: REG_SINT_CTL :: L0_Eq_1 [14:14] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_L0_Eq_1_MASK 0x00004000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_L0_Eq_1_SHIFT 14 /* DECODE_SINT_0 :: REG_SINT_CTL :: new_slice [13:13] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_new_slice_MASK 0x00002000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_new_slice_SHIFT 13 /* DECODE_SINT_0 :: REG_SINT_CTL :: reserved_for_eco0 [12:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_reserved_for_eco0_MASK 0x00001000 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_reserved_for_eco0_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_CTL :: Dir_8x8 [11:11] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Dir_8x8_MASK 0x00000800 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Dir_8x8_SHIFT 11 /* DECODE_SINT_0 :: REG_SINT_CTL :: Spa_Dir [10:10] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Spa_Dir_MASK 0x00000400 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Spa_Dir_SHIFT 10 /* DECODE_SINT_0 :: REG_SINT_CTL :: PTYPE [09:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_PTYPE_MASK 0x00000300 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_PTYPE_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_CTL :: MBAFF [07:07] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_MBAFF_MASK 0x00000080 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_MBAFF_SHIFT 7 /* DECODE_SINT_0 :: REG_SINT_CTL :: TFld [06:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_TFld_MASK 0x00000040 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_TFld_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_CTL :: Field [05:05] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Field_MASK 0x00000020 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Field_SHIFT 5 /* DECODE_SINT_0 :: REG_SINT_CTL :: CAVLC [04:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_CAVLC_MASK 0x00000010 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_CAVLC_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_CTL :: Uleft [03:03] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Uleft_MASK 0x00000008 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Uleft_SHIFT 3 /* DECODE_SINT_0 :: REG_SINT_CTL :: Top [02:02] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Top_MASK 0x00000004 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Top_SHIFT 2 /* DECODE_SINT_0 :: REG_SINT_CTL :: Left [01:01] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Left_MASK 0x00000002 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_Left_SHIFT 1 /* DECODE_SINT_0 :: REG_SINT_CTL :: URtAvail [00:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTL_URtAvail_MASK 0x00000001 #define BCHP_DECODE_SINT_0_REG_SINT_CTL_URtAvail_SHIFT 0 /*************************************************************************** *REG_SINT_VLC_TOPCTX - REG_SINT_VLC_TOPCTX ***************************************************************************/ /* union - case VLC [31:00] */ /* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: V2 [31:28] */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_V2_MASK 0xf0000000 #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_V2_SHIFT 28 /* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: V3 [27:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_V3_MASK 0x0f000000 #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_V3_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: U2 [23:20] */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_U2_MASK 0x00f00000 #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_U2_SHIFT 20 /* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: U3 [19:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_U3_MASK 0x000f0000 #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_U3_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: Lum10 [15:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum10_MASK 0x0000f000 #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum10_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: Lum11 [11:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum11_MASK 0x00000f00 #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum11_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: Lum14 [07:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum14_MASK 0x000000f0 #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum14_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VLC :: Lum15 [03:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum15_MASK 0x0000000f #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VLC_Lum15_SHIFT 0 /* union - case VC1 [31:00] */ /* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VC1 :: reserved0 [31:25] */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_reserved0_MASK 0xfe000000 #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_reserved0_SHIFT 25 /* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VC1 :: Top4x4 [24:21] */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_Top4x4_MASK 0x01e00000 #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_Top4x4_SHIFT 21 /* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VC1 :: TopXNZ [20:13] */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopXNZ_MASK 0x001fe000 #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopXNZ_SHIFT 13 /* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VC1 :: TopOlapEnb [12:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopOlapEnb_MASK 0x00001000 #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopOlapEnb_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VC1 :: TopIntra [11:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopIntra_MASK 0x00000fc0 #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopIntra_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_VLC_TOPCTX :: VC1 :: TopCBP [05:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopCBP_MASK 0x0000003f #define BCHP_DECODE_SINT_0_REG_SINT_VLC_TOPCTX_VC1_TopCBP_SHIFT 0 /*************************************************************************** *REG_SINT_SLICE_ID - REG_SINT_SLICE_ID ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_SLICE_ID :: reserved0 [31:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_SLICE_ID_reserved0_MASK 0xfffff000 #define BCHP_DECODE_SINT_0_REG_SINT_SLICE_ID_reserved0_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_SLICE_ID :: SliceID [11:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_SLICE_ID_SliceID_MASK 0x00000fff #define BCHP_DECODE_SINT_0_REG_SINT_SLICE_ID_SliceID_SHIFT 0 /*************************************************************************** *REG_SINT_QP - REG_SINT_QP ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_QP :: reserved0 [31:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_QP_reserved0_MASK 0xffffffc0 #define BCHP_DECODE_SINT_0_REG_SINT_QP_reserved0_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_QP :: qp [05:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_QP_qp_MASK 0x0000003f #define BCHP_DECODE_SINT_0_REG_SINT_QP_qp_SHIFT 0 /*************************************************************************** *REG_SINT_TOP_BASE_ADDR - REG_SINT_TOP_BASE_ADDR ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_TOP_BASE_ADDR :: Addr [31:06] */ #define BCHP_DECODE_SINT_0_REG_SINT_TOP_BASE_ADDR_Addr_MASK 0xffffffc0 #define BCHP_DECODE_SINT_0_REG_SINT_TOP_BASE_ADDR_Addr_SHIFT 6 /* DECODE_SINT_0 :: REG_SINT_TOP_BASE_ADDR :: reserved0 [05:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_TOP_BASE_ADDR_reserved0_MASK 0x0000003f #define BCHP_DECODE_SINT_0_REG_SINT_TOP_BASE_ADDR_reserved0_SHIFT 0 /*************************************************************************** *REG_SINT_DIRCTX_WR_ADDR - REG_SINT_DIRCTX_WR_ADDR ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_DIRCTX_WR_ADDR :: Addr [31:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_DIRCTX_WR_ADDR_Addr_MASK 0xffffffff #define BCHP_DECODE_SINT_0_REG_SINT_DIRCTX_WR_ADDR_Addr_SHIFT 0 /*************************************************************************** *REG_SINT_TOPCTX_DATA - REG_SINT_TOPCTX_DATA ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_TOPCTX_DATA :: Data [31:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_TOPCTX_DATA_Data_MASK 0xffffffff #define BCHP_DECODE_SINT_0_REG_SINT_TOPCTX_DATA_Data_SHIFT 0 /*************************************************************************** *REG_SINT_XFER_SYMB - REG_SINT_XFER_SYMB ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_XFER_SYMB :: reserved0 [31:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_XFER_SYMB_reserved0_MASK 0xffff0000 #define BCHP_DECODE_SINT_0_REG_SINT_XFER_SYMB_reserved0_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_XFER_SYMB :: Type [15:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_XFER_SYMB_Type_MASK 0x0000ff00 #define BCHP_DECODE_SINT_0_REG_SINT_XFER_SYMB_Type_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_XFER_SYMB :: N [07:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_XFER_SYMB_N_MASK 0x000000ff #define BCHP_DECODE_SINT_0_REG_SINT_XFER_SYMB_N_SHIFT 0 /*************************************************************************** *REG_SINT_SMODE_BASE - REG_SINT_SMODE_BASE ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode0 [31:28] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode0_MASK 0xf0000000 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode0_SHIFT 28 /* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode1 [27:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode1_MASK 0x0f000000 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode1_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode2 [23:20] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode2_MASK 0x00f00000 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode2_SHIFT 20 /* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode3 [19:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode3_MASK 0x000f0000 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode3_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode4 [15:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode4_MASK 0x0000f000 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode4_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode5 [11:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode5_MASK 0x00000f00 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode5_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode6 [07:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode6_MASK 0x000000f0 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode6_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_SMODE_BASE :: Mode7 [03:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode7_MASK 0x0000000f #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_BASE_Mode7_SHIFT 0 /*************************************************************************** *REG_SINT_SMODE_LEFT - REG_SINT_SMODE_LEFT ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_SMODE_LEFT :: reserved0 [31:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_reserved0_MASK 0xffff0000 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_reserved0_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_SMODE_LEFT :: LeftMode5 [15:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode5_MASK 0x0000f000 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode5_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_SMODE_LEFT :: LeftMode7 [11:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode7_MASK 0x00000f00 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode7_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_SMODE_LEFT :: LeftMode13 [07:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode13_MASK 0x000000f0 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode13_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_SMODE_LEFT :: LeftMode15 [03:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode15_MASK 0x0000000f #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_LEFT_LeftMode15_SHIFT 0 /*************************************************************************** *REG_SINT_SMODE_TOP - REG_SINT_SMODE_TOP ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_SMODE_TOP :: reserved0 [31:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_reserved0_MASK 0xffff0000 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_reserved0_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_SMODE_TOP :: TopMode10 [15:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode10_MASK 0x0000f000 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode10_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_SMODE_TOP :: TopMode11 [11:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode11_MASK 0x00000f00 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode11_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_SMODE_TOP :: TopMode14 [07:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode14_MASK 0x000000f0 #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode14_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_SMODE_TOP :: TopMode15 [03:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode15_MASK 0x0000000f #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_TOP_TopMode15_SHIFT 0 /*************************************************************************** *REG_SINT_SMODE_END - REG_SINT_SMODE_END ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_SMODE_END :: reserved0 [31:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_SINT_0_REG_SINT_SMODE_END_reserved0_SHIFT 0 /*************************************************************************** *REG_SINT_CTX_INIT - REG_SINT_CTX_INIT ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_CTX_INIT :: reserved0 [31:25] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_reserved0_MASK 0xfe000000 #define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_reserved0_SHIFT 25 /* DECODE_SINT_0 :: REG_SINT_CTX_INIT :: MBAFF [24:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_MBAFF_MASK 0x01000000 #define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_MBAFF_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_CTX_INIT :: MBWIDTH [23:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_MBWIDTH_MASK 0x00ff0000 #define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_MBWIDTH_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_CTX_INIT :: YPOS [15:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_YPOS_MASK 0x0000ff00 #define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_YPOS_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_CTX_INIT :: XPOS [07:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_XPOS_MASK 0x000000ff #define BCHP_DECODE_SINT_0_REG_SINT_CTX_INIT_XPOS_SHIFT 0 /*************************************************************************** *REG_SINT_TOP_CTX - REG_SINT_TOP_CTX ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_TOP_CTX :: reserved0 [31:05] */ #define BCHP_DECODE_SINT_0_REG_SINT_TOP_CTX_reserved0_MASK 0xffffffe0 #define BCHP_DECODE_SINT_0_REG_SINT_TOP_CTX_reserved0_SHIFT 5 /* DECODE_SINT_0 :: REG_SINT_TOP_CTX :: TOP_TOP [04:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_TOP_CTX_TOP_TOP_MASK 0x00000010 #define BCHP_DECODE_SINT_0_REG_SINT_TOP_CTX_TOP_TOP_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_TOP_CTX :: RD_OFFSET [03:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_TOP_CTX_RD_OFFSET_MASK 0x0000000f #define BCHP_DECODE_SINT_0_REG_SINT_TOP_CTX_RD_OFFSET_SHIFT 0 /*************************************************************************** *REG_SINT_VC1_TABSEL - REG_SINT_VC1_TABSEL ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: reserved0 [31:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_reserved0_MASK 0xff000000 #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_reserved0_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: ESC_LVL_SZ [23:23] */ #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_ESC_LVL_SZ_MASK 0x00800000 #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_ESC_LVL_SZ_SHIFT 23 /* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: TTYPE [22:21] */ #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_TTYPE_MASK 0x00600000 #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_TTYPE_SHIFT 21 /* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: INTER_AC [20:19] */ #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_INTER_AC_MASK 0x00180000 #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_INTER_AC_SHIFT 19 /* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: Y_INTRA_AC [18:17] */ #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_Y_INTRA_AC_MASK 0x00060000 #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_Y_INTRA_AC_SHIFT 17 /* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: DCTABLE [16:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_DCTABLE_MASK 0x00010000 #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_DCTABLE_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: reserved_for_eco1 [15:15] */ #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_reserved_for_eco1_MASK 0x00008000 #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_reserved_for_eco1_SHIFT 15 /* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: MBMODE [14:12] */ #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_MBMODE_MASK 0x00007000 #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_MBMODE_SHIFT 12 /* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: field_2REF [11:11] */ #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_field_2REF_MASK 0x00000800 #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_field_2REF_SHIFT 11 /* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: reserved_for_eco2 [10:07] */ #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_reserved_for_eco2_MASK 0x00000780 #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_reserved_for_eco2_SHIFT 7 /* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: CPPCY [06:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_CPPCY_MASK 0x00000070 #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_CPPCY_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: field_2MB_PAT [03:02] */ #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_field_2MB_PAT_MASK 0x0000000c #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_field_2MB_PAT_SHIFT 2 /* DECODE_SINT_0 :: REG_SINT_VC1_TABSEL :: field_4MB_PAT [01:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_field_4MB_PAT_MASK 0x00000003 #define BCHP_DECODE_SINT_0_REG_SINT_VC1_TABSEL_field_4MB_PAT_SHIFT 0 /*************************************************************************** *REG_SINT_CNST_INTRA - REG_SINT_CNST_INTRA ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_CNST_INTRA :: reserved0 [31:04] */ #define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_reserved0_MASK 0xfffffff0 #define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_reserved0_SHIFT 4 /* DECODE_SINT_0 :: REG_SINT_CNST_INTRA :: ULftAvail [03:03] */ #define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_ULftAvail_MASK 0x00000008 #define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_ULftAvail_SHIFT 3 /* DECODE_SINT_0 :: REG_SINT_CNST_INTRA :: TopAvail [02:02] */ #define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_TopAvail_MASK 0x00000004 #define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_TopAvail_SHIFT 2 /* DECODE_SINT_0 :: REG_SINT_CNST_INTRA :: LeftAvail [01:01] */ #define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_LeftAvail_MASK 0x00000002 #define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_LeftAvail_SHIFT 1 /* DECODE_SINT_0 :: REG_SINT_CNST_INTRA :: URtAvail [00:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_URtAvail_MASK 0x00000001 #define BCHP_DECODE_SINT_0_REG_SINT_CNST_INTRA_URtAvail_SHIFT 0 /*************************************************************************** *REG_SINT_OPIC_MEM_BASE - Outpic Lookup ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_OPIC_MEM_BASE :: OutPic3 [31:24] */ #define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic3_MASK 0xff000000 #define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic3_SHIFT 24 /* DECODE_SINT_0 :: REG_SINT_OPIC_MEM_BASE :: OutPic2 [23:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic2_MASK 0x00ff0000 #define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic2_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_OPIC_MEM_BASE :: OutPic1 [15:08] */ #define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic1_MASK 0x0000ff00 #define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic1_SHIFT 8 /* DECODE_SINT_0 :: REG_SINT_OPIC_MEM_BASE :: OutPic0 [07:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic0_MASK 0x000000ff #define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_BASE_OutPic0_SHIFT 0 /*************************************************************************** *REG_SINT_OPIC_MEM_END - REG_SINT_OPIC_MEM_END ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_OPIC_MEM_END :: reserved0 [31:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_SINT_0_REG_SINT_OPIC_MEM_END_reserved0_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_MEM_BASE - Vector Memory ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_MEM_BASE :: Vector_Y_Delta [31:16] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_BASE_Vector_Y_Delta_MASK 0xffff0000 #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_BASE_Vector_Y_Delta_SHIFT 16 /* DECODE_SINT_0 :: REG_SINT_VEC_MEM_BASE :: Vector_X_Delta [15:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_BASE_Vector_X_Delta_MASK 0x0000ffff #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_BASE_Vector_X_Delta_SHIFT 0 /*************************************************************************** *REG_SINT_VEC_MEM_END - REG_SINT_VEC_MEM_END ***************************************************************************/ /* DECODE_SINT_0 :: REG_SINT_VEC_MEM_END :: reserved0 [31:00] */ #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_SINT_0_REG_SINT_VEC_MEM_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_SINT_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015600000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pcroffset.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pc0000644000175000017500000163436311610313111031053 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_xpt_pcroffset.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:25p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:05 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pcroffset.h $ * * Hydra_Software_Devel/1 7/17/09 8:25p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_XPT_PCROFFSET_H__ #define BCHP_XPT_PCROFFSET_H__ /*************************************************************************** *XPT_PCROFFSET - XPT PCROFFSET Control Registers ***************************************************************************/ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS 0x00227000 /* PCR INTERRUPT STATUS register for Contexts 3 to 0 */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_ENABLE 0x00227004 /* PCR INTERRUPT ENABLE register for Contexts 3 to 0 */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS 0x00227008 /* PCR INTERRUPT STATUS register for Contexts 7 to 4 */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_ENABLE 0x0022700c /* PCR INTERRUPT ENABLE register for Contexts 7 to 4 */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS 0x00227010 /* PCR INTERRUPT STATUS register for Contexts 11 to 8 */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_ENABLE 0x00227014 /* PCR INTERRUPT ENABLE register for Contexts 11 to 8 */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS 0x00227018 /* PCR INTERRUPT STATUS register for Contexts 15 to 12 */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_ENABLE 0x0022701c /* PCR INTERRUPT ENABLE register for Contexts 15 to 12 */ #define BCHP_XPT_PCROFFSET_STC0_CTRL 0x00227020 /* STC0 Counter Control */ #define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL 0x00227024 /* STC0 Timebase Select */ #define BCHP_XPT_PCROFFSET_STC0_RATE_CTRL 0x00227028 /* STC0 Counter Increment and Prescale */ #define BCHP_XPT_PCROFFSET_STC0_CAPTURE_PCR_ONCE 0x0022702c /* STC0 Capture PCR once */ #define BCHP_XPT_PCROFFSET_STC0 0x00227030 /* STC0 Counter */ #define BCHP_XPT_PCROFFSET_STC1_CTRL 0x00227034 /* STC1 Counter Control */ #define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL 0x00227038 /* STC1 Timebase Select */ #define BCHP_XPT_PCROFFSET_STC1_RATE_CTRL 0x0022703c /* STC1 Counter Increment and Prescale */ #define BCHP_XPT_PCROFFSET_STC1_CAPTURE_PCR_ONCE 0x00227040 /* STC1 Capture PCR once */ #define BCHP_XPT_PCROFFSET_STC1 0x00227044 /* STC1 Counter */ #define BCHP_XPT_PCROFFSET_STC2_CTRL 0x00227048 /* STC2 Counter Control */ #define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL 0x0022704c /* STC2 Timebase Select */ #define BCHP_XPT_PCROFFSET_STC2_RATE_CTRL 0x00227050 /* STC2 Counter Increment and Prescale */ #define BCHP_XPT_PCROFFSET_STC2_CAPTURE_PCR_ONCE 0x00227054 /* STC2 Capture PCR once */ #define BCHP_XPT_PCROFFSET_STC2 0x00227058 /* STC2 Counter */ #define BCHP_XPT_PCROFFSET_STC3_CTRL 0x0022705c /* STC3 Counter Control */ #define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL 0x00227060 /* STC3 Timebase Select */ #define BCHP_XPT_PCROFFSET_STC3_RATE_CTRL 0x00227064 /* STC3 Counter Increment and Prescale */ #define BCHP_XPT_PCROFFSET_STC3_CAPTURE_PCR_ONCE 0x00227068 /* STC3 Capture PCR once */ #define BCHP_XPT_PCROFFSET_STC3 0x0022706c /* STC3 Counter */ #define BCHP_XPT_PCROFFSET_TM_PCROFFSET_CONFIG_TABLE 0x00227070 /* TM Control */ #define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL 0x00227074 /* STC Broadcast bus select */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL 0x00227800 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_PID_CH_NUM 0x00227804 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATE 0x00227808 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATUS 0x0022780c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_RD_PTR 0x00227810 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_WR_PTR 0x00227814 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1 0x00227818 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3 0x0022781c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5 0x00227820 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7 0x00227824 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATE 0x00227828 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET 0x0022782c /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_VALID 0x00227830 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_MAX_ERROR 0x00227834 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_THRESHOLD 0x00227838 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT0_FIXED_OFFSET 0x0022783c /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_COUNT 0x00227840 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_SEND_PCR_BASE 0x00227844 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_LAST_PCR_BASE 0x00227848 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_0 0x0022784c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_1 0x00227850 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_2 0x00227854 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_3 0x00227858 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_0 0x0022786c /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_1 0x00227870 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_2 0x00227874 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_3 0x00227878 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_4 0x0022787c /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL 0x00227880 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_PID_CH_NUM 0x00227884 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATE 0x00227888 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATUS 0x0022788c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_RD_PTR 0x00227890 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_WR_PTR 0x00227894 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1 0x00227898 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3 0x0022789c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5 0x002278a0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7 0x002278a4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATE 0x002278a8 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET 0x002278ac /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_VALID 0x002278b0 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_MAX_ERROR 0x002278b4 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_THRESHOLD 0x002278b8 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT1_FIXED_OFFSET 0x002278bc /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_COUNT 0x002278c0 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_SEND_PCR_BASE 0x002278c4 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_LAST_PCR_BASE 0x002278c8 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_0 0x002278cc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_1 0x002278d0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_2 0x002278d4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_3 0x002278d8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_0 0x002278ec /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_1 0x002278f0 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_2 0x002278f4 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_3 0x002278f8 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_4 0x002278fc /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL 0x00227900 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_PID_CH_NUM 0x00227904 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATE 0x00227908 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATUS 0x0022790c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_RD_PTR 0x00227910 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_WR_PTR 0x00227914 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1 0x00227918 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3 0x0022791c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5 0x00227920 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7 0x00227924 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATE 0x00227928 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET 0x0022792c /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_VALID 0x00227930 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_MAX_ERROR 0x00227934 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_THRESHOLD 0x00227938 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT2_FIXED_OFFSET 0x0022793c /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_COUNT 0x00227940 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_SEND_PCR_BASE 0x00227944 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_LAST_PCR_BASE 0x00227948 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_0 0x0022794c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_1 0x00227950 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_2 0x00227954 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_3 0x00227958 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_0 0x0022796c /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_1 0x00227970 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_2 0x00227974 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_3 0x00227978 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_4 0x0022797c /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL 0x00227980 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_PID_CH_NUM 0x00227984 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATE 0x00227988 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATUS 0x0022798c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_RD_PTR 0x00227990 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_WR_PTR 0x00227994 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1 0x00227998 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3 0x0022799c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5 0x002279a0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7 0x002279a4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATE 0x002279a8 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET 0x002279ac /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_VALID 0x002279b0 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_MAX_ERROR 0x002279b4 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_THRESHOLD 0x002279b8 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT3_FIXED_OFFSET 0x002279bc /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_COUNT 0x002279c0 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_SEND_PCR_BASE 0x002279c4 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_LAST_PCR_BASE 0x002279c8 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_0 0x002279cc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_1 0x002279d0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_2 0x002279d4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_3 0x002279d8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_0 0x002279ec /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_1 0x002279f0 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_2 0x002279f4 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_3 0x002279f8 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_4 0x002279fc /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL 0x00227a00 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_PID_CH_NUM 0x00227a04 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATE 0x00227a08 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATUS 0x00227a0c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_RD_PTR 0x00227a10 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_WR_PTR 0x00227a14 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1 0x00227a18 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3 0x00227a1c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5 0x00227a20 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7 0x00227a24 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATE 0x00227a28 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET 0x00227a2c /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_VALID 0x00227a30 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_MAX_ERROR 0x00227a34 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_THRESHOLD 0x00227a38 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT4_FIXED_OFFSET 0x00227a3c /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_COUNT 0x00227a40 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_SEND_PCR_BASE 0x00227a44 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_LAST_PCR_BASE 0x00227a48 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_0 0x00227a4c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_1 0x00227a50 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_2 0x00227a54 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_3 0x00227a58 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_0 0x00227a6c /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_1 0x00227a70 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_2 0x00227a74 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_3 0x00227a78 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_4 0x00227a7c /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL 0x00227a80 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_PID_CH_NUM 0x00227a84 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATE 0x00227a88 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATUS 0x00227a8c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_RD_PTR 0x00227a90 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_WR_PTR 0x00227a94 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1 0x00227a98 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3 0x00227a9c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5 0x00227aa0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7 0x00227aa4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATE 0x00227aa8 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET 0x00227aac /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_VALID 0x00227ab0 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_MAX_ERROR 0x00227ab4 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_THRESHOLD 0x00227ab8 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT5_FIXED_OFFSET 0x00227abc /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_COUNT 0x00227ac0 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_SEND_PCR_BASE 0x00227ac4 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_LAST_PCR_BASE 0x00227ac8 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_0 0x00227acc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_1 0x00227ad0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_2 0x00227ad4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_3 0x00227ad8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_0 0x00227aec /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_1 0x00227af0 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_2 0x00227af4 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_3 0x00227af8 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_4 0x00227afc /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL 0x00227b00 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_PID_CH_NUM 0x00227b04 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATE 0x00227b08 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATUS 0x00227b0c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_RD_PTR 0x00227b10 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_WR_PTR 0x00227b14 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1 0x00227b18 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3 0x00227b1c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5 0x00227b20 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7 0x00227b24 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATE 0x00227b28 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET 0x00227b2c /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_VALID 0x00227b30 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_MAX_ERROR 0x00227b34 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_THRESHOLD 0x00227b38 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT6_FIXED_OFFSET 0x00227b3c /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_COUNT 0x00227b40 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_SEND_PCR_BASE 0x00227b44 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_LAST_PCR_BASE 0x00227b48 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_0 0x00227b4c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_1 0x00227b50 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_2 0x00227b54 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_3 0x00227b58 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_0 0x00227b6c /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_1 0x00227b70 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_2 0x00227b74 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_3 0x00227b78 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_4 0x00227b7c /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL 0x00227b80 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_PID_CH_NUM 0x00227b84 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATE 0x00227b88 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATUS 0x00227b8c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_RD_PTR 0x00227b90 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_WR_PTR 0x00227b94 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1 0x00227b98 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3 0x00227b9c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5 0x00227ba0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7 0x00227ba4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATE 0x00227ba8 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET 0x00227bac /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_VALID 0x00227bb0 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_MAX_ERROR 0x00227bb4 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_THRESHOLD 0x00227bb8 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT7_FIXED_OFFSET 0x00227bbc /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_COUNT 0x00227bc0 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_SEND_PCR_BASE 0x00227bc4 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_LAST_PCR_BASE 0x00227bc8 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_0 0x00227bcc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_1 0x00227bd0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_2 0x00227bd4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_3 0x00227bd8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_0 0x00227bec /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_1 0x00227bf0 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_2 0x00227bf4 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_3 0x00227bf8 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_4 0x00227bfc /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL 0x00227c00 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_PID_CH_NUM 0x00227c04 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATE 0x00227c08 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATUS 0x00227c0c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_RD_PTR 0x00227c10 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_WR_PTR 0x00227c14 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1 0x00227c18 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3 0x00227c1c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5 0x00227c20 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7 0x00227c24 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATE 0x00227c28 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET 0x00227c2c /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_VALID 0x00227c30 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_MAX_ERROR 0x00227c34 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_THRESHOLD 0x00227c38 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT8_FIXED_OFFSET 0x00227c3c /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_COUNT 0x00227c40 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_SEND_PCR_BASE 0x00227c44 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_LAST_PCR_BASE 0x00227c48 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_0 0x00227c4c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_1 0x00227c50 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_2 0x00227c54 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_3 0x00227c58 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_0 0x00227c6c /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_1 0x00227c70 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_2 0x00227c74 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_3 0x00227c78 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_4 0x00227c7c /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL 0x00227c80 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_PID_CH_NUM 0x00227c84 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATE 0x00227c88 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATUS 0x00227c8c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_RD_PTR 0x00227c90 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_WR_PTR 0x00227c94 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1 0x00227c98 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3 0x00227c9c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5 0x00227ca0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7 0x00227ca4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATE 0x00227ca8 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET 0x00227cac /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_VALID 0x00227cb0 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_MAX_ERROR 0x00227cb4 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_THRESHOLD 0x00227cb8 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT9_FIXED_OFFSET 0x00227cbc /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_COUNT 0x00227cc0 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_SEND_PCR_BASE 0x00227cc4 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_LAST_PCR_BASE 0x00227cc8 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_0 0x00227ccc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_1 0x00227cd0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_2 0x00227cd4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_3 0x00227cd8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_0 0x00227cec /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_1 0x00227cf0 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_2 0x00227cf4 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_3 0x00227cf8 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_4 0x00227cfc /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL 0x00227d00 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_PID_CH_NUM 0x00227d04 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATE 0x00227d08 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATUS 0x00227d0c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_RD_PTR 0x00227d10 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_WR_PTR 0x00227d14 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1 0x00227d18 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3 0x00227d1c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5 0x00227d20 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7 0x00227d24 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATE 0x00227d28 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET 0x00227d2c /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_VALID 0x00227d30 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_MAX_ERROR 0x00227d34 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_THRESHOLD 0x00227d38 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT10_FIXED_OFFSET 0x00227d3c /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_COUNT 0x00227d40 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_SEND_PCR_BASE 0x00227d44 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_LAST_PCR_BASE 0x00227d48 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_0 0x00227d4c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_1 0x00227d50 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_2 0x00227d54 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_3 0x00227d58 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_0 0x00227d6c /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_1 0x00227d70 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_2 0x00227d74 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_3 0x00227d78 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_4 0x00227d7c /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL 0x00227d80 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_PID_CH_NUM 0x00227d84 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATE 0x00227d88 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATUS 0x00227d8c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_RD_PTR 0x00227d90 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_WR_PTR 0x00227d94 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1 0x00227d98 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3 0x00227d9c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5 0x00227da0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7 0x00227da4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATE 0x00227da8 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET 0x00227dac /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_VALID 0x00227db0 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_MAX_ERROR 0x00227db4 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_THRESHOLD 0x00227db8 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT11_FIXED_OFFSET 0x00227dbc /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_COUNT 0x00227dc0 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_SEND_PCR_BASE 0x00227dc4 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_LAST_PCR_BASE 0x00227dc8 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_0 0x00227dcc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_1 0x00227dd0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_2 0x00227dd4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_3 0x00227dd8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_0 0x00227dec /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_1 0x00227df0 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_2 0x00227df4 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_3 0x00227df8 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_4 0x00227dfc /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL 0x00227e00 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_PID_CH_NUM 0x00227e04 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATE 0x00227e08 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATUS 0x00227e0c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_RD_PTR 0x00227e10 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_WR_PTR 0x00227e14 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1 0x00227e18 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3 0x00227e1c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5 0x00227e20 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7 0x00227e24 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATE 0x00227e28 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET 0x00227e2c /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_VALID 0x00227e30 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_MAX_ERROR 0x00227e34 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_THRESHOLD 0x00227e38 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT12_FIXED_OFFSET 0x00227e3c /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_COUNT 0x00227e40 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_SEND_PCR_BASE 0x00227e44 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_LAST_PCR_BASE 0x00227e48 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_0 0x00227e4c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_1 0x00227e50 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_2 0x00227e54 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_3 0x00227e58 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_0 0x00227e6c /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_1 0x00227e70 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_2 0x00227e74 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_3 0x00227e78 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_4 0x00227e7c /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL 0x00227e80 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_PID_CH_NUM 0x00227e84 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATE 0x00227e88 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATUS 0x00227e8c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_RD_PTR 0x00227e90 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_WR_PTR 0x00227e94 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1 0x00227e98 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3 0x00227e9c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5 0x00227ea0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7 0x00227ea4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATE 0x00227ea8 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET 0x00227eac /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_VALID 0x00227eb0 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_MAX_ERROR 0x00227eb4 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_THRESHOLD 0x00227eb8 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT13_FIXED_OFFSET 0x00227ebc /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_COUNT 0x00227ec0 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_SEND_PCR_BASE 0x00227ec4 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_LAST_PCR_BASE 0x00227ec8 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_0 0x00227ecc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_1 0x00227ed0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_2 0x00227ed4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_3 0x00227ed8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_0 0x00227eec /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_1 0x00227ef0 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_2 0x00227ef4 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_3 0x00227ef8 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_4 0x00227efc /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL 0x00227f00 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_PID_CH_NUM 0x00227f04 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATE 0x00227f08 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATUS 0x00227f0c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_RD_PTR 0x00227f10 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_WR_PTR 0x00227f14 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1 0x00227f18 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3 0x00227f1c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5 0x00227f20 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7 0x00227f24 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATE 0x00227f28 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET 0x00227f2c /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_VALID 0x00227f30 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_MAX_ERROR 0x00227f34 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_THRESHOLD 0x00227f38 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT14_FIXED_OFFSET 0x00227f3c /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_COUNT 0x00227f40 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_SEND_PCR_BASE 0x00227f44 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_LAST_PCR_BASE 0x00227f48 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_0 0x00227f4c /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_1 0x00227f50 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_2 0x00227f54 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_3 0x00227f58 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_0 0x00227f6c /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_1 0x00227f70 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_2 0x00227f74 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_3 0x00227f78 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_4 0x00227f7c /* Config Word 31 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL 0x00227f80 /* Config word 0 - PCROFFSET Main Control */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_PID_CH_NUM 0x00227f84 /* Config Word 1 - PP_PCR_PID_CH_NUM Register */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATE 0x00227f88 /* Config Word 2 - SPLICE STATE Register */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATUS 0x00227f8c /* Config Word 3 - SPLICE STATUS Register */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_RD_PTR 0x00227f90 /* Config Word 4 - SPLICE PID Channel Read Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_WR_PTR 0x00227f94 /* Config Word 5 - SPLICE PID Channel Write Pointer */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1 0x00227f98 /* Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3 0x00227f9c /* Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5 0x00227fa0 /* Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7 0x00227fa4 /* Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATE 0x00227fa8 /* Config Word 10 - OFFSET STATE register */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET 0x00227fac /* Config Word 11 - OFFSET read/write */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_VALID 0x00227fb0 /* Config Word 12 - OFFSET Valid */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_MAX_ERROR 0x00227fb4 /* Config Word 13 - OFFSET MAX Error */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_THRESHOLD 0x00227fb8 /* Config Word 14 - OFFSET Threshold */ #define BCHP_XPT_PCROFFSET_CONTEXT15_FIXED_OFFSET 0x00227fbc /* Config Word 15 - Fixed OFFSET */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_COUNT 0x00227fc0 /* Config Word 16 - PCR COUNT register */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_SEND_PCR_BASE 0x00227fc4 /* Config Word 17 - Send PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_LAST_PCR_BASE 0x00227fc8 /* Config Word 18 - Last PCR Base Register */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_0 0x00227fcc /* Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_1 0x00227fd0 /* Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_2 0x00227fd4 /* Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_3 0x00227fd8 /* Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 */ #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_0 0x00227fec /* Config Word 27 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_1 0x00227ff0 /* Config Word 28 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_2 0x00227ff4 /* Config Word 29 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_3 0x00227ff8 /* Config Word 30 - RESERVED */ #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_4 0x00227ffc /* Config Word 31 - RESERVED */ /*************************************************************************** *INTERRUPT0_STATUS - PCR INTERRUPT STATUS register for Contexts 3 to 0 ***************************************************************************/ /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco0_SHIFT 31 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT3_STC_CAPTURED [30:30] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_STC_CAPTURED_MASK 0x40000000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_STC_CAPTURED_SHIFT 30 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT3_SPLICE_ERROR [29:29] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_SPLICE_ERROR_MASK 0x20000000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_SPLICE_ERROR_SHIFT 29 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT3_SPLICE_DONE [28:28] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_SPLICE_DONE_MASK 0x10000000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_SPLICE_DONE_SHIFT 28 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT3_PCR_TWO_ERROR [27:27] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_TWO_ERROR_MASK 0x08000000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_TWO_ERROR_SHIFT 27 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT3_PCR_ONE_ERROR [26:26] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_ONE_ERROR_MASK 0x04000000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_ONE_ERROR_SHIFT 26 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT3_PCR_DISCONT [25:25] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_DISCONT_MASK 0x02000000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_DISCONT_SHIFT 25 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT3_PCR_NEW [24:24] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_NEW_MASK 0x01000000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT3_PCR_NEW_SHIFT 24 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: reserved_for_eco1 [23:23] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco1_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco1_SHIFT 23 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT2_STC_CAPTURED [22:22] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_STC_CAPTURED_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_STC_CAPTURED_SHIFT 22 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT2_SPLICE_ERROR [21:21] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_SPLICE_ERROR_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_SPLICE_ERROR_SHIFT 21 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT2_SPLICE_DONE [20:20] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_SPLICE_DONE_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_SPLICE_DONE_SHIFT 20 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT2_PCR_TWO_ERROR [19:19] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_TWO_ERROR_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_TWO_ERROR_SHIFT 19 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT2_PCR_ONE_ERROR [18:18] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_ONE_ERROR_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_ONE_ERROR_SHIFT 18 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT2_PCR_DISCONT [17:17] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_DISCONT_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_DISCONT_SHIFT 17 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT2_PCR_NEW [16:16] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_NEW_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT2_PCR_NEW_SHIFT 16 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: reserved_for_eco2 [15:15] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco2_MASK 0x00008000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco2_SHIFT 15 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT1_STC_CAPTURED [14:14] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_STC_CAPTURED_MASK 0x00004000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_STC_CAPTURED_SHIFT 14 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT1_SPLICE_ERROR [13:13] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_SPLICE_ERROR_MASK 0x00002000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_SPLICE_ERROR_SHIFT 13 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT1_SPLICE_DONE [12:12] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_SPLICE_DONE_MASK 0x00001000 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_SPLICE_DONE_SHIFT 12 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT1_PCR_TWO_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_TWO_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_TWO_ERROR_SHIFT 11 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT1_PCR_ONE_ERROR [10:10] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_ONE_ERROR_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_ONE_ERROR_SHIFT 10 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT1_PCR_DISCONT [09:09] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_DISCONT_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_DISCONT_SHIFT 9 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT1_PCR_NEW [08:08] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_NEW_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT1_PCR_NEW_SHIFT 8 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: reserved_for_eco3 [07:07] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco3_MASK 0x00000080 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_reserved_for_eco3_SHIFT 7 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT0_STC_CAPTURED [06:06] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_STC_CAPTURED_MASK 0x00000040 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_STC_CAPTURED_SHIFT 6 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT0_SPLICE_ERROR [05:05] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_SPLICE_ERROR_MASK 0x00000020 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_SPLICE_ERROR_SHIFT 5 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT0_SPLICE_DONE [04:04] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_SPLICE_DONE_MASK 0x00000010 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_SPLICE_DONE_SHIFT 4 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT0_PCR_TWO_ERROR [03:03] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_TWO_ERROR_MASK 0x00000008 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_TWO_ERROR_SHIFT 3 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT0_PCR_ONE_ERROR [02:02] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_ONE_ERROR_MASK 0x00000004 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_ONE_ERROR_SHIFT 2 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT0_PCR_DISCONT [01:01] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_DISCONT_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_DISCONT_SHIFT 1 /* XPT_PCROFFSET :: INTERRUPT0_STATUS :: CONTEXT0_PCR_NEW [00:00] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_NEW_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_INTERRUPT0_STATUS_CONTEXT0_PCR_NEW_SHIFT 0 /*************************************************************************** *INTERRUPT0_ENABLE - PCR INTERRUPT ENABLE register for Contexts 3 to 0 ***************************************************************************/ /* XPT_PCROFFSET :: INTERRUPT0_ENABLE :: INTR0_STATUS_REG_EN [31:00] */ #define BCHP_XPT_PCROFFSET_INTERRUPT0_ENABLE_INTR0_STATUS_REG_EN_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_INTERRUPT0_ENABLE_INTR0_STATUS_REG_EN_SHIFT 0 /*************************************************************************** *INTERRUPT1_STATUS - PCR INTERRUPT STATUS register for Contexts 7 to 4 ***************************************************************************/ /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco0_SHIFT 31 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT7_STC_CAPTURED [30:30] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_STC_CAPTURED_MASK 0x40000000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_STC_CAPTURED_SHIFT 30 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT7_SPLICE_ERROR [29:29] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_SPLICE_ERROR_MASK 0x20000000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_SPLICE_ERROR_SHIFT 29 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT7_SPLICE_DONE [28:28] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_SPLICE_DONE_MASK 0x10000000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_SPLICE_DONE_SHIFT 28 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT7_PCR_TWO_ERROR [27:27] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_TWO_ERROR_MASK 0x08000000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_TWO_ERROR_SHIFT 27 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT7_PCR_ONE_ERROR [26:26] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_ONE_ERROR_MASK 0x04000000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_ONE_ERROR_SHIFT 26 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT7_PCR_DISCONT [25:25] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_DISCONT_MASK 0x02000000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_DISCONT_SHIFT 25 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT7_PCR_NEW [24:24] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_NEW_MASK 0x01000000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT7_PCR_NEW_SHIFT 24 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: reserved_for_eco1 [23:23] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco1_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco1_SHIFT 23 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT6_STC_CAPTURED [22:22] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_STC_CAPTURED_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_STC_CAPTURED_SHIFT 22 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT6_SPLICE_ERROR [21:21] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_SPLICE_ERROR_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_SPLICE_ERROR_SHIFT 21 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT6_SPLICE_DONE [20:20] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_SPLICE_DONE_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_SPLICE_DONE_SHIFT 20 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT6_PCR_TWO_ERROR [19:19] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_TWO_ERROR_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_TWO_ERROR_SHIFT 19 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT6_PCR_ONE_ERROR [18:18] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_ONE_ERROR_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_ONE_ERROR_SHIFT 18 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT6_PCR_DISCONT [17:17] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_DISCONT_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_DISCONT_SHIFT 17 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT6_PCR_NEW [16:16] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_NEW_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT6_PCR_NEW_SHIFT 16 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: reserved_for_eco2 [15:15] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco2_MASK 0x00008000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco2_SHIFT 15 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT5_STC_CAPTURED [14:14] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_STC_CAPTURED_MASK 0x00004000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_STC_CAPTURED_SHIFT 14 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT5_SPLICE_ERROR [13:13] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_SPLICE_ERROR_MASK 0x00002000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_SPLICE_ERROR_SHIFT 13 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT5_SPLICE_DONE [12:12] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_SPLICE_DONE_MASK 0x00001000 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_SPLICE_DONE_SHIFT 12 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT5_PCR_TWO_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_TWO_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_TWO_ERROR_SHIFT 11 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT5_PCR_ONE_ERROR [10:10] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_ONE_ERROR_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_ONE_ERROR_SHIFT 10 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT5_PCR_DISCONT [09:09] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_DISCONT_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_DISCONT_SHIFT 9 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT5_PCR_NEW [08:08] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_NEW_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT5_PCR_NEW_SHIFT 8 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: reserved_for_eco3 [07:07] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco3_MASK 0x00000080 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_reserved_for_eco3_SHIFT 7 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT4_STC_CAPTURED [06:06] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_STC_CAPTURED_MASK 0x00000040 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_STC_CAPTURED_SHIFT 6 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT4_SPLICE_ERROR [05:05] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_SPLICE_ERROR_MASK 0x00000020 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_SPLICE_ERROR_SHIFT 5 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT4_SPLICE_DONE [04:04] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_SPLICE_DONE_MASK 0x00000010 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_SPLICE_DONE_SHIFT 4 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT4_PCR_TWO_ERROR [03:03] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_TWO_ERROR_MASK 0x00000008 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_TWO_ERROR_SHIFT 3 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT4_PCR_ONE_ERROR [02:02] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_ONE_ERROR_MASK 0x00000004 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_ONE_ERROR_SHIFT 2 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT4_PCR_DISCONT [01:01] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_DISCONT_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_DISCONT_SHIFT 1 /* XPT_PCROFFSET :: INTERRUPT1_STATUS :: CONTEXT4_PCR_NEW [00:00] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_NEW_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_INTERRUPT1_STATUS_CONTEXT4_PCR_NEW_SHIFT 0 /*************************************************************************** *INTERRUPT1_ENABLE - PCR INTERRUPT ENABLE register for Contexts 7 to 4 ***************************************************************************/ /* XPT_PCROFFSET :: INTERRUPT1_ENABLE :: INTR0_STATUS_REG_EN [31:00] */ #define BCHP_XPT_PCROFFSET_INTERRUPT1_ENABLE_INTR0_STATUS_REG_EN_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_INTERRUPT1_ENABLE_INTR0_STATUS_REG_EN_SHIFT 0 /*************************************************************************** *INTERRUPT2_STATUS - PCR INTERRUPT STATUS register for Contexts 11 to 8 ***************************************************************************/ /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco0_SHIFT 31 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT11_STC_CAPTURED [30:30] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_STC_CAPTURED_MASK 0x40000000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_STC_CAPTURED_SHIFT 30 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT11_SPLICE_ERROR [29:29] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_SPLICE_ERROR_MASK 0x20000000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_SPLICE_ERROR_SHIFT 29 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT11_SPLICE_DONE [28:28] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_SPLICE_DONE_MASK 0x10000000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_SPLICE_DONE_SHIFT 28 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT11_PCR_TWO_ERROR [27:27] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_TWO_ERROR_MASK 0x08000000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_TWO_ERROR_SHIFT 27 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT11_PCR_ONE_ERROR [26:26] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_ONE_ERROR_MASK 0x04000000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_ONE_ERROR_SHIFT 26 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT11_PCR_DISCONT [25:25] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_DISCONT_MASK 0x02000000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_DISCONT_SHIFT 25 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT11_PCR_NEW [24:24] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_NEW_MASK 0x01000000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT11_PCR_NEW_SHIFT 24 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: reserved_for_eco1 [23:23] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco1_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco1_SHIFT 23 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT10_STC_CAPTURED [22:22] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_STC_CAPTURED_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_STC_CAPTURED_SHIFT 22 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT10_SPLICE_ERROR [21:21] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_SPLICE_ERROR_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_SPLICE_ERROR_SHIFT 21 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT10_SPLICE_DONE [20:20] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_SPLICE_DONE_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_SPLICE_DONE_SHIFT 20 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT10_PCR_TWO_ERROR [19:19] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_TWO_ERROR_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_TWO_ERROR_SHIFT 19 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT10_PCR_ONE_ERROR [18:18] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_ONE_ERROR_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_ONE_ERROR_SHIFT 18 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT10_PCR_DISCONT [17:17] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_DISCONT_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_DISCONT_SHIFT 17 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT10_PCR_NEW [16:16] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_NEW_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT10_PCR_NEW_SHIFT 16 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: reserved_for_eco2 [15:15] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco2_MASK 0x00008000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco2_SHIFT 15 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT9_STC_CAPTURED [14:14] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_STC_CAPTURED_MASK 0x00004000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_STC_CAPTURED_SHIFT 14 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT9_SPLICE_ERROR [13:13] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_SPLICE_ERROR_MASK 0x00002000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_SPLICE_ERROR_SHIFT 13 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT9_SPLICE_DONE [12:12] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_SPLICE_DONE_MASK 0x00001000 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_SPLICE_DONE_SHIFT 12 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT9_PCR_TWO_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_TWO_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_TWO_ERROR_SHIFT 11 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT9_PCR_ONE_ERROR [10:10] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_ONE_ERROR_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_ONE_ERROR_SHIFT 10 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT9_PCR_DISCONT [09:09] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_DISCONT_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_DISCONT_SHIFT 9 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT9_PCR_NEW [08:08] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_NEW_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT9_PCR_NEW_SHIFT 8 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: reserved_for_eco3 [07:07] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco3_MASK 0x00000080 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_reserved_for_eco3_SHIFT 7 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT8_STC_CAPTURED [06:06] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_STC_CAPTURED_MASK 0x00000040 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_STC_CAPTURED_SHIFT 6 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT8_SPLICE_ERROR [05:05] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_SPLICE_ERROR_MASK 0x00000020 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_SPLICE_ERROR_SHIFT 5 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT8_SPLICE_DONE [04:04] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_SPLICE_DONE_MASK 0x00000010 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_SPLICE_DONE_SHIFT 4 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT8_PCR_TWO_ERROR [03:03] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_TWO_ERROR_MASK 0x00000008 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_TWO_ERROR_SHIFT 3 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT8_PCR_ONE_ERROR [02:02] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_ONE_ERROR_MASK 0x00000004 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_ONE_ERROR_SHIFT 2 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT8_PCR_DISCONT [01:01] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_DISCONT_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_DISCONT_SHIFT 1 /* XPT_PCROFFSET :: INTERRUPT2_STATUS :: CONTEXT8_PCR_NEW [00:00] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_NEW_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_INTERRUPT2_STATUS_CONTEXT8_PCR_NEW_SHIFT 0 /*************************************************************************** *INTERRUPT2_ENABLE - PCR INTERRUPT ENABLE register for Contexts 11 to 8 ***************************************************************************/ /* XPT_PCROFFSET :: INTERRUPT2_ENABLE :: INTR0_STATUS_REG_EN [31:00] */ #define BCHP_XPT_PCROFFSET_INTERRUPT2_ENABLE_INTR0_STATUS_REG_EN_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_INTERRUPT2_ENABLE_INTR0_STATUS_REG_EN_SHIFT 0 /*************************************************************************** *INTERRUPT3_STATUS - PCR INTERRUPT STATUS register for Contexts 15 to 12 ***************************************************************************/ /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco0_SHIFT 31 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT15_STC_CAPTURED [30:30] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_STC_CAPTURED_MASK 0x40000000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_STC_CAPTURED_SHIFT 30 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT15_SPLICE_ERROR [29:29] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_SPLICE_ERROR_MASK 0x20000000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_SPLICE_ERROR_SHIFT 29 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT15_SPLICE_DONE [28:28] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_SPLICE_DONE_MASK 0x10000000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_SPLICE_DONE_SHIFT 28 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT15_PCR_TWO_ERROR [27:27] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_TWO_ERROR_MASK 0x08000000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_TWO_ERROR_SHIFT 27 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT15_PCR_ONE_ERROR [26:26] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_ONE_ERROR_MASK 0x04000000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_ONE_ERROR_SHIFT 26 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT15_PCR_DISCONT [25:25] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_DISCONT_MASK 0x02000000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_DISCONT_SHIFT 25 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT15_PCR_NEW [24:24] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_NEW_MASK 0x01000000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT15_PCR_NEW_SHIFT 24 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: reserved_for_eco1 [23:23] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco1_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco1_SHIFT 23 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT14_STC_CAPTURED [22:22] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_STC_CAPTURED_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_STC_CAPTURED_SHIFT 22 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT14_SPLICE_ERROR [21:21] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_SPLICE_ERROR_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_SPLICE_ERROR_SHIFT 21 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT14_SPLICE_DONE [20:20] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_SPLICE_DONE_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_SPLICE_DONE_SHIFT 20 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT14_PCR_TWO_ERROR [19:19] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_TWO_ERROR_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_TWO_ERROR_SHIFT 19 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT14_PCR_ONE_ERROR [18:18] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_ONE_ERROR_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_ONE_ERROR_SHIFT 18 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT14_PCR_DISCONT [17:17] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_DISCONT_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_DISCONT_SHIFT 17 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT14_PCR_NEW [16:16] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_NEW_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT14_PCR_NEW_SHIFT 16 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: reserved_for_eco2 [15:15] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco2_MASK 0x00008000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco2_SHIFT 15 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT13_STC_CAPTURED [14:14] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_STC_CAPTURED_MASK 0x00004000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_STC_CAPTURED_SHIFT 14 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT13_SPLICE_ERROR [13:13] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_SPLICE_ERROR_MASK 0x00002000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_SPLICE_ERROR_SHIFT 13 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT13_SPLICE_DONE [12:12] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_SPLICE_DONE_MASK 0x00001000 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_SPLICE_DONE_SHIFT 12 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT13_PCR_TWO_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_TWO_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_TWO_ERROR_SHIFT 11 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT13_PCR_ONE_ERROR [10:10] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_ONE_ERROR_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_ONE_ERROR_SHIFT 10 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT13_PCR_DISCONT [09:09] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_DISCONT_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_DISCONT_SHIFT 9 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT13_PCR_NEW [08:08] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_NEW_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT13_PCR_NEW_SHIFT 8 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: reserved_for_eco3 [07:07] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco3_MASK 0x00000080 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_reserved_for_eco3_SHIFT 7 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT12_STC_CAPTURED [06:06] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_STC_CAPTURED_MASK 0x00000040 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_STC_CAPTURED_SHIFT 6 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT12_SPLICE_ERROR [05:05] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_SPLICE_ERROR_MASK 0x00000020 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_SPLICE_ERROR_SHIFT 5 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT12_SPLICE_DONE [04:04] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_SPLICE_DONE_MASK 0x00000010 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_SPLICE_DONE_SHIFT 4 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT12_PCR_TWO_ERROR [03:03] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_TWO_ERROR_MASK 0x00000008 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_TWO_ERROR_SHIFT 3 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT12_PCR_ONE_ERROR [02:02] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_ONE_ERROR_MASK 0x00000004 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_ONE_ERROR_SHIFT 2 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT12_PCR_DISCONT [01:01] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_DISCONT_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_DISCONT_SHIFT 1 /* XPT_PCROFFSET :: INTERRUPT3_STATUS :: CONTEXT12_PCR_NEW [00:00] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_NEW_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_INTERRUPT3_STATUS_CONTEXT12_PCR_NEW_SHIFT 0 /*************************************************************************** *INTERRUPT3_ENABLE - PCR INTERRUPT ENABLE register for Contexts 15 to 12 ***************************************************************************/ /* XPT_PCROFFSET :: INTERRUPT3_ENABLE :: INTR0_STATUS_REG_EN [31:00] */ #define BCHP_XPT_PCROFFSET_INTERRUPT3_ENABLE_INTR0_STATUS_REG_EN_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_INTERRUPT3_ENABLE_INTR0_STATUS_REG_EN_SHIFT 0 /*************************************************************************** *STC0_CTRL - STC0 Counter Control ***************************************************************************/ /* XPT_PCROFFSET :: STC0_CTRL :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_STC0_CTRL_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_STC0_CTRL_reserved0_SHIFT 3 /* XPT_PCROFFSET :: STC0_CTRL :: MODE [02:02] */ #define BCHP_XPT_PCROFFSET_STC0_CTRL_MODE_MASK 0x00000004 #define BCHP_XPT_PCROFFSET_STC0_CTRL_MODE_SHIFT 2 #define BCHP_XPT_PCROFFSET_STC0_CTRL_MODE_BINARY 1 #define BCHP_XPT_PCROFFSET_STC0_CTRL_MODE_MOD_300 0 /* XPT_PCROFFSET :: STC0_CTRL :: FREEZE [01:01] */ #define BCHP_XPT_PCROFFSET_STC0_CTRL_FREEZE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_STC0_CTRL_FREEZE_SHIFT 1 #define BCHP_XPT_PCROFFSET_STC0_CTRL_FREEZE_STC_FREEZE 1 #define BCHP_XPT_PCROFFSET_STC0_CTRL_FREEZE_STC_NORMAL 0 /* XPT_PCROFFSET :: STC0_CTRL :: RESET [00:00] */ #define BCHP_XPT_PCROFFSET_STC0_CTRL_RESET_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_STC0_CTRL_RESET_SHIFT 0 #define BCHP_XPT_PCROFFSET_STC0_CTRL_RESET_STC_RESET 1 #define BCHP_XPT_PCROFFSET_STC0_CTRL_RESET_STC_NORMAL 0 /*************************************************************************** *STC0_TIMEBASE_SEL - STC0 Timebase Select ***************************************************************************/ /* XPT_PCROFFSET :: STC0_TIMEBASE_SEL :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_reserved0_SHIFT 3 /* XPT_PCROFFSET :: STC0_TIMEBASE_SEL :: TIMEBASE_SEL [02:00] */ #define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_TIMEBASE_SEL_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_TIMEBASE_SEL_SHIFT 0 #define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_0 0 #define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_1 1 #define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_2 2 #define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_3 3 #define BCHP_XPT_PCROFFSET_STC0_TIMEBASE_SEL_TIMEBASE_SEL_stc_free_run 4 /*************************************************************************** *STC0_RATE_CTRL - STC0 Counter Increment and Prescale ***************************************************************************/ /* XPT_PCROFFSET :: STC0_RATE_CTRL :: reserved0 [31:16] */ #define BCHP_XPT_PCROFFSET_STC0_RATE_CTRL_reserved0_MASK 0xffff0000 #define BCHP_XPT_PCROFFSET_STC0_RATE_CTRL_reserved0_SHIFT 16 /* XPT_PCROFFSET :: STC0_RATE_CTRL :: PRESCALE [15:08] */ #define BCHP_XPT_PCROFFSET_STC0_RATE_CTRL_PRESCALE_MASK 0x0000ff00 #define BCHP_XPT_PCROFFSET_STC0_RATE_CTRL_PRESCALE_SHIFT 8 /* XPT_PCROFFSET :: STC0_RATE_CTRL :: INCREMENT [07:00] */ #define BCHP_XPT_PCROFFSET_STC0_RATE_CTRL_INCREMENT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_STC0_RATE_CTRL_INCREMENT_SHIFT 0 /*************************************************************************** *STC0_CAPTURE_PCR_ONCE - STC0 Capture PCR once ***************************************************************************/ /* XPT_PCROFFSET :: STC0_CAPTURE_PCR_ONCE :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_STC0_CAPTURE_PCR_ONCE_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_STC0_CAPTURE_PCR_ONCE_reserved0_SHIFT 1 /* XPT_PCROFFSET :: STC0_CAPTURE_PCR_ONCE :: ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_STC0_CAPTURE_PCR_ONCE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_STC0_CAPTURE_PCR_ONCE_ENABLE_SHIFT 0 #define BCHP_XPT_PCROFFSET_STC0_CAPTURE_PCR_ONCE_ENABLE_ENABLE 1 #define BCHP_XPT_PCROFFSET_STC0_CAPTURE_PCR_ONCE_ENABLE_DISABLE 0 /*************************************************************************** *STC0 - STC0 Counter ***************************************************************************/ /* XPT_PCROFFSET :: STC0 :: COUNT [31:00] */ #define BCHP_XPT_PCROFFSET_STC0_COUNT_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_STC0_COUNT_SHIFT 0 /*************************************************************************** *STC1_CTRL - STC1 Counter Control ***************************************************************************/ /* XPT_PCROFFSET :: STC1_CTRL :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_STC1_CTRL_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_STC1_CTRL_reserved0_SHIFT 3 /* XPT_PCROFFSET :: STC1_CTRL :: MODE [02:02] */ #define BCHP_XPT_PCROFFSET_STC1_CTRL_MODE_MASK 0x00000004 #define BCHP_XPT_PCROFFSET_STC1_CTRL_MODE_SHIFT 2 #define BCHP_XPT_PCROFFSET_STC1_CTRL_MODE_BINARY 1 #define BCHP_XPT_PCROFFSET_STC1_CTRL_MODE_MOD_300 0 /* XPT_PCROFFSET :: STC1_CTRL :: FREEZE [01:01] */ #define BCHP_XPT_PCROFFSET_STC1_CTRL_FREEZE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_STC1_CTRL_FREEZE_SHIFT 1 #define BCHP_XPT_PCROFFSET_STC1_CTRL_FREEZE_STC_FREEZE 1 #define BCHP_XPT_PCROFFSET_STC1_CTRL_FREEZE_STC_NORMAL 0 /* XPT_PCROFFSET :: STC1_CTRL :: RESET [00:00] */ #define BCHP_XPT_PCROFFSET_STC1_CTRL_RESET_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_STC1_CTRL_RESET_SHIFT 0 #define BCHP_XPT_PCROFFSET_STC1_CTRL_RESET_STC_RESET 1 #define BCHP_XPT_PCROFFSET_STC1_CTRL_RESET_STC_NORMAL 0 /*************************************************************************** *STC1_TIMEBASE_SEL - STC1 Timebase Select ***************************************************************************/ /* XPT_PCROFFSET :: STC1_TIMEBASE_SEL :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_reserved0_SHIFT 3 /* XPT_PCROFFSET :: STC1_TIMEBASE_SEL :: TIMEBASE_SEL [02:00] */ #define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_TIMEBASE_SEL_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_TIMEBASE_SEL_SHIFT 0 #define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_0 0 #define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_1 1 #define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_2 2 #define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_3 3 #define BCHP_XPT_PCROFFSET_STC1_TIMEBASE_SEL_TIMEBASE_SEL_stc_free_run 4 /*************************************************************************** *STC1_RATE_CTRL - STC1 Counter Increment and Prescale ***************************************************************************/ /* XPT_PCROFFSET :: STC1_RATE_CTRL :: reserved0 [31:16] */ #define BCHP_XPT_PCROFFSET_STC1_RATE_CTRL_reserved0_MASK 0xffff0000 #define BCHP_XPT_PCROFFSET_STC1_RATE_CTRL_reserved0_SHIFT 16 /* XPT_PCROFFSET :: STC1_RATE_CTRL :: PRESCALE [15:08] */ #define BCHP_XPT_PCROFFSET_STC1_RATE_CTRL_PRESCALE_MASK 0x0000ff00 #define BCHP_XPT_PCROFFSET_STC1_RATE_CTRL_PRESCALE_SHIFT 8 /* XPT_PCROFFSET :: STC1_RATE_CTRL :: INCREMENT [07:00] */ #define BCHP_XPT_PCROFFSET_STC1_RATE_CTRL_INCREMENT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_STC1_RATE_CTRL_INCREMENT_SHIFT 0 /*************************************************************************** *STC1_CAPTURE_PCR_ONCE - STC1 Capture PCR once ***************************************************************************/ /* XPT_PCROFFSET :: STC1_CAPTURE_PCR_ONCE :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_STC1_CAPTURE_PCR_ONCE_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_STC1_CAPTURE_PCR_ONCE_reserved0_SHIFT 1 /* XPT_PCROFFSET :: STC1_CAPTURE_PCR_ONCE :: ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_STC1_CAPTURE_PCR_ONCE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_STC1_CAPTURE_PCR_ONCE_ENABLE_SHIFT 0 #define BCHP_XPT_PCROFFSET_STC1_CAPTURE_PCR_ONCE_ENABLE_ENABLE 1 #define BCHP_XPT_PCROFFSET_STC1_CAPTURE_PCR_ONCE_ENABLE_DISABLE 0 /*************************************************************************** *STC1 - STC1 Counter ***************************************************************************/ /* XPT_PCROFFSET :: STC1 :: COUNT [31:00] */ #define BCHP_XPT_PCROFFSET_STC1_COUNT_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_STC1_COUNT_SHIFT 0 /*************************************************************************** *STC2_CTRL - STC2 Counter Control ***************************************************************************/ /* XPT_PCROFFSET :: STC2_CTRL :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_STC2_CTRL_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_STC2_CTRL_reserved0_SHIFT 3 /* XPT_PCROFFSET :: STC2_CTRL :: MODE [02:02] */ #define BCHP_XPT_PCROFFSET_STC2_CTRL_MODE_MASK 0x00000004 #define BCHP_XPT_PCROFFSET_STC2_CTRL_MODE_SHIFT 2 #define BCHP_XPT_PCROFFSET_STC2_CTRL_MODE_BINARY 1 #define BCHP_XPT_PCROFFSET_STC2_CTRL_MODE_MOD_300 0 /* XPT_PCROFFSET :: STC2_CTRL :: FREEZE [01:01] */ #define BCHP_XPT_PCROFFSET_STC2_CTRL_FREEZE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_STC2_CTRL_FREEZE_SHIFT 1 #define BCHP_XPT_PCROFFSET_STC2_CTRL_FREEZE_STC_FREEZE 1 #define BCHP_XPT_PCROFFSET_STC2_CTRL_FREEZE_STC_NORMAL 0 /* XPT_PCROFFSET :: STC2_CTRL :: RESET [00:00] */ #define BCHP_XPT_PCROFFSET_STC2_CTRL_RESET_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_STC2_CTRL_RESET_SHIFT 0 #define BCHP_XPT_PCROFFSET_STC2_CTRL_RESET_STC_RESET 1 #define BCHP_XPT_PCROFFSET_STC2_CTRL_RESET_STC_NORMAL 0 /*************************************************************************** *STC2_TIMEBASE_SEL - STC2 Timebase Select ***************************************************************************/ /* XPT_PCROFFSET :: STC2_TIMEBASE_SEL :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_reserved0_SHIFT 3 /* XPT_PCROFFSET :: STC2_TIMEBASE_SEL :: TIMEBASE_SEL [02:00] */ #define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_TIMEBASE_SEL_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_TIMEBASE_SEL_SHIFT 0 #define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_0 0 #define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_1 1 #define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_2 2 #define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_3 3 #define BCHP_XPT_PCROFFSET_STC2_TIMEBASE_SEL_TIMEBASE_SEL_stc_free_run 4 /*************************************************************************** *STC2_RATE_CTRL - STC2 Counter Increment and Prescale ***************************************************************************/ /* XPT_PCROFFSET :: STC2_RATE_CTRL :: reserved0 [31:16] */ #define BCHP_XPT_PCROFFSET_STC2_RATE_CTRL_reserved0_MASK 0xffff0000 #define BCHP_XPT_PCROFFSET_STC2_RATE_CTRL_reserved0_SHIFT 16 /* XPT_PCROFFSET :: STC2_RATE_CTRL :: PRESCALE [15:08] */ #define BCHP_XPT_PCROFFSET_STC2_RATE_CTRL_PRESCALE_MASK 0x0000ff00 #define BCHP_XPT_PCROFFSET_STC2_RATE_CTRL_PRESCALE_SHIFT 8 /* XPT_PCROFFSET :: STC2_RATE_CTRL :: INCREMENT [07:00] */ #define BCHP_XPT_PCROFFSET_STC2_RATE_CTRL_INCREMENT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_STC2_RATE_CTRL_INCREMENT_SHIFT 0 /*************************************************************************** *STC2_CAPTURE_PCR_ONCE - STC2 Capture PCR once ***************************************************************************/ /* XPT_PCROFFSET :: STC2_CAPTURE_PCR_ONCE :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_STC2_CAPTURE_PCR_ONCE_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_STC2_CAPTURE_PCR_ONCE_reserved0_SHIFT 1 /* XPT_PCROFFSET :: STC2_CAPTURE_PCR_ONCE :: ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_STC2_CAPTURE_PCR_ONCE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_STC2_CAPTURE_PCR_ONCE_ENABLE_SHIFT 0 #define BCHP_XPT_PCROFFSET_STC2_CAPTURE_PCR_ONCE_ENABLE_ENABLE 1 #define BCHP_XPT_PCROFFSET_STC2_CAPTURE_PCR_ONCE_ENABLE_DISABLE 0 /*************************************************************************** *STC2 - STC2 Counter ***************************************************************************/ /* XPT_PCROFFSET :: STC2 :: COUNT [31:00] */ #define BCHP_XPT_PCROFFSET_STC2_COUNT_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_STC2_COUNT_SHIFT 0 /*************************************************************************** *STC3_CTRL - STC3 Counter Control ***************************************************************************/ /* XPT_PCROFFSET :: STC3_CTRL :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_STC3_CTRL_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_STC3_CTRL_reserved0_SHIFT 3 /* XPT_PCROFFSET :: STC3_CTRL :: MODE [02:02] */ #define BCHP_XPT_PCROFFSET_STC3_CTRL_MODE_MASK 0x00000004 #define BCHP_XPT_PCROFFSET_STC3_CTRL_MODE_SHIFT 2 #define BCHP_XPT_PCROFFSET_STC3_CTRL_MODE_BINARY 1 #define BCHP_XPT_PCROFFSET_STC3_CTRL_MODE_MOD_300 0 /* XPT_PCROFFSET :: STC3_CTRL :: FREEZE [01:01] */ #define BCHP_XPT_PCROFFSET_STC3_CTRL_FREEZE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_STC3_CTRL_FREEZE_SHIFT 1 #define BCHP_XPT_PCROFFSET_STC3_CTRL_FREEZE_STC_FREEZE 1 #define BCHP_XPT_PCROFFSET_STC3_CTRL_FREEZE_STC_NORMAL 0 /* XPT_PCROFFSET :: STC3_CTRL :: RESET [00:00] */ #define BCHP_XPT_PCROFFSET_STC3_CTRL_RESET_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_STC3_CTRL_RESET_SHIFT 0 #define BCHP_XPT_PCROFFSET_STC3_CTRL_RESET_STC_RESET 1 #define BCHP_XPT_PCROFFSET_STC3_CTRL_RESET_STC_NORMAL 0 /*************************************************************************** *STC3_TIMEBASE_SEL - STC3 Timebase Select ***************************************************************************/ /* XPT_PCROFFSET :: STC3_TIMEBASE_SEL :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_reserved0_SHIFT 3 /* XPT_PCROFFSET :: STC3_TIMEBASE_SEL :: TIMEBASE_SEL [02:00] */ #define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_TIMEBASE_SEL_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_TIMEBASE_SEL_SHIFT 0 #define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_0 0 #define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_1 1 #define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_2 2 #define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_TIMEBASE_SEL_Timebase_3 3 #define BCHP_XPT_PCROFFSET_STC3_TIMEBASE_SEL_TIMEBASE_SEL_stc_free_run 4 /*************************************************************************** *STC3_RATE_CTRL - STC3 Counter Increment and Prescale ***************************************************************************/ /* XPT_PCROFFSET :: STC3_RATE_CTRL :: reserved0 [31:16] */ #define BCHP_XPT_PCROFFSET_STC3_RATE_CTRL_reserved0_MASK 0xffff0000 #define BCHP_XPT_PCROFFSET_STC3_RATE_CTRL_reserved0_SHIFT 16 /* XPT_PCROFFSET :: STC3_RATE_CTRL :: PRESCALE [15:08] */ #define BCHP_XPT_PCROFFSET_STC3_RATE_CTRL_PRESCALE_MASK 0x0000ff00 #define BCHP_XPT_PCROFFSET_STC3_RATE_CTRL_PRESCALE_SHIFT 8 /* XPT_PCROFFSET :: STC3_RATE_CTRL :: INCREMENT [07:00] */ #define BCHP_XPT_PCROFFSET_STC3_RATE_CTRL_INCREMENT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_STC3_RATE_CTRL_INCREMENT_SHIFT 0 /*************************************************************************** *STC3_CAPTURE_PCR_ONCE - STC3 Capture PCR once ***************************************************************************/ /* XPT_PCROFFSET :: STC3_CAPTURE_PCR_ONCE :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_STC3_CAPTURE_PCR_ONCE_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_STC3_CAPTURE_PCR_ONCE_reserved0_SHIFT 1 /* XPT_PCROFFSET :: STC3_CAPTURE_PCR_ONCE :: ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_STC3_CAPTURE_PCR_ONCE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_STC3_CAPTURE_PCR_ONCE_ENABLE_SHIFT 0 #define BCHP_XPT_PCROFFSET_STC3_CAPTURE_PCR_ONCE_ENABLE_ENABLE 1 #define BCHP_XPT_PCROFFSET_STC3_CAPTURE_PCR_ONCE_ENABLE_DISABLE 0 /*************************************************************************** *STC3 - STC3 Counter ***************************************************************************/ /* XPT_PCROFFSET :: STC3 :: COUNT [31:00] */ #define BCHP_XPT_PCROFFSET_STC3_COUNT_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_STC3_COUNT_SHIFT 0 /*************************************************************************** *TM_PCROFFSET_CONFIG_TABLE - TM Control ***************************************************************************/ /* XPT_PCROFFSET :: TM_PCROFFSET_CONFIG_TABLE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_TM_PCROFFSET_CONFIG_TABLE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_TM_PCROFFSET_CONFIG_TABLE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: TM_PCROFFSET_CONFIG_TABLE :: TM [03:00] */ #define BCHP_XPT_PCROFFSET_TM_PCROFFSET_CONFIG_TABLE_TM_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_TM_PCROFFSET_CONFIG_TABLE_TM_SHIFT 0 /*************************************************************************** *STC_BROADCAST_SEL - STC Broadcast bus select ***************************************************************************/ /* XPT_PCROFFSET :: STC_BROADCAST_SEL :: reserved0 [31:16] */ #define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_reserved0_MASK 0xffff0000 #define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_reserved0_SHIFT 16 /* XPT_PCROFFSET :: STC_BROADCAST_SEL :: STC_BCAST3_SEL [15:12] */ #define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST3_SEL_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST3_SEL_SHIFT 12 /* XPT_PCROFFSET :: STC_BROADCAST_SEL :: STC_BCAST2_SEL [11:08] */ #define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST2_SEL_MASK 0x00000f00 #define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST2_SEL_SHIFT 8 /* XPT_PCROFFSET :: STC_BROADCAST_SEL :: STC_BCAST1_SEL [07:04] */ #define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST1_SEL_MASK 0x000000f0 #define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST1_SEL_SHIFT 4 /* XPT_PCROFFSET :: STC_BROADCAST_SEL :: STC_BCAST0_SEL [03:00] */ #define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST0_SEL_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_STC_BROADCAST_SEL_STC_BCAST0_SEL_SHIFT 0 /*************************************************************************** *PID_CONFIG_TABLE_%i - PID Configuration Table ***************************************************************************/ #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_ARRAY_BASE 0x00227400 #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_ARRAY_START 0 #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_ARRAY_END 127 #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *PID_CONFIG_TABLE_%i - PID Configuration Table ***************************************************************************/ /* XPT_PCROFFSET :: PID_CONFIG_TABLE_i :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_reserved0_SHIFT 8 /* XPT_PCROFFSET :: PID_CONFIG_TABLE_i :: reserved_for_eco1 [07:07] */ #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_reserved_for_eco1_MASK 0x00000080 #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: PID_CONFIG_TABLE_i :: JITTER_DIS [06:06] */ #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_JITTER_DIS_MASK 0x00000040 #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_JITTER_DIS_SHIFT 6 #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_JITTER_DIS_ENABLE 0 #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_JITTER_DIS_DISABLE 1 /* XPT_PCROFFSET :: PID_CONFIG_TABLE_i :: FIXED_OFFSET_EN [05:05] */ #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_FIXED_OFFSET_EN_MASK 0x00000020 #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_FIXED_OFFSET_EN_SHIFT 5 #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_FIXED_OFFSET_EN_ENABLE 1 #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_FIXED_OFFSET_EN_DISABLE 0 /* XPT_PCROFFSET :: PID_CONFIG_TABLE_i :: PCROFFSET_EN [04:04] */ #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_PCROFFSET_EN_MASK 0x00000010 #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_PCROFFSET_EN_SHIFT 4 #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_PCROFFSET_EN_ENABLE 1 #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_PCROFFSET_EN_DISABLE 0 /* XPT_PCROFFSET :: PID_CONFIG_TABLE_i :: OFFSET_INDEX [03:00] */ #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_OFFSET_INDEX_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_PID_CONFIG_TABLE_i_OFFSET_INDEX_SHIFT 0 /*************************************************************************** *CONTEXT0_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT0_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT0_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT0_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT0_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT0_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT0_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT0_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT0_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT0_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT0_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT0_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT0_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT0_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT0_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT0_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT0_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT0_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT0_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT0_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT0_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT0_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT0_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT0_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT0_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT0_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT0_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT0_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT0_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT0_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT0_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT0_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT0_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT0_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT0_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT0_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT0_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT0_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT1_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT1_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT1_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT1_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT1_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT1_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT1_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT1_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT1_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT1_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT1_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT1_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT1_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT1_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT1_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT1_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT1_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT1_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT1_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT1_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT1_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT1_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT1_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT1_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT1_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT1_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT1_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT1_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT1_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT1_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT1_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT1_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT1_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT1_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT1_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT1_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT1_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT1_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT2_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT2_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT2_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT2_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT2_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT2_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT2_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT2_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT2_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT2_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT2_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT2_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT2_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT2_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT2_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT2_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT2_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT2_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT2_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT2_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT2_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT2_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT2_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT2_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT2_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT2_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT2_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT2_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT2_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT2_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT2_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT2_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT2_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT2_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT2_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT2_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT2_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT2_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT3_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT3_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT3_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT3_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT3_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT3_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT3_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT3_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT3_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT3_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT3_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT3_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT3_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT3_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT3_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT3_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT3_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT3_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT3_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT3_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT3_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT3_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT3_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT3_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT3_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT3_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT3_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT3_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT3_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT3_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT3_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT3_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT3_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT3_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT3_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT3_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT3_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT3_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT4_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT4_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT4_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT4_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT4_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT4_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT4_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT4_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT4_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT4_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT4_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT4_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT4_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT4_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT4_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT4_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT4_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT4_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT4_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT4_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT4_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT4_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT4_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT4_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT4_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT4_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT4_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT4_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT4_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT4_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT4_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT4_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT4_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT4_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT4_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT4_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT4_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT4_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT5_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT5_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT5_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT5_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT5_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT5_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT5_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT5_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT5_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT5_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT5_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT5_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT5_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT5_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT5_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT5_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT5_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT5_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT5_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT5_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT5_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT5_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT5_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT5_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT5_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT5_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT5_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT5_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT5_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT5_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT5_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT5_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT5_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT5_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT5_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT5_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT5_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT5_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT6_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT6_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT6_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT6_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT6_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT6_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT6_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT6_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT6_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT6_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT6_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT6_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT6_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT6_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT6_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT6_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT6_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT6_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT6_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT6_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT6_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT6_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT6_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT6_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT6_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT6_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT6_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT6_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT6_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT6_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT6_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT6_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT6_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT6_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT6_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT6_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT6_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT6_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT7_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT7_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT7_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT7_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT7_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT7_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT7_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT7_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT7_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT7_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT7_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT7_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT7_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT7_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT7_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT7_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT7_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT7_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT7_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT7_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT7_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT7_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT7_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT7_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT7_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT7_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT7_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT7_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT7_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT7_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT7_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT7_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT7_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT7_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT7_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT7_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT7_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT7_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT8_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT8_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT8_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT8_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT8_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT8_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT8_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT8_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT8_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT8_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT8_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT8_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT8_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT8_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT8_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT8_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT8_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT8_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT8_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT8_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT8_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT8_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT8_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT8_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT8_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT8_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT8_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT8_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT8_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT8_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT8_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT8_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT8_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT8_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT8_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT8_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT8_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT8_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT9_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT9_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT9_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT9_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT9_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT9_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT9_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT9_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT9_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT9_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT9_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT9_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT9_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT9_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT9_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT9_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT9_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT9_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT9_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT9_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT9_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT9_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT9_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT9_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT9_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT9_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT9_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT9_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT9_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT9_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT9_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT9_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT9_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT9_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT9_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT9_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT9_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT9_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT10_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT10_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT10_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT10_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT10_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT10_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT10_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT10_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT10_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT10_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT10_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT10_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT10_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT10_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT10_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT10_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT10_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT10_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT10_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT10_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT10_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT10_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT10_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT10_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT10_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT10_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT10_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT10_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT10_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT10_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT10_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT10_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT10_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT10_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT10_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT10_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT10_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT10_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT11_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT11_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT11_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT11_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT11_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT11_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT11_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT11_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT11_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT11_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT11_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT11_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT11_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT11_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT11_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT11_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT11_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT11_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT11_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT11_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT11_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT11_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT11_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT11_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT11_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT11_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT11_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT11_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT11_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT11_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT11_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT11_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT11_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT11_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT11_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT11_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT11_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT11_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT12_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT12_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT12_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT12_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT12_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT12_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT12_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT12_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT12_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT12_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT12_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT12_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT12_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT12_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT12_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT12_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT12_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT12_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT12_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT12_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT12_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT12_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT12_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT12_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT12_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT12_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT12_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT12_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT12_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT12_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT12_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT12_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT12_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT12_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT12_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT12_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT12_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT12_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT13_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT13_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT13_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT13_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT13_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT13_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT13_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT13_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT13_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT13_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT13_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT13_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT13_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT13_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT13_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT13_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT13_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT13_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT13_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT13_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT13_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT13_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT13_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT13_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT13_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT13_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT13_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT13_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT13_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT13_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT13_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT13_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT13_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT13_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT13_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT13_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT13_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT13_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT14_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT14_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT14_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT14_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT14_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT14_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT14_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT14_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT14_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT14_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT14_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT14_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT14_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT14_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT14_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT14_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT14_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT14_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT14_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT14_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT14_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT14_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT14_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT14_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT14_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT14_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT14_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT14_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT14_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT14_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT14_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT14_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT14_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT14_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT14_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT14_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT14_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT14_RESERVED_CFG_4_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT15_PCROFFSET_CTRL - Config word 0 - PCROFFSET Main Control ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: reserved0 [31:24] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved0_MASK 0xff000000 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved0_SHIFT 24 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: IGNORE_AFID [23:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFID_MASK 0x00800000 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFID_SHIFT 23 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFID_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFID_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: IGNORE_CFF [22:22] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CFF_MASK 0x00400000 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CFF_SHIFT 22 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CFF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CFF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: IGNORE_RTS00 [21:21] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_RTS00_MASK 0x00200000 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_RTS00_SHIFT 21 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_RTS00_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_RTS00_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: IGNORE_AFS [20:20] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFS_MASK 0x00100000 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFS_SHIFT 20 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFS_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_AFS_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: IGNORE_CC [19:19] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CC_MASK 0x00080000 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CC_SHIFT 19 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CC_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_CC_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: IGNORE_OCF [18:18] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_OCF_MASK 0x00040000 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_OCF_SHIFT 18 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_OCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_OCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: IGNORE_SCF [17:17] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_SCF_MASK 0x00020000 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_SCF_SHIFT 17 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_SCF_IGNORE 1 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_IGNORE_SCF_NORMAL 0 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: PACKET_MODE [16:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_PACKET_MODE_MASK 0x00010000 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_PACKET_MODE_SHIFT 16 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_PACKET_MODE_MPEG 0 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_PACKET_MODE_DIRECTV 1 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: reserved_for_eco1 [15:12] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved_for_eco1_MASK 0x0000f000 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved_for_eco1_SHIFT 12 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: USE_NEW_OFFSET_DURING_ERROR [11:11] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_MASK 0x00000800 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_USE_NEW_OFFSET_DURING_ERROR_SHIFT 11 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: TWO_ERR_ACQ [10:10] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_TWO_ERR_ACQ_MASK 0x00000400 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_TWO_ERR_ACQ_SHIFT 10 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: ONE_ERR_ACQ [09:09] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_ONE_ERR_ACQ_MASK 0x00000200 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_ONE_ERR_ACQ_SHIFT 9 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: CTXT_ENABLE [08:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_CTXT_ENABLE_MASK 0x00000100 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_CTXT_ENABLE_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: reserved_for_eco2 [07:06] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved_for_eco2_MASK 0x000000c0 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved_for_eco2_SHIFT 6 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: STC_SEL [05:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_STC_SEL_MASK 0x00000030 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_STC_SEL_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: reserved_for_eco3 [03:02] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved_for_eco3_MASK 0x0000000c #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_reserved_for_eco3_SHIFT 2 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: INVALIDATE_PCR_OFFSET_ON_SPLICE [01:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_MASK 0x00000002 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_INVALIDATE_PCR_OFFSET_ON_SPLICE_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT15_PCROFFSET_CTRL :: SPLICE_ENABLE [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_SPLICE_ENABLE_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT15_PCROFFSET_CTRL_SPLICE_ENABLE_SHIFT 0 /*************************************************************************** *CONTEXT15_PP_PCR_PID_CH_NUM - Config Word 1 - PP_PCR_PID_CH_NUM Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_PP_PCR_PID_CH_NUM :: reserved0 [31:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_PID_CH_NUM_reserved0_MASK 0xffffff80 #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_PID_CH_NUM_reserved0_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT15_PP_PCR_PID_CH_NUM :: PCR_PID_CH_NUM [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_PID_CH_NUM_PCR_PID_CH_NUM_SHIFT 0 /*************************************************************************** *CONTEXT15_SPLICE_STATE - Config Word 2 - SPLICE STATE Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_SPLICE_STATE :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATE_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATE_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_STATE :: SPLICE_STATE [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATE_SPLICE_STATE_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATE_SPLICE_STATE_SHIFT 0 /*************************************************************************** *CONTEXT15_SPLICE_STATUS - Config Word 3 - SPLICE STATUS Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_SPLICE_STATUS :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATUS_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATUS_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_STATUS :: COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATUS_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_STATUS_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT15_SPLICE_RD_PTR - Config Word 4 - SPLICE PID Channel Read Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_SPLICE_RD_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_RD_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_RD_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_RD_PTR :: NEXT_PID_CH_RD_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_RD_PTR_NEXT_PID_CH_RD_PTR_SHIFT 0 /*************************************************************************** *CONTEXT15_SPLICE_WR_PTR - Config Word 5 - SPLICE PID Channel Write Pointer ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_SPLICE_WR_PTR :: reserved0 [31:03] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_WR_PTR_reserved0_MASK 0xfffffff8 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_WR_PTR_reserved0_SHIFT 3 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_WR_PTR :: NEXT_PID_CH_WR_PTR [02:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_MASK 0x00000007 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_WR_PTR_NEXT_PID_CH_WR_PTR_SHIFT 0 /*************************************************************************** *CONTEXT15_SPLICE_PID_CH0_CH1 - Config Word 6 - NEXT SPLICE PCR PID Channel 0 and Channel 1 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH0_CH1 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_1 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_NEXT_PID_CH_1_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH0_CH1 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH0_CH1 :: NEXT_PID_CH_0 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH0_CH1_NEXT_PID_CH_0_SHIFT 0 /*************************************************************************** *CONTEXT15_SPLICE_PID_CH2_CH3 - Config Word 7 - NEXT SPLICE PCR PID Channel 2 and Channel 3 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH2_CH3 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_3 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_NEXT_PID_CH_3_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH2_CH3 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH2_CH3 :: NEXT_PID_CH_2 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH2_CH3_NEXT_PID_CH_2_SHIFT 0 /*************************************************************************** *CONTEXT15_SPLICE_PID_CH4_CH5 - Config Word 8 - NEXT SPLICE PCR PID Channel 4 and Channel 5 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH4_CH5 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_5 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_NEXT_PID_CH_5_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH4_CH5 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH4_CH5 :: NEXT_PID_CH_4 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH4_CH5_NEXT_PID_CH_4_SHIFT 0 /*************************************************************************** *CONTEXT15_SPLICE_PID_CH6_CH7 - Config Word 9 - NEXT SPLICE PCR PID Channel 6 and Channel 7 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH6_CH7 :: reserved_for_eco0 [31:23] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_reserved_for_eco0_MASK 0xff800000 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_reserved_for_eco0_SHIFT 23 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_7 [22:16] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_MASK 0x007f0000 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_NEXT_PID_CH_7_SHIFT 16 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH6_CH7 :: reserved_for_eco1 [15:07] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_reserved_for_eco1_MASK 0x0000ff80 #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_reserved_for_eco1_SHIFT 7 /* XPT_PCROFFSET :: CONTEXT15_SPLICE_PID_CH6_CH7 :: NEXT_PID_CH_6 [06:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_MASK 0x0000007f #define BCHP_XPT_PCROFFSET_CONTEXT15_SPLICE_PID_CH6_CH7_NEXT_PID_CH_6_SHIFT 0 /*************************************************************************** *CONTEXT15_OFFSET_STATE - Config Word 10 - OFFSET STATE register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_OFFSET_STATE :: reserved0 [31:04] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATE_reserved0_SHIFT 4 /* XPT_PCROFFSET :: CONTEXT15_OFFSET_STATE :: OFFSET_STATE [03:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATE_OFFSET_STATE_MASK 0x0000000f #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATE_OFFSET_STATE_SHIFT 0 /*************************************************************************** *CONTEXT15_OFFSET - Config Word 11 - OFFSET read/write ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_OFFSET :: PCR_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_PCR_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_PCR_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT15_OFFSET_VALID - Config Word 12 - OFFSET Valid ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_OFFSET_VALID :: reserved0 [31:01] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_VALID_reserved0_MASK 0xfffffffe #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_VALID_reserved0_SHIFT 1 /* XPT_PCROFFSET :: CONTEXT15_OFFSET_VALID :: PCR_OFFSET_VALID [00:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_VALID_PCR_OFFSET_VALID_MASK 0x00000001 #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_VALID_PCR_OFFSET_VALID_SHIFT 0 #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_VALID_PCR_OFFSET_VALID_INVALID 0 #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_VALID_PCR_OFFSET_VALID_VALID 1 /*************************************************************************** *CONTEXT15_OFFSET_MAX_ERROR - Config Word 13 - OFFSET MAX Error ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_OFFSET_MAX_ERROR :: MAX_ERROR [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_MAX_ERROR_MAX_ERROR_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_MAX_ERROR_MAX_ERROR_SHIFT 0 /*************************************************************************** *CONTEXT15_OFFSET_THRESHOLD - Config Word 14 - OFFSET Threshold ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_OFFSET_THRESHOLD :: OFFSET_THRESHOLD [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_THRESHOLD_OFFSET_THRESHOLD_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_THRESHOLD_OFFSET_THRESHOLD_SHIFT 0 /*************************************************************************** *CONTEXT15_FIXED_OFFSET - Config Word 15 - Fixed OFFSET ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_FIXED_OFFSET :: FIXED_OFFSET [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_FIXED_OFFSET_FIXED_OFFSET_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_FIXED_OFFSET_FIXED_OFFSET_SHIFT 0 /*************************************************************************** *CONTEXT15_PP_PCR_COUNT - Config Word 16 - PCR COUNT register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_PP_PCR_COUNT :: reserved0 [31:08] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_COUNT_reserved0_MASK 0xffffff00 #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_COUNT_reserved0_SHIFT 8 /* XPT_PCROFFSET :: CONTEXT15_PP_PCR_COUNT :: PCR_COUNT [07:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_COUNT_PCR_COUNT_MASK 0x000000ff #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_PCR_COUNT_PCR_COUNT_SHIFT 0 /*************************************************************************** *CONTEXT15_PP_SEND_PCR_BASE - Config Word 17 - Send PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_PP_SEND_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_SEND_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_SEND_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT15_PP_LAST_PCR_BASE - Config Word 18 - Last PCR Base Register ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_PP_LAST_PCR_BASE :: PCR_BASE [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_LAST_PCR_BASE_PCR_BASE_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_PP_LAST_PCR_BASE_PCR_BASE_SHIFT 0 /*************************************************************************** *CONTEXT15_OFFSET_STATUS_0 - Config Word 19 - OFFSET STATUS 0 for PID channel 0 to 31 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_OFFSET_STATUS_0 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_0_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_0_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT15_OFFSET_STATUS_1 - Config Word 20 - OFFSET STATUS 1 for PID channel 32 to 63 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_OFFSET_STATUS_1 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_1_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_1_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT15_OFFSET_STATUS_2 - Config Word 21 - OFFSET STATUS 2 for PID channel 64 to 95 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_OFFSET_STATUS_2 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_2_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_2_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT15_OFFSET_STATUS_3 - Config Word 22 - OFFSET STATUS 3 for PID channel 96 to 127 ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_OFFSET_STATUS_3 :: PID_STATUS [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_3_PID_STATUS_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_OFFSET_STATUS_3_PID_STATUS_SHIFT 0 /*************************************************************************** *CONTEXT15_RESERVED_CFG_0 - Config Word 27 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_RESERVED_CFG_0 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_0_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_0_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT15_RESERVED_CFG_1 - Config Word 28 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_RESERVED_CFG_1 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_1_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_1_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT15_RESERVED_CFG_2 - Config Word 29 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_RESERVED_CFG_2 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_2_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_2_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT15_RESERVED_CFG_3 - Config Word 30 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_RESERVED_CFG_3 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_3_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_3_RESERVED_SHIFT 0 /*************************************************************************** *CONTEXT15_RESERVED_CFG_4 - Config Word 31 - RESERVED ***************************************************************************/ /* XPT_PCROFFSET :: CONTEXT15_RESERVED_CFG_4 :: RESERVED [31:00] */ #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_4_RESERVED_MASK 0xffffffff #define BCHP_XPT_PCROFFSET_CONTEXT15_RESERVED_CFG_4_RESERVED_SHIFT 0 #endif /* #ifndef BCHP_XPT_PCROFFSET_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015000000000000011561 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xpu.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xp0000644000175000017500000004317711610313111031074 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_xpt_xpu.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:28p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:07 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xpu.h $ * * Hydra_Software_Devel/1 7/17/09 8:28p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_XPT_XPU_H__ #define BCHP_XPT_XPU_H__ /*************************************************************************** *XPT_XPU - XPT XPU Control Registers ***************************************************************************/ #define BCHP_XPT_XPU_TESTREG 0x00220000 /* Test register - reserved */ #define BCHP_XPT_XPU_PSW 0x00220004 /* Processor status word */ #define BCHP_XPT_XPU_PSWSH 0x00220008 /* Processor status word shadow */ #define BCHP_XPT_XPU_SP 0x00220010 /* Stack pointer */ #define BCHP_XPT_XPU_PC 0x00220018 /* Program counter */ #define BCHP_XPT_XPU_STACK_0 0x00220020 /* Stack 0 */ #define BCHP_XPT_XPU_STACK_1 0x00220024 /* Stack 1 */ #define BCHP_XPT_XPU_STACK_2 0x00220028 /* Stack 2 */ #define BCHP_XPT_XPU_STACK_3 0x0022002c /* Stack 3 */ #define BCHP_XPT_XPU_REG_R0_R1 0x00220030 /* Register pair r0/r1 */ #define BCHP_XPT_XPU_REG_R2_R3 0x00220034 /* Register pair r2/r3 */ #define BCHP_XPT_XPU_REG_R4_R5 0x00220038 /* Register pair r4/r5 */ #define BCHP_XPT_XPU_REG_R6_R7 0x0022003c /* Register pair r6/r7 */ #define BCHP_XPT_XPU_REG_R8_R9 0x00220040 /* Register pair r8/r9 */ #define BCHP_XPT_XPU_REG_R10_R11 0x00220044 /* Register pair r10/r11 */ #define BCHP_XPT_XPU_REG_R12_R13 0x00220048 /* Register pair r12/r13 */ #define BCHP_XPT_XPU_REG_R14_R15 0x0022004c /* Register pair r14/r15 */ /*************************************************************************** *TESTREG - Test register - reserved ***************************************************************************/ /* XPT_XPU :: TESTREG :: reserved0 [31:01] */ #define BCHP_XPT_XPU_TESTREG_reserved0_MASK 0xfffffffe #define BCHP_XPT_XPU_TESTREG_reserved0_SHIFT 1 /* XPT_XPU :: TESTREG :: TESTBIT [00:00] */ #define BCHP_XPT_XPU_TESTREG_TESTBIT_MASK 0x00000001 #define BCHP_XPT_XPU_TESTREG_TESTBIT_SHIFT 0 /*************************************************************************** *PSW - Processor status word ***************************************************************************/ /* XPT_XPU :: PSW :: reserved0 [31:11] */ #define BCHP_XPT_XPU_PSW_reserved0_MASK 0xfffff800 #define BCHP_XPT_XPU_PSW_reserved0_SHIFT 11 /* XPT_XPU :: PSW :: DFLAG [10:10] */ #define BCHP_XPT_XPU_PSW_DFLAG_MASK 0x00000400 #define BCHP_XPT_XPU_PSW_DFLAG_SHIFT 10 /* XPT_XPU :: PSW :: LFLAG [09:09] */ #define BCHP_XPT_XPU_PSW_LFLAG_MASK 0x00000200 #define BCHP_XPT_XPU_PSW_LFLAG_SHIFT 9 /* XPT_XPU :: PSW :: VFLAG [08:08] */ #define BCHP_XPT_XPU_PSW_VFLAG_MASK 0x00000100 #define BCHP_XPT_XPU_PSW_VFLAG_SHIFT 8 /* XPT_XPU :: PSW :: HFLAG [07:07] */ #define BCHP_XPT_XPU_PSW_HFLAG_MASK 0x00000080 #define BCHP_XPT_XPU_PSW_HFLAG_SHIFT 7 /* XPT_XPU :: PSW :: WFLAG [06:06] */ #define BCHP_XPT_XPU_PSW_WFLAG_MASK 0x00000040 #define BCHP_XPT_XPU_PSW_WFLAG_SHIFT 6 /* XPT_XPU :: PSW :: IFLAG [05:05] */ #define BCHP_XPT_XPU_PSW_IFLAG_MASK 0x00000020 #define BCHP_XPT_XPU_PSW_IFLAG_SHIFT 5 /* XPT_XPU :: PSW :: EFLAG [04:04] */ #define BCHP_XPT_XPU_PSW_EFLAG_MASK 0x00000010 #define BCHP_XPT_XPU_PSW_EFLAG_SHIFT 4 /* XPT_XPU :: PSW :: CFLAG [03:03] */ #define BCHP_XPT_XPU_PSW_CFLAG_MASK 0x00000008 #define BCHP_XPT_XPU_PSW_CFLAG_SHIFT 3 /* XPT_XPU :: PSW :: SFLAG [02:02] */ #define BCHP_XPT_XPU_PSW_SFLAG_MASK 0x00000004 #define BCHP_XPT_XPU_PSW_SFLAG_SHIFT 2 /* XPT_XPU :: PSW :: ZFLAG [01:01] */ #define BCHP_XPT_XPU_PSW_ZFLAG_MASK 0x00000002 #define BCHP_XPT_XPU_PSW_ZFLAG_SHIFT 1 /* XPT_XPU :: PSW :: OFLAG [00:00] */ #define BCHP_XPT_XPU_PSW_OFLAG_MASK 0x00000001 #define BCHP_XPT_XPU_PSW_OFLAG_SHIFT 0 /*************************************************************************** *PSWSH - Processor status word shadow ***************************************************************************/ /* XPT_XPU :: PSWSH :: reserved0 [31:07] */ #define BCHP_XPT_XPU_PSWSH_reserved0_MASK 0xffffff80 #define BCHP_XPT_XPU_PSWSH_reserved0_SHIFT 7 /* XPT_XPU :: PSWSH :: WFLAG [06:06] */ #define BCHP_XPT_XPU_PSWSH_WFLAG_MASK 0x00000040 #define BCHP_XPT_XPU_PSWSH_WFLAG_SHIFT 6 /* XPT_XPU :: PSWSH :: reserved1 [05:04] */ #define BCHP_XPT_XPU_PSWSH_reserved1_MASK 0x00000030 #define BCHP_XPT_XPU_PSWSH_reserved1_SHIFT 4 /* XPT_XPU :: PSWSH :: CFLAG [03:03] */ #define BCHP_XPT_XPU_PSWSH_CFLAG_MASK 0x00000008 #define BCHP_XPT_XPU_PSWSH_CFLAG_SHIFT 3 /* XPT_XPU :: PSWSH :: SFLAG [02:02] */ #define BCHP_XPT_XPU_PSWSH_SFLAG_MASK 0x00000004 #define BCHP_XPT_XPU_PSWSH_SFLAG_SHIFT 2 /* XPT_XPU :: PSWSH :: ZFLAG [01:01] */ #define BCHP_XPT_XPU_PSWSH_ZFLAG_MASK 0x00000002 #define BCHP_XPT_XPU_PSWSH_ZFLAG_SHIFT 1 /* XPT_XPU :: PSWSH :: OFLAG [00:00] */ #define BCHP_XPT_XPU_PSWSH_OFLAG_MASK 0x00000001 #define BCHP_XPT_XPU_PSWSH_OFLAG_SHIFT 0 /*************************************************************************** *SP - Stack pointer ***************************************************************************/ /* XPT_XPU :: SP :: reserved0 [31:02] */ #define BCHP_XPT_XPU_SP_reserved0_MASK 0xfffffffc #define BCHP_XPT_XPU_SP_reserved0_SHIFT 2 /* XPT_XPU :: SP :: SPTR [01:00] */ #define BCHP_XPT_XPU_SP_SPTR_MASK 0x00000003 #define BCHP_XPT_XPU_SP_SPTR_SHIFT 0 /*************************************************************************** *PC - Program counter ***************************************************************************/ /* XPT_XPU :: PC :: reserved0 [31:12] */ #define BCHP_XPT_XPU_PC_reserved0_MASK 0xfffff000 #define BCHP_XPT_XPU_PC_reserved0_SHIFT 12 /* XPT_XPU :: PC :: PC [11:00] */ #define BCHP_XPT_XPU_PC_PC_MASK 0x00000fff #define BCHP_XPT_XPU_PC_PC_SHIFT 0 /*************************************************************************** *STACK_0 - Stack 0 ***************************************************************************/ /* XPT_XPU :: STACK_0 :: reserved0 [31:13] */ #define BCHP_XPT_XPU_STACK_0_reserved0_MASK 0xffffe000 #define BCHP_XPT_XPU_STACK_0_reserved0_SHIFT 13 /* XPT_XPU :: STACK_0 :: VALID [12:12] */ #define BCHP_XPT_XPU_STACK_0_VALID_MASK 0x00001000 #define BCHP_XPT_XPU_STACK_0_VALID_SHIFT 12 /* XPT_XPU :: STACK_0 :: STACK_DATA [11:00] */ #define BCHP_XPT_XPU_STACK_0_STACK_DATA_MASK 0x00000fff #define BCHP_XPT_XPU_STACK_0_STACK_DATA_SHIFT 0 /*************************************************************************** *STACK_1 - Stack 1 ***************************************************************************/ /* XPT_XPU :: STACK_1 :: reserved0 [31:13] */ #define BCHP_XPT_XPU_STACK_1_reserved0_MASK 0xffffe000 #define BCHP_XPT_XPU_STACK_1_reserved0_SHIFT 13 /* XPT_XPU :: STACK_1 :: VALID [12:12] */ #define BCHP_XPT_XPU_STACK_1_VALID_MASK 0x00001000 #define BCHP_XPT_XPU_STACK_1_VALID_SHIFT 12 /* XPT_XPU :: STACK_1 :: STACK_DATA [11:00] */ #define BCHP_XPT_XPU_STACK_1_STACK_DATA_MASK 0x00000fff #define BCHP_XPT_XPU_STACK_1_STACK_DATA_SHIFT 0 /*************************************************************************** *STACK_2 - Stack 2 ***************************************************************************/ /* XPT_XPU :: STACK_2 :: reserved0 [31:13] */ #define BCHP_XPT_XPU_STACK_2_reserved0_MASK 0xffffe000 #define BCHP_XPT_XPU_STACK_2_reserved0_SHIFT 13 /* XPT_XPU :: STACK_2 :: VALID [12:12] */ #define BCHP_XPT_XPU_STACK_2_VALID_MASK 0x00001000 #define BCHP_XPT_XPU_STACK_2_VALID_SHIFT 12 /* XPT_XPU :: STACK_2 :: STACK_DATA [11:00] */ #define BCHP_XPT_XPU_STACK_2_STACK_DATA_MASK 0x00000fff #define BCHP_XPT_XPU_STACK_2_STACK_DATA_SHIFT 0 /*************************************************************************** *STACK_3 - Stack 3 ***************************************************************************/ /* XPT_XPU :: STACK_3 :: reserved0 [31:13] */ #define BCHP_XPT_XPU_STACK_3_reserved0_MASK 0xffffe000 #define BCHP_XPT_XPU_STACK_3_reserved0_SHIFT 13 /* XPT_XPU :: STACK_3 :: VALID [12:12] */ #define BCHP_XPT_XPU_STACK_3_VALID_MASK 0x00001000 #define BCHP_XPT_XPU_STACK_3_VALID_SHIFT 12 /* XPT_XPU :: STACK_3 :: STACK_DATA [11:00] */ #define BCHP_XPT_XPU_STACK_3_STACK_DATA_MASK 0x00000fff #define BCHP_XPT_XPU_STACK_3_STACK_DATA_SHIFT 0 /*************************************************************************** *REG_R0_R1 - Register pair r0/r1 ***************************************************************************/ /* XPT_XPU :: REG_R0_R1 :: reserved0 [31:16] */ #define BCHP_XPT_XPU_REG_R0_R1_reserved0_MASK 0xffff0000 #define BCHP_XPT_XPU_REG_R0_R1_reserved0_SHIFT 16 /* XPT_XPU :: REG_R0_R1 :: REGISTER [15:00] */ #define BCHP_XPT_XPU_REG_R0_R1_REGISTER_MASK 0x0000ffff #define BCHP_XPT_XPU_REG_R0_R1_REGISTER_SHIFT 0 /*************************************************************************** *REG_R2_R3 - Register pair r2/r3 ***************************************************************************/ /* XPT_XPU :: REG_R2_R3 :: reserved0 [31:16] */ #define BCHP_XPT_XPU_REG_R2_R3_reserved0_MASK 0xffff0000 #define BCHP_XPT_XPU_REG_R2_R3_reserved0_SHIFT 16 /* XPT_XPU :: REG_R2_R3 :: REGISTER [15:00] */ #define BCHP_XPT_XPU_REG_R2_R3_REGISTER_MASK 0x0000ffff #define BCHP_XPT_XPU_REG_R2_R3_REGISTER_SHIFT 0 /*************************************************************************** *REG_R4_R5 - Register pair r4/r5 ***************************************************************************/ /* XPT_XPU :: REG_R4_R5 :: reserved0 [31:16] */ #define BCHP_XPT_XPU_REG_R4_R5_reserved0_MASK 0xffff0000 #define BCHP_XPT_XPU_REG_R4_R5_reserved0_SHIFT 16 /* XPT_XPU :: REG_R4_R5 :: REGISTER [15:00] */ #define BCHP_XPT_XPU_REG_R4_R5_REGISTER_MASK 0x0000ffff #define BCHP_XPT_XPU_REG_R4_R5_REGISTER_SHIFT 0 /*************************************************************************** *REG_R6_R7 - Register pair r6/r7 ***************************************************************************/ /* XPT_XPU :: REG_R6_R7 :: reserved0 [31:16] */ #define BCHP_XPT_XPU_REG_R6_R7_reserved0_MASK 0xffff0000 #define BCHP_XPT_XPU_REG_R6_R7_reserved0_SHIFT 16 /* XPT_XPU :: REG_R6_R7 :: REGISTER [15:00] */ #define BCHP_XPT_XPU_REG_R6_R7_REGISTER_MASK 0x0000ffff #define BCHP_XPT_XPU_REG_R6_R7_REGISTER_SHIFT 0 /*************************************************************************** *REG_R8_R9 - Register pair r8/r9 ***************************************************************************/ /* XPT_XPU :: REG_R8_R9 :: reserved0 [31:16] */ #define BCHP_XPT_XPU_REG_R8_R9_reserved0_MASK 0xffff0000 #define BCHP_XPT_XPU_REG_R8_R9_reserved0_SHIFT 16 /* XPT_XPU :: REG_R8_R9 :: REGISTER [15:00] */ #define BCHP_XPT_XPU_REG_R8_R9_REGISTER_MASK 0x0000ffff #define BCHP_XPT_XPU_REG_R8_R9_REGISTER_SHIFT 0 /*************************************************************************** *REG_R10_R11 - Register pair r10/r11 ***************************************************************************/ /* XPT_XPU :: REG_R10_R11 :: reserved0 [31:16] */ #define BCHP_XPT_XPU_REG_R10_R11_reserved0_MASK 0xffff0000 #define BCHP_XPT_XPU_REG_R10_R11_reserved0_SHIFT 16 /* XPT_XPU :: REG_R10_R11 :: REGISTER [15:00] */ #define BCHP_XPT_XPU_REG_R10_R11_REGISTER_MASK 0x0000ffff #define BCHP_XPT_XPU_REG_R10_R11_REGISTER_SHIFT 0 /*************************************************************************** *REG_R12_R13 - Register pair r12/r13 ***************************************************************************/ /* XPT_XPU :: REG_R12_R13 :: reserved0 [31:16] */ #define BCHP_XPT_XPU_REG_R12_R13_reserved0_MASK 0xffff0000 #define BCHP_XPT_XPU_REG_R12_R13_reserved0_SHIFT 16 /* XPT_XPU :: REG_R12_R13 :: REGISTER [15:00] */ #define BCHP_XPT_XPU_REG_R12_R13_REGISTER_MASK 0x0000ffff #define BCHP_XPT_XPU_REG_R12_R13_REGISTER_SHIFT 0 /*************************************************************************** *REG_R14_R15 - Register pair r14/r15 ***************************************************************************/ /* XPT_XPU :: REG_R14_R15 :: reserved0 [31:16] */ #define BCHP_XPT_XPU_REG_R14_R15_reserved0_MASK 0xffff0000 #define BCHP_XPT_XPU_REG_R14_R15_reserved0_SHIFT 16 /* XPT_XPU :: REG_R14_R15 :: REGISTER [15:00] */ #define BCHP_XPT_XPU_REG_R14_R15_REGISTER_MASK 0x0000ffff #define BCHP_XPT_XPU_REG_R14_R15_REGISTER_SHIFT 0 /*************************************************************************** *IMEM%i - Instruction memory address 0..2047 ***************************************************************************/ #define BCHP_XPT_XPU_IMEMi_ARRAY_BASE 0x00220800 #define BCHP_XPT_XPU_IMEMi_ARRAY_START 0 #define BCHP_XPT_XPU_IMEMi_ARRAY_END 2047 #define BCHP_XPT_XPU_IMEMi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *IMEM%i - Instruction memory address 0..2047 ***************************************************************************/ /* XPT_XPU :: IMEMi :: reserved0 [31:22] */ #define BCHP_XPT_XPU_IMEMi_reserved0_MASK 0xffc00000 #define BCHP_XPT_XPU_IMEMi_reserved0_SHIFT 22 /* XPT_XPU :: IMEMi :: INSTRUCTION [21:00] */ #define BCHP_XPT_XPU_IMEMi_INSTRUCTION_MASK 0x003fffff #define BCHP_XPT_XPU_IMEMi_INSTRUCTION_SHIFT 0 #endif /* #ifndef BCHP_XPT_XPU_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015000000000000011561 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_l1_intr.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_l1_int0000644000175000017500000004610111610313111030726 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_l1_intr.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:10p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:52 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_l1_intr.h $ * * Hydra_Software_Devel/1 7/17/09 8:10p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_L1_INTR_H__ #define BCHP_L1_INTR_H__ /*************************************************************************** *L1_INTR - TGT L1 Interrupt Controller Registers (feeds into L2 above) ***************************************************************************/ #define BCHP_L1_INTR_INTR_W0_STATUS 0x00500740 /* Interrupt Status Register */ #define BCHP_L1_INTR_INTR_W1_STATUS 0x00500744 /* Interrupt Status Register */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS 0x00500748 /* Interrupt Mask Status Register */ #define BCHP_L1_INTR_INTR_W1_MASK_STATUS 0x0050074c /* Interrupt Mask Status Register */ #define BCHP_L1_INTR_INTR_W0_MASK_SET 0x00500750 /* Interrupt Mask Set Register */ #define BCHP_L1_INTR_INTR_W1_MASK_SET 0x00500754 /* Interrupt Mask Set Register */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR 0x00500758 /* Interrupt Mask Clear Register */ #define BCHP_L1_INTR_INTR_W1_MASK_CLEAR 0x0050075c /* Interrupt Mask Clear Register */ /*************************************************************************** *INTR_W0_STATUS - Interrupt Status Register ***************************************************************************/ /* L1_INTR :: INTR_W0_STATUS :: reserved0 [31:16] */ #define BCHP_L1_INTR_INTR_W0_STATUS_reserved0_MASK 0xffff0000 #define BCHP_L1_INTR_INTR_W0_STATUS_reserved0_SHIFT 16 /* L1_INTR :: INTR_W0_STATUS :: BVN_INTR [15:15] */ #define BCHP_L1_INTR_INTR_W0_STATUS_BVN_INTR_MASK 0x00008000 #define BCHP_L1_INTR_INTR_W0_STATUS_BVN_INTR_SHIFT 15 /* L1_INTR :: INTR_W0_STATUS :: BLINK_INTR [14:14] */ #define BCHP_L1_INTR_INTR_W0_STATUS_BLINK_INTR_MASK 0x00004000 #define BCHP_L1_INTR_INTR_W0_STATUS_BLINK_INTR_SHIFT 14 /* L1_INTR :: INTR_W0_STATUS :: SECURE_INTR [13:13] */ #define BCHP_L1_INTR_INTR_W0_STATUS_SECURE_INTR_MASK 0x00002000 #define BCHP_L1_INTR_INTR_W0_STATUS_SECURE_INTR_SHIFT 13 /* L1_INTR :: INTR_W0_STATUS :: ARB_RTS_INTR [12:12] */ #define BCHP_L1_INTR_INTR_W0_STATUS_ARB_RTS_INTR_MASK 0x00001000 #define BCHP_L1_INTR_INTR_W0_STATUS_ARB_RTS_INTR_SHIFT 12 /* L1_INTR :: INTR_W0_STATUS :: ARB_CRIT_INTR [11:11] */ #define BCHP_L1_INTR_INTR_W0_STATUS_ARB_CRIT_INTR_MASK 0x00000800 #define BCHP_L1_INTR_INTR_W0_STATUS_ARB_CRIT_INTR_SHIFT 11 /* L1_INTR :: INTR_W0_STATUS :: ARB_ARCH_INTR [10:10] */ #define BCHP_L1_INTR_INTR_W0_STATUS_ARB_ARCH_INTR_MASK 0x00000400 #define BCHP_L1_INTR_INTR_W0_STATUS_ARB_ARCH_INTR_SHIFT 10 /* L1_INTR :: INTR_W0_STATUS :: ARB_MEM_INTR [09:09] */ #define BCHP_L1_INTR_INTR_W0_STATUS_ARB_MEM_INTR_MASK 0x00000200 #define BCHP_L1_INTR_INTR_W0_STATUS_ARB_MEM_INTR_SHIFT 9 /* L1_INTR :: INTR_W0_STATUS :: UPG_MAIN_INTR [08:08] */ #define BCHP_L1_INTR_INTR_W0_STATUS_UPG_MAIN_INTR_MASK 0x00000100 #define BCHP_L1_INTR_INTR_W0_STATUS_UPG_MAIN_INTR_SHIFT 8 /* L1_INTR :: INTR_W0_STATUS :: UPG_TMR_INTR [07:07] */ #define BCHP_L1_INTR_INTR_W0_STATUS_UPG_TMR_INTR_MASK 0x00000080 #define BCHP_L1_INTR_INTR_W0_STATUS_UPG_TMR_INTR_SHIFT 7 /* L1_INTR :: INTR_W0_STATUS :: SUN_INTR [06:06] */ #define BCHP_L1_INTR_INTR_W0_STATUS_SUN_INTR_MASK 0x00000040 #define BCHP_L1_INTR_INTR_W0_STATUS_SUN_INTR_SHIFT 6 /* L1_INTR :: INTR_W0_STATUS :: AVD_INTR [05:05] */ #define BCHP_L1_INTR_INTR_W0_STATUS_AVD_INTR_MASK 0x00000020 #define BCHP_L1_INTR_INTR_W0_STATUS_AVD_INTR_SHIFT 5 /* L1_INTR :: INTR_W0_STATUS :: XPT_STATUS_INTR [04:04] */ #define BCHP_L1_INTR_INTR_W0_STATUS_XPT_STATUS_INTR_MASK 0x00000010 #define BCHP_L1_INTR_INTR_W0_STATUS_XPT_STATUS_INTR_SHIFT 4 /* L1_INTR :: INTR_W0_STATUS :: XPT_PCR_INTR [03:03] */ #define BCHP_L1_INTR_INTR_W0_STATUS_XPT_PCR_INTR_MASK 0x00000008 #define BCHP_L1_INTR_INTR_W0_STATUS_XPT_PCR_INTR_SHIFT 3 /* L1_INTR :: INTR_W0_STATUS :: XPT_FE_INTR [02:02] */ #define BCHP_L1_INTR_INTR_W0_STATUS_XPT_FE_INTR_MASK 0x00000004 #define BCHP_L1_INTR_INTR_W0_STATUS_XPT_FE_INTR_SHIFT 2 /* L1_INTR :: INTR_W0_STATUS :: XPT_RAV_INTR [01:01] */ #define BCHP_L1_INTR_INTR_W0_STATUS_XPT_RAV_INTR_MASK 0x00000002 #define BCHP_L1_INTR_INTR_W0_STATUS_XPT_RAV_INTR_SHIFT 1 /* L1_INTR :: INTR_W0_STATUS :: WRAP_MISC_INTR [00:00] */ #define BCHP_L1_INTR_INTR_W0_STATUS_WRAP_MISC_INTR_MASK 0x00000001 #define BCHP_L1_INTR_INTR_W0_STATUS_WRAP_MISC_INTR_SHIFT 0 /*************************************************************************** *INTR_W1_STATUS - Interrupt Status Register ***************************************************************************/ /* L1_INTR :: INTR_W1_STATUS :: reserved0 [31:00] */ #define BCHP_L1_INTR_INTR_W1_STATUS_reserved0_MASK 0xffffffff #define BCHP_L1_INTR_INTR_W1_STATUS_reserved0_SHIFT 0 /*************************************************************************** *INTR_W0_MASK_STATUS - Interrupt Mask Status Register ***************************************************************************/ /* L1_INTR :: INTR_W0_MASK_STATUS :: reserved0 [31:16] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_reserved0_MASK 0xffff0000 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_reserved0_SHIFT 16 /* L1_INTR :: INTR_W0_MASK_STATUS :: BVN_MASK [15:15] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_BVN_MASK_MASK 0x00008000 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_BVN_MASK_SHIFT 15 /* L1_INTR :: INTR_W0_MASK_STATUS :: BLINK_MASK [14:14] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_BLINK_MASK_MASK 0x00004000 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_BLINK_MASK_SHIFT 14 /* L1_INTR :: INTR_W0_MASK_STATUS :: SECURE_MASK [13:13] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_SECURE_MASK_MASK 0x00002000 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_SECURE_MASK_SHIFT 13 /* L1_INTR :: INTR_W0_MASK_STATUS :: ARB_RTS_MASK [12:12] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_RTS_MASK_MASK 0x00001000 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_RTS_MASK_SHIFT 12 /* L1_INTR :: INTR_W0_MASK_STATUS :: ARB_CRIT_MASK [11:11] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_CRIT_MASK_MASK 0x00000800 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_CRIT_MASK_SHIFT 11 /* L1_INTR :: INTR_W0_MASK_STATUS :: ARB_ARCH_MASK [10:10] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_ARCH_MASK_MASK 0x00000400 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_ARCH_MASK_SHIFT 10 /* L1_INTR :: INTR_W0_MASK_STATUS :: ARB_MEM_MASK [09:09] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_MEM_MASK_MASK 0x00000200 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_ARB_MEM_MASK_SHIFT 9 /* L1_INTR :: INTR_W0_MASK_STATUS :: UPG_MAIN_MASK [08:08] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_UPG_MAIN_MASK_MASK 0x00000100 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_UPG_MAIN_MASK_SHIFT 8 /* L1_INTR :: INTR_W0_MASK_STATUS :: UPG_TMR_MASK [07:07] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_UPG_TMR_MASK_MASK 0x00000080 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_UPG_TMR_MASK_SHIFT 7 /* L1_INTR :: INTR_W0_MASK_STATUS :: SUN_MASK [06:06] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_SUN_MASK_MASK 0x00000040 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_SUN_MASK_SHIFT 6 /* L1_INTR :: INTR_W0_MASK_STATUS :: AVD_MASK [05:05] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_AVD_MASK_MASK 0x00000020 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_AVD_MASK_SHIFT 5 /* L1_INTR :: INTR_W0_MASK_STATUS :: XPT_STATUS_MASK [04:04] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_STATUS_MASK_MASK 0x00000010 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_STATUS_MASK_SHIFT 4 /* L1_INTR :: INTR_W0_MASK_STATUS :: XPT_PCR_MASK [03:03] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_PCR_MASK_MASK 0x00000008 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_PCR_MASK_SHIFT 3 /* L1_INTR :: INTR_W0_MASK_STATUS :: XPT_FE_MASK [02:02] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_FE_MASK_MASK 0x00000004 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_FE_MASK_SHIFT 2 /* L1_INTR :: INTR_W0_MASK_STATUS :: XPT_RAV_MASK [01:01] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_RAV_MASK_MASK 0x00000002 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_XPT_RAV_MASK_SHIFT 1 /* L1_INTR :: INTR_W0_MASK_STATUS :: WRAP_MISC_MASK [00:00] */ #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_WRAP_MISC_MASK_MASK 0x00000001 #define BCHP_L1_INTR_INTR_W0_MASK_STATUS_WRAP_MISC_MASK_SHIFT 0 /*************************************************************************** *INTR_W1_MASK_STATUS - Interrupt Mask Status Register ***************************************************************************/ /* L1_INTR :: INTR_W1_MASK_STATUS :: reserved0 [31:00] */ #define BCHP_L1_INTR_INTR_W1_MASK_STATUS_reserved0_MASK 0xffffffff #define BCHP_L1_INTR_INTR_W1_MASK_STATUS_reserved0_SHIFT 0 /*************************************************************************** *INTR_W0_MASK_SET - Interrupt Mask Set Register ***************************************************************************/ /* L1_INTR :: INTR_W0_MASK_SET :: reserved0 [31:16] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_reserved0_MASK 0xffff0000 #define BCHP_L1_INTR_INTR_W0_MASK_SET_reserved0_SHIFT 16 /* L1_INTR :: INTR_W0_MASK_SET :: BVN_MASK [15:15] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_BVN_MASK_MASK 0x00008000 #define BCHP_L1_INTR_INTR_W0_MASK_SET_BVN_MASK_SHIFT 15 /* L1_INTR :: INTR_W0_MASK_SET :: BLINK_MASK [14:14] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_BLINK_MASK_MASK 0x00004000 #define BCHP_L1_INTR_INTR_W0_MASK_SET_BLINK_MASK_SHIFT 14 /* L1_INTR :: INTR_W0_MASK_SET :: SECURE_MASK [13:13] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_SECURE_MASK_MASK 0x00002000 #define BCHP_L1_INTR_INTR_W0_MASK_SET_SECURE_MASK_SHIFT 13 /* L1_INTR :: INTR_W0_MASK_SET :: ARB_RTS_MASK [12:12] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_RTS_MASK_MASK 0x00001000 #define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_RTS_MASK_SHIFT 12 /* L1_INTR :: INTR_W0_MASK_SET :: ARB_CRIT_MASK [11:11] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_CRIT_MASK_MASK 0x00000800 #define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_CRIT_MASK_SHIFT 11 /* L1_INTR :: INTR_W0_MASK_SET :: ARB_ARCH_MASK [10:10] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_ARCH_MASK_MASK 0x00000400 #define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_ARCH_MASK_SHIFT 10 /* L1_INTR :: INTR_W0_MASK_SET :: ARB_MEM_MASK [09:09] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_MEM_MASK_MASK 0x00000200 #define BCHP_L1_INTR_INTR_W0_MASK_SET_ARB_MEM_MASK_SHIFT 9 /* L1_INTR :: INTR_W0_MASK_SET :: UPG_MAIN_MASK [08:08] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_UPG_MAIN_MASK_MASK 0x00000100 #define BCHP_L1_INTR_INTR_W0_MASK_SET_UPG_MAIN_MASK_SHIFT 8 /* L1_INTR :: INTR_W0_MASK_SET :: UPG_TMR_MASK [07:07] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_UPG_TMR_MASK_MASK 0x00000080 #define BCHP_L1_INTR_INTR_W0_MASK_SET_UPG_TMR_MASK_SHIFT 7 /* L1_INTR :: INTR_W0_MASK_SET :: SUN_MASK [06:06] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_SUN_MASK_MASK 0x00000040 #define BCHP_L1_INTR_INTR_W0_MASK_SET_SUN_MASK_SHIFT 6 /* L1_INTR :: INTR_W0_MASK_SET :: AVD_MASK [05:05] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_AVD_MASK_MASK 0x00000020 #define BCHP_L1_INTR_INTR_W0_MASK_SET_AVD_MASK_SHIFT 5 /* L1_INTR :: INTR_W0_MASK_SET :: XPT_STATUS_MASK [04:04] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_STATUS_MASK_MASK 0x00000010 #define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_STATUS_MASK_SHIFT 4 /* L1_INTR :: INTR_W0_MASK_SET :: XPT_PCR_MASK [03:03] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_PCR_MASK_MASK 0x00000008 #define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_PCR_MASK_SHIFT 3 /* L1_INTR :: INTR_W0_MASK_SET :: XPT_FE_MASK [02:02] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_FE_MASK_MASK 0x00000004 #define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_FE_MASK_SHIFT 2 /* L1_INTR :: INTR_W0_MASK_SET :: XPT_RAV_MASK [01:01] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_RAV_MASK_MASK 0x00000002 #define BCHP_L1_INTR_INTR_W0_MASK_SET_XPT_RAV_MASK_SHIFT 1 /* L1_INTR :: INTR_W0_MASK_SET :: WRAP_MISC_MASK [00:00] */ #define BCHP_L1_INTR_INTR_W0_MASK_SET_WRAP_MISC_MASK_MASK 0x00000001 #define BCHP_L1_INTR_INTR_W0_MASK_SET_WRAP_MISC_MASK_SHIFT 0 /*************************************************************************** *INTR_W1_MASK_SET - Interrupt Mask Set Register ***************************************************************************/ /* L1_INTR :: INTR_W1_MASK_SET :: reserved0 [31:00] */ #define BCHP_L1_INTR_INTR_W1_MASK_SET_reserved0_MASK 0xffffffff #define BCHP_L1_INTR_INTR_W1_MASK_SET_reserved0_SHIFT 0 /*************************************************************************** *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register ***************************************************************************/ /* L1_INTR :: INTR_W0_MASK_CLEAR :: reserved0 [31:16] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_reserved0_MASK 0xffff0000 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_reserved0_SHIFT 16 /* L1_INTR :: INTR_W0_MASK_CLEAR :: BVN_MASK [15:15] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_BVN_MASK_MASK 0x00008000 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_BVN_MASK_SHIFT 15 /* L1_INTR :: INTR_W0_MASK_CLEAR :: BLINK_MASK [14:14] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_BLINK_MASK_MASK 0x00004000 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_BLINK_MASK_SHIFT 14 /* L1_INTR :: INTR_W0_MASK_CLEAR :: SECURE_MASK [13:13] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_SECURE_MASK_MASK 0x00002000 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_SECURE_MASK_SHIFT 13 /* L1_INTR :: INTR_W0_MASK_CLEAR :: ARB_RTS_MASK [12:12] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_RTS_MASK_MASK 0x00001000 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_RTS_MASK_SHIFT 12 /* L1_INTR :: INTR_W0_MASK_CLEAR :: ARB_CRIT_MASK [11:11] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_CRIT_MASK_MASK 0x00000800 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_CRIT_MASK_SHIFT 11 /* L1_INTR :: INTR_W0_MASK_CLEAR :: ARB_ARCH_MASK [10:10] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_ARCH_MASK_MASK 0x00000400 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_ARCH_MASK_SHIFT 10 /* L1_INTR :: INTR_W0_MASK_CLEAR :: ARB_MEM_MASK [09:09] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_MEM_MASK_MASK 0x00000200 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_ARB_MEM_MASK_SHIFT 9 /* L1_INTR :: INTR_W0_MASK_CLEAR :: UPG_MAIN_MASK [08:08] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_UPG_MAIN_MASK_MASK 0x00000100 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_UPG_MAIN_MASK_SHIFT 8 /* L1_INTR :: INTR_W0_MASK_CLEAR :: UPG_TMR_MASK [07:07] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_UPG_TMR_MASK_MASK 0x00000080 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_UPG_TMR_MASK_SHIFT 7 /* L1_INTR :: INTR_W0_MASK_CLEAR :: SUN_MASK [06:06] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_SUN_MASK_MASK 0x00000040 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_SUN_MASK_SHIFT 6 /* L1_INTR :: INTR_W0_MASK_CLEAR :: AVD_MASK [05:05] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_AVD_MASK_MASK 0x00000020 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_AVD_MASK_SHIFT 5 /* L1_INTR :: INTR_W0_MASK_CLEAR :: XPT_STATUS_MASK [04:04] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_STATUS_MASK_MASK 0x00000010 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_STATUS_MASK_SHIFT 4 /* L1_INTR :: INTR_W0_MASK_CLEAR :: XPT_PCR_MASK [03:03] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_PCR_MASK_MASK 0x00000008 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_PCR_MASK_SHIFT 3 /* L1_INTR :: INTR_W0_MASK_CLEAR :: XPT_FE_MASK [02:02] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_FE_MASK_MASK 0x00000004 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_FE_MASK_SHIFT 2 /* L1_INTR :: INTR_W0_MASK_CLEAR :: XPT_RAV_MASK [01:01] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_RAV_MASK_MASK 0x00000002 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_XPT_RAV_MASK_SHIFT 1 /* L1_INTR :: INTR_W0_MASK_CLEAR :: WRAP_MISC_MASK [00:00] */ #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_WRAP_MISC_MASK_MASK 0x00000001 #define BCHP_L1_INTR_INTR_W0_MASK_CLEAR_WRAP_MISC_MASK_SHIFT 0 /*************************************************************************** *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register ***************************************************************************/ /* L1_INTR :: INTR_W1_MASK_CLEAR :: reserved0 [31:00] */ #define BCHP_L1_INTR_INTR_W1_MASK_CLEAR_reserved0_MASK 0xffffffff #define BCHP_L1_INTR_INTR_W1_MASK_CLEAR_reserved0_SHIFT 0 #endif /* #ifndef BCHP_L1_INTR_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016300000000000011565 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_1.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_cr0000644000175000017500000016534711610313111031034 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_crit_l2_regs_1.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:16p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:24 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_1.h $ * * Hydra_Software_Devel/1 7/17/09 8:16p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_CRIT_L2_REGS_1_H__ #define BCHP_PRI_CRIT_L2_REGS_1_H__ /*************************************************************************** *PRI_CRIT_L2_REGS_1 - PRIMARY_ARB_CLIENTS L2 (Mips) critical interrupt controller 1 registers ***************************************************************************/ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS 0x0040c400 /* CPU interrupt Status Register */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET 0x0040c404 /* CPU interrupt Set Register */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR 0x0040c408 /* CPU interrupt Clear Register */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS 0x0040c40c /* CPU interrupt Mask Status Register */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET 0x0040c410 /* CPU interrupt Mask Set Register */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR 0x0040c414 /* CPU interrupt Mask Clear Register */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS 0x0040c418 /* PCI interrupt Status Register */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET 0x0040c41c /* PCI interrupt Set Register */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR 0x0040c420 /* PCI interrupt Clear Register */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS 0x0040c424 /* PCI interrupt Mask Status Register */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET 0x0040c428 /* PCI interrupt Mask Set Register */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR 0x0040c42c /* PCI interrupt Mask Clear Register */ /*************************************************************************** *CPU_STATUS - CPU interrupt Status Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: reserved0 [31:20] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_reserved0_MASK 0xfff00000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_reserved0_SHIFT 20 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_19_INTR [19:19] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_19_INTR_MASK 0x00080000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_19_INTR_SHIFT 19 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_18_INTR [18:18] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_18_INTR_MASK 0x00040000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_18_INTR_SHIFT 18 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_17_INTR [17:17] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_17_INTR_MASK 0x00020000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_17_INTR_SHIFT 17 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_16_INTR [16:16] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_16_INTR_MASK 0x00010000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_16_INTR_SHIFT 16 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_15_INTR [15:15] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_15_INTR_MASK 0x00008000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_15_INTR_SHIFT 15 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_14_INTR [14:14] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_14_INTR_MASK 0x00004000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_14_INTR_SHIFT 14 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_13_INTR [13:13] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_13_INTR_MASK 0x00002000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_13_INTR_SHIFT 13 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_12_INTR [12:12] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_12_INTR_MASK 0x00001000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_12_INTR_SHIFT 12 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_11_INTR [11:11] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_11_INTR_MASK 0x00000800 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_11_INTR_SHIFT 11 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_10_INTR [10:10] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_10_INTR_MASK 0x00000400 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_10_INTR_SHIFT 10 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_09_INTR [09:09] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_09_INTR_MASK 0x00000200 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_09_INTR_SHIFT 9 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_08_INTR [08:08] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_08_INTR_MASK 0x00000100 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_08_INTR_SHIFT 8 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_07_INTR [07:07] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_07_INTR_MASK 0x00000080 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_07_INTR_SHIFT 7 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_06_INTR [06:06] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_06_INTR_MASK 0x00000040 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_06_INTR_SHIFT 6 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_05_INTR [05:05] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_05_INTR_MASK 0x00000020 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_05_INTR_SHIFT 5 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_04_INTR [04:04] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_04_INTR_MASK 0x00000010 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_04_INTR_SHIFT 4 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_03_INTR [03:03] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_03_INTR_MASK 0x00000008 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_03_INTR_SHIFT 3 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_02_INTR [02:02] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_02_INTR_MASK 0x00000004 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_02_INTR_SHIFT 2 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_01_INTR [01:01] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_01_INTR_MASK 0x00000002 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_01_INTR_SHIFT 1 /* PRI_CRIT_L2_REGS_1 :: CPU_STATUS :: CLIENT_00_INTR [00:00] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_00_INTR_MASK 0x00000001 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_STATUS_CLIENT_00_INTR_SHIFT 0 /*************************************************************************** *CPU_SET - CPU interrupt Set Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: reserved0 [31:20] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_reserved0_MASK 0xfff00000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_reserved0_SHIFT 20 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_19_INTR [19:19] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_19_INTR_MASK 0x00080000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_19_INTR_SHIFT 19 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_18_INTR [18:18] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_18_INTR_MASK 0x00040000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_18_INTR_SHIFT 18 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_17_INTR [17:17] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_17_INTR_MASK 0x00020000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_17_INTR_SHIFT 17 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_16_INTR [16:16] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_16_INTR_MASK 0x00010000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_16_INTR_SHIFT 16 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_15_INTR [15:15] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_15_INTR_MASK 0x00008000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_15_INTR_SHIFT 15 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_14_INTR [14:14] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_14_INTR_MASK 0x00004000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_14_INTR_SHIFT 14 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_13_INTR [13:13] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_13_INTR_MASK 0x00002000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_13_INTR_SHIFT 13 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_12_INTR [12:12] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_12_INTR_MASK 0x00001000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_12_INTR_SHIFT 12 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_11_INTR [11:11] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_11_INTR_MASK 0x00000800 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_11_INTR_SHIFT 11 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_10_INTR [10:10] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_10_INTR_MASK 0x00000400 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_10_INTR_SHIFT 10 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_09_INTR [09:09] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_09_INTR_MASK 0x00000200 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_09_INTR_SHIFT 9 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_08_INTR [08:08] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_08_INTR_MASK 0x00000100 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_08_INTR_SHIFT 8 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_07_INTR [07:07] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_07_INTR_MASK 0x00000080 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_07_INTR_SHIFT 7 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_06_INTR [06:06] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_06_INTR_MASK 0x00000040 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_06_INTR_SHIFT 6 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_05_INTR [05:05] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_05_INTR_MASK 0x00000020 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_05_INTR_SHIFT 5 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_04_INTR [04:04] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_04_INTR_MASK 0x00000010 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_04_INTR_SHIFT 4 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_03_INTR [03:03] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_03_INTR_MASK 0x00000008 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_03_INTR_SHIFT 3 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_02_INTR [02:02] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_02_INTR_MASK 0x00000004 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_02_INTR_SHIFT 2 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_01_INTR [01:01] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_01_INTR_MASK 0x00000002 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_01_INTR_SHIFT 1 /* PRI_CRIT_L2_REGS_1 :: CPU_SET :: CLIENT_00_INTR [00:00] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_00_INTR_MASK 0x00000001 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_SET_CLIENT_00_INTR_SHIFT 0 /*************************************************************************** *CPU_CLEAR - CPU interrupt Clear Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: reserved0 [31:20] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_reserved0_MASK 0xfff00000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_reserved0_SHIFT 20 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_19_INTR [19:19] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_19_INTR_MASK 0x00080000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_19_INTR_SHIFT 19 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_18_INTR [18:18] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_18_INTR_MASK 0x00040000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_18_INTR_SHIFT 18 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_17_INTR [17:17] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_17_INTR_MASK 0x00020000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_17_INTR_SHIFT 17 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_16_INTR [16:16] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_16_INTR_MASK 0x00010000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_16_INTR_SHIFT 16 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_15_INTR [15:15] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_15_INTR_MASK 0x00008000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_15_INTR_SHIFT 15 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_14_INTR [14:14] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_14_INTR_MASK 0x00004000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_14_INTR_SHIFT 14 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_13_INTR [13:13] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_13_INTR_MASK 0x00002000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_13_INTR_SHIFT 13 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_12_INTR [12:12] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_12_INTR_MASK 0x00001000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_12_INTR_SHIFT 12 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_11_INTR [11:11] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_11_INTR_MASK 0x00000800 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_11_INTR_SHIFT 11 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_10_INTR [10:10] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_10_INTR_MASK 0x00000400 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_10_INTR_SHIFT 10 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_09_INTR [09:09] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_09_INTR_MASK 0x00000200 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_09_INTR_SHIFT 9 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_08_INTR [08:08] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_08_INTR_MASK 0x00000100 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_08_INTR_SHIFT 8 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_07_INTR [07:07] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_07_INTR_MASK 0x00000080 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_07_INTR_SHIFT 7 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_06_INTR [06:06] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_06_INTR_MASK 0x00000040 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_06_INTR_SHIFT 6 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_05_INTR [05:05] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_05_INTR_MASK 0x00000020 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_05_INTR_SHIFT 5 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_04_INTR [04:04] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_04_INTR_MASK 0x00000010 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_04_INTR_SHIFT 4 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_03_INTR [03:03] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_03_INTR_MASK 0x00000008 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_03_INTR_SHIFT 3 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_02_INTR [02:02] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_02_INTR_MASK 0x00000004 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_02_INTR_SHIFT 2 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_01_INTR [01:01] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_01_INTR_MASK 0x00000002 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_01_INTR_SHIFT 1 /* PRI_CRIT_L2_REGS_1 :: CPU_CLEAR :: CLIENT_00_INTR [00:00] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_00_INTR_MASK 0x00000001 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_CLEAR_CLIENT_00_INTR_SHIFT 0 /*************************************************************************** *CPU_MASK_STATUS - CPU interrupt Mask Status Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: reserved0 [31:20] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_reserved0_MASK 0xfff00000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_reserved0_SHIFT 20 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_19_MASK [19:19] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_19_MASK_MASK 0x00080000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_19_MASK_SHIFT 19 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_18_MASK [18:18] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_18_MASK_MASK 0x00040000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_18_MASK_SHIFT 18 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_17_MASK [17:17] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_17_MASK_MASK 0x00020000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_17_MASK_SHIFT 17 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_16_MASK [16:16] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_16_MASK_MASK 0x00010000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_16_MASK_SHIFT 16 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_15_MASK [15:15] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_15_MASK_MASK 0x00008000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_15_MASK_SHIFT 15 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_14_MASK [14:14] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_14_MASK_MASK 0x00004000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_14_MASK_SHIFT 14 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_13_MASK [13:13] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_13_MASK_MASK 0x00002000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_13_MASK_SHIFT 13 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_12_MASK [12:12] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_12_MASK_MASK 0x00001000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_12_MASK_SHIFT 12 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_11_MASK [11:11] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_11_MASK_MASK 0x00000800 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_11_MASK_SHIFT 11 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_10_MASK [10:10] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_10_MASK_MASK 0x00000400 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_10_MASK_SHIFT 10 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_09_MASK [09:09] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_09_MASK_MASK 0x00000200 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_09_MASK_SHIFT 9 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_08_MASK [08:08] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_08_MASK_MASK 0x00000100 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_08_MASK_SHIFT 8 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_07_MASK [07:07] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_07_MASK_MASK 0x00000080 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_07_MASK_SHIFT 7 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_06_MASK [06:06] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_06_MASK_MASK 0x00000040 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_06_MASK_SHIFT 6 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_05_MASK [05:05] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_05_MASK_MASK 0x00000020 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_05_MASK_SHIFT 5 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_04_MASK [04:04] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_04_MASK_MASK 0x00000010 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_04_MASK_SHIFT 4 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_03_MASK [03:03] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_03_MASK_MASK 0x00000008 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_03_MASK_SHIFT 3 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_02_MASK [02:02] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_02_MASK_MASK 0x00000004 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_02_MASK_SHIFT 2 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_01_MASK [01:01] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_01_MASK_MASK 0x00000002 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_01_MASK_SHIFT 1 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_STATUS :: CLIENT_00_MASK [00:00] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_00_MASK_MASK 0x00000001 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_STATUS_CLIENT_00_MASK_SHIFT 0 /*************************************************************************** *CPU_MASK_SET - CPU interrupt Mask Set Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: reserved0 [31:20] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_reserved0_MASK 0xfff00000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_reserved0_SHIFT 20 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_19_MASK [19:19] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_19_MASK_MASK 0x00080000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_19_MASK_SHIFT 19 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_18_MASK [18:18] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_18_MASK_MASK 0x00040000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_18_MASK_SHIFT 18 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_17_MASK [17:17] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_17_MASK_MASK 0x00020000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_17_MASK_SHIFT 17 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_16_MASK [16:16] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_16_MASK_MASK 0x00010000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_16_MASK_SHIFT 16 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_15_MASK [15:15] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_15_MASK_MASK 0x00008000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_15_MASK_SHIFT 15 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_14_MASK [14:14] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_14_MASK_MASK 0x00004000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_14_MASK_SHIFT 14 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_13_MASK [13:13] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_13_MASK_MASK 0x00002000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_13_MASK_SHIFT 13 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_12_MASK [12:12] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_12_MASK_MASK 0x00001000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_12_MASK_SHIFT 12 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_11_MASK [11:11] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_11_MASK_MASK 0x00000800 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_11_MASK_SHIFT 11 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_10_MASK [10:10] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_10_MASK_MASK 0x00000400 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_10_MASK_SHIFT 10 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_09_MASK [09:09] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_09_MASK_MASK 0x00000200 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_09_MASK_SHIFT 9 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_08_MASK [08:08] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_08_MASK_MASK 0x00000100 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_08_MASK_SHIFT 8 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_07_MASK [07:07] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_07_MASK_MASK 0x00000080 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_07_MASK_SHIFT 7 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_06_MASK [06:06] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_06_MASK_MASK 0x00000040 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_06_MASK_SHIFT 6 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_05_MASK [05:05] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_05_MASK_MASK 0x00000020 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_05_MASK_SHIFT 5 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_04_MASK [04:04] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_04_MASK_MASK 0x00000010 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_04_MASK_SHIFT 4 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_03_MASK [03:03] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_03_MASK_MASK 0x00000008 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_03_MASK_SHIFT 3 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_02_MASK [02:02] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_02_MASK_MASK 0x00000004 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_02_MASK_SHIFT 2 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_01_MASK [01:01] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_01_MASK_MASK 0x00000002 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_01_MASK_SHIFT 1 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_SET :: CLIENT_00_MASK [00:00] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_00_MASK_MASK 0x00000001 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_SET_CLIENT_00_MASK_SHIFT 0 /*************************************************************************** *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: reserved0 [31:20] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_reserved0_MASK 0xfff00000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_reserved0_SHIFT 20 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_19_MASK [19:19] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_19_MASK_MASK 0x00080000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_19_MASK_SHIFT 19 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_18_MASK [18:18] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_18_MASK_MASK 0x00040000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_18_MASK_SHIFT 18 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_17_MASK [17:17] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_17_MASK_MASK 0x00020000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_17_MASK_SHIFT 17 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_16_MASK [16:16] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_16_MASK_MASK 0x00010000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_16_MASK_SHIFT 16 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_15_MASK [15:15] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_15_MASK_MASK 0x00008000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_15_MASK_SHIFT 15 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_14_MASK [14:14] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_14_MASK_MASK 0x00004000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_14_MASK_SHIFT 14 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_13_MASK [13:13] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_13_MASK_MASK 0x00002000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_13_MASK_SHIFT 13 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_12_MASK [12:12] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_12_MASK_MASK 0x00001000 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_12_MASK_SHIFT 12 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_11_MASK [11:11] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_11_MASK_MASK 0x00000800 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_11_MASK_SHIFT 11 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_10_MASK [10:10] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_10_MASK_MASK 0x00000400 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_10_MASK_SHIFT 10 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_09_MASK [09:09] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_09_MASK_MASK 0x00000200 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_09_MASK_SHIFT 9 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_08_MASK [08:08] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_08_MASK_MASK 0x00000100 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_08_MASK_SHIFT 8 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_07_MASK [07:07] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_07_MASK_MASK 0x00000080 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_07_MASK_SHIFT 7 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_06_MASK [06:06] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_06_MASK_MASK 0x00000040 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_06_MASK_SHIFT 6 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_05_MASK [05:05] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_05_MASK_MASK 0x00000020 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_05_MASK_SHIFT 5 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_04_MASK [04:04] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_04_MASK_MASK 0x00000010 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_04_MASK_SHIFT 4 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_03_MASK [03:03] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_03_MASK_MASK 0x00000008 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_03_MASK_SHIFT 3 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_02_MASK [02:02] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_02_MASK_MASK 0x00000004 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_02_MASK_SHIFT 2 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_01_MASK [01:01] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_01_MASK_MASK 0x00000002 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_01_MASK_SHIFT 1 /* PRI_CRIT_L2_REGS_1 :: CPU_MASK_CLEAR :: CLIENT_00_MASK [00:00] */ #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_00_MASK_MASK 0x00000001 #define BCHP_PRI_CRIT_L2_REGS_1_CPU_MASK_CLEAR_CLIENT_00_MASK_SHIFT 0 /*************************************************************************** *PCI_STATUS - PCI interrupt Status Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: reserved0 [31:20] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_reserved0_MASK 0xfff00000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_reserved0_SHIFT 20 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_19_INTR [19:19] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_19_INTR_MASK 0x00080000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_19_INTR_SHIFT 19 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_18_INTR [18:18] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_18_INTR_MASK 0x00040000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_18_INTR_SHIFT 18 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_17_INTR [17:17] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_17_INTR_MASK 0x00020000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_17_INTR_SHIFT 17 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_16_INTR [16:16] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_16_INTR_MASK 0x00010000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_16_INTR_SHIFT 16 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_15_INTR [15:15] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_15_INTR_MASK 0x00008000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_15_INTR_SHIFT 15 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_14_INTR [14:14] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_14_INTR_MASK 0x00004000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_14_INTR_SHIFT 14 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_13_INTR [13:13] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_13_INTR_MASK 0x00002000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_13_INTR_SHIFT 13 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_12_INTR [12:12] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_12_INTR_MASK 0x00001000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_12_INTR_SHIFT 12 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_11_INTR [11:11] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_11_INTR_MASK 0x00000800 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_11_INTR_SHIFT 11 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_10_INTR [10:10] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_10_INTR_MASK 0x00000400 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_10_INTR_SHIFT 10 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_09_INTR [09:09] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_09_INTR_MASK 0x00000200 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_09_INTR_SHIFT 9 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_08_INTR [08:08] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_08_INTR_MASK 0x00000100 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_08_INTR_SHIFT 8 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_07_INTR [07:07] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_07_INTR_MASK 0x00000080 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_07_INTR_SHIFT 7 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_06_INTR [06:06] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_06_INTR_MASK 0x00000040 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_06_INTR_SHIFT 6 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_05_INTR [05:05] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_05_INTR_MASK 0x00000020 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_05_INTR_SHIFT 5 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_04_INTR [04:04] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_04_INTR_MASK 0x00000010 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_04_INTR_SHIFT 4 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_03_INTR [03:03] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_03_INTR_MASK 0x00000008 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_03_INTR_SHIFT 3 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_02_INTR [02:02] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_02_INTR_MASK 0x00000004 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_02_INTR_SHIFT 2 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_01_INTR [01:01] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_01_INTR_MASK 0x00000002 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_01_INTR_SHIFT 1 /* PRI_CRIT_L2_REGS_1 :: PCI_STATUS :: CLIENT_00_INTR [00:00] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_00_INTR_MASK 0x00000001 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_STATUS_CLIENT_00_INTR_SHIFT 0 /*************************************************************************** *PCI_SET - PCI interrupt Set Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: reserved0 [31:20] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_reserved0_MASK 0xfff00000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_reserved0_SHIFT 20 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_19_INTR [19:19] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_19_INTR_MASK 0x00080000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_19_INTR_SHIFT 19 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_18_INTR [18:18] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_18_INTR_MASK 0x00040000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_18_INTR_SHIFT 18 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_17_INTR [17:17] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_17_INTR_MASK 0x00020000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_17_INTR_SHIFT 17 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_16_INTR [16:16] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_16_INTR_MASK 0x00010000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_16_INTR_SHIFT 16 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_15_INTR [15:15] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_15_INTR_MASK 0x00008000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_15_INTR_SHIFT 15 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_14_INTR [14:14] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_14_INTR_MASK 0x00004000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_14_INTR_SHIFT 14 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_13_INTR [13:13] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_13_INTR_MASK 0x00002000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_13_INTR_SHIFT 13 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_12_INTR [12:12] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_12_INTR_MASK 0x00001000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_12_INTR_SHIFT 12 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_11_INTR [11:11] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_11_INTR_MASK 0x00000800 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_11_INTR_SHIFT 11 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_10_INTR [10:10] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_10_INTR_MASK 0x00000400 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_10_INTR_SHIFT 10 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_09_INTR [09:09] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_09_INTR_MASK 0x00000200 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_09_INTR_SHIFT 9 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_08_INTR [08:08] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_08_INTR_MASK 0x00000100 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_08_INTR_SHIFT 8 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_07_INTR [07:07] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_07_INTR_MASK 0x00000080 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_07_INTR_SHIFT 7 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_06_INTR [06:06] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_06_INTR_MASK 0x00000040 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_06_INTR_SHIFT 6 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_05_INTR [05:05] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_05_INTR_MASK 0x00000020 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_05_INTR_SHIFT 5 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_04_INTR [04:04] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_04_INTR_MASK 0x00000010 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_04_INTR_SHIFT 4 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_03_INTR [03:03] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_03_INTR_MASK 0x00000008 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_03_INTR_SHIFT 3 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_02_INTR [02:02] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_02_INTR_MASK 0x00000004 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_02_INTR_SHIFT 2 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_01_INTR [01:01] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_01_INTR_MASK 0x00000002 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_01_INTR_SHIFT 1 /* PRI_CRIT_L2_REGS_1 :: PCI_SET :: CLIENT_00_INTR [00:00] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_00_INTR_MASK 0x00000001 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_SET_CLIENT_00_INTR_SHIFT 0 /*************************************************************************** *PCI_CLEAR - PCI interrupt Clear Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: reserved0 [31:20] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_reserved0_MASK 0xfff00000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_reserved0_SHIFT 20 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_19_INTR [19:19] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_19_INTR_MASK 0x00080000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_19_INTR_SHIFT 19 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_18_INTR [18:18] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_18_INTR_MASK 0x00040000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_18_INTR_SHIFT 18 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_17_INTR [17:17] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_17_INTR_MASK 0x00020000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_17_INTR_SHIFT 17 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_16_INTR [16:16] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_16_INTR_MASK 0x00010000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_16_INTR_SHIFT 16 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_15_INTR [15:15] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_15_INTR_MASK 0x00008000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_15_INTR_SHIFT 15 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_14_INTR [14:14] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_14_INTR_MASK 0x00004000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_14_INTR_SHIFT 14 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_13_INTR [13:13] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_13_INTR_MASK 0x00002000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_13_INTR_SHIFT 13 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_12_INTR [12:12] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_12_INTR_MASK 0x00001000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_12_INTR_SHIFT 12 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_11_INTR [11:11] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_11_INTR_MASK 0x00000800 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_11_INTR_SHIFT 11 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_10_INTR [10:10] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_10_INTR_MASK 0x00000400 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_10_INTR_SHIFT 10 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_09_INTR [09:09] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_09_INTR_MASK 0x00000200 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_09_INTR_SHIFT 9 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_08_INTR [08:08] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_08_INTR_MASK 0x00000100 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_08_INTR_SHIFT 8 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_07_INTR [07:07] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_07_INTR_MASK 0x00000080 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_07_INTR_SHIFT 7 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_06_INTR [06:06] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_06_INTR_MASK 0x00000040 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_06_INTR_SHIFT 6 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_05_INTR [05:05] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_05_INTR_MASK 0x00000020 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_05_INTR_SHIFT 5 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_04_INTR [04:04] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_04_INTR_MASK 0x00000010 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_04_INTR_SHIFT 4 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_03_INTR [03:03] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_03_INTR_MASK 0x00000008 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_03_INTR_SHIFT 3 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_02_INTR [02:02] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_02_INTR_MASK 0x00000004 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_02_INTR_SHIFT 2 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_01_INTR [01:01] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_01_INTR_MASK 0x00000002 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_01_INTR_SHIFT 1 /* PRI_CRIT_L2_REGS_1 :: PCI_CLEAR :: CLIENT_00_INTR [00:00] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_00_INTR_MASK 0x00000001 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_CLEAR_CLIENT_00_INTR_SHIFT 0 /*************************************************************************** *PCI_MASK_STATUS - PCI interrupt Mask Status Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: reserved0 [31:20] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_reserved0_MASK 0xfff00000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_reserved0_SHIFT 20 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_19_MASK [19:19] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_19_MASK_MASK 0x00080000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_19_MASK_SHIFT 19 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_18_MASK [18:18] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_18_MASK_MASK 0x00040000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_18_MASK_SHIFT 18 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_17_MASK [17:17] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_17_MASK_MASK 0x00020000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_17_MASK_SHIFT 17 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_16_MASK [16:16] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_16_MASK_MASK 0x00010000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_16_MASK_SHIFT 16 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_15_MASK [15:15] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_15_MASK_MASK 0x00008000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_15_MASK_SHIFT 15 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_14_MASK [14:14] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_14_MASK_MASK 0x00004000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_14_MASK_SHIFT 14 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_13_MASK [13:13] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_13_MASK_MASK 0x00002000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_13_MASK_SHIFT 13 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_12_MASK [12:12] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_12_MASK_MASK 0x00001000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_12_MASK_SHIFT 12 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_11_MASK [11:11] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_11_MASK_MASK 0x00000800 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_11_MASK_SHIFT 11 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_10_MASK [10:10] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_10_MASK_MASK 0x00000400 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_10_MASK_SHIFT 10 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_09_MASK [09:09] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_09_MASK_MASK 0x00000200 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_09_MASK_SHIFT 9 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_08_MASK [08:08] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_08_MASK_MASK 0x00000100 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_08_MASK_SHIFT 8 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_07_MASK [07:07] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_07_MASK_MASK 0x00000080 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_07_MASK_SHIFT 7 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_06_MASK [06:06] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_06_MASK_MASK 0x00000040 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_06_MASK_SHIFT 6 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_05_MASK [05:05] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_05_MASK_MASK 0x00000020 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_05_MASK_SHIFT 5 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_04_MASK [04:04] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_04_MASK_MASK 0x00000010 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_04_MASK_SHIFT 4 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_03_MASK [03:03] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_03_MASK_MASK 0x00000008 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_03_MASK_SHIFT 3 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_02_MASK [02:02] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_02_MASK_MASK 0x00000004 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_02_MASK_SHIFT 2 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_01_MASK [01:01] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_01_MASK_MASK 0x00000002 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_01_MASK_SHIFT 1 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_STATUS :: CLIENT_00_MASK [00:00] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_00_MASK_MASK 0x00000001 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_STATUS_CLIENT_00_MASK_SHIFT 0 /*************************************************************************** *PCI_MASK_SET - PCI interrupt Mask Set Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: reserved0 [31:20] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_reserved0_MASK 0xfff00000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_reserved0_SHIFT 20 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_19_MASK [19:19] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_19_MASK_MASK 0x00080000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_19_MASK_SHIFT 19 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_18_MASK [18:18] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_18_MASK_MASK 0x00040000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_18_MASK_SHIFT 18 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_17_MASK [17:17] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_17_MASK_MASK 0x00020000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_17_MASK_SHIFT 17 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_16_MASK [16:16] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_16_MASK_MASK 0x00010000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_16_MASK_SHIFT 16 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_15_MASK [15:15] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_15_MASK_MASK 0x00008000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_15_MASK_SHIFT 15 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_14_MASK [14:14] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_14_MASK_MASK 0x00004000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_14_MASK_SHIFT 14 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_13_MASK [13:13] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_13_MASK_MASK 0x00002000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_13_MASK_SHIFT 13 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_12_MASK [12:12] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_12_MASK_MASK 0x00001000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_12_MASK_SHIFT 12 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_11_MASK [11:11] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_11_MASK_MASK 0x00000800 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_11_MASK_SHIFT 11 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_10_MASK [10:10] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_10_MASK_MASK 0x00000400 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_10_MASK_SHIFT 10 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_09_MASK [09:09] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_09_MASK_MASK 0x00000200 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_09_MASK_SHIFT 9 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_08_MASK [08:08] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_08_MASK_MASK 0x00000100 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_08_MASK_SHIFT 8 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_07_MASK [07:07] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_07_MASK_MASK 0x00000080 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_07_MASK_SHIFT 7 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_06_MASK [06:06] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_06_MASK_MASK 0x00000040 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_06_MASK_SHIFT 6 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_05_MASK [05:05] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_05_MASK_MASK 0x00000020 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_05_MASK_SHIFT 5 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_04_MASK [04:04] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_04_MASK_MASK 0x00000010 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_04_MASK_SHIFT 4 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_03_MASK [03:03] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_03_MASK_MASK 0x00000008 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_03_MASK_SHIFT 3 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_02_MASK [02:02] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_02_MASK_MASK 0x00000004 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_02_MASK_SHIFT 2 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_01_MASK [01:01] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_01_MASK_MASK 0x00000002 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_01_MASK_SHIFT 1 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_SET :: CLIENT_00_MASK [00:00] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_00_MASK_MASK 0x00000001 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_SET_CLIENT_00_MASK_SHIFT 0 /*************************************************************************** *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: reserved0 [31:20] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_reserved0_MASK 0xfff00000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_reserved0_SHIFT 20 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_19_MASK [19:19] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_19_MASK_MASK 0x00080000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_19_MASK_SHIFT 19 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_18_MASK [18:18] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_18_MASK_MASK 0x00040000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_18_MASK_SHIFT 18 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_17_MASK [17:17] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_17_MASK_MASK 0x00020000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_17_MASK_SHIFT 17 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_16_MASK [16:16] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_16_MASK_MASK 0x00010000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_16_MASK_SHIFT 16 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_15_MASK [15:15] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_15_MASK_MASK 0x00008000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_15_MASK_SHIFT 15 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_14_MASK [14:14] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_14_MASK_MASK 0x00004000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_14_MASK_SHIFT 14 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_13_MASK [13:13] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_13_MASK_MASK 0x00002000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_13_MASK_SHIFT 13 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_12_MASK [12:12] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_12_MASK_MASK 0x00001000 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_12_MASK_SHIFT 12 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_11_MASK [11:11] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_11_MASK_MASK 0x00000800 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_11_MASK_SHIFT 11 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_10_MASK [10:10] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_10_MASK_MASK 0x00000400 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_10_MASK_SHIFT 10 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_09_MASK [09:09] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_09_MASK_MASK 0x00000200 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_09_MASK_SHIFT 9 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_08_MASK [08:08] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_08_MASK_MASK 0x00000100 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_08_MASK_SHIFT 8 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_07_MASK [07:07] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_07_MASK_MASK 0x00000080 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_07_MASK_SHIFT 7 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_06_MASK [06:06] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_06_MASK_MASK 0x00000040 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_06_MASK_SHIFT 6 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_05_MASK [05:05] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_05_MASK_MASK 0x00000020 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_05_MASK_SHIFT 5 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_04_MASK [04:04] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_04_MASK_MASK 0x00000010 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_04_MASK_SHIFT 4 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_03_MASK [03:03] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_03_MASK_MASK 0x00000008 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_03_MASK_SHIFT 3 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_02_MASK [02:02] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_02_MASK_MASK 0x00000004 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_02_MASK_SHIFT 2 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_01_MASK [01:01] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_01_MASK_MASK 0x00000002 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_01_MASK_SHIFT 1 /* PRI_CRIT_L2_REGS_1 :: PCI_MASK_CLEAR :: CLIENT_00_MASK [00:00] */ #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_00_MASK_MASK 0x00000001 #define BCHP_PRI_CRIT_L2_REGS_1_PCI_MASK_CLEAR_CLIENT_00_MASK_SHIFT 0 #endif /* #ifndef BCHP_PRI_CRIT_L2_REGS_1_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000017100000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs2_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000536111610313111030766 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_ind_sdram_regs2_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:03p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:41 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs2_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:03p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_IND_SDRAM_REGS2_0_H__ #define BCHP_DECODE_IND_SDRAM_REGS2_0_H__ /*************************************************************************** *DECODE_IND_SDRAM_REGS2_0 ***************************************************************************/ #define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_SDRAM_INC 0x00851000 /* REG_SDRAM_INC */ #define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_SDRAM_ADDR 0x00851004 /* REG_SDRAM_ADDR */ #define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_SDRAM_DATA 0x00851008 /* REG_SDRAM_DATA */ #define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_CPU_DBG 0x00851010 /* REG_CPU_DBG */ #define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_SDRAM_STAT 0x00851014 /* REG_SDRAM_STAT */ #define BCHP_DECODE_IND_SDRAM_REGS2_0_REG_SDRAM_END 0x0085107c /* REG_SDRAM_END */ #endif /* #ifndef BCHP_DECODE_IND_SDRAM_REGS2_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016000000000000011562 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuaux_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000614011610313111030762 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_cpuaux_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:00p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:00 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuaux_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:00p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_CPUAUX_0_H__ #define BCHP_DECODE_CPUAUX_0_H__ /*************************************************************************** *DECODE_CPUAUX_0 ***************************************************************************/ #define BCHP_DECODE_CPUAUX_0_CPUAUX_REG 0x00845000 /* CPUAUX_REG */ #define BCHP_DECODE_CPUAUX_0_CPUAUX_END 0x00845ffc /* CPUAUX_END */ /*************************************************************************** *CPUAUX_REG - CPUAUX_REG ***************************************************************************/ /* DECODE_CPUAUX_0 :: CPUAUX_REG :: Addr [31:00] */ #define BCHP_DECODE_CPUAUX_0_CPUAUX_REG_Addr_MASK 0xffffffff #define BCHP_DECODE_CPUAUX_0_CPUAUX_REG_Addr_SHIFT 0 /*************************************************************************** *CPUAUX_END - CPUAUX_END ***************************************************************************/ /* DECODE_CPUAUX_0 :: CPUAUX_END :: reserved0 [31:00] */ #define BCHP_DECODE_CPUAUX_0_CPUAUX_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_CPUAUX_0_CPUAUX_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_CPUAUX_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000014700000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_vich_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_vich_00000644000175000017500000000603511610313111030712 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_vich_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:22p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:22 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_vich_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:22p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_VICH_0_H__ #define BCHP_VICH_0_H__ /*************************************************************************** *VICH_0 ***************************************************************************/ #define BCHP_VICH_0_RESERVED 0x00b00000 /* RESERVED */ #define BCHP_VICH_0_RESERVED_END 0x00b0004c /* RESERVED_END */ /*************************************************************************** *RESERVED - RESERVED ***************************************************************************/ /* VICH_0 :: RESERVED :: reserved0 [31:00] */ #define BCHP_VICH_0_RESERVED_reserved0_MASK 0xffffffff #define BCHP_VICH_0_RESERVED_reserved0_SHIFT 0 /*************************************************************************** *RESERVED_END - RESERVED_END ***************************************************************************/ /* VICH_0 :: RESERVED_END :: reserved0 [31:00] */ #define BCHP_VICH_0_RESERVED_END_reserved0_MASK 0xffffffff #define BCHP_VICH_0_RESERVED_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_VICH_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016000000000000011562 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_rave.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id0000644000175000017500000000741511610313111031013 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_int_id_xpt_rave.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:09p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:42 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility unknown * RDB Parser 3.0 * generate_int_id.pl 1.0 * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_rave.h $ * * Hydra_Software_Devel/1 7/17/09 8:09p albertl * PR56880: Initial revision. * ***************************************************************************/ #include "bchp.h" #include "bchp_xpt_rave.h" #ifndef BCHP_INT_ID_XPT_RAVE_H__ #define BCHP_INT_ID_XPT_RAVE_H__ #define BCHP_INT_ID_XPT_RAVE_CC_ERROR_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_CC_ERROR_INT_SHIFT) #define BCHP_INT_ID_XPT_RAVE_CDB_LOWER_THRESH_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_CDB_LOWER_THRESH_INT_SHIFT) #define BCHP_INT_ID_XPT_RAVE_CDB_OVERFLOW_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_CDB_OVERFLOW_INT_SHIFT) #define BCHP_INT_ID_XPT_RAVE_CDB_UPPER_THRESH_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_CDB_UPPER_THRESH_INT_SHIFT) #define BCHP_INT_ID_XPT_RAVE_EMU_ERROR_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_EMU_ERROR_INT_SHIFT) #define BCHP_INT_ID_XPT_RAVE_ITB_LOWER_THRESH_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_ITB_LOWER_THRESH_INT_SHIFT) #define BCHP_INT_ID_XPT_RAVE_ITB_OVERFLOW_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_ITB_OVERFLOW_INT_SHIFT) #define BCHP_INT_ID_XPT_RAVE_ITB_UPPER_THRESH_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_ITB_UPPER_THRESH_INT_SHIFT) #define BCHP_INT_ID_XPT_RAVE_LAST_CMD_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_LAST_CMD_INT_SHIFT) #define BCHP_INT_ID_XPT_RAVE_PUSI_ERROR_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_PUSI_ERROR_INT_SHIFT) #define BCHP_INT_ID_XPT_RAVE_SCD_INDEX BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_SCD_INDEX_SHIFT) #define BCHP_INT_ID_XPT_RAVE_SPLICE_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_SPLICE_INT_SHIFT) #define BCHP_INT_ID_XPT_RAVE_TEI_ERROR_INT BCHP_INT_ID_CREATE(BCHP_XPT_RAVE_INT_CX5, BCHP_XPT_RAVE_INT_CX5_TEI_ERROR_INT_SHIFT) #endif /* #ifndef BCHP_INT_ID_XPT_RAVE_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015600000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dblk_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000013417311610313111030772 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_dblk_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:02p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:48 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dblk_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:02p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_DBLK_0_H__ #define BCHP_DECODE_DBLK_0_H__ /*************************************************************************** *DECODE_DBLK_0 ***************************************************************************/ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL 0x00800720 /* Deblocking Control */ #define BCHP_DECODE_DBLK_0_REG_DBLK_OUT 0x00800724 /* Deblocking Output Control */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM 0x00800728 /* REG_OLAP_XFORM - VC-1 only */ #define BCHP_DECODE_DBLK_0_REG_DBLK_QNT 0x0080072c /* Deblocking Quantization Data */ #define BCHP_DECODE_DBLK_0_REG_DBLK_OFFSET 0x00800730 /* Deblocking filter offsets (H.264 only) */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX 0x00800734 /* Deblocking Top Context */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO 0x00800738 /* Deblocking: Transform has non-zero coefs */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF 0x0080073c /* Deblocking Motion Vector Difference */ /*************************************************************************** *REG_DBLK_CTL - Deblocking Control ***************************************************************************/ /* DECODE_DBLK_0 :: REG_DBLK_CTL :: reserved0 [31:15] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_reserved0_MASK 0xffff8000 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_reserved0_SHIFT 15 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: Ctl_Edge_Top [14:14] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Ctl_Edge_Top_MASK 0x00004000 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Ctl_Edge_Top_SHIFT 14 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: Ctl_Edge_Bottom [13:13] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Ctl_Edge_Bottom_MASK 0x00002000 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Ctl_Edge_Bottom_SHIFT 13 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: Csr_dbhz_chr_top_mvdiff [12:12] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbhz_chr_top_mvdiff_MASK 0x00001000 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbhz_chr_top_mvdiff_SHIFT 12 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: Csr_dbvt_chr_top_mvdiff [11:11] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbvt_chr_top_mvdiff_MASK 0x00000800 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbvt_chr_top_mvdiff_SHIFT 11 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: Csr_dbhz_chr_mvdiff [10:10] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbhz_chr_mvdiff_MASK 0x00000400 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbhz_chr_mvdiff_SHIFT 10 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: Csr_dbvt_chr_mvdiff [09:09] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbvt_chr_mvdiff_MASK 0x00000200 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Csr_dbvt_chr_mvdiff_SHIFT 9 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: MPEG [08:08] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_MPEG_MASK 0x00000100 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_MPEG_SHIFT 8 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: H264_8x8 [07:07] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_H264_8x8_MASK 0x00000080 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_H264_8x8_SHIFT 7 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: Mono [06:06] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Mono_MASK 0x00000040 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Mono_SHIFT 6 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: Is_Last [05:05] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Is_Last_MASK 0x00000020 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Is_Last_SHIFT 5 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: Intra [04:04] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Intra_MASK 0x00000010 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Intra_SHIFT 4 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: Fleft [03:03] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Fleft_MASK 0x00000008 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Fleft_SHIFT 3 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: Ftop [02:02] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Ftop_MASK 0x00000004 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Ftop_SHIFT 2 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: Fint [01:01] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Fint_MASK 0x00000002 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_Fint_SHIFT 1 /* DECODE_DBLK_0 :: REG_DBLK_CTL :: CES [00:00] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_CES_MASK 0x00000001 #define BCHP_DECODE_DBLK_0_REG_DBLK_CTL_CES_SHIFT 0 /*************************************************************************** *REG_DBLK_OUT - Deblocking Output Control ***************************************************************************/ /* DECODE_DBLK_0 :: REG_DBLK_OUT :: reserved0 [31:17] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_reserved0_MASK 0xfffe0000 #define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_reserved0_SHIFT 17 /* DECODE_DBLK_0 :: REG_DBLK_OUT :: Out2 [16:16] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_Out2_MASK 0x00010000 #define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_Out2_SHIFT 16 /* DECODE_DBLK_0 :: REG_DBLK_OUT :: PicNum2 [15:08] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_PicNum2_MASK 0x0000ff00 #define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_PicNum2_SHIFT 8 /* DECODE_DBLK_0 :: REG_DBLK_OUT :: PicNum [07:00] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_PicNum_MASK 0x000000ff #define BCHP_DECODE_DBLK_0_REG_DBLK_OUT_PicNum_SHIFT 0 /*************************************************************************** *REG_OLAP_XFORM - REG_OLAP_XFORM - VC-1 only ***************************************************************************/ /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: reserved0 [31:30] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_reserved0_MASK 0xc0000000 #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_reserved0_SHIFT 30 /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: TopVIntra [29:29] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_TopVIntra_MASK 0x20000000 #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_TopVIntra_SHIFT 29 /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: TopUIntra [28:28] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_TopUIntra_MASK 0x10000000 #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_TopUIntra_SHIFT 28 /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: TopLIntra [27:24] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_TopLIntra_MASK 0x0f000000 #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_TopLIntra_SHIFT 24 /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: reserved1 [23:22] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_reserved1_MASK 0x00c00000 #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_reserved1_SHIFT 22 /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: Vintra [21:21] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_Vintra_MASK 0x00200000 #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_Vintra_SHIFT 21 /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: Uintra [20:20] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_Uintra_MASK 0x00100000 #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_Uintra_SHIFT 20 /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: LumaIntra [19:16] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_LumaIntra_MASK 0x000f0000 #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_LumaIntra_SHIFT 16 /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: reserved2 [15:12] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_reserved2_MASK 0x0000f000 #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_reserved2_SHIFT 12 /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: VV [11:11] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_VV_MASK 0x00000800 #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_VV_SHIFT 11 /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: VH [10:10] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_VH_MASK 0x00000400 #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_VH_SHIFT 10 /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: UV [09:09] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_UV_MASK 0x00000200 #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_UV_SHIFT 9 /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: UH [08:08] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_UH_MASK 0x00000100 #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_UH_SHIFT 8 /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: LumaVert [07:04] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_LumaVert_MASK 0x000000f0 #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_LumaVert_SHIFT 4 /* DECODE_DBLK_0 :: REG_OLAP_XFORM :: LumaHoriz [03:00] */ #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_LumaHoriz_MASK 0x0000000f #define BCHP_DECODE_DBLK_0_REG_OLAP_XFORM_LumaHoriz_SHIFT 0 /*************************************************************************** *REG_DBLK_QNT - Deblocking Quantization Data ***************************************************************************/ /* DECODE_DBLK_0 :: REG_DBLK_QNT :: reserved0 [31:24] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_reserved0_MASK 0xff000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_reserved0_SHIFT 24 /* DECODE_DBLK_0 :: REG_DBLK_QNT :: OPvTopTop [23:16] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_OPvTopTop_MASK 0x00ff0000 #define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_OPvTopTop_SHIFT 16 /* DECODE_DBLK_0 :: REG_DBLK_QNT :: OPvTop [15:08] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_OPvTop_MASK 0x0000ff00 #define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_OPvTop_SHIFT 8 /* DECODE_DBLK_0 :: REG_DBLK_QNT :: Opv [07:00] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_Opv_MASK 0x000000ff #define BCHP_DECODE_DBLK_0_REG_DBLK_QNT_Opv_SHIFT 0 /*************************************************************************** *REG_DBLK_OFFSET - Deblocking filter offsets (H.264 only) ***************************************************************************/ /* DECODE_DBLK_0 :: REG_DBLK_OFFSET :: reserved0 [31:16] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_OFFSET_reserved0_MASK 0xffff0000 #define BCHP_DECODE_DBLK_0_REG_DBLK_OFFSET_reserved0_SHIFT 16 /* DECODE_DBLK_0 :: REG_DBLK_OFFSET :: OffsetB [15:08] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_OFFSET_OffsetB_MASK 0x0000ff00 #define BCHP_DECODE_DBLK_0_REG_DBLK_OFFSET_OffsetB_SHIFT 8 /* DECODE_DBLK_0 :: REG_DBLK_OFFSET :: OffsetA [07:00] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_OFFSET_OffsetA_MASK 0x000000ff #define BCHP_DECODE_DBLK_0_REG_DBLK_OFFSET_OffsetA_SHIFT 0 /*************************************************************************** *REG_DBLK_TOP_CTX - Deblocking Top Context ***************************************************************************/ /* union - case H264 [31:00] */ /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: reserved0 [31:22] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_reserved0_MASK 0xffc00000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_reserved0_SHIFT 22 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: TB15 [21:21] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB15_MASK 0x00200000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB15_SHIFT 21 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: TB14 [20:20] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB14_MASK 0x00100000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB14_SHIFT 20 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: TB11 [19:19] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB11_MASK 0x00080000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB11_SHIFT 19 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: TB10 [18:18] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB10_MASK 0x00040000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_TB10_SHIFT 18 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: reserved1 [17:17] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_reserved1_MASK 0x00020000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_reserved1_SHIFT 17 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: Tintra [16:16] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_Tintra_MASK 0x00010000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_Tintra_SHIFT 16 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: reserved2 [15:06] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_reserved2_MASK 0x0000ffc0 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_reserved2_SHIFT 6 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: B15 [05:05] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B15_MASK 0x00000020 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B15_SHIFT 5 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: B14 [04:04] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B14_MASK 0x00000010 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B14_SHIFT 4 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: B11 [03:03] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B11_MASK 0x00000008 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B11_SHIFT 3 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: B10 [02:02] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B10_MASK 0x00000004 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_B10_SHIFT 2 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: Field [01:01] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_Field_MASK 0x00000002 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_Field_SHIFT 1 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: H264 :: Intra [00:00] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_Intra_MASK 0x00000001 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_H264_Intra_SHIFT 0 /* union - case VC1_0 [31:00] */ /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: VV3 [31:31] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV3_MASK 0x80000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV3_SHIFT 31 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: VV2 [30:30] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV2_MASK 0x40000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV2_SHIFT 30 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: VV1 [29:29] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV1_MASK 0x20000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV1_SHIFT 29 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: VV0 [28:28] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV0_MASK 0x10000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VV0_SHIFT 28 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: UV3 [27:27] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV3_MASK 0x08000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV3_SHIFT 27 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: UV2 [26:26] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV2_MASK 0x04000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV2_SHIFT 26 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: UV1 [25:25] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV1_MASK 0x02000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV1_SHIFT 25 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: UV0 [24:24] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV0_MASK 0x01000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UV0_SHIFT 24 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV15 [23:23] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV15_MASK 0x00800000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV15_SHIFT 23 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV14 [22:22] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV14_MASK 0x00400000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV14_SHIFT 22 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV11 [21:21] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV11_MASK 0x00200000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV11_SHIFT 21 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV10 [20:20] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV10_MASK 0x00100000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV10_SHIFT 20 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV7 [19:19] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV7_MASK 0x00080000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV7_SHIFT 19 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV6 [18:18] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV6_MASK 0x00040000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV6_SHIFT 18 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV3 [17:17] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV3_MASK 0x00020000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV3_SHIFT 17 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YV2 [16:16] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV2_MASK 0x00010000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YV2_SHIFT 16 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: VH3 [15:15] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VH3_MASK 0x00008000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VH3_SHIFT 15 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: VH2 [14:14] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VH2_MASK 0x00004000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_VH2_SHIFT 14 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: reserved0 [13:12] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_reserved0_MASK 0x00003000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_reserved0_SHIFT 12 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: UH3 [11:11] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UH3_MASK 0x00000800 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UH3_SHIFT 11 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: UH2 [10:10] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UH2_MASK 0x00000400 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_UH2_SHIFT 10 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: reserved1 [09:08] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_reserved1_MASK 0x00000300 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_reserved1_SHIFT 8 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YH15 [07:07] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH15_MASK 0x00000080 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH15_SHIFT 7 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YH14 [06:06] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH14_MASK 0x00000040 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH14_SHIFT 6 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YH13 [05:05] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH13_MASK 0x00000020 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH13_SHIFT 5 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: YH12 [04:04] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH12_MASK 0x00000010 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_YH12_SHIFT 4 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: reserved2 [03:01] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_reserved2_MASK 0x0000000e #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_reserved2_SHIFT 1 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_0 :: TFld [00:00] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_TFld_MASK 0x00000001 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_0_TFld_SHIFT 0 /* union - case VC1_1 [31:00] */ /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: VV3 [31:31] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV3_MASK 0x80000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV3_SHIFT 31 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: VV2 [30:30] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV2_MASK 0x40000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV2_SHIFT 30 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: VV1 [29:29] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV1_MASK 0x20000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV1_SHIFT 29 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: VV0 [28:28] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV0_MASK 0x10000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_VV0_SHIFT 28 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: UV3 [27:27] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV3_MASK 0x08000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV3_SHIFT 27 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: UV2 [26:26] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV2_MASK 0x04000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV2_SHIFT 26 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: UV1 [25:25] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV1_MASK 0x02000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV1_SHIFT 25 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: UV0 [24:24] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV0_MASK 0x01000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_UV0_SHIFT 24 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV13 [23:23] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV13_MASK 0x00800000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV13_SHIFT 23 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV12 [22:22] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV12_MASK 0x00400000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV12_SHIFT 22 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV9 [21:21] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV9_MASK 0x00200000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV9_SHIFT 21 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV8 [20:20] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV8_MASK 0x00100000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV8_SHIFT 20 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV5 [19:19] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV5_MASK 0x00080000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV5_SHIFT 19 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV4 [18:18] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV4_MASK 0x00040000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV4_SHIFT 18 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV1 [17:17] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV1_MASK 0x00020000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV1_SHIFT 17 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: YV0 [16:16] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV0_MASK 0x00010000 #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_YV0_SHIFT 16 /* DECODE_DBLK_0 :: REG_DBLK_TOP_CTX :: VC1_1 :: reserved0 [15:00] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_reserved0_MASK 0x0000ffff #define BCHP_DECODE_DBLK_0_REG_DBLK_TOP_CTX_VC1_1_reserved0_SHIFT 0 /*************************************************************************** *REG_DBLK_XZERO - Deblocking: Transform has non-zero coefs ***************************************************************************/ /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: reserved0 [31:16] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_reserved0_MASK 0xffff0000 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_reserved0_SHIFT 16 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B15 [15:15] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B15_MASK 0x00008000 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B15_SHIFT 15 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B14 [14:14] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B14_MASK 0x00004000 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B14_SHIFT 14 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B13 [13:13] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B13_MASK 0x00002000 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B13_SHIFT 13 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B12 [12:12] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B12_MASK 0x00001000 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B12_SHIFT 12 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B11 [11:11] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B11_MASK 0x00000800 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B11_SHIFT 11 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B10 [10:10] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B10_MASK 0x00000400 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B10_SHIFT 10 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B9 [09:09] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B9_MASK 0x00000200 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B9_SHIFT 9 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B8 [08:08] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B8_MASK 0x00000100 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B8_SHIFT 8 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B7 [07:07] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B7_MASK 0x00000080 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B7_SHIFT 7 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B6 [06:06] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B6_MASK 0x00000040 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B6_SHIFT 6 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B5 [05:05] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B5_MASK 0x00000020 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B5_SHIFT 5 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B4 [04:04] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B4_MASK 0x00000010 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B4_SHIFT 4 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B3 [03:03] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B3_MASK 0x00000008 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B3_SHIFT 3 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B2 [02:02] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B2_MASK 0x00000004 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B2_SHIFT 2 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B1 [01:01] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B1_MASK 0x00000002 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B1_SHIFT 1 /* DECODE_DBLK_0 :: REG_DBLK_XZERO :: B0 [00:00] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B0_MASK 0x00000001 #define BCHP_DECODE_DBLK_0_REG_DBLK_XZERO_B0_SHIFT 0 /*************************************************************************** *REG_DBLK_MVDIFF - Deblocking Motion Vector Difference ***************************************************************************/ /* union - case H264 [31:00] */ /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V15 [31:31] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V15_MASK 0x80000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V15_SHIFT 31 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V14 [30:30] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V14_MASK 0x40000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V14_SHIFT 30 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V13 [29:29] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V13_MASK 0x20000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V13_SHIFT 29 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V12 [28:28] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V12_MASK 0x10000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V12_SHIFT 28 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V11 [27:27] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V11_MASK 0x08000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V11_SHIFT 27 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V10 [26:26] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V10_MASK 0x04000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V10_SHIFT 26 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V9 [25:25] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V9_MASK 0x02000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V9_SHIFT 25 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V8 [24:24] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V8_MASK 0x01000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V8_SHIFT 24 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V7 [23:23] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V7_MASK 0x00800000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V7_SHIFT 23 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V6 [22:22] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V6_MASK 0x00400000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V6_SHIFT 22 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V5 [21:21] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V5_MASK 0x00200000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V5_SHIFT 21 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V4 [20:20] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V4_MASK 0x00100000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V4_SHIFT 20 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V3 [19:19] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V3_MASK 0x00080000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V3_SHIFT 19 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V2 [18:18] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V2_MASK 0x00040000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V2_SHIFT 18 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V1 [17:17] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V1_MASK 0x00020000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V1_SHIFT 17 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: V0 [16:16] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V0_MASK 0x00010000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_V0_SHIFT 16 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H15 [15:15] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H15_MASK 0x00008000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H15_SHIFT 15 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H14 [14:14] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H14_MASK 0x00004000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H14_SHIFT 14 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H13 [13:13] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H13_MASK 0x00002000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H13_SHIFT 13 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H12 [12:12] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H12_MASK 0x00001000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H12_SHIFT 12 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H11 [11:11] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H11_MASK 0x00000800 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H11_SHIFT 11 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H10 [10:10] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H10_MASK 0x00000400 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H10_SHIFT 10 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H9 [09:09] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H9_MASK 0x00000200 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H9_SHIFT 9 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H8 [08:08] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H8_MASK 0x00000100 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H8_SHIFT 8 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H7 [07:07] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H7_MASK 0x00000080 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H7_SHIFT 7 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H6 [06:06] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H6_MASK 0x00000040 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H6_SHIFT 6 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H5 [05:05] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H5_MASK 0x00000020 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H5_SHIFT 5 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H4 [04:04] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H4_MASK 0x00000010 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H4_SHIFT 4 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H3 [03:03] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H3_MASK 0x00000008 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H3_SHIFT 3 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H2 [02:02] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H2_MASK 0x00000004 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H2_SHIFT 2 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H1 [01:01] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H1_MASK 0x00000002 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H1_SHIFT 1 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: H264 :: H0 [00:00] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H0_MASK 0x00000001 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_H264_H0_SHIFT 0 /* union - case VC1_0 [31:00] */ /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V15 [31:31] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V15_MASK 0x80000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V15_SHIFT 31 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V14 [30:30] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V14_MASK 0x40000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V14_SHIFT 30 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V13 [29:29] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V13_MASK 0x20000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V13_SHIFT 29 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V12 [28:28] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V12_MASK 0x10000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V12_SHIFT 28 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V11 [27:27] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V11_MASK 0x08000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V11_SHIFT 27 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V10 [26:26] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V10_MASK 0x04000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V10_SHIFT 26 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V9 [25:25] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V9_MASK 0x02000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V9_SHIFT 25 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V8 [24:24] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V8_MASK 0x01000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V8_SHIFT 24 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V7 [23:23] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V7_MASK 0x00800000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V7_SHIFT 23 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V6 [22:22] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V6_MASK 0x00400000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V6_SHIFT 22 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V5 [21:21] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V5_MASK 0x00200000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V5_SHIFT 21 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V4 [20:20] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V4_MASK 0x00100000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V4_SHIFT 20 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V3 [19:19] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V3_MASK 0x00080000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V3_SHIFT 19 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V2 [18:18] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V2_MASK 0x00040000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V2_SHIFT 18 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V1 [17:17] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V1_MASK 0x00020000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V1_SHIFT 17 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: V0 [16:16] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V0_MASK 0x00010000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_V0_SHIFT 16 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H15 [15:15] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H15_MASK 0x00008000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H15_SHIFT 15 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H14 [14:14] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H14_MASK 0x00004000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H14_SHIFT 14 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H13 [13:13] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H13_MASK 0x00002000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H13_SHIFT 13 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H12 [12:12] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H12_MASK 0x00001000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H12_SHIFT 12 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H11 [11:11] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H11_MASK 0x00000800 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H11_SHIFT 11 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H10 [10:10] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H10_MASK 0x00000400 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H10_SHIFT 10 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H9 [09:09] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H9_MASK 0x00000200 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H9_SHIFT 9 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H8 [08:08] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H8_MASK 0x00000100 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H8_SHIFT 8 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H7 [07:07] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H7_MASK 0x00000080 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H7_SHIFT 7 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H6 [06:06] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H6_MASK 0x00000040 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H6_SHIFT 6 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H5 [05:05] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H5_MASK 0x00000020 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H5_SHIFT 5 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H4 [04:04] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H4_MASK 0x00000010 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H4_SHIFT 4 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H3 [03:03] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H3_MASK 0x00000008 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H3_SHIFT 3 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H2 [02:02] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H2_MASK 0x00000004 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H2_SHIFT 2 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H1 [01:01] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H1_MASK 0x00000002 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H1_SHIFT 1 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_0 :: H0 [00:00] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H0_MASK 0x00000001 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_0_H0_SHIFT 0 /* union - case VC1_1 [31:00] */ /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: reserved0 [31:28] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved0_MASK 0xf0000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved0_SHIFT 28 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VV3 [27:27] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV3_MASK 0x08000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV3_SHIFT 27 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VV2 [26:26] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV2_MASK 0x04000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV2_SHIFT 26 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VV1 [25:25] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV1_MASK 0x02000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV1_SHIFT 25 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VV0 [24:24] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV0_MASK 0x01000000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VV0_SHIFT 24 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: reserved1 [23:20] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved1_MASK 0x00f00000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved1_SHIFT 20 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UV3 [19:19] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV3_MASK 0x00080000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV3_SHIFT 19 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UV2 [18:18] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV2_MASK 0x00040000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV2_SHIFT 18 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UV1 [17:17] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV1_MASK 0x00020000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV1_SHIFT 17 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UV0 [16:16] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV0_MASK 0x00010000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UV0_SHIFT 16 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: reserved2 [15:12] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved2_MASK 0x0000f000 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved2_SHIFT 12 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VH3 [11:11] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH3_MASK 0x00000800 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH3_SHIFT 11 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VH2 [10:10] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH2_MASK 0x00000400 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH2_SHIFT 10 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VH1 [09:09] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH1_MASK 0x00000200 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH1_SHIFT 9 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: VH0 [08:08] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH0_MASK 0x00000100 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_VH0_SHIFT 8 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: reserved3 [07:04] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved3_MASK 0x000000f0 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_reserved3_SHIFT 4 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UH3 [03:03] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH3_MASK 0x00000008 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH3_SHIFT 3 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UH2 [02:02] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH2_MASK 0x00000004 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH2_SHIFT 2 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UH1 [01:01] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH1_MASK 0x00000002 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH1_SHIFT 1 /* DECODE_DBLK_0 :: REG_DBLK_MVDIFF :: VC1_1 :: UH0 [00:00] */ #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH0_MASK 0x00000001 #define BCHP_DECODE_DBLK_0_REG_DBLK_MVDIFF_VC1_1_UH0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_DBLK_0_H__ */ /* End of File */ crystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_intr.h0000644000175000017500000017653311610313111030757 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_intr.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:09p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:44 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_intr.h $ * * Hydra_Software_Devel/1 7/17/09 8:09p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_INTR_H__ #define BCHP_INTR_H__ /*************************************************************************** *INTR - TGT L2 Interrupt Controller Registers ***************************************************************************/ #define BCHP_INTR_INTR_STATUS 0x00500700 /* Interrupt Status Register */ #define BCHP_INTR_INTR_SET 0x00500704 /* Interrupt Set Register */ #define BCHP_INTR_INTR_CLR_REG 0x00500708 /* Interrupt Clear Register */ #define BCHP_INTR_INTR_MSK_STS_REG 0x0050070c /* Interrupt Mask Status Register */ #define BCHP_INTR_INTR_MSK_SET_REG 0x00500710 /* Interrupt Mask Set Register */ #define BCHP_INTR_INTR_MSK_CLR_REG 0x00500714 /* Interrupt Mask Clear Register */ #define BCHP_INTR_EOI_CTRL 0x00500718 /* End of interrupt control register */ #define BCHP_INTR_CPU_INTR_STATUS 0x00500720 /* CPU_Interrupt Status Register */ #define BCHP_INTR_CPU_INTR_SET 0x00500724 /* CPU_Interrupt Set Register */ #define BCHP_INTR_CPU_INTR_CLR_REG 0x00500728 /* CPU_Interrupt Clear Register */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG 0x0050072c /* CPU_Interrupt Mask Status Register */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG 0x00500730 /* CPU Interrupt Mask Set Register */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG 0x00500734 /* CPU Interrupt Mask Clear Register */ /*************************************************************************** *INTR_STATUS - Interrupt Status Register ***************************************************************************/ /* INTR :: INTR_STATUS :: reserved0 [31:27] */ #define BCHP_INTR_INTR_STATUS_reserved0_MASK 0xf8000000 #define BCHP_INTR_INTR_STATUS_reserved0_SHIFT 27 /* INTR :: INTR_STATUS :: HAT_INTR [26:26] */ #define BCHP_INTR_INTR_STATUS_HAT_INTR_MASK 0x04000000 #define BCHP_INTR_INTR_STATUS_HAT_INTR_SHIFT 26 /* INTR :: INTR_STATUS :: PCIE_TGT_CA_ATTN [25:25] */ #define BCHP_INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define BCHP_INTR_INTR_STATUS_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: INTR_STATUS :: PCIE_TGT_UR_ATTN [24:24] */ #define BCHP_INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define BCHP_INTR_INTR_STATUS_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: INTR_STATUS :: reserved1 [23:20] */ #define BCHP_INTR_INTR_STATUS_reserved1_MASK 0x00f00000 #define BCHP_INTR_INTR_STATUS_reserved1_SHIFT 20 /* INTR :: INTR_STATUS :: ARM_MBOX3_INTR [19:19] */ #define BCHP_INTR_INTR_STATUS_ARM_MBOX3_INTR_MASK 0x00080000 #define BCHP_INTR_INTR_STATUS_ARM_MBOX3_INTR_SHIFT 19 /* INTR :: INTR_STATUS :: ARM_MBOX2_INTR [18:18] */ #define BCHP_INTR_INTR_STATUS_ARM_MBOX2_INTR_MASK 0x00040000 #define BCHP_INTR_INTR_STATUS_ARM_MBOX2_INTR_SHIFT 18 /* INTR :: INTR_STATUS :: ARM_MBOX1_INTR [17:17] */ #define BCHP_INTR_INTR_STATUS_ARM_MBOX1_INTR_MASK 0x00020000 #define BCHP_INTR_INTR_STATUS_ARM_MBOX1_INTR_SHIFT 17 /* INTR :: INTR_STATUS :: ARM_MBOX0_INTR [16:16] */ #define BCHP_INTR_INTR_STATUS_ARM_MBOX0_INTR_MASK 0x00010000 #define BCHP_INTR_INTR_STATUS_ARM_MBOX0_INTR_SHIFT 16 /* INTR :: INTR_STATUS :: reserved2 [15:14] */ #define BCHP_INTR_INTR_STATUS_reserved2_MASK 0x0000c000 #define BCHP_INTR_INTR_STATUS_reserved2_SHIFT 14 /* INTR :: INTR_STATUS :: L1_HIF_RX_DMA_ERR_INTR [13:13] */ #define BCHP_INTR_INTR_STATUS_L1_HIF_RX_DMA_ERR_INTR_MASK 0x00002000 #define BCHP_INTR_INTR_STATUS_L1_HIF_RX_DMA_ERR_INTR_SHIFT 13 /* INTR :: INTR_STATUS :: L1_HIF_RX_DMA_DONE_INTR [12:12] */ #define BCHP_INTR_INTR_STATUS_L1_HIF_RX_DMA_DONE_INTR_MASK 0x00001000 #define BCHP_INTR_INTR_STATUS_L1_HIF_RX_DMA_DONE_INTR_SHIFT 12 /* INTR :: INTR_STATUS :: L1_Y_RX_DMA_ERR_INTR [11:11] */ #define BCHP_INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK 0x00000800 #define BCHP_INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_SHIFT 11 /* INTR :: INTR_STATUS :: L1_Y_RX_DMA_DONE_INTR [10:10] */ #define BCHP_INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK 0x00000400 #define BCHP_INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_SHIFT 10 /* INTR :: INTR_STATUS :: L1_TX_DMA_ERR_INTR [09:09] */ #define BCHP_INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000200 #define BCHP_INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 9 /* INTR :: INTR_STATUS :: L1_TX_DMA_DONE_INTR [08:08] */ #define BCHP_INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000100 #define BCHP_INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 8 /* INTR :: INTR_STATUS :: reserved3 [07:06] */ #define BCHP_INTR_INTR_STATUS_reserved3_MASK 0x000000c0 #define BCHP_INTR_INTR_STATUS_reserved3_SHIFT 6 /* INTR :: INTR_STATUS :: L0_HIF_RX_DMA_ERR_INTR [05:05] */ #define BCHP_INTR_INTR_STATUS_L0_HIF_RX_DMA_ERR_INTR_MASK 0x00000020 #define BCHP_INTR_INTR_STATUS_L0_HIF_RX_DMA_ERR_INTR_SHIFT 5 /* INTR :: INTR_STATUS :: L0_HIF_RX_DMA_DONE_INTR [04:04] */ #define BCHP_INTR_INTR_STATUS_L0_HIF_RX_DMA_DONE_INTR_MASK 0x00000010 #define BCHP_INTR_INTR_STATUS_L0_HIF_RX_DMA_DONE_INTR_SHIFT 4 /* INTR :: INTR_STATUS :: L0_Y_RX_DMA_ERR_INTR [03:03] */ #define BCHP_INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK 0x00000008 #define BCHP_INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_SHIFT 3 /* INTR :: INTR_STATUS :: L0_Y_RX_DMA_DONE_INTR [02:02] */ #define BCHP_INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK 0x00000004 #define BCHP_INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_SHIFT 2 /* INTR :: INTR_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */ #define BCHP_INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002 #define BCHP_INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1 /* INTR :: INTR_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */ #define BCHP_INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001 #define BCHP_INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0 /*************************************************************************** *INTR_SET - Interrupt Set Register ***************************************************************************/ /* INTR :: INTR_SET :: reserved0 [31:27] */ #define BCHP_INTR_INTR_SET_reserved0_MASK 0xf8000000 #define BCHP_INTR_INTR_SET_reserved0_SHIFT 27 /* INTR :: INTR_SET :: HAT_INTR [26:26] */ #define BCHP_INTR_INTR_SET_HAT_INTR_MASK 0x04000000 #define BCHP_INTR_INTR_SET_HAT_INTR_SHIFT 26 /* INTR :: INTR_SET :: PCIE_TGT_CA_ATTN [25:25] */ #define BCHP_INTR_INTR_SET_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define BCHP_INTR_INTR_SET_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: INTR_SET :: PCIE_TGT_UR_ATTN [24:24] */ #define BCHP_INTR_INTR_SET_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define BCHP_INTR_INTR_SET_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: INTR_SET :: reserved1 [23:20] */ #define BCHP_INTR_INTR_SET_reserved1_MASK 0x00f00000 #define BCHP_INTR_INTR_SET_reserved1_SHIFT 20 /* INTR :: INTR_SET :: ARM_MBOX3_INTR [19:19] */ #define BCHP_INTR_INTR_SET_ARM_MBOX3_INTR_MASK 0x00080000 #define BCHP_INTR_INTR_SET_ARM_MBOX3_INTR_SHIFT 19 /* INTR :: INTR_SET :: ARM_MBOX2_INTR [18:18] */ #define BCHP_INTR_INTR_SET_ARM_MBOX2_INTR_MASK 0x00040000 #define BCHP_INTR_INTR_SET_ARM_MBOX2_INTR_SHIFT 18 /* INTR :: INTR_SET :: ARM_MBOX1_INTR [17:17] */ #define BCHP_INTR_INTR_SET_ARM_MBOX1_INTR_MASK 0x00020000 #define BCHP_INTR_INTR_SET_ARM_MBOX1_INTR_SHIFT 17 /* INTR :: INTR_SET :: ARM_MBOX0_INTR [16:16] */ #define BCHP_INTR_INTR_SET_ARM_MBOX0_INTR_MASK 0x00010000 #define BCHP_INTR_INTR_SET_ARM_MBOX0_INTR_SHIFT 16 /* INTR :: INTR_SET :: reserved2 [15:14] */ #define BCHP_INTR_INTR_SET_reserved2_MASK 0x0000c000 #define BCHP_INTR_INTR_SET_reserved2_SHIFT 14 /* INTR :: INTR_SET :: HIF_RX_DMA_L1_ERR_INTR [13:13] */ #define BCHP_INTR_INTR_SET_HIF_RX_DMA_L1_ERR_INTR_MASK 0x00002000 #define BCHP_INTR_INTR_SET_HIF_RX_DMA_L1_ERR_INTR_SHIFT 13 /* INTR :: INTR_SET :: HIF_RX_DMA_L1_DONE_INTR [12:12] */ #define BCHP_INTR_INTR_SET_HIF_RX_DMA_L1_DONE_INTR_MASK 0x00001000 #define BCHP_INTR_INTR_SET_HIF_RX_DMA_L1_DONE_INTR_SHIFT 12 /* INTR :: INTR_SET :: Y_RX_DMA_L1_ERR_INTR [11:11] */ #define BCHP_INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_MASK 0x00000800 #define BCHP_INTR_INTR_SET_Y_RX_DMA_L1_ERR_INTR_SHIFT 11 /* INTR :: INTR_SET :: Y_RX_DMA_L1_DONE_INTR [10:10] */ #define BCHP_INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_MASK 0x00000400 #define BCHP_INTR_INTR_SET_Y_RX_DMA_L1_DONE_INTR_SHIFT 10 /* INTR :: INTR_SET :: TX_DMA_L1_ERR_INTR [09:09] */ #define BCHP_INTR_INTR_SET_TX_DMA_L1_ERR_INTR_MASK 0x00000200 #define BCHP_INTR_INTR_SET_TX_DMA_L1_ERR_INTR_SHIFT 9 /* INTR :: INTR_SET :: TX_DMA_L1_DONE_INTR [08:08] */ #define BCHP_INTR_INTR_SET_TX_DMA_L1_DONE_INTR_MASK 0x00000100 #define BCHP_INTR_INTR_SET_TX_DMA_L1_DONE_INTR_SHIFT 8 /* INTR :: INTR_SET :: reserved3 [07:06] */ #define BCHP_INTR_INTR_SET_reserved3_MASK 0x000000c0 #define BCHP_INTR_INTR_SET_reserved3_SHIFT 6 /* INTR :: INTR_SET :: HIF_RX_DMA_L0_ERR_INTR [05:05] */ #define BCHP_INTR_INTR_SET_HIF_RX_DMA_L0_ERR_INTR_MASK 0x00000020 #define BCHP_INTR_INTR_SET_HIF_RX_DMA_L0_ERR_INTR_SHIFT 5 /* INTR :: INTR_SET :: HIF_RX_DMA_L0_DONE_INTR [04:04] */ #define BCHP_INTR_INTR_SET_HIF_RX_DMA_L0_DONE_INTR_MASK 0x00000010 #define BCHP_INTR_INTR_SET_HIF_RX_DMA_L0_DONE_INTR_SHIFT 4 /* INTR :: INTR_SET :: Y_RX_DMA_L0_ERR_INTR [03:03] */ #define BCHP_INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_MASK 0x00000008 #define BCHP_INTR_INTR_SET_Y_RX_DMA_L0_ERR_INTR_SHIFT 3 /* INTR :: INTR_SET :: Y_RX_DMA_L0_DONE_INTR [02:02] */ #define BCHP_INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_MASK 0x00000004 #define BCHP_INTR_INTR_SET_Y_RX_DMA_L0_DONE_INTR_SHIFT 2 /* INTR :: INTR_SET :: TX_DMA_L0_ERR_INTR [01:01] */ #define BCHP_INTR_INTR_SET_TX_DMA_L0_ERR_INTR_MASK 0x00000002 #define BCHP_INTR_INTR_SET_TX_DMA_L0_ERR_INTR_SHIFT 1 /* INTR :: INTR_SET :: TX_DMA_L0_DONE_INTR [00:00] */ #define BCHP_INTR_INTR_SET_TX_DMA_L0_DONE_INTR_MASK 0x00000001 #define BCHP_INTR_INTR_SET_TX_DMA_L0_DONE_INTR_SHIFT 0 /*************************************************************************** *INTR_CLR_REG - Interrupt Clear Register ***************************************************************************/ /* INTR :: INTR_CLR_REG :: reserved0 [31:27] */ #define BCHP_INTR_INTR_CLR_REG_reserved0_MASK 0xf8000000 #define BCHP_INTR_INTR_CLR_REG_reserved0_SHIFT 27 /* INTR :: INTR_CLR_REG :: HAT_INTR [26:26] */ #define BCHP_INTR_INTR_CLR_REG_HAT_INTR_MASK 0x04000000 #define BCHP_INTR_INTR_CLR_REG_HAT_INTR_SHIFT 26 /* INTR :: INTR_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ #define BCHP_INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define BCHP_INTR_INTR_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: INTR_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ #define BCHP_INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define BCHP_INTR_INTR_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: INTR_CLR_REG :: reserved1 [23:20] */ #define BCHP_INTR_INTR_CLR_REG_reserved1_MASK 0x00f00000 #define BCHP_INTR_INTR_CLR_REG_reserved1_SHIFT 20 /* INTR :: INTR_CLR_REG :: ARM_MBOX3_INTR [19:19] */ #define BCHP_INTR_INTR_CLR_REG_ARM_MBOX3_INTR_MASK 0x00080000 #define BCHP_INTR_INTR_CLR_REG_ARM_MBOX3_INTR_SHIFT 19 /* INTR :: INTR_CLR_REG :: ARM_MBOX2_INTR [18:18] */ #define BCHP_INTR_INTR_CLR_REG_ARM_MBOX2_INTR_MASK 0x00040000 #define BCHP_INTR_INTR_CLR_REG_ARM_MBOX2_INTR_SHIFT 18 /* INTR :: INTR_CLR_REG :: ARM_MBOX1_INTR [17:17] */ #define BCHP_INTR_INTR_CLR_REG_ARM_MBOX1_INTR_MASK 0x00020000 #define BCHP_INTR_INTR_CLR_REG_ARM_MBOX1_INTR_SHIFT 17 /* INTR :: INTR_CLR_REG :: ARM_MBOX0_INTR [16:16] */ #define BCHP_INTR_INTR_CLR_REG_ARM_MBOX0_INTR_MASK 0x00010000 #define BCHP_INTR_INTR_CLR_REG_ARM_MBOX0_INTR_SHIFT 16 /* INTR :: INTR_CLR_REG :: reserved2 [15:14] */ #define BCHP_INTR_INTR_CLR_REG_reserved2_MASK 0x0000c000 #define BCHP_INTR_INTR_CLR_REG_reserved2_SHIFT 14 /* INTR :: INTR_CLR_REG :: L1_HIF_RX_DMA_ERR_INTR_CLR [13:13] */ #define BCHP_INTR_INTR_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_CLR_MASK 0x00002000 #define BCHP_INTR_INTR_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_CLR_SHIFT 13 /* INTR :: INTR_CLR_REG :: L1_HIF_RX_DMA_DONE_INTR_CLR [12:12] */ #define BCHP_INTR_INTR_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_CLR_MASK 0x00001000 #define BCHP_INTR_INTR_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_CLR_SHIFT 12 /* INTR :: INTR_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_CLR [11:11] */ #define BCHP_INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000800 #define BCHP_INTR_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_SHIFT 11 /* INTR :: INTR_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_CLR [10:10] */ #define BCHP_INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000400 #define BCHP_INTR_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_SHIFT 10 /* INTR :: INTR_CLR_REG :: L1_TX_DMA_ERR_INTR_CLR [09:09] */ #define BCHP_INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_MASK 0x00000200 #define BCHP_INTR_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_SHIFT 9 /* INTR :: INTR_CLR_REG :: L1_TX_DMA_DONE_INTR_CLR [08:08] */ #define BCHP_INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_MASK 0x00000100 #define BCHP_INTR_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_SHIFT 8 /* INTR :: INTR_CLR_REG :: reserved3 [07:06] */ #define BCHP_INTR_INTR_CLR_REG_reserved3_MASK 0x000000c0 #define BCHP_INTR_INTR_CLR_REG_reserved3_SHIFT 6 /* INTR :: INTR_CLR_REG :: L0_HIF_RX_DMA_ERR_INTR_CLR [05:05] */ #define BCHP_INTR_INTR_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_CLR_MASK 0x00000020 #define BCHP_INTR_INTR_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_CLR_SHIFT 5 /* INTR :: INTR_CLR_REG :: L0_HIF_RX_DMA_DONE_INTR_CLR [04:04] */ #define BCHP_INTR_INTR_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_CLR_MASK 0x00000010 #define BCHP_INTR_INTR_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_CLR_SHIFT 4 /* INTR :: INTR_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_CLR [03:03] */ #define BCHP_INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000008 #define BCHP_INTR_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_SHIFT 3 /* INTR :: INTR_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_CLR [02:02] */ #define BCHP_INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000004 #define BCHP_INTR_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_SHIFT 2 /* INTR :: INTR_CLR_REG :: L0_TX_DMA_ERR_INTR_CLR [01:01] */ #define BCHP_INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_MASK 0x00000002 #define BCHP_INTR_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_SHIFT 1 /* INTR :: INTR_CLR_REG :: L0_TX_DMA_DONE_INTR_CLR [00:00] */ #define BCHP_INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_MASK 0x00000001 #define BCHP_INTR_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_SHIFT 0 /*************************************************************************** *INTR_MSK_STS_REG - Interrupt Mask Status Register ***************************************************************************/ /* INTR :: INTR_MSK_STS_REG :: reserved0 [31:27] */ #define BCHP_INTR_INTR_MSK_STS_REG_reserved0_MASK 0xf8000000 #define BCHP_INTR_INTR_MSK_STS_REG_reserved0_SHIFT 27 /* INTR :: INTR_MSK_STS_REG :: HAT_INTR [26:26] */ #define BCHP_INTR_INTR_MSK_STS_REG_HAT_INTR_MASK 0x04000000 #define BCHP_INTR_INTR_MSK_STS_REG_HAT_INTR_SHIFT 26 /* INTR :: INTR_MSK_STS_REG :: PCIE_TGT_CA_ATTN [25:25] */ #define BCHP_INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define BCHP_INTR_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: INTR_MSK_STS_REG :: PCIE_TGT_UR_ATTN [24:24] */ #define BCHP_INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define BCHP_INTR_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: INTR_MSK_STS_REG :: reserved1 [23:20] */ #define BCHP_INTR_INTR_MSK_STS_REG_reserved1_MASK 0x00f00000 #define BCHP_INTR_INTR_MSK_STS_REG_reserved1_SHIFT 20 /* INTR :: INTR_MSK_STS_REG :: ARM_MBOX3_INTR [19:19] */ #define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX3_INTR_MASK 0x00080000 #define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX3_INTR_SHIFT 19 /* INTR :: INTR_MSK_STS_REG :: ARM_MBOX2_INTR [18:18] */ #define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX2_INTR_MASK 0x00040000 #define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX2_INTR_SHIFT 18 /* INTR :: INTR_MSK_STS_REG :: ARM_MBOX1_INTR [17:17] */ #define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX1_INTR_MASK 0x00020000 #define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX1_INTR_SHIFT 17 /* INTR :: INTR_MSK_STS_REG :: ARM_MBOX0_INTR [16:16] */ #define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX0_INTR_MASK 0x00010000 #define BCHP_INTR_INTR_MSK_STS_REG_ARM_MBOX0_INTR_SHIFT 16 /* INTR :: INTR_MSK_STS_REG :: reserved2 [15:14] */ #define BCHP_INTR_INTR_MSK_STS_REG_reserved2_MASK 0x0000c000 #define BCHP_INTR_INTR_MSK_STS_REG_reserved2_SHIFT 14 /* INTR :: INTR_MSK_STS_REG :: L1_HIF_RX_DMA_ERR_INTR_MSK [13:13] */ #define BCHP_INTR_INTR_MSK_STS_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_MASK 0x00002000 #define BCHP_INTR_INTR_MSK_STS_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_SHIFT 13 /* INTR :: INTR_MSK_STS_REG :: L1_HIF_RX_DMA_DONE_INTR_MSK [12:12] */ #define BCHP_INTR_INTR_MSK_STS_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_MASK 0x00001000 #define BCHP_INTR_INTR_MSK_STS_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_SHIFT 12 /* INTR :: INTR_MSK_STS_REG :: LIST1_Y_RX_DMA_ERR_INTR_MSK [11:11] */ #define BCHP_INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000800 #define BCHP_INTR_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_SHIFT 11 /* INTR :: INTR_MSK_STS_REG :: L1_Y_RX_DMA_DONE_INTR_MSK [10:10] */ #define BCHP_INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000400 #define BCHP_INTR_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SHIFT 10 /* INTR :: INTR_MSK_STS_REG :: L1_TX_DMA_ERR_INTR_MSK [09:09] */ #define BCHP_INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_MASK 0x00000200 #define BCHP_INTR_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_SHIFT 9 /* INTR :: INTR_MSK_STS_REG :: L1_TX_DMA_DONE_INTR_MSK [08:08] */ #define BCHP_INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_MASK 0x00000100 #define BCHP_INTR_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_SHIFT 8 /* INTR :: INTR_MSK_STS_REG :: reserved3 [07:06] */ #define BCHP_INTR_INTR_MSK_STS_REG_reserved3_MASK 0x000000c0 #define BCHP_INTR_INTR_MSK_STS_REG_reserved3_SHIFT 6 /* INTR :: INTR_MSK_STS_REG :: L0_HIF_RX_DMA_ERR_INTR_MSK [05:05] */ #define BCHP_INTR_INTR_MSK_STS_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_MASK 0x00000020 #define BCHP_INTR_INTR_MSK_STS_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_SHIFT 5 /* INTR :: INTR_MSK_STS_REG :: L0_HIF_RX_DMA_DONE_INTR_MSK [04:04] */ #define BCHP_INTR_INTR_MSK_STS_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_MASK 0x00000010 #define BCHP_INTR_INTR_MSK_STS_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_SHIFT 4 /* INTR :: INTR_MSK_STS_REG :: LIST0_Y_RX_DMA_ERR_INTR_MSK [03:03] */ #define BCHP_INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000008 #define BCHP_INTR_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_SHIFT 3 /* INTR :: INTR_MSK_STS_REG :: L0_Y_RX_DMA_DONE_INTR_MSK [02:02] */ #define BCHP_INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000004 #define BCHP_INTR_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SHIFT 2 /* INTR :: INTR_MSK_STS_REG :: L0_TX_DMA_ERR_INTR_MSK [01:01] */ #define BCHP_INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_MASK 0x00000002 #define BCHP_INTR_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_SHIFT 1 /* INTR :: INTR_MSK_STS_REG :: L0_TX_DMA_DONE_INTR_MSK [00:00] */ #define BCHP_INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_MASK 0x00000001 #define BCHP_INTR_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_SHIFT 0 /*************************************************************************** *INTR_MSK_SET_REG - Interrupt Mask Set Register ***************************************************************************/ /* INTR :: INTR_MSK_SET_REG :: reserved0 [31:27] */ #define BCHP_INTR_INTR_MSK_SET_REG_reserved0_MASK 0xf8000000 #define BCHP_INTR_INTR_MSK_SET_REG_reserved0_SHIFT 27 /* INTR :: INTR_MSK_SET_REG :: HAT_INTR [26:26] */ #define BCHP_INTR_INTR_MSK_SET_REG_HAT_INTR_MASK 0x04000000 #define BCHP_INTR_INTR_MSK_SET_REG_HAT_INTR_SHIFT 26 /* INTR :: INTR_MSK_SET_REG :: PCIE_TGT_CA_ATTN [25:25] */ #define BCHP_INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define BCHP_INTR_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: INTR_MSK_SET_REG :: PCIE_TGT_UR_ATTN [24:24] */ #define BCHP_INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define BCHP_INTR_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: INTR_MSK_SET_REG :: reserved1 [23:20] */ #define BCHP_INTR_INTR_MSK_SET_REG_reserved1_MASK 0x00f00000 #define BCHP_INTR_INTR_MSK_SET_REG_reserved1_SHIFT 20 /* INTR :: INTR_MSK_SET_REG :: ARM_MBOX3_INTR [19:19] */ #define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX3_INTR_MASK 0x00080000 #define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX3_INTR_SHIFT 19 /* INTR :: INTR_MSK_SET_REG :: ARM_MBOX2_INTR [18:18] */ #define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX2_INTR_MASK 0x00040000 #define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX2_INTR_SHIFT 18 /* INTR :: INTR_MSK_SET_REG :: ARM_MBOX1_INTR [17:17] */ #define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX1_INTR_MASK 0x00020000 #define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX1_INTR_SHIFT 17 /* INTR :: INTR_MSK_SET_REG :: ARM_MBOX0_INTR [16:16] */ #define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX0_INTR_MASK 0x00010000 #define BCHP_INTR_INTR_MSK_SET_REG_ARM_MBOX0_INTR_SHIFT 16 /* INTR :: INTR_MSK_SET_REG :: reserved2 [15:14] */ #define BCHP_INTR_INTR_MSK_SET_REG_reserved2_MASK 0x0000c000 #define BCHP_INTR_INTR_MSK_SET_REG_reserved2_SHIFT 14 /* INTR :: INTR_MSK_SET_REG :: L1_HIF_RX_DMA_ERR_INTR_MSK_SET [13:13] */ #define BCHP_INTR_INTR_MSK_SET_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00002000 #define BCHP_INTR_INTR_MSK_SET_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_SET_SHIFT 13 /* INTR :: INTR_MSK_SET_REG :: L1_HIF_RX_DMA_DONE_INTR_MSK_SET [12:12] */ #define BCHP_INTR_INTR_MSK_SET_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00001000 #define BCHP_INTR_INTR_MSK_SET_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_SET_SHIFT 12 /* INTR :: INTR_MSK_SET_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_SET [11:11] */ #define BCHP_INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000800 #define BCHP_INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 11 /* INTR :: INTR_MSK_SET_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_SET [10:10] */ #define BCHP_INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000400 #define BCHP_INTR_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 10 /* INTR :: INTR_MSK_SET_REG :: L1_TX_DMA_ERR_INTR_MSK_SET [09:09] */ #define BCHP_INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000200 #define BCHP_INTR_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_SHIFT 9 /* INTR :: INTR_MSK_SET_REG :: L1_TX_DMA_DONE_INTR_MSK_SET [08:08] */ #define BCHP_INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000100 #define BCHP_INTR_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_SHIFT 8 /* INTR :: INTR_MSK_SET_REG :: reserved3 [07:06] */ #define BCHP_INTR_INTR_MSK_SET_REG_reserved3_MASK 0x000000c0 #define BCHP_INTR_INTR_MSK_SET_REG_reserved3_SHIFT 6 /* INTR :: INTR_MSK_SET_REG :: L0_HIF_RX_DMA_ERR_INTR_MSK_SET [05:05] */ #define BCHP_INTR_INTR_MSK_SET_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000020 #define BCHP_INTR_INTR_MSK_SET_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_SET_SHIFT 5 /* INTR :: INTR_MSK_SET_REG :: L0_HIF_RX_DMA_DONE_INTR_MSK_SET [04:04] */ #define BCHP_INTR_INTR_MSK_SET_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000010 #define BCHP_INTR_INTR_MSK_SET_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_SET_SHIFT 4 /* INTR :: INTR_MSK_SET_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_SET [03:03] */ #define BCHP_INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000008 #define BCHP_INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 3 /* INTR :: INTR_MSK_SET_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_SET [02:02] */ #define BCHP_INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000004 #define BCHP_INTR_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 2 /* INTR :: INTR_MSK_SET_REG :: L0_TX_DMA_ERR_INTR_MSK_SET [01:01] */ #define BCHP_INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000002 #define BCHP_INTR_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_SHIFT 1 /* INTR :: INTR_MSK_SET_REG :: L0_TX_DMA_DONE_INTR_MSK_SET [00:00] */ #define BCHP_INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000001 #define BCHP_INTR_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_SHIFT 0 /*************************************************************************** *INTR_MSK_CLR_REG - Interrupt Mask Clear Register ***************************************************************************/ /* INTR :: INTR_MSK_CLR_REG :: reserved0 [31:27] */ #define BCHP_INTR_INTR_MSK_CLR_REG_reserved0_MASK 0xf8000000 #define BCHP_INTR_INTR_MSK_CLR_REG_reserved0_SHIFT 27 /* INTR :: INTR_MSK_CLR_REG :: HAT_INTR [26:26] */ #define BCHP_INTR_INTR_MSK_CLR_REG_HAT_INTR_MASK 0x04000000 #define BCHP_INTR_INTR_MSK_CLR_REG_HAT_INTR_SHIFT 26 /* INTR :: INTR_MSK_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ #define BCHP_INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define BCHP_INTR_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: INTR_MSK_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ #define BCHP_INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define BCHP_INTR_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: INTR_MSK_CLR_REG :: reserved1 [23:20] */ #define BCHP_INTR_INTR_MSK_CLR_REG_reserved1_MASK 0x00f00000 #define BCHP_INTR_INTR_MSK_CLR_REG_reserved1_SHIFT 20 /* INTR :: INTR_MSK_CLR_REG :: ARM_MBOX3_INTR [19:19] */ #define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX3_INTR_MASK 0x00080000 #define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX3_INTR_SHIFT 19 /* INTR :: INTR_MSK_CLR_REG :: ARM_MBOX2_INTR [18:18] */ #define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX2_INTR_MASK 0x00040000 #define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX2_INTR_SHIFT 18 /* INTR :: INTR_MSK_CLR_REG :: ARM_MBOX1_INTR [17:17] */ #define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX1_INTR_MASK 0x00020000 #define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX1_INTR_SHIFT 17 /* INTR :: INTR_MSK_CLR_REG :: ARM_MBOX0_INTR [16:16] */ #define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX0_INTR_MASK 0x00010000 #define BCHP_INTR_INTR_MSK_CLR_REG_ARM_MBOX0_INTR_SHIFT 16 /* INTR :: INTR_MSK_CLR_REG :: reserved2 [15:14] */ #define BCHP_INTR_INTR_MSK_CLR_REG_reserved2_MASK 0x0000c000 #define BCHP_INTR_INTR_MSK_CLR_REG_reserved2_SHIFT 14 /* INTR :: INTR_MSK_CLR_REG :: L1_HIF_RX_DMA_ERR_INTR_MSK_CLR [13:13] */ #define BCHP_INTR_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00002000 #define BCHP_INTR_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 13 /* INTR :: INTR_MSK_CLR_REG :: L1_HIF_RX_DMA_DONE_INTR_MSK_CLR [12:12] */ #define BCHP_INTR_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00001000 #define BCHP_INTR_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 12 /* INTR :: INTR_MSK_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_CLR [11:11] */ #define BCHP_INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000800 #define BCHP_INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 11 /* INTR :: INTR_MSK_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_CLR [10:10] */ #define BCHP_INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000400 #define BCHP_INTR_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 10 /* INTR :: INTR_MSK_CLR_REG :: L1_TX_DMA_ERR_INTR_MSK_CLR [09:09] */ #define BCHP_INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000200 #define BCHP_INTR_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 9 /* INTR :: INTR_MSK_CLR_REG :: L1_TX_DMA_DONE_INTR_MSK_CLR [08:08] */ #define BCHP_INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000100 #define BCHP_INTR_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 8 /* INTR :: INTR_MSK_CLR_REG :: reserved3 [07:06] */ #define BCHP_INTR_INTR_MSK_CLR_REG_reserved3_MASK 0x000000c0 #define BCHP_INTR_INTR_MSK_CLR_REG_reserved3_SHIFT 6 /* INTR :: INTR_MSK_CLR_REG :: L0_HIF_RX_DMA_ERR_INTR_MSK_CLR [05:05] */ #define BCHP_INTR_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000020 #define BCHP_INTR_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 5 /* INTR :: INTR_MSK_CLR_REG :: L0_HIF_RX_DMA_DONE_INTR_MSK_CLR [04:04] */ #define BCHP_INTR_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000010 #define BCHP_INTR_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 4 /* INTR :: INTR_MSK_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_CLR [03:03] */ #define BCHP_INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000008 #define BCHP_INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 3 /* INTR :: INTR_MSK_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_CLR [02:02] */ #define BCHP_INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000004 #define BCHP_INTR_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 2 /* INTR :: INTR_MSK_CLR_REG :: L0_TX_DMA_ERR_INTR_MSK_CLR [01:01] */ #define BCHP_INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000002 #define BCHP_INTR_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 1 /* INTR :: INTR_MSK_CLR_REG :: L0_TX_DMA_DONE_INTR_MSK_CLR [00:00] */ #define BCHP_INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000001 #define BCHP_INTR_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 0 /*************************************************************************** *EOI_CTRL - End of interrupt control register ***************************************************************************/ /* INTR :: EOI_CTRL :: reserved0 [31:01] */ #define BCHP_INTR_EOI_CTRL_reserved0_MASK 0xfffffffe #define BCHP_INTR_EOI_CTRL_reserved0_SHIFT 1 /* INTR :: EOI_CTRL :: EOI [00:00] */ #define BCHP_INTR_EOI_CTRL_EOI_MASK 0x00000001 #define BCHP_INTR_EOI_CTRL_EOI_SHIFT 0 /*************************************************************************** *CPU_INTR_STATUS - CPU_Interrupt Status Register ***************************************************************************/ /* INTR :: CPU_INTR_STATUS :: reserved0 [31:27] */ #define BCHP_INTR_CPU_INTR_STATUS_reserved0_MASK 0xf8000000 #define BCHP_INTR_CPU_INTR_STATUS_reserved0_SHIFT 27 /* INTR :: CPU_INTR_STATUS :: HAT_INTR [26:26] */ #define BCHP_INTR_CPU_INTR_STATUS_HAT_INTR_MASK 0x04000000 #define BCHP_INTR_CPU_INTR_STATUS_HAT_INTR_SHIFT 26 /* INTR :: CPU_INTR_STATUS :: PCIE_TGT_CA_ATTN [25:25] */ #define BCHP_INTR_CPU_INTR_STATUS_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define BCHP_INTR_CPU_INTR_STATUS_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: CPU_INTR_STATUS :: PCIE_TGT_UR_ATTN [24:24] */ #define BCHP_INTR_CPU_INTR_STATUS_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define BCHP_INTR_CPU_INTR_STATUS_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: CPU_INTR_STATUS :: reserved1 [23:20] */ #define BCHP_INTR_CPU_INTR_STATUS_reserved1_MASK 0x00f00000 #define BCHP_INTR_CPU_INTR_STATUS_reserved1_SHIFT 20 /* INTR :: CPU_INTR_STATUS :: ARM_MBOX3_INTR [19:19] */ #define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX3_INTR_MASK 0x00080000 #define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX3_INTR_SHIFT 19 /* INTR :: CPU_INTR_STATUS :: ARM_MBOX2_INTR [18:18] */ #define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX2_INTR_MASK 0x00040000 #define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX2_INTR_SHIFT 18 /* INTR :: CPU_INTR_STATUS :: ARM_MBOX1_INTR [17:17] */ #define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX1_INTR_MASK 0x00020000 #define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX1_INTR_SHIFT 17 /* INTR :: CPU_INTR_STATUS :: ARM_MBOX0_INTR [16:16] */ #define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX0_INTR_MASK 0x00010000 #define BCHP_INTR_CPU_INTR_STATUS_ARM_MBOX0_INTR_SHIFT 16 /* INTR :: CPU_INTR_STATUS :: reserved2 [15:14] */ #define BCHP_INTR_CPU_INTR_STATUS_reserved2_MASK 0x0000c000 #define BCHP_INTR_CPU_INTR_STATUS_reserved2_SHIFT 14 /* INTR :: CPU_INTR_STATUS :: L1_HIF_RX_DMA_ERR_INTR [13:13] */ #define BCHP_INTR_CPU_INTR_STATUS_L1_HIF_RX_DMA_ERR_INTR_MASK 0x00002000 #define BCHP_INTR_CPU_INTR_STATUS_L1_HIF_RX_DMA_ERR_INTR_SHIFT 13 /* INTR :: CPU_INTR_STATUS :: L1_HIF_RX_DMA_DONE_INTR [12:12] */ #define BCHP_INTR_CPU_INTR_STATUS_L1_HIF_RX_DMA_DONE_INTR_MASK 0x00001000 #define BCHP_INTR_CPU_INTR_STATUS_L1_HIF_RX_DMA_DONE_INTR_SHIFT 12 /* INTR :: CPU_INTR_STATUS :: L1_Y_RX_DMA_ERR_INTR [11:11] */ #define BCHP_INTR_CPU_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK 0x00000800 #define BCHP_INTR_CPU_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_SHIFT 11 /* INTR :: CPU_INTR_STATUS :: L1_Y_RX_DMA_DONE_INTR [10:10] */ #define BCHP_INTR_CPU_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK 0x00000400 #define BCHP_INTR_CPU_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_SHIFT 10 /* INTR :: CPU_INTR_STATUS :: L1_TX_DMA_ERR_INTR [09:09] */ #define BCHP_INTR_CPU_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK 0x00000200 #define BCHP_INTR_CPU_INTR_STATUS_L1_TX_DMA_ERR_INTR_SHIFT 9 /* INTR :: CPU_INTR_STATUS :: L1_TX_DMA_DONE_INTR [08:08] */ #define BCHP_INTR_CPU_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK 0x00000100 #define BCHP_INTR_CPU_INTR_STATUS_L1_TX_DMA_DONE_INTR_SHIFT 8 /* INTR :: CPU_INTR_STATUS :: reserved3 [07:06] */ #define BCHP_INTR_CPU_INTR_STATUS_reserved3_MASK 0x000000c0 #define BCHP_INTR_CPU_INTR_STATUS_reserved3_SHIFT 6 /* INTR :: CPU_INTR_STATUS :: L0_HIF_RX_DMA_ERR_INTR [05:05] */ #define BCHP_INTR_CPU_INTR_STATUS_L0_HIF_RX_DMA_ERR_INTR_MASK 0x00000020 #define BCHP_INTR_CPU_INTR_STATUS_L0_HIF_RX_DMA_ERR_INTR_SHIFT 5 /* INTR :: CPU_INTR_STATUS :: L0_HIF_RX_DMA_DONE_INTR [04:04] */ #define BCHP_INTR_CPU_INTR_STATUS_L0_HIF_RX_DMA_DONE_INTR_MASK 0x00000010 #define BCHP_INTR_CPU_INTR_STATUS_L0_HIF_RX_DMA_DONE_INTR_SHIFT 4 /* INTR :: CPU_INTR_STATUS :: L0_Y_RX_DMA_ERR_INTR [03:03] */ #define BCHP_INTR_CPU_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK 0x00000008 #define BCHP_INTR_CPU_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_SHIFT 3 /* INTR :: CPU_INTR_STATUS :: L0_Y_RX_DMA_DONE_INTR [02:02] */ #define BCHP_INTR_CPU_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK 0x00000004 #define BCHP_INTR_CPU_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_SHIFT 2 /* INTR :: CPU_INTR_STATUS :: L0_TX_DMA_ERR_INTR [01:01] */ #define BCHP_INTR_CPU_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK 0x00000002 #define BCHP_INTR_CPU_INTR_STATUS_L0_TX_DMA_ERR_INTR_SHIFT 1 /* INTR :: CPU_INTR_STATUS :: L0_TX_DMA_DONE_INTR [00:00] */ #define BCHP_INTR_CPU_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK 0x00000001 #define BCHP_INTR_CPU_INTR_STATUS_L0_TX_DMA_DONE_INTR_SHIFT 0 /*************************************************************************** *CPU_INTR_SET - CPU_Interrupt Set Register ***************************************************************************/ /* INTR :: CPU_INTR_SET :: reserved0 [31:27] */ #define BCHP_INTR_CPU_INTR_SET_reserved0_MASK 0xf8000000 #define BCHP_INTR_CPU_INTR_SET_reserved0_SHIFT 27 /* INTR :: CPU_INTR_SET :: HAT_INTR [26:26] */ #define BCHP_INTR_CPU_INTR_SET_HAT_INTR_MASK 0x04000000 #define BCHP_INTR_CPU_INTR_SET_HAT_INTR_SHIFT 26 /* INTR :: CPU_INTR_SET :: PCIE_TGT_CA_ATTN [25:25] */ #define BCHP_INTR_CPU_INTR_SET_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define BCHP_INTR_CPU_INTR_SET_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: CPU_INTR_SET :: PCIE_TGT_UR_ATTN [24:24] */ #define BCHP_INTR_CPU_INTR_SET_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define BCHP_INTR_CPU_INTR_SET_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: CPU_INTR_SET :: reserved1 [23:20] */ #define BCHP_INTR_CPU_INTR_SET_reserved1_MASK 0x00f00000 #define BCHP_INTR_CPU_INTR_SET_reserved1_SHIFT 20 /* INTR :: CPU_INTR_SET :: ARM_MBOX3_INTR [19:19] */ #define BCHP_INTR_CPU_INTR_SET_ARM_MBOX3_INTR_MASK 0x00080000 #define BCHP_INTR_CPU_INTR_SET_ARM_MBOX3_INTR_SHIFT 19 /* INTR :: CPU_INTR_SET :: ARM_MBOX2_INTR [18:18] */ #define BCHP_INTR_CPU_INTR_SET_ARM_MBOX2_INTR_MASK 0x00040000 #define BCHP_INTR_CPU_INTR_SET_ARM_MBOX2_INTR_SHIFT 18 /* INTR :: CPU_INTR_SET :: ARM_MBOX1_INTR [17:17] */ #define BCHP_INTR_CPU_INTR_SET_ARM_MBOX1_INTR_MASK 0x00020000 #define BCHP_INTR_CPU_INTR_SET_ARM_MBOX1_INTR_SHIFT 17 /* INTR :: CPU_INTR_SET :: ARM_MBOX0_INTR [16:16] */ #define BCHP_INTR_CPU_INTR_SET_ARM_MBOX0_INTR_MASK 0x00010000 #define BCHP_INTR_CPU_INTR_SET_ARM_MBOX0_INTR_SHIFT 16 /* INTR :: CPU_INTR_SET :: reserved2 [15:14] */ #define BCHP_INTR_CPU_INTR_SET_reserved2_MASK 0x0000c000 #define BCHP_INTR_CPU_INTR_SET_reserved2_SHIFT 14 /* INTR :: CPU_INTR_SET :: HIF_RX_DMA_L1_ERR_INTR [13:13] */ #define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L1_ERR_INTR_MASK 0x00002000 #define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L1_ERR_INTR_SHIFT 13 /* INTR :: CPU_INTR_SET :: HIF_RX_DMA_L1_DONE_INTR [12:12] */ #define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L1_DONE_INTR_MASK 0x00001000 #define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L1_DONE_INTR_SHIFT 12 /* INTR :: CPU_INTR_SET :: Y_RX_DMA_L1_ERR_INTR [11:11] */ #define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L1_ERR_INTR_MASK 0x00000800 #define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L1_ERR_INTR_SHIFT 11 /* INTR :: CPU_INTR_SET :: Y_RX_DMA_L1_DONE_INTR [10:10] */ #define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L1_DONE_INTR_MASK 0x00000400 #define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L1_DONE_INTR_SHIFT 10 /* INTR :: CPU_INTR_SET :: TX_DMA_L1_ERR_INTR [09:09] */ #define BCHP_INTR_CPU_INTR_SET_TX_DMA_L1_ERR_INTR_MASK 0x00000200 #define BCHP_INTR_CPU_INTR_SET_TX_DMA_L1_ERR_INTR_SHIFT 9 /* INTR :: CPU_INTR_SET :: TX_DMA_L1_DONE_INTR [08:08] */ #define BCHP_INTR_CPU_INTR_SET_TX_DMA_L1_DONE_INTR_MASK 0x00000100 #define BCHP_INTR_CPU_INTR_SET_TX_DMA_L1_DONE_INTR_SHIFT 8 /* INTR :: CPU_INTR_SET :: reserved3 [07:06] */ #define BCHP_INTR_CPU_INTR_SET_reserved3_MASK 0x000000c0 #define BCHP_INTR_CPU_INTR_SET_reserved3_SHIFT 6 /* INTR :: CPU_INTR_SET :: HIF_RX_DMA_L0_ERR_INTR [05:05] */ #define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L0_ERR_INTR_MASK 0x00000020 #define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L0_ERR_INTR_SHIFT 5 /* INTR :: CPU_INTR_SET :: HIF_RX_DMA_L0_DONE_INTR [04:04] */ #define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L0_DONE_INTR_MASK 0x00000010 #define BCHP_INTR_CPU_INTR_SET_HIF_RX_DMA_L0_DONE_INTR_SHIFT 4 /* INTR :: CPU_INTR_SET :: Y_RX_DMA_L0_ERR_INTR [03:03] */ #define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L0_ERR_INTR_MASK 0x00000008 #define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L0_ERR_INTR_SHIFT 3 /* INTR :: CPU_INTR_SET :: Y_RX_DMA_L0_DONE_INTR [02:02] */ #define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L0_DONE_INTR_MASK 0x00000004 #define BCHP_INTR_CPU_INTR_SET_Y_RX_DMA_L0_DONE_INTR_SHIFT 2 /* INTR :: CPU_INTR_SET :: TX_DMA_L0_ERR_INTR [01:01] */ #define BCHP_INTR_CPU_INTR_SET_TX_DMA_L0_ERR_INTR_MASK 0x00000002 #define BCHP_INTR_CPU_INTR_SET_TX_DMA_L0_ERR_INTR_SHIFT 1 /* INTR :: CPU_INTR_SET :: TX_DMA_L0_DONE_INTR [00:00] */ #define BCHP_INTR_CPU_INTR_SET_TX_DMA_L0_DONE_INTR_MASK 0x00000001 #define BCHP_INTR_CPU_INTR_SET_TX_DMA_L0_DONE_INTR_SHIFT 0 /*************************************************************************** *CPU_INTR_CLR_REG - CPU_Interrupt Clear Register ***************************************************************************/ /* INTR :: CPU_INTR_CLR_REG :: reserved0 [31:27] */ #define BCHP_INTR_CPU_INTR_CLR_REG_reserved0_MASK 0xf8000000 #define BCHP_INTR_CPU_INTR_CLR_REG_reserved0_SHIFT 27 /* INTR :: CPU_INTR_CLR_REG :: HAT_INTR [26:26] */ #define BCHP_INTR_CPU_INTR_CLR_REG_HAT_INTR_MASK 0x04000000 #define BCHP_INTR_CPU_INTR_CLR_REG_HAT_INTR_SHIFT 26 /* INTR :: CPU_INTR_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ #define BCHP_INTR_CPU_INTR_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define BCHP_INTR_CPU_INTR_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: CPU_INTR_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ #define BCHP_INTR_CPU_INTR_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define BCHP_INTR_CPU_INTR_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: CPU_INTR_CLR_REG :: reserved1 [23:20] */ #define BCHP_INTR_CPU_INTR_CLR_REG_reserved1_MASK 0x00f00000 #define BCHP_INTR_CPU_INTR_CLR_REG_reserved1_SHIFT 20 /* INTR :: CPU_INTR_CLR_REG :: ARM_MBOX3_INTR [19:19] */ #define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX3_INTR_MASK 0x00080000 #define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX3_INTR_SHIFT 19 /* INTR :: CPU_INTR_CLR_REG :: ARM_MBOX2_INTR [18:18] */ #define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX2_INTR_MASK 0x00040000 #define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX2_INTR_SHIFT 18 /* INTR :: CPU_INTR_CLR_REG :: ARM_MBOX1_INTR [17:17] */ #define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX1_INTR_MASK 0x00020000 #define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX1_INTR_SHIFT 17 /* INTR :: CPU_INTR_CLR_REG :: ARM_MBOX0_INTR [16:16] */ #define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX0_INTR_MASK 0x00010000 #define BCHP_INTR_CPU_INTR_CLR_REG_ARM_MBOX0_INTR_SHIFT 16 /* INTR :: CPU_INTR_CLR_REG :: reserved2 [15:14] */ #define BCHP_INTR_CPU_INTR_CLR_REG_reserved2_MASK 0x0000c000 #define BCHP_INTR_CPU_INTR_CLR_REG_reserved2_SHIFT 14 /* INTR :: CPU_INTR_CLR_REG :: L1_HIF_RX_DMA_ERR_INTR_CLR [13:13] */ #define BCHP_INTR_CPU_INTR_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_CLR_MASK 0x00002000 #define BCHP_INTR_CPU_INTR_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_CLR_SHIFT 13 /* INTR :: CPU_INTR_CLR_REG :: L1_HIF_RX_DMA_DONE_INTR_CLR [12:12] */ #define BCHP_INTR_CPU_INTR_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_CLR_MASK 0x00001000 #define BCHP_INTR_CPU_INTR_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_CLR_SHIFT 12 /* INTR :: CPU_INTR_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_CLR [11:11] */ #define BCHP_INTR_CPU_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000800 #define BCHP_INTR_CPU_INTR_CLR_REG_L1_Y_RX_DMA_ERR_INTR_CLR_SHIFT 11 /* INTR :: CPU_INTR_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_CLR [10:10] */ #define BCHP_INTR_CPU_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000400 #define BCHP_INTR_CPU_INTR_CLR_REG_L1_Y_RX_DMA_DONE_INTR_CLR_SHIFT 10 /* INTR :: CPU_INTR_CLR_REG :: L1_TX_DMA_ERR_INTR_CLR [09:09] */ #define BCHP_INTR_CPU_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_MASK 0x00000200 #define BCHP_INTR_CPU_INTR_CLR_REG_L1_TX_DMA_ERR_INTR_CLR_SHIFT 9 /* INTR :: CPU_INTR_CLR_REG :: L1_TX_DMA_DONE_INTR_CLR [08:08] */ #define BCHP_INTR_CPU_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_MASK 0x00000100 #define BCHP_INTR_CPU_INTR_CLR_REG_L1_TX_DMA_DONE_INTR_CLR_SHIFT 8 /* INTR :: CPU_INTR_CLR_REG :: reserved3 [07:06] */ #define BCHP_INTR_CPU_INTR_CLR_REG_reserved3_MASK 0x000000c0 #define BCHP_INTR_CPU_INTR_CLR_REG_reserved3_SHIFT 6 /* INTR :: CPU_INTR_CLR_REG :: L0_HIF_RX_DMA_ERR_INTR_CLR [05:05] */ #define BCHP_INTR_CPU_INTR_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_CLR_MASK 0x00000020 #define BCHP_INTR_CPU_INTR_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_CLR_SHIFT 5 /* INTR :: CPU_INTR_CLR_REG :: L0_HIF_RX_DMA_DONE_INTR_CLR [04:04] */ #define BCHP_INTR_CPU_INTR_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_CLR_MASK 0x00000010 #define BCHP_INTR_CPU_INTR_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_CLR_SHIFT 4 /* INTR :: CPU_INTR_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_CLR [03:03] */ #define BCHP_INTR_CPU_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_MASK 0x00000008 #define BCHP_INTR_CPU_INTR_CLR_REG_L0_Y_RX_DMA_ERR_INTR_CLR_SHIFT 3 /* INTR :: CPU_INTR_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_CLR [02:02] */ #define BCHP_INTR_CPU_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_MASK 0x00000004 #define BCHP_INTR_CPU_INTR_CLR_REG_L0_Y_RX_DMA_DONE_INTR_CLR_SHIFT 2 /* INTR :: CPU_INTR_CLR_REG :: L0_TX_DMA_ERR_INTR_CLR [01:01] */ #define BCHP_INTR_CPU_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_MASK 0x00000002 #define BCHP_INTR_CPU_INTR_CLR_REG_L0_TX_DMA_ERR_INTR_CLR_SHIFT 1 /* INTR :: CPU_INTR_CLR_REG :: L0_TX_DMA_DONE_INTR_CLR [00:00] */ #define BCHP_INTR_CPU_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_MASK 0x00000001 #define BCHP_INTR_CPU_INTR_CLR_REG_L0_TX_DMA_DONE_INTR_CLR_SHIFT 0 /*************************************************************************** *CPU_INTR_MSK_STS_REG - CPU_Interrupt Mask Status Register ***************************************************************************/ /* INTR :: CPU_INTR_MSK_STS_REG :: reserved0 [31:27] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved0_MASK 0xf8000000 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved0_SHIFT 27 /* INTR :: CPU_INTR_MSK_STS_REG :: HAT_INTR [26:26] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_HAT_INTR_MASK 0x04000000 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_HAT_INTR_SHIFT 26 /* INTR :: CPU_INTR_MSK_STS_REG :: PCIE_TGT_CA_ATTN [25:25] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: CPU_INTR_MSK_STS_REG :: PCIE_TGT_UR_ATTN [24:24] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: CPU_INTR_MSK_STS_REG :: reserved1 [23:20] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved1_MASK 0x00f00000 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved1_SHIFT 20 /* INTR :: CPU_INTR_MSK_STS_REG :: ARM_MBOX3_INTR [19:19] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX3_INTR_MASK 0x00080000 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX3_INTR_SHIFT 19 /* INTR :: CPU_INTR_MSK_STS_REG :: ARM_MBOX2_INTR [18:18] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX2_INTR_MASK 0x00040000 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX2_INTR_SHIFT 18 /* INTR :: CPU_INTR_MSK_STS_REG :: ARM_MBOX1_INTR [17:17] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX1_INTR_MASK 0x00020000 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX1_INTR_SHIFT 17 /* INTR :: CPU_INTR_MSK_STS_REG :: ARM_MBOX0_INTR [16:16] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX0_INTR_MASK 0x00010000 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_ARM_MBOX0_INTR_SHIFT 16 /* INTR :: CPU_INTR_MSK_STS_REG :: reserved2 [15:14] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved2_MASK 0x0000c000 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved2_SHIFT 14 /* INTR :: CPU_INTR_MSK_STS_REG :: L1_HIF_RX_DMA_ERR_INTR_MSK [13:13] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_MASK 0x00002000 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_SHIFT 13 /* INTR :: CPU_INTR_MSK_STS_REG :: L1_HIF_RX_DMA_DONE_INTR_MSK [12:12] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_MASK 0x00001000 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_SHIFT 12 /* INTR :: CPU_INTR_MSK_STS_REG :: LIST1_Y_RX_DMA_ERR_INTR_MSK [11:11] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000800 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_LIST1_Y_RX_DMA_ERR_INTR_MSK_SHIFT 11 /* INTR :: CPU_INTR_MSK_STS_REG :: L1_Y_RX_DMA_DONE_INTR_MSK [10:10] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000400 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SHIFT 10 /* INTR :: CPU_INTR_MSK_STS_REG :: L1_TX_DMA_ERR_INTR_MSK [09:09] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_MASK 0x00000200 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_TX_DMA_ERR_INTR_MSK_SHIFT 9 /* INTR :: CPU_INTR_MSK_STS_REG :: L1_TX_DMA_DONE_INTR_MSK [08:08] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_MASK 0x00000100 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L1_TX_DMA_DONE_INTR_MSK_SHIFT 8 /* INTR :: CPU_INTR_MSK_STS_REG :: reserved3 [07:06] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved3_MASK 0x000000c0 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_reserved3_SHIFT 6 /* INTR :: CPU_INTR_MSK_STS_REG :: L0_HIF_RX_DMA_ERR_INTR_MSK [05:05] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_MASK 0x00000020 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_SHIFT 5 /* INTR :: CPU_INTR_MSK_STS_REG :: L0_HIF_RX_DMA_DONE_INTR_MSK [04:04] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_MASK 0x00000010 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_SHIFT 4 /* INTR :: CPU_INTR_MSK_STS_REG :: LIST0_Y_RX_DMA_ERR_INTR_MSK [03:03] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_MASK 0x00000008 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_LIST0_Y_RX_DMA_ERR_INTR_MSK_SHIFT 3 /* INTR :: CPU_INTR_MSK_STS_REG :: L0_Y_RX_DMA_DONE_INTR_MSK [02:02] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_MASK 0x00000004 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SHIFT 2 /* INTR :: CPU_INTR_MSK_STS_REG :: L0_TX_DMA_ERR_INTR_MSK [01:01] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_MASK 0x00000002 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_TX_DMA_ERR_INTR_MSK_SHIFT 1 /* INTR :: CPU_INTR_MSK_STS_REG :: L0_TX_DMA_DONE_INTR_MSK [00:00] */ #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_MASK 0x00000001 #define BCHP_INTR_CPU_INTR_MSK_STS_REG_L0_TX_DMA_DONE_INTR_MSK_SHIFT 0 /*************************************************************************** *CPU_INTR_MSK_SET_REG - CPU Interrupt Mask Set Register ***************************************************************************/ /* INTR :: CPU_INTR_MSK_SET_REG :: reserved0 [31:27] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved0_MASK 0xf8000000 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved0_SHIFT 27 /* INTR :: CPU_INTR_MSK_SET_REG :: HAT_INTR [26:26] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_HAT_INTR_MASK 0x04000000 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_HAT_INTR_SHIFT 26 /* INTR :: CPU_INTR_MSK_SET_REG :: PCIE_TGT_CA_ATTN [25:25] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: CPU_INTR_MSK_SET_REG :: PCIE_TGT_UR_ATTN [24:24] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: CPU_INTR_MSK_SET_REG :: reserved1 [23:20] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved1_MASK 0x00f00000 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved1_SHIFT 20 /* INTR :: CPU_INTR_MSK_SET_REG :: ARM_MBOX3_INTR [19:19] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX3_INTR_MASK 0x00080000 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX3_INTR_SHIFT 19 /* INTR :: CPU_INTR_MSK_SET_REG :: ARM_MBOX2_INTR [18:18] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX2_INTR_MASK 0x00040000 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX2_INTR_SHIFT 18 /* INTR :: CPU_INTR_MSK_SET_REG :: ARM_MBOX1_INTR [17:17] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX1_INTR_MASK 0x00020000 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX1_INTR_SHIFT 17 /* INTR :: CPU_INTR_MSK_SET_REG :: ARM_MBOX0_INTR [16:16] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX0_INTR_MASK 0x00010000 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_ARM_MBOX0_INTR_SHIFT 16 /* INTR :: CPU_INTR_MSK_SET_REG :: reserved2 [15:14] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved2_MASK 0x0000c000 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved2_SHIFT 14 /* INTR :: CPU_INTR_MSK_SET_REG :: L1_HIF_RX_DMA_ERR_INTR_MSK_SET [13:13] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00002000 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_SET_SHIFT 13 /* INTR :: CPU_INTR_MSK_SET_REG :: L1_HIF_RX_DMA_DONE_INTR_MSK_SET [12:12] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00001000 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_SET_SHIFT 12 /* INTR :: CPU_INTR_MSK_SET_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_SET [11:11] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000800 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 11 /* INTR :: CPU_INTR_MSK_SET_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_SET [10:10] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000400 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 10 /* INTR :: CPU_INTR_MSK_SET_REG :: L1_TX_DMA_ERR_INTR_MSK_SET [09:09] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000200 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_TX_DMA_ERR_INTR_MSK_SET_SHIFT 9 /* INTR :: CPU_INTR_MSK_SET_REG :: L1_TX_DMA_DONE_INTR_MSK_SET [08:08] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000100 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L1_TX_DMA_DONE_INTR_MSK_SET_SHIFT 8 /* INTR :: CPU_INTR_MSK_SET_REG :: reserved3 [07:06] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved3_MASK 0x000000c0 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_reserved3_SHIFT 6 /* INTR :: CPU_INTR_MSK_SET_REG :: L0_HIF_RX_DMA_ERR_INTR_MSK_SET [05:05] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000020 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_SET_SHIFT 5 /* INTR :: CPU_INTR_MSK_SET_REG :: L0_HIF_RX_DMA_DONE_INTR_MSK_SET [04:04] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000010 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_SET_SHIFT 4 /* INTR :: CPU_INTR_MSK_SET_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_SET [03:03] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_MASK 0x00000008 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_Y_RX_DMA_ERR_INTR_MSK_SET_SHIFT 3 /* INTR :: CPU_INTR_MSK_SET_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_SET [02:02] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_MASK 0x00000004 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_Y_RX_DMA_DONE_INTR_MSK_SET_SHIFT 2 /* INTR :: CPU_INTR_MSK_SET_REG :: L0_TX_DMA_ERR_INTR_MSK_SET [01:01] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_MASK 0x00000002 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_TX_DMA_ERR_INTR_MSK_SET_SHIFT 1 /* INTR :: CPU_INTR_MSK_SET_REG :: L0_TX_DMA_DONE_INTR_MSK_SET [00:00] */ #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_MASK 0x00000001 #define BCHP_INTR_CPU_INTR_MSK_SET_REG_L0_TX_DMA_DONE_INTR_MSK_SET_SHIFT 0 /*************************************************************************** *CPU_INTR_MSK_CLR_REG - CPU Interrupt Mask Clear Register ***************************************************************************/ /* INTR :: CPU_INTR_MSK_CLR_REG :: reserved0 [31:27] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved0_MASK 0xf8000000 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved0_SHIFT 27 /* INTR :: CPU_INTR_MSK_CLR_REG :: HAT_INTR [26:26] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_HAT_INTR_MASK 0x04000000 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_HAT_INTR_SHIFT 26 /* INTR :: CPU_INTR_MSK_CLR_REG :: PCIE_TGT_CA_ATTN [25:25] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_MASK 0x02000000 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_PCIE_TGT_CA_ATTN_SHIFT 25 /* INTR :: CPU_INTR_MSK_CLR_REG :: PCIE_TGT_UR_ATTN [24:24] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_MASK 0x01000000 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_PCIE_TGT_UR_ATTN_SHIFT 24 /* INTR :: CPU_INTR_MSK_CLR_REG :: reserved1 [23:20] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved1_MASK 0x00f00000 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved1_SHIFT 20 /* INTR :: CPU_INTR_MSK_CLR_REG :: ARM_MBOX3_INTR [19:19] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX3_INTR_MASK 0x00080000 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX3_INTR_SHIFT 19 /* INTR :: CPU_INTR_MSK_CLR_REG :: ARM_MBOX2_INTR [18:18] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX2_INTR_MASK 0x00040000 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX2_INTR_SHIFT 18 /* INTR :: CPU_INTR_MSK_CLR_REG :: ARM_MBOX1_INTR [17:17] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX1_INTR_MASK 0x00020000 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX1_INTR_SHIFT 17 /* INTR :: CPU_INTR_MSK_CLR_REG :: ARM_MBOX0_INTR [16:16] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX0_INTR_MASK 0x00010000 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_ARM_MBOX0_INTR_SHIFT 16 /* INTR :: CPU_INTR_MSK_CLR_REG :: reserved2 [15:14] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved2_MASK 0x0000c000 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved2_SHIFT 14 /* INTR :: CPU_INTR_MSK_CLR_REG :: L1_HIF_RX_DMA_ERR_INTR_MSK_CLR [13:13] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00002000 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 13 /* INTR :: CPU_INTR_MSK_CLR_REG :: L1_HIF_RX_DMA_DONE_INTR_MSK_CLR [12:12] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00001000 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_HIF_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 12 /* INTR :: CPU_INTR_MSK_CLR_REG :: L1_Y_RX_DMA_ERR_INTR_MSK_CLR [11:11] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000800 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 11 /* INTR :: CPU_INTR_MSK_CLR_REG :: L1_Y_RX_DMA_DONE_INTR_MSK_CLR [10:10] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000400 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 10 /* INTR :: CPU_INTR_MSK_CLR_REG :: L1_TX_DMA_ERR_INTR_MSK_CLR [09:09] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000200 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 9 /* INTR :: CPU_INTR_MSK_CLR_REG :: L1_TX_DMA_DONE_INTR_MSK_CLR [08:08] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000100 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L1_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 8 /* INTR :: CPU_INTR_MSK_CLR_REG :: reserved3 [07:06] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved3_MASK 0x000000c0 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_reserved3_SHIFT 6 /* INTR :: CPU_INTR_MSK_CLR_REG :: L0_HIF_RX_DMA_ERR_INTR_MSK_CLR [05:05] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000020 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 5 /* INTR :: CPU_INTR_MSK_CLR_REG :: L0_HIF_RX_DMA_DONE_INTR_MSK_CLR [04:04] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000010 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_HIF_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 4 /* INTR :: CPU_INTR_MSK_CLR_REG :: L0_Y_RX_DMA_ERR_INTR_MSK_CLR [03:03] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000008 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_Y_RX_DMA_ERR_INTR_MSK_CLR_SHIFT 3 /* INTR :: CPU_INTR_MSK_CLR_REG :: L0_Y_RX_DMA_DONE_INTR_MSK_CLR [02:02] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000004 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_Y_RX_DMA_DONE_INTR_MSK_CLR_SHIFT 2 /* INTR :: CPU_INTR_MSK_CLR_REG :: L0_TX_DMA_ERR_INTR_MSK_CLR [01:01] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_MASK 0x00000002 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_TX_DMA_ERR_INTR_MSK_CLR_SHIFT 1 /* INTR :: CPU_INTR_MSK_CLR_REG :: L0_TX_DMA_DONE_INTR_MSK_CLR [00:00] */ #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_MASK 0x00000001 #define BCHP_INTR_CPU_INTR_MSK_CLR_REG_L0_TX_DMA_DONE_INTR_MSK_CLR_SHIFT 0 #endif /* #ifndef BCHP_INTR_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015300000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_bus_if.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_bu0000644000175000017500000003274211610313111031047 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_xpt_bus_if.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:23p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:14 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_bus_if.h $ * * Hydra_Software_Devel/1 7/17/09 8:23p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_XPT_BUS_IF_H__ #define BCHP_XPT_BUS_IF_H__ /*************************************************************************** *XPT_BUS_IF - Data Transport Configuration Registers ***************************************************************************/ #define BCHP_XPT_BUS_IF_MISC_CTRL0 0x00200000 /* Data Transport Misc Control 0 Register */ #define BCHP_XPT_BUS_IF_TEST_MODE 0x00200004 /* Data transport test register */ #define BCHP_XPT_BUS_IF_REV_ID 0x00200008 /* Data Transport Revision Register */ #define BCHP_XPT_BUS_IF_INTR_STATUS4_REG 0x00200038 /* Interrupt Status4 Register */ #define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN 0x0020003c /* Interrupt Status4 Enable Register */ #define BCHP_XPT_BUS_IF_INTR_STATUS5_REG 0x00200040 /* Interrupt Status5 Register */ #define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN 0x00200044 /* Interrupt Status5 Enable Register */ #define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG 0x00200048 /* LCIF to XMEMIF Debug Registers */ #define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG 0x0020004c /* LCIF to XMEMIF Debug Registers */ #define BCHP_XPT_BUS_IF_MAX_PLAYBACKS 0x00200050 /* Data Transport max number of playbacks supported */ #define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS 0x00200058 /* Data Transport max number of PID channels supported */ #define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS 0x00200064 /* Data Transport max number of TPIT channels supported */ #define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS 0x00200068 /* Data Transport max number of RAVE contexts supported */ #define BCHP_XPT_BUS_IF_MAX_SCDS 0x00200074 /* Data Transport max number of SCDs supported */ /*************************************************************************** *MISC_CTRL0 - Data Transport Misc Control 0 Register ***************************************************************************/ /* XPT_BUS_IF :: MISC_CTRL0 :: reserved0 [31:03] */ #define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved0_MASK 0xfffffff8 #define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved0_SHIFT 3 /* XPT_BUS_IF :: MISC_CTRL0 :: ERROR_INT_TEST_MODE [02:02] */ #define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_MASK 0x00000004 #define BCHP_XPT_BUS_IF_MISC_CTRL0_ERROR_INT_TEST_MODE_SHIFT 2 /* XPT_BUS_IF :: MISC_CTRL0 :: reserved1 [01:01] */ #define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved1_MASK 0x00000002 #define BCHP_XPT_BUS_IF_MISC_CTRL0_reserved1_SHIFT 1 /* XPT_BUS_IF :: MISC_CTRL0 :: LINK_LIST_DESC_ENDIAN_CTRL [00:00] */ #define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_MASK 0x00000001 #define BCHP_XPT_BUS_IF_MISC_CTRL0_LINK_LIST_DESC_ENDIAN_CTRL_SHIFT 0 /*************************************************************************** *TEST_MODE - Data transport test register ***************************************************************************/ /* XPT_BUS_IF :: TEST_MODE :: reserved0 [31:01] */ #define BCHP_XPT_BUS_IF_TEST_MODE_reserved0_MASK 0xfffffffe #define BCHP_XPT_BUS_IF_TEST_MODE_reserved0_SHIFT 1 /* XPT_BUS_IF :: TEST_MODE :: PSG_SECRET_ENBLE [00:00] */ #define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_MASK 0x00000001 #define BCHP_XPT_BUS_IF_TEST_MODE_PSG_SECRET_ENBLE_SHIFT 0 /*************************************************************************** *REV_ID - Data Transport Revision Register ***************************************************************************/ /* XPT_BUS_IF :: REV_ID :: reserved0 [31:16] */ #define BCHP_XPT_BUS_IF_REV_ID_reserved0_MASK 0xffff0000 #define BCHP_XPT_BUS_IF_REV_ID_reserved0_SHIFT 16 /* XPT_BUS_IF :: REV_ID :: MAJOR_REV_NUMBER [15:08] */ #define BCHP_XPT_BUS_IF_REV_ID_MAJOR_REV_NUMBER_MASK 0x0000ff00 #define BCHP_XPT_BUS_IF_REV_ID_MAJOR_REV_NUMBER_SHIFT 8 /* XPT_BUS_IF :: REV_ID :: MINOR_REV_NUMBER [07:00] */ #define BCHP_XPT_BUS_IF_REV_ID_MINOR_REV_NUMBER_MASK 0x000000ff #define BCHP_XPT_BUS_IF_REV_ID_MINOR_REV_NUMBER_SHIFT 0 /*************************************************************************** *INTR_STATUS4_REG - Interrupt Status4 Register ***************************************************************************/ /* XPT_BUS_IF :: INTR_STATUS4_REG :: reserved0 [31:15] */ #define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved0_MASK 0xffff8000 #define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved0_SHIFT 15 /* XPT_BUS_IF :: INTR_STATUS4_REG :: GISB_BRIDGE [14:14] */ #define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_MASK 0x00004000 #define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_GISB_BRIDGE_SHIFT 14 /* XPT_BUS_IF :: INTR_STATUS4_REG :: reserved1 [13:00] */ #define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved1_MASK 0x00003fff #define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_reserved1_SHIFT 0 /*************************************************************************** *INTR_STATUS4_REG_EN - Interrupt Status4 Enable Register ***************************************************************************/ /* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: reserved0 [31:15] */ #define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved0_MASK 0xffff8000 #define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved0_SHIFT 15 /* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: INTR_STATUS4_REG_EN [14:14] */ #define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_INTR_STATUS4_REG_EN_MASK 0x00004000 #define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_INTR_STATUS4_REG_EN_SHIFT 14 /* XPT_BUS_IF :: INTR_STATUS4_REG_EN :: reserved1 [13:00] */ #define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved1_MASK 0x00003fff #define BCHP_XPT_BUS_IF_INTR_STATUS4_REG_EN_reserved1_SHIFT 0 /*************************************************************************** *INTR_STATUS5_REG - Interrupt Status5 Register ***************************************************************************/ /* XPT_BUS_IF :: INTR_STATUS5_REG :: reserved0 [31:01] */ #define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_reserved0_MASK 0xfffffffe #define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_reserved0_SHIFT 1 /* XPT_BUS_IF :: INTR_STATUS5_REG :: WRCHECKER_INT [00:00] */ #define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_MASK 0x00000001 #define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_WRCHECKER_INT_SHIFT 0 /*************************************************************************** *INTR_STATUS5_REG_EN - Interrupt Status5 Enable Register ***************************************************************************/ /* XPT_BUS_IF :: INTR_STATUS5_REG_EN :: reserved0 [31:01] */ #define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_reserved0_MASK 0xfffffffe #define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_reserved0_SHIFT 1 /* XPT_BUS_IF :: INTR_STATUS5_REG_EN :: INTR_STATUS5_REG_EN [00:00] */ #define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_INTR_STATUS5_REG_EN_MASK 0x00000001 #define BCHP_XPT_BUS_IF_INTR_STATUS5_REG_EN_INTR_STATUS5_REG_EN_SHIFT 0 /*************************************************************************** *XMEMIF_RD_LC_DEBUG_REG - LCIF to XMEMIF Debug Registers ***************************************************************************/ /* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG :: reserved0 [31:13] */ #define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_reserved0_MASK 0xffffe000 #define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_reserved0_SHIFT 13 /* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG :: PB_DEBUG_REG [12:08] */ #define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_PB_DEBUG_REG_MASK 0x00001f00 #define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_PB_DEBUG_REG_SHIFT 8 /* XPT_BUS_IF :: XMEMIF_RD_LC_DEBUG_REG :: reserved1 [07:00] */ #define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_reserved1_MASK 0x000000ff #define BCHP_XPT_BUS_IF_XMEMIF_RD_LC_DEBUG_REG_reserved1_SHIFT 0 /*************************************************************************** *XMEMIF_WR_LC_DEBUG_REG - LCIF to XMEMIF Debug Registers ***************************************************************************/ /* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: reserved0 [31:02] */ #define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_reserved0_MASK 0xfffffffc #define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_reserved0_SHIFT 2 /* XPT_BUS_IF :: XMEMIF_WR_LC_DEBUG_REG :: RAVE_DEBUG_REG [01:00] */ #define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_MASK 0x00000003 #define BCHP_XPT_BUS_IF_XMEMIF_WR_LC_DEBUG_REG_RAVE_DEBUG_REG_SHIFT 0 /*************************************************************************** *MAX_PLAYBACKS - Data Transport max number of playbacks supported ***************************************************************************/ /* XPT_BUS_IF :: MAX_PLAYBACKS :: reserved0 [31:04] */ #define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_reserved0_MASK 0xfffffff0 #define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_reserved0_SHIFT 4 /* XPT_BUS_IF :: MAX_PLAYBACKS :: MAX_PLAYBACKS [03:00] */ #define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_MASK 0x0000000f #define BCHP_XPT_BUS_IF_MAX_PLAYBACKS_MAX_PLAYBACKS_SHIFT 0 /*************************************************************************** *MAX_PID_CHANNELS - Data Transport max number of PID channels supported ***************************************************************************/ /* XPT_BUS_IF :: MAX_PID_CHANNELS :: reserved0 [31:12] */ #define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_reserved0_MASK 0xfffff000 #define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_reserved0_SHIFT 12 /* XPT_BUS_IF :: MAX_PID_CHANNELS :: MAX_PID_CHANNELS [11:00] */ #define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_MASK 0x00000fff #define BCHP_XPT_BUS_IF_MAX_PID_CHANNELS_MAX_PID_CHANNELS_SHIFT 0 /*************************************************************************** *MAX_TPIT_CHANNELS - Data Transport max number of TPIT channels supported ***************************************************************************/ /* XPT_BUS_IF :: MAX_TPIT_CHANNELS :: reserved0 [31:04] */ #define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_reserved0_MASK 0xfffffff0 #define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_reserved0_SHIFT 4 /* XPT_BUS_IF :: MAX_TPIT_CHANNELS :: MAX_TPIT_CHANNELS [03:00] */ #define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_MASK 0x0000000f #define BCHP_XPT_BUS_IF_MAX_TPIT_CHANNELS_MAX_TPIT_CHANNELS_SHIFT 0 /*************************************************************************** *MAX_RAVE_CONTEXTS - Data Transport max number of RAVE contexts supported ***************************************************************************/ /* XPT_BUS_IF :: MAX_RAVE_CONTEXTS :: reserved0 [31:08] */ #define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_reserved0_MASK 0xffffff00 #define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_reserved0_SHIFT 8 /* XPT_BUS_IF :: MAX_RAVE_CONTEXTS :: MAX_RAVE_CONTEXTS [07:00] */ #define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_MASK 0x000000ff #define BCHP_XPT_BUS_IF_MAX_RAVE_CONTEXTS_MAX_RAVE_CONTEXTS_SHIFT 0 /*************************************************************************** *MAX_SCDS - Data Transport max number of SCDs supported ***************************************************************************/ /* XPT_BUS_IF :: MAX_SCDS :: reserved0 [31:08] */ #define BCHP_XPT_BUS_IF_MAX_SCDS_reserved0_MASK 0xffffff00 #define BCHP_XPT_BUS_IF_MAX_SCDS_reserved0_SHIFT 8 /* XPT_BUS_IF :: MAX_SCDS :: MAX_SCDS [07:00] */ #define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_MASK 0x000000ff #define BCHP_XPT_BUS_IF_MAX_SCDS_MAX_SCDS_SHIFT 0 #endif /* #ifndef BCHP_XPT_BUS_IF_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015300000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_triple_sec.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_triple0000644000175000017500000000607011610313111031040 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_triple_sec.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:22p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:03 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_triple_sec.h $ * * Hydra_Software_Devel/1 7/17/09 8:22p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_TRIPLE_SEC_H__ #define BCHP_TRIPLE_SEC_H__ /*************************************************************************** *TRIPLE_SEC - TRIPLE_SEC Registers ***************************************************************************/ #define BCHP_TRIPLE_SEC_RSV_S 0x000ff000 /* RESERVED */ #define BCHP_TRIPLE_SEC_RSV_E 0x000ff4fc /* RESERVED */ /*************************************************************************** *RSV_S - RESERVED ***************************************************************************/ /* TRIPLE_SEC :: RSV_S :: reserved0 [31:00] */ #define BCHP_TRIPLE_SEC_RSV_S_reserved0_MASK 0xffffffff #define BCHP_TRIPLE_SEC_RSV_S_reserved0_SHIFT 0 /*************************************************************************** *RSV_E - RESERVED ***************************************************************************/ /* TRIPLE_SEC :: RSV_E :: reserved0 [31:00] */ #define BCHP_TRIPLE_SEC_RSV_E_reserved0_MASK 0xffffffff #define BCHP_TRIPLE_SEC_RSV_E_reserved0_SHIFT 0 #endif /* #ifndef BCHP_TRIPLE_SEC_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016100000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_ctl_regs_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_0000644000175000017500000013674011610313111030626 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_ddr23_ctl_regs_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:59p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:08 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_ctl_regs_0.h $ * * Hydra_Software_Devel/1 7/17/09 7:59p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DDR23_CTL_REGS_0_H__ #define BCHP_DDR23_CTL_REGS_0_H__ /*************************************************************************** *DDR23_CTL_REGS_0 - DDR23 controller registers ***************************************************************************/ #define BCHP_DDR23_CTL_REGS_0_REVISION 0x01800000 /* DDR23 Controller revision register */ #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS 0x01800004 /* DDR23 Controller status register */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1 0x01800010 /* DDR23 Controller Configuration Set #1 */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2 0x01800014 /* DDR23 Controller Configuration Set #2 */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3 0x01800018 /* DDR23 Controller Configuration Set #3 */ #define BCHP_DDR23_CTL_REGS_0_REFRESH 0x0180001c /* DDR23 Controller Automated Refresh Configuration */ #define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD 0x01800020 /* Host Initiated Refresh Control */ #define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD 0x01800024 /* Host Initiated Precharge Control */ #define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD 0x01800028 /* Host Initiated Load Mode Control */ #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD 0x0180002c /* Host Initiated Load Extended Mode Control */ #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD 0x01800030 /* Host Initiated Load Extended Mode #2 Control */ #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD 0x01800034 /* Host Initiated Load Extended Mode #3 Control */ #define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE 0x01800038 /* Host Initiated ZQ Calibration Cycle */ #define BCHP_DDR23_CTL_REGS_0_CMD_STATUS 0x0180003c /* Host Command Interface Status */ #define BCHP_DDR23_CTL_REGS_0_LATENCY 0x01800040 /* DDR2 Controller Access Latency Control */ #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0 0x01800044 /* Semaphore Register #0 */ #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1 0x01800048 /* Semaphore Register #1 */ #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2 0x0180004c /* Semaphore Register #2 */ #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3 0x01800050 /* Semaphore Register #3 */ #define BCHP_DDR23_CTL_REGS_0_SCRATCH 0x01800058 /* Scratch Register */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH 0x01800060 /* Stripe Width */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0 0x01800070 /* Stripe Height for picture buffers 0 through 23 */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1 0x01800074 /* Stripe Height for picture buffers 24 through 27 */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2 0x01800078 /* Stripe Height for picture buffers 28 through 31 */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL 0x01800090 /* DDR Phy-Bist Control and Status */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_SEED 0x01800094 /* DDR Phy-Bist PRPG Seed Value */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS 0x01800098 /* DDR Phy-Bist Address & Control Status */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS 0x0180009c /* DDR Phy-Bist DQ Status */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS 0x018000a0 /* DDR Phy-Bist Miscellaneous Status */ #define BCHP_DDR23_CTL_REGS_0_VDL_CTL 0x018000b0 /* Dynamic VDL Changes Control */ #define BCHP_DDR23_CTL_REGS_0_VDL_ADR_BASE 0x018000b4 /* Dynamic VDL Changes Base Address */ #define BCHP_DDR23_CTL_REGS_0_VDL_ADR_END 0x018000b8 /* Dynamic VDL Changes End Address */ #define BCHP_DDR23_CTL_REGS_0_PMON_CTL 0x018000c0 /* Performance Monitoring Control */ #define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD 0x018000c4 /* Performance Monitoring Period Control */ #define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT 0x018000c8 /* Performance Monitoring Active Cycles Count */ #define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT 0x018000cc /* Performance Monitoring Idle Cycles Count */ #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1 0x018000d0 /* Performance Monitoring Data Channel #1 Read Accesses Count */ #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2 0x018000d4 /* Performance Monitoring Data Channel #2 Read Accesses Count */ #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3 0x018000d8 /* Performance Monitoring Data Channel #3 Read Accesses Count */ #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1 0x018000dc /* Performance Monitoring Data Channel #1 Write Accesses Count */ #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2 0x018000e0 /* Performance Monitoring Data Channel #2 Write Accesses Count */ #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3 0x018000e4 /* Performance Monitoring Data Channel #3 Write Accesses Count */ #define BCHP_DDR23_CTL_REGS_0_DDR_TM 0x018000e8 /* RAM Macro TM Control */ #define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL 0x018000f0 /* RAM Macro TM Control */ /*************************************************************************** *REVISION - DDR23 Controller revision register ***************************************************************************/ /* DDR23_CTL_REGS_0 :: REVISION :: reserved0 [31:16] */ #define BCHP_DDR23_CTL_REGS_0_REVISION_reserved0_MASK 0xffff0000 #define BCHP_DDR23_CTL_REGS_0_REVISION_reserved0_SHIFT 16 /* DDR23_CTL_REGS_0 :: REVISION :: MAJOR [15:08] */ #define BCHP_DDR23_CTL_REGS_0_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_DDR23_CTL_REGS_0_REVISION_MAJOR_SHIFT 8 /* DDR23_CTL_REGS_0 :: REVISION :: MINOR [07:00] */ #define BCHP_DDR23_CTL_REGS_0_REVISION_MINOR_MASK 0x000000ff #define BCHP_DDR23_CTL_REGS_0_REVISION_MINOR_SHIFT 0 /*************************************************************************** *CTL_STATUS - DDR23 Controller status register ***************************************************************************/ /* DDR23_CTL_REGS_0 :: CTL_STATUS :: reserved0 [31:07] */ #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved0_MASK 0xffffff80 #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved0_SHIFT 7 /* DDR23_CTL_REGS_0 :: CTL_STATUS :: rd_fifo3_empty [06:06] */ #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo3_empty_MASK 0x00000040 #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo3_empty_SHIFT 6 /* DDR23_CTL_REGS_0 :: CTL_STATUS :: rd_fifo2_empty [05:05] */ #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo2_empty_MASK 0x00000020 #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo2_empty_SHIFT 5 /* DDR23_CTL_REGS_0 :: CTL_STATUS :: rd_fifo1_empty [04:04] */ #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo1_empty_MASK 0x00000010 #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_rd_fifo1_empty_SHIFT 4 /* DDR23_CTL_REGS_0 :: CTL_STATUS :: reserved1 [03:02] */ #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved1_MASK 0x0000000c #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_reserved1_SHIFT 2 /* DDR23_CTL_REGS_0 :: CTL_STATUS :: clke [01:01] */ #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_MASK 0x00000002 #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_SHIFT 1 /* DDR23_CTL_REGS_0 :: CTL_STATUS :: idle [00:00] */ #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_MASK 0x00000001 #define BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_SHIFT 0 /*************************************************************************** *PARAMS1 - DDR23 Controller Configuration Set #1 ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PARAMS1 :: trtp [31:28] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trtp_MASK 0xf0000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trtp_SHIFT 28 /* DDR23_CTL_REGS_0 :: PARAMS1 :: twl [27:24] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_twl_MASK 0x0f000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS1_twl_SHIFT 24 /* DDR23_CTL_REGS_0 :: PARAMS1 :: tcas [23:20] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_tcas_MASK 0x00f00000 #define BCHP_DDR23_CTL_REGS_0_PARAMS1_tcas_SHIFT 20 /* DDR23_CTL_REGS_0 :: PARAMS1 :: twtr [19:16] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_twtr_MASK 0x000f0000 #define BCHP_DDR23_CTL_REGS_0_PARAMS1_twtr_SHIFT 16 /* DDR23_CTL_REGS_0 :: PARAMS1 :: twr [15:12] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_twr_MASK 0x0000f000 #define BCHP_DDR23_CTL_REGS_0_PARAMS1_twr_SHIFT 12 /* DDR23_CTL_REGS_0 :: PARAMS1 :: trrd [11:08] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trrd_MASK 0x00000f00 #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trrd_SHIFT 8 /* DDR23_CTL_REGS_0 :: PARAMS1 :: trp [07:04] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trp_MASK 0x000000f0 #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trp_SHIFT 4 /* DDR23_CTL_REGS_0 :: PARAMS1 :: trcd [03:00] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trcd_MASK 0x0000000f #define BCHP_DDR23_CTL_REGS_0_PARAMS1_trcd_SHIFT 0 /*************************************************************************** *PARAMS2 - DDR23 Controller Configuration Set #2 ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PARAMS2 :: auto_idle [31:31] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_auto_idle_MASK 0x80000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_auto_idle_SHIFT 31 /* DDR23_CTL_REGS_0 :: PARAMS2 :: row_bits [30:30] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_row_bits_MASK 0x40000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_row_bits_SHIFT 30 /* DDR23_CTL_REGS_0 :: PARAMS2 :: use_chr_hgt [29:29] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_use_chr_hgt_MASK 0x20000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_use_chr_hgt_SHIFT 29 /* DDR23_CTL_REGS_0 :: PARAMS2 :: clke [28:28] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_MASK 0x10000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_SHIFT 28 /* DDR23_CTL_REGS_0 :: PARAMS2 :: sd_col_bits [27:26] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_sd_col_bits_MASK 0x0c000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_sd_col_bits_SHIFT 26 /* DDR23_CTL_REGS_0 :: PARAMS2 :: il_sel [25:25] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_il_sel_MASK 0x02000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_il_sel_SHIFT 25 /* DDR23_CTL_REGS_0 :: PARAMS2 :: dis_itlv [24:24] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_dis_itlv_MASK 0x01000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_dis_itlv_SHIFT 24 /* DDR23_CTL_REGS_0 :: PARAMS2 :: reserved0 [23:23] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_reserved0_MASK 0x00800000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_reserved0_SHIFT 23 /* DDR23_CTL_REGS_0 :: PARAMS2 :: cs0_only [22:22] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_cs0_only_MASK 0x00400000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_cs0_only_SHIFT 22 /* DDR23_CTL_REGS_0 :: PARAMS2 :: allow_pictmem_rd [21:21] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_allow_pictmem_rd_MASK 0x00200000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_allow_pictmem_rd_SHIFT 21 /* DDR23_CTL_REGS_0 :: PARAMS2 :: bank_bits [20:20] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_bank_bits_MASK 0x00100000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_bank_bits_SHIFT 20 /* DDR23_CTL_REGS_0 :: PARAMS2 :: trfc [19:12] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_trfc_MASK 0x000ff000 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_trfc_SHIFT 12 /* DDR23_CTL_REGS_0 :: PARAMS2 :: tfaw [11:06] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_tfaw_MASK 0x00000fc0 #define BCHP_DDR23_CTL_REGS_0_PARAMS2_tfaw_SHIFT 6 /* DDR23_CTL_REGS_0 :: PARAMS2 :: tras [05:00] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS2_tras_MASK 0x0000003f #define BCHP_DDR23_CTL_REGS_0_PARAMS2_tras_SHIFT 0 /*************************************************************************** *PARAMS3 - DDR23 Controller Configuration Set #3 ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PARAMS3 :: ddr3_reset [31:31] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr3_reset_MASK 0x80000000 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr3_reset_SHIFT 31 /* DDR23_CTL_REGS_0 :: PARAMS3 :: reserved0 [30:06] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved0_MASK 0x7fffffc0 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_reserved0_SHIFT 6 /* DDR23_CTL_REGS_0 :: PARAMS3 :: ddr_bl [05:05] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr_bl_MASK 0x00000020 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_ddr_bl_SHIFT 5 /* DDR23_CTL_REGS_0 :: PARAMS3 :: cmd_2t [04:04] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_cmd_2t_MASK 0x00000010 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_cmd_2t_SHIFT 4 /* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_mode [03:03] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_mode_MASK 0x00000008 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_mode_SHIFT 3 /* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_te_adj [02:02] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_te_adj_MASK 0x00000004 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_te_adj_SHIFT 2 /* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_le_adj [01:01] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_le_adj_MASK 0x00000002 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_le_adj_SHIFT 1 /* DDR23_CTL_REGS_0 :: PARAMS3 :: wr_odt_en [00:00] */ #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_MASK 0x00000001 #define BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_SHIFT 0 /*************************************************************************** *REFRESH - DDR23 Controller Automated Refresh Configuration ***************************************************************************/ /* DDR23_CTL_REGS_0 :: REFRESH :: reserved0 [31:13] */ #define BCHP_DDR23_CTL_REGS_0_REFRESH_reserved0_MASK 0xffffe000 #define BCHP_DDR23_CTL_REGS_0_REFRESH_reserved0_SHIFT 13 /* DDR23_CTL_REGS_0 :: REFRESH :: enable [12:12] */ #define BCHP_DDR23_CTL_REGS_0_REFRESH_enable_MASK 0x00001000 #define BCHP_DDR23_CTL_REGS_0_REFRESH_enable_SHIFT 12 /* DDR23_CTL_REGS_0 :: REFRESH :: period [11:00] */ #define BCHP_DDR23_CTL_REGS_0_REFRESH_period_MASK 0x00000fff #define BCHP_DDR23_CTL_REGS_0_REFRESH_period_SHIFT 0 /*************************************************************************** *REFRESH_CMD - Host Initiated Refresh Control ***************************************************************************/ /* DDR23_CTL_REGS_0 :: REFRESH_CMD :: reserved0 [31:16] */ #define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_reserved0_MASK 0xffff0000 #define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_reserved0_SHIFT 16 /* DDR23_CTL_REGS_0 :: REFRESH_CMD :: cmd [15:00] */ #define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_cmd_MASK 0x0000ffff #define BCHP_DDR23_CTL_REGS_0_REFRESH_CMD_cmd_SHIFT 0 /*************************************************************************** *PRECHARGE_CMD - Host Initiated Precharge Control ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PRECHARGE_CMD :: reserved0 [31:16] */ #define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_reserved0_MASK 0xffff0000 #define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_reserved0_SHIFT 16 /* DDR23_CTL_REGS_0 :: PRECHARGE_CMD :: cmd [15:00] */ #define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_cmd_MASK 0x0000ffff #define BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD_cmd_SHIFT 0 /*************************************************************************** *LOAD_MODE_CMD - Host Initiated Load Mode Control ***************************************************************************/ /* DDR23_CTL_REGS_0 :: LOAD_MODE_CMD :: reserved0 [31:16] */ #define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_reserved0_MASK 0xffff0000 #define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_reserved0_SHIFT 16 /* DDR23_CTL_REGS_0 :: LOAD_MODE_CMD :: cmd [15:00] */ #define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_cmd_MASK 0x0000ffff #define BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD_cmd_SHIFT 0 /*************************************************************************** *LOAD_EMODE_CMD - Host Initiated Load Extended Mode Control ***************************************************************************/ /* DDR23_CTL_REGS_0 :: LOAD_EMODE_CMD :: reserved0 [31:16] */ #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_reserved0_MASK 0xffff0000 #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_reserved0_SHIFT 16 /* DDR23_CTL_REGS_0 :: LOAD_EMODE_CMD :: cmd [15:00] */ #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_cmd_MASK 0x0000ffff #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD_cmd_SHIFT 0 /*************************************************************************** *LOAD_EMODE2_CMD - Host Initiated Load Extended Mode #2 Control ***************************************************************************/ /* DDR23_CTL_REGS_0 :: LOAD_EMODE2_CMD :: reserved0 [31:16] */ #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_reserved0_MASK 0xffff0000 #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_reserved0_SHIFT 16 /* DDR23_CTL_REGS_0 :: LOAD_EMODE2_CMD :: cmd [15:00] */ #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_cmd_MASK 0x0000ffff #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD_cmd_SHIFT 0 /*************************************************************************** *LOAD_EMODE3_CMD - Host Initiated Load Extended Mode #3 Control ***************************************************************************/ /* DDR23_CTL_REGS_0 :: LOAD_EMODE3_CMD :: reserved0 [31:16] */ #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_reserved0_MASK 0xffff0000 #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_reserved0_SHIFT 16 /* DDR23_CTL_REGS_0 :: LOAD_EMODE3_CMD :: cmd [15:00] */ #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_cmd_MASK 0x0000ffff #define BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD_cmd_SHIFT 0 /*************************************************************************** *ZQ_CALIBRATE - Host Initiated ZQ Calibration Cycle ***************************************************************************/ /* DDR23_CTL_REGS_0 :: ZQ_CALIBRATE :: reserved0 [31:16] */ #define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_reserved0_MASK 0xffff0000 #define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_reserved0_SHIFT 16 /* DDR23_CTL_REGS_0 :: ZQ_CALIBRATE :: cmd [15:00] */ #define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_cmd_MASK 0x0000ffff #define BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE_cmd_SHIFT 0 /*************************************************************************** *CMD_STATUS - Host Command Interface Status ***************************************************************************/ /* DDR23_CTL_REGS_0 :: CMD_STATUS :: reserved0 [31:01] */ #define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_reserved0_MASK 0xfffffffe #define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_reserved0_SHIFT 1 /* DDR23_CTL_REGS_0 :: CMD_STATUS :: status [00:00] */ #define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_status_MASK 0x00000001 #define BCHP_DDR23_CTL_REGS_0_CMD_STATUS_status_SHIFT 0 /*************************************************************************** *LATENCY - DDR2 Controller Access Latency Control ***************************************************************************/ /* DDR23_CTL_REGS_0 :: LATENCY :: reserved0 [31:10] */ #define BCHP_DDR23_CTL_REGS_0_LATENCY_reserved0_MASK 0xfffffc00 #define BCHP_DDR23_CTL_REGS_0_LATENCY_reserved0_SHIFT 10 /* DDR23_CTL_REGS_0 :: LATENCY :: limit [09:00] */ #define BCHP_DDR23_CTL_REGS_0_LATENCY_limit_MASK 0x000003ff #define BCHP_DDR23_CTL_REGS_0_LATENCY_limit_SHIFT 0 /*************************************************************************** *SEMAPHORE0 - Semaphore Register #0 ***************************************************************************/ /* DDR23_CTL_REGS_0 :: SEMAPHORE0 :: reserved0 [31:01] */ #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_reserved0_MASK 0xfffffffe #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_reserved0_SHIFT 1 /* DDR23_CTL_REGS_0 :: SEMAPHORE0 :: enable [00:00] */ #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_enable_MASK 0x00000001 #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE0_enable_SHIFT 0 /*************************************************************************** *SEMAPHORE1 - Semaphore Register #1 ***************************************************************************/ /* DDR23_CTL_REGS_0 :: SEMAPHORE1 :: reserved0 [31:01] */ #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_reserved0_MASK 0xfffffffe #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_reserved0_SHIFT 1 /* DDR23_CTL_REGS_0 :: SEMAPHORE1 :: enable [00:00] */ #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_enable_MASK 0x00000001 #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE1_enable_SHIFT 0 /*************************************************************************** *SEMAPHORE2 - Semaphore Register #2 ***************************************************************************/ /* DDR23_CTL_REGS_0 :: SEMAPHORE2 :: reserved0 [31:01] */ #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_reserved0_MASK 0xfffffffe #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_reserved0_SHIFT 1 /* DDR23_CTL_REGS_0 :: SEMAPHORE2 :: enable [00:00] */ #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_enable_MASK 0x00000001 #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE2_enable_SHIFT 0 /*************************************************************************** *SEMAPHORE3 - Semaphore Register #3 ***************************************************************************/ /* DDR23_CTL_REGS_0 :: SEMAPHORE3 :: reserved0 [31:01] */ #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_reserved0_MASK 0xfffffffe #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_reserved0_SHIFT 1 /* DDR23_CTL_REGS_0 :: SEMAPHORE3 :: enable [00:00] */ #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_enable_MASK 0x00000001 #define BCHP_DDR23_CTL_REGS_0_SEMAPHORE3_enable_SHIFT 0 /*************************************************************************** *SCRATCH - Scratch Register ***************************************************************************/ /* DDR23_CTL_REGS_0 :: SCRATCH :: scratch [31:00] */ #define BCHP_DDR23_CTL_REGS_0_SCRATCH_scratch_MASK 0xffffffff #define BCHP_DDR23_CTL_REGS_0_SCRATCH_scratch_SHIFT 0 /*************************************************************************** *STRIPE_WIDTH - Stripe Width ***************************************************************************/ /* DDR23_CTL_REGS_0 :: STRIPE_WIDTH :: reserved0 [31:02] */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_reserved0_MASK 0xfffffffc #define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_reserved0_SHIFT 2 /* DDR23_CTL_REGS_0 :: STRIPE_WIDTH :: swidth [01:00] */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_swidth_MASK 0x00000003 #define BCHP_DDR23_CTL_REGS_0_STRIPE_WIDTH_swidth_SHIFT 0 /*************************************************************************** *STRIPE_HEIGHT_0 - Stripe Height for picture buffers 0 through 23 ***************************************************************************/ /* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_0 :: reserved0 [31:27] */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved0_MASK 0xf8000000 #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved0_SHIFT 27 /* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_0 :: chroma_height [26:16] */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_chroma_height_MASK 0x07ff0000 #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_chroma_height_SHIFT 16 /* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_0 :: reserved1 [15:11] */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved1_MASK 0x0000f800 #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_reserved1_SHIFT 11 /* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_0 :: luma_height [10:00] */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_luma_height_MASK 0x000007ff #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_0_luma_height_SHIFT 0 /*************************************************************************** *STRIPE_HEIGHT_1 - Stripe Height for picture buffers 24 through 27 ***************************************************************************/ /* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_1 :: reserved0 [31:27] */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved0_MASK 0xf8000000 #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved0_SHIFT 27 /* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_1 :: chroma_height [26:16] */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_chroma_height_MASK 0x07ff0000 #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_chroma_height_SHIFT 16 /* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_1 :: reserved1 [15:11] */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved1_MASK 0x0000f800 #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_reserved1_SHIFT 11 /* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_1 :: luma_height [10:00] */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_luma_height_MASK 0x000007ff #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_1_luma_height_SHIFT 0 /*************************************************************************** *STRIPE_HEIGHT_2 - Stripe Height for picture buffers 28 through 31 ***************************************************************************/ /* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_2 :: reserved0 [31:27] */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved0_MASK 0xf8000000 #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved0_SHIFT 27 /* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_2 :: chroma_height [26:16] */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_chroma_height_MASK 0x07ff0000 #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_chroma_height_SHIFT 16 /* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_2 :: reserved1 [15:11] */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved1_MASK 0x0000f800 #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_reserved1_SHIFT 11 /* DDR23_CTL_REGS_0 :: STRIPE_HEIGHT_2 :: luma_height [10:00] */ #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_luma_height_MASK 0x000007ff #define BCHP_DDR23_CTL_REGS_0_STRIPE_HEIGHT_2_luma_height_SHIFT 0 /*************************************************************************** *PHYBIST_CNTRL - DDR Phy-Bist Control and Status ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: reserved0 [31:18] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_reserved0_MASK 0xfffc0000 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_reserved0_SHIFT 18 /* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: force_error_pos [17:16] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_error_pos_MASK 0x00030000 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_error_pos_SHIFT 16 /* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: reserved1 [15:14] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_reserved1_MASK 0x0000c000 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_reserved1_SHIFT 14 /* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: force_error_sel [13:08] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_error_sel_MASK 0x00003f00 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_error_sel_SHIFT 8 /* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: reserved2 [07:05] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_reserved2_MASK 0x000000e0 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_reserved2_SHIFT 5 /* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: force_dat_error [04:04] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_dat_error_MASK 0x00000010 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_dat_error_SHIFT 4 /* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: force_ctl_error [03:03] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_ctl_error_MASK 0x00000008 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_ctl_error_SHIFT 3 /* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: force_cs_n [02:02] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_cs_n_MASK 0x00000004 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_cs_n_SHIFT 2 /* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: force_odt [01:01] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_odt_MASK 0x00000002 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_force_odt_SHIFT 1 /* DDR23_CTL_REGS_0 :: PHYBIST_CNTRL :: enable [00:00] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_enable_MASK 0x00000001 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CNTRL_enable_SHIFT 0 /*************************************************************************** *PHYBIST_SEED - DDR Phy-Bist PRPG Seed Value ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PHYBIST_SEED :: seed [31:00] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_SEED_seed_MASK 0xffffffff #define BCHP_DDR23_CTL_REGS_0_PHYBIST_SEED_seed_SHIFT 0 /*************************************************************************** *PHYBIST_CTL_STATUS - DDR Phy-Bist Address & Control Status ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: reserved0 [31:27] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_reserved0_MASK 0xf8000000 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_reserved0_SHIFT 27 /* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_ras_n [26:26] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_ras_n_MASK 0x04000000 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_ras_n_SHIFT 26 /* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_cas_n [25:25] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_cas_n_MASK 0x02000000 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_cas_n_SHIFT 25 /* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_we_n [24:24] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_we_n_MASK 0x01000000 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_we_n_SHIFT 24 /* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_cke [23:23] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_cke_MASK 0x00800000 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_cke_SHIFT 23 /* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_odt [22:22] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_odt_MASK 0x00400000 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_odt_SHIFT 22 /* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_reset [21:21] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_reset_MASK 0x00200000 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_reset_SHIFT 21 /* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_ad [20:07] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_ad_MASK 0x001fff80 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_ad_SHIFT 7 /* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_ba [06:04] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_ba_MASK 0x00000070 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_ba_SHIFT 4 /* DDR23_CTL_REGS_0 :: PHYBIST_CTL_STATUS :: ddr_aux [03:00] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_aux_MASK 0x0000000f #define BCHP_DDR23_CTL_REGS_0_PHYBIST_CTL_STATUS_ddr_aux_SHIFT 0 /*************************************************************************** *PHYBIST_DQ_STATUS - DDR Phy-Bist DQ Status ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PHYBIST_DQ_STATUS :: ddr_dq3 [31:24] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq3_MASK 0xff000000 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq3_SHIFT 24 /* DDR23_CTL_REGS_0 :: PHYBIST_DQ_STATUS :: ddr_dq2 [23:16] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq2_MASK 0x00ff0000 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq2_SHIFT 16 /* DDR23_CTL_REGS_0 :: PHYBIST_DQ_STATUS :: ddr_dq1 [15:08] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq1_MASK 0x0000ff00 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq1_SHIFT 8 /* DDR23_CTL_REGS_0 :: PHYBIST_DQ_STATUS :: ddr_dq0 [07:00] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq0_MASK 0x000000ff #define BCHP_DDR23_CTL_REGS_0_PHYBIST_DQ_STATUS_ddr_dq0_SHIFT 0 /*************************************************************************** *PHYBIST_MISC_STATUS - DDR Phy-Bist Miscellaneous Status ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PHYBIST_MISC_STATUS :: dat_done [31:31] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_dat_done_MASK 0x80000000 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_dat_done_SHIFT 31 /* DDR23_CTL_REGS_0 :: PHYBIST_MISC_STATUS :: ctl_done [30:30] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_ctl_done_MASK 0x40000000 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_ctl_done_SHIFT 30 /* DDR23_CTL_REGS_0 :: PHYBIST_MISC_STATUS :: reserved0 [29:08] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_reserved0_MASK 0x3fffff00 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_reserved0_SHIFT 8 /* DDR23_CTL_REGS_0 :: PHYBIST_MISC_STATUS :: ddr_dm [07:04] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_ddr_dm_MASK 0x000000f0 #define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_ddr_dm_SHIFT 4 /* DDR23_CTL_REGS_0 :: PHYBIST_MISC_STATUS :: ddr_clk [03:00] */ #define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_ddr_clk_MASK 0x0000000f #define BCHP_DDR23_CTL_REGS_0_PHYBIST_MISC_STATUS_ddr_clk_SHIFT 0 /*************************************************************************** *VDL_CTL - Dynamic VDL Changes Control ***************************************************************************/ /* DDR23_CTL_REGS_0 :: VDL_CTL :: reserved0 [31:01] */ #define BCHP_DDR23_CTL_REGS_0_VDL_CTL_reserved0_MASK 0xfffffffe #define BCHP_DDR23_CTL_REGS_0_VDL_CTL_reserved0_SHIFT 1 /* DDR23_CTL_REGS_0 :: VDL_CTL :: enable [00:00] */ #define BCHP_DDR23_CTL_REGS_0_VDL_CTL_enable_MASK 0x00000001 #define BCHP_DDR23_CTL_REGS_0_VDL_CTL_enable_SHIFT 0 /*************************************************************************** *VDL_ADR_BASE - Dynamic VDL Changes Base Address ***************************************************************************/ /* DDR23_CTL_REGS_0 :: VDL_ADR_BASE :: addr [31:00] */ #define BCHP_DDR23_CTL_REGS_0_VDL_ADR_BASE_addr_MASK 0xffffffff #define BCHP_DDR23_CTL_REGS_0_VDL_ADR_BASE_addr_SHIFT 0 /*************************************************************************** *VDL_ADR_END - Dynamic VDL Changes End Address ***************************************************************************/ /* DDR23_CTL_REGS_0 :: VDL_ADR_END :: addr [31:00] */ #define BCHP_DDR23_CTL_REGS_0_VDL_ADR_END_addr_MASK 0xffffffff #define BCHP_DDR23_CTL_REGS_0_VDL_ADR_END_addr_SHIFT 0 /*************************************************************************** *PMON_CTL - Performance Monitoring Control ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PMON_CTL :: reserved0 [31:01] */ #define BCHP_DDR23_CTL_REGS_0_PMON_CTL_reserved0_MASK 0xfffffffe #define BCHP_DDR23_CTL_REGS_0_PMON_CTL_reserved0_SHIFT 1 /* DDR23_CTL_REGS_0 :: PMON_CTL :: enable [00:00] */ #define BCHP_DDR23_CTL_REGS_0_PMON_CTL_enable_MASK 0x00000001 #define BCHP_DDR23_CTL_REGS_0_PMON_CTL_enable_SHIFT 0 /*************************************************************************** *PMON_PERIOD - Performance Monitoring Period Control ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PMON_PERIOD :: reserved0 [31:24] */ #define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_reserved0_MASK 0xff000000 #define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_reserved0_SHIFT 24 /* DDR23_CTL_REGS_0 :: PMON_PERIOD :: count [23:00] */ #define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_count_MASK 0x00ffffff #define BCHP_DDR23_CTL_REGS_0_PMON_PERIOD_count_SHIFT 0 /*************************************************************************** *PMON_CYCLE_CNT - Performance Monitoring Active Cycles Count ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PMON_CYCLE_CNT :: reserved0 [31:24] */ #define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_reserved0_MASK 0xff000000 #define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_reserved0_SHIFT 24 /* DDR23_CTL_REGS_0 :: PMON_CYCLE_CNT :: count [23:00] */ #define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_count_MASK 0x00ffffff #define BCHP_DDR23_CTL_REGS_0_PMON_CYCLE_CNT_count_SHIFT 0 /*************************************************************************** *PMON_IDLE_CNT - Performance Monitoring Idle Cycles Count ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PMON_IDLE_CNT :: reserved0 [31:24] */ #define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_reserved0_MASK 0xff000000 #define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_reserved0_SHIFT 24 /* DDR23_CTL_REGS_0 :: PMON_IDLE_CNT :: count [23:00] */ #define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_count_MASK 0x00ffffff #define BCHP_DDR23_CTL_REGS_0_PMON_IDLE_CNT_count_SHIFT 0 /*************************************************************************** *PMON_RD_CNT1 - Performance Monitoring Data Channel #1 Read Accesses Count ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PMON_RD_CNT1 :: reserved0 [31:24] */ #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_reserved0_MASK 0xff000000 #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_reserved0_SHIFT 24 /* DDR23_CTL_REGS_0 :: PMON_RD_CNT1 :: count [23:00] */ #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_count_MASK 0x00ffffff #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT1_count_SHIFT 0 /*************************************************************************** *PMON_RD_CNT2 - Performance Monitoring Data Channel #2 Read Accesses Count ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PMON_RD_CNT2 :: reserved0 [31:24] */ #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_reserved0_MASK 0xff000000 #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_reserved0_SHIFT 24 /* DDR23_CTL_REGS_0 :: PMON_RD_CNT2 :: count [23:00] */ #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_count_MASK 0x00ffffff #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT2_count_SHIFT 0 /*************************************************************************** *PMON_RD_CNT3 - Performance Monitoring Data Channel #3 Read Accesses Count ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PMON_RD_CNT3 :: reserved0 [31:24] */ #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_reserved0_MASK 0xff000000 #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_reserved0_SHIFT 24 /* DDR23_CTL_REGS_0 :: PMON_RD_CNT3 :: count [23:00] */ #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_count_MASK 0x00ffffff #define BCHP_DDR23_CTL_REGS_0_PMON_RD_CNT3_count_SHIFT 0 /*************************************************************************** *PMON_WR_CNT1 - Performance Monitoring Data Channel #1 Write Accesses Count ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PMON_WR_CNT1 :: reserved0 [31:24] */ #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_reserved0_MASK 0xff000000 #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_reserved0_SHIFT 24 /* DDR23_CTL_REGS_0 :: PMON_WR_CNT1 :: count [23:00] */ #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_count_MASK 0x00ffffff #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT1_count_SHIFT 0 /*************************************************************************** *PMON_WR_CNT2 - Performance Monitoring Data Channel #2 Write Accesses Count ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PMON_WR_CNT2 :: reserved0 [31:24] */ #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_reserved0_MASK 0xff000000 #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_reserved0_SHIFT 24 /* DDR23_CTL_REGS_0 :: PMON_WR_CNT2 :: count [23:00] */ #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_count_MASK 0x00ffffff #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT2_count_SHIFT 0 /*************************************************************************** *PMON_WR_CNT3 - Performance Monitoring Data Channel #3 Write Accesses Count ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PMON_WR_CNT3 :: reserved0 [31:24] */ #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_reserved0_MASK 0xff000000 #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_reserved0_SHIFT 24 /* DDR23_CTL_REGS_0 :: PMON_WR_CNT3 :: count [23:00] */ #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_count_MASK 0x00ffffff #define BCHP_DDR23_CTL_REGS_0_PMON_WR_CNT3_count_SHIFT 0 /*************************************************************************** *DDR_TM - RAM Macro TM Control ***************************************************************************/ /* DDR23_CTL_REGS_0 :: DDR_TM :: reserved0 [31:22] */ #define BCHP_DDR23_CTL_REGS_0_DDR_TM_reserved0_MASK 0xffc00000 #define BCHP_DDR23_CTL_REGS_0_DDR_TM_reserved0_SHIFT 22 /* DDR23_CTL_REGS_0 :: DDR_TM :: sdc [21:20] */ #define BCHP_DDR23_CTL_REGS_0_DDR_TM_sdc_MASK 0x00300000 #define BCHP_DDR23_CTL_REGS_0_DDR_TM_sdc_SHIFT 20 /* DDR23_CTL_REGS_0 :: DDR_TM :: row [19:18] */ #define BCHP_DDR23_CTL_REGS_0_DDR_TM_row_MASK 0x000c0000 #define BCHP_DDR23_CTL_REGS_0_DDR_TM_row_SHIFT 18 /* DDR23_CTL_REGS_0 :: DDR_TM :: col [17:16] */ #define BCHP_DDR23_CTL_REGS_0_DDR_TM_col_MASK 0x00030000 #define BCHP_DDR23_CTL_REGS_0_DDR_TM_col_SHIFT 16 /* DDR23_CTL_REGS_0 :: DDR_TM :: pic [15:14] */ #define BCHP_DDR23_CTL_REGS_0_DDR_TM_pic_MASK 0x0000c000 #define BCHP_DDR23_CTL_REGS_0_DDR_TM_pic_SHIFT 14 /* DDR23_CTL_REGS_0 :: DDR_TM :: wrf3 [13:12] */ #define BCHP_DDR23_CTL_REGS_0_DDR_TM_wrf3_MASK 0x00003000 #define BCHP_DDR23_CTL_REGS_0_DDR_TM_wrf3_SHIFT 12 /* DDR23_CTL_REGS_0 :: DDR_TM :: wrf2 [11:10] */ #define BCHP_DDR23_CTL_REGS_0_DDR_TM_wrf2_MASK 0x00000c00 #define BCHP_DDR23_CTL_REGS_0_DDR_TM_wrf2_SHIFT 10 /* DDR23_CTL_REGS_0 :: DDR_TM :: wrf1 [09:08] */ #define BCHP_DDR23_CTL_REGS_0_DDR_TM_wrf1_MASK 0x00000300 #define BCHP_DDR23_CTL_REGS_0_DDR_TM_wrf1_SHIFT 8 /* DDR23_CTL_REGS_0 :: DDR_TM :: rdf3 [07:06] */ #define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf3_MASK 0x000000c0 #define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf3_SHIFT 6 /* DDR23_CTL_REGS_0 :: DDR_TM :: rdf2 [05:04] */ #define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf2_MASK 0x00000030 #define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf2_SHIFT 4 /* DDR23_CTL_REGS_0 :: DDR_TM :: rdf1_1 [03:02] */ #define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf1_1_MASK 0x0000000c #define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf1_1_SHIFT 2 /* DDR23_CTL_REGS_0 :: DDR_TM :: rdf1_0 [01:00] */ #define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf1_0_MASK 0x00000003 #define BCHP_DDR23_CTL_REGS_0_DDR_TM_rdf1_0_SHIFT 0 /*************************************************************************** *UPDATE_VDL - RAM Macro TM Control ***************************************************************************/ /* DDR23_CTL_REGS_0 :: UPDATE_VDL :: reserved0 [31:02] */ #define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_reserved0_MASK 0xfffffffc #define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_reserved0_SHIFT 2 /* DDR23_CTL_REGS_0 :: UPDATE_VDL :: force [01:01] */ #define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_force_MASK 0x00000002 #define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_force_SHIFT 1 /* DDR23_CTL_REGS_0 :: UPDATE_VDL :: refresh [00:00] */ #define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_refresh_MASK 0x00000001 #define BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_refresh_SHIFT 0 /*************************************************************************** *PICT_BASE%i - Picture Buffer Base Address Ram ***************************************************************************/ #define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_ARRAY_BASE 0x01800100 #define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_ARRAY_START 0 #define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_ARRAY_END 63 #define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *PICT_BASE%i - Picture Buffer Base Address Ram ***************************************************************************/ /* DDR23_CTL_REGS_0 :: PICT_BASEi :: address [31:12] */ #define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_address_MASK 0xfffff000 #define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_address_SHIFT 12 /* DDR23_CTL_REGS_0 :: PICT_BASEi :: reserved0 [11:00] */ #define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_reserved0_MASK 0x00000fff #define BCHP_DDR23_CTL_REGS_0_PICT_BASEi_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DDR23_CTL_REGS_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015700000000000011570 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_tgt_rgr_bridge.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_tgt_rg0000644000175000017500000001424211610313111031027 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_tgt_rgr_bridge.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:21p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:57 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_tgt_rgr_bridge.h $ * * Hydra_Software_Devel/1 7/17/09 8:21p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_TGT_RGR_BRIDGE_H__ #define BCHP_TGT_RGR_BRIDGE_H__ /*************************************************************************** *TGT_RGR_BRIDGE - TGT RGR Bridge Registers ***************************************************************************/ #define BCHP_TGT_RGR_BRIDGE_REVISION 0x00500780 /* PCIE RGR Bridge Revision Register */ #define BCHP_TGT_RGR_BRIDGE_CTRL 0x00500784 /* RGR Bridge Control Register */ #define BCHP_TGT_RGR_BRIDGE_RBUS_TIMER 0x00500788 /* RGR Bridge RBUS Timer Register */ #define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_0 0x0050078c /* RGR Bridge Spare Software Reset 0 Register */ #define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_1 0x00500790 /* RGR Bridge Spare Software Reset 1 Register */ /*************************************************************************** *REVISION - PCIE RGR Bridge Revision Register ***************************************************************************/ /* TGT_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define BCHP_TGT_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define BCHP_TGT_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 /* TGT_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define BCHP_TGT_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_TGT_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* TGT_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ #define BCHP_TGT_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define BCHP_TGT_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 /*************************************************************************** *CTRL - RGR Bridge Control Register ***************************************************************************/ /* TGT_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ #define BCHP_TGT_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc #define BCHP_TGT_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 /* TGT_RGR_BRIDGE :: CTRL :: RBUS_ERROR_INTR [01:01] */ #define BCHP_TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_MASK 0x00000002 #define BCHP_TGT_RGR_BRIDGE_CTRL_RBUS_ERROR_INTR_SHIFT 1 /* TGT_RGR_BRIDGE :: CTRL :: GISB_ERROR_INTR [00:00] */ #define BCHP_TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_MASK 0x00000001 #define BCHP_TGT_RGR_BRIDGE_CTRL_GISB_ERROR_INTR_SHIFT 0 /*************************************************************************** *RBUS_TIMER - RGR Bridge RBUS Timer Register ***************************************************************************/ /* TGT_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ #define BCHP_TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 #define BCHP_TGT_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 /* TGT_RGR_BRIDGE :: RBUS_TIMER :: RBUS_TO_RBUS_TRANS_TIMER_CNT [15:00] */ #define BCHP_TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_MASK 0x0000ffff #define BCHP_TGT_RGR_BRIDGE_RBUS_TIMER_RBUS_TO_RBUS_TRANS_TIMER_CNT_SHIFT 0 /*************************************************************************** *SPARE_SW_RESET_0 - RGR Bridge Spare Software Reset 0 Register ***************************************************************************/ /* TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ #define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe #define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 /* TGT_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 /*************************************************************************** *SPARE_SW_RESET_1 - RGR Bridge Spare Software Reset 1 Register ***************************************************************************/ /* TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ #define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe #define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 /* TGT_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ #define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 #define BCHP_TGT_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 #endif /* #ifndef BCHP_TGT_RGR_BRIDGE_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000014700000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_l2.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_l20000644000175000017500000027630211610313111030752 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_sun_l2.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:20p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:43 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_l2.h $ * * Hydra_Software_Devel/1 7/17/09 8:20p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_SUN_L2_H__ #define BCHP_SUN_L2_H__ /*************************************************************************** *SUN_L2 - Registers for the Sundry block's L2 interrupt controller ***************************************************************************/ #define BCHP_SUN_L2_CPU_STATUS 0x00401800 /* CPU interrupt Status Register */ #define BCHP_SUN_L2_CPU_SET 0x00401804 /* CPU interrupt Set Register */ #define BCHP_SUN_L2_CPU_CLEAR 0x00401808 /* CPU interrupt Clear Register */ #define BCHP_SUN_L2_CPU_MASK_STATUS 0x0040180c /* CPU interrupt Mask Status Register */ #define BCHP_SUN_L2_CPU_MASK_SET 0x00401810 /* CPU interrupt Mask Set Register */ #define BCHP_SUN_L2_CPU_MASK_CLEAR 0x00401814 /* CPU interrupt Mask Clear Register */ #define BCHP_SUN_L2_PCI_STATUS 0x00401818 /* PCI interrupt Status Register */ #define BCHP_SUN_L2_PCI_SET 0x0040181c /* PCI interrupt Set Register */ #define BCHP_SUN_L2_PCI_CLEAR 0x00401820 /* PCI interrupt Clear Register */ #define BCHP_SUN_L2_PCI_MASK_STATUS 0x00401824 /* PCI interrupt Mask Status Register */ #define BCHP_SUN_L2_PCI_MASK_SET 0x00401828 /* PCI interrupt Mask Set Register */ #define BCHP_SUN_L2_PCI_MASK_CLEAR 0x0040182c /* PCI interrupt Mask Clear Register */ /*************************************************************************** *CPU_STATUS - CPU interrupt Status Register ***************************************************************************/ /* SUN_L2 :: CPU_STATUS :: SPARE_INTR_31 [31:31] */ #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_31_MASK 0x80000000 #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_31_SHIFT 31 /* SUN_L2 :: CPU_STATUS :: SPARE_INTR_30 [30:30] */ #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_30_MASK 0x40000000 #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_30_SHIFT 30 /* SUN_L2 :: CPU_STATUS :: SPARE_INTR_29 [29:29] */ #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_29_MASK 0x20000000 #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_29_SHIFT 29 /* SUN_L2 :: CPU_STATUS :: SPARE_INTR_28 [28:28] */ #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_28_MASK 0x10000000 #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_28_SHIFT 28 /* SUN_L2 :: CPU_STATUS :: SPARE_INTR_27 [27:27] */ #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_27_MASK 0x08000000 #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_27_SHIFT 27 /* SUN_L2 :: CPU_STATUS :: SPARE_INTR_26 [26:26] */ #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_26_MASK 0x04000000 #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_26_SHIFT 26 /* SUN_L2 :: CPU_STATUS :: SPARE_INTR_25 [25:25] */ #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_25_MASK 0x02000000 #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_25_SHIFT 25 /* SUN_L2 :: CPU_STATUS :: SPARE_INTR_24 [24:24] */ #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_24_MASK 0x01000000 #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_24_SHIFT 24 /* SUN_L2 :: CPU_STATUS :: SPARE_INTR_23 [23:23] */ #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_23_MASK 0x00800000 #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_23_SHIFT 23 /* SUN_L2 :: CPU_STATUS :: SPARE_INTR_22 [22:22] */ #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_22_MASK 0x00400000 #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_22_SHIFT 22 /* SUN_L2 :: CPU_STATUS :: SPARE_INTR_21 [21:21] */ #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_21_MASK 0x00200000 #define BCHP_SUN_L2_CPU_STATUS_SPARE_INTR_21_SHIFT 21 /* SUN_L2 :: CPU_STATUS :: JTAG_GISB_RG_ERROR [20:20] */ #define BCHP_SUN_L2_CPU_STATUS_JTAG_GISB_RG_ERROR_MASK 0x00100000 #define BCHP_SUN_L2_CPU_STATUS_JTAG_GISB_RG_ERROR_SHIFT 20 /* SUN_L2 :: CPU_STATUS :: AUX_INTR [19:19] */ #define BCHP_SUN_L2_CPU_STATUS_AUX_INTR_MASK 0x00080000 #define BCHP_SUN_L2_CPU_STATUS_AUX_INTR_SHIFT 19 /* SUN_L2 :: CPU_STATUS :: SERS_PKT_ERR [18:18] */ #define BCHP_SUN_L2_CPU_STATUS_SERS_PKT_ERR_MASK 0x00040000 #define BCHP_SUN_L2_CPU_STATUS_SERS_PKT_ERR_SHIFT 18 /* SUN_L2 :: CPU_STATUS :: SERS_CLK_ERR [17:17] */ #define BCHP_SUN_L2_CPU_STATUS_SERS_CLK_ERR_MASK 0x00020000 #define BCHP_SUN_L2_CPU_STATUS_SERS_CLK_ERR_SHIFT 17 /* union - case mapped_buffer_mode [16:13] */ /* SUN_L2 :: CPU_STATUS :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ #define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 #define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 /* SUN_L2 :: CPU_STATUS :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ #define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 #define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 /* SUN_L2 :: CPU_STATUS :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ #define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 #define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 /* SUN_L2 :: CPU_STATUS :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ #define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 #define BCHP_SUN_L2_CPU_STATUS_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 /* union - case cmd_fifo_mode [16:13] */ /* SUN_L2 :: CPU_STATUS :: cmd_fifo_mode :: reserved0 [16:16] */ #define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_reserved0_MASK 0x00010000 #define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_reserved0_SHIFT 16 /* SUN_L2 :: CPU_STATUS :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ #define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 #define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 /* SUN_L2 :: CPU_STATUS :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ #define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 #define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 /* SUN_L2 :: CPU_STATUS :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ #define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 #define BCHP_SUN_L2_CPU_STATUS_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 /* SUN_L2 :: CPU_STATUS :: SERS_R_PKT [12:12] */ #define BCHP_SUN_L2_CPU_STATUS_SERS_R_PKT_MASK 0x00001000 #define BCHP_SUN_L2_CPU_STATUS_SERS_R_PKT_SHIFT 12 /* SUN_L2 :: CPU_STATUS :: WATCHDOG_1_DISABLE_INTR [11:11] */ #define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 #define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_DISABLE_INTR_SHIFT 11 /* SUN_L2 :: CPU_STATUS :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ #define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 #define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 /* SUN_L2 :: CPU_STATUS :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ #define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 #define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 /* SUN_L2 :: CPU_STATUS :: WATCHDOG_0_DISABLE_INTR [08:08] */ #define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 #define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_DISABLE_INTR_SHIFT 8 /* SUN_L2 :: CPU_STATUS :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ #define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 #define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 /* SUN_L2 :: CPU_STATUS :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ #define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 #define BCHP_SUN_L2_CPU_STATUS_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 /* SUN_L2 :: CPU_STATUS :: FRONT_PANEL_RESET_INTR [05:05] */ #define BCHP_SUN_L2_CPU_STATUS_FRONT_PANEL_RESET_INTR_MASK 0x00000020 #define BCHP_SUN_L2_CPU_STATUS_FRONT_PANEL_RESET_INTR_SHIFT 5 /* SUN_L2 :: CPU_STATUS :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ #define BCHP_SUN_L2_CPU_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 #define BCHP_SUN_L2_CPU_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 /* SUN_L2 :: CPU_STATUS :: RGR_BRIDGE_ERROR_INTR [03:03] */ #define BCHP_SUN_L2_CPU_STATUS_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 #define BCHP_SUN_L2_CPU_STATUS_RGR_BRIDGE_ERROR_INTR_SHIFT 3 /* SUN_L2 :: CPU_STATUS :: GISB_TEA_INTR [02:02] */ #define BCHP_SUN_L2_CPU_STATUS_GISB_TEA_INTR_MASK 0x00000004 #define BCHP_SUN_L2_CPU_STATUS_GISB_TEA_INTR_SHIFT 2 /* SUN_L2 :: CPU_STATUS :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ #define BCHP_SUN_L2_CPU_STATUS_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 #define BCHP_SUN_L2_CPU_STATUS_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 /* SUN_L2 :: CPU_STATUS :: GISB_TIMEOUT_INTR [00:00] */ #define BCHP_SUN_L2_CPU_STATUS_GISB_TIMEOUT_INTR_MASK 0x00000001 #define BCHP_SUN_L2_CPU_STATUS_GISB_TIMEOUT_INTR_SHIFT 0 /*************************************************************************** *CPU_SET - CPU interrupt Set Register ***************************************************************************/ /* SUN_L2 :: CPU_SET :: SPARE_INTR_31 [31:31] */ #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_31_MASK 0x80000000 #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_31_SHIFT 31 /* SUN_L2 :: CPU_SET :: SPARE_INTR_30 [30:30] */ #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_30_MASK 0x40000000 #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_30_SHIFT 30 /* SUN_L2 :: CPU_SET :: SPARE_INTR_29 [29:29] */ #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_29_MASK 0x20000000 #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_29_SHIFT 29 /* SUN_L2 :: CPU_SET :: SPARE_INTR_28 [28:28] */ #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_28_MASK 0x10000000 #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_28_SHIFT 28 /* SUN_L2 :: CPU_SET :: SPARE_INTR_27 [27:27] */ #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_27_MASK 0x08000000 #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_27_SHIFT 27 /* SUN_L2 :: CPU_SET :: SPARE_INTR_26 [26:26] */ #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_26_MASK 0x04000000 #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_26_SHIFT 26 /* SUN_L2 :: CPU_SET :: SPARE_INTR_25 [25:25] */ #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_25_MASK 0x02000000 #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_25_SHIFT 25 /* SUN_L2 :: CPU_SET :: SPARE_INTR_24 [24:24] */ #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_24_MASK 0x01000000 #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_24_SHIFT 24 /* SUN_L2 :: CPU_SET :: SPARE_INTR_23 [23:23] */ #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_23_MASK 0x00800000 #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_23_SHIFT 23 /* SUN_L2 :: CPU_SET :: SPARE_INTR_22 [22:22] */ #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_22_MASK 0x00400000 #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_22_SHIFT 22 /* SUN_L2 :: CPU_SET :: SPARE_INTR_21 [21:21] */ #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_21_MASK 0x00200000 #define BCHP_SUN_L2_CPU_SET_SPARE_INTR_21_SHIFT 21 /* SUN_L2 :: CPU_SET :: JTAG_GISB_RG_ERROR [20:20] */ #define BCHP_SUN_L2_CPU_SET_JTAG_GISB_RG_ERROR_MASK 0x00100000 #define BCHP_SUN_L2_CPU_SET_JTAG_GISB_RG_ERROR_SHIFT 20 /* SUN_L2 :: CPU_SET :: AUX_INTR [19:19] */ #define BCHP_SUN_L2_CPU_SET_AUX_INTR_MASK 0x00080000 #define BCHP_SUN_L2_CPU_SET_AUX_INTR_SHIFT 19 /* SUN_L2 :: CPU_SET :: SERS_PKT_ERR [18:18] */ #define BCHP_SUN_L2_CPU_SET_SERS_PKT_ERR_MASK 0x00040000 #define BCHP_SUN_L2_CPU_SET_SERS_PKT_ERR_SHIFT 18 /* SUN_L2 :: CPU_SET :: SERS_CLK_ERR [17:17] */ #define BCHP_SUN_L2_CPU_SET_SERS_CLK_ERR_MASK 0x00020000 #define BCHP_SUN_L2_CPU_SET_SERS_CLK_ERR_SHIFT 17 /* union - case mapped_buffer_mode [16:13] */ /* SUN_L2 :: CPU_SET :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ #define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 #define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 /* SUN_L2 :: CPU_SET :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ #define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 #define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 /* SUN_L2 :: CPU_SET :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ #define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 #define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 /* SUN_L2 :: CPU_SET :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ #define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 #define BCHP_SUN_L2_CPU_SET_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 /* union - case cmd_fifo_mode [16:13] */ /* SUN_L2 :: CPU_SET :: cmd_fifo_mode :: reserved0 [16:16] */ #define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_reserved0_MASK 0x00010000 #define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_reserved0_SHIFT 16 /* SUN_L2 :: CPU_SET :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ #define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 #define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 /* SUN_L2 :: CPU_SET :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ #define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 #define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 /* SUN_L2 :: CPU_SET :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ #define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 #define BCHP_SUN_L2_CPU_SET_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 /* SUN_L2 :: CPU_SET :: SERS_R_PKT [12:12] */ #define BCHP_SUN_L2_CPU_SET_SERS_R_PKT_MASK 0x00001000 #define BCHP_SUN_L2_CPU_SET_SERS_R_PKT_SHIFT 12 /* SUN_L2 :: CPU_SET :: WATCHDOG_1_DISABLE_INTR [11:11] */ #define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 #define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_DISABLE_INTR_SHIFT 11 /* SUN_L2 :: CPU_SET :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ #define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 #define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 /* SUN_L2 :: CPU_SET :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ #define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 #define BCHP_SUN_L2_CPU_SET_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 /* SUN_L2 :: CPU_SET :: WATCHDOG_0_DISABLE_INTR [08:08] */ #define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 #define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_DISABLE_INTR_SHIFT 8 /* SUN_L2 :: CPU_SET :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ #define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 #define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 /* SUN_L2 :: CPU_SET :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ #define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 #define BCHP_SUN_L2_CPU_SET_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 /* SUN_L2 :: CPU_SET :: FRONT_PANEL_RESET_INTR [05:05] */ #define BCHP_SUN_L2_CPU_SET_FRONT_PANEL_RESET_INTR_MASK 0x00000020 #define BCHP_SUN_L2_CPU_SET_FRONT_PANEL_RESET_INTR_SHIFT 5 /* SUN_L2 :: CPU_SET :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ #define BCHP_SUN_L2_CPU_SET_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 #define BCHP_SUN_L2_CPU_SET_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 /* SUN_L2 :: CPU_SET :: RGR_BRIDGE_ERROR_INTR [03:03] */ #define BCHP_SUN_L2_CPU_SET_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 #define BCHP_SUN_L2_CPU_SET_RGR_BRIDGE_ERROR_INTR_SHIFT 3 /* SUN_L2 :: CPU_SET :: GISB_TEA_INTR [02:02] */ #define BCHP_SUN_L2_CPU_SET_GISB_TEA_INTR_MASK 0x00000004 #define BCHP_SUN_L2_CPU_SET_GISB_TEA_INTR_SHIFT 2 /* SUN_L2 :: CPU_SET :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ #define BCHP_SUN_L2_CPU_SET_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 #define BCHP_SUN_L2_CPU_SET_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 /* SUN_L2 :: CPU_SET :: GISB_TIMEOUT_INTR [00:00] */ #define BCHP_SUN_L2_CPU_SET_GISB_TIMEOUT_INTR_MASK 0x00000001 #define BCHP_SUN_L2_CPU_SET_GISB_TIMEOUT_INTR_SHIFT 0 /*************************************************************************** *CPU_CLEAR - CPU interrupt Clear Register ***************************************************************************/ /* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_31 [31:31] */ #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_31_MASK 0x80000000 #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_31_SHIFT 31 /* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_30 [30:30] */ #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_30_MASK 0x40000000 #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_30_SHIFT 30 /* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_29 [29:29] */ #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_29_MASK 0x20000000 #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_29_SHIFT 29 /* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_28 [28:28] */ #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_28_MASK 0x10000000 #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_28_SHIFT 28 /* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_27 [27:27] */ #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_27_MASK 0x08000000 #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_27_SHIFT 27 /* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_26 [26:26] */ #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_26_MASK 0x04000000 #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_26_SHIFT 26 /* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_25 [25:25] */ #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_25_MASK 0x02000000 #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_25_SHIFT 25 /* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_24 [24:24] */ #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_24_MASK 0x01000000 #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_24_SHIFT 24 /* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_23 [23:23] */ #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_23_MASK 0x00800000 #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_23_SHIFT 23 /* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_22 [22:22] */ #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_22_MASK 0x00400000 #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_22_SHIFT 22 /* SUN_L2 :: CPU_CLEAR :: SPARE_INTR_21 [21:21] */ #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_21_MASK 0x00200000 #define BCHP_SUN_L2_CPU_CLEAR_SPARE_INTR_21_SHIFT 21 /* SUN_L2 :: CPU_CLEAR :: JTAG_GISB_RG_ERROR [20:20] */ #define BCHP_SUN_L2_CPU_CLEAR_JTAG_GISB_RG_ERROR_MASK 0x00100000 #define BCHP_SUN_L2_CPU_CLEAR_JTAG_GISB_RG_ERROR_SHIFT 20 /* SUN_L2 :: CPU_CLEAR :: AUX_INTR [19:19] */ #define BCHP_SUN_L2_CPU_CLEAR_AUX_INTR_MASK 0x00080000 #define BCHP_SUN_L2_CPU_CLEAR_AUX_INTR_SHIFT 19 /* SUN_L2 :: CPU_CLEAR :: SERS_PKT_ERR [18:18] */ #define BCHP_SUN_L2_CPU_CLEAR_SERS_PKT_ERR_MASK 0x00040000 #define BCHP_SUN_L2_CPU_CLEAR_SERS_PKT_ERR_SHIFT 18 /* SUN_L2 :: CPU_CLEAR :: SERS_CLK_ERR [17:17] */ #define BCHP_SUN_L2_CPU_CLEAR_SERS_CLK_ERR_MASK 0x00020000 #define BCHP_SUN_L2_CPU_CLEAR_SERS_CLK_ERR_SHIFT 17 /* union - case mapped_buffer_mode [16:13] */ /* SUN_L2 :: CPU_CLEAR :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ #define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 #define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 /* SUN_L2 :: CPU_CLEAR :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ #define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 #define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 /* SUN_L2 :: CPU_CLEAR :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ #define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 #define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 /* SUN_L2 :: CPU_CLEAR :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ #define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 #define BCHP_SUN_L2_CPU_CLEAR_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 /* union - case cmd_fifo_mode [16:13] */ /* SUN_L2 :: CPU_CLEAR :: cmd_fifo_mode :: reserved0 [16:16] */ #define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_reserved0_MASK 0x00010000 #define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_reserved0_SHIFT 16 /* SUN_L2 :: CPU_CLEAR :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ #define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 #define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 /* SUN_L2 :: CPU_CLEAR :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ #define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 #define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 /* SUN_L2 :: CPU_CLEAR :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ #define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 #define BCHP_SUN_L2_CPU_CLEAR_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 /* SUN_L2 :: CPU_CLEAR :: SERS_R_PKT [12:12] */ #define BCHP_SUN_L2_CPU_CLEAR_SERS_R_PKT_MASK 0x00001000 #define BCHP_SUN_L2_CPU_CLEAR_SERS_R_PKT_SHIFT 12 /* SUN_L2 :: CPU_CLEAR :: WATCHDOG_1_DISABLE_INTR [11:11] */ #define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 #define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_DISABLE_INTR_SHIFT 11 /* SUN_L2 :: CPU_CLEAR :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ #define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 #define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 /* SUN_L2 :: CPU_CLEAR :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ #define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 #define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 /* SUN_L2 :: CPU_CLEAR :: WATCHDOG_0_DISABLE_INTR [08:08] */ #define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 #define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_DISABLE_INTR_SHIFT 8 /* SUN_L2 :: CPU_CLEAR :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ #define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 #define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 /* SUN_L2 :: CPU_CLEAR :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ #define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 #define BCHP_SUN_L2_CPU_CLEAR_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 /* SUN_L2 :: CPU_CLEAR :: FRONT_PANEL_RESET_INTR [05:05] */ #define BCHP_SUN_L2_CPU_CLEAR_FRONT_PANEL_RESET_INTR_MASK 0x00000020 #define BCHP_SUN_L2_CPU_CLEAR_FRONT_PANEL_RESET_INTR_SHIFT 5 /* SUN_L2 :: CPU_CLEAR :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ #define BCHP_SUN_L2_CPU_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 #define BCHP_SUN_L2_CPU_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 /* SUN_L2 :: CPU_CLEAR :: RGR_BRIDGE_ERROR_INTR [03:03] */ #define BCHP_SUN_L2_CPU_CLEAR_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 #define BCHP_SUN_L2_CPU_CLEAR_RGR_BRIDGE_ERROR_INTR_SHIFT 3 /* SUN_L2 :: CPU_CLEAR :: GISB_TEA_INTR [02:02] */ #define BCHP_SUN_L2_CPU_CLEAR_GISB_TEA_INTR_MASK 0x00000004 #define BCHP_SUN_L2_CPU_CLEAR_GISB_TEA_INTR_SHIFT 2 /* SUN_L2 :: CPU_CLEAR :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ #define BCHP_SUN_L2_CPU_CLEAR_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 #define BCHP_SUN_L2_CPU_CLEAR_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 /* SUN_L2 :: CPU_CLEAR :: GISB_TIMEOUT_INTR [00:00] */ #define BCHP_SUN_L2_CPU_CLEAR_GISB_TIMEOUT_INTR_MASK 0x00000001 #define BCHP_SUN_L2_CPU_CLEAR_GISB_TIMEOUT_INTR_SHIFT 0 /*************************************************************************** *CPU_MASK_STATUS - CPU interrupt Mask Status Register ***************************************************************************/ /* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_31 [31:31] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_31_MASK 0x80000000 #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_31_SHIFT 31 /* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_30 [30:30] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_30_MASK 0x40000000 #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_30_SHIFT 30 /* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_29 [29:29] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_29_MASK 0x20000000 #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_29_SHIFT 29 /* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_28 [28:28] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_28_MASK 0x10000000 #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_28_SHIFT 28 /* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_27 [27:27] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_27_MASK 0x08000000 #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_27_SHIFT 27 /* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_26 [26:26] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_26_MASK 0x04000000 #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_26_SHIFT 26 /* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_25 [25:25] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_25_MASK 0x02000000 #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_25_SHIFT 25 /* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_24 [24:24] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_24_MASK 0x01000000 #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_24_SHIFT 24 /* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_23 [23:23] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_23_MASK 0x00800000 #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_23_SHIFT 23 /* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_22 [22:22] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_22_MASK 0x00400000 #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_22_SHIFT 22 /* SUN_L2 :: CPU_MASK_STATUS :: SPARE_INTR_21 [21:21] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_21_MASK 0x00200000 #define BCHP_SUN_L2_CPU_MASK_STATUS_SPARE_INTR_21_SHIFT 21 /* SUN_L2 :: CPU_MASK_STATUS :: JTAG_GISB_RG_ERROR [20:20] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_JTAG_GISB_RG_ERROR_MASK 0x00100000 #define BCHP_SUN_L2_CPU_MASK_STATUS_JTAG_GISB_RG_ERROR_SHIFT 20 /* SUN_L2 :: CPU_MASK_STATUS :: AUX_INTR [19:19] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_AUX_INTR_MASK 0x00080000 #define BCHP_SUN_L2_CPU_MASK_STATUS_AUX_INTR_SHIFT 19 /* SUN_L2 :: CPU_MASK_STATUS :: SERS_PKT_ERR [18:18] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_PKT_ERR_MASK 0x00040000 #define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_PKT_ERR_SHIFT 18 /* SUN_L2 :: CPU_MASK_STATUS :: SERS_CLK_ERR [17:17] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_CLK_ERR_MASK 0x00020000 #define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_CLK_ERR_SHIFT 17 /* union - case mapped_buffer_mode [16:13] */ /* SUN_L2 :: CPU_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 #define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 /* SUN_L2 :: CPU_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 #define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 /* SUN_L2 :: CPU_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 #define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 /* SUN_L2 :: CPU_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 #define BCHP_SUN_L2_CPU_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 /* union - case cmd_fifo_mode [16:13] */ /* SUN_L2 :: CPU_MASK_STATUS :: cmd_fifo_mode :: reserved0 [16:16] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_reserved0_MASK 0x00010000 #define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_reserved0_SHIFT 16 /* SUN_L2 :: CPU_MASK_STATUS :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 #define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 /* SUN_L2 :: CPU_MASK_STATUS :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 #define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 /* SUN_L2 :: CPU_MASK_STATUS :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 #define BCHP_SUN_L2_CPU_MASK_STATUS_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 /* SUN_L2 :: CPU_MASK_STATUS :: SERS_R_PKT [12:12] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_R_PKT_MASK 0x00001000 #define BCHP_SUN_L2_CPU_MASK_STATUS_SERS_R_PKT_SHIFT 12 /* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_1_DISABLE_INTR [11:11] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 #define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_DISABLE_INTR_SHIFT 11 /* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 #define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 /* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 #define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 /* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_0_DISABLE_INTR [08:08] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 #define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_DISABLE_INTR_SHIFT 8 /* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 #define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 /* SUN_L2 :: CPU_MASK_STATUS :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 #define BCHP_SUN_L2_CPU_MASK_STATUS_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 /* SUN_L2 :: CPU_MASK_STATUS :: FRONT_PANEL_RESET_INTR [05:05] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_FRONT_PANEL_RESET_INTR_MASK 0x00000020 #define BCHP_SUN_L2_CPU_MASK_STATUS_FRONT_PANEL_RESET_INTR_SHIFT 5 /* SUN_L2 :: CPU_MASK_STATUS :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 #define BCHP_SUN_L2_CPU_MASK_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 /* SUN_L2 :: CPU_MASK_STATUS :: RGR_BRIDGE_ERROR_INTR [03:03] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 #define BCHP_SUN_L2_CPU_MASK_STATUS_RGR_BRIDGE_ERROR_INTR_SHIFT 3 /* SUN_L2 :: CPU_MASK_STATUS :: GISB_TEA_INTR [02:02] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_TEA_INTR_MASK 0x00000004 #define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_TEA_INTR_SHIFT 2 /* SUN_L2 :: CPU_MASK_STATUS :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 #define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 /* SUN_L2 :: CPU_MASK_STATUS :: GISB_TIMEOUT_INTR [00:00] */ #define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_TIMEOUT_INTR_MASK 0x00000001 #define BCHP_SUN_L2_CPU_MASK_STATUS_GISB_TIMEOUT_INTR_SHIFT 0 /*************************************************************************** *CPU_MASK_SET - CPU interrupt Mask Set Register ***************************************************************************/ /* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_31 [31:31] */ #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_31_MASK 0x80000000 #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_31_SHIFT 31 /* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_30 [30:30] */ #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_30_MASK 0x40000000 #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_30_SHIFT 30 /* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_29 [29:29] */ #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_29_MASK 0x20000000 #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_29_SHIFT 29 /* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_28 [28:28] */ #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_28_MASK 0x10000000 #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_28_SHIFT 28 /* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_27 [27:27] */ #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_27_MASK 0x08000000 #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_27_SHIFT 27 /* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_26 [26:26] */ #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_26_MASK 0x04000000 #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_26_SHIFT 26 /* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_25 [25:25] */ #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_25_MASK 0x02000000 #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_25_SHIFT 25 /* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_24 [24:24] */ #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_24_MASK 0x01000000 #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_24_SHIFT 24 /* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_23 [23:23] */ #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_23_MASK 0x00800000 #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_23_SHIFT 23 /* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_22 [22:22] */ #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_22_MASK 0x00400000 #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_22_SHIFT 22 /* SUN_L2 :: CPU_MASK_SET :: SPARE_INTR_21 [21:21] */ #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_21_MASK 0x00200000 #define BCHP_SUN_L2_CPU_MASK_SET_SPARE_INTR_21_SHIFT 21 /* SUN_L2 :: CPU_MASK_SET :: JTAG_GISB_RG_ERROR [20:20] */ #define BCHP_SUN_L2_CPU_MASK_SET_JTAG_GISB_RG_ERROR_MASK 0x00100000 #define BCHP_SUN_L2_CPU_MASK_SET_JTAG_GISB_RG_ERROR_SHIFT 20 /* SUN_L2 :: CPU_MASK_SET :: AUX_INTR [19:19] */ #define BCHP_SUN_L2_CPU_MASK_SET_AUX_INTR_MASK 0x00080000 #define BCHP_SUN_L2_CPU_MASK_SET_AUX_INTR_SHIFT 19 /* SUN_L2 :: CPU_MASK_SET :: SERS_PKT_ERR [18:18] */ #define BCHP_SUN_L2_CPU_MASK_SET_SERS_PKT_ERR_MASK 0x00040000 #define BCHP_SUN_L2_CPU_MASK_SET_SERS_PKT_ERR_SHIFT 18 /* SUN_L2 :: CPU_MASK_SET :: SERS_CLK_ERR [17:17] */ #define BCHP_SUN_L2_CPU_MASK_SET_SERS_CLK_ERR_MASK 0x00020000 #define BCHP_SUN_L2_CPU_MASK_SET_SERS_CLK_ERR_SHIFT 17 /* union - case mapped_buffer_mode [16:13] */ /* SUN_L2 :: CPU_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ #define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 #define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 /* SUN_L2 :: CPU_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ #define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 #define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 /* SUN_L2 :: CPU_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ #define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 #define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 /* SUN_L2 :: CPU_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ #define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 #define BCHP_SUN_L2_CPU_MASK_SET_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 /* union - case cmd_fifo_mode [16:13] */ /* SUN_L2 :: CPU_MASK_SET :: cmd_fifo_mode :: reserved0 [16:16] */ #define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_reserved0_MASK 0x00010000 #define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_reserved0_SHIFT 16 /* SUN_L2 :: CPU_MASK_SET :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ #define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 #define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 /* SUN_L2 :: CPU_MASK_SET :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ #define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 #define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 /* SUN_L2 :: CPU_MASK_SET :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ #define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 #define BCHP_SUN_L2_CPU_MASK_SET_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 /* SUN_L2 :: CPU_MASK_SET :: SERS_R_PKT [12:12] */ #define BCHP_SUN_L2_CPU_MASK_SET_SERS_R_PKT_MASK 0x00001000 #define BCHP_SUN_L2_CPU_MASK_SET_SERS_R_PKT_SHIFT 12 /* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_1_DISABLE_INTR [11:11] */ #define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 #define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_DISABLE_INTR_SHIFT 11 /* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ #define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 #define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 /* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ #define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 #define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 /* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_0_DISABLE_INTR [08:08] */ #define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 #define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_DISABLE_INTR_SHIFT 8 /* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ #define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 #define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 /* SUN_L2 :: CPU_MASK_SET :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ #define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 #define BCHP_SUN_L2_CPU_MASK_SET_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 /* SUN_L2 :: CPU_MASK_SET :: FRONT_PANEL_RESET_INTR [05:05] */ #define BCHP_SUN_L2_CPU_MASK_SET_FRONT_PANEL_RESET_INTR_MASK 0x00000020 #define BCHP_SUN_L2_CPU_MASK_SET_FRONT_PANEL_RESET_INTR_SHIFT 5 /* SUN_L2 :: CPU_MASK_SET :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ #define BCHP_SUN_L2_CPU_MASK_SET_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 #define BCHP_SUN_L2_CPU_MASK_SET_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 /* SUN_L2 :: CPU_MASK_SET :: RGR_BRIDGE_ERROR_INTR [03:03] */ #define BCHP_SUN_L2_CPU_MASK_SET_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 #define BCHP_SUN_L2_CPU_MASK_SET_RGR_BRIDGE_ERROR_INTR_SHIFT 3 /* SUN_L2 :: CPU_MASK_SET :: GISB_TEA_INTR [02:02] */ #define BCHP_SUN_L2_CPU_MASK_SET_GISB_TEA_INTR_MASK 0x00000004 #define BCHP_SUN_L2_CPU_MASK_SET_GISB_TEA_INTR_SHIFT 2 /* SUN_L2 :: CPU_MASK_SET :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ #define BCHP_SUN_L2_CPU_MASK_SET_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 #define BCHP_SUN_L2_CPU_MASK_SET_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 /* SUN_L2 :: CPU_MASK_SET :: GISB_TIMEOUT_INTR [00:00] */ #define BCHP_SUN_L2_CPU_MASK_SET_GISB_TIMEOUT_INTR_MASK 0x00000001 #define BCHP_SUN_L2_CPU_MASK_SET_GISB_TIMEOUT_INTR_SHIFT 0 /*************************************************************************** *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register ***************************************************************************/ /* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_31 [31:31] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_31_MASK 0x80000000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_31_SHIFT 31 /* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_30 [30:30] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_30_MASK 0x40000000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_30_SHIFT 30 /* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_29 [29:29] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_29_MASK 0x20000000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_29_SHIFT 29 /* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_28 [28:28] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_28_MASK 0x10000000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_28_SHIFT 28 /* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_27 [27:27] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_27_MASK 0x08000000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_27_SHIFT 27 /* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_26 [26:26] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_26_MASK 0x04000000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_26_SHIFT 26 /* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_25 [25:25] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_25_MASK 0x02000000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_25_SHIFT 25 /* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_24 [24:24] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_24_MASK 0x01000000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_24_SHIFT 24 /* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_23 [23:23] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_23_MASK 0x00800000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_23_SHIFT 23 /* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_22 [22:22] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_22_MASK 0x00400000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_22_SHIFT 22 /* SUN_L2 :: CPU_MASK_CLEAR :: SPARE_INTR_21 [21:21] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_21_MASK 0x00200000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_SPARE_INTR_21_SHIFT 21 /* SUN_L2 :: CPU_MASK_CLEAR :: JTAG_GISB_RG_ERROR [20:20] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_JTAG_GISB_RG_ERROR_MASK 0x00100000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_JTAG_GISB_RG_ERROR_SHIFT 20 /* SUN_L2 :: CPU_MASK_CLEAR :: AUX_INTR [19:19] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_AUX_INTR_MASK 0x00080000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_AUX_INTR_SHIFT 19 /* SUN_L2 :: CPU_MASK_CLEAR :: SERS_PKT_ERR [18:18] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_PKT_ERR_MASK 0x00040000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_PKT_ERR_SHIFT 18 /* SUN_L2 :: CPU_MASK_CLEAR :: SERS_CLK_ERR [17:17] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_CLK_ERR_MASK 0x00020000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_CLK_ERR_SHIFT 17 /* union - case mapped_buffer_mode [16:13] */ /* SUN_L2 :: CPU_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 /* SUN_L2 :: CPU_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 /* SUN_L2 :: CPU_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 /* SUN_L2 :: CPU_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 /* union - case cmd_fifo_mode [16:13] */ /* SUN_L2 :: CPU_MASK_CLEAR :: cmd_fifo_mode :: reserved0 [16:16] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_reserved0_MASK 0x00010000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_reserved0_SHIFT 16 /* SUN_L2 :: CPU_MASK_CLEAR :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 /* SUN_L2 :: CPU_MASK_CLEAR :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 /* SUN_L2 :: CPU_MASK_CLEAR :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 /* SUN_L2 :: CPU_MASK_CLEAR :: SERS_R_PKT [12:12] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_R_PKT_MASK 0x00001000 #define BCHP_SUN_L2_CPU_MASK_CLEAR_SERS_R_PKT_SHIFT 12 /* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_1_DISABLE_INTR [11:11] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 #define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_DISABLE_INTR_SHIFT 11 /* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 #define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 /* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 #define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 /* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_0_DISABLE_INTR [08:08] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 #define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_DISABLE_INTR_SHIFT 8 /* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 #define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 /* SUN_L2 :: CPU_MASK_CLEAR :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 #define BCHP_SUN_L2_CPU_MASK_CLEAR_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 /* SUN_L2 :: CPU_MASK_CLEAR :: FRONT_PANEL_RESET_INTR [05:05] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_FRONT_PANEL_RESET_INTR_MASK 0x00000020 #define BCHP_SUN_L2_CPU_MASK_CLEAR_FRONT_PANEL_RESET_INTR_SHIFT 5 /* SUN_L2 :: CPU_MASK_CLEAR :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 #define BCHP_SUN_L2_CPU_MASK_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 /* SUN_L2 :: CPU_MASK_CLEAR :: RGR_BRIDGE_ERROR_INTR [03:03] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 #define BCHP_SUN_L2_CPU_MASK_CLEAR_RGR_BRIDGE_ERROR_INTR_SHIFT 3 /* SUN_L2 :: CPU_MASK_CLEAR :: GISB_TEA_INTR [02:02] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_TEA_INTR_MASK 0x00000004 #define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_TEA_INTR_SHIFT 2 /* SUN_L2 :: CPU_MASK_CLEAR :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 #define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 /* SUN_L2 :: CPU_MASK_CLEAR :: GISB_TIMEOUT_INTR [00:00] */ #define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_TIMEOUT_INTR_MASK 0x00000001 #define BCHP_SUN_L2_CPU_MASK_CLEAR_GISB_TIMEOUT_INTR_SHIFT 0 /*************************************************************************** *PCI_STATUS - PCI interrupt Status Register ***************************************************************************/ /* SUN_L2 :: PCI_STATUS :: SPARE_INTR_31 [31:31] */ #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_31_MASK 0x80000000 #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_31_SHIFT 31 /* SUN_L2 :: PCI_STATUS :: SPARE_INTR_30 [30:30] */ #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_30_MASK 0x40000000 #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_30_SHIFT 30 /* SUN_L2 :: PCI_STATUS :: SPARE_INTR_29 [29:29] */ #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_29_MASK 0x20000000 #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_29_SHIFT 29 /* SUN_L2 :: PCI_STATUS :: SPARE_INTR_28 [28:28] */ #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_28_MASK 0x10000000 #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_28_SHIFT 28 /* SUN_L2 :: PCI_STATUS :: SPARE_INTR_27 [27:27] */ #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_27_MASK 0x08000000 #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_27_SHIFT 27 /* SUN_L2 :: PCI_STATUS :: SPARE_INTR_26 [26:26] */ #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_26_MASK 0x04000000 #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_26_SHIFT 26 /* SUN_L2 :: PCI_STATUS :: SPARE_INTR_25 [25:25] */ #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_25_MASK 0x02000000 #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_25_SHIFT 25 /* SUN_L2 :: PCI_STATUS :: SPARE_INTR_24 [24:24] */ #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_24_MASK 0x01000000 #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_24_SHIFT 24 /* SUN_L2 :: PCI_STATUS :: SPARE_INTR_23 [23:23] */ #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_23_MASK 0x00800000 #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_23_SHIFT 23 /* SUN_L2 :: PCI_STATUS :: SPARE_INTR_22 [22:22] */ #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_22_MASK 0x00400000 #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_22_SHIFT 22 /* SUN_L2 :: PCI_STATUS :: SPARE_INTR_21 [21:21] */ #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_21_MASK 0x00200000 #define BCHP_SUN_L2_PCI_STATUS_SPARE_INTR_21_SHIFT 21 /* SUN_L2 :: PCI_STATUS :: JTAG_GISB_RG_ERROR [20:20] */ #define BCHP_SUN_L2_PCI_STATUS_JTAG_GISB_RG_ERROR_MASK 0x00100000 #define BCHP_SUN_L2_PCI_STATUS_JTAG_GISB_RG_ERROR_SHIFT 20 /* SUN_L2 :: PCI_STATUS :: AUX_INTR [19:19] */ #define BCHP_SUN_L2_PCI_STATUS_AUX_INTR_MASK 0x00080000 #define BCHP_SUN_L2_PCI_STATUS_AUX_INTR_SHIFT 19 /* SUN_L2 :: PCI_STATUS :: SERS_PKT_ERR [18:18] */ #define BCHP_SUN_L2_PCI_STATUS_SERS_PKT_ERR_MASK 0x00040000 #define BCHP_SUN_L2_PCI_STATUS_SERS_PKT_ERR_SHIFT 18 /* SUN_L2 :: PCI_STATUS :: SERS_CLK_ERR [17:17] */ #define BCHP_SUN_L2_PCI_STATUS_SERS_CLK_ERR_MASK 0x00020000 #define BCHP_SUN_L2_PCI_STATUS_SERS_CLK_ERR_SHIFT 17 /* union - case mapped_buffer_mode [16:13] */ /* SUN_L2 :: PCI_STATUS :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ #define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 #define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 /* SUN_L2 :: PCI_STATUS :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ #define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 #define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 /* SUN_L2 :: PCI_STATUS :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ #define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 #define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 /* SUN_L2 :: PCI_STATUS :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ #define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 #define BCHP_SUN_L2_PCI_STATUS_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 /* union - case cmd_fifo_mode [16:13] */ /* SUN_L2 :: PCI_STATUS :: cmd_fifo_mode :: reserved0 [16:16] */ #define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_reserved0_MASK 0x00010000 #define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_reserved0_SHIFT 16 /* SUN_L2 :: PCI_STATUS :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ #define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 #define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 /* SUN_L2 :: PCI_STATUS :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ #define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 #define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 /* SUN_L2 :: PCI_STATUS :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ #define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 #define BCHP_SUN_L2_PCI_STATUS_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 /* SUN_L2 :: PCI_STATUS :: SERS_R_PKT [12:12] */ #define BCHP_SUN_L2_PCI_STATUS_SERS_R_PKT_MASK 0x00001000 #define BCHP_SUN_L2_PCI_STATUS_SERS_R_PKT_SHIFT 12 /* SUN_L2 :: PCI_STATUS :: WATCHDOG_1_DISABLE_INTR [11:11] */ #define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 #define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_DISABLE_INTR_SHIFT 11 /* SUN_L2 :: PCI_STATUS :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ #define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 #define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 /* SUN_L2 :: PCI_STATUS :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ #define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 #define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 /* SUN_L2 :: PCI_STATUS :: WATCHDOG_0_DISABLE_INTR [08:08] */ #define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 #define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_DISABLE_INTR_SHIFT 8 /* SUN_L2 :: PCI_STATUS :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ #define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 #define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 /* SUN_L2 :: PCI_STATUS :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ #define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 #define BCHP_SUN_L2_PCI_STATUS_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 /* SUN_L2 :: PCI_STATUS :: FRONT_PANEL_RESET_INTR [05:05] */ #define BCHP_SUN_L2_PCI_STATUS_FRONT_PANEL_RESET_INTR_MASK 0x00000020 #define BCHP_SUN_L2_PCI_STATUS_FRONT_PANEL_RESET_INTR_SHIFT 5 /* SUN_L2 :: PCI_STATUS :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ #define BCHP_SUN_L2_PCI_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 #define BCHP_SUN_L2_PCI_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 /* SUN_L2 :: PCI_STATUS :: RGR_BRIDGE_ERROR_INTR [03:03] */ #define BCHP_SUN_L2_PCI_STATUS_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 #define BCHP_SUN_L2_PCI_STATUS_RGR_BRIDGE_ERROR_INTR_SHIFT 3 /* SUN_L2 :: PCI_STATUS :: GISB_TEA_INTR [02:02] */ #define BCHP_SUN_L2_PCI_STATUS_GISB_TEA_INTR_MASK 0x00000004 #define BCHP_SUN_L2_PCI_STATUS_GISB_TEA_INTR_SHIFT 2 /* SUN_L2 :: PCI_STATUS :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ #define BCHP_SUN_L2_PCI_STATUS_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 #define BCHP_SUN_L2_PCI_STATUS_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 /* SUN_L2 :: PCI_STATUS :: GISB_TIMEOUT_INTR [00:00] */ #define BCHP_SUN_L2_PCI_STATUS_GISB_TIMEOUT_INTR_MASK 0x00000001 #define BCHP_SUN_L2_PCI_STATUS_GISB_TIMEOUT_INTR_SHIFT 0 /*************************************************************************** *PCI_SET - PCI interrupt Set Register ***************************************************************************/ /* SUN_L2 :: PCI_SET :: SPARE_INTR_31 [31:31] */ #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_31_MASK 0x80000000 #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_31_SHIFT 31 /* SUN_L2 :: PCI_SET :: SPARE_INTR_30 [30:30] */ #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_30_MASK 0x40000000 #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_30_SHIFT 30 /* SUN_L2 :: PCI_SET :: SPARE_INTR_29 [29:29] */ #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_29_MASK 0x20000000 #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_29_SHIFT 29 /* SUN_L2 :: PCI_SET :: SPARE_INTR_28 [28:28] */ #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_28_MASK 0x10000000 #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_28_SHIFT 28 /* SUN_L2 :: PCI_SET :: SPARE_INTR_27 [27:27] */ #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_27_MASK 0x08000000 #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_27_SHIFT 27 /* SUN_L2 :: PCI_SET :: SPARE_INTR_26 [26:26] */ #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_26_MASK 0x04000000 #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_26_SHIFT 26 /* SUN_L2 :: PCI_SET :: SPARE_INTR_25 [25:25] */ #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_25_MASK 0x02000000 #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_25_SHIFT 25 /* SUN_L2 :: PCI_SET :: SPARE_INTR_24 [24:24] */ #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_24_MASK 0x01000000 #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_24_SHIFT 24 /* SUN_L2 :: PCI_SET :: SPARE_INTR_23 [23:23] */ #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_23_MASK 0x00800000 #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_23_SHIFT 23 /* SUN_L2 :: PCI_SET :: SPARE_INTR_22 [22:22] */ #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_22_MASK 0x00400000 #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_22_SHIFT 22 /* SUN_L2 :: PCI_SET :: SPARE_INTR_21 [21:21] */ #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_21_MASK 0x00200000 #define BCHP_SUN_L2_PCI_SET_SPARE_INTR_21_SHIFT 21 /* SUN_L2 :: PCI_SET :: JTAG_GISB_RG_ERROR [20:20] */ #define BCHP_SUN_L2_PCI_SET_JTAG_GISB_RG_ERROR_MASK 0x00100000 #define BCHP_SUN_L2_PCI_SET_JTAG_GISB_RG_ERROR_SHIFT 20 /* SUN_L2 :: PCI_SET :: AUX_INTR [19:19] */ #define BCHP_SUN_L2_PCI_SET_AUX_INTR_MASK 0x00080000 #define BCHP_SUN_L2_PCI_SET_AUX_INTR_SHIFT 19 /* SUN_L2 :: PCI_SET :: SERS_PKT_ERR [18:18] */ #define BCHP_SUN_L2_PCI_SET_SERS_PKT_ERR_MASK 0x00040000 #define BCHP_SUN_L2_PCI_SET_SERS_PKT_ERR_SHIFT 18 /* SUN_L2 :: PCI_SET :: SERS_CLK_ERR [17:17] */ #define BCHP_SUN_L2_PCI_SET_SERS_CLK_ERR_MASK 0x00020000 #define BCHP_SUN_L2_PCI_SET_SERS_CLK_ERR_SHIFT 17 /* union - case mapped_buffer_mode [16:13] */ /* SUN_L2 :: PCI_SET :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ #define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 #define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 /* SUN_L2 :: PCI_SET :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ #define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 #define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 /* SUN_L2 :: PCI_SET :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ #define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 #define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 /* SUN_L2 :: PCI_SET :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ #define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 #define BCHP_SUN_L2_PCI_SET_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 /* union - case cmd_fifo_mode [16:13] */ /* SUN_L2 :: PCI_SET :: cmd_fifo_mode :: reserved0 [16:16] */ #define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_reserved0_MASK 0x00010000 #define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_reserved0_SHIFT 16 /* SUN_L2 :: PCI_SET :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ #define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 #define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 /* SUN_L2 :: PCI_SET :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ #define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 #define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 /* SUN_L2 :: PCI_SET :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ #define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 #define BCHP_SUN_L2_PCI_SET_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 /* SUN_L2 :: PCI_SET :: SERS_R_PKT [12:12] */ #define BCHP_SUN_L2_PCI_SET_SERS_R_PKT_MASK 0x00001000 #define BCHP_SUN_L2_PCI_SET_SERS_R_PKT_SHIFT 12 /* SUN_L2 :: PCI_SET :: WATCHDOG_1_DISABLE_INTR [11:11] */ #define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 #define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_DISABLE_INTR_SHIFT 11 /* SUN_L2 :: PCI_SET :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ #define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 #define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 /* SUN_L2 :: PCI_SET :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ #define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 #define BCHP_SUN_L2_PCI_SET_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 /* SUN_L2 :: PCI_SET :: WATCHDOG_0_DISABLE_INTR [08:08] */ #define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 #define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_DISABLE_INTR_SHIFT 8 /* SUN_L2 :: PCI_SET :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ #define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 #define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 /* SUN_L2 :: PCI_SET :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ #define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 #define BCHP_SUN_L2_PCI_SET_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 /* SUN_L2 :: PCI_SET :: FRONT_PANEL_RESET_INTR [05:05] */ #define BCHP_SUN_L2_PCI_SET_FRONT_PANEL_RESET_INTR_MASK 0x00000020 #define BCHP_SUN_L2_PCI_SET_FRONT_PANEL_RESET_INTR_SHIFT 5 /* SUN_L2 :: PCI_SET :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ #define BCHP_SUN_L2_PCI_SET_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 #define BCHP_SUN_L2_PCI_SET_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 /* SUN_L2 :: PCI_SET :: RGR_BRIDGE_ERROR_INTR [03:03] */ #define BCHP_SUN_L2_PCI_SET_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 #define BCHP_SUN_L2_PCI_SET_RGR_BRIDGE_ERROR_INTR_SHIFT 3 /* SUN_L2 :: PCI_SET :: GISB_TEA_INTR [02:02] */ #define BCHP_SUN_L2_PCI_SET_GISB_TEA_INTR_MASK 0x00000004 #define BCHP_SUN_L2_PCI_SET_GISB_TEA_INTR_SHIFT 2 /* SUN_L2 :: PCI_SET :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ #define BCHP_SUN_L2_PCI_SET_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 #define BCHP_SUN_L2_PCI_SET_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 /* SUN_L2 :: PCI_SET :: GISB_TIMEOUT_INTR [00:00] */ #define BCHP_SUN_L2_PCI_SET_GISB_TIMEOUT_INTR_MASK 0x00000001 #define BCHP_SUN_L2_PCI_SET_GISB_TIMEOUT_INTR_SHIFT 0 /*************************************************************************** *PCI_CLEAR - PCI interrupt Clear Register ***************************************************************************/ /* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_31 [31:31] */ #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_31_MASK 0x80000000 #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_31_SHIFT 31 /* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_30 [30:30] */ #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_30_MASK 0x40000000 #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_30_SHIFT 30 /* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_29 [29:29] */ #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_29_MASK 0x20000000 #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_29_SHIFT 29 /* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_28 [28:28] */ #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_28_MASK 0x10000000 #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_28_SHIFT 28 /* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_27 [27:27] */ #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_27_MASK 0x08000000 #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_27_SHIFT 27 /* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_26 [26:26] */ #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_26_MASK 0x04000000 #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_26_SHIFT 26 /* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_25 [25:25] */ #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_25_MASK 0x02000000 #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_25_SHIFT 25 /* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_24 [24:24] */ #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_24_MASK 0x01000000 #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_24_SHIFT 24 /* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_23 [23:23] */ #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_23_MASK 0x00800000 #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_23_SHIFT 23 /* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_22 [22:22] */ #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_22_MASK 0x00400000 #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_22_SHIFT 22 /* SUN_L2 :: PCI_CLEAR :: SPARE_INTR_21 [21:21] */ #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_21_MASK 0x00200000 #define BCHP_SUN_L2_PCI_CLEAR_SPARE_INTR_21_SHIFT 21 /* SUN_L2 :: PCI_CLEAR :: JTAG_GISB_RG_ERROR [20:20] */ #define BCHP_SUN_L2_PCI_CLEAR_JTAG_GISB_RG_ERROR_MASK 0x00100000 #define BCHP_SUN_L2_PCI_CLEAR_JTAG_GISB_RG_ERROR_SHIFT 20 /* SUN_L2 :: PCI_CLEAR :: AUX_INTR [19:19] */ #define BCHP_SUN_L2_PCI_CLEAR_AUX_INTR_MASK 0x00080000 #define BCHP_SUN_L2_PCI_CLEAR_AUX_INTR_SHIFT 19 /* SUN_L2 :: PCI_CLEAR :: SERS_PKT_ERR [18:18] */ #define BCHP_SUN_L2_PCI_CLEAR_SERS_PKT_ERR_MASK 0x00040000 #define BCHP_SUN_L2_PCI_CLEAR_SERS_PKT_ERR_SHIFT 18 /* SUN_L2 :: PCI_CLEAR :: SERS_CLK_ERR [17:17] */ #define BCHP_SUN_L2_PCI_CLEAR_SERS_CLK_ERR_MASK 0x00020000 #define BCHP_SUN_L2_PCI_CLEAR_SERS_CLK_ERR_SHIFT 17 /* union - case mapped_buffer_mode [16:13] */ /* SUN_L2 :: PCI_CLEAR :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ #define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 #define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 /* SUN_L2 :: PCI_CLEAR :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ #define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 #define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 /* SUN_L2 :: PCI_CLEAR :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ #define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 #define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 /* SUN_L2 :: PCI_CLEAR :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ #define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 #define BCHP_SUN_L2_PCI_CLEAR_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 /* union - case cmd_fifo_mode [16:13] */ /* SUN_L2 :: PCI_CLEAR :: cmd_fifo_mode :: reserved0 [16:16] */ #define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_reserved0_MASK 0x00010000 #define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_reserved0_SHIFT 16 /* SUN_L2 :: PCI_CLEAR :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ #define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 #define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 /* SUN_L2 :: PCI_CLEAR :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ #define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 #define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 /* SUN_L2 :: PCI_CLEAR :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ #define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 #define BCHP_SUN_L2_PCI_CLEAR_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 /* SUN_L2 :: PCI_CLEAR :: SERS_R_PKT [12:12] */ #define BCHP_SUN_L2_PCI_CLEAR_SERS_R_PKT_MASK 0x00001000 #define BCHP_SUN_L2_PCI_CLEAR_SERS_R_PKT_SHIFT 12 /* SUN_L2 :: PCI_CLEAR :: WATCHDOG_1_DISABLE_INTR [11:11] */ #define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 #define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_DISABLE_INTR_SHIFT 11 /* SUN_L2 :: PCI_CLEAR :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ #define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 #define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 /* SUN_L2 :: PCI_CLEAR :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ #define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 #define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 /* SUN_L2 :: PCI_CLEAR :: WATCHDOG_0_DISABLE_INTR [08:08] */ #define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 #define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_DISABLE_INTR_SHIFT 8 /* SUN_L2 :: PCI_CLEAR :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ #define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 #define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 /* SUN_L2 :: PCI_CLEAR :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ #define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 #define BCHP_SUN_L2_PCI_CLEAR_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 /* SUN_L2 :: PCI_CLEAR :: FRONT_PANEL_RESET_INTR [05:05] */ #define BCHP_SUN_L2_PCI_CLEAR_FRONT_PANEL_RESET_INTR_MASK 0x00000020 #define BCHP_SUN_L2_PCI_CLEAR_FRONT_PANEL_RESET_INTR_SHIFT 5 /* SUN_L2 :: PCI_CLEAR :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ #define BCHP_SUN_L2_PCI_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 #define BCHP_SUN_L2_PCI_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 /* SUN_L2 :: PCI_CLEAR :: RGR_BRIDGE_ERROR_INTR [03:03] */ #define BCHP_SUN_L2_PCI_CLEAR_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 #define BCHP_SUN_L2_PCI_CLEAR_RGR_BRIDGE_ERROR_INTR_SHIFT 3 /* SUN_L2 :: PCI_CLEAR :: GISB_TEA_INTR [02:02] */ #define BCHP_SUN_L2_PCI_CLEAR_GISB_TEA_INTR_MASK 0x00000004 #define BCHP_SUN_L2_PCI_CLEAR_GISB_TEA_INTR_SHIFT 2 /* SUN_L2 :: PCI_CLEAR :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ #define BCHP_SUN_L2_PCI_CLEAR_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 #define BCHP_SUN_L2_PCI_CLEAR_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 /* SUN_L2 :: PCI_CLEAR :: GISB_TIMEOUT_INTR [00:00] */ #define BCHP_SUN_L2_PCI_CLEAR_GISB_TIMEOUT_INTR_MASK 0x00000001 #define BCHP_SUN_L2_PCI_CLEAR_GISB_TIMEOUT_INTR_SHIFT 0 /*************************************************************************** *PCI_MASK_STATUS - PCI interrupt Mask Status Register ***************************************************************************/ /* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_31 [31:31] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_31_MASK 0x80000000 #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_31_SHIFT 31 /* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_30 [30:30] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_30_MASK 0x40000000 #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_30_SHIFT 30 /* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_29 [29:29] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_29_MASK 0x20000000 #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_29_SHIFT 29 /* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_28 [28:28] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_28_MASK 0x10000000 #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_28_SHIFT 28 /* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_27 [27:27] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_27_MASK 0x08000000 #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_27_SHIFT 27 /* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_26 [26:26] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_26_MASK 0x04000000 #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_26_SHIFT 26 /* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_25 [25:25] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_25_MASK 0x02000000 #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_25_SHIFT 25 /* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_24 [24:24] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_24_MASK 0x01000000 #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_24_SHIFT 24 /* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_23 [23:23] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_23_MASK 0x00800000 #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_23_SHIFT 23 /* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_22 [22:22] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_22_MASK 0x00400000 #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_22_SHIFT 22 /* SUN_L2 :: PCI_MASK_STATUS :: SPARE_INTR_21 [21:21] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_21_MASK 0x00200000 #define BCHP_SUN_L2_PCI_MASK_STATUS_SPARE_INTR_21_SHIFT 21 /* SUN_L2 :: PCI_MASK_STATUS :: JTAG_GISB_RG_ERROR [20:20] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_JTAG_GISB_RG_ERROR_MASK 0x00100000 #define BCHP_SUN_L2_PCI_MASK_STATUS_JTAG_GISB_RG_ERROR_SHIFT 20 /* SUN_L2 :: PCI_MASK_STATUS :: AUX_INTR [19:19] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_AUX_INTR_MASK 0x00080000 #define BCHP_SUN_L2_PCI_MASK_STATUS_AUX_INTR_SHIFT 19 /* SUN_L2 :: PCI_MASK_STATUS :: SERS_PKT_ERR [18:18] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_PKT_ERR_MASK 0x00040000 #define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_PKT_ERR_SHIFT 18 /* SUN_L2 :: PCI_MASK_STATUS :: SERS_CLK_ERR [17:17] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_CLK_ERR_MASK 0x00020000 #define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_CLK_ERR_SHIFT 17 /* union - case mapped_buffer_mode [16:13] */ /* SUN_L2 :: PCI_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 #define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 /* SUN_L2 :: PCI_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 #define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 /* SUN_L2 :: PCI_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 #define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 /* SUN_L2 :: PCI_MASK_STATUS :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 #define BCHP_SUN_L2_PCI_MASK_STATUS_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 /* union - case cmd_fifo_mode [16:13] */ /* SUN_L2 :: PCI_MASK_STATUS :: cmd_fifo_mode :: reserved0 [16:16] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_reserved0_MASK 0x00010000 #define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_reserved0_SHIFT 16 /* SUN_L2 :: PCI_MASK_STATUS :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 #define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 /* SUN_L2 :: PCI_MASK_STATUS :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 #define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 /* SUN_L2 :: PCI_MASK_STATUS :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 #define BCHP_SUN_L2_PCI_MASK_STATUS_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 /* SUN_L2 :: PCI_MASK_STATUS :: SERS_R_PKT [12:12] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_R_PKT_MASK 0x00001000 #define BCHP_SUN_L2_PCI_MASK_STATUS_SERS_R_PKT_SHIFT 12 /* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_1_DISABLE_INTR [11:11] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 #define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_DISABLE_INTR_SHIFT 11 /* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 #define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 /* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 #define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 /* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_0_DISABLE_INTR [08:08] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 #define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_DISABLE_INTR_SHIFT 8 /* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 #define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 /* SUN_L2 :: PCI_MASK_STATUS :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 #define BCHP_SUN_L2_PCI_MASK_STATUS_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 /* SUN_L2 :: PCI_MASK_STATUS :: FRONT_PANEL_RESET_INTR [05:05] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_FRONT_PANEL_RESET_INTR_MASK 0x00000020 #define BCHP_SUN_L2_PCI_MASK_STATUS_FRONT_PANEL_RESET_INTR_SHIFT 5 /* SUN_L2 :: PCI_MASK_STATUS :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 #define BCHP_SUN_L2_PCI_MASK_STATUS_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 /* SUN_L2 :: PCI_MASK_STATUS :: RGR_BRIDGE_ERROR_INTR [03:03] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 #define BCHP_SUN_L2_PCI_MASK_STATUS_RGR_BRIDGE_ERROR_INTR_SHIFT 3 /* SUN_L2 :: PCI_MASK_STATUS :: GISB_TEA_INTR [02:02] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_TEA_INTR_MASK 0x00000004 #define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_TEA_INTR_SHIFT 2 /* SUN_L2 :: PCI_MASK_STATUS :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 #define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 /* SUN_L2 :: PCI_MASK_STATUS :: GISB_TIMEOUT_INTR [00:00] */ #define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_TIMEOUT_INTR_MASK 0x00000001 #define BCHP_SUN_L2_PCI_MASK_STATUS_GISB_TIMEOUT_INTR_SHIFT 0 /*************************************************************************** *PCI_MASK_SET - PCI interrupt Mask Set Register ***************************************************************************/ /* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_31 [31:31] */ #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_31_MASK 0x80000000 #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_31_SHIFT 31 /* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_30 [30:30] */ #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_30_MASK 0x40000000 #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_30_SHIFT 30 /* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_29 [29:29] */ #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_29_MASK 0x20000000 #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_29_SHIFT 29 /* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_28 [28:28] */ #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_28_MASK 0x10000000 #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_28_SHIFT 28 /* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_27 [27:27] */ #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_27_MASK 0x08000000 #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_27_SHIFT 27 /* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_26 [26:26] */ #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_26_MASK 0x04000000 #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_26_SHIFT 26 /* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_25 [25:25] */ #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_25_MASK 0x02000000 #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_25_SHIFT 25 /* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_24 [24:24] */ #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_24_MASK 0x01000000 #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_24_SHIFT 24 /* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_23 [23:23] */ #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_23_MASK 0x00800000 #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_23_SHIFT 23 /* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_22 [22:22] */ #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_22_MASK 0x00400000 #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_22_SHIFT 22 /* SUN_L2 :: PCI_MASK_SET :: SPARE_INTR_21 [21:21] */ #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_21_MASK 0x00200000 #define BCHP_SUN_L2_PCI_MASK_SET_SPARE_INTR_21_SHIFT 21 /* SUN_L2 :: PCI_MASK_SET :: JTAG_GISB_RG_ERROR [20:20] */ #define BCHP_SUN_L2_PCI_MASK_SET_JTAG_GISB_RG_ERROR_MASK 0x00100000 #define BCHP_SUN_L2_PCI_MASK_SET_JTAG_GISB_RG_ERROR_SHIFT 20 /* SUN_L2 :: PCI_MASK_SET :: AUX_INTR [19:19] */ #define BCHP_SUN_L2_PCI_MASK_SET_AUX_INTR_MASK 0x00080000 #define BCHP_SUN_L2_PCI_MASK_SET_AUX_INTR_SHIFT 19 /* SUN_L2 :: PCI_MASK_SET :: SERS_PKT_ERR [18:18] */ #define BCHP_SUN_L2_PCI_MASK_SET_SERS_PKT_ERR_MASK 0x00040000 #define BCHP_SUN_L2_PCI_MASK_SET_SERS_PKT_ERR_SHIFT 18 /* SUN_L2 :: PCI_MASK_SET :: SERS_CLK_ERR [17:17] */ #define BCHP_SUN_L2_PCI_MASK_SET_SERS_CLK_ERR_MASK 0x00020000 #define BCHP_SUN_L2_PCI_MASK_SET_SERS_CLK_ERR_SHIFT 17 /* union - case mapped_buffer_mode [16:13] */ /* SUN_L2 :: PCI_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ #define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 #define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 /* SUN_L2 :: PCI_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ #define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 #define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 /* SUN_L2 :: PCI_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ #define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 #define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 /* SUN_L2 :: PCI_MASK_SET :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ #define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 #define BCHP_SUN_L2_PCI_MASK_SET_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 /* union - case cmd_fifo_mode [16:13] */ /* SUN_L2 :: PCI_MASK_SET :: cmd_fifo_mode :: reserved0 [16:16] */ #define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_reserved0_MASK 0x00010000 #define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_reserved0_SHIFT 16 /* SUN_L2 :: PCI_MASK_SET :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ #define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 #define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 /* SUN_L2 :: PCI_MASK_SET :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ #define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 #define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 /* SUN_L2 :: PCI_MASK_SET :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ #define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 #define BCHP_SUN_L2_PCI_MASK_SET_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 /* SUN_L2 :: PCI_MASK_SET :: SERS_R_PKT [12:12] */ #define BCHP_SUN_L2_PCI_MASK_SET_SERS_R_PKT_MASK 0x00001000 #define BCHP_SUN_L2_PCI_MASK_SET_SERS_R_PKT_SHIFT 12 /* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_1_DISABLE_INTR [11:11] */ #define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 #define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_DISABLE_INTR_SHIFT 11 /* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ #define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 #define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 /* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ #define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 #define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 /* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_0_DISABLE_INTR [08:08] */ #define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 #define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_DISABLE_INTR_SHIFT 8 /* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ #define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 #define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 /* SUN_L2 :: PCI_MASK_SET :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ #define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 #define BCHP_SUN_L2_PCI_MASK_SET_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 /* SUN_L2 :: PCI_MASK_SET :: FRONT_PANEL_RESET_INTR [05:05] */ #define BCHP_SUN_L2_PCI_MASK_SET_FRONT_PANEL_RESET_INTR_MASK 0x00000020 #define BCHP_SUN_L2_PCI_MASK_SET_FRONT_PANEL_RESET_INTR_SHIFT 5 /* SUN_L2 :: PCI_MASK_SET :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ #define BCHP_SUN_L2_PCI_MASK_SET_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 #define BCHP_SUN_L2_PCI_MASK_SET_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 /* SUN_L2 :: PCI_MASK_SET :: RGR_BRIDGE_ERROR_INTR [03:03] */ #define BCHP_SUN_L2_PCI_MASK_SET_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 #define BCHP_SUN_L2_PCI_MASK_SET_RGR_BRIDGE_ERROR_INTR_SHIFT 3 /* SUN_L2 :: PCI_MASK_SET :: GISB_TEA_INTR [02:02] */ #define BCHP_SUN_L2_PCI_MASK_SET_GISB_TEA_INTR_MASK 0x00000004 #define BCHP_SUN_L2_PCI_MASK_SET_GISB_TEA_INTR_SHIFT 2 /* SUN_L2 :: PCI_MASK_SET :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ #define BCHP_SUN_L2_PCI_MASK_SET_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 #define BCHP_SUN_L2_PCI_MASK_SET_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 /* SUN_L2 :: PCI_MASK_SET :: GISB_TIMEOUT_INTR [00:00] */ #define BCHP_SUN_L2_PCI_MASK_SET_GISB_TIMEOUT_INTR_MASK 0x00000001 #define BCHP_SUN_L2_PCI_MASK_SET_GISB_TIMEOUT_INTR_SHIFT 0 /*************************************************************************** *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register ***************************************************************************/ /* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_31 [31:31] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_31_MASK 0x80000000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_31_SHIFT 31 /* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_30 [30:30] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_30_MASK 0x40000000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_30_SHIFT 30 /* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_29 [29:29] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_29_MASK 0x20000000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_29_SHIFT 29 /* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_28 [28:28] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_28_MASK 0x10000000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_28_SHIFT 28 /* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_27 [27:27] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_27_MASK 0x08000000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_27_SHIFT 27 /* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_26 [26:26] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_26_MASK 0x04000000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_26_SHIFT 26 /* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_25 [25:25] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_25_MASK 0x02000000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_25_SHIFT 25 /* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_24 [24:24] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_24_MASK 0x01000000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_24_SHIFT 24 /* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_23 [23:23] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_23_MASK 0x00800000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_23_SHIFT 23 /* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_22 [22:22] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_22_MASK 0x00400000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_22_SHIFT 22 /* SUN_L2 :: PCI_MASK_CLEAR :: SPARE_INTR_21 [21:21] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_21_MASK 0x00200000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_SPARE_INTR_21_SHIFT 21 /* SUN_L2 :: PCI_MASK_CLEAR :: JTAG_GISB_RG_ERROR [20:20] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_JTAG_GISB_RG_ERROR_MASK 0x00100000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_JTAG_GISB_RG_ERROR_SHIFT 20 /* SUN_L2 :: PCI_MASK_CLEAR :: AUX_INTR [19:19] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_AUX_INTR_MASK 0x00080000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_AUX_INTR_SHIFT 19 /* SUN_L2 :: PCI_MASK_CLEAR :: SERS_PKT_ERR [18:18] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_PKT_ERR_MASK 0x00040000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_PKT_ERR_SHIFT 18 /* SUN_L2 :: PCI_MASK_CLEAR :: SERS_CLK_ERR [17:17] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_CLK_ERR_MASK 0x00020000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_CLK_ERR_SHIFT 17 /* union - case mapped_buffer_mode [16:13] */ /* SUN_L2 :: PCI_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT4 [16:16] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT4_MASK 0x00010000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT4_SHIFT 16 /* SUN_L2 :: PCI_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT3 [15:15] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT3_MASK 0x00008000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT3_SHIFT 15 /* SUN_L2 :: PCI_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT2 [14:14] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT2_MASK 0x00004000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT2_SHIFT 14 /* SUN_L2 :: PCI_MASK_CLEAR :: mapped_buffer_mode :: SERS_W_PKT1 [13:13] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT1_MASK 0x00002000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_mapped_buffer_mode_SERS_W_PKT1_SHIFT 13 /* union - case cmd_fifo_mode [16:13] */ /* SUN_L2 :: PCI_MASK_CLEAR :: cmd_fifo_mode :: reserved0 [16:16] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_reserved0_MASK 0x00010000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_reserved0_SHIFT 16 /* SUN_L2 :: PCI_MASK_CLEAR :: cmd_fifo_mode :: SERS_FIFO_FULL [15:15] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_MASK 0x00008000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_FULL_SHIFT 15 /* SUN_L2 :: PCI_MASK_CLEAR :: cmd_fifo_mode :: SERS_FIFO_THRESHOLD [14:14] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_MASK 0x00004000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_FIFO_THRESHOLD_SHIFT 14 /* SUN_L2 :: PCI_MASK_CLEAR :: cmd_fifo_mode :: SERS_W_PKT [13:13] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_W_PKT_MASK 0x00002000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_cmd_fifo_mode_SERS_W_PKT_SHIFT 13 /* SUN_L2 :: PCI_MASK_CLEAR :: SERS_R_PKT [12:12] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_R_PKT_MASK 0x00001000 #define BCHP_SUN_L2_PCI_MASK_CLEAR_SERS_R_PKT_SHIFT 12 /* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_1_DISABLE_INTR [11:11] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_DISABLE_INTR_MASK 0x00000800 #define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_DISABLE_INTR_SHIFT 11 /* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_1_WR_ERROR_INTR [10:10] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_WR_ERROR_INTR_MASK 0x00000400 #define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_WR_ERROR_INTR_SHIFT 10 /* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_1_TIMEOUT_INTR [09:09] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_TIMEOUT_INTR_MASK 0x00000200 #define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_1_TIMEOUT_INTR_SHIFT 9 /* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_0_DISABLE_INTR [08:08] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_DISABLE_INTR_MASK 0x00000100 #define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_DISABLE_INTR_SHIFT 8 /* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_0_WR_ERROR_INTR [07:07] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_WR_ERROR_INTR_MASK 0x00000080 #define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_WR_ERROR_INTR_SHIFT 7 /* SUN_L2 :: PCI_MASK_CLEAR :: WATCHDOG_0_TIMEOUT_INTR [06:06] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_TIMEOUT_INTR_MASK 0x00000040 #define BCHP_SUN_L2_PCI_MASK_CLEAR_WATCHDOG_0_TIMEOUT_INTR_SHIFT 6 /* SUN_L2 :: PCI_MASK_CLEAR :: FRONT_PANEL_RESET_INTR [05:05] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_FRONT_PANEL_RESET_INTR_MASK 0x00000020 #define BCHP_SUN_L2_PCI_MASK_CLEAR_FRONT_PANEL_RESET_INTR_SHIFT 5 /* SUN_L2 :: PCI_MASK_CLEAR :: CLK_GEN_BRIDGE_ERROR_INTR [04:04] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_MASK 0x00000010 #define BCHP_SUN_L2_PCI_MASK_CLEAR_CLK_GEN_BRIDGE_ERROR_INTR_SHIFT 4 /* SUN_L2 :: PCI_MASK_CLEAR :: RGR_BRIDGE_ERROR_INTR [03:03] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_RGR_BRIDGE_ERROR_INTR_MASK 0x00000008 #define BCHP_SUN_L2_PCI_MASK_CLEAR_RGR_BRIDGE_ERROR_INTR_SHIFT 3 /* SUN_L2 :: PCI_MASK_CLEAR :: GISB_TEA_INTR [02:02] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_TEA_INTR_MASK 0x00000004 #define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_TEA_INTR_SHIFT 2 /* SUN_L2 :: PCI_MASK_CLEAR :: GISB_BREAKPOINT_ERROR_INTR [01:01] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_BREAKPOINT_ERROR_INTR_MASK 0x00000002 #define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_BREAKPOINT_ERROR_INTR_SHIFT 1 /* SUN_L2 :: PCI_MASK_CLEAR :: GISB_TIMEOUT_INTR [00:00] */ #define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_TIMEOUT_INTR_MASK 0x00000001 #define BCHP_SUN_L2_PCI_MASK_CLEAR_GISB_TIMEOUT_INTR_SHIFT 0 #endif /* #ifndef BCHP_SUN_L2_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015000000000000011561 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mmscram.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_mmscra0000644000175000017500000000603511610313111031024 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_mmscram.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:12p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:09 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_mmscram.h $ * * Hydra_Software_Devel/1 7/17/09 8:12p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_MMSCRAM_H__ #define BCHP_MMSCRAM_H__ /*************************************************************************** *MMSCRAM - MMSCRAM Registers ***************************************************************************/ #define BCHP_MMSCRAM_RSV_S 0x000fd000 /* RESERVED */ #define BCHP_MMSCRAM_RSV_E 0x000feffc /* RESERVED */ /*************************************************************************** *RSV_S - RESERVED ***************************************************************************/ /* MMSCRAM :: RSV_S :: reserved0 [31:00] */ #define BCHP_MMSCRAM_RSV_S_reserved0_MASK 0xffffffff #define BCHP_MMSCRAM_RSV_S_reserved0_SHIFT 0 /*************************************************************************** *RSV_E - RESERVED ***************************************************************************/ /* MMSCRAM :: RSV_E :: reserved0 [31:00] */ #define BCHP_MMSCRAM_RSV_E_reserved0_MASK 0xffffffff #define BCHP_MMSCRAM_RSV_E_reserved0_SHIFT 0 #endif /* #ifndef BCHP_MMSCRAM_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015000000000000011561 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bop_aes.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bop_ae0000644000175000017500000002572611610313111030777 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_bop_aes.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:57p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:05 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_bop_aes.h $ * * Hydra_Software_Devel/1 7/17/09 7:57p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_BOP_AES_H__ #define BCHP_BOP_AES_H__ /*************************************************************************** *BOP_AES - BOP Top Control Registers ***************************************************************************/ #define BCHP_BOP_AES_CTRL 0x00510000 /* AES Control Register */ #define BCHP_BOP_AES_SCRAMBLE_SETUP 0x00510004 /* AES Scramble Setup Register */ #define BCHP_BOP_AES_ENCRYPTION_SETUP 0x00510008 /* AES Encryption Setup Register */ #define BCHP_BOP_AES_STATUS 0x0051000c /* AES Status Register */ #define BCHP_BOP_AES_SCRAMBLE_NONCE0 0x00510010 /* AES Scramble Nonce Register0 */ #define BCHP_BOP_AES_SCRAMBLE_NONCE1 0x00510014 /* AES Scramble Nonce Register1 */ #define BCHP_BOP_AES_INITIAL_VECTOR0 0x00510018 /* AES Initial Vector Register0 */ #define BCHP_BOP_AES_INITIAL_VECTOR1 0x0051001c /* AES Initial Vector Register1 */ #define BCHP_BOP_AES_INITIAL_VECTOR2 0x00510020 /* AES Initial Vector Register2 */ #define BCHP_BOP_AES_INITIAL_VECTOR3 0x00510024 /* AES Initial Vector Register3 */ #define BCHP_BOP_AES_INITIAL_COUNTER0 0x00510028 /* AES Initial Counter Register0 */ #define BCHP_BOP_AES_INITIAL_COUNTER1 0x0051002c /* AES Initial Counter Register1 */ #define BCHP_BOP_AES_INITIAL_COUNTER2 0x00510030 /* AES Initial Counter Register2 */ #define BCHP_BOP_AES_INITIAL_COUNTER3 0x00510034 /* AES Initial Counter Register3 */ /*************************************************************************** *CTRL - AES Control Register ***************************************************************************/ /* BOP_AES :: CTRL :: reserved0 [31:11] */ #define BCHP_BOP_AES_CTRL_reserved0_MASK 0xfffff800 #define BCHP_BOP_AES_CTRL_reserved0_SHIFT 11 /* BOP_AES :: CTRL :: SCRAMBLE_MODE [10:10] */ #define BCHP_BOP_AES_CTRL_SCRAMBLE_MODE_MASK 0x00000400 #define BCHP_BOP_AES_CTRL_SCRAMBLE_MODE_SHIFT 10 /* BOP_AES :: CTRL :: ENCRYPTION_MODE [09:08] */ #define BCHP_BOP_AES_CTRL_ENCRYPTION_MODE_MASK 0x00000300 #define BCHP_BOP_AES_CTRL_ENCRYPTION_MODE_SHIFT 8 /* BOP_AES :: CTRL :: reserved1 [07:05] */ #define BCHP_BOP_AES_CTRL_reserved1_MASK 0x000000e0 #define BCHP_BOP_AES_CTRL_reserved1_SHIFT 5 /* BOP_AES :: CTRL :: SWAP [04:04] */ #define BCHP_BOP_AES_CTRL_SWAP_MASK 0x00000010 #define BCHP_BOP_AES_CTRL_SWAP_SHIFT 4 /* BOP_AES :: CTRL :: reserved2 [03:01] */ #define BCHP_BOP_AES_CTRL_reserved2_MASK 0x0000000e #define BCHP_BOP_AES_CTRL_reserved2_SHIFT 1 /* BOP_AES :: CTRL :: START_ENCRYPTION_SCRAMBLE [00:00] */ #define BCHP_BOP_AES_CTRL_START_ENCRYPTION_SCRAMBLE_MASK 0x00000001 #define BCHP_BOP_AES_CTRL_START_ENCRYPTION_SCRAMBLE_SHIFT 0 /*************************************************************************** *SCRAMBLE_SETUP - AES Scramble Setup Register ***************************************************************************/ /* BOP_AES :: SCRAMBLE_SETUP :: Length [31:16] */ #define BCHP_BOP_AES_SCRAMBLE_SETUP_Length_MASK 0xffff0000 #define BCHP_BOP_AES_SCRAMBLE_SETUP_Length_SHIFT 16 /* BOP_AES :: SCRAMBLE_SETUP :: OFFSET [15:00] */ #define BCHP_BOP_AES_SCRAMBLE_SETUP_OFFSET_MASK 0x0000ffff #define BCHP_BOP_AES_SCRAMBLE_SETUP_OFFSET_SHIFT 0 /*************************************************************************** *ENCRYPTION_SETUP - AES Encryption Setup Register ***************************************************************************/ /* BOP_AES :: ENCRYPTION_SETUP :: Length [31:16] */ #define BCHP_BOP_AES_ENCRYPTION_SETUP_Length_MASK 0xffff0000 #define BCHP_BOP_AES_ENCRYPTION_SETUP_Length_SHIFT 16 /* BOP_AES :: ENCRYPTION_SETUP :: OFFSET [15:00] */ #define BCHP_BOP_AES_ENCRYPTION_SETUP_OFFSET_MASK 0x0000ffff #define BCHP_BOP_AES_ENCRYPTION_SETUP_OFFSET_SHIFT 0 /*************************************************************************** *STATUS - AES Status Register ***************************************************************************/ /* BOP_AES :: STATUS :: reserved0 [31:04] */ #define BCHP_BOP_AES_STATUS_reserved0_MASK 0xfffffff0 #define BCHP_BOP_AES_STATUS_reserved0_SHIFT 4 /* BOP_AES :: STATUS :: SCRAMBLE_KEY_NUMBER_IN_USE [03:02] */ #define BCHP_BOP_AES_STATUS_SCRAMBLE_KEY_NUMBER_IN_USE_MASK 0x0000000c #define BCHP_BOP_AES_STATUS_SCRAMBLE_KEY_NUMBER_IN_USE_SHIFT 2 /* BOP_AES :: STATUS :: ENCRYPTION_KEY_NUMBER_IN_USE [01:00] */ #define BCHP_BOP_AES_STATUS_ENCRYPTION_KEY_NUMBER_IN_USE_MASK 0x00000003 #define BCHP_BOP_AES_STATUS_ENCRYPTION_KEY_NUMBER_IN_USE_SHIFT 0 /*************************************************************************** *SCRAMBLE_NONCE0 - AES Scramble Nonce Register0 ***************************************************************************/ /* BOP_AES :: SCRAMBLE_NONCE0 :: SCRAMBLE_NONCE [31:00] */ #define BCHP_BOP_AES_SCRAMBLE_NONCE0_SCRAMBLE_NONCE_MASK 0xffffffff #define BCHP_BOP_AES_SCRAMBLE_NONCE0_SCRAMBLE_NONCE_SHIFT 0 /*************************************************************************** *SCRAMBLE_NONCE1 - AES Scramble Nonce Register1 ***************************************************************************/ /* BOP_AES :: SCRAMBLE_NONCE1 :: SCRAMBLE_NONCE [31:00] */ #define BCHP_BOP_AES_SCRAMBLE_NONCE1_SCRAMBLE_NONCE_MASK 0xffffffff #define BCHP_BOP_AES_SCRAMBLE_NONCE1_SCRAMBLE_NONCE_SHIFT 0 /*************************************************************************** *INITIAL_VECTOR0 - AES Initial Vector Register0 ***************************************************************************/ /* BOP_AES :: INITIAL_VECTOR0 :: INITIAL_VECTOR [31:00] */ #define BCHP_BOP_AES_INITIAL_VECTOR0_INITIAL_VECTOR_MASK 0xffffffff #define BCHP_BOP_AES_INITIAL_VECTOR0_INITIAL_VECTOR_SHIFT 0 /*************************************************************************** *INITIAL_VECTOR1 - AES Initial Vector Register1 ***************************************************************************/ /* BOP_AES :: INITIAL_VECTOR1 :: INITIAL_VECTOR [31:00] */ #define BCHP_BOP_AES_INITIAL_VECTOR1_INITIAL_VECTOR_MASK 0xffffffff #define BCHP_BOP_AES_INITIAL_VECTOR1_INITIAL_VECTOR_SHIFT 0 /*************************************************************************** *INITIAL_VECTOR2 - AES Initial Vector Register2 ***************************************************************************/ /* BOP_AES :: INITIAL_VECTOR2 :: INITIAL_VECTOR [31:00] */ #define BCHP_BOP_AES_INITIAL_VECTOR2_INITIAL_VECTOR_MASK 0xffffffff #define BCHP_BOP_AES_INITIAL_VECTOR2_INITIAL_VECTOR_SHIFT 0 /*************************************************************************** *INITIAL_VECTOR3 - AES Initial Vector Register3 ***************************************************************************/ /* BOP_AES :: INITIAL_VECTOR3 :: INITIAL_VECTOR [31:00] */ #define BCHP_BOP_AES_INITIAL_VECTOR3_INITIAL_VECTOR_MASK 0xffffffff #define BCHP_BOP_AES_INITIAL_VECTOR3_INITIAL_VECTOR_SHIFT 0 /*************************************************************************** *INITIAL_COUNTER0 - AES Initial Counter Register0 ***************************************************************************/ /* BOP_AES :: INITIAL_COUNTER0 :: INITIAL_COUNTER [31:00] */ #define BCHP_BOP_AES_INITIAL_COUNTER0_INITIAL_COUNTER_MASK 0xffffffff #define BCHP_BOP_AES_INITIAL_COUNTER0_INITIAL_COUNTER_SHIFT 0 /*************************************************************************** *INITIAL_COUNTER1 - AES Initial Counter Register1 ***************************************************************************/ /* BOP_AES :: INITIAL_COUNTER1 :: INITIAL_COUNTER [31:00] */ #define BCHP_BOP_AES_INITIAL_COUNTER1_INITIAL_COUNTER_MASK 0xffffffff #define BCHP_BOP_AES_INITIAL_COUNTER1_INITIAL_COUNTER_SHIFT 0 /*************************************************************************** *INITIAL_COUNTER2 - AES Initial Counter Register2 ***************************************************************************/ /* BOP_AES :: INITIAL_COUNTER2 :: INITIAL_COUNTER [31:00] */ #define BCHP_BOP_AES_INITIAL_COUNTER2_INITIAL_COUNTER_MASK 0xffffffff #define BCHP_BOP_AES_INITIAL_COUNTER2_INITIAL_COUNTER_SHIFT 0 /*************************************************************************** *INITIAL_COUNTER3 - AES Initial Counter Register3 ***************************************************************************/ /* BOP_AES :: INITIAL_COUNTER3 :: INITIAL_COUNTER [31:00] */ #define BCHP_BOP_AES_INITIAL_COUNTER3_INITIAL_COUNTER_MASK 0xffffffff #define BCHP_BOP_AES_INITIAL_COUNTER3_INITIAL_COUNTER_SHIFT 0 #endif /* #ifndef BCHP_BOP_AES_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016300000000000011565 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_sarch_regs.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_ar0000644000175000017500000003217611610313111031023 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_arb_sarch_regs.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:15p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:07 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_sarch_regs.h $ * * Hydra_Software_Devel/1 7/17/09 8:15p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_ARB_SARCH_REGS_H__ #define BCHP_PRI_ARB_SARCH_REGS_H__ /*************************************************************************** *PRI_ARB_SARCH_REGS - PRIMARY_ARB secure address range checker registers ***************************************************************************/ /*************************************************************************** *CNTRL_REG%i - Address Range Checker (SARCH0..7) control register ***************************************************************************/ #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_ARRAY_BASE 0x00461400 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_ARRAY_START 0 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_ARRAY_END 7 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *CNTRL_REG%i - Address Range Checker (SARCH0..7) control register ***************************************************************************/ /* PRI_ARB_SARCH_REGS :: CNTRL_REGi :: reserved0 [31:06] */ #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_reserved0_MASK 0xffffffc0 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_reserved0_SHIFT 6 /* PRI_ARB_SARCH_REGS :: CNTRL_REGi :: READ_ABORT [05:05] */ #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_ABORT_MASK 0x00000020 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_ABORT_SHIFT 5 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_ABORT_DISABLED 0 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_ABORT_ENABLED 1 /* PRI_ARB_SARCH_REGS :: CNTRL_REGi :: WRITE_ABORT [04:04] */ #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_ABORT_MASK 0x00000010 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_ABORT_SHIFT 4 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_ABORT_DISABLED 0 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_ABORT_ENABLED 1 /* PRI_ARB_SARCH_REGS :: CNTRL_REGi :: WRITE_CHECK [03:03] */ #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_CHECK_MASK 0x00000008 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_CHECK_SHIFT 3 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_CHECK_DISABLED 0 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_WRITE_CHECK_ENABLED 1 /* PRI_ARB_SARCH_REGS :: CNTRL_REGi :: READ_CHECK [02:02] */ #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_CHECK_MASK 0x00000004 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_CHECK_SHIFT 2 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_CHECK_DISABLED 0 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_READ_CHECK_ENABLED 1 /* PRI_ARB_SARCH_REGS :: CNTRL_REGi :: MODE [01:00] */ #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_MODE_MASK 0x00000003 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_MODE_SHIFT 0 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_MODE_NON_EXCLUSIVE 0 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_MODE_EXCLUSIVE 1 #define BCHP_PRI_ARB_SARCH_REGS_CNTRL_REGi_MODE_ULTRA_EXCLUSIVE 2 /*************************************************************************** *ADRS_RANGE_LOW%i - Address Range Checker (SARCH0..7) memory range lower address register ***************************************************************************/ #define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_LOWi_ARRAY_BASE 0x00461420 #define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_LOWi_ARRAY_START 0 #define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_LOWi_ARRAY_END 7 #define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_LOWi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *ADRS_RANGE_LOW%i - Address Range Checker (SARCH0..7) memory range lower address register ***************************************************************************/ /* PRI_ARB_SARCH_REGS :: ADRS_RANGE_LOWi :: ADDRESS [31:00] */ #define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_LOWi_ADDRESS_MASK 0xffffffff #define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_LOWi_ADDRESS_SHIFT 0 /*************************************************************************** *ADRS_RANGE_HIGH%i - Address Range Checker (SARCH0..7) memory range upper address register ***************************************************************************/ #define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_BASE 0x00461440 #define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_START 0 #define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_END 7 #define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *ADRS_RANGE_HIGH%i - Address Range Checker (SARCH0..7) memory range upper address register ***************************************************************************/ /* PRI_ARB_SARCH_REGS :: ADRS_RANGE_HIGHi :: ADDRESS [31:00] */ #define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_HIGHi_ADDRESS_MASK 0xffffffff #define BCHP_PRI_ARB_SARCH_REGS_ADRS_RANGE_HIGHi_ADDRESS_SHIFT 0 /*************************************************************************** *READ_RIGHTS_0_%i - Address Range Checker (SARCH0..7) read access rights for clients #0 through #19. ***************************************************************************/ #define BCHP_PRI_ARB_SARCH_REGS_READ_RIGHTS_0_i_ARRAY_BASE 0x00461460 #define BCHP_PRI_ARB_SARCH_REGS_READ_RIGHTS_0_i_ARRAY_START 0 #define BCHP_PRI_ARB_SARCH_REGS_READ_RIGHTS_0_i_ARRAY_END 7 #define BCHP_PRI_ARB_SARCH_REGS_READ_RIGHTS_0_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *READ_RIGHTS_0_%i - Address Range Checker (SARCH0..7) read access rights for clients #0 through #19. ***************************************************************************/ /* PRI_ARB_SARCH_REGS :: READ_RIGHTS_0_i :: ACCESS_RIGHT [31:00] */ #define BCHP_PRI_ARB_SARCH_REGS_READ_RIGHTS_0_i_ACCESS_RIGHT_MASK 0xffffffff #define BCHP_PRI_ARB_SARCH_REGS_READ_RIGHTS_0_i_ACCESS_RIGHT_SHIFT 0 /*************************************************************************** *WRITE_RIGHTS_0_%i - Address Range Checker (SARCH0..7) write access rights for clients #0 through #19. ***************************************************************************/ #define BCHP_PRI_ARB_SARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_BASE 0x004614c0 #define BCHP_PRI_ARB_SARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_START 0 #define BCHP_PRI_ARB_SARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_END 7 #define BCHP_PRI_ARB_SARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *WRITE_RIGHTS_0_%i - Address Range Checker (SARCH0..7) write access rights for clients #0 through #19. ***************************************************************************/ /* PRI_ARB_SARCH_REGS :: WRITE_RIGHTS_0_i :: ACCESS_RIGHT [31:00] */ #define BCHP_PRI_ARB_SARCH_REGS_WRITE_RIGHTS_0_i_ACCESS_RIGHT_MASK 0xffffffff #define BCHP_PRI_ARB_SARCH_REGS_WRITE_RIGHTS_0_i_ACCESS_RIGHT_SHIFT 0 /*************************************************************************** *VIOL_ADDR%i - Address Range Checker (SARCH0..7) violating command address. ***************************************************************************/ #define BCHP_PRI_ARB_SARCH_REGS_VIOL_ADDRi_ARRAY_BASE 0x00461540 #define BCHP_PRI_ARB_SARCH_REGS_VIOL_ADDRi_ARRAY_START 0 #define BCHP_PRI_ARB_SARCH_REGS_VIOL_ADDRi_ARRAY_END 7 #define BCHP_PRI_ARB_SARCH_REGS_VIOL_ADDRi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *VIOL_ADDR%i - Address Range Checker (SARCH0..7) violating command address. ***************************************************************************/ /* PRI_ARB_SARCH_REGS :: VIOL_ADDRi :: ADDRESS [31:00] */ #define BCHP_PRI_ARB_SARCH_REGS_VIOL_ADDRi_ADDRESS_MASK 0xffffffff #define BCHP_PRI_ARB_SARCH_REGS_VIOL_ADDRi_ADDRESS_SHIFT 0 /*************************************************************************** *VIOL_INFO%i - Address Range Checker (SARCH0..7) violating command information. ***************************************************************************/ #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_ARRAY_BASE 0x00461560 #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_ARRAY_START 0 #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_ARRAY_END 7 #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *VIOL_INFO%i - Address Range Checker (SARCH0..7) violating command information. ***************************************************************************/ /* PRI_ARB_SARCH_REGS :: VIOL_INFOi :: CLIENTID [31:24] */ #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_CLIENTID_MASK 0xff000000 #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_CLIENTID_SHIFT 24 /* PRI_ARB_SARCH_REGS :: VIOL_INFOi :: reserved0 [23:22] */ #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_reserved0_MASK 0x00c00000 #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_reserved0_SHIFT 22 /* PRI_ARB_SARCH_REGS :: VIOL_INFOi :: LENGTH [21:12] */ #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_LENGTH_MASK 0x003ff000 #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_LENGTH_SHIFT 12 /* PRI_ARB_SARCH_REGS :: VIOL_INFOi :: MODE [11:09] */ #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_MODE_MASK 0x00000e00 #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_MODE_SHIFT 9 /* PRI_ARB_SARCH_REGS :: VIOL_INFOi :: WRITE [08:08] */ #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_WRITE_MASK 0x00000100 #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_WRITE_SHIFT 8 /* PRI_ARB_SARCH_REGS :: VIOL_INFOi :: reserved1 [07:01] */ #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_reserved1_MASK 0x000000fe #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_reserved1_SHIFT 1 /* PRI_ARB_SARCH_REGS :: VIOL_INFOi :: STATUS [00:00] */ #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_STATUS_MASK 0x00000001 #define BCHP_PRI_ARB_SARCH_REGS_VIOL_INFOi_STATUS_SHIFT 0 /*************************************************************************** *STATUS_CLEAR%i - Address Range Checker (SARCH0..7) violating command status release. ***************************************************************************/ #define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_ARRAY_BASE 0x00461580 #define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_ARRAY_START 0 #define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_ARRAY_END 7 #define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *STATUS_CLEAR%i - Address Range Checker (SARCH0..7) violating command status release. ***************************************************************************/ /* PRI_ARB_SARCH_REGS :: STATUS_CLEARi :: reserved0 [31:01] */ #define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_reserved0_MASK 0xfffffffe #define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_reserved0_SHIFT 1 /* PRI_ARB_SARCH_REGS :: STATUS_CLEARi :: CLEAR [00:00] */ #define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_CLEAR_MASK 0x00000001 #define BCHP_PRI_ARB_SARCH_REGS_STATUS_CLEARi_CLEAR_SHIFT 0 #endif /* #ifndef BCHP_PRI_ARB_SARCH_REGS_H__ */ /* End of File */ crystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp.h0000644000175000017500000000000011610313111027672 0ustar andresandres././@LongLink0000000000000000000000000000016200000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_wrch_regs.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_ar0000644000175000017500000000622311610313111031015 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_arb_wrch_regs.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:15p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:44 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_wrch_regs.h $ * * Hydra_Software_Devel/1 7/17/09 8:15p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_ARB_WRCH_REGS_H__ #define BCHP_PRI_ARB_WRCH_REGS_H__ /*************************************************************************** *PRI_ARB_WRCH_REGS - PRIMARY_ARB secure wrch control registers ***************************************************************************/ #define BCHP_PRI_ARB_WRCH_REGS_RESERVED0 0x00461000 /* Reserved */ #define BCHP_PRI_ARB_WRCH_REGS_RESERVED1 0x004610fc /* Reserved */ /*************************************************************************** *RESERVED0 - Reserved ***************************************************************************/ /* PRI_ARB_WRCH_REGS :: RESERVED0 :: RESERVED [31:00] */ #define BCHP_PRI_ARB_WRCH_REGS_RESERVED0_RESERVED_MASK 0xffffffff #define BCHP_PRI_ARB_WRCH_REGS_RESERVED0_RESERVED_SHIFT 0 /*************************************************************************** *RESERVED1 - Reserved ***************************************************************************/ /* PRI_ARB_WRCH_REGS :: RESERVED1 :: RESERVED [31:00] */ #define BCHP_PRI_ARB_WRCH_REGS_RESERVED1_RESERVED_MASK 0xffffffff #define BCHP_PRI_ARB_WRCH_REGS_RESERVED1_RESERVED_SHIFT 0 #endif /* #ifndef BCHP_PRI_ARB_WRCH_REGS_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000014700000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_clk_gr.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_clk_gr0000644000175000017500000001145011610313111031000 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_clk_gr.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:58p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:15 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_clk_gr.h $ * * Hydra_Software_Devel/1 7/17/09 7:58p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_CLK_GR_H__ #define BCHP_CLK_GR_H__ /*************************************************************************** *CLK_GR - Registers for the clock_gen block's GR bridge ***************************************************************************/ #define BCHP_CLK_GR_REVISION 0x00072000 /* GR Bridge Revision */ #define BCHP_CLK_GR_CTRL 0x00072004 /* GR Bridge Control Register */ #define BCHP_CLK_GR_SW_RESET_0 0x00072008 /* GR Bridge Software Reset 0 Register */ #define BCHP_CLK_GR_SW_RESET_1 0x0007200c /* GR Bridge Software Reset 1 Register */ /*************************************************************************** *REVISION - GR Bridge Revision ***************************************************************************/ /* CLK_GR :: REVISION :: reserved0 [31:16] */ #define BCHP_CLK_GR_REVISION_reserved0_MASK 0xffff0000 #define BCHP_CLK_GR_REVISION_reserved0_SHIFT 16 /* CLK_GR :: REVISION :: MAJOR [15:08] */ #define BCHP_CLK_GR_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_CLK_GR_REVISION_MAJOR_SHIFT 8 /* CLK_GR :: REVISION :: MINOR [07:00] */ #define BCHP_CLK_GR_REVISION_MINOR_MASK 0x000000ff #define BCHP_CLK_GR_REVISION_MINOR_SHIFT 0 /*************************************************************************** *CTRL - GR Bridge Control Register ***************************************************************************/ /* CLK_GR :: CTRL :: reserved0 [31:01] */ #define BCHP_CLK_GR_CTRL_reserved0_MASK 0xfffffffe #define BCHP_CLK_GR_CTRL_reserved0_SHIFT 1 /* CLK_GR :: CTRL :: gisb_error_intr [00:00] */ #define BCHP_CLK_GR_CTRL_gisb_error_intr_MASK 0x00000001 #define BCHP_CLK_GR_CTRL_gisb_error_intr_SHIFT 0 #define BCHP_CLK_GR_CTRL_gisb_error_intr_INTR_DISABLE 0 #define BCHP_CLK_GR_CTRL_gisb_error_intr_INTR_ENABLE 1 /*************************************************************************** *SW_RESET_0 - GR Bridge Software Reset 0 Register ***************************************************************************/ /* CLK_GR :: SW_RESET_0 :: reserved0 [31:00] */ #define BCHP_CLK_GR_SW_RESET_0_reserved0_MASK 0xffffffff #define BCHP_CLK_GR_SW_RESET_0_reserved0_SHIFT 0 /*************************************************************************** *SW_RESET_1 - GR Bridge Software Reset 1 Register ***************************************************************************/ /* CLK_GR :: SW_RESET_1 :: reserved0 [31:00] */ #define BCHP_CLK_GR_SW_RESET_1_reserved0_MASK 0xffffffff #define BCHP_CLK_GR_SW_RESET_1_reserved0_SHIFT 0 #endif /* #ifndef BCHP_CLK_GR_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015100000000000011562 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_rave.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_ra0000644000175000017500001352550011610313111031046 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_xpt_rave.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:26p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:27 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_rave.h $ * * Hydra_Software_Devel/1 7/17/09 8:26p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_XPT_RAVE_H__ #define BCHP_XPT_RAVE_H__ /*************************************************************************** *XPT_RAVE - XPT RAV Control Registers ***************************************************************************/ #define BCHP_XPT_RAVE_CX0_AV_CDB_WRITE_PTR 0x00210000 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX0_AV_CDB_READ_PTR 0x00210004 /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX0_AV_CDB_BASE_PTR 0x00210008 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX0_AV_CDB_END_PTR 0x0021000c /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX0_AV_CDB_VALID_PTR 0x00210010 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX0_AV_CDB_WRAPAROUND_PTR 0x00210014 /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL 0x00210018 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH 0x0021001c /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS 0x00210020 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX0_AV_ITB_WRITE_PTR 0x00210024 /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX0_AV_ITB_READ_PTR 0x00210028 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX0_AV_ITB_BASE_PTR 0x0021002c /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX0_AV_ITB_END_PTR 0x00210030 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX0_AV_ITB_VALID_PTR 0x00210034 /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX0_AV_ITB_WRAPAROUND_PTR 0x00210038 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL 0x0021003c /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH 0x00210040 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG 0x00210044 /* Context 0 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB 0x00210048 /* Context 0 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD 0x0021004c /* Context 0 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF 0x00210050 /* Context 0 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH 0x00210054 /* Context 0 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1 0x00210058 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2 0x0021005c /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3 0x00210060 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES 0x00210064 /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL 0x00210068 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL 0x0021006c /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL 0x00210070 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL 0x00210074 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL 0x00210078 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL 0x0021007c /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL 0x00210080 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL 0x00210084 /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL 0x00210088 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL 0x0021008c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode 0x00210090 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID 0x00210094 /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX0_REC_CTRL1 0x00210098 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX0_REC_INIT_TS 0x0021009c /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX0_REC_TS_CTRL 0x002100a0 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG 0x002100a4 /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4 0x002100a8 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX0_PIC_CTR 0x002100ac /* Picture Counter register */ #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE 0x002100b0 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX0_REC_TIMER 0x002100b4 /* Record Timer Register */ #define BCHP_XPT_RAVE_CX0_REC_STATE0 0x002100b8 /* Record State Register */ #define BCHP_XPT_RAVE_CX0_REC_STATE1 0x002100bc /* Record State Register */ #define BCHP_XPT_RAVE_CX0_REC_STATE2 0x002100c0 /* Record State Register */ #define BCHP_XPT_RAVE_CX0_REC_STATE2b 0x002100c4 /* Record State Register */ #define BCHP_XPT_RAVE_CX0_REC_STATE3 0x002100c8 /* Record State Register */ #define BCHP_XPT_RAVE_CX0_REC_COUNT 0x002100cc /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL 0x002100d0 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX0_REC_RESERVE_STATE1 0x002100d4 /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX0_RAVE_Reg_0 0x002100d8 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX0_RAVE_Reg_1 0x002100dc /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX0_RAVE_Reg_2 0x002100e0 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX0_RAVE_Reg_3 0x002100e4 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX1_AV_CDB_WRITE_PTR 0x002100e8 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX1_AV_CDB_READ_PTR 0x002100ec /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX1_AV_CDB_BASE_PTR 0x002100f0 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX1_AV_CDB_END_PTR 0x002100f4 /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX1_AV_CDB_VALID_PTR 0x002100f8 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX1_AV_CDB_WRAPAROUND_PTR 0x002100fc /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL 0x00210100 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH 0x00210104 /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS 0x00210108 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX1_AV_ITB_WRITE_PTR 0x0021010c /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX1_AV_ITB_READ_PTR 0x00210110 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX1_AV_ITB_BASE_PTR 0x00210114 /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX1_AV_ITB_END_PTR 0x00210118 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX1_AV_ITB_VALID_PTR 0x0021011c /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX1_AV_ITB_WRAPAROUND_PTR 0x00210120 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL 0x00210124 /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH 0x00210128 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG 0x0021012c /* Context 1 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB 0x00210130 /* Context 1 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD 0x00210134 /* Context 1 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF 0x00210138 /* Context 1 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH 0x0021013c /* Context 1 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1 0x00210140 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2 0x00210144 /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3 0x00210148 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES 0x0021014c /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL 0x00210150 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL 0x00210154 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL 0x00210158 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL 0x0021015c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL 0x00210160 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL 0x00210164 /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL 0x00210168 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL 0x0021016c /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL 0x00210170 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL 0x00210174 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE 0x00210178 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID 0x0021017c /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX1_REC_CTRL1 0x00210180 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX1_REC_INIT_TS 0x00210184 /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX1_REC_TS_CTRL 0x00210188 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG 0x0021018c /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4 0x00210190 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX1_PIC_CTR 0x00210194 /* Picture Counter register */ #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE 0x00210198 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX1_REC_TIMER 0x0021019c /* Record Timer Register */ #define BCHP_XPT_RAVE_CX1_REC_STATE0 0x002101a0 /* Record State Register */ #define BCHP_XPT_RAVE_CX1_REC_STATE1 0x002101a4 /* Record State Register */ #define BCHP_XPT_RAVE_CX1_REC_STATE2 0x002101a8 /* Record State Register */ #define BCHP_XPT_RAVE_CX1_REC_STATE2b 0x002101ac /* Record State Register */ #define BCHP_XPT_RAVE_CX1_REC_STATE3 0x002101b0 /* Record State Register */ #define BCHP_XPT_RAVE_CX1_REC_COUNT 0x002101b4 /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL 0x002101b8 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX1_REC_RESERVE_STATE1 0x002101bc /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX1_RAVE_Reg_0 0x002101c0 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX1_RAVE_Reg_1 0x002101c4 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX1_RAVE_Reg_2 0x002101c8 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX1_RAVE_Reg_3 0x002101cc /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX2_AV_CDB_WRITE_PTR 0x002101d0 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX2_AV_CDB_READ_PTR 0x002101d4 /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX2_AV_CDB_BASE_PTR 0x002101d8 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX2_AV_CDB_END_PTR 0x002101dc /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX2_AV_CDB_VALID_PTR 0x002101e0 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX2_AV_CDB_WRAPAROUND_PTR 0x002101e4 /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL 0x002101e8 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH 0x002101ec /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS 0x002101f0 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX2_AV_ITB_WRITE_PTR 0x002101f4 /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX2_AV_ITB_READ_PTR 0x002101f8 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX2_AV_ITB_BASE_PTR 0x002101fc /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX2_AV_ITB_END_PTR 0x00210200 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX2_AV_ITB_VALID_PTR 0x00210204 /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX2_AV_ITB_WRAPAROUND_PTR 0x00210208 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL 0x0021020c /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH 0x00210210 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG 0x00210214 /* Context 2 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB 0x00210218 /* Context 2 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD 0x0021021c /* Context 2 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF 0x00210220 /* Context 2 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH 0x00210224 /* Context 2 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1 0x00210228 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2 0x0021022c /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3 0x00210230 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES 0x00210234 /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL 0x00210238 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL 0x0021023c /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL 0x00210240 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL 0x00210244 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL 0x00210248 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL 0x0021024c /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL 0x00210250 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL 0x00210254 /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL 0x00210258 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL 0x0021025c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode 0x00210260 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID 0x00210264 /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX2_REC_CTRL1 0x00210268 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX2_REC_INIT_TS 0x0021026c /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX2_REC_TS_CTRL 0x00210270 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG 0x00210274 /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4 0x00210278 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX2_PIC_CTR 0x0021027c /* Picture Counter register */ #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE 0x00210280 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX2_REC_TIMER 0x00210284 /* Record Timer Register */ #define BCHP_XPT_RAVE_CX2_REC_STATE0 0x00210288 /* Record State Register */ #define BCHP_XPT_RAVE_CX2_REC_STATE1 0x0021028c /* Record State Register */ #define BCHP_XPT_RAVE_CX2_REC_STATE2 0x00210290 /* Record State Register */ #define BCHP_XPT_RAVE_CX2_REC_STATE2b 0x00210294 /* Record State Register */ #define BCHP_XPT_RAVE_CX2_REC_STATE3 0x00210298 /* Record State Register */ #define BCHP_XPT_RAVE_CX2_REC_COUNT 0x0021029c /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL 0x002102a0 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX2_REC_RESERVE_STATE1 0x002102a4 /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX2_RAVE_Reg_0 0x002102a8 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX2_RAVE_Reg_1 0x002102ac /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX2_RAVE_Reg_2 0x002102b0 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX2_RAVE_Reg_3 0x002102b4 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX3_AV_CDB_WRITE_PTR 0x002102b8 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX3_AV_CDB_READ_PTR 0x002102bc /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX3_AV_CDB_BASE_PTR 0x002102c0 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX3_AV_CDB_END_PTR 0x002102c4 /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX3_AV_CDB_VALID_PTR 0x002102c8 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX3_AV_CDB_WRAPAROUND_PTR 0x002102cc /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL 0x002102d0 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH 0x002102d4 /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS 0x002102d8 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX3_AV_ITB_WRITE_PTR 0x002102dc /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX3_AV_ITB_READ_PTR 0x002102e0 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX3_AV_ITB_BASE_PTR 0x002102e4 /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX3_AV_ITB_END_PTR 0x002102e8 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX3_AV_ITB_VALID_PTR 0x002102ec /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX3_AV_ITB_WRAPAROUND_PTR 0x002102f0 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL 0x002102f4 /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH 0x002102f8 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG 0x002102fc /* Context 3 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB 0x00210300 /* Context 3 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD 0x00210304 /* Context 3 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF 0x00210308 /* Context 3 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH 0x0021030c /* Context 3 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1 0x00210310 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2 0x00210314 /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3 0x00210318 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES 0x0021031c /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL 0x00210320 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL 0x00210324 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL 0x00210328 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL 0x0021032c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL 0x00210330 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL 0x00210334 /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL 0x00210338 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL 0x0021033c /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL 0x00210340 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL 0x00210344 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode 0x00210348 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID 0x0021034c /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX3_REC_CTRL1 0x00210350 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX3_REC_INIT_TS 0x00210354 /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX3_REC_TS_CTRL 0x00210358 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG 0x0021035c /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4 0x00210360 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX3_PIC_CTR 0x00210364 /* Picture Counter register */ #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE 0x00210368 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX3_REC_TIMER 0x0021036c /* Record Timer Register */ #define BCHP_XPT_RAVE_CX3_REC_STATE0 0x00210370 /* Record State Register */ #define BCHP_XPT_RAVE_CX3_REC_STATE1 0x00210374 /* Record State Register */ #define BCHP_XPT_RAVE_CX3_REC_STATE2 0x00210378 /* Record State Register */ #define BCHP_XPT_RAVE_CX3_REC_STATE2b 0x0021037c /* Record State Register */ #define BCHP_XPT_RAVE_CX3_REC_STATE3 0x00210380 /* Record State Register */ #define BCHP_XPT_RAVE_CX3_REC_COUNT 0x00210384 /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL 0x00210388 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX3_REC_RESERVE_STATE1 0x0021038c /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX3_RAVE_Reg_0 0x00210390 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX3_RAVE_Reg_1 0x00210394 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX3_RAVE_Reg_2 0x00210398 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX3_RAVE_Reg_3 0x0021039c /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX4_AV_CDB_WRITE_PTR 0x002103a0 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX4_AV_CDB_READ_PTR 0x002103a4 /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX4_AV_CDB_BASE_PTR 0x002103a8 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX4_AV_CDB_END_PTR 0x002103ac /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX4_AV_CDB_VALID_PTR 0x002103b0 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX4_AV_CDB_WRAPAROUND_PTR 0x002103b4 /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL 0x002103b8 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH 0x002103bc /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS 0x002103c0 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX4_AV_ITB_WRITE_PTR 0x002103c4 /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX4_AV_ITB_READ_PTR 0x002103c8 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX4_AV_ITB_BASE_PTR 0x002103cc /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX4_AV_ITB_END_PTR 0x002103d0 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX4_AV_ITB_VALID_PTR 0x002103d4 /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX4_AV_ITB_WRAPAROUND_PTR 0x002103d8 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL 0x002103dc /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH 0x002103e0 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG 0x002103e4 /* Context 4 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB 0x002103e8 /* Context 4 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD 0x002103ec /* Context 4 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF 0x002103f0 /* Context 4 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH 0x002103f4 /* Context 4 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1 0x002103f8 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2 0x002103fc /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3 0x00210400 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES 0x00210404 /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL 0x00210408 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL 0x0021040c /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL 0x00210410 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL 0x00210414 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL 0x00210418 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL 0x0021041c /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL 0x00210420 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL 0x00210424 /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL 0x00210428 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL 0x0021042c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode 0x00210430 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID 0x00210434 /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX4_REC_CTRL1 0x00210438 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX4_REC_INIT_TS 0x0021043c /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX4_REC_TS_CTRL 0x00210440 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG 0x00210444 /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4 0x00210448 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX4_PIC_CTR 0x0021044c /* Picture Counter register */ #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE 0x00210450 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX4_REC_TIMER 0x00210454 /* Record Timer Register */ #define BCHP_XPT_RAVE_CX4_REC_STATE0 0x00210458 /* Record State Register */ #define BCHP_XPT_RAVE_CX4_REC_STATE1 0x0021045c /* Record State Register */ #define BCHP_XPT_RAVE_CX4_REC_STATE2 0x00210460 /* Record State Register */ #define BCHP_XPT_RAVE_CX4_REC_STATE2b 0x00210464 /* Record State Register */ #define BCHP_XPT_RAVE_CX4_REC_STATE3 0x00210468 /* Record State Register */ #define BCHP_XPT_RAVE_CX4_REC_COUNT 0x0021046c /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL 0x00210470 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX4_REC_RESERVE_STATE1 0x00210474 /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX4_RAVE_Reg_0 0x00210478 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX4_RAVE_Reg_1 0x0021047c /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX4_RAVE_Reg_2 0x00210480 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX4_RAVE_Reg_3 0x00210484 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX5_AV_CDB_WRITE_PTR 0x00210488 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX5_AV_CDB_READ_PTR 0x0021048c /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX5_AV_CDB_BASE_PTR 0x00210490 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX5_AV_CDB_END_PTR 0x00210494 /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX5_AV_CDB_VALID_PTR 0x00210498 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX5_AV_CDB_WRAPAROUND_PTR 0x0021049c /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL 0x002104a0 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH 0x002104a4 /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS 0x002104a8 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX5_AV_ITB_WRITE_PTR 0x002104ac /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX5_AV_ITB_READ_PTR 0x002104b0 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX5_AV_ITB_BASE_PTR 0x002104b4 /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX5_AV_ITB_END_PTR 0x002104b8 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX5_AV_ITB_VALID_PTR 0x002104bc /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX5_AV_ITB_WRAPAROUND_PTR 0x002104c0 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL 0x002104c4 /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH 0x002104c8 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG 0x002104cc /* Context 5 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB 0x002104d0 /* Context 5 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD 0x002104d4 /* Context 5 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF 0x002104d8 /* Context 5 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH 0x002104dc /* Context 5 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1 0x002104e0 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2 0x002104e4 /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3 0x002104e8 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES 0x002104ec /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL 0x002104f0 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL 0x002104f4 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL 0x002104f8 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL 0x002104fc /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL 0x00210500 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL 0x00210504 /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL 0x00210508 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL 0x0021050c /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL 0x00210510 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL 0x00210514 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE 0x00210518 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID 0x0021051c /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX5_REC_CTRL1 0x00210520 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX5_REC_INIT_TS 0x00210524 /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX5_REC_TS_CTRL 0x00210528 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG 0x0021052c /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4 0x00210530 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX5_PIC_CTR 0x00210534 /* Picture Counter register */ #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE 0x00210538 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX5_REC_TIMER 0x0021053c /* Record Timer Register */ #define BCHP_XPT_RAVE_CX5_REC_STATE0 0x00210540 /* Record State Register */ #define BCHP_XPT_RAVE_CX5_REC_STATE1 0x00210544 /* Record State Register */ #define BCHP_XPT_RAVE_CX5_REC_STATE2 0x00210548 /* Record State Register */ #define BCHP_XPT_RAVE_CX5_REC_STATE2b 0x0021054c /* Record State Register */ #define BCHP_XPT_RAVE_CX5_REC_STATE3 0x00210550 /* Record State Register */ #define BCHP_XPT_RAVE_CX5_REC_COUNT 0x00210554 /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL 0x00210558 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX5_REC_RESERVE_STATE1 0x0021055c /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX5_RAVE_Reg_0 0x00210560 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX5_RAVE_Reg_1 0x00210564 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX5_RAVE_Reg_2 0x00210568 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX5_RAVE_Reg_3 0x0021056c /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX6_AV_CDB_WRITE_PTR 0x00210570 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX6_AV_CDB_READ_PTR 0x00210574 /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX6_AV_CDB_BASE_PTR 0x00210578 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX6_AV_CDB_END_PTR 0x0021057c /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX6_AV_CDB_VALID_PTR 0x00210580 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX6_AV_CDB_WRAPAROUND_PTR 0x00210584 /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL 0x00210588 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH 0x0021058c /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS 0x00210590 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX6_AV_ITB_WRITE_PTR 0x00210594 /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX6_AV_ITB_READ_PTR 0x00210598 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX6_AV_ITB_BASE_PTR 0x0021059c /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX6_AV_ITB_END_PTR 0x002105a0 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX6_AV_ITB_VALID_PTR 0x002105a4 /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX6_AV_ITB_WRAPAROUND_PTR 0x002105a8 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL 0x002105ac /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH 0x002105b0 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG 0x002105b4 /* Context 6 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB 0x002105b8 /* Context 6 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD 0x002105bc /* Context 6 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF 0x002105c0 /* Context 6 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH 0x002105c4 /* Context 6 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1 0x002105c8 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2 0x002105cc /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3 0x002105d0 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES 0x002105d4 /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL 0x002105d8 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL 0x002105dc /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL 0x002105e0 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL 0x002105e4 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL 0x002105e8 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL 0x002105ec /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL 0x002105f0 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL 0x002105f4 /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL 0x002105f8 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL 0x002105fc /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode 0x00210600 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID 0x00210604 /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX6_REC_CTRL1 0x00210608 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX6_REC_INIT_TS 0x0021060c /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX6_REC_TS_CTRL 0x00210610 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG 0x00210614 /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4 0x00210618 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX6_PIC_CTR 0x0021061c /* Picture Counter register */ #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE 0x00210620 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX6_REC_TIMER 0x00210624 /* Record Timer Register */ #define BCHP_XPT_RAVE_CX6_REC_STATE0 0x00210628 /* Record State Register */ #define BCHP_XPT_RAVE_CX6_REC_STATE1 0x0021062c /* Record State Register */ #define BCHP_XPT_RAVE_CX6_REC_STATE2 0x00210630 /* Record State Register */ #define BCHP_XPT_RAVE_CX6_REC_STATE2b 0x00210634 /* Record State Register */ #define BCHP_XPT_RAVE_CX6_REC_STATE3 0x00210638 /* Record State Register */ #define BCHP_XPT_RAVE_CX6_REC_COUNT 0x0021063c /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL 0x00210640 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX6_REC_RESERVE_STATE1 0x00210644 /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX6_RAVE_Reg_0 0x00210648 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX6_RAVE_Reg_1 0x0021064c /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX6_RAVE_Reg_2 0x00210650 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX6_RAVE_Reg_3 0x00210654 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX7_AV_CDB_WRITE_PTR 0x00210658 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX7_AV_CDB_READ_PTR 0x0021065c /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX7_AV_CDB_BASE_PTR 0x00210660 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX7_AV_CDB_END_PTR 0x00210664 /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX7_AV_CDB_VALID_PTR 0x00210668 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX7_AV_CDB_WRAPAROUND_PTR 0x0021066c /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL 0x00210670 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH 0x00210674 /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS 0x00210678 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX7_AV_ITB_WRITE_PTR 0x0021067c /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX7_AV_ITB_READ_PTR 0x00210680 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX7_AV_ITB_BASE_PTR 0x00210684 /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX7_AV_ITB_END_PTR 0x00210688 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX7_AV_ITB_VALID_PTR 0x0021068c /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX7_AV_ITB_WRAPAROUND_PTR 0x00210690 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL 0x00210694 /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH 0x00210698 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG 0x0021069c /* Context 7 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB 0x002106a0 /* Context 7 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD 0x002106a4 /* Context 7 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF 0x002106a8 /* Context 7 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH 0x002106ac /* Context 7 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1 0x002106b0 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2 0x002106b4 /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3 0x002106b8 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES 0x002106bc /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL 0x002106c0 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL 0x002106c4 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL 0x002106c8 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL 0x002106cc /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL 0x002106d0 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL 0x002106d4 /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL 0x002106d8 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL 0x002106dc /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL 0x002106e0 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL 0x002106e4 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE 0x002106e8 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID 0x002106ec /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX7_REC_CTRL1 0x002106f0 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX7_REC_INIT_TS 0x002106f4 /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX7_REC_TS_CTRL 0x002106f8 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG 0x002106fc /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4 0x00210700 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX7_PIC_CTR 0x00210704 /* Picture Counter register */ #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE 0x00210708 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX7_REC_TIMER 0x0021070c /* Record Timer Register */ #define BCHP_XPT_RAVE_CX7_REC_STATE0 0x00210710 /* Record State Register */ #define BCHP_XPT_RAVE_CX7_REC_STATE1 0x00210714 /* Record State Register */ #define BCHP_XPT_RAVE_CX7_REC_STATE2 0x00210718 /* Record State Register */ #define BCHP_XPT_RAVE_CX7_REC_STATE2b 0x0021071c /* Record State Register */ #define BCHP_XPT_RAVE_CX7_REC_STATE3 0x00210720 /* Record State Register */ #define BCHP_XPT_RAVE_CX7_REC_COUNT 0x00210724 /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL 0x00210728 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX7_REC_RESERVE_STATE1 0x0021072c /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX7_RAVE_Reg_0 0x00210730 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX7_RAVE_Reg_1 0x00210734 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX7_RAVE_Reg_2 0x00210738 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX7_RAVE_Reg_3 0x0021073c /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX8_AV_CDB_WRITE_PTR 0x00210740 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX8_AV_CDB_READ_PTR 0x00210744 /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX8_AV_CDB_BASE_PTR 0x00210748 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX8_AV_CDB_END_PTR 0x0021074c /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX8_AV_CDB_VALID_PTR 0x00210750 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX8_AV_CDB_WRAPAROUND_PTR 0x00210754 /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL 0x00210758 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH 0x0021075c /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS 0x00210760 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX8_AV_ITB_WRITE_PTR 0x00210764 /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX8_AV_ITB_READ_PTR 0x00210768 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX8_AV_ITB_BASE_PTR 0x0021076c /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX8_AV_ITB_END_PTR 0x00210770 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX8_AV_ITB_VALID_PTR 0x00210774 /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX8_AV_ITB_WRAPAROUND_PTR 0x00210778 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL 0x0021077c /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH 0x00210780 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG 0x00210784 /* Context 8 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB 0x00210788 /* Context 8 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD 0x0021078c /* Context 8 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF 0x00210790 /* Context 8 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH 0x00210794 /* Context 8 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1 0x00210798 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2 0x0021079c /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3 0x002107a0 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES 0x002107a4 /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL 0x002107a8 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL 0x002107ac /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL 0x002107b0 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL 0x002107b4 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL 0x002107b8 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL 0x002107bc /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL 0x002107c0 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL 0x002107c4 /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL 0x002107c8 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL 0x002107cc /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode 0x002107d0 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID 0x002107d4 /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX8_REC_CTRL1 0x002107d8 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX8_REC_INIT_TS 0x002107dc /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX8_REC_TS_CTRL 0x002107e0 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG 0x002107e4 /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4 0x002107e8 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX8_PIC_CTR 0x002107ec /* Picture Counter register */ #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE 0x002107f0 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX8_REC_TIMER 0x002107f4 /* Record Timer Register */ #define BCHP_XPT_RAVE_CX8_REC_STATE0 0x002107f8 /* Record State Register */ #define BCHP_XPT_RAVE_CX8_REC_STATE1 0x002107fc /* Record State Register */ #define BCHP_XPT_RAVE_CX8_REC_STATE2 0x00210800 /* Record State Register */ #define BCHP_XPT_RAVE_CX8_REC_STATE2b 0x00210804 /* Record State Register */ #define BCHP_XPT_RAVE_CX8_REC_STATE3 0x00210808 /* Record State Register */ #define BCHP_XPT_RAVE_CX8_REC_COUNT 0x0021080c /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL 0x00210810 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX8_REC_RESERVE_STATE1 0x00210814 /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX8_RAVE_Reg_0 0x00210818 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX8_RAVE_Reg_1 0x0021081c /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX8_RAVE_Reg_2 0x00210820 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX8_RAVE_Reg_3 0x00210824 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX9_AV_CDB_WRITE_PTR 0x00210828 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX9_AV_CDB_READ_PTR 0x0021082c /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX9_AV_CDB_BASE_PTR 0x00210830 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX9_AV_CDB_END_PTR 0x00210834 /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX9_AV_CDB_VALID_PTR 0x00210838 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX9_AV_CDB_WRAPAROUND_PTR 0x0021083c /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL 0x00210840 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH 0x00210844 /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS 0x00210848 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX9_AV_ITB_WRITE_PTR 0x0021084c /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX9_AV_ITB_READ_PTR 0x00210850 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX9_AV_ITB_BASE_PTR 0x00210854 /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX9_AV_ITB_END_PTR 0x00210858 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX9_AV_ITB_VALID_PTR 0x0021085c /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX9_AV_ITB_WRAPAROUND_PTR 0x00210860 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL 0x00210864 /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH 0x00210868 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG 0x0021086c /* Context 9 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB 0x00210870 /* Context 9 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD 0x00210874 /* Context 9 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF 0x00210878 /* Context 9 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH 0x0021087c /* Context 9 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1 0x00210880 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2 0x00210884 /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3 0x00210888 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES 0x0021088c /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL 0x00210890 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL 0x00210894 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL 0x00210898 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL 0x0021089c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL 0x002108a0 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL 0x002108a4 /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL 0x002108a8 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL 0x002108ac /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL 0x002108b0 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL 0x002108b4 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode 0x002108b8 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID 0x002108bc /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX9_REC_CTRL1 0x002108c0 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX9_REC_INIT_TS 0x002108c4 /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX9_REC_TS_CTRL 0x002108c8 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG 0x002108cc /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4 0x002108d0 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX9_PIC_CTR 0x002108d4 /* Picture Counter register */ #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE 0x002108d8 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX9_REC_TIMER 0x002108dc /* Record Timer Register */ #define BCHP_XPT_RAVE_CX9_REC_STATE0 0x002108e0 /* Record State Register */ #define BCHP_XPT_RAVE_CX9_REC_STATE1 0x002108e4 /* Record State Register */ #define BCHP_XPT_RAVE_CX9_REC_STATE2 0x002108e8 /* Record State Register */ #define BCHP_XPT_RAVE_CX9_REC_STATE2b 0x002108ec /* Record State Register */ #define BCHP_XPT_RAVE_CX9_REC_STATE3 0x002108f0 /* Record State Register */ #define BCHP_XPT_RAVE_CX9_REC_COUNT 0x002108f4 /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL 0x002108f8 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX9_REC_RESERVE_STATE1 0x002108fc /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX9_RAVE_Reg_0 0x00210900 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX9_RAVE_Reg_1 0x00210904 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX9_RAVE_Reg_2 0x00210908 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX9_RAVE_Reg_3 0x0021090c /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX10_AV_CDB_WRITE_PTR 0x00210910 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX10_AV_CDB_READ_PTR 0x00210914 /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX10_AV_CDB_BASE_PTR 0x00210918 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX10_AV_CDB_END_PTR 0x0021091c /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX10_AV_CDB_VALID_PTR 0x00210920 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX10_AV_CDB_WRAPAROUND_PTR 0x00210924 /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL 0x00210928 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH 0x0021092c /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS 0x00210930 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX10_AV_ITB_WRITE_PTR 0x00210934 /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX10_AV_ITB_READ_PTR 0x00210938 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX10_AV_ITB_BASE_PTR 0x0021093c /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX10_AV_ITB_END_PTR 0x00210940 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX10_AV_ITB_VALID_PTR 0x00210944 /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX10_AV_ITB_WRAPAROUND_PTR 0x00210948 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL 0x0021094c /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH 0x00210950 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG 0x00210954 /* Context 10 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB 0x00210958 /* Context 10 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD 0x0021095c /* Context 10 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF 0x00210960 /* Context 10 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH 0x00210964 /* Context 10 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1 0x00210968 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2 0x0021096c /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3 0x00210970 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES 0x00210974 /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL 0x00210978 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL 0x0021097c /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL 0x00210980 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL 0x00210984 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL 0x00210988 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL 0x0021098c /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL 0x00210990 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL 0x00210994 /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL 0x00210998 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL 0x0021099c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE 0x002109a0 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID 0x002109a4 /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX10_REC_CTRL1 0x002109a8 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX10_REC_INIT_TS 0x002109ac /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX10_REC_TS_CTRL 0x002109b0 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG 0x002109b4 /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4 0x002109b8 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX10_PIC_CTR 0x002109bc /* Picture Counter register */ #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE 0x002109c0 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX10_REC_TIMER 0x002109c4 /* Record Timer Register */ #define BCHP_XPT_RAVE_CX10_REC_STATE0 0x002109c8 /* Record State Register */ #define BCHP_XPT_RAVE_CX10_REC_STATE1 0x002109cc /* Record State Register */ #define BCHP_XPT_RAVE_CX10_REC_STATE2 0x002109d0 /* Record State Register */ #define BCHP_XPT_RAVE_CX10_REC_STATE2b 0x002109d4 /* Record State Register */ #define BCHP_XPT_RAVE_CX10_REC_STATE3 0x002109d8 /* Record State Register */ #define BCHP_XPT_RAVE_CX10_REC_COUNT 0x002109dc /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL 0x002109e0 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX10_REC_RESERVE_STATE1 0x002109e4 /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX10_RAVE_Reg_0 0x002109e8 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX10_RAVE_Reg_1 0x002109ec /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX10_RAVE_Reg_2 0x002109f0 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX10_RAVE_Reg_3 0x002109f4 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX11_AV_CDB_WRITE_PTR 0x002109f8 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX11_AV_CDB_READ_PTR 0x002109fc /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX11_AV_CDB_BASE_PTR 0x00210a00 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX11_AV_CDB_END_PTR 0x00210a04 /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX11_AV_CDB_VALID_PTR 0x00210a08 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX11_AV_CDB_WRAPAROUND_PTR 0x00210a0c /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL 0x00210a10 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH 0x00210a14 /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS 0x00210a18 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX11_AV_ITB_WRITE_PTR 0x00210a1c /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX11_AV_ITB_READ_PTR 0x00210a20 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX11_AV_ITB_BASE_PTR 0x00210a24 /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX11_AV_ITB_END_PTR 0x00210a28 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX11_AV_ITB_VALID_PTR 0x00210a2c /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX11_AV_ITB_WRAPAROUND_PTR 0x00210a30 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL 0x00210a34 /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH 0x00210a38 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG 0x00210a3c /* Context 11 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB 0x00210a40 /* Context 11 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD 0x00210a44 /* Context 11 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF 0x00210a48 /* Context 11 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH 0x00210a4c /* Context 11 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1 0x00210a50 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2 0x00210a54 /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3 0x00210a58 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES 0x00210a5c /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL 0x00210a60 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL 0x00210a64 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL 0x00210a68 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL 0x00210a6c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL 0x00210a70 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL 0x00210a74 /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL 0x00210a78 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL 0x00210a7c /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL 0x00210a80 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL 0x00210a84 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE 0x00210a88 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID 0x00210a8c /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX11_REC_CTRL1 0x00210a90 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX11_REC_INIT_TS 0x00210a94 /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX11_REC_TS_CTRL 0x00210a98 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG 0x00210a9c /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4 0x00210aa0 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX11_PIC_CTR 0x00210aa4 /* Picture Counter register */ #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE 0x00210aa8 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX11_REC_TIMER 0x00210aac /* Record Timer Register */ #define BCHP_XPT_RAVE_CX11_REC_STATE0 0x00210ab0 /* Record State Register */ #define BCHP_XPT_RAVE_CX11_REC_STATE1 0x00210ab4 /* Record State Register */ #define BCHP_XPT_RAVE_CX11_REC_STATE2 0x00210ab8 /* Record State Register */ #define BCHP_XPT_RAVE_CX11_REC_STATE2b 0x00210abc /* Record State Register */ #define BCHP_XPT_RAVE_CX11_REC_STATE3 0x00210ac0 /* Record State Register */ #define BCHP_XPT_RAVE_CX11_REC_COUNT 0x00210ac4 /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL 0x00210ac8 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX11_REC_RESERVE_STATE1 0x00210acc /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX11_RAVE_Reg_0 0x00210ad0 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX11_RAVE_Reg_1 0x00210ad4 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX11_RAVE_Reg_2 0x00210ad8 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX11_RAVE_Reg_3 0x00210adc /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX12_AV_CDB_WRITE_PTR 0x00210ae0 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX12_AV_CDB_READ_PTR 0x00210ae4 /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX12_AV_CDB_BASE_PTR 0x00210ae8 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX12_AV_CDB_END_PTR 0x00210aec /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX12_AV_CDB_VALID_PTR 0x00210af0 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX12_AV_CDB_WRAPAROUND_PTR 0x00210af4 /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL 0x00210af8 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH 0x00210afc /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS 0x00210b00 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX12_AV_ITB_WRITE_PTR 0x00210b04 /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX12_AV_ITB_READ_PTR 0x00210b08 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX12_AV_ITB_BASE_PTR 0x00210b0c /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX12_AV_ITB_END_PTR 0x00210b10 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX12_AV_ITB_VALID_PTR 0x00210b14 /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX12_AV_ITB_WRAPAROUND_PTR 0x00210b18 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL 0x00210b1c /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH 0x00210b20 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG 0x00210b24 /* Context 12 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB 0x00210b28 /* Context 12 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD 0x00210b2c /* Context 12 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF 0x00210b30 /* Context 12 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH 0x00210b34 /* Context 12 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1 0x00210b38 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2 0x00210b3c /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3 0x00210b40 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES 0x00210b44 /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL 0x00210b48 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL 0x00210b4c /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL 0x00210b50 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL 0x00210b54 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL 0x00210b58 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL 0x00210b5c /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL 0x00210b60 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL 0x00210b64 /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL 0x00210b68 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL 0x00210b6c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode 0x00210b70 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID 0x00210b74 /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX12_REC_CTRL1 0x00210b78 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX12_REC_INIT_TS 0x00210b7c /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX12_REC_TS_CTRL 0x00210b80 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG 0x00210b84 /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4 0x00210b88 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX12_PIC_CTR 0x00210b8c /* Picture Counter register */ #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE 0x00210b90 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX12_REC_TIMER 0x00210b94 /* Record Timer Register */ #define BCHP_XPT_RAVE_CX12_REC_STATE0 0x00210b98 /* Record State Register */ #define BCHP_XPT_RAVE_CX12_REC_STATE1 0x00210b9c /* Record State Register */ #define BCHP_XPT_RAVE_CX12_REC_STATE2 0x00210ba0 /* Record State Register */ #define BCHP_XPT_RAVE_CX12_REC_STATE2b 0x00210ba4 /* Record State Register */ #define BCHP_XPT_RAVE_CX12_REC_STATE3 0x00210ba8 /* Record State Register */ #define BCHP_XPT_RAVE_CX12_REC_COUNT 0x00210bac /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL 0x00210bb0 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX12_REC_RESERVE_STATE1 0x00210bb4 /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX12_RAVE_Reg_0 0x00210bb8 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX12_RAVE_Reg_1 0x00210bbc /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX12_RAVE_Reg_2 0x00210bc0 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX12_RAVE_Reg_3 0x00210bc4 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX13_AV_CDB_WRITE_PTR 0x00210bc8 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX13_AV_CDB_READ_PTR 0x00210bcc /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX13_AV_CDB_BASE_PTR 0x00210bd0 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX13_AV_CDB_END_PTR 0x00210bd4 /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX13_AV_CDB_VALID_PTR 0x00210bd8 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX13_AV_CDB_WRAPAROUND_PTR 0x00210bdc /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL 0x00210be0 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH 0x00210be4 /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS 0x00210be8 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX13_AV_ITB_WRITE_PTR 0x00210bec /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX13_AV_ITB_READ_PTR 0x00210bf0 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX13_AV_ITB_BASE_PTR 0x00210bf4 /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX13_AV_ITB_END_PTR 0x00210bf8 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX13_AV_ITB_VALID_PTR 0x00210bfc /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX13_AV_ITB_WRAPAROUND_PTR 0x00210c00 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL 0x00210c04 /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH 0x00210c08 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG 0x00210c0c /* Context 13 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB 0x00210c10 /* Context 13 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD 0x00210c14 /* Context 13 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF 0x00210c18 /* Context 13 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH 0x00210c1c /* Context 13 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1 0x00210c20 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2 0x00210c24 /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3 0x00210c28 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES 0x00210c2c /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL 0x00210c30 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL 0x00210c34 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL 0x00210c38 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL 0x00210c3c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL 0x00210c40 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL 0x00210c44 /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL 0x00210c48 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL 0x00210c4c /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL 0x00210c50 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL 0x00210c54 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE 0x00210c58 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID 0x00210c5c /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX13_REC_CTRL1 0x00210c60 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX13_REC_INIT_TS 0x00210c64 /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX13_REC_TS_CTRL 0x00210c68 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG 0x00210c6c /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4 0x00210c70 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX13_PIC_CTR 0x00210c74 /* Picture Counter register */ #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE 0x00210c78 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX13_REC_TIMER 0x00210c7c /* Record Timer Register */ #define BCHP_XPT_RAVE_CX13_REC_STATE0 0x00210c80 /* Record State Register */ #define BCHP_XPT_RAVE_CX13_REC_STATE1 0x00210c84 /* Record State Register */ #define BCHP_XPT_RAVE_CX13_REC_STATE2 0x00210c88 /* Record State Register */ #define BCHP_XPT_RAVE_CX13_REC_STATE2b 0x00210c8c /* Record State Register */ #define BCHP_XPT_RAVE_CX13_REC_STATE3 0x00210c90 /* Record State Register */ #define BCHP_XPT_RAVE_CX13_REC_COUNT 0x00210c94 /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL 0x00210c98 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX13_REC_RESERVE_STATE1 0x00210c9c /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX13_RAVE_Reg_0 0x00210ca0 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX13_RAVE_Reg_1 0x00210ca4 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX13_RAVE_Reg_2 0x00210ca8 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX13_RAVE_Reg_3 0x00210cac /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX14_AV_CDB_WRITE_PTR 0x00210cb0 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX14_AV_CDB_READ_PTR 0x00210cb4 /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX14_AV_CDB_BASE_PTR 0x00210cb8 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX14_AV_CDB_END_PTR 0x00210cbc /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX14_AV_CDB_VALID_PTR 0x00210cc0 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX14_AV_CDB_WRAPAROUND_PTR 0x00210cc4 /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL 0x00210cc8 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH 0x00210ccc /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS 0x00210cd0 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX14_AV_ITB_WRITE_PTR 0x00210cd4 /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX14_AV_ITB_READ_PTR 0x00210cd8 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX14_AV_ITB_BASE_PTR 0x00210cdc /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX14_AV_ITB_END_PTR 0x00210ce0 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX14_AV_ITB_VALID_PTR 0x00210ce4 /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX14_AV_ITB_WRAPAROUND_PTR 0x00210ce8 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL 0x00210cec /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH 0x00210cf0 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG 0x00210cf4 /* Context 14 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB 0x00210cf8 /* Context 14 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD 0x00210cfc /* Context 14 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF 0x00210d00 /* Context 14 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH 0x00210d04 /* Context 14 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1 0x00210d08 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2 0x00210d0c /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3 0x00210d10 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES 0x00210d14 /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL 0x00210d18 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL 0x00210d1c /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL 0x00210d20 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL 0x00210d24 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL 0x00210d28 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL 0x00210d2c /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL 0x00210d30 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL 0x00210d34 /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL 0x00210d38 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL 0x00210d3c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode 0x00210d40 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID 0x00210d44 /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX14_REC_CTRL1 0x00210d48 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX14_REC_INIT_TS 0x00210d4c /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX14_REC_TS_CTRL 0x00210d50 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG 0x00210d54 /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4 0x00210d58 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX14_PIC_CTR 0x00210d5c /* Picture Counter register */ #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE 0x00210d60 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX14_REC_TIMER 0x00210d64 /* Record Timer Register */ #define BCHP_XPT_RAVE_CX14_REC_STATE0 0x00210d68 /* Record State Register */ #define BCHP_XPT_RAVE_CX14_REC_STATE1 0x00210d6c /* Record State Register */ #define BCHP_XPT_RAVE_CX14_REC_STATE2 0x00210d70 /* Record State Register */ #define BCHP_XPT_RAVE_CX14_REC_STATE2b 0x00210d74 /* Record State Register */ #define BCHP_XPT_RAVE_CX14_REC_STATE3 0x00210d78 /* Record State Register */ #define BCHP_XPT_RAVE_CX14_REC_COUNT 0x00210d7c /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL 0x00210d80 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX14_REC_RESERVE_STATE1 0x00210d84 /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX14_RAVE_Reg_0 0x00210d88 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX14_RAVE_Reg_1 0x00210d8c /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX14_RAVE_Reg_2 0x00210d90 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX14_RAVE_Reg_3 0x00210d94 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX15_AV_CDB_WRITE_PTR 0x00210d98 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX15_AV_CDB_READ_PTR 0x00210d9c /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX15_AV_CDB_BASE_PTR 0x00210da0 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX15_AV_CDB_END_PTR 0x00210da4 /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX15_AV_CDB_VALID_PTR 0x00210da8 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX15_AV_CDB_WRAPAROUND_PTR 0x00210dac /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL 0x00210db0 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH 0x00210db4 /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS 0x00210db8 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX15_AV_ITB_WRITE_PTR 0x00210dbc /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX15_AV_ITB_READ_PTR 0x00210dc0 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX15_AV_ITB_BASE_PTR 0x00210dc4 /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX15_AV_ITB_END_PTR 0x00210dc8 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX15_AV_ITB_VALID_PTR 0x00210dcc /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX15_AV_ITB_WRAPAROUND_PTR 0x00210dd0 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL 0x00210dd4 /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH 0x00210dd8 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG 0x00210ddc /* Context 15 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB 0x00210de0 /* Context 15 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD 0x00210de4 /* Context 15 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF 0x00210de8 /* Context 15 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH 0x00210dec /* Context 15 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1 0x00210df0 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2 0x00210df4 /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3 0x00210df8 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES 0x00210dfc /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL 0x00210e00 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL 0x00210e04 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL 0x00210e08 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL 0x00210e0c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL 0x00210e10 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL 0x00210e14 /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL 0x00210e18 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL 0x00210e1c /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL 0x00210e20 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL 0x00210e24 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE 0x00210e28 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID 0x00210e2c /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX15_REC_CTRL1 0x00210e30 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX15_REC_INIT_TS 0x00210e34 /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX15_REC_TS_CTRL 0x00210e38 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG 0x00210e3c /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4 0x00210e40 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX15_PIC_CTR 0x00210e44 /* Picture Counter register */ #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE 0x00210e48 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX15_REC_TIMER 0x00210e4c /* Record Timer Register */ #define BCHP_XPT_RAVE_CX15_REC_STATE0 0x00210e50 /* Record State Register */ #define BCHP_XPT_RAVE_CX15_REC_STATE1 0x00210e54 /* Record State Register */ #define BCHP_XPT_RAVE_CX15_REC_STATE2 0x00210e58 /* Record State Register */ #define BCHP_XPT_RAVE_CX15_REC_STATE2b 0x00210e5c /* Record State Register */ #define BCHP_XPT_RAVE_CX15_REC_STATE3 0x00210e60 /* Record State Register */ #define BCHP_XPT_RAVE_CX15_REC_COUNT 0x00210e64 /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL 0x00210e68 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX15_REC_RESERVE_STATE1 0x00210e6c /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX15_RAVE_Reg_0 0x00210e70 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX15_RAVE_Reg_1 0x00210e74 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX15_RAVE_Reg_2 0x00210e78 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX15_RAVE_Reg_3 0x00210e7c /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX16_AV_CDB_WRITE_PTR 0x00210e80 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX16_AV_CDB_READ_PTR 0x00210e84 /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX16_AV_CDB_BASE_PTR 0x00210e88 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX16_AV_CDB_END_PTR 0x00210e8c /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX16_AV_CDB_VALID_PTR 0x00210e90 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX16_AV_CDB_WRAPAROUND_PTR 0x00210e94 /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL 0x00210e98 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH 0x00210e9c /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS 0x00210ea0 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX16_AV_ITB_WRITE_PTR 0x00210ea4 /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX16_AV_ITB_READ_PTR 0x00210ea8 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX16_AV_ITB_BASE_PTR 0x00210eac /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX16_AV_ITB_END_PTR 0x00210eb0 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX16_AV_ITB_VALID_PTR 0x00210eb4 /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX16_AV_ITB_WRAPAROUND_PTR 0x00210eb8 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL 0x00210ebc /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH 0x00210ec0 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG 0x00210ec4 /* Context 16 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB 0x00210ec8 /* Context 16 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD 0x00210ecc /* Context 16 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF 0x00210ed0 /* Context 16 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH 0x00210ed4 /* Context 16 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1 0x00210ed8 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2 0x00210edc /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3 0x00210ee0 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES 0x00210ee4 /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL 0x00210ee8 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL 0x00210eec /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL 0x00210ef0 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL 0x00210ef4 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL 0x00210ef8 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL 0x00210efc /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL 0x00210f00 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL 0x00210f04 /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL 0x00210f08 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL 0x00210f0c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE 0x00210f10 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID 0x00210f14 /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX16_REC_CTRL1 0x00210f18 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX16_REC_INIT_TS 0x00210f1c /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX16_REC_TS_CTRL 0x00210f20 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG 0x00210f24 /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4 0x00210f28 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX16_PIC_CTR 0x00210f2c /* Picture Counter register */ #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE 0x00210f30 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX16_REC_TIMER 0x00210f34 /* Record Timer Register */ #define BCHP_XPT_RAVE_CX16_REC_STATE0 0x00210f38 /* Record State Register */ #define BCHP_XPT_RAVE_CX16_REC_STATE1 0x00210f3c /* Record State Register */ #define BCHP_XPT_RAVE_CX16_REC_STATE2 0x00210f40 /* Record State Register */ #define BCHP_XPT_RAVE_CX16_REC_STATE2b 0x00210f44 /* Record State Register */ #define BCHP_XPT_RAVE_CX16_REC_STATE3 0x00210f48 /* Record State Register */ #define BCHP_XPT_RAVE_CX16_REC_COUNT 0x00210f4c /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL 0x00210f50 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX16_REC_RESERVE_STATE1 0x00210f54 /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX16_RAVE_Reg_0 0x00210f58 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX16_RAVE_Reg_1 0x00210f5c /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX16_RAVE_Reg_2 0x00210f60 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX16_RAVE_Reg_3 0x00210f64 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX17_AV_CDB_WRITE_PTR 0x00210f68 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX17_AV_CDB_READ_PTR 0x00210f6c /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX17_AV_CDB_BASE_PTR 0x00210f70 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX17_AV_CDB_END_PTR 0x00210f74 /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX17_AV_CDB_VALID_PTR 0x00210f78 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX17_AV_CDB_WRAPAROUND_PTR 0x00210f7c /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL 0x00210f80 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH 0x00210f84 /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS 0x00210f88 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX17_AV_ITB_WRITE_PTR 0x00210f8c /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX17_AV_ITB_READ_PTR 0x00210f90 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX17_AV_ITB_BASE_PTR 0x00210f94 /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX17_AV_ITB_END_PTR 0x00210f98 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX17_AV_ITB_VALID_PTR 0x00210f9c /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX17_AV_ITB_WRAPAROUND_PTR 0x00210fa0 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL 0x00210fa4 /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH 0x00210fa8 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG 0x00210fac /* Context 17 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB 0x00210fb0 /* Context 17 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD 0x00210fb4 /* Context 17 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF 0x00210fb8 /* Context 17 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH 0x00210fbc /* Context 17 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1 0x00210fc0 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2 0x00210fc4 /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3 0x00210fc8 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES 0x00210fcc /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL 0x00210fd0 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL 0x00210fd4 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL 0x00210fd8 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL 0x00210fdc /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL 0x00210fe0 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL 0x00210fe4 /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL 0x00210fe8 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL 0x00210fec /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL 0x00210ff0 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL 0x00210ff4 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE 0x00210ff8 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID 0x00210ffc /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX17_REC_CTRL1 0x00211000 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX17_REC_INIT_TS 0x00211004 /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX17_REC_TS_CTRL 0x00211008 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG 0x0021100c /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4 0x00211010 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX17_PIC_CTR 0x00211014 /* Picture Counter register */ #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE 0x00211018 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX17_REC_TIMER 0x0021101c /* Record Timer Register */ #define BCHP_XPT_RAVE_CX17_REC_STATE0 0x00211020 /* Record State Register */ #define BCHP_XPT_RAVE_CX17_REC_STATE1 0x00211024 /* Record State Register */ #define BCHP_XPT_RAVE_CX17_REC_STATE2 0x00211028 /* Record State Register */ #define BCHP_XPT_RAVE_CX17_REC_STATE2b 0x0021102c /* Record State Register */ #define BCHP_XPT_RAVE_CX17_REC_STATE3 0x00211030 /* Record State Register */ #define BCHP_XPT_RAVE_CX17_REC_COUNT 0x00211034 /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL 0x00211038 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX17_REC_RESERVE_STATE1 0x0021103c /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX17_RAVE_Reg_0 0x00211040 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX17_RAVE_Reg_1 0x00211044 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX17_RAVE_Reg_2 0x00211048 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX17_RAVE_Reg_3 0x0021104c /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX18_AV_CDB_WRITE_PTR 0x00211050 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX18_AV_CDB_READ_PTR 0x00211054 /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX18_AV_CDB_BASE_PTR 0x00211058 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX18_AV_CDB_END_PTR 0x0021105c /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX18_AV_CDB_VALID_PTR 0x00211060 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX18_AV_CDB_WRAPAROUND_PTR 0x00211064 /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL 0x00211068 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH 0x0021106c /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS 0x00211070 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX18_AV_ITB_WRITE_PTR 0x00211074 /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX18_AV_ITB_READ_PTR 0x00211078 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX18_AV_ITB_BASE_PTR 0x0021107c /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX18_AV_ITB_END_PTR 0x00211080 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX18_AV_ITB_VALID_PTR 0x00211084 /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX18_AV_ITB_WRAPAROUND_PTR 0x00211088 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL 0x0021108c /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH 0x00211090 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG 0x00211094 /* Context 18 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB 0x00211098 /* Context 18 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD 0x0021109c /* Context 18 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF 0x002110a0 /* Context 18 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH 0x002110a4 /* Context 18 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1 0x002110a8 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2 0x002110ac /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3 0x002110b0 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES 0x002110b4 /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL 0x002110b8 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL 0x002110bc /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL 0x002110c0 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL 0x002110c4 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL 0x002110c8 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL 0x002110cc /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL 0x002110d0 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL 0x002110d4 /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL 0x002110d8 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL 0x002110dc /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE 0x002110e0 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID 0x002110e4 /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX18_REC_CTRL1 0x002110e8 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX18_REC_INIT_TS 0x002110ec /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX18_REC_TS_CTRL 0x002110f0 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG 0x002110f4 /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4 0x002110f8 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX18_PIC_CTR 0x002110fc /* Picture Counter register */ #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE 0x00211100 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX18_REC_TIMER 0x00211104 /* Record Timer Register */ #define BCHP_XPT_RAVE_CX18_REC_STATE0 0x00211108 /* Record State Register */ #define BCHP_XPT_RAVE_CX18_REC_STATE1 0x0021110c /* Record State Register */ #define BCHP_XPT_RAVE_CX18_REC_STATE2 0x00211110 /* Record State Register */ #define BCHP_XPT_RAVE_CX18_REC_STATE2b 0x00211114 /* Record State Register */ #define BCHP_XPT_RAVE_CX18_REC_STATE3 0x00211118 /* Record State Register */ #define BCHP_XPT_RAVE_CX18_REC_COUNT 0x0021111c /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL 0x00211120 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX18_REC_RESERVE_STATE1 0x00211124 /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX18_RAVE_Reg_0 0x00211128 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX18_RAVE_Reg_1 0x0021112c /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX18_RAVE_Reg_2 0x00211130 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX18_RAVE_Reg_3 0x00211134 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX19_AV_CDB_WRITE_PTR 0x00211138 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX19_AV_CDB_READ_PTR 0x0021113c /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX19_AV_CDB_BASE_PTR 0x00211140 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX19_AV_CDB_END_PTR 0x00211144 /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX19_AV_CDB_VALID_PTR 0x00211148 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX19_AV_CDB_WRAPAROUND_PTR 0x0021114c /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL 0x00211150 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH 0x00211154 /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS 0x00211158 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX19_AV_ITB_WRITE_PTR 0x0021115c /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX19_AV_ITB_READ_PTR 0x00211160 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX19_AV_ITB_BASE_PTR 0x00211164 /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX19_AV_ITB_END_PTR 0x00211168 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX19_AV_ITB_VALID_PTR 0x0021116c /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX19_AV_ITB_WRAPAROUND_PTR 0x00211170 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL 0x00211174 /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH 0x00211178 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG 0x0021117c /* Context 19 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB 0x00211180 /* Context 19 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD 0x00211184 /* Context 19 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF 0x00211188 /* Context 19 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH 0x0021118c /* Context 19 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1 0x00211190 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2 0x00211194 /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3 0x00211198 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES 0x0021119c /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL 0x002111a0 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL 0x002111a4 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL 0x002111a8 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL 0x002111ac /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL 0x002111b0 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL 0x002111b4 /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL 0x002111b8 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL 0x002111bc /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL 0x002111c0 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL 0x002111c4 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE 0x002111c8 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID 0x002111cc /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX19_REC_CTRL1 0x002111d0 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX19_REC_INIT_TS 0x002111d4 /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX19_REC_TS_CTRL 0x002111d8 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG 0x002111dc /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4 0x002111e0 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX19_PIC_CTR 0x002111e4 /* Picture Counter register */ #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE 0x002111e8 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX19_REC_TIMER 0x002111ec /* Record Timer Register */ #define BCHP_XPT_RAVE_CX19_REC_STATE0 0x002111f0 /* Record State Register */ #define BCHP_XPT_RAVE_CX19_REC_STATE1 0x002111f4 /* Record State Register */ #define BCHP_XPT_RAVE_CX19_REC_STATE2 0x002111f8 /* Record State Register */ #define BCHP_XPT_RAVE_CX19_REC_STATE2b 0x002111fc /* Record State Register */ #define BCHP_XPT_RAVE_CX19_REC_STATE3 0x00211200 /* Record State Register */ #define BCHP_XPT_RAVE_CX19_REC_COUNT 0x00211204 /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL 0x00211208 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX19_REC_RESERVE_STATE1 0x0021120c /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX19_RAVE_Reg_0 0x00211210 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX19_RAVE_Reg_1 0x00211214 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX19_RAVE_Reg_2 0x00211218 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX19_RAVE_Reg_3 0x0021121c /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX20_AV_CDB_WRITE_PTR 0x00211220 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX20_AV_CDB_READ_PTR 0x00211224 /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX20_AV_CDB_BASE_PTR 0x00211228 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX20_AV_CDB_END_PTR 0x0021122c /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX20_AV_CDB_VALID_PTR 0x00211230 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX20_AV_CDB_WRAPAROUND_PTR 0x00211234 /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL 0x00211238 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH 0x0021123c /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS 0x00211240 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX20_AV_ITB_WRITE_PTR 0x00211244 /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX20_AV_ITB_READ_PTR 0x00211248 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX20_AV_ITB_BASE_PTR 0x0021124c /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX20_AV_ITB_END_PTR 0x00211250 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX20_AV_ITB_VALID_PTR 0x00211254 /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX20_AV_ITB_WRAPAROUND_PTR 0x00211258 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL 0x0021125c /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH 0x00211260 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG 0x00211264 /* Context 20 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB 0x00211268 /* Context 20 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD 0x0021126c /* Context 20 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF 0x00211270 /* Context 20 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH 0x00211274 /* Context 20 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1 0x00211278 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2 0x0021127c /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3 0x00211280 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES 0x00211284 /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL 0x00211288 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL 0x0021128c /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL 0x00211290 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL 0x00211294 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL 0x00211298 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL 0x0021129c /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL 0x002112a0 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL 0x002112a4 /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL 0x002112a8 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL 0x002112ac /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode 0x002112b0 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID 0x002112b4 /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX20_REC_CTRL1 0x002112b8 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX20_REC_INIT_TS 0x002112bc /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX20_REC_TS_CTRL 0x002112c0 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG 0x002112c4 /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4 0x002112c8 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX20_PIC_CTR 0x002112cc /* Picture Counter register */ #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE 0x002112d0 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX20_REC_TIMER 0x002112d4 /* Record Timer Register */ #define BCHP_XPT_RAVE_CX20_REC_STATE0 0x002112d8 /* Record State Register */ #define BCHP_XPT_RAVE_CX20_REC_STATE1 0x002112dc /* Record State Register */ #define BCHP_XPT_RAVE_CX20_REC_STATE2 0x002112e0 /* Record State Register */ #define BCHP_XPT_RAVE_CX20_REC_STATE2b 0x002112e4 /* Record State Register */ #define BCHP_XPT_RAVE_CX20_REC_STATE3 0x002112e8 /* Record State Register */ #define BCHP_XPT_RAVE_CX20_REC_COUNT 0x002112ec /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL 0x002112f0 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX20_REC_RESERVE_STATE1 0x002112f4 /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX20_RAVE_Reg_0 0x002112f8 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX20_RAVE_Reg_1 0x002112fc /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX20_RAVE_Reg_2 0x00211300 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX20_RAVE_Reg_3 0x00211304 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX21_AV_CDB_WRITE_PTR 0x00211308 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX21_AV_CDB_READ_PTR 0x0021130c /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX21_AV_CDB_BASE_PTR 0x00211310 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX21_AV_CDB_END_PTR 0x00211314 /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX21_AV_CDB_VALID_PTR 0x00211318 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX21_AV_CDB_WRAPAROUND_PTR 0x0021131c /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL 0x00211320 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH 0x00211324 /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS 0x00211328 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX21_AV_ITB_WRITE_PTR 0x0021132c /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX21_AV_ITB_READ_PTR 0x00211330 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX21_AV_ITB_BASE_PTR 0x00211334 /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX21_AV_ITB_END_PTR 0x00211338 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX21_AV_ITB_VALID_PTR 0x0021133c /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX21_AV_ITB_WRAPAROUND_PTR 0x00211340 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL 0x00211344 /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH 0x00211348 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG 0x0021134c /* Context 21 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB 0x00211350 /* Context 21 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD 0x00211354 /* Context 21 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF 0x00211358 /* Context 21 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH 0x0021135c /* Context 21 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1 0x00211360 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2 0x00211364 /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3 0x00211368 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES 0x0021136c /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL 0x00211370 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL 0x00211374 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL 0x00211378 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL 0x0021137c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL 0x00211380 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL 0x00211384 /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL 0x00211388 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL 0x0021138c /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL 0x00211390 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL 0x00211394 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE 0x00211398 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID 0x0021139c /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX21_REC_CTRL1 0x002113a0 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX21_REC_INIT_TS 0x002113a4 /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX21_REC_TS_CTRL 0x002113a8 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG 0x002113ac /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4 0x002113b0 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX21_PIC_CTR 0x002113b4 /* Picture Counter register */ #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE 0x002113b8 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX21_REC_TIMER 0x002113bc /* Record Timer Register */ #define BCHP_XPT_RAVE_CX21_REC_STATE0 0x002113c0 /* Record State Register */ #define BCHP_XPT_RAVE_CX21_REC_STATE1 0x002113c4 /* Record State Register */ #define BCHP_XPT_RAVE_CX21_REC_STATE2 0x002113c8 /* Record State Register */ #define BCHP_XPT_RAVE_CX21_REC_STATE2b 0x002113cc /* Record State Register */ #define BCHP_XPT_RAVE_CX21_REC_STATE3 0x002113d0 /* Record State Register */ #define BCHP_XPT_RAVE_CX21_REC_COUNT 0x002113d4 /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL 0x002113d8 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX21_REC_RESERVE_STATE1 0x002113dc /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX21_RAVE_Reg_0 0x002113e0 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX21_RAVE_Reg_1 0x002113e4 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX21_RAVE_Reg_2 0x002113e8 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX21_RAVE_Reg_3 0x002113ec /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX22_AV_CDB_WRITE_PTR 0x002113f0 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX22_AV_CDB_READ_PTR 0x002113f4 /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX22_AV_CDB_BASE_PTR 0x002113f8 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX22_AV_CDB_END_PTR 0x002113fc /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX22_AV_CDB_VALID_PTR 0x00211400 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX22_AV_CDB_WRAPAROUND_PTR 0x00211404 /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL 0x00211408 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH 0x0021140c /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS 0x00211410 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX22_AV_ITB_WRITE_PTR 0x00211414 /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX22_AV_ITB_READ_PTR 0x00211418 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX22_AV_ITB_BASE_PTR 0x0021141c /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX22_AV_ITB_END_PTR 0x00211420 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX22_AV_ITB_VALID_PTR 0x00211424 /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX22_AV_ITB_WRAPAROUND_PTR 0x00211428 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL 0x0021142c /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH 0x00211430 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG 0x00211434 /* Context 22 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB 0x00211438 /* Context 22 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD 0x0021143c /* Context 22 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF 0x00211440 /* Context 22 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH 0x00211444 /* Context 22 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1 0x00211448 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2 0x0021144c /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3 0x00211450 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES 0x00211454 /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL 0x00211458 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL 0x0021145c /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL 0x00211460 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL 0x00211464 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL 0x00211468 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL 0x0021146c /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL 0x00211470 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL 0x00211474 /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL 0x00211478 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL 0x0021147c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode 0x00211480 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID 0x00211484 /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX22_REC_CTRL1 0x00211488 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX22_REC_INIT_TS 0x0021148c /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX22_REC_TS_CTRL 0x00211490 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG 0x00211494 /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4 0x00211498 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX22_PIC_CTR 0x0021149c /* Picture Counter register */ #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE 0x002114a0 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX22_REC_TIMER 0x002114a4 /* Record Timer Register */ #define BCHP_XPT_RAVE_CX22_REC_STATE0 0x002114a8 /* Record State Register */ #define BCHP_XPT_RAVE_CX22_REC_STATE1 0x002114ac /* Record State Register */ #define BCHP_XPT_RAVE_CX22_REC_STATE2 0x002114b0 /* Record State Register */ #define BCHP_XPT_RAVE_CX22_REC_STATE2b 0x002114b4 /* Record State Register */ #define BCHP_XPT_RAVE_CX22_REC_STATE3 0x002114b8 /* Record State Register */ #define BCHP_XPT_RAVE_CX22_REC_COUNT 0x002114bc /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL 0x002114c0 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX22_REC_RESERVE_STATE1 0x002114c4 /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX22_RAVE_Reg_0 0x002114c8 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX22_RAVE_Reg_1 0x002114cc /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX22_RAVE_Reg_2 0x002114d0 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX22_RAVE_Reg_3 0x002114d4 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX23_AV_CDB_WRITE_PTR 0x002114d8 /* Context CDB Write Pointer */ #define BCHP_XPT_RAVE_CX23_AV_CDB_READ_PTR 0x002114dc /* Context CDB Read Pointer */ #define BCHP_XPT_RAVE_CX23_AV_CDB_BASE_PTR 0x002114e0 /* Context CDB Base Pointer */ #define BCHP_XPT_RAVE_CX23_AV_CDB_END_PTR 0x002114e4 /* Context CDB End Pointer */ #define BCHP_XPT_RAVE_CX23_AV_CDB_VALID_PTR 0x002114e8 /* Context CDB Valid Pointer */ #define BCHP_XPT_RAVE_CX23_AV_CDB_WRAPAROUND_PTR 0x002114ec /* Context CDB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL 0x002114f0 /* Context CDB Watermark Level */ #define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH 0x002114f4 /* Context CDB Depth */ #define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS 0x002114f8 /* Context Thresholds */ #define BCHP_XPT_RAVE_CX23_AV_ITB_WRITE_PTR 0x002114fc /* Context ITB Write Pointer */ #define BCHP_XPT_RAVE_CX23_AV_ITB_READ_PTR 0x00211500 /* Context ITB Read Pointer */ #define BCHP_XPT_RAVE_CX23_AV_ITB_BASE_PTR 0x00211504 /* Context ITB Base Pointer */ #define BCHP_XPT_RAVE_CX23_AV_ITB_END_PTR 0x00211508 /* Context ITB End Pointer */ #define BCHP_XPT_RAVE_CX23_AV_ITB_VALID_PTR 0x0021150c /* Context ITB Valid Pointer */ #define BCHP_XPT_RAVE_CX23_AV_ITB_WRAPAROUND_PTR 0x00211510 /* Context ITB Wraparound Pointer */ #define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL 0x00211514 /* Context ITB Watermark Level */ #define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH 0x00211518 /* Context ITB Depth */ #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG 0x0021151c /* Context 23 Miscellaneous Config */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB 0x00211520 /* Context 23 SCD map PIDS A and B */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD 0x00211524 /* Context 23 SCD map PIDS C and D */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF 0x00211528 /* Context 23 SCD map PIDS E and F */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH 0x0021152c /* Context 23 SCD map PIDS G and H */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1 0x00211530 /* Context Miscellaneous Config 1 Register */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2 0x00211534 /* Context Miscellaneous Config 2 Register */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3 0x00211538 /* Context Miscellaneous Config 3 Register */ #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES 0x0021153c /* Context Interrupt Enables */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL 0x00211540 /* Context Comparator 1 Control Register */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL 0x00211544 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL 0x00211548 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL 0x0021154c /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL 0x00211550 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL 0x00211554 /* Context Comparator 2 Control Register */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL 0x00211558 /* Context Comparator 2 32-bit compare value */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL 0x0021155c /* Context Comparator 2 32-bit mask value */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL 0x00211560 /* Context Comparator 1 32-bit compare value */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL 0x00211564 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE 0x00211568 /* Context Comparator 1 32-bit mask value */ #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID 0x0021156c /* Context PID and Stream ID Filter Value */ #define BCHP_XPT_RAVE_CX23_REC_CTRL1 0x00211570 /* Record Control Register 1 */ #define BCHP_XPT_RAVE_CX23_REC_INIT_TS 0x00211574 /* Record Initial Timestamp Value Register */ #define BCHP_XPT_RAVE_CX23_REC_TS_CTRL 0x00211578 /* Record Timestamp Control Register */ #define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG 0x0021157c /* Record Time Configuration Register */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4 0x00211580 /* Context Miscellaneous Config 4 Register */ #define BCHP_XPT_RAVE_CX23_PIC_CTR 0x00211584 /* Picture Counter register */ #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE 0x00211588 /* Picture Counter Mode Register */ #define BCHP_XPT_RAVE_CX23_REC_TIMER 0x0021158c /* Record Timer Register */ #define BCHP_XPT_RAVE_CX23_REC_STATE0 0x00211590 /* Record State Register */ #define BCHP_XPT_RAVE_CX23_REC_STATE1 0x00211594 /* Record State Register */ #define BCHP_XPT_RAVE_CX23_REC_STATE2 0x00211598 /* Record State Register */ #define BCHP_XPT_RAVE_CX23_REC_STATE2b 0x0021159c /* Record State Register */ #define BCHP_XPT_RAVE_CX23_REC_STATE3 0x002115a0 /* Record State Register */ #define BCHP_XPT_RAVE_CX23_REC_COUNT 0x002115a4 /* Record Packet Count Register */ #define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL 0x002115a8 /* Picture Counter Increment/Decrement/Reset Control Register */ #define BCHP_XPT_RAVE_CX23_REC_RESERVE_STATE1 0x002115ac /* Reserved Record State Register */ #define BCHP_XPT_RAVE_CX23_RAVE_Reg_0 0x002115b0 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX23_RAVE_Reg_1 0x002115b4 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX23_RAVE_Reg_2 0x002115b8 /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_CX23_RAVE_Reg_3 0x002115bc /* Reserved Rave Register for future use */ #define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG 0x002115c0 /* SCD 0 Misc Config Register */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE0 0x002115c4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE1 0x002115c8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE2 0x002115cc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE3 0x002115d0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE4 0x002115d4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE5 0x002115d8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE6 0x002115dc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE7 0x002115e0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE8 0x002115e4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE9 0x002115e8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE10 0x002115ec /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE11 0x002115f0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_RESERVE_COMP_STATE0 0x002115f4 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE0 0x002115f8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE1 0x002115fc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE2 0x00211600 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE3 0x00211604 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_PACKET_COUNT 0x00211608 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE0 0x0021160c /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE1 0x00211610 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_STATE0 0x00211614 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_STATE1 0x00211618 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_STATE2 0x0021161c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_STATE3 0x00211620 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_STATE4 0x00211624 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_SCD_STATE5 0x00211628 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD0_RESERVED_STATE0 0x0021162c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD0_RESERVED_STATE1 0x00211630 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD0_RESERVED_STATE2 0x00211634 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD0_RESERVED_STATE3 0x00211638 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG 0x0021163c /* SCD 1 Misc Config Register */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE0 0x00211640 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE1 0x00211644 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE2 0x00211648 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE3 0x0021164c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE4 0x00211650 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE5 0x00211654 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE6 0x00211658 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE7 0x0021165c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE8 0x00211660 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE9 0x00211664 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE10 0x00211668 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE11 0x0021166c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_RESERVE_COMP_STATE0 0x00211670 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE0 0x00211674 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE1 0x00211678 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE2 0x0021167c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE3 0x00211680 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_PACKET_COUNT 0x00211684 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE0 0x00211688 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE1 0x0021168c /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_STATE0 0x00211690 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_STATE1 0x00211694 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_STATE2 0x00211698 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_STATE3 0x0021169c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_STATE4 0x002116a0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_SCD_STATE5 0x002116a4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD1_RESERVED_STATE0 0x002116a8 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD1_RESERVED_STATE1 0x002116ac /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD1_RESERVED_STATE2 0x002116b0 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD1_RESERVED_STATE3 0x002116b4 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG 0x002116b8 /* SCD 2 Misc Config Register */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE0 0x002116bc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE1 0x002116c0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE2 0x002116c4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE3 0x002116c8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE4 0x002116cc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE5 0x002116d0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE6 0x002116d4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE7 0x002116d8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE8 0x002116dc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE9 0x002116e0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE10 0x002116e4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE11 0x002116e8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_RESERVE_COMP_STATE0 0x002116ec /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE0 0x002116f0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE1 0x002116f4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE2 0x002116f8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE3 0x002116fc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_PACKET_COUNT 0x00211700 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE0 0x00211704 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE1 0x00211708 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_STATE0 0x0021170c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_STATE1 0x00211710 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_STATE2 0x00211714 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_STATE3 0x00211718 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_STATE4 0x0021171c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_SCD_STATE5 0x00211720 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD2_RESERVED_STATE0 0x00211724 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD2_RESERVED_STATE1 0x00211728 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD2_RESERVED_STATE2 0x0021172c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD2_RESERVED_STATE3 0x00211730 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG 0x00211734 /* SCD 3 Misc Config Register */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE0 0x00211738 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE1 0x0021173c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE2 0x00211740 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE3 0x00211744 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE4 0x00211748 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE5 0x0021174c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE6 0x00211750 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE7 0x00211754 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE8 0x00211758 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE9 0x0021175c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE10 0x00211760 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE11 0x00211764 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_RESERVE_COMP_STATE0 0x00211768 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE0 0x0021176c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE1 0x00211770 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE2 0x00211774 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE3 0x00211778 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_PACKET_COUNT 0x0021177c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE0 0x00211780 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE1 0x00211784 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_STATE0 0x00211788 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_STATE1 0x0021178c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_STATE2 0x00211790 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_STATE3 0x00211794 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_STATE4 0x00211798 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_SCD_STATE5 0x0021179c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD3_RESERVED_STATE0 0x002117a0 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD3_RESERVED_STATE1 0x002117a4 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD3_RESERVED_STATE2 0x002117a8 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD3_RESERVED_STATE3 0x002117ac /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG 0x002117b0 /* SCD 4 Misc Config Register */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE0 0x002117b4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE1 0x002117b8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE2 0x002117bc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE3 0x002117c0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE4 0x002117c4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE5 0x002117c8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE6 0x002117cc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE7 0x002117d0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE8 0x002117d4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE9 0x002117d8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE10 0x002117dc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE11 0x002117e0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_RESERVE_COMP_STATE0 0x002117e4 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE0 0x002117e8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE1 0x002117ec /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE2 0x002117f0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE3 0x002117f4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_PACKET_COUNT 0x002117f8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE0 0x002117fc /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE1 0x00211800 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_STATE0 0x00211804 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_STATE1 0x00211808 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_STATE2 0x0021180c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_STATE3 0x00211810 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_STATE4 0x00211814 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_SCD_STATE5 0x00211818 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD4_RESERVED_STATE0 0x0021181c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD4_RESERVED_STATE1 0x00211820 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD4_RESERVED_STATE2 0x00211824 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD4_RESERVED_STATE3 0x00211828 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG 0x0021182c /* SCD 5 Misc Config Register */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE0 0x00211830 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE1 0x00211834 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE2 0x00211838 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE3 0x0021183c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE4 0x00211840 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE5 0x00211844 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE6 0x00211848 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE7 0x0021184c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE8 0x00211850 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE9 0x00211854 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE10 0x00211858 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE11 0x0021185c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_RESERVE_COMP_STATE0 0x00211860 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE0 0x00211864 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE1 0x00211868 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE2 0x0021186c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE3 0x00211870 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_PACKET_COUNT 0x00211874 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE0 0x00211878 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE1 0x0021187c /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_STATE0 0x00211880 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_STATE1 0x00211884 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_STATE2 0x00211888 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_STATE3 0x0021188c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_STATE4 0x00211890 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_SCD_STATE5 0x00211894 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD5_RESERVED_STATE0 0x00211898 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD5_RESERVED_STATE1 0x0021189c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD5_RESERVED_STATE2 0x002118a0 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD5_RESERVED_STATE3 0x002118a4 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG 0x002118a8 /* SCD 6 Misc Config Register */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE0 0x002118ac /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE1 0x002118b0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE2 0x002118b4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE3 0x002118b8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE4 0x002118bc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE5 0x002118c0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE6 0x002118c4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE7 0x002118c8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE8 0x002118cc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE9 0x002118d0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE10 0x002118d4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE11 0x002118d8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_RESERVE_COMP_STATE0 0x002118dc /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE0 0x002118e0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE1 0x002118e4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE2 0x002118e8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE3 0x002118ec /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_PACKET_COUNT 0x002118f0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE0 0x002118f4 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE1 0x002118f8 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_STATE0 0x002118fc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_STATE1 0x00211900 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_STATE2 0x00211904 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_STATE3 0x00211908 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_STATE4 0x0021190c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_SCD_STATE5 0x00211910 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD6_RESERVED_STATE0 0x00211914 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD6_RESERVED_STATE1 0x00211918 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD6_RESERVED_STATE2 0x0021191c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD6_RESERVED_STATE3 0x00211920 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG 0x00211924 /* SCD 7 Misc Config Register */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE0 0x00211928 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE1 0x0021192c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE2 0x00211930 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE3 0x00211934 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE4 0x00211938 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE5 0x0021193c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE6 0x00211940 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE7 0x00211944 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE8 0x00211948 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE9 0x0021194c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE10 0x00211950 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE11 0x00211954 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_RESERVE_COMP_STATE0 0x00211958 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE0 0x0021195c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE1 0x00211960 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE2 0x00211964 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE3 0x00211968 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_PACKET_COUNT 0x0021196c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE0 0x00211970 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE1 0x00211974 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_STATE0 0x00211978 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_STATE1 0x0021197c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_STATE2 0x00211980 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_STATE3 0x00211984 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_STATE4 0x00211988 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_SCD_STATE5 0x0021198c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD7_RESERVED_STATE0 0x00211990 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD7_RESERVED_STATE1 0x00211994 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD7_RESERVED_STATE2 0x00211998 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD7_RESERVED_STATE3 0x0021199c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG 0x002119a0 /* SCD 8 Misc Config Register */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE0 0x002119a4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE1 0x002119a8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE2 0x002119ac /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE3 0x002119b0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE4 0x002119b4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE5 0x002119b8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE6 0x002119bc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE7 0x002119c0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE8 0x002119c4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE9 0x002119c8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE10 0x002119cc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE11 0x002119d0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_RESERVE_COMP_STATE0 0x002119d4 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE0 0x002119d8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE1 0x002119dc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE2 0x002119e0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE3 0x002119e4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_PACKET_COUNT 0x002119e8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE0 0x002119ec /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE1 0x002119f0 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_STATE0 0x002119f4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_STATE1 0x002119f8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_STATE2 0x002119fc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_STATE3 0x00211a00 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_STATE4 0x00211a04 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_SCD_STATE5 0x00211a08 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD8_RESERVED_STATE0 0x00211a0c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD8_RESERVED_STATE1 0x00211a10 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD8_RESERVED_STATE2 0x00211a14 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD8_RESERVED_STATE3 0x00211a18 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG 0x00211a1c /* SCD 9 Misc Config Register */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE0 0x00211a20 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE1 0x00211a24 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE2 0x00211a28 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE3 0x00211a2c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE4 0x00211a30 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE5 0x00211a34 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE6 0x00211a38 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE7 0x00211a3c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE8 0x00211a40 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE9 0x00211a44 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE10 0x00211a48 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE11 0x00211a4c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_RESERVE_COMP_STATE0 0x00211a50 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE0 0x00211a54 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE1 0x00211a58 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE2 0x00211a5c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE3 0x00211a60 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_PACKET_COUNT 0x00211a64 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE0 0x00211a68 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE1 0x00211a6c /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_STATE0 0x00211a70 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_STATE1 0x00211a74 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_STATE2 0x00211a78 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_STATE3 0x00211a7c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_STATE4 0x00211a80 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_SCD_STATE5 0x00211a84 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD9_RESERVED_STATE0 0x00211a88 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD9_RESERVED_STATE1 0x00211a8c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD9_RESERVED_STATE2 0x00211a90 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD9_RESERVED_STATE3 0x00211a94 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG 0x00211a98 /* SCD 10 Misc Config Register */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE0 0x00211a9c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE1 0x00211aa0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE2 0x00211aa4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE3 0x00211aa8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE4 0x00211aac /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE5 0x00211ab0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE6 0x00211ab4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE7 0x00211ab8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE8 0x00211abc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE9 0x00211ac0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE10 0x00211ac4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE11 0x00211ac8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_RESERVE_COMP_STATE0 0x00211acc /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE0 0x00211ad0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE1 0x00211ad4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE2 0x00211ad8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE3 0x00211adc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_PACKET_COUNT 0x00211ae0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE0 0x00211ae4 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE1 0x00211ae8 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_STATE0 0x00211aec /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_STATE1 0x00211af0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_STATE2 0x00211af4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_STATE3 0x00211af8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_STATE4 0x00211afc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_SCD_STATE5 0x00211b00 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD10_RESERVED_STATE0 0x00211b04 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD10_RESERVED_STATE1 0x00211b08 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD10_RESERVED_STATE2 0x00211b0c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD10_RESERVED_STATE3 0x00211b10 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG 0x00211b14 /* SCD 11 Misc Config Register */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE0 0x00211b18 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE1 0x00211b1c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE2 0x00211b20 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE3 0x00211b24 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE4 0x00211b28 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE5 0x00211b2c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE6 0x00211b30 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE7 0x00211b34 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE8 0x00211b38 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE9 0x00211b3c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE10 0x00211b40 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE11 0x00211b44 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_RESERVE_COMP_STATE0 0x00211b48 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE0 0x00211b4c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE1 0x00211b50 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE2 0x00211b54 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE3 0x00211b58 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_PACKET_COUNT 0x00211b5c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE0 0x00211b60 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE1 0x00211b64 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_STATE0 0x00211b68 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_STATE1 0x00211b6c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_STATE2 0x00211b70 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_STATE3 0x00211b74 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_STATE4 0x00211b78 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_SCD_STATE5 0x00211b7c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD11_RESERVED_STATE0 0x00211b80 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD11_RESERVED_STATE1 0x00211b84 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD11_RESERVED_STATE2 0x00211b88 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD11_RESERVED_STATE3 0x00211b8c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG 0x00211b90 /* SCD 12 Misc Config Register */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE0 0x00211b94 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE1 0x00211b98 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE2 0x00211b9c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE3 0x00211ba0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE4 0x00211ba4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE5 0x00211ba8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE6 0x00211bac /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE7 0x00211bb0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE8 0x00211bb4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE9 0x00211bb8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE10 0x00211bbc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE11 0x00211bc0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_RESERVE_COMP_STATE0 0x00211bc4 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE0 0x00211bc8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE1 0x00211bcc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE2 0x00211bd0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE3 0x00211bd4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_PACKET_COUNT 0x00211bd8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE0 0x00211bdc /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE1 0x00211be0 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_STATE0 0x00211be4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_STATE1 0x00211be8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_STATE2 0x00211bec /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_STATE3 0x00211bf0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_STATE4 0x00211bf4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_SCD_STATE5 0x00211bf8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD12_RESERVED_STATE0 0x00211bfc /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD12_RESERVED_STATE1 0x00211c00 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD12_RESERVED_STATE2 0x00211c04 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD12_RESERVED_STATE3 0x00211c08 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG 0x00211c0c /* SCD 13 Misc Config Register */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE0 0x00211c10 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE1 0x00211c14 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE2 0x00211c18 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE3 0x00211c1c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE4 0x00211c20 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE5 0x00211c24 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE6 0x00211c28 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE7 0x00211c2c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE8 0x00211c30 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE9 0x00211c34 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE10 0x00211c38 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE11 0x00211c3c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_RESERVE_COMP_STATE0 0x00211c40 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE0 0x00211c44 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE1 0x00211c48 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE2 0x00211c4c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE3 0x00211c50 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_PACKET_COUNT 0x00211c54 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE0 0x00211c58 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE1 0x00211c5c /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_STATE0 0x00211c60 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_STATE1 0x00211c64 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_STATE2 0x00211c68 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_STATE3 0x00211c6c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_STATE4 0x00211c70 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_SCD_STATE5 0x00211c74 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD13_RESERVED_STATE0 0x00211c78 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD13_RESERVED_STATE1 0x00211c7c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD13_RESERVED_STATE2 0x00211c80 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD13_RESERVED_STATE3 0x00211c84 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG 0x00211c88 /* SCD 14 Misc Config Register */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE0 0x00211c8c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE1 0x00211c90 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE2 0x00211c94 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE3 0x00211c98 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE4 0x00211c9c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE5 0x00211ca0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE6 0x00211ca4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE7 0x00211ca8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE8 0x00211cac /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE9 0x00211cb0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE10 0x00211cb4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE11 0x00211cb8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_RESERVE_COMP_STATE0 0x00211cbc /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE0 0x00211cc0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE1 0x00211cc4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE2 0x00211cc8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE3 0x00211ccc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_PACKET_COUNT 0x00211cd0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE0 0x00211cd4 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE1 0x00211cd8 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_STATE0 0x00211cdc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_STATE1 0x00211ce0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_STATE2 0x00211ce4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_STATE3 0x00211ce8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_STATE4 0x00211cec /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_SCD_STATE5 0x00211cf0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD14_RESERVED_STATE0 0x00211cf4 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD14_RESERVED_STATE1 0x00211cf8 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD14_RESERVED_STATE2 0x00211cfc /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD14_RESERVED_STATE3 0x00211d00 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG 0x00211d04 /* SCD 15 Misc Config Register */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE0 0x00211d08 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE1 0x00211d0c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE2 0x00211d10 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE3 0x00211d14 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE4 0x00211d18 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE5 0x00211d1c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE6 0x00211d20 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE7 0x00211d24 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE8 0x00211d28 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE9 0x00211d2c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE10 0x00211d30 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE11 0x00211d34 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_RESERVE_COMP_STATE0 0x00211d38 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE0 0x00211d3c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE1 0x00211d40 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE2 0x00211d44 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE3 0x00211d48 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_PACKET_COUNT 0x00211d4c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE0 0x00211d50 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE1 0x00211d54 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_STATE0 0x00211d58 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_STATE1 0x00211d5c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_STATE2 0x00211d60 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_STATE3 0x00211d64 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_STATE4 0x00211d68 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_SCD_STATE5 0x00211d6c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD15_RESERVED_STATE0 0x00211d70 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD15_RESERVED_STATE1 0x00211d74 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD15_RESERVED_STATE2 0x00211d78 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD15_RESERVED_STATE3 0x00211d7c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG 0x00211d80 /* SCD 16 Misc Config Register */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE0 0x00211d84 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE1 0x00211d88 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE2 0x00211d8c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE3 0x00211d90 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE4 0x00211d94 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE5 0x00211d98 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE6 0x00211d9c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE7 0x00211da0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE8 0x00211da4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE9 0x00211da8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE10 0x00211dac /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE11 0x00211db0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_RESERVE_COMP_STATE0 0x00211db4 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE0 0x00211db8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE1 0x00211dbc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE2 0x00211dc0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE3 0x00211dc4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_PACKET_COUNT 0x00211dc8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE0 0x00211dcc /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE1 0x00211dd0 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_STATE0 0x00211dd4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_STATE1 0x00211dd8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_STATE2 0x00211ddc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_STATE3 0x00211de0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_STATE4 0x00211de4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_SCD_STATE5 0x00211de8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD16_RESERVED_STATE0 0x00211dec /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD16_RESERVED_STATE1 0x00211df0 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD16_RESERVED_STATE2 0x00211df4 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD16_RESERVED_STATE3 0x00211df8 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG 0x00211dfc /* SCD 17 Misc Config Register */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE0 0x00211e00 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE1 0x00211e04 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE2 0x00211e08 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE3 0x00211e0c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE4 0x00211e10 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE5 0x00211e14 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE6 0x00211e18 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE7 0x00211e1c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE8 0x00211e20 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE9 0x00211e24 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE10 0x00211e28 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE11 0x00211e2c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_RESERVE_COMP_STATE0 0x00211e30 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE0 0x00211e34 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE1 0x00211e38 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE2 0x00211e3c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE3 0x00211e40 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_PACKET_COUNT 0x00211e44 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE0 0x00211e48 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE1 0x00211e4c /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_STATE0 0x00211e50 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_STATE1 0x00211e54 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_STATE2 0x00211e58 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_STATE3 0x00211e5c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_STATE4 0x00211e60 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_SCD_STATE5 0x00211e64 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD17_RESERVED_STATE0 0x00211e68 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD17_RESERVED_STATE1 0x00211e6c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD17_RESERVED_STATE2 0x00211e70 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD17_RESERVED_STATE3 0x00211e74 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG 0x00211e78 /* SCD 18 Misc Config Register */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE0 0x00211e7c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE1 0x00211e80 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE2 0x00211e84 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE3 0x00211e88 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE4 0x00211e8c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE5 0x00211e90 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE6 0x00211e94 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE7 0x00211e98 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE8 0x00211e9c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE9 0x00211ea0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE10 0x00211ea4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE11 0x00211ea8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_RESERVE_COMP_STATE0 0x00211eac /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE0 0x00211eb0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE1 0x00211eb4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE2 0x00211eb8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE3 0x00211ebc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_PACKET_COUNT 0x00211ec0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE0 0x00211ec4 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE1 0x00211ec8 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_STATE0 0x00211ecc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_STATE1 0x00211ed0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_STATE2 0x00211ed4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_STATE3 0x00211ed8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_STATE4 0x00211edc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_SCD_STATE5 0x00211ee0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD18_RESERVED_STATE0 0x00211ee4 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD18_RESERVED_STATE1 0x00211ee8 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD18_RESERVED_STATE2 0x00211eec /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD18_RESERVED_STATE3 0x00211ef0 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG 0x00211ef4 /* SCD 19 Misc Config Register */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE0 0x00211ef8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE1 0x00211efc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE2 0x00211f00 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE3 0x00211f04 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE4 0x00211f08 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE5 0x00211f0c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE6 0x00211f10 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE7 0x00211f14 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE8 0x00211f18 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE9 0x00211f1c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE10 0x00211f20 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE11 0x00211f24 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_RESERVE_COMP_STATE0 0x00211f28 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE0 0x00211f2c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE1 0x00211f30 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE2 0x00211f34 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE3 0x00211f38 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_PACKET_COUNT 0x00211f3c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE0 0x00211f40 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE1 0x00211f44 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_STATE0 0x00211f48 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_STATE1 0x00211f4c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_STATE2 0x00211f50 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_STATE3 0x00211f54 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_STATE4 0x00211f58 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_SCD_STATE5 0x00211f5c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD19_RESERVED_STATE0 0x00211f60 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD19_RESERVED_STATE1 0x00211f64 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD19_RESERVED_STATE2 0x00211f68 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD19_RESERVED_STATE3 0x00211f6c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG 0x00211f70 /* SCD 20 Misc Config Register */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE0 0x00211f74 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE1 0x00211f78 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE2 0x00211f7c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE3 0x00211f80 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE4 0x00211f84 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE5 0x00211f88 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE6 0x00211f8c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE7 0x00211f90 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE8 0x00211f94 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE9 0x00211f98 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE10 0x00211f9c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE11 0x00211fa0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_RESERVE_COMP_STATE0 0x00211fa4 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE0 0x00211fa8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE1 0x00211fac /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE2 0x00211fb0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE3 0x00211fb4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_PACKET_COUNT 0x00211fb8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE0 0x00211fbc /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE1 0x00211fc0 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_STATE0 0x00211fc4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_STATE1 0x00211fc8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_STATE2 0x00211fcc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_STATE3 0x00211fd0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_STATE4 0x00211fd4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_SCD_STATE5 0x00211fd8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD20_RESERVED_STATE0 0x00211fdc /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD20_RESERVED_STATE1 0x00211fe0 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD20_RESERVED_STATE2 0x00211fe4 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD20_RESERVED_STATE3 0x00211fe8 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG 0x00211fec /* SCD 21 Misc Config Register */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE0 0x00211ff0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE1 0x00211ff4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE2 0x00211ff8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE3 0x00211ffc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE4 0x00212000 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE5 0x00212004 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE6 0x00212008 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE7 0x0021200c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE8 0x00212010 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE9 0x00212014 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE10 0x00212018 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE11 0x0021201c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_RESERVE_COMP_STATE0 0x00212020 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE0 0x00212024 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE1 0x00212028 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE2 0x0021202c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE3 0x00212030 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_PACKET_COUNT 0x00212034 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE0 0x00212038 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE1 0x0021203c /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_STATE0 0x00212040 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_STATE1 0x00212044 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_STATE2 0x00212048 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_STATE3 0x0021204c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_STATE4 0x00212050 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_SCD_STATE5 0x00212054 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD21_RESERVED_STATE0 0x00212058 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD21_RESERVED_STATE1 0x0021205c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD21_RESERVED_STATE2 0x00212060 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD21_RESERVED_STATE3 0x00212064 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG 0x00212068 /* SCD 22 Misc Config Register */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE0 0x0021206c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE1 0x00212070 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE2 0x00212074 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE3 0x00212078 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE4 0x0021207c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE5 0x00212080 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE6 0x00212084 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE7 0x00212088 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE8 0x0021208c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE9 0x00212090 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE10 0x00212094 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE11 0x00212098 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_RESERVE_COMP_STATE0 0x0021209c /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE0 0x002120a0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE1 0x002120a4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE2 0x002120a8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE3 0x002120ac /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_PACKET_COUNT 0x002120b0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE0 0x002120b4 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE1 0x002120b8 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_STATE0 0x002120bc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_STATE1 0x002120c0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_STATE2 0x002120c4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_STATE3 0x002120c8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_STATE4 0x002120cc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_SCD_STATE5 0x002120d0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD22_RESERVED_STATE0 0x002120d4 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD22_RESERVED_STATE1 0x002120d8 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD22_RESERVED_STATE2 0x002120dc /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD22_RESERVED_STATE3 0x002120e0 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG 0x002120e4 /* SCD 23 Misc Config Register */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE0 0x002120e8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE1 0x002120ec /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE2 0x002120f0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE3 0x002120f4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE4 0x002120f8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE5 0x002120fc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE6 0x00212100 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE7 0x00212104 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE8 0x00212108 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE9 0x0021210c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE10 0x00212110 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE11 0x00212114 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_RESERVE_COMP_STATE0 0x00212118 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE0 0x0021211c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE1 0x00212120 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE2 0x00212124 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE3 0x00212128 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_PACKET_COUNT 0x0021212c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE0 0x00212130 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE1 0x00212134 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_STATE0 0x00212138 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_STATE1 0x0021213c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_STATE2 0x00212140 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_STATE3 0x00212144 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_STATE4 0x00212148 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_SCD_STATE5 0x0021214c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD23_RESERVED_STATE0 0x00212150 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD23_RESERVED_STATE1 0x00212154 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD23_RESERVED_STATE2 0x00212158 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD23_RESERVED_STATE3 0x0021215c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG 0x00212160 /* SCD 24 Misc Config Register */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE0 0x00212164 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE1 0x00212168 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE2 0x0021216c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE3 0x00212170 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE4 0x00212174 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE5 0x00212178 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE6 0x0021217c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE7 0x00212180 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE8 0x00212184 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE9 0x00212188 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE10 0x0021218c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE11 0x00212190 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_RESERVE_COMP_STATE0 0x00212194 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE0 0x00212198 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE1 0x0021219c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE2 0x002121a0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE3 0x002121a4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_PACKET_COUNT 0x002121a8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE0 0x002121ac /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE1 0x002121b0 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_STATE0 0x002121b4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_STATE1 0x002121b8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_STATE2 0x002121bc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_STATE3 0x002121c0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_STATE4 0x002121c4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_SCD_STATE5 0x002121c8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD24_RESERVED_STATE0 0x002121cc /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD24_RESERVED_STATE1 0x002121d0 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD24_RESERVED_STATE2 0x002121d4 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD24_RESERVED_STATE3 0x002121d8 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG 0x002121dc /* SCD 25 Misc Config Register */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE0 0x002121e0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE1 0x002121e4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE2 0x002121e8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE3 0x002121ec /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE4 0x002121f0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE5 0x002121f4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE6 0x002121f8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE7 0x002121fc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE8 0x00212200 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE9 0x00212204 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE10 0x00212208 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE11 0x0021220c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_RESERVE_COMP_STATE0 0x00212210 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE0 0x00212214 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE1 0x00212218 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE2 0x0021221c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE3 0x00212220 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_PACKET_COUNT 0x00212224 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE0 0x00212228 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE1 0x0021222c /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_STATE0 0x00212230 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_STATE1 0x00212234 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_STATE2 0x00212238 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_STATE3 0x0021223c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_STATE4 0x00212240 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_SCD_STATE5 0x00212244 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD25_RESERVED_STATE0 0x00212248 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD25_RESERVED_STATE1 0x0021224c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD25_RESERVED_STATE2 0x00212250 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD25_RESERVED_STATE3 0x00212254 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG 0x00212258 /* SCD 26 Misc Config Register */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE0 0x0021225c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE1 0x00212260 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE2 0x00212264 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE3 0x00212268 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE4 0x0021226c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE5 0x00212270 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE6 0x00212274 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE7 0x00212278 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE8 0x0021227c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE9 0x00212280 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE10 0x00212284 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE11 0x00212288 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_RESERVE_COMP_STATE0 0x0021228c /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE0 0x00212290 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE1 0x00212294 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE2 0x00212298 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE3 0x0021229c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_PACKET_COUNT 0x002122a0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE0 0x002122a4 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE1 0x002122a8 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_STATE0 0x002122ac /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_STATE1 0x002122b0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_STATE2 0x002122b4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_STATE3 0x002122b8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_STATE4 0x002122bc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_SCD_STATE5 0x002122c0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD26_RESERVED_STATE0 0x002122c4 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD26_RESERVED_STATE1 0x002122c8 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD26_RESERVED_STATE2 0x002122cc /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD26_RESERVED_STATE3 0x002122d0 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG 0x002122d4 /* SCD 27 Misc Config Register */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE0 0x002122d8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE1 0x002122dc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE2 0x002122e0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE3 0x002122e4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE4 0x002122e8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE5 0x002122ec /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE6 0x002122f0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE7 0x002122f4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE8 0x002122f8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE9 0x002122fc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE10 0x00212300 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE11 0x00212304 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_RESERVE_COMP_STATE0 0x00212308 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE0 0x0021230c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE1 0x00212310 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE2 0x00212314 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE3 0x00212318 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_PACKET_COUNT 0x0021231c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE0 0x00212320 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE1 0x00212324 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_STATE0 0x00212328 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_STATE1 0x0021232c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_STATE2 0x00212330 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_STATE3 0x00212334 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_STATE4 0x00212338 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_SCD_STATE5 0x0021233c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD27_RESERVED_STATE0 0x00212340 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD27_RESERVED_STATE1 0x00212344 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD27_RESERVED_STATE2 0x00212348 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD27_RESERVED_STATE3 0x0021234c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG 0x00212350 /* SCD 28 Misc Config Register */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE0 0x00212354 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE1 0x00212358 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE2 0x0021235c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE3 0x00212360 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE4 0x00212364 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE5 0x00212368 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE6 0x0021236c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE7 0x00212370 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE8 0x00212374 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE9 0x00212378 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE10 0x0021237c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE11 0x00212380 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_RESERVE_COMP_STATE0 0x00212384 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE0 0x00212388 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE1 0x0021238c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE2 0x00212390 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE3 0x00212394 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_PACKET_COUNT 0x00212398 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE0 0x0021239c /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE1 0x002123a0 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_STATE0 0x002123a4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_STATE1 0x002123a8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_STATE2 0x002123ac /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_STATE3 0x002123b0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_STATE4 0x002123b4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_SCD_STATE5 0x002123b8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD28_RESERVED_STATE0 0x002123bc /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD28_RESERVED_STATE1 0x002123c0 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD28_RESERVED_STATE2 0x002123c4 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD28_RESERVED_STATE3 0x002123c8 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG 0x002123cc /* SCD 29 Misc Config Register */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE0 0x002123d0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE1 0x002123d4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE2 0x002123d8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE3 0x002123dc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE4 0x002123e0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE5 0x002123e4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE6 0x002123e8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE7 0x002123ec /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE8 0x002123f0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE9 0x002123f4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE10 0x002123f8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE11 0x002123fc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_RESERVE_COMP_STATE0 0x00212400 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE0 0x00212404 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE1 0x00212408 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE2 0x0021240c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE3 0x00212410 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_PACKET_COUNT 0x00212414 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE0 0x00212418 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE1 0x0021241c /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_STATE0 0x00212420 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_STATE1 0x00212424 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_STATE2 0x00212428 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_STATE3 0x0021242c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_STATE4 0x00212430 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_SCD_STATE5 0x00212434 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD29_RESERVED_STATE0 0x00212438 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD29_RESERVED_STATE1 0x0021243c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD29_RESERVED_STATE2 0x00212440 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD29_RESERVED_STATE3 0x00212444 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG 0x00212448 /* SCD 30 Misc Config Register */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE0 0x0021244c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE1 0x00212450 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE2 0x00212454 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE3 0x00212458 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE4 0x0021245c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE5 0x00212460 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE6 0x00212464 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE7 0x00212468 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE8 0x0021246c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE9 0x00212470 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE10 0x00212474 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE11 0x00212478 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_RESERVE_COMP_STATE0 0x0021247c /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE0 0x00212480 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE1 0x00212484 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE2 0x00212488 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE3 0x0021248c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_PACKET_COUNT 0x00212490 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE0 0x00212494 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE1 0x00212498 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_STATE0 0x0021249c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_STATE1 0x002124a0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_STATE2 0x002124a4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_STATE3 0x002124a8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_STATE4 0x002124ac /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_SCD_STATE5 0x002124b0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD30_RESERVED_STATE0 0x002124b4 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD30_RESERVED_STATE1 0x002124b8 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD30_RESERVED_STATE2 0x002124bc /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD30_RESERVED_STATE3 0x002124c0 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG 0x002124c4 /* SCD 31 Misc Config Register */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE0 0x002124c8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE1 0x002124cc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE2 0x002124d0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE3 0x002124d4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE4 0x002124d8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE5 0x002124dc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE6 0x002124e0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE7 0x002124e4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE8 0x002124e8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE9 0x002124ec /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE10 0x002124f0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE11 0x002124f4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_RESERVE_COMP_STATE0 0x002124f8 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE0 0x002124fc /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE1 0x00212500 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE2 0x00212504 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE3 0x00212508 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_PACKET_COUNT 0x0021250c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE0 0x00212510 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE1 0x00212514 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_STATE0 0x00212518 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_STATE1 0x0021251c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_STATE2 0x00212520 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_STATE3 0x00212524 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_STATE4 0x00212528 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_SCD_STATE5 0x0021252c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD31_RESERVED_STATE0 0x00212530 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD31_RESERVED_STATE1 0x00212534 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD31_RESERVED_STATE2 0x00212538 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD31_RESERVED_STATE3 0x0021253c /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG 0x00212540 /* SCD 32 Misc Config Register */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE0 0x00212544 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE1 0x00212548 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE2 0x0021254c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE3 0x00212550 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE4 0x00212554 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE5 0x00212558 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE6 0x0021255c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE7 0x00212560 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE8 0x00212564 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE9 0x00212568 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE10 0x0021256c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE11 0x00212570 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_RESERVE_COMP_STATE0 0x00212574 /* Reserved Comparator State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE0 0x00212578 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE1 0x0021257c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE2 0x00212580 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE3 0x00212584 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_PACKET_COUNT 0x00212588 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE0 0x0021258c /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE1 0x00212590 /* Reserved PES State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_STATE0 0x00212594 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_STATE1 0x00212598 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_STATE2 0x0021259c /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_STATE3 0x002125a0 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_STATE4 0x002125a4 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_SCD_STATE5 0x002125a8 /* SCD State Register */ #define BCHP_XPT_RAVE_SCD32_RESERVED_STATE0 0x002125ac /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD32_RESERVED_STATE1 0x002125b0 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD32_RESERVED_STATE2 0x002125b4 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_SCD32_RESERVED_STATE3 0x002125b8 /* SCD Reserved State Register */ #define BCHP_XPT_RAVE_XPU_CONFIG 0x00213000 /* XPU TEST ENABLE REGISTER */ #define BCHP_XPT_RAVE_XPU_TEST_CONTROL 0x00213004 /* XPU TEST CONTROL REGISTER */ #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO 0x00213008 /* XPU TEST CONTROL EXT IO */ #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0 0x0021300c /* XPU TEST OBSERVE REGISTER */ #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1 0x00213010 /* XPU TEST OBSERVE REGISTER */ #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO 0x00213014 /* XPU TEST OBSERVE EXT IO REGISTER */ #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL 0x00213018 /* RAVE Diagnostics Control Register */ #define BCHP_XPT_RAVE_STOP_PACKET_COUNT_VALUE 0x0021301c /* Stop Packet Count Value */ #define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL 0x00213020 /* AVS SCV Filter mode */ #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3 0x00213024 /* AVS SCV Filter value 0 to 3 */ #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7 0x00213028 /* AVS SCV Filter value 4 to 7 */ #define BCHP_XPT_RAVE_AV_STATUS 0x00213040 /* RAVE Status */ #define BCHP_XPT_RAVE_PACKET_COUNT 0x00213044 /* RAVE input packet counter */ #define BCHP_XPT_RAVE_DATA_START_ADDR_A 0x00213048 /* Pkt and HWA data buffer A base addresses */ #define BCHP_XPT_RAVE_DATA_START_ADDR_B 0x0021304c /* Pkt and HWA data buffer B base addresses */ #define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE 0x00213050 /* Watchdog Timer Timeout Value */ #define BCHP_XPT_RAVE_MISC_CONTROL 0x00213058 /* Miscellaneous Control */ #define BCHP_XPT_RAVE_BASE_ADDRESSES 0x0021305c /* Record and SCD Base Addresses */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS 0x00213064 /* Context Hold Status and Clear */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS 0x00213060 /* Band Hold Status and Clear */ #define BCHP_XPT_RAVE_FW_WATERMARK 0x00213068 /* Firmware throughput watermark */ #define BCHP_XPT_RAVE_HW_WATCHDOG 0x0021306c /* Hardware Watchdog Counter */ #define BCHP_XPT_RAVE_MISC_CONTROL2 0x00213070 /* Miscellaneous Control 2 */ #define BCHP_XPT_RAVE_RC0_SP_CONTROL 0x00213080 /* Seamless Pause Control */ #define BCHP_XPT_RAVE_RC1_SP_CONTROL 0x00213084 /* Seamless Pause Control */ #define BCHP_XPT_RAVE_RC2_SP_CONTROL 0x00213088 /* Seamless Pause Control */ #define BCHP_XPT_RAVE_RC3_SP_CONTROL 0x0021308c /* Seamless Pause Control */ #define BCHP_XPT_RAVE_RC4_SP_CONTROL 0x00213090 /* Seamless Pause Control */ #define BCHP_XPT_RAVE_RC5_SP_CONTROL 0x00213094 /* Seamless Pause Control */ #define BCHP_XPT_RAVE_RC6_SP_CONTROL 0x00213098 /* Seamless Pause Control */ #define BCHP_XPT_RAVE_RC7_SP_CONTROL 0x0021309c /* Seamless Pause Control */ #define BCHP_XPT_RAVE_RC8_SP_CONTROL 0x002130a0 /* Seamless Pause Control */ #define BCHP_XPT_RAVE_AV_STATUS2 0x002130a4 /* RAVE Status */ #define BCHP_XPT_RAVE_TM_DMEM 0x002130b0 /* TM Control */ #define BCHP_XPT_RAVE_TM_IMEM 0x002130b4 /* TM Control */ #define BCHP_XPT_RAVE_TM_POINTER_RAM 0x002130b8 /* TM Control */ #define BCHP_XPT_RAVE_TM_MUX_BUFFER 0x002130bc /* TM Control */ #define BCHP_XPT_RAVE_TM_CX_TABLE 0x002130c0 /* TM Control */ #define BCHP_XPT_RAVE_TM_CX_TABLE_HI 0x002130c4 /* TM Control */ #define BCHP_XPT_RAVE_TM_SMEM 0x002130c8 /* TM Control */ #define BCHP_XPT_RAVE_INT_CX0 0x00213100 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX1 0x00213104 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX2 0x00213108 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX3 0x0021310c /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX4 0x00213110 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX5 0x00213114 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX6 0x00213118 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX7 0x0021311c /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX8 0x00213120 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX9 0x00213124 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX10 0x00213128 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX11 0x0021312c /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX12 0x00213130 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX13 0x00213134 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX14 0x00213138 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX15 0x0021313c /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX16 0x00213140 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX17 0x00213144 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX18 0x00213148 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX19 0x0021314c /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX20 0x00213150 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX21 0x00213154 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX22 0x00213158 /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_CX23 0x0021315c /* Context Interrupts */ #define BCHP_XPT_RAVE_INT_MISC 0x00213160 /* Miscellaneous Interrupts */ #define BCHP_XPT_RAVE_EMM_TID_MODE 0x00216000 /* TPIT EMM_TID_MODE Register (NDS only) */ #define BCHP_XPT_RAVE_EMM_DATA_ID_1 0x00216004 /* TPIT EMM_DATA_ID_1 Register (NDS only) */ #define BCHP_XPT_RAVE_EMM_DATA_ID_2 0x00216008 /* TPIT EMM_DATA_ID_2 Register (NDS only) */ #define BCHP_XPT_RAVE_EMM_DATA_ID_3 0x0021600c /* TPIT EMM_DATA_ID_3 Register (NDS only) */ #define BCHP_XPT_RAVE_EMM_MASK_ID_1 0x00216010 /* TPIT EMM_MASK_ID_1 Register (NDS only) */ #define BCHP_XPT_RAVE_EMM_MASK_ID_2 0x00216014 /* TPIT EMM_MASK_ID_2 Register (NDS only) */ #define BCHP_XPT_RAVE_EMM_MASK_ID_3 0x00216018 /* TPIT EMM_MASK_ID_3 Register (NDS only) */ #define BCHP_XPT_RAVE_TPIT_TIME_TICK 0x00216020 /* TPIT Time Tick Register */ #define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT 0x00216024 /* TPIT Time Packet Timeout Register */ #define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT 0x00216028 /* TPIT Time Event Timeout Register */ #define BCHP_XPT_RAVE_TPIT0_CTRL1 0x0021a300 /* TPIT 0 Control Register 1 */ #define BCHP_XPT_RAVE_TPIT0_COR1 0x0021a304 /* TPIT 0 Corrupt Register */ #define BCHP_XPT_RAVE_TPIT0_TID 0x0021a308 /* TPIT TID Register */ #define BCHP_XPT_RAVE_TPIT0_TID2 0x0021a30c /* TPIT TID Register 2 */ #define BCHP_XPT_RAVE_TPIT0_STATE0 0x0021a310 /* TPIT 0 State Register */ #define BCHP_XPT_RAVE_TPIT0_STATE1 0x0021a314 /* TPIT 0 State Register */ #define BCHP_XPT_RAVE_TPIT0_STATE2 0x0021a318 /* TPIT 0 State Register */ #define BCHP_XPT_RAVE_TPIT0_STATE2a 0x0021a31c /* TPIT 0 State Register */ #define BCHP_XPT_RAVE_TPIT0_STATE2b 0x0021a320 /* TPIT 0 State Register */ #define BCHP_XPT_RAVE_TPIT0_STATE2c 0x0021a324 /* TPIT 0 State Register */ #define BCHP_XPT_RAVE_TPIT0_STATE2d 0x0021a328 /* TPIT 0 State Register */ #define BCHP_XPT_RAVE_TPIT0_STATE3 0x0021a32c /* TPIT 0 State Register */ #define BCHP_XPT_RAVE_TPIT0_STATE4 0x0021a330 /* TPIT 0 State Register */ #define BCHP_XPT_RAVE_TPIT0_STATE5 0x0021a334 /* TPIT 0 State Register */ #define BCHP_XPT_RAVE_TPIT0_STATE6 0x0021a338 /* TPIT 0 State Register */ #define BCHP_XPT_RAVE_TPIT0_STATE7 0x0021a33c /* TPIT 0 State Register */ #define BCHP_XPT_RAVE_TPIT0_STATE8 0x0021a340 /* TPIT 0 State Register */ #define BCHP_XPT_RAVE_TPIT0_STATE9 0x0021a344 /* TPIT 0 State Register */ #define BCHP_XPT_RAVE_TPIT1_CTRL1 0x0021a348 /* TPIT 1 Control Register 1 */ #define BCHP_XPT_RAVE_TPIT1_COR1 0x0021a34c /* TPIT 1 Corrupt Register */ #define BCHP_XPT_RAVE_TPIT1_TID 0x0021a350 /* TPIT TID Register */ #define BCHP_XPT_RAVE_TPIT1_TID2 0x0021a354 /* TPIT TID Register 2 */ #define BCHP_XPT_RAVE_TPIT1_STATE0 0x0021a358 /* TPIT 1 State Register */ #define BCHP_XPT_RAVE_TPIT1_STATE1 0x0021a35c /* TPIT 1 State Register */ #define BCHP_XPT_RAVE_TPIT1_STATE2 0x0021a360 /* TPIT 1 State Register */ #define BCHP_XPT_RAVE_TPIT1_STATE2a 0x0021a364 /* TPIT 1 State Register */ #define BCHP_XPT_RAVE_TPIT1_STATE2b 0x0021a368 /* TPIT 1 State Register */ #define BCHP_XPT_RAVE_TPIT1_STATE2c 0x0021a36c /* TPIT 1 State Register */ #define BCHP_XPT_RAVE_TPIT1_STATE2d 0x0021a370 /* TPIT 1 State Register */ #define BCHP_XPT_RAVE_TPIT1_STATE3 0x0021a374 /* TPIT 1 State Register */ #define BCHP_XPT_RAVE_TPIT1_STATE4 0x0021a378 /* TPIT 1 State Register */ #define BCHP_XPT_RAVE_TPIT1_STATE5 0x0021a37c /* TPIT 1 State Register */ #define BCHP_XPT_RAVE_TPIT1_STATE6 0x0021a380 /* TPIT 1 State Register */ #define BCHP_XPT_RAVE_TPIT1_STATE7 0x0021a384 /* TPIT 1 State Register */ #define BCHP_XPT_RAVE_TPIT1_STATE8 0x0021a388 /* TPIT 1 State Register */ #define BCHP_XPT_RAVE_TPIT1_STATE9 0x0021a38c /* TPIT 1 State Register */ #define BCHP_XPT_RAVE_TPIT2_CTRL1 0x0021a390 /* TPIT 2 Control Register 1 */ #define BCHP_XPT_RAVE_TPIT2_COR1 0x0021a394 /* TPIT 2 Corrupt Register */ #define BCHP_XPT_RAVE_TPIT2_TID 0x0021a398 /* TPIT TID Register */ #define BCHP_XPT_RAVE_TPIT2_TID2 0x0021a39c /* TPIT TID Register 2 */ #define BCHP_XPT_RAVE_TPIT2_STATE0 0x0021a3a0 /* TPIT 2 State Register */ #define BCHP_XPT_RAVE_TPIT2_STATE1 0x0021a3a4 /* TPIT 2 State Register */ #define BCHP_XPT_RAVE_TPIT2_STATE2 0x0021a3a8 /* TPIT 2 State Register */ #define BCHP_XPT_RAVE_TPIT2_STATE2a 0x0021a3ac /* TPIT 2 State Register */ #define BCHP_XPT_RAVE_TPIT2_STATE2b 0x0021a3b0 /* TPIT 2 State Register */ #define BCHP_XPT_RAVE_TPIT2_STATE2c 0x0021a3b4 /* TPIT 2 State Register */ #define BCHP_XPT_RAVE_TPIT2_STATE2d 0x0021a3b8 /* TPIT 2 State Register */ #define BCHP_XPT_RAVE_TPIT2_STATE3 0x0021a3bc /* TPIT 2 State Register */ #define BCHP_XPT_RAVE_TPIT2_STATE4 0x0021a3c0 /* TPIT 2 State Register */ #define BCHP_XPT_RAVE_TPIT2_STATE5 0x0021a3c4 /* TPIT 2 State Register */ #define BCHP_XPT_RAVE_TPIT2_STATE6 0x0021a3c8 /* TPIT 2 State Register */ #define BCHP_XPT_RAVE_TPIT2_STATE7 0x0021a3cc /* TPIT 2 State Register */ #define BCHP_XPT_RAVE_TPIT2_STATE8 0x0021a3d0 /* TPIT 2 State Register */ #define BCHP_XPT_RAVE_TPIT2_STATE9 0x0021a3d4 /* TPIT 2 State Register */ #define BCHP_XPT_RAVE_TPIT3_CTRL1 0x0021a3d8 /* TPIT 3 Control Register 1 */ #define BCHP_XPT_RAVE_TPIT3_COR1 0x0021a3dc /* TPIT 3 Corrupt Register */ #define BCHP_XPT_RAVE_TPIT3_TID 0x0021a3e0 /* TPIT TID Register */ #define BCHP_XPT_RAVE_TPIT3_TID2 0x0021a3e4 /* TPIT TID Register 2 */ #define BCHP_XPT_RAVE_TPIT3_STATE0 0x0021a3e8 /* TPIT 3 State Register */ #define BCHP_XPT_RAVE_TPIT3_STATE1 0x0021a3ec /* TPIT 3 State Register */ #define BCHP_XPT_RAVE_TPIT3_STATE2 0x0021a3f0 /* TPIT 3 State Register */ #define BCHP_XPT_RAVE_TPIT3_STATE2a 0x0021a3f4 /* TPIT 3 State Register */ #define BCHP_XPT_RAVE_TPIT3_STATE2b 0x0021a3f8 /* TPIT 3 State Register */ #define BCHP_XPT_RAVE_TPIT3_STATE2c 0x0021a3fc /* TPIT 3 State Register */ #define BCHP_XPT_RAVE_TPIT3_STATE2d 0x0021a400 /* TPIT 3 State Register */ #define BCHP_XPT_RAVE_TPIT3_STATE3 0x0021a404 /* TPIT 3 State Register */ #define BCHP_XPT_RAVE_TPIT3_STATE4 0x0021a408 /* TPIT 3 State Register */ #define BCHP_XPT_RAVE_TPIT3_STATE5 0x0021a40c /* TPIT 3 State Register */ #define BCHP_XPT_RAVE_TPIT3_STATE6 0x0021a410 /* TPIT 3 State Register */ #define BCHP_XPT_RAVE_TPIT3_STATE7 0x0021a414 /* TPIT 3 State Register */ #define BCHP_XPT_RAVE_TPIT3_STATE8 0x0021a418 /* TPIT 3 State Register */ #define BCHP_XPT_RAVE_TPIT3_STATE9 0x0021a41c /* TPIT 3 State Register */ #define BCHP_XPT_RAVE_TPIT4_CTRL1 0x0021a420 /* TPIT 4 Control Register 1 */ #define BCHP_XPT_RAVE_TPIT4_COR1 0x0021a424 /* TPIT 4 Corrupt Register */ #define BCHP_XPT_RAVE_TPIT4_TID 0x0021a428 /* TPIT TID Register */ #define BCHP_XPT_RAVE_TPIT4_TID2 0x0021a42c /* TPIT TID Register 2 */ #define BCHP_XPT_RAVE_TPIT4_STATE0 0x0021a430 /* TPIT 4 State Register */ #define BCHP_XPT_RAVE_TPIT4_STATE1 0x0021a434 /* TPIT 4 State Register */ #define BCHP_XPT_RAVE_TPIT4_STATE2 0x0021a438 /* TPIT 4 State Register */ #define BCHP_XPT_RAVE_TPIT4_STATE2a 0x0021a43c /* TPIT 4 State Register */ #define BCHP_XPT_RAVE_TPIT4_STATE2b 0x0021a440 /* TPIT 4 State Register */ #define BCHP_XPT_RAVE_TPIT4_STATE2c 0x0021a444 /* TPIT 4 State Register */ #define BCHP_XPT_RAVE_TPIT4_STATE2d 0x0021a448 /* TPIT 4 State Register */ #define BCHP_XPT_RAVE_TPIT4_STATE3 0x0021a44c /* TPIT 4 State Register */ #define BCHP_XPT_RAVE_TPIT4_STATE4 0x0021a450 /* TPIT 4 State Register */ #define BCHP_XPT_RAVE_TPIT4_STATE5 0x0021a454 /* TPIT 4 State Register */ #define BCHP_XPT_RAVE_TPIT4_STATE6 0x0021a458 /* TPIT 4 State Register */ #define BCHP_XPT_RAVE_TPIT4_STATE7 0x0021a45c /* TPIT 4 State Register */ #define BCHP_XPT_RAVE_TPIT4_STATE8 0x0021a460 /* TPIT 4 State Register */ #define BCHP_XPT_RAVE_TPIT4_STATE9 0x0021a464 /* TPIT 4 State Register */ #define BCHP_XPT_RAVE_TPIT5_CTRL1 0x0021a468 /* TPIT 5 Control Register 1 */ #define BCHP_XPT_RAVE_TPIT5_COR1 0x0021a46c /* TPIT 5 Corrupt Register */ #define BCHP_XPT_RAVE_TPIT5_TID 0x0021a470 /* TPIT TID Register */ #define BCHP_XPT_RAVE_TPIT5_TID2 0x0021a474 /* TPIT TID Register 2 */ #define BCHP_XPT_RAVE_TPIT5_STATE0 0x0021a478 /* TPIT 5 State Register */ #define BCHP_XPT_RAVE_TPIT5_STATE1 0x0021a47c /* TPIT 5 State Register */ #define BCHP_XPT_RAVE_TPIT5_STATE2 0x0021a480 /* TPIT 5 State Register */ #define BCHP_XPT_RAVE_TPIT5_STATE2a 0x0021a484 /* TPIT 5 State Register */ #define BCHP_XPT_RAVE_TPIT5_STATE2b 0x0021a488 /* TPIT 5 State Register */ #define BCHP_XPT_RAVE_TPIT5_STATE2c 0x0021a48c /* TPIT 5 State Register */ #define BCHP_XPT_RAVE_TPIT5_STATE2d 0x0021a490 /* TPIT 5 State Register */ #define BCHP_XPT_RAVE_TPIT5_STATE3 0x0021a494 /* TPIT 5 State Register */ #define BCHP_XPT_RAVE_TPIT5_STATE4 0x0021a498 /* TPIT 5 State Register */ #define BCHP_XPT_RAVE_TPIT5_STATE5 0x0021a49c /* TPIT 5 State Register */ #define BCHP_XPT_RAVE_TPIT5_STATE6 0x0021a4a0 /* TPIT 5 State Register */ #define BCHP_XPT_RAVE_TPIT5_STATE7 0x0021a4a4 /* TPIT 5 State Register */ #define BCHP_XPT_RAVE_TPIT5_STATE8 0x0021a4a8 /* TPIT 5 State Register */ #define BCHP_XPT_RAVE_TPIT5_STATE9 0x0021a4ac /* TPIT 5 State Register */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0 0x0021a4b0 /* TPIT State Register for Context 0 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1 0x0021a4b4 /* TPIT State Register for Context 1 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2 0x0021a4b8 /* TPIT State Register for Context 2 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3 0x0021a4bc /* TPIT State Register for Context 3 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4 0x0021a4c0 /* TPIT State Register for Context 4 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5 0x0021a4c4 /* TPIT State Register for Context 5 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6 0x0021a4c8 /* TPIT State Register for Context 6 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7 0x0021a4cc /* TPIT State Register for Context 7 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8 0x0021a4d0 /* TPIT State Register for Context 8 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9 0x0021a4d4 /* TPIT State Register for Context 9 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10 0x0021a4d8 /* TPIT State Register for Context 10 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11 0x0021a4dc /* TPIT State Register for Context 11 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12 0x0021a4e0 /* TPIT State Register for Context 12 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13 0x0021a4e4 /* TPIT State Register for Context 13 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14 0x0021a4e8 /* TPIT State Register for Context 14 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15 0x0021a4ec /* TPIT State Register for Context 15 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16 0x0021a4f0 /* TPIT State Register for Context 16 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17 0x0021a4f4 /* TPIT State Register for Context 17 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18 0x0021a4f8 /* TPIT State Register for Context 18 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19 0x0021a4fc /* TPIT State Register for Context 19 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20 0x0021a500 /* TPIT State Register for Context 20 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21 0x0021a504 /* TPIT State Register for Context 21 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22 0x0021a508 /* TPIT State Register for Context 22 */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23 0x0021a50c /* TPIT State Register for Context 23 */ /*************************************************************************** *CX0_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX0_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX0_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX0_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX0_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX0_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX0_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX0_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX0_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX0_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX0_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX0_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX0_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX0_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX0_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX0_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX0_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX0_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX0_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX0_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX0_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX0_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX0_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX0_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX0_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX0_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX0_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX0_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX0_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX0_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX0_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX0_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX0_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX0_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX0_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX0_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX0_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX0_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX0_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX0_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX0_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX0_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX0_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX0_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX0_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX0_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX0_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX0_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX0_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX0_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX0_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX0_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX0_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX0_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX0_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX0_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX0_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX0_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX0_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX0_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX0_REC_MISC_CONFIG - Context 0 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX0_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX0_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX0_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX0_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX0_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX0_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX0_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX0_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX0_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX0_REC_SCD_PIDS_AB - Context 0 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX0_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX0_REC_SCD_PIDS_CD - Context 0 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX0_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX0_REC_SCD_PIDS_EF - Context 0 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX0_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX0_REC_SCD_PIDS_GH - Context 0 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX0_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX0_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX0_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX0_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX0_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX0_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX0_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX0_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX0_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX0_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX0_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX0_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX0_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX0_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX0_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX0_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX0_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX0_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX0_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX0_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX0_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX0_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX0_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX0_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX0_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX0_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX0_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX0_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX0_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX0_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX0_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX0_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX0_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX0_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX0_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX0_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX0_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX0_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX0_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX0_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX0_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX0_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX0_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX0_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX0_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX0_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX0_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX0_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX0_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX0_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX0_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX0_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX0_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX0_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX0_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX0_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX0_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX0_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX0_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX0_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX0_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX0_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX0_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX0_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX0_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX0_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX0_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX0_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX0_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX0_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX0_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX0_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX0_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX0_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX0_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX0_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX0_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX0_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX0_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX0_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX0_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX0_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX0_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX0_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX0_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX0_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX0_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX0_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX0_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX0_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX0_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX0_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX0_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX0_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX0_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX0_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX0_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX0_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX0_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX0_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX0_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX0_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX0_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX0_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX0_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX0_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX0_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX0_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX0_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX0_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX0_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX0_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX0_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX0_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX0_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX0_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX0_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX0_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX0_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX0_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX0_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX0_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX0_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX0_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX0_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX0_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX0_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX0_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX0_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX0_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX0_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX0_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX0_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX0_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX0_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX0_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX0_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX0_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX0_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX0_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX0_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX0_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX0_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX0_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX0_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX0_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX0_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX0_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX0_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX0_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX0_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX0_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX0_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX0_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX0_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX0_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX0_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX0_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX0_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX0_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX0_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX0_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX0_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX0_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX0_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX0_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX0_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX0_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX0_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX0_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX0_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX0_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX0_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX0_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX0_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX1_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX1_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX1_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX1_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX1_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX1_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX1_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX1_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX1_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX1_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX1_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX1_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX1_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX1_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX1_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX1_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX1_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX1_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX1_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX1_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX1_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX1_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX1_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX1_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX1_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX1_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX1_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX1_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX1_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX1_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX1_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX1_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX1_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX1_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX1_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX1_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX1_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX1_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX1_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX1_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX1_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX1_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX1_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX1_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX1_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX1_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX1_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX1_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX1_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX1_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX1_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX1_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX1_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX1_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX1_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX1_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX1_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX1_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX1_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX1_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX1_REC_MISC_CONFIG - Context 1 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX1_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX1_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX1_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX1_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX1_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX1_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX1_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX1_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX1_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX1_REC_SCD_PIDS_AB - Context 1 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX1_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX1_REC_SCD_PIDS_CD - Context 1 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX1_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX1_REC_SCD_PIDS_EF - Context 1 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX1_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX1_REC_SCD_PIDS_GH - Context 1 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX1_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX1_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX1_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX1_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX1_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX1_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX1_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX1_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX1_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX1_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX1_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX1_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX1_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX1_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX1_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX1_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX1_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX1_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX1_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX1_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX1_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX1_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX1_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX1_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX1_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX1_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX1_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX1_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX1_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX1_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX1_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX1_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX1_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX1_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX1_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX1_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX1_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX1_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX1_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX1_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX1_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX1_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX1_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX1_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX1_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX1_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX1_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX1_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX1_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX1_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX1_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX1_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX1_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX1_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX1_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX1_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX1_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX1_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX1_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX1_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX1_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX1_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX1_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX1_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX1_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX1_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX1_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX1_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX1_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX1_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX1_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX1_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX1_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX1_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX1_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX1_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX1_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX1_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX1_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX1_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX1_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX1_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX1_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX1_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX1_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX1_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX1_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX1_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX1_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX1_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX1_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX1_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX1_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX1_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX1_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX1_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX1_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX1_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX1_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX1_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX1_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX1_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX1_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX1_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX1_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX1_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX1_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX1_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX1_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX1_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX1_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX1_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX1_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX1_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX1_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX1_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX1_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX1_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX1_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX1_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX1_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX1_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX1_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX1_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX1_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX1_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX1_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX1_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX1_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX1_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX1_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX1_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX1_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX1_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX1_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX1_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX1_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX1_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX1_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX1_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX1_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX1_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX1_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX1_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX1_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX1_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX1_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX1_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX1_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX1_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX1_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX1_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX1_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX1_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX1_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX1_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX1_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX1_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX1_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX1_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX1_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX1_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX1_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX1_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX1_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX1_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX1_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX1_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX1_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX1_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX1_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX1_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX1_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX1_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX1_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX2_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX2_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX2_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX2_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX2_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX2_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX2_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX2_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX2_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX2_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX2_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX2_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX2_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX2_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX2_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX2_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX2_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX2_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX2_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX2_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX2_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX2_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX2_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX2_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX2_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX2_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX2_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX2_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX2_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX2_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX2_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX2_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX2_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX2_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX2_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX2_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX2_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX2_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX2_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX2_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX2_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX2_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX2_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX2_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX2_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX2_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX2_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX2_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX2_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX2_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX2_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX2_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX2_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX2_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX2_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX2_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX2_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX2_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX2_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX2_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX2_REC_MISC_CONFIG - Context 2 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX2_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX2_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX2_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX2_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX2_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX2_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX2_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX2_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX2_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX2_REC_SCD_PIDS_AB - Context 2 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX2_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX2_REC_SCD_PIDS_CD - Context 2 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX2_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX2_REC_SCD_PIDS_EF - Context 2 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX2_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX2_REC_SCD_PIDS_GH - Context 2 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX2_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX2_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX2_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX2_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX2_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX2_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX2_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX2_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX2_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX2_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX2_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX2_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX2_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX2_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX2_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX2_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX2_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX2_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX2_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX2_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX2_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX2_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX2_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX2_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX2_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX2_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX2_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX2_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX2_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX2_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX2_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX2_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX2_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX2_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX2_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX2_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX2_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX2_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX2_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX2_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX2_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX2_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX2_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX2_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX2_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX2_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX2_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX2_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX2_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX2_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX2_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX2_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX2_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX2_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX2_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX2_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX2_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX2_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX2_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX2_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX2_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX2_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX2_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX2_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX2_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX2_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX2_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX2_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX2_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX2_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX2_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX2_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX2_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX2_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX2_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX2_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX2_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX2_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX2_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX2_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX2_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX2_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX2_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX2_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX2_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX2_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX2_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX2_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX2_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX2_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX2_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX2_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX2_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX2_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX2_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX2_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX2_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX2_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX2_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX2_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX2_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX2_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX2_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX2_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX2_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX2_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX2_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX2_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX2_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX2_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX2_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX2_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX2_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX2_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX2_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX2_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX2_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX2_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX2_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX2_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX2_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX2_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX2_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX2_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX2_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX2_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX2_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX2_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX2_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX2_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX2_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX2_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX2_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX2_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX2_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX2_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX2_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX2_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX2_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX2_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX2_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX2_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX2_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX2_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX2_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX2_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX2_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX2_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX2_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX2_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX2_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX2_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX2_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX2_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX2_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX2_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX2_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX2_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX2_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX2_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX2_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX2_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX2_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX2_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX2_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX2_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX2_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX2_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX2_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX2_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX2_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX2_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX2_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX2_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX2_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX3_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX3_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX3_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX3_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX3_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX3_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX3_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX3_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX3_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX3_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX3_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX3_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX3_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX3_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX3_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX3_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX3_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX3_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX3_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX3_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX3_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX3_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX3_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX3_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX3_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX3_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX3_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX3_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX3_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX3_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX3_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX3_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX3_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX3_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX3_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX3_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX3_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX3_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX3_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX3_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX3_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX3_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX3_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX3_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX3_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX3_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX3_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX3_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX3_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX3_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX3_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX3_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX3_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX3_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX3_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX3_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX3_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX3_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX3_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX3_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX3_REC_MISC_CONFIG - Context 3 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX3_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX3_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX3_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX3_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX3_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX3_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX3_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX3_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX3_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX3_REC_SCD_PIDS_AB - Context 3 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX3_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX3_REC_SCD_PIDS_CD - Context 3 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX3_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX3_REC_SCD_PIDS_EF - Context 3 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX3_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX3_REC_SCD_PIDS_GH - Context 3 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX3_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX3_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX3_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX3_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX3_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX3_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX3_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX3_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX3_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX3_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX3_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX3_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX3_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX3_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX3_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX3_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX3_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX3_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX3_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX3_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX3_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX3_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX3_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX3_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX3_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX3_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX3_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX3_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX3_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX3_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX3_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX3_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX3_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX3_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX3_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX3_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX3_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX3_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX3_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX3_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX3_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX3_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX3_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX3_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX3_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX3_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX3_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX3_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX3_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX3_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX3_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX3_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX3_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX3_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX3_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX3_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX3_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX3_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX3_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX3_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX3_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX3_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX3_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX3_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX3_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX3_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX3_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX3_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX3_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX3_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX3_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX3_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX3_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX3_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX3_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX3_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX3_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX3_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX3_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX3_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX3_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX3_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX3_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX3_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX3_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX3_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX3_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX3_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX3_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX3_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX3_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX3_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX3_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX3_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX3_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX3_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX3_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX3_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX3_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX3_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX3_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX3_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX3_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX3_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX3_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX3_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX3_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX3_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX3_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX3_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX3_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX3_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX3_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX3_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX3_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX3_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX3_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX3_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX3_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX3_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX3_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX3_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX3_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX3_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX3_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX3_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX3_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX3_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX3_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX3_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX3_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX3_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX3_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX3_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX3_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX3_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX3_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX3_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX3_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX3_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX3_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX3_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX3_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX3_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX3_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX3_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX3_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX3_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX3_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX3_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX3_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX3_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX3_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX3_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX3_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX3_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX3_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX3_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX3_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX3_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX3_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX3_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX3_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX3_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX3_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX3_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX3_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX3_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX3_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX3_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX3_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX3_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX3_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX3_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX3_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX4_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX4_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX4_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX4_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX4_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX4_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX4_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX4_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX4_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX4_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX4_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX4_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX4_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX4_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX4_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX4_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX4_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX4_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX4_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX4_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX4_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX4_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX4_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX4_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX4_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX4_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX4_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX4_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX4_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX4_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX4_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX4_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX4_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX4_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX4_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX4_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX4_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX4_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX4_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX4_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX4_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX4_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX4_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX4_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX4_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX4_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX4_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX4_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX4_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX4_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX4_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX4_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX4_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX4_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX4_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX4_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX4_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX4_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX4_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX4_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX4_REC_MISC_CONFIG - Context 4 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX4_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX4_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX4_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX4_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX4_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX4_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX4_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX4_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX4_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX4_REC_SCD_PIDS_AB - Context 4 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX4_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX4_REC_SCD_PIDS_CD - Context 4 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX4_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX4_REC_SCD_PIDS_EF - Context 4 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX4_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX4_REC_SCD_PIDS_GH - Context 4 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX4_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX4_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX4_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX4_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX4_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX4_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX4_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX4_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX4_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX4_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX4_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX4_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX4_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX4_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX4_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX4_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX4_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX4_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX4_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX4_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX4_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX4_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX4_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX4_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX4_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX4_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX4_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX4_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX4_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX4_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX4_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX4_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX4_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX4_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX4_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX4_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX4_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX4_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX4_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX4_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX4_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX4_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX4_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX4_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX4_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX4_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX4_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX4_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX4_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX4_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX4_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX4_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX4_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX4_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX4_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX4_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX4_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX4_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX4_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX4_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX4_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX4_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX4_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX4_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX4_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX4_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX4_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX4_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX4_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX4_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX4_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX4_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX4_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX4_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX4_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX4_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX4_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX4_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX4_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX4_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX4_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX4_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX4_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX4_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX4_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX4_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX4_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX4_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX4_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX4_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX4_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX4_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX4_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX4_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX4_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX4_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX4_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX4_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX4_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX4_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX4_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX4_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX4_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX4_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX4_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX4_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX4_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX4_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX4_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX4_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX4_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX4_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX4_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX4_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX4_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX4_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX4_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX4_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX4_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX4_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX4_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX4_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX4_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX4_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX4_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX4_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX4_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX4_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX4_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX4_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX4_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX4_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX4_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX4_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX4_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX4_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX4_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX4_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX4_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX4_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX4_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX4_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX4_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX4_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX4_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX4_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX4_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX4_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX4_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX4_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX4_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX4_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX4_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX4_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX4_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX4_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX4_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX4_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX4_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX4_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX4_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX4_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX4_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX4_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX4_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX4_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX4_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX4_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX4_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX4_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX4_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX4_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX4_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX4_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX4_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX5_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX5_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX5_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX5_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX5_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX5_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX5_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX5_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX5_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX5_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX5_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX5_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX5_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX5_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX5_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX5_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX5_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX5_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX5_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX5_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX5_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX5_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX5_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX5_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX5_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX5_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX5_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX5_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX5_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX5_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX5_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX5_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX5_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX5_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX5_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX5_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX5_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX5_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX5_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX5_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX5_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX5_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX5_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX5_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX5_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX5_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX5_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX5_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX5_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX5_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX5_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX5_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX5_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX5_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX5_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX5_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX5_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX5_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX5_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX5_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX5_REC_MISC_CONFIG - Context 5 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX5_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX5_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX5_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX5_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX5_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX5_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX5_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX5_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX5_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX5_REC_SCD_PIDS_AB - Context 5 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX5_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX5_REC_SCD_PIDS_CD - Context 5 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX5_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX5_REC_SCD_PIDS_EF - Context 5 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX5_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX5_REC_SCD_PIDS_GH - Context 5 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX5_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX5_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX5_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX5_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX5_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX5_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX5_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX5_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX5_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX5_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX5_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX5_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX5_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX5_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX5_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX5_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX5_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX5_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX5_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX5_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX5_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX5_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX5_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX5_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX5_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX5_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX5_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX5_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX5_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX5_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX5_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX5_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX5_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX5_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX5_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX5_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX5_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX5_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX5_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX5_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX5_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX5_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX5_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX5_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX5_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX5_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX5_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX5_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX5_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX5_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX5_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX5_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX5_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX5_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX5_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX5_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX5_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX5_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX5_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX5_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX5_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX5_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX5_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX5_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX5_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX5_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX5_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX5_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX5_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX5_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX5_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX5_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX5_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX5_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX5_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX5_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX5_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX5_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX5_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX5_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX5_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX5_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX5_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX5_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX5_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX5_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX5_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX5_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX5_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX5_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX5_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX5_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX5_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX5_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX5_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX5_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX5_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX5_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX5_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX5_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX5_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX5_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX5_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX5_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX5_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX5_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX5_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX5_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX5_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX5_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX5_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX5_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX5_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX5_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX5_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX5_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX5_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX5_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX5_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX5_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX5_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX5_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX5_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX5_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX5_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX5_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX5_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX5_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX5_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX5_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX5_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX5_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX5_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX5_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX5_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX5_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX5_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX5_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX5_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX5_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX5_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX5_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX5_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX5_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX5_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX5_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX5_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX5_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX5_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX5_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX5_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX5_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX5_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX5_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX5_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX5_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX5_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX5_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX5_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX5_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX5_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX5_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX5_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX5_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX5_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX5_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX5_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX5_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX5_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX5_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX5_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX5_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX5_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX5_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX5_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX6_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX6_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX6_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX6_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX6_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX6_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX6_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX6_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX6_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX6_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX6_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX6_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX6_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX6_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX6_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX6_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX6_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX6_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX6_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX6_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX6_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX6_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX6_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX6_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX6_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX6_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX6_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX6_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX6_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX6_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX6_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX6_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX6_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX6_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX6_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX6_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX6_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX6_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX6_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX6_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX6_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX6_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX6_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX6_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX6_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX6_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX6_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX6_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX6_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX6_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX6_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX6_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX6_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX6_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX6_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX6_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX6_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX6_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX6_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX6_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX6_REC_MISC_CONFIG - Context 6 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX6_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX6_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX6_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX6_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX6_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX6_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX6_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX6_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX6_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX6_REC_SCD_PIDS_AB - Context 6 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX6_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX6_REC_SCD_PIDS_CD - Context 6 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX6_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX6_REC_SCD_PIDS_EF - Context 6 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX6_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX6_REC_SCD_PIDS_GH - Context 6 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX6_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX6_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX6_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX6_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX6_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX6_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX6_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX6_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX6_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX6_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX6_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX6_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX6_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX6_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX6_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX6_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX6_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX6_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX6_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX6_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX6_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX6_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX6_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX6_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX6_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX6_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX6_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX6_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX6_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX6_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX6_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX6_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX6_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX6_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX6_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX6_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX6_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX6_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX6_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX6_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX6_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX6_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX6_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX6_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX6_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX6_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX6_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX6_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX6_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX6_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX6_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX6_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX6_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX6_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX6_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX6_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX6_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX6_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX6_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX6_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX6_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX6_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX6_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX6_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX6_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX6_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX6_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX6_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX6_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX6_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX6_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX6_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX6_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX6_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX6_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX6_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX6_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX6_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX6_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX6_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX6_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX6_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX6_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX6_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX6_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX6_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX6_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX6_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX6_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX6_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX6_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX6_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX6_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX6_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX6_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX6_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX6_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX6_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX6_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX6_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX6_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX6_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX6_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX6_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX6_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX6_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX6_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX6_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX6_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX6_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX6_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX6_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX6_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX6_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX6_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX6_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX6_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX6_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX6_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX6_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX6_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX6_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX6_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX6_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX6_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX6_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX6_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX6_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX6_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX6_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX6_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX6_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX6_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX6_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX6_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX6_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX6_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX6_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX6_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX6_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX6_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX6_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX6_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX6_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX6_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX6_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX6_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX6_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX6_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX6_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX6_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX6_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX6_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX6_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX6_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX6_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX6_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX6_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX6_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX6_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX6_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX6_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX6_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX6_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX6_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX6_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX6_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX6_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX6_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX6_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX6_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX6_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX6_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX6_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX6_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX7_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX7_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX7_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX7_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX7_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX7_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX7_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX7_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX7_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX7_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX7_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX7_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX7_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX7_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX7_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX7_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX7_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX7_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX7_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX7_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX7_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX7_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX7_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX7_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX7_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX7_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX7_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX7_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX7_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX7_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX7_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX7_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX7_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX7_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX7_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX7_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX7_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX7_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX7_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX7_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX7_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX7_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX7_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX7_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX7_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX7_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX7_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX7_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX7_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX7_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX7_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX7_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX7_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX7_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX7_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX7_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX7_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX7_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX7_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX7_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX7_REC_MISC_CONFIG - Context 7 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX7_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX7_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX7_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX7_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX7_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX7_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX7_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX7_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX7_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX7_REC_SCD_PIDS_AB - Context 7 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX7_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX7_REC_SCD_PIDS_CD - Context 7 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX7_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX7_REC_SCD_PIDS_EF - Context 7 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX7_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX7_REC_SCD_PIDS_GH - Context 7 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX7_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX7_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX7_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX7_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX7_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX7_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX7_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX7_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX7_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX7_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX7_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX7_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX7_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX7_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX7_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX7_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX7_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX7_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX7_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX7_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX7_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX7_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX7_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX7_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX7_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX7_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX7_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX7_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX7_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX7_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX7_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX7_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX7_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX7_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX7_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX7_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX7_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX7_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX7_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX7_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX7_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX7_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX7_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX7_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX7_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX7_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX7_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX7_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX7_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX7_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX7_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX7_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX7_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX7_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX7_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX7_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX7_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX7_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX7_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX7_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX7_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX7_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX7_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX7_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX7_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX7_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX7_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX7_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX7_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX7_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX7_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX7_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX7_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX7_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX7_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX7_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX7_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX7_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX7_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX7_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX7_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX7_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX7_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX7_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX7_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX7_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX7_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX7_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX7_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX7_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX7_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX7_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX7_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX7_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX7_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX7_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX7_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX7_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX7_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX7_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX7_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX7_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX7_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX7_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX7_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX7_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX7_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX7_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX7_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX7_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX7_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX7_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX7_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX7_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX7_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX7_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX7_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX7_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX7_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX7_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX7_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX7_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX7_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX7_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX7_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX7_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX7_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX7_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX7_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX7_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX7_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX7_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX7_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX7_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX7_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX7_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX7_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX7_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX7_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX7_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX7_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX7_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX7_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX7_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX7_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX7_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX7_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX7_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX7_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX7_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX7_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX7_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX7_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX7_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX7_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX7_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX7_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX7_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX7_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX7_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX7_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX7_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX7_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX7_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX7_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX7_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX7_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX7_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX7_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX7_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX7_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX7_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX7_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX7_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX7_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX8_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX8_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX8_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX8_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX8_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX8_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX8_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX8_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX8_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX8_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX8_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX8_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX8_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX8_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX8_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX8_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX8_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX8_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX8_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX8_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX8_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX8_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX8_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX8_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX8_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX8_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX8_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX8_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX8_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX8_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX8_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX8_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX8_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX8_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX8_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX8_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX8_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX8_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX8_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX8_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX8_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX8_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX8_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX8_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX8_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX8_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX8_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX8_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX8_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX8_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX8_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX8_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX8_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX8_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX8_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX8_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX8_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX8_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX8_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX8_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX8_REC_MISC_CONFIG - Context 8 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX8_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX8_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX8_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX8_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX8_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX8_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX8_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX8_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX8_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX8_REC_SCD_PIDS_AB - Context 8 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX8_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX8_REC_SCD_PIDS_CD - Context 8 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX8_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX8_REC_SCD_PIDS_EF - Context 8 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX8_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX8_REC_SCD_PIDS_GH - Context 8 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX8_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX8_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX8_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX8_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX8_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX8_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX8_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX8_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX8_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX8_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX8_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX8_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX8_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX8_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX8_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX8_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX8_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX8_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX8_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX8_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX8_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX8_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX8_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX8_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX8_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX8_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX8_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX8_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX8_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX8_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX8_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX8_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX8_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX8_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX8_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX8_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX8_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX8_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX8_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX8_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX8_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX8_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX8_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX8_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX8_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX8_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX8_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX8_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX8_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX8_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX8_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX8_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX8_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX8_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX8_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX8_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX8_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX8_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX8_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX8_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX8_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX8_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX8_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX8_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX8_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX8_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX8_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX8_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX8_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX8_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX8_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX8_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX8_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX8_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX8_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX8_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX8_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX8_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX8_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX8_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX8_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX8_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX8_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX8_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX8_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX8_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX8_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX8_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX8_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX8_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX8_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX8_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX8_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX8_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX8_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX8_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX8_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX8_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX8_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX8_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX8_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX8_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX8_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX8_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX8_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX8_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX8_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX8_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX8_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX8_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX8_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX8_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX8_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX8_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX8_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX8_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX8_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX8_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX8_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX8_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX8_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX8_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX8_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX8_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX8_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX8_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX8_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX8_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX8_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX8_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX8_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX8_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX8_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX8_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX8_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX8_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX8_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX8_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX8_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX8_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX8_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX8_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX8_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX8_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX8_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX8_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX8_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX8_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX8_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX8_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX8_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX8_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX8_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX8_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX8_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX8_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX8_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX8_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX8_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX8_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX8_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX8_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX8_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX8_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX8_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX8_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX8_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX8_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX8_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX8_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX8_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX8_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX8_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX8_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX8_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX9_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX9_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX9_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX9_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX9_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX9_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX9_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX9_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX9_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX9_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX9_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX9_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX9_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX9_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX9_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX9_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX9_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX9_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX9_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX9_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX9_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX9_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX9_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX9_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX9_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX9_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX9_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX9_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX9_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX9_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX9_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX9_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX9_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX9_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX9_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX9_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX9_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX9_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX9_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX9_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX9_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX9_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX9_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX9_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX9_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX9_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX9_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX9_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX9_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX9_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX9_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX9_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX9_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX9_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX9_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX9_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX9_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX9_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX9_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX9_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX9_REC_MISC_CONFIG - Context 9 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX9_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX9_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX9_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX9_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX9_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX9_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX9_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX9_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX9_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX9_REC_SCD_PIDS_AB - Context 9 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX9_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX9_REC_SCD_PIDS_CD - Context 9 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX9_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX9_REC_SCD_PIDS_EF - Context 9 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX9_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX9_REC_SCD_PIDS_GH - Context 9 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX9_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX9_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX9_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX9_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX9_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX9_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX9_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX9_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX9_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX9_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX9_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX9_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX9_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX9_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX9_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX9_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX9_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX9_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX9_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX9_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX9_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX9_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX9_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX9_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX9_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX9_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX9_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX9_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX9_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX9_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX9_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX9_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX9_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX9_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX9_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX9_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX9_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX9_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX9_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX9_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX9_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX9_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX9_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX9_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX9_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX9_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX9_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX9_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX9_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX9_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX9_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX9_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX9_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX9_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX9_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX9_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX9_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX9_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX9_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX9_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX9_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX9_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX9_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX9_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX9_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX9_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX9_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX9_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX9_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX9_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX9_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX9_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX9_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX9_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX9_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX9_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX9_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX9_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX9_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX9_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX9_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX9_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX9_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX9_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX9_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX9_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX9_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX9_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX9_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX9_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX9_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX9_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX9_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX9_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX9_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX9_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX9_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX9_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX9_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX9_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX9_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX9_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX9_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX9_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX9_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX9_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX9_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX9_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX9_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX9_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX9_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX9_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX9_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX9_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX9_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX9_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX9_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX9_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX9_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX9_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX9_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX9_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX9_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX9_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX9_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX9_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX9_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX9_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX9_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX9_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX9_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX9_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX9_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX9_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX9_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX9_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX9_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX9_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX9_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX9_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX9_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX9_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX9_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX9_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX9_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX9_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX9_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX9_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX9_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX9_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX9_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX9_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX9_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX9_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX9_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX9_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX9_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX9_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX9_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX9_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX9_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX9_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX9_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX9_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX9_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX9_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX9_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX9_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX9_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX9_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX9_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX9_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX9_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX9_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX9_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX10_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX10_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX10_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX10_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX10_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX10_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX10_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX10_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX10_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX10_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX10_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX10_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX10_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX10_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX10_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX10_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX10_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX10_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX10_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX10_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX10_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX10_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX10_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX10_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX10_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX10_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX10_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX10_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX10_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX10_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX10_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX10_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX10_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX10_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX10_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX10_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX10_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX10_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX10_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX10_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX10_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX10_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX10_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX10_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX10_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX10_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX10_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX10_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX10_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX10_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX10_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX10_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX10_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX10_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX10_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX10_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX10_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX10_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX10_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX10_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX10_REC_MISC_CONFIG - Context 10 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX10_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX10_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX10_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX10_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX10_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX10_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX10_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX10_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX10_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX10_REC_SCD_PIDS_AB - Context 10 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX10_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX10_REC_SCD_PIDS_CD - Context 10 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX10_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX10_REC_SCD_PIDS_EF - Context 10 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX10_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX10_REC_SCD_PIDS_GH - Context 10 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX10_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX10_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX10_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX10_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX10_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX10_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX10_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX10_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX10_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX10_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX10_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX10_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX10_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX10_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX10_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX10_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX10_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX10_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX10_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX10_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX10_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX10_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX10_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX10_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX10_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX10_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX10_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX10_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX10_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX10_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX10_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX10_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX10_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX10_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX10_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX10_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX10_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX10_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX10_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX10_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX10_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX10_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX10_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX10_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX10_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX10_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX10_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX10_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX10_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX10_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX10_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX10_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX10_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX10_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX10_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX10_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX10_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX10_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX10_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX10_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX10_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX10_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX10_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX10_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX10_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX10_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX10_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX10_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX10_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX10_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX10_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX10_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX10_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX10_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX10_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX10_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX10_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX10_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX10_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX10_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX10_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX10_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX10_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX10_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX10_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX10_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX10_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX10_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX10_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX10_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX10_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX10_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX10_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX10_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX10_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX10_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX10_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX10_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX10_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX10_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX10_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX10_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX10_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX10_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX10_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX10_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX10_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX10_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX10_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX10_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX10_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX10_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX10_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX10_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX10_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX10_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX10_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX10_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX10_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX10_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX10_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX10_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX10_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX10_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX10_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX10_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX10_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX10_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX10_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX10_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX10_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX10_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX10_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX10_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX10_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX10_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX10_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX10_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX10_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX10_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX10_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX10_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX10_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX10_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX10_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX10_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX10_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX10_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX10_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX10_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX10_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX10_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX10_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX10_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX10_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX10_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX10_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX10_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX10_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX10_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX10_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX10_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX10_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX10_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX10_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX10_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX10_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX10_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX10_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX10_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX10_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX10_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX10_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX10_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX10_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX11_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX11_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX11_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX11_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX11_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX11_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX11_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX11_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX11_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX11_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX11_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX11_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX11_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX11_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX11_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX11_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX11_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX11_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX11_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX11_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX11_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX11_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX11_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX11_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX11_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX11_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX11_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX11_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX11_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX11_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX11_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX11_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX11_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX11_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX11_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX11_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX11_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX11_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX11_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX11_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX11_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX11_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX11_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX11_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX11_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX11_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX11_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX11_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX11_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX11_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX11_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX11_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX11_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX11_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX11_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX11_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX11_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX11_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX11_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX11_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX11_REC_MISC_CONFIG - Context 11 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX11_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX11_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX11_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX11_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX11_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX11_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX11_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX11_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX11_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX11_REC_SCD_PIDS_AB - Context 11 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX11_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX11_REC_SCD_PIDS_CD - Context 11 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX11_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX11_REC_SCD_PIDS_EF - Context 11 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX11_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX11_REC_SCD_PIDS_GH - Context 11 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX11_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX11_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX11_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX11_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX11_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX11_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX11_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX11_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX11_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX11_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX11_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX11_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX11_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX11_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX11_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX11_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX11_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX11_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX11_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX11_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX11_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX11_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX11_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX11_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX11_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX11_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX11_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX11_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX11_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX11_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX11_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX11_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX11_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX11_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX11_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX11_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX11_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX11_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX11_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX11_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX11_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX11_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX11_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX11_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX11_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX11_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX11_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX11_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX11_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX11_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX11_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX11_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX11_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX11_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX11_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX11_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX11_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX11_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX11_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX11_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX11_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX11_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX11_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX11_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX11_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX11_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX11_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX11_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX11_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX11_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX11_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX11_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX11_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX11_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX11_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX11_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX11_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX11_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX11_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX11_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX11_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX11_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX11_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX11_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX11_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX11_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX11_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX11_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX11_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX11_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX11_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX11_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX11_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX11_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX11_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX11_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX11_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX11_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX11_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX11_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX11_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX11_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX11_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX11_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX11_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX11_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX11_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX11_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX11_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX11_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX11_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX11_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX11_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX11_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX11_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX11_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX11_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX11_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX11_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX11_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX11_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX11_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX11_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX11_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX11_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX11_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX11_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX11_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX11_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX11_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX11_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX11_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX11_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX11_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX11_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX11_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX11_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX11_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX11_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX11_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX11_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX11_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX11_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX11_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX11_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX11_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX11_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX11_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX11_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX11_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX11_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX11_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX11_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX11_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX11_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX11_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX11_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX11_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX11_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX11_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX11_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX11_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX11_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX11_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX11_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX11_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX11_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX11_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX11_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX11_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX11_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX11_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX11_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX11_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX11_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX12_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX12_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX12_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX12_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX12_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX12_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX12_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX12_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX12_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX12_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX12_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX12_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX12_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX12_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX12_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX12_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX12_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX12_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX12_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX12_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX12_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX12_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX12_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX12_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX12_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX12_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX12_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX12_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX12_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX12_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX12_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX12_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX12_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX12_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX12_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX12_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX12_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX12_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX12_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX12_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX12_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX12_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX12_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX12_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX12_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX12_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX12_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX12_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX12_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX12_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX12_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX12_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX12_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX12_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX12_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX12_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX12_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX12_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX12_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX12_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX12_REC_MISC_CONFIG - Context 12 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX12_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX12_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX12_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX12_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX12_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX12_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX12_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX12_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX12_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX12_REC_SCD_PIDS_AB - Context 12 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX12_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX12_REC_SCD_PIDS_CD - Context 12 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX12_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX12_REC_SCD_PIDS_EF - Context 12 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX12_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX12_REC_SCD_PIDS_GH - Context 12 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX12_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX12_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX12_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX12_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX12_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX12_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX12_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX12_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX12_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX12_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX12_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX12_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX12_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX12_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX12_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX12_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX12_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX12_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX12_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX12_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX12_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX12_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX12_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX12_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX12_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX12_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX12_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX12_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX12_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX12_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX12_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX12_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX12_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX12_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX12_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX12_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX12_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX12_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX12_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX12_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX12_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX12_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX12_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX12_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX12_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX12_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX12_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX12_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX12_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX12_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX12_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX12_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX12_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX12_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX12_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX12_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX12_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX12_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX12_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX12_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX12_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX12_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX12_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX12_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX12_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX12_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX12_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX12_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX12_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX12_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX12_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX12_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX12_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX12_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX12_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX12_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX12_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX12_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX12_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX12_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX12_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX12_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX12_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX12_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX12_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX12_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX12_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX12_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX12_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX12_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX12_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX12_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX12_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX12_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX12_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX12_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX12_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX12_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX12_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX12_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX12_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX12_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX12_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX12_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX12_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX12_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX12_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX12_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX12_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX12_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX12_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX12_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX12_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX12_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX12_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX12_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX12_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX12_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX12_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX12_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX12_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX12_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX12_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX12_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX12_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX12_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX12_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX12_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX12_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX12_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX12_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX12_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX12_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX12_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX12_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX12_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX12_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX12_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX12_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX12_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX12_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX12_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX12_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX12_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX12_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX12_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX12_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX12_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX12_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX12_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX12_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX12_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX12_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX12_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX12_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX12_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX12_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX12_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX12_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX12_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX12_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX12_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX12_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX12_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX12_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX12_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX12_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX12_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX12_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX12_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX12_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX12_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX12_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX12_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX12_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX13_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX13_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX13_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX13_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX13_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX13_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX13_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX13_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX13_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX13_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX13_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX13_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX13_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX13_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX13_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX13_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX13_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX13_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX13_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX13_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX13_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX13_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX13_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX13_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX13_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX13_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX13_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX13_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX13_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX13_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX13_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX13_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX13_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX13_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX13_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX13_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX13_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX13_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX13_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX13_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX13_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX13_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX13_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX13_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX13_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX13_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX13_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX13_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX13_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX13_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX13_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX13_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX13_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX13_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX13_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX13_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX13_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX13_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX13_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX13_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX13_REC_MISC_CONFIG - Context 13 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX13_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX13_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX13_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX13_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX13_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX13_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX13_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX13_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX13_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX13_REC_SCD_PIDS_AB - Context 13 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX13_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX13_REC_SCD_PIDS_CD - Context 13 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX13_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX13_REC_SCD_PIDS_EF - Context 13 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX13_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX13_REC_SCD_PIDS_GH - Context 13 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX13_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX13_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX13_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX13_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX13_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX13_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX13_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX13_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX13_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX13_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX13_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX13_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX13_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX13_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX13_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX13_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX13_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX13_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX13_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX13_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX13_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX13_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX13_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX13_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX13_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX13_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX13_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX13_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX13_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX13_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX13_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX13_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX13_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX13_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX13_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX13_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX13_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX13_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX13_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX13_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX13_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX13_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX13_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX13_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX13_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX13_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX13_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX13_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX13_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX13_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX13_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX13_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX13_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX13_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX13_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX13_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX13_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX13_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX13_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX13_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX13_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX13_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX13_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX13_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX13_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX13_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX13_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX13_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX13_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX13_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX13_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX13_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX13_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX13_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX13_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX13_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX13_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX13_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX13_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX13_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX13_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX13_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX13_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX13_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX13_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX13_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX13_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX13_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX13_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX13_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX13_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX13_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX13_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX13_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX13_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX13_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX13_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX13_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX13_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX13_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX13_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX13_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX13_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX13_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX13_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX13_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX13_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX13_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX13_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX13_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX13_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX13_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX13_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX13_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX13_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX13_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX13_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX13_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX13_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX13_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX13_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX13_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX13_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX13_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX13_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX13_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX13_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX13_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX13_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX13_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX13_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX13_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX13_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX13_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX13_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX13_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX13_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX13_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX13_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX13_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX13_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX13_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX13_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX13_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX13_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX13_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX13_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX13_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX13_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX13_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX13_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX13_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX13_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX13_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX13_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX13_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX13_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX13_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX13_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX13_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX13_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX13_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX13_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX13_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX13_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX13_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX13_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX13_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX13_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX13_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX13_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX13_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX13_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX13_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX13_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX14_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX14_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX14_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX14_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX14_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX14_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX14_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX14_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX14_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX14_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX14_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX14_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX14_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX14_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX14_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX14_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX14_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX14_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX14_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX14_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX14_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX14_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX14_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX14_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX14_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX14_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX14_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX14_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX14_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX14_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX14_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX14_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX14_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX14_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX14_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX14_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX14_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX14_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX14_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX14_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX14_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX14_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX14_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX14_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX14_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX14_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX14_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX14_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX14_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX14_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX14_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX14_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX14_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX14_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX14_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX14_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX14_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX14_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX14_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX14_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX14_REC_MISC_CONFIG - Context 14 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX14_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX14_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX14_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX14_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX14_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX14_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX14_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX14_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX14_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX14_REC_SCD_PIDS_AB - Context 14 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX14_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX14_REC_SCD_PIDS_CD - Context 14 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX14_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX14_REC_SCD_PIDS_EF - Context 14 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX14_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX14_REC_SCD_PIDS_GH - Context 14 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX14_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX14_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX14_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX14_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX14_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX14_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX14_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX14_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX14_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX14_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX14_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX14_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX14_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX14_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX14_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX14_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX14_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX14_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX14_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX14_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX14_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX14_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX14_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX14_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX14_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX14_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX14_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX14_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX14_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX14_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX14_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX14_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX14_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX14_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX14_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX14_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX14_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX14_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX14_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX14_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX14_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX14_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX14_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX14_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX14_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX14_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX14_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX14_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX14_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX14_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX14_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX14_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX14_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX14_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX14_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX14_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX14_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX14_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX14_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX14_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX14_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX14_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX14_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX14_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX14_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX14_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX14_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX14_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX14_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX14_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX14_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX14_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX14_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX14_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX14_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX14_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX14_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX14_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX14_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX14_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX14_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX14_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX14_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX14_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX14_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX14_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX14_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX14_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX14_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX14_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX14_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX14_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX14_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX14_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX14_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX14_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX14_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX14_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX14_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX14_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX14_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX14_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX14_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX14_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX14_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX14_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX14_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX14_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX14_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX14_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX14_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX14_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX14_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX14_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX14_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX14_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX14_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX14_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX14_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX14_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX14_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX14_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX14_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX14_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX14_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX14_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX14_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX14_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX14_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX14_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX14_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX14_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX14_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX14_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX14_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX14_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX14_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX14_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX14_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX14_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX14_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX14_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX14_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX14_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX14_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX14_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX14_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX14_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX14_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX14_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX14_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX14_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX14_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX14_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX14_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX14_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX14_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX14_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX14_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX14_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX14_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX14_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX14_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX14_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX14_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX14_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX14_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX14_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX14_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX14_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX14_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX14_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX14_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX14_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX14_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX15_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX15_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX15_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX15_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX15_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX15_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX15_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX15_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX15_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX15_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX15_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX15_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX15_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX15_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX15_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX15_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX15_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX15_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX15_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX15_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX15_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX15_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX15_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX15_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX15_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX15_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX15_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX15_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX15_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX15_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX15_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX15_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX15_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX15_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX15_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX15_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX15_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX15_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX15_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX15_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX15_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX15_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX15_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX15_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX15_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX15_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX15_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX15_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX15_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX15_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX15_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX15_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX15_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX15_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX15_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX15_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX15_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX15_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX15_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX15_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX15_REC_MISC_CONFIG - Context 15 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX15_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX15_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX15_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX15_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX15_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX15_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX15_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX15_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX15_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX15_REC_SCD_PIDS_AB - Context 15 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX15_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX15_REC_SCD_PIDS_CD - Context 15 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX15_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX15_REC_SCD_PIDS_EF - Context 15 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX15_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX15_REC_SCD_PIDS_GH - Context 15 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX15_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX15_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX15_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX15_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX15_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX15_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX15_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX15_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX15_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX15_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX15_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX15_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX15_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX15_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX15_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX15_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX15_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX15_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX15_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX15_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX15_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX15_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX15_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX15_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX15_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX15_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX15_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX15_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX15_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX15_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX15_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX15_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX15_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX15_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX15_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX15_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX15_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX15_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX15_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX15_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX15_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX15_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX15_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX15_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX15_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX15_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX15_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX15_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX15_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX15_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX15_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX15_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX15_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX15_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX15_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX15_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX15_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX15_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX15_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX15_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX15_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX15_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX15_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX15_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX15_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX15_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX15_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX15_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX15_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX15_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX15_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX15_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX15_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX15_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX15_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX15_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX15_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX15_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX15_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX15_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX15_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX15_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX15_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX15_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX15_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX15_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX15_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX15_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX15_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX15_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX15_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX15_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX15_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX15_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX15_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX15_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX15_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX15_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX15_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX15_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX15_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX15_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX15_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX15_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX15_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX15_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX15_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX15_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX15_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX15_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX15_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX15_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX15_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX15_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX15_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX15_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX15_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX15_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX15_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX15_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX15_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX15_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX15_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX15_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX15_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX15_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX15_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX15_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX15_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX15_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX15_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX15_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX15_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX15_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX15_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX15_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX15_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX15_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX15_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX15_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX15_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX15_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX15_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX15_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX15_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX15_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX15_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX15_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX15_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX15_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX15_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX15_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX15_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX15_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX15_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX15_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX15_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX15_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX15_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX15_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX15_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX15_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX15_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX15_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX15_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX15_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX15_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX15_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX15_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX15_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX15_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX15_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX15_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX15_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX15_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX16_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX16_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX16_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX16_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX16_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX16_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX16_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX16_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX16_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX16_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX16_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX16_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX16_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX16_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX16_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX16_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX16_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX16_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX16_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX16_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX16_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX16_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX16_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX16_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX16_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX16_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX16_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX16_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX16_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX16_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX16_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX16_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX16_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX16_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX16_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX16_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX16_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX16_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX16_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX16_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX16_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX16_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX16_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX16_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX16_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX16_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX16_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX16_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX16_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX16_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX16_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX16_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX16_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX16_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX16_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX16_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX16_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX16_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX16_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX16_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX16_REC_MISC_CONFIG - Context 16 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX16_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX16_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX16_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX16_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX16_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX16_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX16_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX16_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX16_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX16_REC_SCD_PIDS_AB - Context 16 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX16_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX16_REC_SCD_PIDS_CD - Context 16 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX16_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX16_REC_SCD_PIDS_EF - Context 16 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX16_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX16_REC_SCD_PIDS_GH - Context 16 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX16_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX16_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX16_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX16_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX16_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX16_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX16_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX16_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX16_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX16_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX16_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX16_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX16_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX16_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX16_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX16_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX16_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX16_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX16_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX16_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX16_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX16_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX16_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX16_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX16_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX16_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX16_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX16_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX16_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX16_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX16_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX16_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX16_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX16_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX16_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX16_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX16_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX16_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX16_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX16_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX16_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX16_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX16_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX16_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX16_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX16_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX16_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX16_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX16_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX16_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX16_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX16_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX16_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX16_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX16_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX16_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX16_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX16_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX16_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX16_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX16_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX16_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX16_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX16_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX16_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX16_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX16_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX16_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX16_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX16_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX16_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX16_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX16_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX16_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX16_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX16_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX16_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX16_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX16_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX16_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX16_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX16_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX16_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX16_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX16_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX16_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX16_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX16_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX16_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX16_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX16_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX16_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX16_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX16_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX16_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX16_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX16_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX16_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX16_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX16_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX16_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX16_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX16_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX16_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX16_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX16_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX16_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX16_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX16_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX16_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX16_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX16_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX16_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX16_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX16_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX16_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX16_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX16_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX16_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX16_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX16_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX16_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX16_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX16_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX16_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX16_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX16_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX16_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX16_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX16_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX16_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX16_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX16_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX16_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX16_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX16_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX16_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX16_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX16_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX16_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX16_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX16_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX16_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX16_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX16_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX16_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX16_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX16_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX16_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX16_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX16_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX16_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX16_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX16_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX16_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX16_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX16_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX16_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX16_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX16_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX16_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX16_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX16_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX16_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX16_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX16_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX16_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX16_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX16_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX16_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX16_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX16_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX16_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX16_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX16_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX17_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX17_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX17_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX17_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX17_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX17_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX17_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX17_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX17_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX17_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX17_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX17_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX17_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX17_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX17_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX17_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX17_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX17_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX17_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX17_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX17_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX17_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX17_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX17_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX17_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX17_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX17_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX17_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX17_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX17_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX17_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX17_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX17_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX17_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX17_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX17_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX17_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX17_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX17_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX17_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX17_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX17_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX17_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX17_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX17_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX17_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX17_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX17_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX17_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX17_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX17_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX17_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX17_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX17_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX17_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX17_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX17_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX17_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX17_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX17_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX17_REC_MISC_CONFIG - Context 17 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX17_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX17_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX17_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX17_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX17_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX17_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX17_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX17_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX17_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX17_REC_SCD_PIDS_AB - Context 17 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX17_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX17_REC_SCD_PIDS_CD - Context 17 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX17_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX17_REC_SCD_PIDS_EF - Context 17 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX17_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX17_REC_SCD_PIDS_GH - Context 17 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX17_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX17_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX17_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX17_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX17_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX17_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX17_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX17_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX17_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX17_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX17_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX17_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX17_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX17_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX17_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX17_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX17_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX17_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX17_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX17_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX17_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX17_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX17_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX17_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX17_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX17_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX17_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX17_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX17_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX17_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX17_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX17_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX17_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX17_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX17_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX17_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX17_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX17_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX17_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX17_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX17_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX17_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX17_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX17_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX17_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX17_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX17_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX17_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX17_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX17_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX17_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX17_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX17_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX17_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX17_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX17_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX17_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX17_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX17_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX17_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX17_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX17_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX17_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX17_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX17_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX17_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX17_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX17_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX17_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX17_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX17_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX17_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX17_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX17_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX17_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX17_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX17_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX17_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX17_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX17_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX17_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX17_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX17_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX17_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX17_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX17_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX17_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX17_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX17_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX17_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX17_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX17_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX17_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX17_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX17_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX17_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX17_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX17_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX17_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX17_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX17_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX17_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX17_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX17_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX17_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX17_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX17_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX17_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX17_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX17_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX17_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX17_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX17_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX17_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX17_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX17_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX17_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX17_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX17_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX17_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX17_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX17_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX17_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX17_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX17_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX17_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX17_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX17_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX17_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX17_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX17_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX17_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX17_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX17_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX17_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX17_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX17_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX17_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX17_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX17_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX17_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX17_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX17_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX17_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX17_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX17_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX17_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX17_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX17_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX17_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX17_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX17_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX17_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX17_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX17_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX17_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX17_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX17_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX17_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX17_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX17_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX17_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX17_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX17_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX17_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX17_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX17_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX17_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX17_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX17_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX17_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX17_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX17_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX17_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX17_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX18_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX18_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX18_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX18_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX18_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX18_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX18_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX18_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX18_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX18_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX18_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX18_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX18_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX18_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX18_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX18_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX18_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX18_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX18_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX18_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX18_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX18_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX18_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX18_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX18_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX18_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX18_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX18_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX18_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX18_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX18_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX18_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX18_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX18_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX18_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX18_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX18_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX18_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX18_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX18_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX18_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX18_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX18_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX18_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX18_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX18_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX18_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX18_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX18_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX18_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX18_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX18_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX18_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX18_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX18_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX18_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX18_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX18_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX18_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX18_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX18_REC_MISC_CONFIG - Context 18 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX18_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX18_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX18_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX18_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX18_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX18_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX18_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX18_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX18_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX18_REC_SCD_PIDS_AB - Context 18 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX18_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX18_REC_SCD_PIDS_CD - Context 18 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX18_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX18_REC_SCD_PIDS_EF - Context 18 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX18_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX18_REC_SCD_PIDS_GH - Context 18 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX18_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX18_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX18_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX18_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX18_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX18_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX18_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX18_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX18_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX18_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX18_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX18_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX18_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX18_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX18_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX18_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX18_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX18_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX18_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX18_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX18_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX18_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX18_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX18_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX18_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX18_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX18_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX18_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX18_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX18_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX18_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX18_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX18_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX18_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX18_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX18_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX18_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX18_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX18_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX18_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX18_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX18_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX18_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX18_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX18_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX18_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX18_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX18_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX18_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX18_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX18_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX18_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX18_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX18_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX18_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX18_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX18_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX18_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX18_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX18_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX18_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX18_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX18_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX18_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX18_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX18_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX18_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX18_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX18_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX18_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX18_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX18_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX18_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX18_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX18_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX18_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX18_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX18_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX18_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX18_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX18_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX18_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX18_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX18_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX18_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX18_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX18_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX18_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX18_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX18_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX18_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX18_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX18_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX18_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX18_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX18_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX18_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX18_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX18_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX18_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX18_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX18_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX18_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX18_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX18_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX18_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX18_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX18_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX18_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX18_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX18_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX18_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX18_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX18_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX18_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX18_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX18_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX18_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX18_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX18_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX18_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX18_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX18_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX18_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX18_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX18_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX18_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX18_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX18_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX18_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX18_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX18_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX18_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX18_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX18_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX18_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX18_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX18_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX18_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX18_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX18_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX18_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX18_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX18_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX18_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX18_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX18_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX18_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX18_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX18_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX18_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX18_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX18_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX18_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX18_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX18_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX18_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX18_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX18_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX18_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX18_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX18_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX18_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX18_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX18_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX18_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX18_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX18_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX18_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX18_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX18_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX18_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX18_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX18_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX18_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX19_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX19_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX19_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX19_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX19_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX19_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX19_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX19_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX19_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX19_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX19_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX19_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX19_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX19_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX19_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX19_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX19_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX19_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX19_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX19_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX19_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX19_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX19_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX19_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX19_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX19_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX19_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX19_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX19_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX19_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX19_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX19_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX19_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX19_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX19_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX19_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX19_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX19_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX19_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX19_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX19_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX19_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX19_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX19_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX19_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX19_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX19_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX19_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX19_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX19_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX19_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX19_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX19_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX19_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX19_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX19_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX19_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX19_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX19_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX19_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX19_REC_MISC_CONFIG - Context 19 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX19_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX19_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX19_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX19_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX19_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX19_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX19_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX19_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX19_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX19_REC_SCD_PIDS_AB - Context 19 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX19_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX19_REC_SCD_PIDS_CD - Context 19 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX19_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX19_REC_SCD_PIDS_EF - Context 19 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX19_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX19_REC_SCD_PIDS_GH - Context 19 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX19_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX19_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX19_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX19_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX19_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX19_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX19_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX19_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX19_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX19_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX19_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX19_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX19_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX19_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX19_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX19_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX19_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX19_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX19_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX19_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX19_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX19_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX19_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX19_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX19_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX19_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX19_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX19_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX19_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX19_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX19_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX19_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX19_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX19_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX19_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX19_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX19_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX19_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX19_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX19_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX19_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX19_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX19_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX19_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX19_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX19_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX19_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX19_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX19_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX19_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX19_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX19_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX19_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX19_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX19_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX19_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX19_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX19_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX19_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX19_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX19_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX19_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX19_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX19_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX19_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX19_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX19_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX19_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX19_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX19_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX19_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX19_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX19_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX19_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX19_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX19_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX19_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX19_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX19_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX19_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX19_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX19_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX19_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX19_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX19_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX19_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX19_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX19_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX19_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX19_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX19_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX19_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX19_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX19_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX19_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX19_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX19_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX19_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX19_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX19_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX19_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX19_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX19_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX19_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX19_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX19_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX19_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX19_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX19_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX19_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX19_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX19_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX19_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX19_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX19_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX19_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX19_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX19_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX19_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX19_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX19_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX19_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX19_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX19_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX19_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX19_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX19_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX19_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX19_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX19_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX19_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX19_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX19_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX19_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX19_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX19_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX19_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX19_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX19_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX19_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX19_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX19_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX19_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX19_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX19_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX19_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX19_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX19_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX19_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX19_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX19_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX19_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX19_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX19_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX19_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX19_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX19_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX19_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX19_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX19_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX19_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX19_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX19_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX19_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX19_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX19_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX19_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX19_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX19_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX19_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX19_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX19_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX19_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX19_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX19_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX20_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX20_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX20_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX20_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX20_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX20_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX20_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX20_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX20_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX20_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX20_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX20_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX20_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX20_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX20_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX20_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX20_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX20_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX20_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX20_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX20_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX20_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX20_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX20_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX20_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX20_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX20_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX20_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX20_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX20_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX20_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX20_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX20_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX20_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX20_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX20_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX20_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX20_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX20_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX20_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX20_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX20_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX20_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX20_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX20_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX20_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX20_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX20_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX20_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX20_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX20_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX20_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX20_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX20_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX20_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX20_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX20_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX20_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX20_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX20_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX20_REC_MISC_CONFIG - Context 20 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX20_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX20_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX20_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX20_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX20_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX20_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX20_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX20_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX20_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX20_REC_SCD_PIDS_AB - Context 20 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX20_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX20_REC_SCD_PIDS_CD - Context 20 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX20_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX20_REC_SCD_PIDS_EF - Context 20 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX20_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX20_REC_SCD_PIDS_GH - Context 20 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX20_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX20_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX20_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX20_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX20_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX20_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX20_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX20_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX20_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX20_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX20_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX20_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX20_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX20_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX20_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX20_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX20_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX20_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX20_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX20_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX20_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX20_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX20_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX20_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX20_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX20_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX20_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX20_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX20_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX20_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX20_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX20_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX20_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX20_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX20_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX20_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX20_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX20_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX20_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX20_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX20_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX20_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX20_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX20_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX20_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX20_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX20_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX20_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX20_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX20_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX20_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX20_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX20_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX20_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX20_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX20_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX20_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX20_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX20_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX20_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX20_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX20_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX20_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX20_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX20_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX20_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX20_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX20_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX20_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX20_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX20_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX20_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX20_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX20_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX20_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX20_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX20_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX20_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX20_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX20_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX20_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX20_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX20_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX20_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX20_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX20_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX20_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX20_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX20_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX20_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX20_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX20_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX20_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX20_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX20_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX20_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX20_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX20_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX20_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX20_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX20_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX20_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX20_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX20_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX20_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX20_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX20_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX20_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX20_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX20_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX20_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX20_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX20_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX20_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX20_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX20_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX20_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX20_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX20_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX20_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX20_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX20_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX20_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX20_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX20_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX20_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX20_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX20_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX20_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX20_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX20_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX20_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX20_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX20_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX20_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX20_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX20_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX20_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX20_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX20_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX20_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX20_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX20_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX20_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX20_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX20_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX20_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX20_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX20_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX20_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX20_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX20_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX20_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX20_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX20_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX20_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX20_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX20_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX20_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX20_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX20_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX20_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX20_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX20_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX20_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX20_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX20_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX20_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX20_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX20_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX20_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX20_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX20_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX20_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX20_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX21_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX21_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX21_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX21_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX21_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX21_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX21_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX21_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX21_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX21_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX21_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX21_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX21_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX21_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX21_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX21_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX21_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX21_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX21_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX21_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX21_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX21_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX21_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX21_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX21_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX21_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX21_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX21_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX21_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX21_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX21_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX21_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX21_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX21_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX21_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX21_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX21_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX21_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX21_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX21_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX21_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX21_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX21_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX21_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX21_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX21_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX21_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX21_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX21_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX21_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX21_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX21_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX21_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX21_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX21_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX21_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX21_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX21_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX21_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX21_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX21_REC_MISC_CONFIG - Context 21 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX21_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX21_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX21_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX21_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX21_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX21_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX21_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX21_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX21_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX21_REC_SCD_PIDS_AB - Context 21 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX21_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX21_REC_SCD_PIDS_CD - Context 21 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX21_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX21_REC_SCD_PIDS_EF - Context 21 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX21_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX21_REC_SCD_PIDS_GH - Context 21 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX21_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX21_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX21_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX21_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX21_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX21_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX21_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX21_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX21_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX21_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX21_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX21_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX21_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX21_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX21_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX21_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX21_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX21_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX21_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX21_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX21_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX21_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX21_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX21_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX21_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX21_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX21_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX21_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX21_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX21_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX21_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX21_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX21_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX21_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX21_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX21_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX21_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX21_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX21_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX21_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX21_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX21_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX21_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX21_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX21_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX21_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX21_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX21_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX21_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX21_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX21_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX21_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX21_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX21_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX21_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX21_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX21_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX21_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX21_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX21_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX21_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX21_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX21_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX21_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX21_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX21_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX21_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX21_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX21_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX21_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX21_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX21_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX21_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX21_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX21_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX21_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX21_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX21_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX21_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX21_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX21_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX21_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX21_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX21_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX21_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX21_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX21_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX21_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX21_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX21_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX21_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX21_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX21_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX21_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX21_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX21_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX21_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX21_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX21_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX21_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX21_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX21_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX21_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX21_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX21_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX21_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX21_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX21_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX21_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX21_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX21_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX21_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX21_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX21_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX21_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX21_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX21_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX21_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX21_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX21_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX21_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX21_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX21_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX21_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX21_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX21_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX21_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX21_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX21_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX21_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX21_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX21_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX21_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX21_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX21_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX21_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX21_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX21_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX21_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX21_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX21_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX21_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX21_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX21_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX21_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX21_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX21_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX21_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX21_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX21_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX21_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX21_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX21_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX21_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX21_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX21_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX21_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX21_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX21_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX21_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX21_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX21_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX21_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX21_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX21_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX21_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX21_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX21_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX21_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX21_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX21_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX21_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX21_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX21_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX21_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX22_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX22_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX22_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX22_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX22_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX22_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX22_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX22_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX22_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX22_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX22_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX22_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX22_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX22_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX22_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX22_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX22_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX22_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX22_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX22_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX22_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX22_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX22_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX22_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX22_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX22_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX22_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX22_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX22_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX22_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX22_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX22_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX22_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX22_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX22_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX22_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX22_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX22_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX22_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX22_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX22_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX22_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX22_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX22_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX22_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX22_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX22_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX22_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX22_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX22_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX22_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX22_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX22_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX22_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX22_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX22_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX22_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX22_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX22_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX22_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX22_REC_MISC_CONFIG - Context 22 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX22_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX22_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX22_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX22_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX22_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX22_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX22_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX22_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX22_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX22_REC_SCD_PIDS_AB - Context 22 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX22_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX22_REC_SCD_PIDS_CD - Context 22 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX22_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX22_REC_SCD_PIDS_EF - Context 22 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX22_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX22_REC_SCD_PIDS_GH - Context 22 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX22_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX22_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX22_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX22_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX22_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX22_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX22_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX22_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX22_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX22_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX22_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX22_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX22_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX22_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX22_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX22_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX22_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX22_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX22_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX22_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX22_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX22_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX22_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX22_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX22_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX22_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX22_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX22_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX22_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX22_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX22_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX22_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX22_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX22_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX22_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX22_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX22_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX22_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX22_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX22_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX22_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX22_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX22_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX22_AV_COMP12_FILTER_Mode - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX22_AV_COMP12_FILTER_Mode :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX22_AV_COMP12_FILTER_Mode_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX22_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX22_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX22_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX22_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX22_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX22_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX22_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX22_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX22_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX22_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX22_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX22_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX22_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX22_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX22_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX22_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX22_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX22_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX22_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX22_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX22_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX22_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX22_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX22_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX22_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX22_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX22_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX22_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX22_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX22_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX22_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX22_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX22_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX22_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX22_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX22_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX22_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX22_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX22_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX22_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX22_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX22_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX22_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX22_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX22_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX22_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX22_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX22_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX22_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX22_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX22_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX22_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX22_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX22_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX22_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX22_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX22_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX22_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX22_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX22_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX22_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX22_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX22_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX22_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX22_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX22_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX22_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX22_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX22_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX22_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX22_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX22_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX22_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX22_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX22_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX22_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX22_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX22_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX22_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX22_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX22_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX22_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX22_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX22_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX22_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX22_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX22_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX22_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX22_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX22_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX22_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX22_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX22_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX22_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX22_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX22_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX22_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX22_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX22_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX22_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX22_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX22_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX22_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX22_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX22_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX22_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX22_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX22_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX22_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX22_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX22_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX22_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX22_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX22_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX22_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX22_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX22_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX22_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX22_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX22_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX22_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX22_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX22_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX22_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX22_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX22_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX22_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX22_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX22_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX23_AV_CDB_WRITE_PTR - Context CDB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX23_AV_CDB_WRITE_PTR :: CDB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX23_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_AV_CDB_WRITE_PTR_CDB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX23_AV_CDB_READ_PTR - Context CDB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX23_AV_CDB_READ_PTR :: CDB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX23_AV_CDB_READ_PTR_CDB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_AV_CDB_READ_PTR_CDB_READ_PTR_SHIFT 0 /*************************************************************************** *CX23_AV_CDB_BASE_PTR - Context CDB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX23_AV_CDB_BASE_PTR :: CDB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX23_AV_CDB_BASE_PTR_CDB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_AV_CDB_BASE_PTR_CDB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX23_AV_CDB_END_PTR - Context CDB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX23_AV_CDB_END_PTR :: CDB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX23_AV_CDB_END_PTR_CDB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_AV_CDB_END_PTR_CDB_END_PTR_SHIFT 0 /*************************************************************************** *CX23_AV_CDB_VALID_PTR - Context CDB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX23_AV_CDB_VALID_PTR :: CDB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX23_AV_CDB_VALID_PTR_CDB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_AV_CDB_VALID_PTR_CDB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX23_AV_CDB_WRAPAROUND_PTR - Context CDB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX23_AV_CDB_WRAPAROUND_PTR :: CDB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX23_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_AV_CDB_WRAPAROUND_PTR_CDB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX23_AV_CDB_THRESHOLD_LEVEL - Context CDB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX23_AV_CDB_THRESHOLD_LEVEL :: CDB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL_CDB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX23_AV_CDB_THRESHOLD_LEVEL :: CDB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX23_AV_CDB_THRESHOLD_LEVEL_CDB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX23_AV_CDB_DEPTH - Context CDB Depth ***************************************************************************/ /* XPT_RAVE :: CX23_AV_CDB_DEPTH :: CDB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX23_AV_CDB_DEPTH :: CDB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX23_AV_CDB_DEPTH :: CDB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX23_AV_CDB_DEPTH :: CDB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX23_AV_CDB_DEPTH_CDB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX23_AV_THRESHOLDS - Context Thresholds ***************************************************************************/ /* XPT_RAVE :: CX23_AV_THRESHOLDS :: CONTEXT_OVERFLOW_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS_CONTEXT_OVERFLOW_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX23_AV_THRESHOLDS :: CONTEXT_WRAPAROUND_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX23_AV_THRESHOLDS_CONTEXT_WRAPAROUND_THRESHOLD_SHIFT 0 /*************************************************************************** *CX23_AV_ITB_WRITE_PTR - Context ITB Write Pointer ***************************************************************************/ /* XPT_RAVE :: CX23_AV_ITB_WRITE_PTR :: ITB_WRITE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX23_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_AV_ITB_WRITE_PTR_ITB_WRITE_PTR_SHIFT 0 /*************************************************************************** *CX23_AV_ITB_READ_PTR - Context ITB Read Pointer ***************************************************************************/ /* XPT_RAVE :: CX23_AV_ITB_READ_PTR :: ITB_READ_PTR [31:00] */ #define BCHP_XPT_RAVE_CX23_AV_ITB_READ_PTR_ITB_READ_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_AV_ITB_READ_PTR_ITB_READ_PTR_SHIFT 0 /*************************************************************************** *CX23_AV_ITB_BASE_PTR - Context ITB Base Pointer ***************************************************************************/ /* XPT_RAVE :: CX23_AV_ITB_BASE_PTR :: ITB_BASE_PTR [31:00] */ #define BCHP_XPT_RAVE_CX23_AV_ITB_BASE_PTR_ITB_BASE_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_AV_ITB_BASE_PTR_ITB_BASE_PTR_SHIFT 0 /*************************************************************************** *CX23_AV_ITB_END_PTR - Context ITB End Pointer ***************************************************************************/ /* XPT_RAVE :: CX23_AV_ITB_END_PTR :: ITB_END_PTR [31:00] */ #define BCHP_XPT_RAVE_CX23_AV_ITB_END_PTR_ITB_END_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_AV_ITB_END_PTR_ITB_END_PTR_SHIFT 0 /*************************************************************************** *CX23_AV_ITB_VALID_PTR - Context ITB Valid Pointer ***************************************************************************/ /* XPT_RAVE :: CX23_AV_ITB_VALID_PTR :: ITB_VALID_PTR [31:00] */ #define BCHP_XPT_RAVE_CX23_AV_ITB_VALID_PTR_ITB_VALID_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_AV_ITB_VALID_PTR_ITB_VALID_PTR_SHIFT 0 /*************************************************************************** *CX23_AV_ITB_WRAPAROUND_PTR - Context ITB Wraparound Pointer ***************************************************************************/ /* XPT_RAVE :: CX23_AV_ITB_WRAPAROUND_PTR :: ITB_WRAPAROUND_PTR [31:00] */ #define BCHP_XPT_RAVE_CX23_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_AV_ITB_WRAPAROUND_PTR_ITB_WRAPAROUND_PTR_SHIFT 0 /*************************************************************************** *CX23_AV_ITB_THRESHOLD_LEVEL - Context ITB Watermark Level ***************************************************************************/ /* XPT_RAVE :: CX23_AV_ITB_THRESHOLD_LEVEL :: ITB_UPPER_THRESHOLD [31:16] */ #define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL_ITB_UPPER_THRESHOLD_SHIFT 16 /* XPT_RAVE :: CX23_AV_ITB_THRESHOLD_LEVEL :: ITB_LOWER_THRESHOLD [15:00] */ #define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX23_AV_ITB_THRESHOLD_LEVEL_ITB_LOWER_THRESHOLD_SHIFT 0 /*************************************************************************** *CX23_AV_ITB_DEPTH - Context ITB Depth ***************************************************************************/ /* XPT_RAVE :: CX23_AV_ITB_DEPTH :: ITB_WRAPAROUND [31:31] */ #define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_WRAPAROUND_MASK 0x80000000 #define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_WRAPAROUND_SHIFT 31 /* XPT_RAVE :: CX23_AV_ITB_DEPTH :: ITB_OVERFLOW [30:30] */ #define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_OVERFLOW_MASK 0x40000000 #define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_OVERFLOW_SHIFT 30 /* XPT_RAVE :: CX23_AV_ITB_DEPTH :: ITB_WMARK_INDICATOR [29:28] */ #define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_MASK 0x30000000 #define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_WMARK_INDICATOR_SHIFT 28 /* XPT_RAVE :: CX23_AV_ITB_DEPTH :: ITB_BUFFER_DEPTH [27:00] */ #define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_MASK 0x0fffffff #define BCHP_XPT_RAVE_CX23_AV_ITB_DEPTH_ITB_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *CX23_REC_MISC_CONFIG - Context 23 Miscellaneous Config ***************************************************************************/ /* XPT_RAVE :: CX23_REC_MISC_CONFIG :: reserved_for_eco0 [31:17] */ #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_reserved_for_eco0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_reserved_for_eco0_SHIFT 17 /* XPT_RAVE :: CX23_REC_MISC_CONFIG :: IGNORE_CLEAR_SC_EVENT [16:16] */ #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_MASK 0x00010000 #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_IGNORE_CLEAR_SC_EVENT_SHIFT 16 /* XPT_RAVE :: CX23_REC_MISC_CONFIG :: SC_DETECT_FOR_ALL [15:15] */ #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_MASK 0x00008000 #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_SC_DETECT_FOR_ALL_SHIFT 15 /* XPT_RAVE :: CX23_REC_MISC_CONFIG :: REC_AVN [14:14] */ #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_REC_AVN_MASK 0x00004000 #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_REC_AVN_SHIFT 14 /* XPT_RAVE :: CX23_REC_MISC_CONFIG :: TPIT_ENABLE [13:13] */ #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_TPIT_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_TPIT_ENABLE_SHIFT 13 /* XPT_RAVE :: CX23_REC_MISC_CONFIG :: TPIT_CHANNEL [12:08] */ #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_TPIT_CHANNEL_MASK 0x00001f00 #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_TPIT_CHANNEL_SHIFT 8 /* XPT_RAVE :: CX23_REC_MISC_CONFIG :: reserved_for_eco1 [07:02] */ #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_reserved_for_eco1_MASK 0x000000fc #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: CX23_REC_MISC_CONFIG :: SCD_MAP_MODE [01:00] */ #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_SCD_MAP_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX23_REC_MISC_CONFIG_SCD_MAP_MODE_SHIFT 0 /*************************************************************************** *CX23_REC_SCD_PIDS_AB - Context 23 SCD map PIDS A and B ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDB_VALID [31:31] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDB_VALID_SHIFT 31 /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_B [30:30] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_MASK 0x40000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_B_SHIFT 30 /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMB [29:24] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMB_SHIFT 24 /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDB [23:16] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDB_SHIFT 16 /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_A [14:14] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_MASK 0x00004000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_A_SHIFT 14 /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_NUMA [13:08] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_NUMA_SHIFT 8 /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_PID_channels :: SCD_PIDA [07:00] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_PID_channels_SCD_PIDA_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_A [30:30] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_MASK 0x40000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_A_SHIFT 30 /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_NUMA [29:24] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_NUMA_SHIFT 24 /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: PIDA_VALID [15:15] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_PIDA_VALID_SHIFT 15 /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX23_REC_SCD_PIDS_AB :: Mapped_SCD_via_stream_PID_values :: SCD_PIDA [12:00] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_MASK 0x00001fff #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_AB_Mapped_SCD_via_stream_PID_values_SCD_PIDA_SHIFT 0 /*************************************************************************** *CX23_REC_SCD_PIDS_CD - Context 23 SCD map PIDS C and D ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDD_VALID [31:31] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDD_VALID_SHIFT 31 /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_D [30:30] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_MASK 0x40000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_D_SHIFT 30 /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMD [29:24] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMD_SHIFT 24 /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDD [23:16] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDD_SHIFT 16 /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_C [14:14] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_MASK 0x00004000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_C_SHIFT 14 /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_NUMC [13:08] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_NUMC_SHIFT 8 /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_PID_channels :: SCD_PIDC [07:00] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_PID_channels_SCD_PIDC_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_C [30:30] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_MASK 0x40000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_C_SHIFT 30 /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_NUMC [29:24] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_NUMC_SHIFT 24 /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: PIDC_VALID [15:15] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_PIDC_VALID_SHIFT 15 /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX23_REC_SCD_PIDS_CD :: Mapped_SCD_via_stream_PID_values :: SCD_PIDC [12:00] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_MASK 0x00001fff #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_CD_Mapped_SCD_via_stream_PID_values_SCD_PIDC_SHIFT 0 /*************************************************************************** *CX23_REC_SCD_PIDS_EF - Context 23 SCD map PIDS E and F ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDF_VALID [31:31] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDF_VALID_SHIFT 31 /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_F [30:30] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_MASK 0x40000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_F_SHIFT 30 /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUMF [29:24] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUMF_SHIFT 24 /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDF [23:16] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDF_SHIFT 16 /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_E [14:14] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_MASK 0x00004000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_E_SHIFT 14 /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_NUME [13:08] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_NUME_SHIFT 8 /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_PID_channels :: SCD_PIDE [07:00] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_PID_channels_SCD_PIDE_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_E [30:30] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_MASK 0x40000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_E_SHIFT 30 /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_NUME [29:24] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_NUME_SHIFT 24 /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: PIDE_VALID [15:15] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_PIDE_VALID_SHIFT 15 /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX23_REC_SCD_PIDS_EF :: Mapped_SCD_via_stream_PID_values :: SCD_PIDE [12:00] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_MASK 0x00001fff #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_EF_Mapped_SCD_via_stream_PID_values_SCD_PIDE_SHIFT 0 /*************************************************************************** *CX23_REC_SCD_PIDS_GH - Context 23 SCD map PIDS G and H ***************************************************************************/ /* union - case Mapped_SCD_via_PID_channels [31:00] */ /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDH_VALID [31:31] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_MASK 0x80000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDH_VALID_SHIFT 31 /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_H [30:30] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_MASK 0x40000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_H_SHIFT 30 /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMH [29:24] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMH_SHIFT 24 /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDH [23:16] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDH_SHIFT 16 /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PTS_MODE_PIDCH_G [14:14] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_MASK 0x00004000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PTS_MODE_PIDCH_G_SHIFT 14 /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_NUMG [13:08] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_MASK 0x00003f00 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_NUMG_SHIFT 8 /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_PID_channels :: SCD_PIDG [07:00] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_PID_channels_SCD_PIDG_SHIFT 0 /* union - case Mapped_SCD_via_stream_PID_values [31:00] */ /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco0 [31:31] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco0_SHIFT 31 /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PTS_MODE_PID_G [30:30] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_MASK 0x40000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PTS_MODE_PID_G_SHIFT 30 /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_NUMG [29:24] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_MASK 0x3f000000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_NUMG_SHIFT 24 /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco1 [23:16] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco1_SHIFT 16 /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: PIDG_VALID [15:15] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_MASK 0x00008000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_PIDG_VALID_SHIFT 15 /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: reserved_for_eco2 [14:13] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_MASK 0x00006000 #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_reserved_for_eco2_SHIFT 13 /* XPT_RAVE :: CX23_REC_SCD_PIDS_GH :: Mapped_SCD_via_stream_PID_values :: SCD_PIDG [12:00] */ #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_MASK 0x00001fff #define BCHP_XPT_RAVE_CX23_REC_SCD_PIDS_GH_Mapped_SCD_via_stream_PID_values_SCD_PIDG_SHIFT 0 /*************************************************************************** *CX23_AV_MISC_CONFIG1 - Context Miscellaneous Config 1 Register ***************************************************************************/ /* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: BAND_HOLD_EN [31:31] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_BAND_HOLD_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_BAND_HOLD_EN_SHIFT 31 /* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: EMU_PREV_BYTE_REMOVE [30:30] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_MASK 0x40000000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_EMU_PREV_BYTE_REMOVE_SHIFT 30 /* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: SHIFT_PTS [29:29] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_SHIFT_PTS_MASK 0x20000000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_SHIFT_PTS_SHIFT 29 /* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: CONVERT_PTS [28:28] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_CONVERT_PTS_MASK 0x10000000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_CONVERT_PTS_SHIFT 28 /* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: PES_SYNC_MODE [27:26] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_PES_SYNC_MODE_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_PES_SYNC_MODE_SHIFT 26 /* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: PES_TYPE_MODE [25:24] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_PES_TYPE_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_PES_TYPE_MODE_SHIFT 24 /* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: EMU_PREV_MODE [23:23] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_EMU_PREV_MODE_MASK 0x00800000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_EMU_PREV_MODE_SHIFT 23 /* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: OUTPUT_FORMAT [22:21] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_OUTPUT_FORMAT_MASK 0x00600000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_OUTPUT_FORMAT_SHIFT 21 /* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: CONTEXT_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_CONTEXT_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_CONTEXT_ENABLE_SHIFT 20 /* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: INPUT_ES_FORMAT [19:16] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_INPUT_ES_FORMAT_MASK 0x000f0000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_INPUT_ES_FORMAT_SHIFT 16 /* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_STREAM_ID_HI_SHIFT 8 /* XPT_RAVE :: CX23_AV_MISC_CONFIG1 :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG1_STREAM_ID_LO_SHIFT 0 /*************************************************************************** *CX23_AV_MISC_CONFIG2 - Context Miscellaneous Config 2 Register ***************************************************************************/ /* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: DISABLE_BEFORE_PES [31:31] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_MASK 0x80000000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_DISABLE_BEFORE_PES_SHIFT 31 /* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: reserved_for_eco0 [30:22] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_reserved_for_eco0_MASK 0x7fc00000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_reserved_for_eco0_SHIFT 22 /* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: ITB_ENDIAN_CTRL [21:21] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_MASK 0x00200000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_ITB_ENDIAN_CTRL_SHIFT 21 /* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: CDB_ENDIAN_CTRL [20:20] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_MASK 0x00100000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_CDB_ENDIAN_CTRL_SHIFT 20 /* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: reserved_for_eco1 [19:11] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_reserved_for_eco1_MASK 0x000ff800 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_reserved_for_eco1_SHIFT 11 /* XPT_RAVE :: CX23_AV_MISC_CONFIG2 :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG2_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *CX23_AV_MISC_CONFIG3 - Context Miscellaneous Config 3 Register ***************************************************************************/ /* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_HI [31:24] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_SID_EXCLUDE_HI_SHIFT 24 /* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: PES_SID_EXCLUDE_LO [23:16] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_SID_EXCLUDE_LO_SHIFT 16 /* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: reserved_for_eco0 [15:15] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_reserved_for_eco0_MASK 0x00008000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_reserved_for_eco0_SHIFT 15 /* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: DISABLE_PRV_HDR_DMEM [14:14] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_MASK 0x00004000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_PRV_HDR_DMEM_SHIFT 14 /* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: ENABLE_BPP_SEARCH [13:13] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_MASK 0x00002000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_ENABLE_BPP_SEARCH_SHIFT 13 /* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: CHK_PACK_HDR_IN_AF [12:12] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_MASK 0x00001000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CHK_PACK_HDR_IN_AF_SHIFT 12 /* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: CP_PERM_CHANGE_DETECT [11:11] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_MASK 0x00000800 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CP_PERM_CHANGE_DETECT_SHIFT 11 /* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: PES_EXT_SEARCH_MODE [10:09] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_MASK 0x00000600 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_PES_EXT_SEARCH_MODE_SHIFT 9 /* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: CDB_ITB_DEPTH_MODE [08:08] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_CDB_ITB_DEPTH_MODE_SHIFT 8 /* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: DISABLE_PKT_ERRORS [07:07] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_MASK 0x00000080 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_PKT_ERRORS_SHIFT 7 /* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: DISABLE_CC_CHECK [06:06] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_CC_CHECK_MASK 0x00000040 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_DISABLE_CC_CHECK_SHIFT 6 /* XPT_RAVE :: CX23_AV_MISC_CONFIG3 :: MAX_COMPARE_PATTERNS [05:00] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_MASK 0x0000003f #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG3_MAX_COMPARE_PATTERNS_SHIFT 0 /*************************************************************************** *CX23_AV_INTERRUPT_ENABLES - Context Interrupt Enables ***************************************************************************/ /* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_reserved0_SHIFT 12 /* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: ITB_UPPER_THRESH_INT_EN [11:11] */ #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_MASK 0x00000800 #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_UPPER_THRESH_INT_EN_SHIFT 11 /* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: ITB_LOWER_THRESH_INT_EN [10:10] */ #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_MASK 0x00000400 #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_LOWER_THRESH_INT_EN_SHIFT 10 /* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: CDB_UPPER_THRESH_INT_EN [09:09] */ #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_UPPER_THRESH_INT_EN_SHIFT 9 /* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: CDB_LOWER_THRESH_INT_EN [08:08] */ #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_MASK 0x00000100 #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_LOWER_THRESH_INT_EN_SHIFT 8 /* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: LAST_CMD_INT_EN [07:07] */ #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_LAST_CMD_INT_EN_SHIFT 7 /* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: SPLICE_INT_EN [06:06] */ #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_MASK 0x00000040 #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_SPLICE_INT_EN_SHIFT 6 /* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: ITB_OVERFLOW_INT_EN [05:05] */ #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_MASK 0x00000020 #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_ITB_OVERFLOW_INT_EN_SHIFT 5 /* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: CDB_OVERFLOW_INT_EN [04:04] */ #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_MASK 0x00000010 #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CDB_OVERFLOW_INT_EN_SHIFT 4 /* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: CC_ERROR_INT_EN [03:03] */ #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_CC_ERROR_INT_EN_SHIFT 3 /* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: TEI_ERROR_INT_EN [02:02] */ #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_TEI_ERROR_INT_EN_SHIFT 2 /* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: PUSI_ERROR_INT_EN [01:01] */ #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_PUSI_ERROR_INT_EN_SHIFT 1 /* XPT_RAVE :: CX23_AV_INTERRUPT_ENABLES :: EMU_ERROR_INT_EN [00:00] */ #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_CX23_AV_INTERRUPT_ENABLES_EMU_ERROR_INT_EN_SHIFT 0 /*************************************************************************** *CX23_AV_COMP1_CONTROL - Context Comparator 1 Control Register ***************************************************************************/ /* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: CASCADE_ENABLE [21:21] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_CASCADE_ENABLE_MASK 0x00200000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_CASCADE_ENABLE_SHIFT 21 /* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: NUM_COMPARE_BYTES [19:17] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_MASK 0x000e0000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX23_AV_COMP1_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX23_AV_COMP1_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX23_AV_COMP1_COMPARE_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX23_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX23_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX23_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX23_AV_COMP1_COMPARE_VAL :: COMP1_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_AV_COMP1_COMPARE_VAL_COMP1_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX23_AV_COMP1_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX23_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX23_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX23_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX23_AV_COMP1_MASK_VAL :: COMP1_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_AV_COMP1_MASK_VAL_COMP1_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX23_AV_COMP1_FILTER_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Exclusion_Value_D :: COMP1_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_D_COMP1_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Inclusion_Range_D :: COMP1_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_D_COMP1_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Exclusion_Value_C :: COMP1_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_C_COMP1_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Inclusion_Range_C :: COMP1_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_C_COMP1_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Exclusion_Value_B :: COMP1_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_B_COMP1_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Inclusion_Range_B :: COMP1_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_B_COMP1_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Exclusion_Value_A :: COMP1_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Exclusion_Value_A_COMP1_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_VAL :: Inclusion_Range_A :: COMP1_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_VAL_Inclusion_Range_A_COMP1_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX23_AV_COMP1_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP1_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_D_COMP1_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP1_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_D_COMP1_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP1_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_C_COMP1_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP1_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_C_COMP1_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP1_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_B_COMP1_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP1_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_B_COMP1_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP1_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Exclusion_Mask_A_COMP1_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX23_AV_COMP1_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP1_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_AV_COMP1_FILTER_MASK_VAL_Inclusion_Range_A_COMP1_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX23_AV_COMP2_CONTROL - Context Comparator 2 Control Register ***************************************************************************/ /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: reserved_for_eco0 [31:27] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco0_MASK 0xf8000000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco0_SHIFT 27 /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: ALIGNMENT_EN [26:26] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_ALIGNMENT_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_ALIGNMENT_EN_SHIFT 26 /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMPARE_ES_DATA [25:25] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ES_DATA_MASK 0x02000000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ES_DATA_SHIFT 25 /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMPARE_PES_HDR_DATA [24:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_MASK 0x01000000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_PES_HDR_DATA_SHIFT 24 /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMPARE_ADAPTATION_FIELD [23:23] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ADAPTATION_FIELD_SHIFT 23 /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMPARE_ALL_DATA [22:22] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ALL_DATA_MASK 0x00400000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMPARE_ALL_DATA_SHIFT 22 /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: reserved_for_eco1 [21:21] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco1_MASK 0x00200000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco1_SHIFT 21 /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: VALID_BYTE_ENABLE [20:20] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_MASK 0x00100000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_VALID_BYTE_ENABLE_SHIFT 20 /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: reserved_for_eco2 [19:19] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco2_MASK 0x00080000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_reserved_for_eco2_SHIFT 19 /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: NUM_COMPARE_BYTES [18:17] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_MASK 0x00060000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_NUM_COMPARE_BYTES_SHIFT 17 /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: REPEAT_BYTE [16:13] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_REPEAT_BYTE_MASK 0x0001e000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_REPEAT_BYTE_SHIFT 13 /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: COMP_ENABLE [12:12] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMP_ENABLE_MASK 0x00001000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_COMP_ENABLE_SHIFT 12 /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BYTE [11:10] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_START_BYTE_SHIFT 10 /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: DATA_EXTRACT_START_BIT [09:07] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_MASK 0x00000380 #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_START_BIT_SHIFT 7 /* XPT_RAVE :: CX23_AV_COMP2_CONTROL :: DATA_EXTRACT_NUM_BITS [06:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_MASK 0x0000007f #define BCHP_XPT_RAVE_CX23_AV_COMP2_CONTROL_DATA_EXTRACT_NUM_BITS_SHIFT 0 /*************************************************************************** *CX23_AV_COMP2_COMPARE_VAL - Context Comparator 2 32-bit compare value ***************************************************************************/ /* XPT_RAVE :: CX23_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_0_SHIFT 24 /* XPT_RAVE :: CX23_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_1_SHIFT 16 /* XPT_RAVE :: CX23_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_2_SHIFT 8 /* XPT_RAVE :: CX23_AV_COMP2_COMPARE_VAL :: COMP2_COMPARE_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_AV_COMP2_COMPARE_VAL_COMP2_COMPARE_VAL_3_SHIFT 0 /*************************************************************************** *CX23_AV_COMP2_MASK_VAL - Context Comparator 2 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX23_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_0 [31:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_0_SHIFT 24 /* XPT_RAVE :: CX23_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_1 [23:16] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_1_SHIFT 16 /* XPT_RAVE :: CX23_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_2 [15:08] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_2_SHIFT 8 /* XPT_RAVE :: CX23_AV_COMP2_MASK_VAL :: COMP2_MASK_VAL_3 [07:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_AV_COMP2_MASK_VAL_COMP2_MASK_VAL_3_SHIFT 0 /*************************************************************************** *CX23_AV_COMP2_FILTER_VAL - Context Comparator 1 32-bit compare value ***************************************************************************/ /* union - case Exclusion_Value_D [31:24] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Exclusion_Value_D :: COMP2_EXCLUSION_VAL_D [31:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_D_COMP2_EXCLUSION_VAL_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Inclusion_Range_D :: COMP2_RANGED_HI [31:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_MASK 0xff000000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_D_COMP2_RANGED_HI_SHIFT 24 /* union - case Exclusion_Value_C [23:16] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Exclusion_Value_C :: COMP2_EXCLUSION_VAL_C [23:16] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_C_COMP2_EXCLUSION_VAL_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Inclusion_Range_C :: COMP2_RANGEC_HI [23:16] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_C_COMP2_RANGEC_HI_SHIFT 16 /* union - case Exclusion_Value_B [15:08] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Exclusion_Value_B :: COMP2_EXCLUSION_VAL_B [15:08] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_B_COMP2_EXCLUSION_VAL_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Inclusion_Range_B :: COMP2_RANGEB_HI [15:08] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_B_COMP2_RANGEB_HI_SHIFT 8 /* union - case Exclusion_Value_A [07:00] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Exclusion_Value_A :: COMP2_EXCLUSION_VAL_A [07:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Exclusion_Value_A_COMP2_EXCLUSION_VAL_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_VAL :: Inclusion_Range_A :: COMP2_RANGEA_HI [07:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_VAL_Inclusion_Range_A_COMP2_RANGEA_HI_SHIFT 0 /*************************************************************************** *CX23_AV_COMP2_FILTER_MASK_VAL - Context Comparator 1 32-bit mask value ***************************************************************************/ /* union - case Exclusion_Mask_D [31:24] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_D :: COMP2_EXCLUSION_MASK_D [31:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_MASK 0xff000000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_D_COMP2_EXCLUSION_MASK_D_SHIFT 24 /* union - case Inclusion_Range_D [31:24] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_D :: COMP2_RANGED_LO [31:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_MASK 0xff000000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_D_COMP2_RANGED_LO_SHIFT 24 /* union - case Exclusion_Mask_C [23:16] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_C :: COMP2_EXCLUSION_MASK_C [23:16] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_C_COMP2_EXCLUSION_MASK_C_SHIFT 16 /* union - case Inclusion_Range_C [23:16] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_C :: COMP2_RANGEC_LO [23:16] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_C_COMP2_RANGEC_LO_SHIFT 16 /* union - case Exclusion_Mask_B [15:08] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_B :: COMP2_EXCLUSION_MASK_B [15:08] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_B_COMP2_EXCLUSION_MASK_B_SHIFT 8 /* union - case Inclusion_Range_B [15:08] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_B :: COMP2_RANGEB_LO [15:08] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_B_COMP2_RANGEB_LO_SHIFT 8 /* union - case Exclusion_Mask_A [07:00] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Exclusion_Mask_A :: COMP2_EXCLUSION_MASK_A [07:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Exclusion_Mask_A_COMP2_EXCLUSION_MASK_A_SHIFT 0 /* union - case Inclusion_Range_A [07:00] */ /* XPT_RAVE :: CX23_AV_COMP2_FILTER_MASK_VAL :: Inclusion_Range_A :: COMP2_RANGEA_LO [07:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_AV_COMP2_FILTER_MASK_VAL_Inclusion_Range_A_COMP2_RANGEA_LO_SHIFT 0 /*************************************************************************** *CX23_AV_COMP12_FILTER_MODE - Context Comparator 1 32-bit mask value ***************************************************************************/ /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_D [31:30] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_MASK 0xc0000000 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_D_SHIFT 30 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_D [29:28] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_MASK 0x30000000 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_D_SHIFT 28 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_C [27:26] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_MASK 0x0c000000 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_C_SHIFT 26 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_C [25:24] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_MASK 0x03000000 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_C_SHIFT 24 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_B [23:22] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_B_SHIFT 22 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_B [21:20] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_MASK 0x00300000 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_B_SHIFT 20 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_FUNC_A [19:18] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_MASK 0x000c0000 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_FUNC_A_SHIFT 18 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP1_FILT_OFFSET_A [17:16] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_MASK 0x00030000 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP1_FILT_OFFSET_A_SHIFT 16 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_D [15:14] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_MASK 0x0000c000 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_D_SHIFT 14 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_D [13:12] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_MASK 0x00003000 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_D_SHIFT 12 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_C [11:10] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_MASK 0x00000c00 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_C_SHIFT 10 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_C [09:08] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_MASK 0x00000300 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_C_SHIFT 8 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_B [07:06] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_B_SHIFT 6 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_B [05:04] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_MASK 0x00000030 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_B_SHIFT 4 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_FUNC_A [03:02] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_MASK 0x0000000c #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_FUNC_A_SHIFT 2 /* XPT_RAVE :: CX23_AV_COMP12_FILTER_MODE :: COMP2_FILT_OFFSET_A [01:00] */ #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_MASK 0x00000003 #define BCHP_XPT_RAVE_CX23_AV_COMP12_FILTER_MODE_COMP2_FILT_OFFSET_A_SHIFT 0 /*************************************************************************** *CX23_AV_PID_STREAM_ID - Context PID and Stream ID Filter Value ***************************************************************************/ /* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: PRV_HDR_ITB_EN [31:31] */ #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_PRV_HDR_ITB_EN_SHIFT 31 /* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: PID_VALID [30:30] */ #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_PID_VALID_MASK 0x40000000 #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_PID_VALID_SHIFT 30 /* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: AUD_FRAME_INFO [29:26] */ #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_AUD_FRAME_INFO_MASK 0x3c000000 #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_AUD_FRAME_INFO_SHIFT 26 /* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: SSID_ENABLE [25:25] */ #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_SSID_ENABLE_MASK 0x02000000 #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_SSID_ENABLE_SHIFT 25 /* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: SPLICE_EN [24:24] */ #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_SPLICE_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_SPLICE_EN_SHIFT 24 /* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: reserved_for_eco0 [23:21] */ #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_reserved_for_eco0_MASK 0x00e00000 #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: BAND_NUM [20:16] */ #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_BAND_NUM_MASK 0x001f0000 #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_BAND_NUM_SHIFT 16 /* XPT_RAVE :: CX23_AV_PID_STREAM_ID :: FILTER_PID_STREAM_ID [15:00] */ #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX23_AV_PID_STREAM_ID_FILTER_PID_STREAM_ID_SHIFT 0 /*************************************************************************** *CX23_REC_CTRL1 - Record Control Register 1 ***************************************************************************/ /* XPT_RAVE :: CX23_REC_CTRL1 :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CX23_REC_CTRL1_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX23_REC_CTRL1_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CX23_REC_CTRL1 :: DTV2MPEG_PADNUM [15:08] */ #define BCHP_XPT_RAVE_CX23_REC_CTRL1_DTV2MPEG_PADNUM_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_REC_CTRL1_DTV2MPEG_PADNUM_SHIFT 8 /* XPT_RAVE :: CX23_REC_CTRL1 :: reserved_for_eco1 [07:06] */ #define BCHP_XPT_RAVE_CX23_REC_CTRL1_reserved_for_eco1_MASK 0x000000c0 #define BCHP_XPT_RAVE_CX23_REC_CTRL1_reserved_for_eco1_SHIFT 6 /* XPT_RAVE :: CX23_REC_CTRL1 :: ATSC_SCRAM_CTRL [05:05] */ #define BCHP_XPT_RAVE_CX23_REC_CTRL1_ATSC_SCRAM_CTRL_MASK 0x00000020 #define BCHP_XPT_RAVE_CX23_REC_CTRL1_ATSC_SCRAM_CTRL_SHIFT 5 /* XPT_RAVE :: CX23_REC_CTRL1 :: PARSE_SC [04:04] */ #define BCHP_XPT_RAVE_CX23_REC_CTRL1_PARSE_SC_MASK 0x00000010 #define BCHP_XPT_RAVE_CX23_REC_CTRL1_PARSE_SC_SHIFT 4 /* XPT_RAVE :: CX23_REC_CTRL1 :: SEAMLESS_PAUSE_MODE [03:03] */ #define BCHP_XPT_RAVE_CX23_REC_CTRL1_SEAMLESS_PAUSE_MODE_MASK 0x00000008 #define BCHP_XPT_RAVE_CX23_REC_CTRL1_SEAMLESS_PAUSE_MODE_SHIFT 3 /* XPT_RAVE :: CX23_REC_CTRL1 :: DTV_PF_TOGGLE_DIS [02:02] */ #define BCHP_XPT_RAVE_CX23_REC_CTRL1_DTV_PF_TOGGLE_DIS_MASK 0x00000004 #define BCHP_XPT_RAVE_CX23_REC_CTRL1_DTV_PF_TOGGLE_DIS_SHIFT 2 /* XPT_RAVE :: CX23_REC_CTRL1 :: REC_DTV2MPG_EN [01:01] */ #define BCHP_XPT_RAVE_CX23_REC_CTRL1_REC_DTV2MPG_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_CX23_REC_CTRL1_REC_DTV2MPG_EN_SHIFT 1 /* XPT_RAVE :: CX23_REC_CTRL1 :: REC_TIMESTAMP_ENABLE [00:00] */ #define BCHP_XPT_RAVE_CX23_REC_CTRL1_REC_TIMESTAMP_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_CX23_REC_CTRL1_REC_TIMESTAMP_ENABLE_SHIFT 0 /*************************************************************************** *CX23_REC_INIT_TS - Record Initial Timestamp Value Register ***************************************************************************/ /* XPT_RAVE :: CX23_REC_INIT_TS :: INIT_TS [31:00] */ #define BCHP_XPT_RAVE_CX23_REC_INIT_TS_INIT_TS_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_REC_INIT_TS_INIT_TS_SHIFT 0 /*************************************************************************** *CX23_REC_TS_CTRL - Record Timestamp Control Register ***************************************************************************/ /* XPT_RAVE :: CX23_REC_TS_CTRL :: reserved_for_eco0 [31:06] */ #define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_reserved_for_eco0_MASK 0xffffffc0 #define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_reserved_for_eco0_SHIFT 6 /* XPT_RAVE :: CX23_REC_TS_CTRL :: TS_CHECK_DIS [05:05] */ #define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_CHECK_DIS_MASK 0x00000020 #define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_CHECK_DIS_SHIFT 5 /* XPT_RAVE :: CX23_REC_TS_CTRL :: REC_TIMESTAMP_MODE [04:03] */ #define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_REC_TIMESTAMP_MODE_MASK 0x00000018 #define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_REC_TIMESTAMP_MODE_SHIFT 3 /* XPT_RAVE :: CX23_REC_TS_CTRL :: TS_INIT_EN [02:02] */ #define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_INIT_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_INIT_EN_SHIFT 2 /* XPT_RAVE :: CX23_REC_TS_CTRL :: TS_USER_BITS [01:00] */ #define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_USER_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_CX23_REC_TS_CTRL_TS_USER_BITS_SHIFT 0 /*************************************************************************** *CX23_REC_TIME_CONFIG - Record Time Configuration Register ***************************************************************************/ /* XPT_RAVE :: CX23_REC_TIME_CONFIG :: reserved_for_eco0 [31:25] */ #define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_reserved_for_eco0_MASK 0xfe000000 #define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_reserved_for_eco0_SHIFT 25 /* XPT_RAVE :: CX23_REC_TIME_CONFIG :: REC_COUNT_MODE [24:24] */ #define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_REC_COUNT_MODE_MASK 0x01000000 #define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_REC_COUNT_MODE_SHIFT 24 /* XPT_RAVE :: CX23_REC_TIME_CONFIG :: REC_TIMEOUT_VAL [23:00] */ #define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_REC_TIMEOUT_VAL_MASK 0x00ffffff #define BCHP_XPT_RAVE_CX23_REC_TIME_CONFIG_REC_TIMEOUT_VAL_SHIFT 0 /*************************************************************************** *CX23_AV_MISC_CONFIG4 - Context Miscellaneous Config 4 Register ***************************************************************************/ /* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: RESERVED_CONFIG [31:24] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_RESERVED_CONFIG_MASK 0xff000000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_RESERVED_CONFIG_SHIFT 24 /* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: reserved_for_eco0 [23:23] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco0_MASK 0x00800000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco0_SHIFT 23 /* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: PES_SID_EXT_DEP [22:16] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_DEP_MASK 0x007f0000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_DEP_SHIFT 16 /* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: PES_SID_EXT_IND [14:08] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_IND_MASK 0x00007f00 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_IND_SHIFT 8 /* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: reserved_for_eco2 [07:02] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco2_MASK 0x000000fc #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_reserved_for_eco2_SHIFT 2 /* XPT_RAVE :: CX23_AV_MISC_CONFIG4 :: PES_SID_EXT_MODE [01:00] */ #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_CX23_AV_MISC_CONFIG4_PES_SID_EXT_MODE_SHIFT 0 /*************************************************************************** *CX23_PIC_CTR - Picture Counter register ***************************************************************************/ /* XPT_RAVE :: CX23_PIC_CTR :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_CX23_PIC_CTR_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CX23_PIC_CTR_reserved0_SHIFT 16 /* XPT_RAVE :: CX23_PIC_CTR :: VALUE [15:00] */ #define BCHP_XPT_RAVE_CX23_PIC_CTR_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX23_PIC_CTR_VALUE_SHIFT 0 /*************************************************************************** *CX23_PIC_CTR_MODE - Picture Counter Mode Register ***************************************************************************/ /* XPT_RAVE :: CX23_PIC_CTR_MODE :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_reserved0_SHIFT 31 /* XPT_RAVE :: CX23_PIC_CTR_MODE :: Valid_PIC_CTR_VALUE [30:28] */ #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_MASK 0x70000000 #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_Valid_PIC_CTR_VALUE_SHIFT 28 /* XPT_RAVE :: CX23_PIC_CTR_MODE :: PIC_CTR_EN [27:27] */ #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_PIC_CTR_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_PIC_CTR_EN_SHIFT 27 /* XPT_RAVE :: CX23_PIC_CTR_MODE :: reserved1 [26:26] */ #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_reserved1_MASK 0x04000000 #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_reserved1_SHIFT 26 /* XPT_RAVE :: CX23_PIC_CTR_MODE :: PIC_CTR_MODE [25:24] */ #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_PIC_CTR_MODE_MASK 0x03000000 #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_PIC_CTR_MODE_SHIFT 24 /* XPT_RAVE :: CX23_PIC_CTR_MODE :: SCV0 [23:16] */ #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV0_MASK 0x00ff0000 #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV0_SHIFT 16 /* XPT_RAVE :: CX23_PIC_CTR_MODE :: SCV1 [15:08] */ #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV1_SHIFT 8 /* XPT_RAVE :: CX23_PIC_CTR_MODE :: SCV2 [07:00] */ #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV2_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_PIC_CTR_MODE_SCV2_SHIFT 0 /*************************************************************************** *CX23_REC_TIMER - Record Timer Register ***************************************************************************/ /* XPT_RAVE :: CX23_REC_TIMER :: REC_TIMER [31:00] */ #define BCHP_XPT_RAVE_CX23_REC_TIMER_REC_TIMER_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_REC_TIMER_REC_TIMER_SHIFT 0 /*************************************************************************** *CX23_REC_STATE0 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX23_REC_STATE0 :: reserved_for_eco0 [31:18] */ #define BCHP_XPT_RAVE_CX23_REC_STATE0_reserved_for_eco0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX23_REC_STATE0_reserved_for_eco0_SHIFT 18 /* XPT_RAVE :: CX23_REC_STATE0 :: REC_INIT_TIME_LO [17:08] */ #define BCHP_XPT_RAVE_CX23_REC_STATE0_REC_INIT_TIME_LO_MASK 0x0003ff00 #define BCHP_XPT_RAVE_CX23_REC_STATE0_REC_INIT_TIME_LO_SHIFT 8 /* XPT_RAVE :: CX23_REC_STATE0 :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_CX23_REC_STATE0_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_CX23_REC_STATE0_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: CX23_REC_STATE0 :: LAST_CONV_TIME_STAMP_HI [03:02] */ #define BCHP_XPT_RAVE_CX23_REC_STATE0_LAST_CONV_TIME_STAMP_HI_MASK 0x0000000c #define BCHP_XPT_RAVE_CX23_REC_STATE0_LAST_CONV_TIME_STAMP_HI_SHIFT 2 /* XPT_RAVE :: CX23_REC_STATE0 :: TS_INITIALIZED [01:01] */ #define BCHP_XPT_RAVE_CX23_REC_STATE0_TS_INITIALIZED_MASK 0x00000002 #define BCHP_XPT_RAVE_CX23_REC_STATE0_TS_INITIALIZED_SHIFT 1 /* XPT_RAVE :: CX23_REC_STATE0 :: REC_INITIALIZED [00:00] */ #define BCHP_XPT_RAVE_CX23_REC_STATE0_REC_INITIALIZED_MASK 0x00000001 #define BCHP_XPT_RAVE_CX23_REC_STATE0_REC_INITIALIZED_SHIFT 0 /*************************************************************************** *CX23_REC_STATE1 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX23_REC_STATE1 :: REC_INIT_TIME_HI [31:00] */ #define BCHP_XPT_RAVE_CX23_REC_STATE1_REC_INIT_TIME_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_REC_STATE1_REC_INIT_TIME_HI_SHIFT 0 /*************************************************************************** *CX23_REC_STATE2 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX23_REC_STATE2 :: INT_TIME_STAMP [31:00] */ #define BCHP_XPT_RAVE_CX23_REC_STATE2_INT_TIME_STAMP_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_REC_STATE2_INT_TIME_STAMP_SHIFT 0 /*************************************************************************** *CX23_REC_STATE2b - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX23_REC_STATE2b :: LAST_CONV_TIME_STAMP_LO [31:00] */ #define BCHP_XPT_RAVE_CX23_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_REC_STATE2b_LAST_CONV_TIME_STAMP_LO_SHIFT 0 /*************************************************************************** *CX23_REC_STATE3 - Record State Register ***************************************************************************/ /* XPT_RAVE :: CX23_REC_STATE3 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_CX23_REC_STATE3_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_CX23_REC_STATE3_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: CX23_REC_STATE3 :: REC_DSS_PARITY [08:08] */ #define BCHP_XPT_RAVE_CX23_REC_STATE3_REC_DSS_PARITY_MASK 0x00000100 #define BCHP_XPT_RAVE_CX23_REC_STATE3_REC_DSS_PARITY_SHIFT 8 /* XPT_RAVE :: CX23_REC_STATE3 :: REC_COUNT_HI [07:00] */ #define BCHP_XPT_RAVE_CX23_REC_STATE3_REC_COUNT_HI_MASK 0x000000ff #define BCHP_XPT_RAVE_CX23_REC_STATE3_REC_COUNT_HI_SHIFT 0 /*************************************************************************** *CX23_REC_COUNT - Record Packet Count Register ***************************************************************************/ /* XPT_RAVE :: CX23_REC_COUNT :: REC_COUNT [31:00] */ #define BCHP_XPT_RAVE_CX23_REC_COUNT_REC_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_REC_COUNT_REC_COUNT_SHIFT 0 /*************************************************************************** *CX23_PIC_INC_DEC_CTRL - Picture Counter Increment/Decrement/Reset Control Register ***************************************************************************/ /* XPT_RAVE :: CX23_PIC_INC_DEC_CTRL :: reserved0 [31:18] */ #define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_reserved0_SHIFT 18 /* XPT_RAVE :: CX23_PIC_INC_DEC_CTRL :: INC_DEC_MODE [17:16] */ #define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_INC_DEC_MODE_MASK 0x00030000 #define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_INC_DEC_MODE_SHIFT 16 /* XPT_RAVE :: CX23_PIC_INC_DEC_CTRL :: INC_DEC_VALUE [15:00] */ #define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_INC_DEC_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_CX23_PIC_INC_DEC_CTRL_INC_DEC_VALUE_SHIFT 0 /*************************************************************************** *CX23_REC_RESERVE_STATE1 - Reserved Record State Register ***************************************************************************/ /* XPT_RAVE :: CX23_REC_RESERVE_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX23_REC_RESERVE_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_REC_RESERVE_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX23_RAVE_Reg_0 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX23_RAVE_Reg_0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX23_RAVE_Reg_0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_RAVE_Reg_0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX23_RAVE_Reg_1 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX23_RAVE_Reg_1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX23_RAVE_Reg_1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_RAVE_Reg_1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX23_RAVE_Reg_2 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX23_RAVE_Reg_2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX23_RAVE_Reg_2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_RAVE_Reg_2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *CX23_RAVE_Reg_3 - Reserved Rave Register for future use ***************************************************************************/ /* XPT_RAVE :: CX23_RAVE_Reg_3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_CX23_RAVE_Reg_3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_CX23_RAVE_Reg_3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_MISC_CONFIG - SCD 0 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD0_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD0_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD0_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD0_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD0_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD0_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD0_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD0_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD0_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD0_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD0_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD0_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD0_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD0_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD0_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD0_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD0_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD0_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD0_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD0_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD0_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD0_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD0_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_MISC_CONFIG - SCD 1 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD1_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD1_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD1_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD1_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD1_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD1_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD1_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD1_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD1_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD1_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD1_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD1_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD1_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD1_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD1_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD1_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD1_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD1_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD1_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD1_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD1_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD1_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD1_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_MISC_CONFIG - SCD 2 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD2_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD2_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD2_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD2_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD2_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD2_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD2_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD2_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD2_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD2_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD2_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD2_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD2_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD2_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD2_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD2_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD2_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD2_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD2_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD2_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD2_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD2_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD2_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_MISC_CONFIG - SCD 3 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD3_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD3_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD3_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD3_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD3_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD3_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD3_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD3_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD3_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD3_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD3_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD3_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD3_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD3_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD3_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD3_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD3_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD3_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD3_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD3_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD3_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD3_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD3_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_MISC_CONFIG - SCD 4 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD4_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD4_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD4_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD4_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD4_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD4_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD4_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD4_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD4_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD4_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD4_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD4_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD4_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD4_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD4_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD4_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD4_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD4_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD4_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD4_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD4_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD4_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD4_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_MISC_CONFIG - SCD 5 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD5_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD5_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD5_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD5_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD5_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD5_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD5_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD5_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD5_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD5_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD5_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD5_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD5_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD5_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD5_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD5_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD5_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD5_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD5_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD5_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD5_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD5_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD5_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_MISC_CONFIG - SCD 6 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD6_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD6_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD6_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD6_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD6_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD6_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD6_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD6_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD6_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD6_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD6_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD6_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD6_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD6_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD6_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD6_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD6_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD6_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD6_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD6_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD6_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD6_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD6_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_MISC_CONFIG - SCD 7 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD7_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD7_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD7_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD7_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD7_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD7_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD7_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD7_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD7_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD7_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD7_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD7_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD7_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD7_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD7_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD7_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD7_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD7_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD7_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD7_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD7_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD7_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD7_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_MISC_CONFIG - SCD 8 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD8_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD8_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD8_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD8_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD8_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD8_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD8_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD8_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD8_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD8_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD8_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD8_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD8_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD8_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD8_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD8_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD8_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD8_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD8_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD8_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD8_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD8_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD8_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_MISC_CONFIG - SCD 9 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD9_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD9_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD9_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD9_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD9_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD9_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD9_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD9_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD9_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD9_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD9_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD9_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD9_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD9_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD9_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD9_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD9_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD9_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD9_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD9_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD9_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD9_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD9_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_MISC_CONFIG - SCD 10 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD10_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD10_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD10_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD10_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD10_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD10_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD10_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD10_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD10_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD10_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD10_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD10_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD10_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD10_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD10_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD10_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD10_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD10_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD10_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD10_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD10_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD10_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD10_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_MISC_CONFIG - SCD 11 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD11_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD11_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD11_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD11_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD11_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD11_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD11_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD11_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD11_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD11_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD11_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD11_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD11_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD11_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD11_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD11_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD11_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD11_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD11_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD11_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD11_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD11_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD11_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_MISC_CONFIG - SCD 12 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD12_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD12_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD12_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD12_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD12_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD12_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD12_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD12_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD12_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD12_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD12_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD12_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD12_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD12_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD12_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD12_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD12_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD12_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD12_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD12_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD12_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD12_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD12_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_MISC_CONFIG - SCD 13 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD13_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD13_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD13_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD13_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD13_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD13_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD13_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD13_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD13_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD13_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD13_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD13_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD13_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD13_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD13_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD13_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD13_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD13_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD13_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD13_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD13_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD13_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD13_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_MISC_CONFIG - SCD 14 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD14_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD14_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD14_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD14_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD14_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD14_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD14_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD14_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD14_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD14_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD14_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD14_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD14_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD14_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD14_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD14_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD14_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD14_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD14_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD14_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD14_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD14_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD14_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_MISC_CONFIG - SCD 15 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD15_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD15_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD15_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD15_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD15_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD15_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD15_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD15_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD15_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD15_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD15_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD15_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD15_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD15_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD15_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD15_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD15_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD15_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD15_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD15_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD15_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD15_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD15_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_MISC_CONFIG - SCD 16 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD16_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD16_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD16_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD16_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD16_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD16_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD16_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD16_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD16_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD16_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD16_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD16_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD16_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD16_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD16_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD16_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD16_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD16_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD16_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD16_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD16_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD16_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD16_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_MISC_CONFIG - SCD 17 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD17_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD17_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD17_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD17_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD17_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD17_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD17_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD17_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD17_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD17_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD17_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD17_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD17_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD17_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD17_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD17_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD17_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD17_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD17_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD17_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD17_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD17_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD17_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_MISC_CONFIG - SCD 18 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD18_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD18_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD18_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD18_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD18_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD18_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD18_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD18_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD18_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD18_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD18_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD18_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD18_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD18_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD18_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD18_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD18_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD18_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD18_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD18_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD18_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD18_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD18_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_MISC_CONFIG - SCD 19 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD19_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD19_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD19_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD19_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD19_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD19_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD19_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD19_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD19_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD19_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD19_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD19_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD19_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD19_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD19_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD19_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD19_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD19_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD19_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD19_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD19_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD19_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD19_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_MISC_CONFIG - SCD 20 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD20_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD20_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD20_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD20_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD20_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD20_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD20_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD20_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD20_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD20_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD20_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD20_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD20_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD20_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD20_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD20_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD20_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD20_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD20_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD20_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD20_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD20_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD20_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_MISC_CONFIG - SCD 21 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD21_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD21_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD21_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD21_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD21_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD21_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD21_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD21_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD21_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD21_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD21_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD21_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD21_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD21_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD21_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD21_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD21_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD21_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD21_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD21_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD21_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD21_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD21_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_MISC_CONFIG - SCD 22 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD22_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD22_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD22_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD22_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD22_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD22_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD22_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD22_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD22_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD22_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD22_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD22_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD22_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD22_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD22_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD22_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD22_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD22_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD22_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD22_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD22_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD22_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD22_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_MISC_CONFIG - SCD 23 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD23_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD23_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD23_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD23_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD23_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD23_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD23_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD23_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD23_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD23_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD23_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD23_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD23_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD23_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD23_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD23_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD23_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD23_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD23_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD23_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD23_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD23_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD23_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_MISC_CONFIG - SCD 24 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD24_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD24_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD24_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD24_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD24_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD24_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD24_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD24_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD24_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD24_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD24_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD24_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD24_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD24_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD24_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD24_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD24_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD24_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD24_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD24_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD24_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD24_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD24_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_MISC_CONFIG - SCD 25 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD25_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD25_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD25_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD25_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD25_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD25_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD25_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD25_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD25_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD25_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD25_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD25_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD25_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD25_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD25_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD25_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD25_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD25_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD25_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD25_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD25_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD25_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD25_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_MISC_CONFIG - SCD 26 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD26_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD26_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD26_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD26_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD26_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD26_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD26_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD26_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD26_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD26_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD26_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD26_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD26_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD26_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD26_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD26_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD26_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD26_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD26_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD26_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD26_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD26_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD26_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_MISC_CONFIG - SCD 27 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD27_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD27_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD27_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD27_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD27_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD27_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD27_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD27_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD27_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD27_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD27_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD27_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD27_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD27_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD27_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD27_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD27_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD27_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD27_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD27_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD27_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD27_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD27_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_MISC_CONFIG - SCD 28 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD28_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD28_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD28_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD28_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD28_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD28_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD28_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD28_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD28_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD28_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD28_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD28_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD28_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD28_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD28_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD28_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD28_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD28_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD28_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD28_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD28_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD28_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD28_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_MISC_CONFIG - SCD 29 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD29_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD29_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD29_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD29_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD29_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD29_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD29_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD29_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD29_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD29_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD29_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD29_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD29_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD29_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD29_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD29_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD29_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD29_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD29_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD29_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD29_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD29_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD29_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_MISC_CONFIG - SCD 30 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD30_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD30_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD30_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD30_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD30_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD30_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD30_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD30_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD30_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD30_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD30_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD30_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD30_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD30_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD30_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD30_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD30_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD30_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD30_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD30_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD30_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD30_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD30_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_MISC_CONFIG - SCD 31 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD31_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD31_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD31_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD31_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD31_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD31_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD31_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD31_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD31_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD31_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD31_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD31_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD31_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD31_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD31_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD31_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD31_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD31_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD31_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD31_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD31_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD31_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD31_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_MISC_CONFIG - SCD 32 Misc Config Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_MISC_CONFIG :: reserved_for_eco0 [31:11] */ #define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG_reserved_for_eco0_MASK 0xfffff800 #define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG_reserved_for_eco0_SHIFT 11 /* XPT_RAVE :: SCD32_SCD_MISC_CONFIG :: CONTEXT_DMEM_BASE [10:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_MASK 0x000007ff #define BCHP_XPT_RAVE_SCD32_SCD_MISC_CONFIG_CONTEXT_DMEM_BASE_SHIFT 0 /*************************************************************************** *SCD32_SCD_COMP_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_COMP_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_COMP_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_COMP_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_COMP_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_COMP_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_COMP_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_COMP_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_COMP_STATE4 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE4_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE4_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_COMP_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_COMP_STATE5 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE5_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE5_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_COMP_STATE6 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_COMP_STATE6 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE6_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE6_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_COMP_STATE7 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_COMP_STATE7 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE7_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE7_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_COMP_STATE8 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_COMP_STATE8 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE8_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE8_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_COMP_STATE9 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_COMP_STATE9 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE9_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE9_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_COMP_STATE10 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_COMP_STATE10 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE10_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE10_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_COMP_STATE11 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_COMP_STATE11 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE11_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_COMP_STATE11_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_RESERVE_COMP_STATE0 - Reserved Comparator State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_RESERVE_COMP_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_RESERVE_COMP_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_RESERVE_COMP_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_PES_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_PES_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_PES_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_PES_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_PES_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_PES_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_PES_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_PACKET_COUNT - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_PACKET_COUNT :: CX_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_PACKET_COUNT_CX_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_PACKET_COUNT_CX_PACKET_COUNT_SHIFT 0 /*************************************************************************** *SCD32_RESERVE_PES_STATE0 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_RESERVE_PES_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_RESERVE_PES_STATE1 - Reserved PES State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_RESERVE_PES_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_RESERVE_PES_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_SCD_STATE0 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_STATE0 :: COUNT_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_STATE0_COUNT_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_STATE0_COUNT_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD32_SCD_STATE1 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_STATE1 :: COUNT_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_STATE1_COUNT_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_STATE1_COUNT_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD32_SCD_STATE2 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_STATE2 :: COUNT_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD32_SCD_STATE2_COUNT_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD32_SCD_STATE2_COUNT_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD32_SCD_STATE2 :: COUNT_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_STATE2_COUNT_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD32_SCD_STATE2_COUNT_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD32_SCD_STATE3 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_STATE3 :: MATCH_STACK1_HI [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_STATE3_MATCH_STACK1_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_STATE3_MATCH_STACK1_HI_SHIFT 0 /*************************************************************************** *SCD32_SCD_STATE4 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_STATE4 :: MATCH_STACK0_HI [31:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_STATE4_MATCH_STACK0_HI_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_SCD_STATE4_MATCH_STACK0_HI_SHIFT 0 /*************************************************************************** *SCD32_SCD_STATE5 - SCD State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_SCD_STATE5 :: MATCH_STACK1_LO [31:16] */ #define BCHP_XPT_RAVE_SCD32_SCD_STATE5_MATCH_STACK1_LO_MASK 0xffff0000 #define BCHP_XPT_RAVE_SCD32_SCD_STATE5_MATCH_STACK1_LO_SHIFT 16 /* XPT_RAVE :: SCD32_SCD_STATE5 :: MATCH_STACK0_LO [15:00] */ #define BCHP_XPT_RAVE_SCD32_SCD_STATE5_MATCH_STACK0_LO_MASK 0x0000ffff #define BCHP_XPT_RAVE_SCD32_SCD_STATE5_MATCH_STACK0_LO_SHIFT 0 /*************************************************************************** *SCD32_RESERVED_STATE0 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_RESERVED_STATE0 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_RESERVED_STATE0_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_RESERVED_STATE0_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_RESERVED_STATE1 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_RESERVED_STATE1 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_RESERVED_STATE1_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_RESERVED_STATE1_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_RESERVED_STATE2 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_RESERVED_STATE2 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_RESERVED_STATE2_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_RESERVED_STATE2_reserved_for_eco0_SHIFT 0 /*************************************************************************** *SCD32_RESERVED_STATE3 - SCD Reserved State Register ***************************************************************************/ /* XPT_RAVE :: SCD32_RESERVED_STATE3 :: reserved_for_eco0 [31:00] */ #define BCHP_XPT_RAVE_SCD32_RESERVED_STATE3_reserved_for_eco0_MASK 0xffffffff #define BCHP_XPT_RAVE_SCD32_RESERVED_STATE3_reserved_for_eco0_SHIFT 0 /*************************************************************************** *XPU_CONFIG - XPU TEST ENABLE REGISTER ***************************************************************************/ /* XPT_RAVE :: XPU_CONFIG :: reserved0 [31:01] */ #define BCHP_XPT_RAVE_XPU_CONFIG_reserved0_MASK 0xfffffffe #define BCHP_XPT_RAVE_XPU_CONFIG_reserved0_SHIFT 1 /* XPT_RAVE :: XPU_CONFIG :: TEST_ENABLE [00:00] */ #define BCHP_XPT_RAVE_XPU_CONFIG_TEST_ENABLE_MASK 0x00000001 #define BCHP_XPT_RAVE_XPU_CONFIG_TEST_ENABLE_SHIFT 0 /*************************************************************************** *XPU_TEST_CONTROL - XPU TEST CONTROL REGISTER ***************************************************************************/ /* XPT_RAVE :: XPU_TEST_CONTROL :: reserved0 [31:04] */ #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_reserved0_MASK 0xfffffff0 #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_reserved0_SHIFT 4 /* XPT_RAVE :: XPU_TEST_CONTROL :: EXT_IN [03:02] */ #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IN_MASK 0x0000000c #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IN_SHIFT 2 /* XPT_RAVE :: XPU_TEST_CONTROL :: WAKE [01:01] */ #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_WAKE_MASK 0x00000002 #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_WAKE_SHIFT 1 /* XPT_RAVE :: XPU_TEST_CONTROL :: INTR [00:00] */ #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_INTR_MASK 0x00000001 #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_INTR_SHIFT 0 /*************************************************************************** *XPU_TEST_CONTROL_EXT_IO - XPU TEST CONTROL EXT IO ***************************************************************************/ /* XPT_RAVE :: XPU_TEST_CONTROL_EXT_IO :: reserved0 [31:09] */ #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_reserved0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_reserved0_SHIFT 9 /* XPT_RAVE :: XPU_TEST_CONTROL_EXT_IO :: WAIT [08:08] */ #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_WAIT_MASK 0x00000100 #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_WAIT_SHIFT 8 /* XPT_RAVE :: XPU_TEST_CONTROL_EXT_IO :: RD_DATA [07:00] */ #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_RD_DATA_MASK 0x000000ff #define BCHP_XPT_RAVE_XPU_TEST_CONTROL_EXT_IO_RD_DATA_SHIFT 0 /*************************************************************************** *XPU_TEST_OBSERVE_0 - XPU TEST OBSERVE REGISTER ***************************************************************************/ /* XPT_RAVE :: XPU_TEST_OBSERVE_0 :: reserved0 [31:02] */ #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0_reserved0_MASK 0xfffffffc #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0_reserved0_SHIFT 2 /* XPT_RAVE :: XPU_TEST_OBSERVE_0 :: P_BITS [01:00] */ #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0_P_BITS_MASK 0x00000003 #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_0_P_BITS_SHIFT 0 /*************************************************************************** *XPU_TEST_OBSERVE_1 - XPU TEST OBSERVE REGISTER ***************************************************************************/ /* XPT_RAVE :: XPU_TEST_OBSERVE_1 :: reserved0 [31:31] */ #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_reserved0_MASK 0x80000000 #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_reserved0_SHIFT 31 /* XPT_RAVE :: XPU_TEST_OBSERVE_1 :: DEBUG_PSW [30:20] */ #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_PSW_MASK 0x7ff00000 #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_PSW_SHIFT 20 /* XPT_RAVE :: XPU_TEST_OBSERVE_1 :: DEBUG_PC [19:08] */ #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_PC_MASK 0x000fff00 #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_PC_SHIFT 8 /* XPT_RAVE :: XPU_TEST_OBSERVE_1 :: DEBUG_DATA [07:00] */ #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_DATA_MASK 0x000000ff #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_1_DEBUG_DATA_SHIFT 0 /*************************************************************************** *XPU_TEST_OBSERVE_EXT_IO - XPU TEST OBSERVE EXT IO REGISTER ***************************************************************************/ /* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: reserved0 [31:22] */ #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_reserved0_MASK 0xffc00000 #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_reserved0_SHIFT 22 /* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: ADDR [21:10] */ #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_ADDR_MASK 0x003ffc00 #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_ADDR_SHIFT 10 /* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: WR_DATA [09:02] */ #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_WR_DATA_MASK 0x000003fc #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_WR_DATA_SHIFT 2 /* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: RD_STROBE [01:01] */ #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_RD_STROBE_MASK 0x00000002 #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_RD_STROBE_SHIFT 1 /* XPT_RAVE :: XPU_TEST_OBSERVE_EXT_IO :: WR_STROBE [00:00] */ #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_WR_STROBE_MASK 0x00000001 #define BCHP_XPT_RAVE_XPU_TEST_OBSERVE_EXT_IO_WR_STROBE_SHIFT 0 /*************************************************************************** *RAVE_DIAGNOSTICS_CONTROL - RAVE Diagnostics Control Register ***************************************************************************/ /* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: reserved0 [31:14] */ #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_reserved0_MASK 0xffffc000 #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_reserved0_SHIFT 14 /* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: UPPER_TESTBUS_SEL [13:09] */ #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_UPPER_TESTBUS_SEL_MASK 0x00003e00 #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_UPPER_TESTBUS_SEL_SHIFT 9 /* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: LOWER_TESTBUS_SEL [08:04] */ #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_LOWER_TESTBUS_SEL_MASK 0x000001f0 #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_LOWER_TESTBUS_SEL_SHIFT 4 /* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: reserved_for_eco1 [03:03] */ #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_reserved_for_eco1_MASK 0x00000008 #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_reserved_for_eco1_SHIFT 3 /* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: NEXT_BREAKPOINT [02:02] */ #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_NEXT_BREAKPOINT_MASK 0x00000004 #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_NEXT_BREAKPOINT_SHIFT 2 /* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: BREAKPOINT_EN [01:01] */ #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_BREAKPOINT_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_BREAKPOINT_EN_SHIFT 1 /* XPT_RAVE :: RAVE_DIAGNOSTICS_CONTROL :: DIAG_EN [00:00] */ #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_DIAG_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_RAVE_DIAGNOSTICS_CONTROL_DIAG_EN_SHIFT 0 /*************************************************************************** *STOP_PACKET_COUNT_VALUE - Stop Packet Count Value ***************************************************************************/ /* XPT_RAVE :: STOP_PACKET_COUNT_VALUE :: STOP_PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_STOP_PACKET_COUNT_VALUE_STOP_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_STOP_PACKET_COUNT_VALUE_STOP_PACKET_COUNT_SHIFT 0 /*************************************************************************** *AVS_SCV_FILTER_MODE_CONTROL - AVS SCV Filter mode ***************************************************************************/ /* XPT_RAVE :: AVS_SCV_FILTER_MODE_CONTROL :: reserved0 [31:02] */ #define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL_reserved0_MASK 0xfffffffc #define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL_reserved0_SHIFT 2 /* XPT_RAVE :: AVS_SCV_FILTER_MODE_CONTROL :: AVS_SCV_FILTER_MODE [01:00] */ #define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL_AVS_SCV_FILTER_MODE_MASK 0x00000003 #define BCHP_XPT_RAVE_AVS_SCV_FILTER_MODE_CONTROL_AVS_SCV_FILTER_MODE_SHIFT 0 /*************************************************************************** *AVS_SCV_FILTER_VALUE_0_TO_3 - AVS SCV Filter value 0 to 3 ***************************************************************************/ /* XPT_RAVE :: AVS_SCV_FILTER_VALUE_0_TO_3 :: AVS_SCV_3 [31:24] */ #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_3_MASK 0xff000000 #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_3_SHIFT 24 /* XPT_RAVE :: AVS_SCV_FILTER_VALUE_0_TO_3 :: AVS_SCV_2 [23:16] */ #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_2_MASK 0x00ff0000 #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_2_SHIFT 16 /* XPT_RAVE :: AVS_SCV_FILTER_VALUE_0_TO_3 :: AVS_SCV_1 [15:08] */ #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_1_MASK 0x0000ff00 #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_1_SHIFT 8 /* XPT_RAVE :: AVS_SCV_FILTER_VALUE_0_TO_3 :: AVS_SCV_0 [07:00] */ #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_0_MASK 0x000000ff #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_0_TO_3_AVS_SCV_0_SHIFT 0 /*************************************************************************** *AVS_SCV_FILTER_VALUE_4_TO_7 - AVS SCV Filter value 4 to 7 ***************************************************************************/ /* XPT_RAVE :: AVS_SCV_FILTER_VALUE_4_TO_7 :: AVS_SCV_7 [31:24] */ #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_7_MASK 0xff000000 #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_7_SHIFT 24 /* XPT_RAVE :: AVS_SCV_FILTER_VALUE_4_TO_7 :: AVS_SCV_6 [23:16] */ #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_6_MASK 0x00ff0000 #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_6_SHIFT 16 /* XPT_RAVE :: AVS_SCV_FILTER_VALUE_4_TO_7 :: AVS_SCV_5 [15:08] */ #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_5_MASK 0x0000ff00 #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_5_SHIFT 8 /* XPT_RAVE :: AVS_SCV_FILTER_VALUE_4_TO_7 :: AVS_SCV_4 [07:00] */ #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_4_MASK 0x000000ff #define BCHP_XPT_RAVE_AVS_SCV_FILTER_VALUE_4_TO_7_AVS_SCV_4_SHIFT 0 /*************************************************************************** *AV_STATUS - RAVE Status ***************************************************************************/ /* XPT_RAVE :: AV_STATUS :: reserved0 [31:26] */ #define BCHP_XPT_RAVE_AV_STATUS_reserved0_MASK 0xfc000000 #define BCHP_XPT_RAVE_AV_STATUS_reserved0_SHIFT 26 /* XPT_RAVE :: AV_STATUS :: XPU_RDY [25:25] */ #define BCHP_XPT_RAVE_AV_STATUS_XPU_RDY_MASK 0x02000000 #define BCHP_XPT_RAVE_AV_STATUS_XPU_RDY_SHIFT 25 /* XPT_RAVE :: AV_STATUS :: ITB_MEM_STATE_IDLE [24:24] */ #define BCHP_XPT_RAVE_AV_STATUS_ITB_MEM_STATE_IDLE_MASK 0x01000000 #define BCHP_XPT_RAVE_AV_STATUS_ITB_MEM_STATE_IDLE_SHIFT 24 /* XPT_RAVE :: AV_STATUS :: CDB_MEM_STATE_IDLE [23:23] */ #define BCHP_XPT_RAVE_AV_STATUS_CDB_MEM_STATE_IDLE_MASK 0x00800000 #define BCHP_XPT_RAVE_AV_STATUS_CDB_MEM_STATE_IDLE_SHIFT 23 /* XPT_RAVE :: AV_STATUS :: HWA_PKT_ACTIVE [22:22] */ #define BCHP_XPT_RAVE_AV_STATUS_HWA_PKT_ACTIVE_MASK 0x00400000 #define BCHP_XPT_RAVE_AV_STATUS_HWA_PKT_ACTIVE_SHIFT 22 /* XPT_RAVE :: AV_STATUS :: DMA_BUSY [21:21] */ #define BCHP_XPT_RAVE_AV_STATUS_DMA_BUSY_MASK 0x00200000 #define BCHP_XPT_RAVE_AV_STATUS_DMA_BUSY_SHIFT 21 /* XPT_RAVE :: AV_STATUS :: AV_MUX_BUF_OVERFLOW [20:20] */ #define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUF_OVERFLOW_MASK 0x00100000 #define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUF_OVERFLOW_SHIFT 20 /* XPT_RAVE :: AV_STATUS :: AV_MUX_BUFFER_WATERMARK [19:10] */ #define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUFFER_WATERMARK_MASK 0x000ffc00 #define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUFFER_WATERMARK_SHIFT 10 /* XPT_RAVE :: AV_STATUS :: AV_MUX_BUFFER_DEPTH [09:00] */ #define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUFFER_DEPTH_MASK 0x000003ff #define BCHP_XPT_RAVE_AV_STATUS_AV_MUX_BUFFER_DEPTH_SHIFT 0 /*************************************************************************** *PACKET_COUNT - RAVE input packet counter ***************************************************************************/ /* XPT_RAVE :: PACKET_COUNT :: PACKET_COUNT [31:00] */ #define BCHP_XPT_RAVE_PACKET_COUNT_PACKET_COUNT_MASK 0xffffffff #define BCHP_XPT_RAVE_PACKET_COUNT_PACKET_COUNT_SHIFT 0 /*************************************************************************** *DATA_START_ADDR_A - Pkt and HWA data buffer A base addresses ***************************************************************************/ /* XPT_RAVE :: DATA_START_ADDR_A :: reserved0 [31:27] */ #define BCHP_XPT_RAVE_DATA_START_ADDR_A_reserved0_MASK 0xf8000000 #define BCHP_XPT_RAVE_DATA_START_ADDR_A_reserved0_SHIFT 27 /* XPT_RAVE :: DATA_START_ADDR_A :: HWA_START [26:16] */ #define BCHP_XPT_RAVE_DATA_START_ADDR_A_HWA_START_MASK 0x07ff0000 #define BCHP_XPT_RAVE_DATA_START_ADDR_A_HWA_START_SHIFT 16 /* XPT_RAVE :: DATA_START_ADDR_A :: reserved1 [15:11] */ #define BCHP_XPT_RAVE_DATA_START_ADDR_A_reserved1_MASK 0x0000f800 #define BCHP_XPT_RAVE_DATA_START_ADDR_A_reserved1_SHIFT 11 /* XPT_RAVE :: DATA_START_ADDR_A :: PKT_START [10:00] */ #define BCHP_XPT_RAVE_DATA_START_ADDR_A_PKT_START_MASK 0x000007ff #define BCHP_XPT_RAVE_DATA_START_ADDR_A_PKT_START_SHIFT 0 /*************************************************************************** *DATA_START_ADDR_B - Pkt and HWA data buffer B base addresses ***************************************************************************/ /* XPT_RAVE :: DATA_START_ADDR_B :: reserved0 [31:27] */ #define BCHP_XPT_RAVE_DATA_START_ADDR_B_reserved0_MASK 0xf8000000 #define BCHP_XPT_RAVE_DATA_START_ADDR_B_reserved0_SHIFT 27 /* XPT_RAVE :: DATA_START_ADDR_B :: HWA_START [26:16] */ #define BCHP_XPT_RAVE_DATA_START_ADDR_B_HWA_START_MASK 0x07ff0000 #define BCHP_XPT_RAVE_DATA_START_ADDR_B_HWA_START_SHIFT 16 /* XPT_RAVE :: DATA_START_ADDR_B :: reserved1 [15:11] */ #define BCHP_XPT_RAVE_DATA_START_ADDR_B_reserved1_MASK 0x0000f800 #define BCHP_XPT_RAVE_DATA_START_ADDR_B_reserved1_SHIFT 11 /* XPT_RAVE :: DATA_START_ADDR_B :: PKT_START [10:00] */ #define BCHP_XPT_RAVE_DATA_START_ADDR_B_PKT_START_MASK 0x000007ff #define BCHP_XPT_RAVE_DATA_START_ADDR_B_PKT_START_SHIFT 0 /*************************************************************************** *WATCHDOG_TIMER_VALUE - Watchdog Timer Timeout Value ***************************************************************************/ /* XPT_RAVE :: WATCHDOG_TIMER_VALUE :: reserved0 [31:17] */ #define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_reserved0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_reserved0_SHIFT 17 /* XPT_RAVE :: WATCHDOG_TIMER_VALUE :: WATCHDOG_TIMER_ENABLE [16:16] */ #define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_WATCHDOG_TIMER_ENABLE_MASK 0x00010000 #define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_WATCHDOG_TIMER_ENABLE_SHIFT 16 /* XPT_RAVE :: WATCHDOG_TIMER_VALUE :: WATCHDOG_TIMER_LOAD_VALUE [15:00] */ #define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_WATCHDOG_TIMER_LOAD_VALUE_MASK 0x0000ffff #define BCHP_XPT_RAVE_WATCHDOG_TIMER_VALUE_WATCHDOG_TIMER_LOAD_VALUE_SHIFT 0 /*************************************************************************** *MISC_CONTROL - Miscellaneous Control ***************************************************************************/ /* XPT_RAVE :: MISC_CONTROL :: PACKET_CNT_CLR [31:31] */ #define BCHP_XPT_RAVE_MISC_CONTROL_PACKET_CNT_CLR_MASK 0x80000000 #define BCHP_XPT_RAVE_MISC_CONTROL_PACKET_CNT_CLR_SHIFT 31 /* XPT_RAVE :: MISC_CONTROL :: WMARK_GRANULARITY [30:28] */ #define BCHP_XPT_RAVE_MISC_CONTROL_WMARK_GRANULARITY_MASK 0x70000000 #define BCHP_XPT_RAVE_MISC_CONTROL_WMARK_GRANULARITY_SHIFT 28 /* XPT_RAVE :: MISC_CONTROL :: reserved_for_eco0 [27:26] */ #define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco0_MASK 0x0c000000 #define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco0_SHIFT 26 /* XPT_RAVE :: MISC_CONTROL :: NUM_CONTEXTS [25:20] */ #define BCHP_XPT_RAVE_MISC_CONTROL_NUM_CONTEXTS_MASK 0x03f00000 #define BCHP_XPT_RAVE_MISC_CONTROL_NUM_CONTEXTS_SHIFT 20 /* XPT_RAVE :: MISC_CONTROL :: EMU_STATE_CLEAR [19:19] */ #define BCHP_XPT_RAVE_MISC_CONTROL_EMU_STATE_CLEAR_MASK 0x00080000 #define BCHP_XPT_RAVE_MISC_CONTROL_EMU_STATE_CLEAR_SHIFT 19 /* XPT_RAVE :: MISC_CONTROL :: AV_WMARK_CLEAR [18:18] */ #define BCHP_XPT_RAVE_MISC_CONTROL_AV_WMARK_CLEAR_MASK 0x00040000 #define BCHP_XPT_RAVE_MISC_CONTROL_AV_WMARK_CLEAR_SHIFT 18 /* XPT_RAVE :: MISC_CONTROL :: DMA_SPEEDUP_EN [17:17] */ #define BCHP_XPT_RAVE_MISC_CONTROL_DMA_SPEEDUP_EN_MASK 0x00020000 #define BCHP_XPT_RAVE_MISC_CONTROL_DMA_SPEEDUP_EN_SHIFT 17 /* XPT_RAVE :: MISC_CONTROL :: MUX_BUFFER_SLOT_SIZE [16:16] */ #define BCHP_XPT_RAVE_MISC_CONTROL_MUX_BUFFER_SLOT_SIZE_MASK 0x00010000 #define BCHP_XPT_RAVE_MISC_CONTROL_MUX_BUFFER_SLOT_SIZE_SHIFT 16 /* XPT_RAVE :: MISC_CONTROL :: INPUT_READ_RATE [15:12] */ #define BCHP_XPT_RAVE_MISC_CONTROL_INPUT_READ_RATE_MASK 0x0000f000 #define BCHP_XPT_RAVE_MISC_CONTROL_INPUT_READ_RATE_SHIFT 12 /* XPT_RAVE :: MISC_CONTROL :: PES_COMPARATOR_RESET [11:11] */ #define BCHP_XPT_RAVE_MISC_CONTROL_PES_COMPARATOR_RESET_MASK 0x00000800 #define BCHP_XPT_RAVE_MISC_CONTROL_PES_COMPARATOR_RESET_SHIFT 11 /* XPT_RAVE :: MISC_CONTROL :: FORCE_SWITCH [10:10] */ #define BCHP_XPT_RAVE_MISC_CONTROL_FORCE_SWITCH_MASK 0x00000400 #define BCHP_XPT_RAVE_MISC_CONTROL_FORCE_SWITCH_SHIFT 10 /* XPT_RAVE :: MISC_CONTROL :: HW_FORCE_SWITCH_EN [09:09] */ #define BCHP_XPT_RAVE_MISC_CONTROL_HW_FORCE_SWITCH_EN_MASK 0x00000200 #define BCHP_XPT_RAVE_MISC_CONTROL_HW_FORCE_SWITCH_EN_SHIFT 9 /* XPT_RAVE :: MISC_CONTROL :: COUNTER_MODE [08:08] */ #define BCHP_XPT_RAVE_MISC_CONTROL_COUNTER_MODE_MASK 0x00000100 #define BCHP_XPT_RAVE_MISC_CONTROL_COUNTER_MODE_SHIFT 8 /* XPT_RAVE :: MISC_CONTROL :: NUM_DMA_CYCLES [07:04] */ #define BCHP_XPT_RAVE_MISC_CONTROL_NUM_DMA_CYCLES_MASK 0x000000f0 #define BCHP_XPT_RAVE_MISC_CONTROL_NUM_DMA_CYCLES_SHIFT 4 /* XPT_RAVE :: MISC_CONTROL :: AV_ENABLE [03:03] */ #define BCHP_XPT_RAVE_MISC_CONTROL_AV_ENABLE_MASK 0x00000008 #define BCHP_XPT_RAVE_MISC_CONTROL_AV_ENABLE_SHIFT 3 /* XPT_RAVE :: MISC_CONTROL :: reserved_for_eco1 [02:02] */ #define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco1_MASK 0x00000004 #define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco1_SHIFT 2 /* XPT_RAVE :: MISC_CONTROL :: PS_WAKE [01:01] */ #define BCHP_XPT_RAVE_MISC_CONTROL_PS_WAKE_MASK 0x00000002 #define BCHP_XPT_RAVE_MISC_CONTROL_PS_WAKE_SHIFT 1 /* XPT_RAVE :: MISC_CONTROL :: reserved_for_eco2 [00:00] */ #define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco2_MASK 0x00000001 #define BCHP_XPT_RAVE_MISC_CONTROL_reserved_for_eco2_SHIFT 0 /*************************************************************************** *BASE_ADDRESSES - Record and SCD Base Addresses ***************************************************************************/ /* XPT_RAVE :: BASE_ADDRESSES :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_BASE_ADDRESSES_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_BASE_ADDRESSES_reserved0_SHIFT 12 /* XPT_RAVE :: BASE_ADDRESSES :: SCD_BASE_ADDR [11:00] */ #define BCHP_XPT_RAVE_BASE_ADDRESSES_SCD_BASE_ADDR_MASK 0x00000fff #define BCHP_XPT_RAVE_BASE_ADDRESSES_SCD_BASE_ADDR_SHIFT 0 /*************************************************************************** *CX_HOLD_CLR_STATUS - Context Hold Status and Clear ***************************************************************************/ /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: reserved0 [31:24] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_reserved0_MASK 0xff000000 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_reserved0_SHIFT 24 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX23_HOLD [23:23] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX23_HOLD_MASK 0x00800000 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX23_HOLD_SHIFT 23 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX22_HOLD [22:22] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX22_HOLD_MASK 0x00400000 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX22_HOLD_SHIFT 22 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX21_HOLD [21:21] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX21_HOLD_MASK 0x00200000 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX21_HOLD_SHIFT 21 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX20_HOLD [20:20] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX20_HOLD_MASK 0x00100000 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX20_HOLD_SHIFT 20 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX19_HOLD [19:19] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX19_HOLD_MASK 0x00080000 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX19_HOLD_SHIFT 19 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX18_HOLD [18:18] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX18_HOLD_MASK 0x00040000 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX18_HOLD_SHIFT 18 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX17_HOLD [17:17] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX17_HOLD_MASK 0x00020000 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX17_HOLD_SHIFT 17 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX16_HOLD [16:16] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX16_HOLD_MASK 0x00010000 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX16_HOLD_SHIFT 16 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX15_HOLD [15:15] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX15_HOLD_MASK 0x00008000 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX15_HOLD_SHIFT 15 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX14_HOLD [14:14] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX14_HOLD_MASK 0x00004000 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX14_HOLD_SHIFT 14 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX13_HOLD [13:13] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX13_HOLD_MASK 0x00002000 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX13_HOLD_SHIFT 13 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX12_HOLD [12:12] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX12_HOLD_MASK 0x00001000 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX12_HOLD_SHIFT 12 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX11_HOLD [11:11] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX11_HOLD_MASK 0x00000800 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX11_HOLD_SHIFT 11 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX10_HOLD [10:10] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX10_HOLD_MASK 0x00000400 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX10_HOLD_SHIFT 10 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX9_HOLD [09:09] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX9_HOLD_MASK 0x00000200 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX9_HOLD_SHIFT 9 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX8_HOLD [08:08] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX8_HOLD_MASK 0x00000100 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX8_HOLD_SHIFT 8 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX7_HOLD [07:07] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX7_HOLD_MASK 0x00000080 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX7_HOLD_SHIFT 7 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX6_HOLD [06:06] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX6_HOLD_MASK 0x00000040 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX6_HOLD_SHIFT 6 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX5_HOLD [05:05] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX5_HOLD_MASK 0x00000020 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX5_HOLD_SHIFT 5 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX4_HOLD [04:04] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX4_HOLD_MASK 0x00000010 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX4_HOLD_SHIFT 4 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX3_HOLD [03:03] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX3_HOLD_MASK 0x00000008 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX3_HOLD_SHIFT 3 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX2_HOLD [02:02] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX2_HOLD_MASK 0x00000004 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX2_HOLD_SHIFT 2 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX1_HOLD [01:01] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX1_HOLD_MASK 0x00000002 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX1_HOLD_SHIFT 1 /* XPT_RAVE :: CX_HOLD_CLR_STATUS :: CX0_HOLD [00:00] */ #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX0_HOLD_MASK 0x00000001 #define BCHP_XPT_RAVE_CX_HOLD_CLR_STATUS_CX0_HOLD_SHIFT 0 /*************************************************************************** *BAND_HOLD_CLR_STATUS - Band Hold Status and Clear ***************************************************************************/ /* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: reserved0 [31:17] */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_reserved0_MASK 0xfffe0000 #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_reserved0_SHIFT 17 /* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK4_HOLD [16:16] */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK4_HOLD_MASK 0x00010000 #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK4_HOLD_SHIFT 16 /* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK3_HOLD [15:15] */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK3_HOLD_MASK 0x00008000 #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK3_HOLD_SHIFT 15 /* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK2_HOLD [14:14] */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK2_HOLD_MASK 0x00004000 #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK2_HOLD_SHIFT 14 /* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK1_HOLD [13:13] */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK1_HOLD_MASK 0x00002000 #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK1_HOLD_SHIFT 13 /* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PLAYBACK0_HOLD [12:12] */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK0_HOLD_MASK 0x00001000 #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PLAYBACK0_HOLD_SHIFT 12 /* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: reserved1 [11:07] */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_reserved1_MASK 0x00000f80 #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_reserved1_SHIFT 7 /* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND6_HOLD [06:06] */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND6_HOLD_MASK 0x00000040 #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND6_HOLD_SHIFT 6 /* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND5_HOLD [05:05] */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND5_HOLD_MASK 0x00000020 #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND5_HOLD_SHIFT 5 /* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND4_HOLD [04:04] */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND4_HOLD_MASK 0x00000010 #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND4_HOLD_SHIFT 4 /* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND3_HOLD [03:03] */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND3_HOLD_MASK 0x00000008 #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND3_HOLD_SHIFT 3 /* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND2_HOLD [02:02] */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND2_HOLD_MASK 0x00000004 #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND2_HOLD_SHIFT 2 /* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND1_HOLD [01:01] */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND1_HOLD_MASK 0x00000002 #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND1_HOLD_SHIFT 1 /* XPT_RAVE :: BAND_HOLD_CLR_STATUS :: PARSER_BAND0_HOLD [00:00] */ #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND0_HOLD_MASK 0x00000001 #define BCHP_XPT_RAVE_BAND_HOLD_CLR_STATUS_PARSER_BAND0_HOLD_SHIFT 0 /*************************************************************************** *FW_WATERMARK - Firmware throughput watermark ***************************************************************************/ /* XPT_RAVE :: FW_WATERMARK :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_FW_WATERMARK_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_FW_WATERMARK_reserved0_SHIFT 16 /* XPT_RAVE :: FW_WATERMARK :: FIRMWARE_WMARK [15:00] */ #define BCHP_XPT_RAVE_FW_WATERMARK_FIRMWARE_WMARK_MASK 0x0000ffff #define BCHP_XPT_RAVE_FW_WATERMARK_FIRMWARE_WMARK_SHIFT 0 /*************************************************************************** *HW_WATCHDOG - Hardware Watchdog Counter ***************************************************************************/ /* XPT_RAVE :: HW_WATCHDOG :: reserved0 [31:16] */ #define BCHP_XPT_RAVE_HW_WATCHDOG_reserved0_MASK 0xffff0000 #define BCHP_XPT_RAVE_HW_WATCHDOG_reserved0_SHIFT 16 /* XPT_RAVE :: HW_WATCHDOG :: HW_WATCHDOG_COUNT [15:00] */ #define BCHP_XPT_RAVE_HW_WATCHDOG_HW_WATCHDOG_COUNT_MASK 0x0000ffff #define BCHP_XPT_RAVE_HW_WATCHDOG_HW_WATCHDOG_COUNT_SHIFT 0 /*************************************************************************** *MISC_CONTROL2 - Miscellaneous Control 2 ***************************************************************************/ /* XPT_RAVE :: MISC_CONTROL2 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_MISC_CONTROL2_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_MISC_CONTROL2_reserved0_SHIFT 8 /* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN7 [07:07] */ #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN7_MASK 0x00000080 #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN7_SHIFT 7 /* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN6 [06:06] */ #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN6_MASK 0x00000040 #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN6_SHIFT 6 /* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN5 [05:05] */ #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN5_MASK 0x00000020 #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN5_SHIFT 5 /* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN4 [04:04] */ #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN4_MASK 0x00000010 #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN4_SHIFT 4 /* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN3 [03:03] */ #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN3_MASK 0x00000008 #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN3_SHIFT 3 /* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN2 [02:02] */ #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN2_MASK 0x00000004 #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN2_SHIFT 2 /* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN1 [01:01] */ #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN1_MASK 0x00000002 #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN1_SHIFT 1 /* XPT_RAVE :: MISC_CONTROL2 :: MISC_INT_EN0 [00:00] */ #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN0_MASK 0x00000001 #define BCHP_XPT_RAVE_MISC_CONTROL2_MISC_INT_EN0_SHIFT 0 /*************************************************************************** *RC0_SP_CONTROL - Seamless Pause Control ***************************************************************************/ /* XPT_RAVE :: RC0_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ #define BCHP_XPT_RAVE_RC0_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_RC0_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 /* XPT_RAVE :: RC0_SP_CONTROL :: reserved0 [30:30] */ #define BCHP_XPT_RAVE_RC0_SP_CONTROL_reserved0_MASK 0x40000000 #define BCHP_XPT_RAVE_RC0_SP_CONTROL_reserved0_SHIFT 30 /* XPT_RAVE :: RC0_SP_CONTROL :: REC_CX_NUM [29:24] */ #define BCHP_XPT_RAVE_RC0_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 #define BCHP_XPT_RAVE_RC0_SP_CONTROL_REC_CX_NUM_SHIFT 24 /* XPT_RAVE :: RC0_SP_CONTROL :: CXX_MASK [23:00] */ #define BCHP_XPT_RAVE_RC0_SP_CONTROL_CXX_MASK_MASK 0x00ffffff #define BCHP_XPT_RAVE_RC0_SP_CONTROL_CXX_MASK_SHIFT 0 /*************************************************************************** *RC1_SP_CONTROL - Seamless Pause Control ***************************************************************************/ /* XPT_RAVE :: RC1_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ #define BCHP_XPT_RAVE_RC1_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_RC1_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 /* XPT_RAVE :: RC1_SP_CONTROL :: reserved0 [30:30] */ #define BCHP_XPT_RAVE_RC1_SP_CONTROL_reserved0_MASK 0x40000000 #define BCHP_XPT_RAVE_RC1_SP_CONTROL_reserved0_SHIFT 30 /* XPT_RAVE :: RC1_SP_CONTROL :: REC_CX_NUM [29:24] */ #define BCHP_XPT_RAVE_RC1_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 #define BCHP_XPT_RAVE_RC1_SP_CONTROL_REC_CX_NUM_SHIFT 24 /* XPT_RAVE :: RC1_SP_CONTROL :: CXX_MASK [23:00] */ #define BCHP_XPT_RAVE_RC1_SP_CONTROL_CXX_MASK_MASK 0x00ffffff #define BCHP_XPT_RAVE_RC1_SP_CONTROL_CXX_MASK_SHIFT 0 /*************************************************************************** *RC2_SP_CONTROL - Seamless Pause Control ***************************************************************************/ /* XPT_RAVE :: RC2_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ #define BCHP_XPT_RAVE_RC2_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_RC2_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 /* XPT_RAVE :: RC2_SP_CONTROL :: reserved0 [30:30] */ #define BCHP_XPT_RAVE_RC2_SP_CONTROL_reserved0_MASK 0x40000000 #define BCHP_XPT_RAVE_RC2_SP_CONTROL_reserved0_SHIFT 30 /* XPT_RAVE :: RC2_SP_CONTROL :: REC_CX_NUM [29:24] */ #define BCHP_XPT_RAVE_RC2_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 #define BCHP_XPT_RAVE_RC2_SP_CONTROL_REC_CX_NUM_SHIFT 24 /* XPT_RAVE :: RC2_SP_CONTROL :: CXX_MASK [23:00] */ #define BCHP_XPT_RAVE_RC2_SP_CONTROL_CXX_MASK_MASK 0x00ffffff #define BCHP_XPT_RAVE_RC2_SP_CONTROL_CXX_MASK_SHIFT 0 /*************************************************************************** *RC3_SP_CONTROL - Seamless Pause Control ***************************************************************************/ /* XPT_RAVE :: RC3_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ #define BCHP_XPT_RAVE_RC3_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_RC3_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 /* XPT_RAVE :: RC3_SP_CONTROL :: reserved0 [30:30] */ #define BCHP_XPT_RAVE_RC3_SP_CONTROL_reserved0_MASK 0x40000000 #define BCHP_XPT_RAVE_RC3_SP_CONTROL_reserved0_SHIFT 30 /* XPT_RAVE :: RC3_SP_CONTROL :: REC_CX_NUM [29:24] */ #define BCHP_XPT_RAVE_RC3_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 #define BCHP_XPT_RAVE_RC3_SP_CONTROL_REC_CX_NUM_SHIFT 24 /* XPT_RAVE :: RC3_SP_CONTROL :: CXX_MASK [23:00] */ #define BCHP_XPT_RAVE_RC3_SP_CONTROL_CXX_MASK_MASK 0x00ffffff #define BCHP_XPT_RAVE_RC3_SP_CONTROL_CXX_MASK_SHIFT 0 /*************************************************************************** *RC4_SP_CONTROL - Seamless Pause Control ***************************************************************************/ /* XPT_RAVE :: RC4_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ #define BCHP_XPT_RAVE_RC4_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_RC4_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 /* XPT_RAVE :: RC4_SP_CONTROL :: reserved0 [30:30] */ #define BCHP_XPT_RAVE_RC4_SP_CONTROL_reserved0_MASK 0x40000000 #define BCHP_XPT_RAVE_RC4_SP_CONTROL_reserved0_SHIFT 30 /* XPT_RAVE :: RC4_SP_CONTROL :: REC_CX_NUM [29:24] */ #define BCHP_XPT_RAVE_RC4_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 #define BCHP_XPT_RAVE_RC4_SP_CONTROL_REC_CX_NUM_SHIFT 24 /* XPT_RAVE :: RC4_SP_CONTROL :: CXX_MASK [23:00] */ #define BCHP_XPT_RAVE_RC4_SP_CONTROL_CXX_MASK_MASK 0x00ffffff #define BCHP_XPT_RAVE_RC4_SP_CONTROL_CXX_MASK_SHIFT 0 /*************************************************************************** *RC5_SP_CONTROL - Seamless Pause Control ***************************************************************************/ /* XPT_RAVE :: RC5_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ #define BCHP_XPT_RAVE_RC5_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_RC5_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 /* XPT_RAVE :: RC5_SP_CONTROL :: reserved0 [30:30] */ #define BCHP_XPT_RAVE_RC5_SP_CONTROL_reserved0_MASK 0x40000000 #define BCHP_XPT_RAVE_RC5_SP_CONTROL_reserved0_SHIFT 30 /* XPT_RAVE :: RC5_SP_CONTROL :: REC_CX_NUM [29:24] */ #define BCHP_XPT_RAVE_RC5_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 #define BCHP_XPT_RAVE_RC5_SP_CONTROL_REC_CX_NUM_SHIFT 24 /* XPT_RAVE :: RC5_SP_CONTROL :: CXX_MASK [23:00] */ #define BCHP_XPT_RAVE_RC5_SP_CONTROL_CXX_MASK_MASK 0x00ffffff #define BCHP_XPT_RAVE_RC5_SP_CONTROL_CXX_MASK_SHIFT 0 /*************************************************************************** *RC6_SP_CONTROL - Seamless Pause Control ***************************************************************************/ /* XPT_RAVE :: RC6_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ #define BCHP_XPT_RAVE_RC6_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_RC6_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 /* XPT_RAVE :: RC6_SP_CONTROL :: reserved0 [30:30] */ #define BCHP_XPT_RAVE_RC6_SP_CONTROL_reserved0_MASK 0x40000000 #define BCHP_XPT_RAVE_RC6_SP_CONTROL_reserved0_SHIFT 30 /* XPT_RAVE :: RC6_SP_CONTROL :: REC_CX_NUM [29:24] */ #define BCHP_XPT_RAVE_RC6_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 #define BCHP_XPT_RAVE_RC6_SP_CONTROL_REC_CX_NUM_SHIFT 24 /* XPT_RAVE :: RC6_SP_CONTROL :: CXX_MASK [23:00] */ #define BCHP_XPT_RAVE_RC6_SP_CONTROL_CXX_MASK_MASK 0x00ffffff #define BCHP_XPT_RAVE_RC6_SP_CONTROL_CXX_MASK_SHIFT 0 /*************************************************************************** *RC7_SP_CONTROL - Seamless Pause Control ***************************************************************************/ /* XPT_RAVE :: RC7_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ #define BCHP_XPT_RAVE_RC7_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_RC7_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 /* XPT_RAVE :: RC7_SP_CONTROL :: reserved0 [30:30] */ #define BCHP_XPT_RAVE_RC7_SP_CONTROL_reserved0_MASK 0x40000000 #define BCHP_XPT_RAVE_RC7_SP_CONTROL_reserved0_SHIFT 30 /* XPT_RAVE :: RC7_SP_CONTROL :: REC_CX_NUM [29:24] */ #define BCHP_XPT_RAVE_RC7_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 #define BCHP_XPT_RAVE_RC7_SP_CONTROL_REC_CX_NUM_SHIFT 24 /* XPT_RAVE :: RC7_SP_CONTROL :: CXX_MASK [23:00] */ #define BCHP_XPT_RAVE_RC7_SP_CONTROL_CXX_MASK_MASK 0x00ffffff #define BCHP_XPT_RAVE_RC7_SP_CONTROL_CXX_MASK_SHIFT 0 /*************************************************************************** *RC8_SP_CONTROL - Seamless Pause Control ***************************************************************************/ /* XPT_RAVE :: RC8_SP_CONTROL :: SEAMLESS_PAUSE_EN [31:31] */ #define BCHP_XPT_RAVE_RC8_SP_CONTROL_SEAMLESS_PAUSE_EN_MASK 0x80000000 #define BCHP_XPT_RAVE_RC8_SP_CONTROL_SEAMLESS_PAUSE_EN_SHIFT 31 /* XPT_RAVE :: RC8_SP_CONTROL :: reserved0 [30:30] */ #define BCHP_XPT_RAVE_RC8_SP_CONTROL_reserved0_MASK 0x40000000 #define BCHP_XPT_RAVE_RC8_SP_CONTROL_reserved0_SHIFT 30 /* XPT_RAVE :: RC8_SP_CONTROL :: REC_CX_NUM [29:24] */ #define BCHP_XPT_RAVE_RC8_SP_CONTROL_REC_CX_NUM_MASK 0x3f000000 #define BCHP_XPT_RAVE_RC8_SP_CONTROL_REC_CX_NUM_SHIFT 24 /* XPT_RAVE :: RC8_SP_CONTROL :: CXX_MASK [23:00] */ #define BCHP_XPT_RAVE_RC8_SP_CONTROL_CXX_MASK_MASK 0x00ffffff #define BCHP_XPT_RAVE_RC8_SP_CONTROL_CXX_MASK_SHIFT 0 /*************************************************************************** *AV_STATUS2 - RAVE Status ***************************************************************************/ /* XPT_RAVE :: AV_STATUS2 :: reserved0 [31:20] */ #define BCHP_XPT_RAVE_AV_STATUS2_reserved0_MASK 0xfff00000 #define BCHP_XPT_RAVE_AV_STATUS2_reserved0_SHIFT 20 /* XPT_RAVE :: AV_STATUS2 :: PONG_SCD_NUM [19:14] */ #define BCHP_XPT_RAVE_AV_STATUS2_PONG_SCD_NUM_MASK 0x000fc000 #define BCHP_XPT_RAVE_AV_STATUS2_PONG_SCD_NUM_SHIFT 14 /* XPT_RAVE :: AV_STATUS2 :: PING_SCD_NUM [13:08] */ #define BCHP_XPT_RAVE_AV_STATUS2_PING_SCD_NUM_MASK 0x00003f00 #define BCHP_XPT_RAVE_AV_STATUS2_PING_SCD_NUM_SHIFT 8 /* XPT_RAVE :: AV_STATUS2 :: PONG_CONTEXT_NUM [07:04] */ #define BCHP_XPT_RAVE_AV_STATUS2_PONG_CONTEXT_NUM_MASK 0x000000f0 #define BCHP_XPT_RAVE_AV_STATUS2_PONG_CONTEXT_NUM_SHIFT 4 /* XPT_RAVE :: AV_STATUS2 :: PING_CONTEXT_NUM [03:00] */ #define BCHP_XPT_RAVE_AV_STATUS2_PING_CONTEXT_NUM_MASK 0x0000000f #define BCHP_XPT_RAVE_AV_STATUS2_PING_CONTEXT_NUM_SHIFT 0 /*************************************************************************** *TM_DMEM - TM Control ***************************************************************************/ /* XPT_RAVE :: TM_DMEM :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TM_DMEM_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TM_DMEM_reserved0_SHIFT 8 /* XPT_RAVE :: TM_DMEM :: TMB [07:04] */ #define BCHP_XPT_RAVE_TM_DMEM_TMB_MASK 0x000000f0 #define BCHP_XPT_RAVE_TM_DMEM_TMB_SHIFT 4 /* XPT_RAVE :: TM_DMEM :: TMA [03:00] */ #define BCHP_XPT_RAVE_TM_DMEM_TMA_MASK 0x0000000f #define BCHP_XPT_RAVE_TM_DMEM_TMA_SHIFT 0 /*************************************************************************** *TM_IMEM - TM Control ***************************************************************************/ /* XPT_RAVE :: TM_IMEM :: reserved0 [31:04] */ #define BCHP_XPT_RAVE_TM_IMEM_reserved0_MASK 0xfffffff0 #define BCHP_XPT_RAVE_TM_IMEM_reserved0_SHIFT 4 /* XPT_RAVE :: TM_IMEM :: TM [03:00] */ #define BCHP_XPT_RAVE_TM_IMEM_TM_MASK 0x0000000f #define BCHP_XPT_RAVE_TM_IMEM_TM_SHIFT 0 /*************************************************************************** *TM_POINTER_RAM - TM Control ***************************************************************************/ /* XPT_RAVE :: TM_POINTER_RAM :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TM_POINTER_RAM_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TM_POINTER_RAM_reserved0_SHIFT 8 /* XPT_RAVE :: TM_POINTER_RAM :: TM [07:00] */ #define BCHP_XPT_RAVE_TM_POINTER_RAM_TM_MASK 0x000000ff #define BCHP_XPT_RAVE_TM_POINTER_RAM_TM_SHIFT 0 /*************************************************************************** *TM_MUX_BUFFER - TM Control ***************************************************************************/ /* XPT_RAVE :: TM_MUX_BUFFER :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TM_MUX_BUFFER_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TM_MUX_BUFFER_reserved0_SHIFT 8 /* XPT_RAVE :: TM_MUX_BUFFER :: TM [07:00] */ #define BCHP_XPT_RAVE_TM_MUX_BUFFER_TM_MASK 0x000000ff #define BCHP_XPT_RAVE_TM_MUX_BUFFER_TM_SHIFT 0 /*************************************************************************** *TM_CX_TABLE - TM Control ***************************************************************************/ /* XPT_RAVE :: TM_CX_TABLE :: reserved0 [31:04] */ #define BCHP_XPT_RAVE_TM_CX_TABLE_reserved0_MASK 0xfffffff0 #define BCHP_XPT_RAVE_TM_CX_TABLE_reserved0_SHIFT 4 /* XPT_RAVE :: TM_CX_TABLE :: TM [03:00] */ #define BCHP_XPT_RAVE_TM_CX_TABLE_TM_MASK 0x0000000f #define BCHP_XPT_RAVE_TM_CX_TABLE_TM_SHIFT 0 /*************************************************************************** *TM_CX_TABLE_HI - TM Control ***************************************************************************/ /* XPT_RAVE :: TM_CX_TABLE_HI :: reserved0 [31:04] */ #define BCHP_XPT_RAVE_TM_CX_TABLE_HI_reserved0_MASK 0xfffffff0 #define BCHP_XPT_RAVE_TM_CX_TABLE_HI_reserved0_SHIFT 4 /* XPT_RAVE :: TM_CX_TABLE_HI :: TM [03:00] */ #define BCHP_XPT_RAVE_TM_CX_TABLE_HI_TM_MASK 0x0000000f #define BCHP_XPT_RAVE_TM_CX_TABLE_HI_TM_SHIFT 0 /*************************************************************************** *TM_SMEM - TM Control ***************************************************************************/ /* XPT_RAVE :: TM_SMEM :: reserved0 [31:04] */ #define BCHP_XPT_RAVE_TM_SMEM_reserved0_MASK 0xfffffff0 #define BCHP_XPT_RAVE_TM_SMEM_reserved0_SHIFT 4 /* XPT_RAVE :: TM_SMEM :: TM [03:00] */ #define BCHP_XPT_RAVE_TM_SMEM_TM_MASK 0x0000000f #define BCHP_XPT_RAVE_TM_SMEM_TM_SHIFT 0 /*************************************************************************** *INT_CX0 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX0 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX0_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX0_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX0 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX0_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX0_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX0 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX0_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX0_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX0 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX0_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX0_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX0 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX0_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX0_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX0 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX0_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX0_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX0 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX0_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX0_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX0 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX0_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX0_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX0 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX0_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX0_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX0 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX0_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX0_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX0 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX0_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX0_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX0 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX0_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX0_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX0 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX0_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX0_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX0 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX0_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX0_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX1 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX1 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX1_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX1_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX1 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX1_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX1_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX1 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX1_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX1_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX1 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX1_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX1_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX1 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX1_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX1_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX1 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX1_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX1_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX1 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX1_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX1_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX1 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX1_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX1_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX1 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX1_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX1_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX1 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX1_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX1_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX1 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX1_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX1_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX1 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX1_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX1_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX1 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX1_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX1_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX1 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX1_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX1_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX2 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX2 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX2_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX2_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX2 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX2_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX2_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX2 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX2_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX2_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX2 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX2_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX2_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX2 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX2_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX2_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX2 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX2_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX2_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX2 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX2_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX2_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX2 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX2_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX2_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX2 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX2_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX2_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX2 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX2_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX2_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX2 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX2_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX2_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX2 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX2_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX2_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX2 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX2_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX2_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX2 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX2_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX2_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX3 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX3 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX3_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX3_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX3 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX3_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX3_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX3 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX3_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX3_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX3 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX3_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX3_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX3 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX3_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX3_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX3 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX3_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX3_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX3 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX3_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX3_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX3 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX3_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX3_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX3 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX3_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX3_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX3 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX3_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX3_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX3 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX3_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX3_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX3 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX3_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX3_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX3 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX3_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX3_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX3 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX3_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX3_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX4 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX4 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX4_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX4_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX4 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX4_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX4_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX4 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX4_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX4_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX4 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX4_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX4_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX4 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX4_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX4_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX4 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX4_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX4_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX4 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX4_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX4_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX4 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX4_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX4_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX4 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX4_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX4_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX4 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX4_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX4_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX4 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX4_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX4_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX4 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX4_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX4_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX4 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX4_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX4_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX4 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX4_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX4_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX5 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX5 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX5_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX5_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX5 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX5_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX5_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX5 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX5_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX5_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX5 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX5_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX5_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX5 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX5_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX5_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX5 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX5_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX5_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX5 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX5_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX5_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX5 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX5_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX5_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX5 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX5_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX5_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX5 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX5_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX5_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX5 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX5_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX5_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX5 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX5_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX5_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX5 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX5_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX5_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX5 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX5_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX5_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX6 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX6 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX6_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX6_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX6 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX6_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX6_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX6 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX6_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX6_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX6 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX6_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX6_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX6 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX6_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX6_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX6 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX6_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX6_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX6 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX6_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX6_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX6 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX6_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX6_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX6 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX6_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX6_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX6 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX6_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX6_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX6 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX6_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX6_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX6 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX6_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX6_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX6 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX6_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX6_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX6 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX6_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX6_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX7 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX7 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX7_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX7_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX7 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX7_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX7_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX7 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX7_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX7_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX7 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX7_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX7_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX7 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX7_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX7_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX7 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX7_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX7_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX7 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX7_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX7_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX7 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX7_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX7_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX7 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX7_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX7_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX7 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX7_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX7_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX7 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX7_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX7_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX7 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX7_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX7_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX7 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX7_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX7_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX7 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX7_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX7_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX8 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX8 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX8_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX8_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX8 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX8_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX8_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX8 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX8_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX8_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX8 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX8_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX8_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX8 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX8_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX8_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX8 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX8_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX8_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX8 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX8_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX8_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX8 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX8_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX8_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX8 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX8_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX8_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX8 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX8_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX8_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX8 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX8_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX8_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX8 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX8_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX8_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX8 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX8_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX8_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX8 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX8_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX8_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX9 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX9 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX9_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX9_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX9 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX9_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX9_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX9 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX9_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX9_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX9 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX9_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX9_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX9 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX9_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX9_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX9 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX9_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX9_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX9 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX9_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX9_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX9 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX9_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX9_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX9 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX9_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX9_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX9 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX9_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX9_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX9 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX9_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX9_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX9 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX9_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX9_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX9 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX9_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX9_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX9 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX9_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX9_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX10 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX10 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX10_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX10_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX10 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX10_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX10_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX10 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX10_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX10_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX10 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX10_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX10_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX10 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX10_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX10_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX10 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX10_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX10_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX10 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX10_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX10_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX10 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX10_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX10_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX10 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX10_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX10_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX10 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX10_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX10_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX10 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX10_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX10_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX10 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX10_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX10_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX10 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX10_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX10_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX10 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX10_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX10_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX11 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX11 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX11_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX11_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX11 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX11_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX11_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX11 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX11_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX11_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX11 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX11_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX11_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX11 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX11_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX11_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX11 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX11_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX11_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX11 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX11_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX11_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX11 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX11_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX11_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX11 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX11_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX11_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX11 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX11_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX11_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX11 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX11_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX11_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX11 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX11_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX11_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX11 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX11_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX11_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX11 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX11_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX11_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX12 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX12 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX12_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX12_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX12 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX12_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX12_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX12 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX12_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX12_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX12 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX12_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX12_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX12 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX12_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX12_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX12 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX12_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX12_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX12 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX12_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX12_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX12 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX12_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX12_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX12 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX12_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX12_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX12 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX12_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX12_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX12 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX12_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX12_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX12 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX12_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX12_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX12 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX12_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX12_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX12 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX12_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX12_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX13 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX13 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX13_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX13_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX13 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX13_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX13_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX13 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX13_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX13_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX13 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX13_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX13_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX13 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX13_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX13_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX13 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX13_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX13_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX13 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX13_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX13_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX13 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX13_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX13_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX13 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX13_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX13_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX13 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX13_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX13_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX13 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX13_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX13_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX13 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX13_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX13_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX13 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX13_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX13_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX13 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX13_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX13_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX14 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX14 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX14_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX14_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX14 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX14_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX14_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX14 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX14_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX14_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX14 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX14_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX14_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX14 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX14_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX14_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX14 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX14_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX14_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX14 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX14_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX14_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX14 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX14_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX14_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX14 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX14_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX14_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX14 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX14_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX14_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX14 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX14_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX14_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX14 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX14_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX14_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX14 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX14_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX14_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX14 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX14_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX14_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX15 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX15 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX15_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX15_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX15 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX15_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX15_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX15 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX15_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX15_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX15 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX15_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX15_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX15 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX15_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX15_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX15 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX15_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX15_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX15 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX15_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX15_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX15 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX15_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX15_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX15 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX15_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX15_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX15 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX15_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX15_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX15 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX15_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX15_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX15 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX15_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX15_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX15 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX15_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX15_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX15 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX15_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX15_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX16 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX16 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX16_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX16_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX16 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX16_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX16_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX16 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX16_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX16_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX16 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX16_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX16_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX16 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX16_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX16_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX16 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX16_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX16_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX16 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX16_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX16_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX16 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX16_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX16_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX16 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX16_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX16_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX16 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX16_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX16_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX16 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX16_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX16_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX16 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX16_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX16_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX16 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX16_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX16_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX16 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX16_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX16_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX17 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX17 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX17_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX17_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX17 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX17_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX17_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX17 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX17_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX17_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX17 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX17_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX17_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX17 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX17_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX17_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX17 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX17_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX17_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX17 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX17_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX17_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX17 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX17_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX17_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX17 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX17_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX17_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX17 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX17_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX17_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX17 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX17_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX17_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX17 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX17_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX17_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX17 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX17_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX17_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX17 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX17_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX17_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX18 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX18 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX18_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX18_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX18 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX18_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX18_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX18 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX18_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX18_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX18 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX18_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX18_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX18 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX18_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX18_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX18 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX18_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX18_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX18 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX18_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX18_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX18 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX18_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX18_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX18 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX18_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX18_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX18 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX18_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX18_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX18 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX18_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX18_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX18 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX18_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX18_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX18 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX18_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX18_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX18 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX18_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX18_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX19 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX19 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX19_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX19_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX19 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX19_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX19_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX19 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX19_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX19_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX19 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX19_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX19_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX19 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX19_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX19_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX19 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX19_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX19_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX19 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX19_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX19_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX19 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX19_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX19_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX19 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX19_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX19_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX19 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX19_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX19_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX19 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX19_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX19_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX19 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX19_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX19_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX19 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX19_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX19_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX19 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX19_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX19_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX20 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX20 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX20_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX20_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX20 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX20_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX20_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX20 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX20_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX20_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX20 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX20_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX20_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX20 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX20_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX20_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX20 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX20_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX20_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX20 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX20_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX20_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX20 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX20_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX20_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX20 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX20_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX20_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX20 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX20_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX20_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX20 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX20_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX20_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX20 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX20_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX20_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX20 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX20_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX20_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX20 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX20_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX20_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX21 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX21 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX21_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX21_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX21 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX21_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX21_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX21 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX21_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX21_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX21 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX21_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX21_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX21 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX21_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX21_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX21 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX21_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX21_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX21 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX21_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX21_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX21 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX21_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX21_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX21 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX21_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX21_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX21 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX21_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX21_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX21 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX21_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX21_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX21 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX21_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX21_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX21 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX21_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX21_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX21 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX21_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX21_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX22 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX22 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX22_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX22_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX22 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX22_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX22_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX22 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX22_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX22_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX22 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX22_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX22_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX22 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX22_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX22_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX22 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX22_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX22_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX22 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX22_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX22_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX22 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX22_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX22_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX22 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX22_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX22_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX22 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX22_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX22_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX22 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX22_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX22_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX22 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX22_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX22_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX22 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX22_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX22_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX22 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX22_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX22_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_CX23 - Context Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_CX23 :: reserved0 [31:15] */ #define BCHP_XPT_RAVE_INT_CX23_reserved0_MASK 0xffff8000 #define BCHP_XPT_RAVE_INT_CX23_reserved0_SHIFT 15 /* XPT_RAVE :: INT_CX23 :: SCD_INDEX [14:12] */ #define BCHP_XPT_RAVE_INT_CX23_SCD_INDEX_MASK 0x00007000 #define BCHP_XPT_RAVE_INT_CX23_SCD_INDEX_SHIFT 12 /* XPT_RAVE :: INT_CX23 :: ITB_UPPER_THRESH_INT [11:11] */ #define BCHP_XPT_RAVE_INT_CX23_ITB_UPPER_THRESH_INT_MASK 0x00000800 #define BCHP_XPT_RAVE_INT_CX23_ITB_UPPER_THRESH_INT_SHIFT 11 /* XPT_RAVE :: INT_CX23 :: ITB_LOWER_THRESH_INT [10:10] */ #define BCHP_XPT_RAVE_INT_CX23_ITB_LOWER_THRESH_INT_MASK 0x00000400 #define BCHP_XPT_RAVE_INT_CX23_ITB_LOWER_THRESH_INT_SHIFT 10 /* XPT_RAVE :: INT_CX23 :: CDB_UPPER_THRESH_INT [09:09] */ #define BCHP_XPT_RAVE_INT_CX23_CDB_UPPER_THRESH_INT_MASK 0x00000200 #define BCHP_XPT_RAVE_INT_CX23_CDB_UPPER_THRESH_INT_SHIFT 9 /* XPT_RAVE :: INT_CX23 :: CDB_LOWER_THRESH_INT [08:08] */ #define BCHP_XPT_RAVE_INT_CX23_CDB_LOWER_THRESH_INT_MASK 0x00000100 #define BCHP_XPT_RAVE_INT_CX23_CDB_LOWER_THRESH_INT_SHIFT 8 /* XPT_RAVE :: INT_CX23 :: LAST_CMD_INT [07:07] */ #define BCHP_XPT_RAVE_INT_CX23_LAST_CMD_INT_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_CX23_LAST_CMD_INT_SHIFT 7 /* XPT_RAVE :: INT_CX23 :: SPLICE_INT [06:06] */ #define BCHP_XPT_RAVE_INT_CX23_SPLICE_INT_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_CX23_SPLICE_INT_SHIFT 6 /* XPT_RAVE :: INT_CX23 :: ITB_OVERFLOW_INT [05:05] */ #define BCHP_XPT_RAVE_INT_CX23_ITB_OVERFLOW_INT_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_CX23_ITB_OVERFLOW_INT_SHIFT 5 /* XPT_RAVE :: INT_CX23 :: CDB_OVERFLOW_INT [04:04] */ #define BCHP_XPT_RAVE_INT_CX23_CDB_OVERFLOW_INT_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_CX23_CDB_OVERFLOW_INT_SHIFT 4 /* XPT_RAVE :: INT_CX23 :: CC_ERROR_INT [03:03] */ #define BCHP_XPT_RAVE_INT_CX23_CC_ERROR_INT_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_CX23_CC_ERROR_INT_SHIFT 3 /* XPT_RAVE :: INT_CX23 :: TEI_ERROR_INT [02:02] */ #define BCHP_XPT_RAVE_INT_CX23_TEI_ERROR_INT_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_CX23_TEI_ERROR_INT_SHIFT 2 /* XPT_RAVE :: INT_CX23 :: PUSI_ERROR_INT [01:01] */ #define BCHP_XPT_RAVE_INT_CX23_PUSI_ERROR_INT_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_CX23_PUSI_ERROR_INT_SHIFT 1 /* XPT_RAVE :: INT_CX23 :: EMU_ERROR_INT [00:00] */ #define BCHP_XPT_RAVE_INT_CX23_EMU_ERROR_INT_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_CX23_EMU_ERROR_INT_SHIFT 0 /*************************************************************************** *INT_MISC - Miscellaneous Interrupts ***************************************************************************/ /* XPT_RAVE :: INT_MISC :: reserved0 [31:12] */ #define BCHP_XPT_RAVE_INT_MISC_reserved0_MASK 0xfffff000 #define BCHP_XPT_RAVE_INT_MISC_reserved0_SHIFT 12 /* XPT_RAVE :: INT_MISC :: reserved_for_eco1 [11:08] */ #define BCHP_XPT_RAVE_INT_MISC_reserved_for_eco1_MASK 0x00000f00 #define BCHP_XPT_RAVE_INT_MISC_reserved_for_eco1_SHIFT 8 /* XPT_RAVE :: INT_MISC :: MISC_INT7 [07:07] */ #define BCHP_XPT_RAVE_INT_MISC_MISC_INT7_MASK 0x00000080 #define BCHP_XPT_RAVE_INT_MISC_MISC_INT7_SHIFT 7 /* XPT_RAVE :: INT_MISC :: MISC_INT6 [06:06] */ #define BCHP_XPT_RAVE_INT_MISC_MISC_INT6_MASK 0x00000040 #define BCHP_XPT_RAVE_INT_MISC_MISC_INT6_SHIFT 6 /* XPT_RAVE :: INT_MISC :: MISC_INT5 [05:05] */ #define BCHP_XPT_RAVE_INT_MISC_MISC_INT5_MASK 0x00000020 #define BCHP_XPT_RAVE_INT_MISC_MISC_INT5_SHIFT 5 /* XPT_RAVE :: INT_MISC :: MISC_INT4 [04:04] */ #define BCHP_XPT_RAVE_INT_MISC_MISC_INT4_MASK 0x00000010 #define BCHP_XPT_RAVE_INT_MISC_MISC_INT4_SHIFT 4 /* XPT_RAVE :: INT_MISC :: MISC_INT3 [03:03] */ #define BCHP_XPT_RAVE_INT_MISC_MISC_INT3_MASK 0x00000008 #define BCHP_XPT_RAVE_INT_MISC_MISC_INT3_SHIFT 3 /* XPT_RAVE :: INT_MISC :: MISC_INT2 [02:02] */ #define BCHP_XPT_RAVE_INT_MISC_MISC_INT2_MASK 0x00000004 #define BCHP_XPT_RAVE_INT_MISC_MISC_INT2_SHIFT 2 /* XPT_RAVE :: INT_MISC :: MISC_INT1 [01:01] */ #define BCHP_XPT_RAVE_INT_MISC_MISC_INT1_MASK 0x00000002 #define BCHP_XPT_RAVE_INT_MISC_MISC_INT1_SHIFT 1 /* XPT_RAVE :: INT_MISC :: MISC_INT0 [00:00] */ #define BCHP_XPT_RAVE_INT_MISC_MISC_INT0_MASK 0x00000001 #define BCHP_XPT_RAVE_INT_MISC_MISC_INT0_SHIFT 0 /*************************************************************************** *CXMEM_LO%i - Context Table 0 (for contexts 0 - 15) 0..287 ***************************************************************************/ #define BCHP_XPT_RAVE_CXMEM_LOi_ARRAY_BASE 0x00213200 #define BCHP_XPT_RAVE_CXMEM_LOi_ARRAY_START 0 #define BCHP_XPT_RAVE_CXMEM_LOi_ARRAY_END 287 #define BCHP_XPT_RAVE_CXMEM_LOi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *CXMEM_LO%i - Context Table 0 (for contexts 0 - 15) 0..287 ***************************************************************************/ /* XPT_RAVE :: CXMEM_LOi :: CX15_MAP_G [31:31] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX15_MAP_G_MASK 0x80000000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX15_MAP_G_SHIFT 31 /* XPT_RAVE :: CXMEM_LOi :: CX15_MAP_R [30:30] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX15_MAP_R_MASK 0x40000000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX15_MAP_R_SHIFT 30 /* XPT_RAVE :: CXMEM_LOi :: CX14_MAP_G [29:29] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX14_MAP_G_MASK 0x20000000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX14_MAP_G_SHIFT 29 /* XPT_RAVE :: CXMEM_LOi :: CX14_MAP_R [28:28] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX14_MAP_R_MASK 0x10000000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX14_MAP_R_SHIFT 28 /* XPT_RAVE :: CXMEM_LOi :: CX13_MAP_G [27:27] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX13_MAP_G_MASK 0x08000000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX13_MAP_G_SHIFT 27 /* XPT_RAVE :: CXMEM_LOi :: CX13_MAP_R [26:26] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX13_MAP_R_MASK 0x04000000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX13_MAP_R_SHIFT 26 /* XPT_RAVE :: CXMEM_LOi :: CX12_MAP_G [25:25] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX12_MAP_G_MASK 0x02000000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX12_MAP_G_SHIFT 25 /* XPT_RAVE :: CXMEM_LOi :: CX12_MAP_R [24:24] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX12_MAP_R_MASK 0x01000000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX12_MAP_R_SHIFT 24 /* XPT_RAVE :: CXMEM_LOi :: CX11_MAP_G [23:23] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX11_MAP_G_MASK 0x00800000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX11_MAP_G_SHIFT 23 /* XPT_RAVE :: CXMEM_LOi :: CX11_MAP_R [22:22] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX11_MAP_R_MASK 0x00400000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX11_MAP_R_SHIFT 22 /* XPT_RAVE :: CXMEM_LOi :: CX10_MAP_G [21:21] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX10_MAP_G_MASK 0x00200000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX10_MAP_G_SHIFT 21 /* XPT_RAVE :: CXMEM_LOi :: CX10_MAP_R [20:20] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX10_MAP_R_MASK 0x00100000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX10_MAP_R_SHIFT 20 /* XPT_RAVE :: CXMEM_LOi :: CX9_MAP_G [19:19] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX9_MAP_G_MASK 0x00080000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX9_MAP_G_SHIFT 19 /* XPT_RAVE :: CXMEM_LOi :: CX9_MAP_R [18:18] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX9_MAP_R_MASK 0x00040000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX9_MAP_R_SHIFT 18 /* XPT_RAVE :: CXMEM_LOi :: CX8_MAP_G [17:17] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX8_MAP_G_MASK 0x00020000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX8_MAP_G_SHIFT 17 /* XPT_RAVE :: CXMEM_LOi :: CX8_MAP_R [16:16] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX8_MAP_R_MASK 0x00010000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX8_MAP_R_SHIFT 16 /* XPT_RAVE :: CXMEM_LOi :: CX7_MAP_G [15:15] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX7_MAP_G_MASK 0x00008000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX7_MAP_G_SHIFT 15 /* XPT_RAVE :: CXMEM_LOi :: CX7_MAP_R [14:14] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX7_MAP_R_MASK 0x00004000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX7_MAP_R_SHIFT 14 /* XPT_RAVE :: CXMEM_LOi :: CX6_MAP_G [13:13] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX6_MAP_G_MASK 0x00002000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX6_MAP_G_SHIFT 13 /* XPT_RAVE :: CXMEM_LOi :: CX6_MAP_R [12:12] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX6_MAP_R_MASK 0x00001000 #define BCHP_XPT_RAVE_CXMEM_LOi_CX6_MAP_R_SHIFT 12 /* XPT_RAVE :: CXMEM_LOi :: CX5_MAP_G [11:11] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX5_MAP_G_MASK 0x00000800 #define BCHP_XPT_RAVE_CXMEM_LOi_CX5_MAP_G_SHIFT 11 /* XPT_RAVE :: CXMEM_LOi :: CX5_MAP_R [10:10] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX5_MAP_R_MASK 0x00000400 #define BCHP_XPT_RAVE_CXMEM_LOi_CX5_MAP_R_SHIFT 10 /* XPT_RAVE :: CXMEM_LOi :: CX4_MAP_G [09:09] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX4_MAP_G_MASK 0x00000200 #define BCHP_XPT_RAVE_CXMEM_LOi_CX4_MAP_G_SHIFT 9 /* XPT_RAVE :: CXMEM_LOi :: CX4_MAP_R [08:08] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX4_MAP_R_MASK 0x00000100 #define BCHP_XPT_RAVE_CXMEM_LOi_CX4_MAP_R_SHIFT 8 /* XPT_RAVE :: CXMEM_LOi :: CX3_MAP_G [07:07] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX3_MAP_G_MASK 0x00000080 #define BCHP_XPT_RAVE_CXMEM_LOi_CX3_MAP_G_SHIFT 7 /* XPT_RAVE :: CXMEM_LOi :: CX3_MAP_R [06:06] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX3_MAP_R_MASK 0x00000040 #define BCHP_XPT_RAVE_CXMEM_LOi_CX3_MAP_R_SHIFT 6 /* XPT_RAVE :: CXMEM_LOi :: CX2_MAP_G [05:05] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX2_MAP_G_MASK 0x00000020 #define BCHP_XPT_RAVE_CXMEM_LOi_CX2_MAP_G_SHIFT 5 /* XPT_RAVE :: CXMEM_LOi :: CX2_MAP_R [04:04] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX2_MAP_R_MASK 0x00000010 #define BCHP_XPT_RAVE_CXMEM_LOi_CX2_MAP_R_SHIFT 4 /* XPT_RAVE :: CXMEM_LOi :: CX1_MAP_G [03:03] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX1_MAP_G_MASK 0x00000008 #define BCHP_XPT_RAVE_CXMEM_LOi_CX1_MAP_G_SHIFT 3 /* XPT_RAVE :: CXMEM_LOi :: CX1_MAP_R [02:02] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX1_MAP_R_MASK 0x00000004 #define BCHP_XPT_RAVE_CXMEM_LOi_CX1_MAP_R_SHIFT 2 /* XPT_RAVE :: CXMEM_LOi :: CX0_MAP_G [01:01] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX0_MAP_G_MASK 0x00000002 #define BCHP_XPT_RAVE_CXMEM_LOi_CX0_MAP_G_SHIFT 1 /* XPT_RAVE :: CXMEM_LOi :: CX0_MAP_R [00:00] */ #define BCHP_XPT_RAVE_CXMEM_LOi_CX0_MAP_R_MASK 0x00000001 #define BCHP_XPT_RAVE_CXMEM_LOi_CX0_MAP_R_SHIFT 0 /*************************************************************************** *CXMEM_HI%i - Context Table 1 (for contexts 16 - 23) 0..287 ***************************************************************************/ #define BCHP_XPT_RAVE_CXMEM_HIi_ARRAY_BASE 0x00213800 #define BCHP_XPT_RAVE_CXMEM_HIi_ARRAY_START 0 #define BCHP_XPT_RAVE_CXMEM_HIi_ARRAY_END 287 #define BCHP_XPT_RAVE_CXMEM_HIi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *CXMEM_HI%i - Context Table 1 (for contexts 16 - 23) 0..287 ***************************************************************************/ /* XPT_RAVE :: CXMEM_HIi :: reserved_for_eco0 [31:16] */ #define BCHP_XPT_RAVE_CXMEM_HIi_reserved_for_eco0_MASK 0xffff0000 #define BCHP_XPT_RAVE_CXMEM_HIi_reserved_for_eco0_SHIFT 16 /* XPT_RAVE :: CXMEM_HIi :: CX23_MAP_G [15:15] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX23_MAP_G_MASK 0x00008000 #define BCHP_XPT_RAVE_CXMEM_HIi_CX23_MAP_G_SHIFT 15 /* XPT_RAVE :: CXMEM_HIi :: CX23_MAP_R [14:14] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX23_MAP_R_MASK 0x00004000 #define BCHP_XPT_RAVE_CXMEM_HIi_CX23_MAP_R_SHIFT 14 /* XPT_RAVE :: CXMEM_HIi :: CX22_MAP_G [13:13] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX22_MAP_G_MASK 0x00002000 #define BCHP_XPT_RAVE_CXMEM_HIi_CX22_MAP_G_SHIFT 13 /* XPT_RAVE :: CXMEM_HIi :: CX22_MAP_R [12:12] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX22_MAP_R_MASK 0x00001000 #define BCHP_XPT_RAVE_CXMEM_HIi_CX22_MAP_R_SHIFT 12 /* XPT_RAVE :: CXMEM_HIi :: CX21_MAP_G [11:11] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX21_MAP_G_MASK 0x00000800 #define BCHP_XPT_RAVE_CXMEM_HIi_CX21_MAP_G_SHIFT 11 /* XPT_RAVE :: CXMEM_HIi :: CX21_MAP_R [10:10] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX21_MAP_R_MASK 0x00000400 #define BCHP_XPT_RAVE_CXMEM_HIi_CX21_MAP_R_SHIFT 10 /* XPT_RAVE :: CXMEM_HIi :: CX20_MAP_G [09:09] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX20_MAP_G_MASK 0x00000200 #define BCHP_XPT_RAVE_CXMEM_HIi_CX20_MAP_G_SHIFT 9 /* XPT_RAVE :: CXMEM_HIi :: CX20_MAP_R [08:08] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX20_MAP_R_MASK 0x00000100 #define BCHP_XPT_RAVE_CXMEM_HIi_CX20_MAP_R_SHIFT 8 /* XPT_RAVE :: CXMEM_HIi :: CX19_MAP_G [07:07] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX19_MAP_G_MASK 0x00000080 #define BCHP_XPT_RAVE_CXMEM_HIi_CX19_MAP_G_SHIFT 7 /* XPT_RAVE :: CXMEM_HIi :: CX19_MAP_R [06:06] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX19_MAP_R_MASK 0x00000040 #define BCHP_XPT_RAVE_CXMEM_HIi_CX19_MAP_R_SHIFT 6 /* XPT_RAVE :: CXMEM_HIi :: CX18_MAP_G [05:05] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX18_MAP_G_MASK 0x00000020 #define BCHP_XPT_RAVE_CXMEM_HIi_CX18_MAP_G_SHIFT 5 /* XPT_RAVE :: CXMEM_HIi :: CX18_MAP_R [04:04] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX18_MAP_R_MASK 0x00000010 #define BCHP_XPT_RAVE_CXMEM_HIi_CX18_MAP_R_SHIFT 4 /* XPT_RAVE :: CXMEM_HIi :: CX17_MAP_G [03:03] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX17_MAP_G_MASK 0x00000008 #define BCHP_XPT_RAVE_CXMEM_HIi_CX17_MAP_G_SHIFT 3 /* XPT_RAVE :: CXMEM_HIi :: CX17_MAP_R [02:02] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX17_MAP_R_MASK 0x00000004 #define BCHP_XPT_RAVE_CXMEM_HIi_CX17_MAP_R_SHIFT 2 /* XPT_RAVE :: CXMEM_HIi :: CX16_MAP_G [01:01] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX16_MAP_G_MASK 0x00000002 #define BCHP_XPT_RAVE_CXMEM_HIi_CX16_MAP_G_SHIFT 1 /* XPT_RAVE :: CXMEM_HIi :: CX16_MAP_R [00:00] */ #define BCHP_XPT_RAVE_CXMEM_HIi_CX16_MAP_R_MASK 0x00000001 #define BCHP_XPT_RAVE_CXMEM_HIi_CX16_MAP_R_SHIFT 0 /*************************************************************************** *DMEM%i - Data Memory Address 0..2047 ***************************************************************************/ #define BCHP_XPT_RAVE_DMEMi_ARRAY_BASE 0x00214000 #define BCHP_XPT_RAVE_DMEMi_ARRAY_START 0 #define BCHP_XPT_RAVE_DMEMi_ARRAY_END 2047 #define BCHP_XPT_RAVE_DMEMi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *DMEM%i - Data Memory Address 0..2047 ***************************************************************************/ /* XPT_RAVE :: DMEMi :: reserved_for_eco0 [31:08] */ #define BCHP_XPT_RAVE_DMEMi_reserved_for_eco0_MASK 0xffffff00 #define BCHP_XPT_RAVE_DMEMi_reserved_for_eco0_SHIFT 8 /* XPT_RAVE :: DMEMi :: DATA [07:00] */ #define BCHP_XPT_RAVE_DMEMi_DATA_MASK 0x000000ff #define BCHP_XPT_RAVE_DMEMi_DATA_SHIFT 0 /*************************************************************************** *EMM_TID_MODE - TPIT EMM_TID_MODE Register (NDS only) ***************************************************************************/ /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_F [31:30] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_F_MASK 0xc0000000 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_F_SHIFT 30 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_E [29:28] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_E_MASK 0x30000000 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_E_SHIFT 28 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_D [27:26] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_D_MASK 0x0c000000 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_D_SHIFT 26 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_C [25:24] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_C_MASK 0x03000000 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_C_SHIFT 24 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_B [23:22] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_B_MASK 0x00c00000 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_B_SHIFT 22 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_A [21:20] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_A_MASK 0x00300000 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_A_SHIFT 20 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_9 [19:18] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_9_MASK 0x000c0000 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_9_SHIFT 18 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_8 [17:16] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_8_MASK 0x00030000 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_8_SHIFT 16 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_7 [15:14] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_7_MASK 0x0000c000 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_7_SHIFT 14 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_6 [13:12] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_6_MASK 0x00003000 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_6_SHIFT 12 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_5 [11:10] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_5_MASK 0x00000c00 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_5_SHIFT 10 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_4 [09:08] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_4_MASK 0x00000300 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_4_SHIFT 8 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_3 [07:06] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_3_MASK 0x000000c0 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_3_SHIFT 6 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_2 [05:04] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_2_MASK 0x00000030 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_2_SHIFT 4 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_1 [03:02] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_1_MASK 0x0000000c #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_1_SHIFT 2 /* XPT_RAVE :: EMM_TID_MODE :: EMM_TID_RULE_0 [01:00] */ #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_0_MASK 0x00000003 #define BCHP_XPT_RAVE_EMM_TID_MODE_EMM_TID_RULE_0_SHIFT 0 /*************************************************************************** *EMM_DATA_ID_1 - TPIT EMM_DATA_ID_1 Register (NDS only) ***************************************************************************/ /* XPT_RAVE :: EMM_DATA_ID_1 :: EMM_DATA_ID_1 [31:00] */ #define BCHP_XPT_RAVE_EMM_DATA_ID_1_EMM_DATA_ID_1_MASK 0xffffffff #define BCHP_XPT_RAVE_EMM_DATA_ID_1_EMM_DATA_ID_1_SHIFT 0 /*************************************************************************** *EMM_DATA_ID_2 - TPIT EMM_DATA_ID_2 Register (NDS only) ***************************************************************************/ /* XPT_RAVE :: EMM_DATA_ID_2 :: EMM_DATA_ID_2 [31:00] */ #define BCHP_XPT_RAVE_EMM_DATA_ID_2_EMM_DATA_ID_2_MASK 0xffffffff #define BCHP_XPT_RAVE_EMM_DATA_ID_2_EMM_DATA_ID_2_SHIFT 0 /*************************************************************************** *EMM_DATA_ID_3 - TPIT EMM_DATA_ID_3 Register (NDS only) ***************************************************************************/ /* XPT_RAVE :: EMM_DATA_ID_3 :: EMM_DATA_ID_3 [31:00] */ #define BCHP_XPT_RAVE_EMM_DATA_ID_3_EMM_DATA_ID_3_MASK 0xffffffff #define BCHP_XPT_RAVE_EMM_DATA_ID_3_EMM_DATA_ID_3_SHIFT 0 /*************************************************************************** *EMM_MASK_ID_1 - TPIT EMM_MASK_ID_1 Register (NDS only) ***************************************************************************/ /* XPT_RAVE :: EMM_MASK_ID_1 :: EMM_DATA_MASK_ID_1 [31:00] */ #define BCHP_XPT_RAVE_EMM_MASK_ID_1_EMM_DATA_MASK_ID_1_MASK 0xffffffff #define BCHP_XPT_RAVE_EMM_MASK_ID_1_EMM_DATA_MASK_ID_1_SHIFT 0 /*************************************************************************** *EMM_MASK_ID_2 - TPIT EMM_MASK_ID_2 Register (NDS only) ***************************************************************************/ /* XPT_RAVE :: EMM_MASK_ID_2 :: EMM_DATA_MASK_ID_2 [31:00] */ #define BCHP_XPT_RAVE_EMM_MASK_ID_2_EMM_DATA_MASK_ID_2_MASK 0xffffffff #define BCHP_XPT_RAVE_EMM_MASK_ID_2_EMM_DATA_MASK_ID_2_SHIFT 0 /*************************************************************************** *EMM_MASK_ID_3 - TPIT EMM_MASK_ID_3 Register (NDS only) ***************************************************************************/ /* XPT_RAVE :: EMM_MASK_ID_3 :: EMM_DATA_MASK_ID_3 [31:00] */ #define BCHP_XPT_RAVE_EMM_MASK_ID_3_EMM_DATA_MASK_ID_3_MASK 0xffffffff #define BCHP_XPT_RAVE_EMM_MASK_ID_3_EMM_DATA_MASK_ID_3_SHIFT 0 /*************************************************************************** *TPIT_TIME_TICK - TPIT Time Tick Register ***************************************************************************/ /* XPT_RAVE :: TPIT_TIME_TICK :: reserved0 [31:24] */ #define BCHP_XPT_RAVE_TPIT_TIME_TICK_reserved0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT_TIME_TICK_reserved0_SHIFT 24 /* XPT_RAVE :: TPIT_TIME_TICK :: TPIT_TIME_TICK [23:00] */ #define BCHP_XPT_RAVE_TPIT_TIME_TICK_TPIT_TIME_TICK_MASK 0x00ffffff #define BCHP_XPT_RAVE_TPIT_TIME_TICK_TPIT_TIME_TICK_SHIFT 0 /*************************************************************************** *TPIT_PKT_TIMEOUT - TPIT Time Packet Timeout Register ***************************************************************************/ /* XPT_RAVE :: TPIT_PKT_TIMEOUT :: reserved0 [31:24] */ #define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT_reserved0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT_reserved0_SHIFT 24 /* XPT_RAVE :: TPIT_PKT_TIMEOUT :: TPIT_PKT_TIMEOUT [23:00] */ #define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT_TPIT_PKT_TIMEOUT_MASK 0x00ffffff #define BCHP_XPT_RAVE_TPIT_PKT_TIMEOUT_TPIT_PKT_TIMEOUT_SHIFT 0 /*************************************************************************** *TPIT_EVE_TIMEOUT - TPIT Time Event Timeout Register ***************************************************************************/ /* XPT_RAVE :: TPIT_EVE_TIMEOUT :: reserved0 [31:24] */ #define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT_reserved0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT_reserved0_SHIFT 24 /* XPT_RAVE :: TPIT_EVE_TIMEOUT :: TPIT_EVE_TIMEOUT [23:00] */ #define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT_TPIT_EVE_TIMEOUT_MASK 0x00ffffff #define BCHP_XPT_RAVE_TPIT_EVE_TIMEOUT_TPIT_EVE_TIMEOUT_SHIFT 0 /*************************************************************************** *TPIT0_PID_TABLE%i - TPIT0 PID Table 0..15 ***************************************************************************/ #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_ARRAY_BASE 0x0021a000 #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_ARRAY_START 0 #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_ARRAY_END 15 #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TPIT0_PID_TABLE%i - TPIT0 PID Table 0..15 ***************************************************************************/ /* XPT_RAVE :: TPIT0_PID_TABLEi :: reserved_for_eco0 [31:21] */ #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_reserved_for_eco0_MASK 0xffe00000 #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_HD [20:17] */ #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_HD_MASK 0x001e0000 #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_HD_SHIFT 17 /* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_HD_FILT_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_HD_FILT_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_HD_FILT_EN_SHIFT 16 /* XPT_RAVE :: TPIT0_PID_TABLEi :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */ #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_CORRUPT_ENABLE_MASK 0x00004000 #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT 14 /* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */ #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_PARSE_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_PARSE_ENABLE_SHIFT 13 /* XPT_RAVE :: TPIT0_PID_TABLEi :: REC_PID [12:00] */ #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_PID_MASK 0x00001fff #define BCHP_XPT_RAVE_TPIT0_PID_TABLEi_REC_PID_SHIFT 0 /*************************************************************************** *TPIT0_PAR_TABLE%i - TPIT0 Parse Table 0..15 ***************************************************************************/ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_ARRAY_BASE 0x0021a040 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_ARRAY_START 0 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_ARRAY_END 15 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TPIT0_PAR_TABLE%i - TPIT0 Parse Table 0..15 ***************************************************************************/ /* union - case MPEG [31:00] */ /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT 24 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK 0x00800000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT 23 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK 0x00080000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK 0x00040000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT 16 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: reserved1 [15:13] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_reserved1_MASK 0x0000e000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_reserved1_SHIFT 13 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK 0x00000080 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: reserved0 [03:02] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_reserved0_MASK 0x0000000c #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_reserved0_SHIFT 2 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT 0 /* union - case DIRECTV [31:00] */ /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved2_MASK 0xc0000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved2_SHIFT 30 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK 0x20000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK 0x10000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT 28 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK 0x02000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT 25 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT 24 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK 0x00f00000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT 20 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT 16 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved1_MASK 0x0000fc00 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved1_SHIFT 10 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK 0x00000200 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT 9 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT 8 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK 0x000000f0 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT 4 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved0_MASK 0x0000000e #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_reserved0_SHIFT 1 /* XPT_RAVE :: TPIT0_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */ #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT0_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT 0 /*************************************************************************** *TPIT1_PID_TABLE%i - TPIT1 PID Table 0..15 ***************************************************************************/ #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_ARRAY_BASE 0x0021a080 #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_ARRAY_START 0 #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_ARRAY_END 15 #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TPIT1_PID_TABLE%i - TPIT1 PID Table 0..15 ***************************************************************************/ /* XPT_RAVE :: TPIT1_PID_TABLEi :: reserved_for_eco0 [31:21] */ #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_reserved_for_eco0_MASK 0xffe00000 #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_HD [20:17] */ #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_HD_MASK 0x001e0000 #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_HD_SHIFT 17 /* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_HD_FILT_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_HD_FILT_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_HD_FILT_EN_SHIFT 16 /* XPT_RAVE :: TPIT1_PID_TABLEi :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */ #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_CORRUPT_ENABLE_MASK 0x00004000 #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT 14 /* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */ #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_PARSE_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_PARSE_ENABLE_SHIFT 13 /* XPT_RAVE :: TPIT1_PID_TABLEi :: REC_PID [12:00] */ #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_PID_MASK 0x00001fff #define BCHP_XPT_RAVE_TPIT1_PID_TABLEi_REC_PID_SHIFT 0 /*************************************************************************** *TPIT1_PAR_TABLE%i - TPIT1 Parse Table 0..15 ***************************************************************************/ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_ARRAY_BASE 0x0021a0c0 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_ARRAY_START 0 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_ARRAY_END 15 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TPIT1_PAR_TABLE%i - TPIT1 Parse Table 0..15 ***************************************************************************/ /* union - case MPEG [31:00] */ /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT 24 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK 0x00800000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT 23 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK 0x00080000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK 0x00040000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT 16 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: reserved1 [15:13] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_reserved1_MASK 0x0000e000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_reserved1_SHIFT 13 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK 0x00000080 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: reserved0 [03:02] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_reserved0_MASK 0x0000000c #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_reserved0_SHIFT 2 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT 0 /* union - case DIRECTV [31:00] */ /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved2_MASK 0xc0000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved2_SHIFT 30 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK 0x20000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK 0x10000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT 28 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK 0x02000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT 25 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT 24 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK 0x00f00000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT 20 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT 16 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved1_MASK 0x0000fc00 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved1_SHIFT 10 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK 0x00000200 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT 9 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT 8 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK 0x000000f0 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT 4 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved0_MASK 0x0000000e #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_reserved0_SHIFT 1 /* XPT_RAVE :: TPIT1_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */ #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT1_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT 0 /*************************************************************************** *TPIT2_PID_TABLE%i - TPIT2 PID Table 0..15 ***************************************************************************/ #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_ARRAY_BASE 0x0021a100 #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_ARRAY_START 0 #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_ARRAY_END 15 #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TPIT2_PID_TABLE%i - TPIT2 PID Table 0..15 ***************************************************************************/ /* XPT_RAVE :: TPIT2_PID_TABLEi :: reserved_for_eco0 [31:21] */ #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_reserved_for_eco0_MASK 0xffe00000 #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_HD [20:17] */ #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_HD_MASK 0x001e0000 #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_HD_SHIFT 17 /* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_HD_FILT_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_HD_FILT_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_HD_FILT_EN_SHIFT 16 /* XPT_RAVE :: TPIT2_PID_TABLEi :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */ #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_CORRUPT_ENABLE_MASK 0x00004000 #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT 14 /* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */ #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_PARSE_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_PARSE_ENABLE_SHIFT 13 /* XPT_RAVE :: TPIT2_PID_TABLEi :: REC_PID [12:00] */ #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_PID_MASK 0x00001fff #define BCHP_XPT_RAVE_TPIT2_PID_TABLEi_REC_PID_SHIFT 0 /*************************************************************************** *TPIT2_PAR_TABLE%i - TPIT2 Parse Table 0..15 ***************************************************************************/ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_ARRAY_BASE 0x0021a140 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_ARRAY_START 0 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_ARRAY_END 15 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TPIT2_PAR_TABLE%i - TPIT2 Parse Table 0..15 ***************************************************************************/ /* union - case MPEG [31:00] */ /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT 24 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK 0x00800000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT 23 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK 0x00080000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK 0x00040000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT 16 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: reserved1 [15:13] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_reserved1_MASK 0x0000e000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_reserved1_SHIFT 13 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK 0x00000080 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: reserved0 [03:02] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_reserved0_MASK 0x0000000c #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_reserved0_SHIFT 2 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT 0 /* union - case DIRECTV [31:00] */ /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved2_MASK 0xc0000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved2_SHIFT 30 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK 0x20000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK 0x10000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT 28 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK 0x02000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT 25 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT 24 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK 0x00f00000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT 20 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT 16 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved1_MASK 0x0000fc00 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved1_SHIFT 10 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK 0x00000200 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT 9 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT 8 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK 0x000000f0 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT 4 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved0_MASK 0x0000000e #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_reserved0_SHIFT 1 /* XPT_RAVE :: TPIT2_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */ #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT2_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT 0 /*************************************************************************** *TPIT3_PID_TABLE%i - TPIT3 PID Table 0..15 ***************************************************************************/ #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_ARRAY_BASE 0x0021a180 #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_ARRAY_START 0 #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_ARRAY_END 15 #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TPIT3_PID_TABLE%i - TPIT3 PID Table 0..15 ***************************************************************************/ /* XPT_RAVE :: TPIT3_PID_TABLEi :: reserved_for_eco0 [31:21] */ #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_reserved_for_eco0_MASK 0xffe00000 #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_HD [20:17] */ #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_HD_MASK 0x001e0000 #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_HD_SHIFT 17 /* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_HD_FILT_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_HD_FILT_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_HD_FILT_EN_SHIFT 16 /* XPT_RAVE :: TPIT3_PID_TABLEi :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */ #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_CORRUPT_ENABLE_MASK 0x00004000 #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT 14 /* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */ #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_PARSE_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_PARSE_ENABLE_SHIFT 13 /* XPT_RAVE :: TPIT3_PID_TABLEi :: REC_PID [12:00] */ #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_PID_MASK 0x00001fff #define BCHP_XPT_RAVE_TPIT3_PID_TABLEi_REC_PID_SHIFT 0 /*************************************************************************** *TPIT3_PAR_TABLE%i - TPIT3 Parse Table 0..15 ***************************************************************************/ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_ARRAY_BASE 0x0021a1c0 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_ARRAY_START 0 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_ARRAY_END 15 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TPIT3_PAR_TABLE%i - TPIT3 Parse Table 0..15 ***************************************************************************/ /* union - case MPEG [31:00] */ /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT 24 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK 0x00800000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT 23 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK 0x00080000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK 0x00040000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT 16 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: reserved1 [15:13] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_reserved1_MASK 0x0000e000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_reserved1_SHIFT 13 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK 0x00000080 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: reserved0 [03:02] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_reserved0_MASK 0x0000000c #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_reserved0_SHIFT 2 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT 0 /* union - case DIRECTV [31:00] */ /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved2_MASK 0xc0000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved2_SHIFT 30 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK 0x20000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK 0x10000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT 28 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK 0x02000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT 25 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT 24 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK 0x00f00000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT 20 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT 16 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved1_MASK 0x0000fc00 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved1_SHIFT 10 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK 0x00000200 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT 9 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT 8 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK 0x000000f0 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT 4 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved0_MASK 0x0000000e #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_reserved0_SHIFT 1 /* XPT_RAVE :: TPIT3_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */ #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT3_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT 0 /*************************************************************************** *TPIT4_PID_TABLE%i - TPIT4 PID Table 0..15 ***************************************************************************/ #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_ARRAY_BASE 0x0021a200 #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_ARRAY_START 0 #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_ARRAY_END 15 #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TPIT4_PID_TABLE%i - TPIT4 PID Table 0..15 ***************************************************************************/ /* XPT_RAVE :: TPIT4_PID_TABLEi :: reserved_for_eco0 [31:21] */ #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_reserved_for_eco0_MASK 0xffe00000 #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_HD [20:17] */ #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_HD_MASK 0x001e0000 #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_HD_SHIFT 17 /* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_HD_FILT_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_HD_FILT_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_HD_FILT_EN_SHIFT 16 /* XPT_RAVE :: TPIT4_PID_TABLEi :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */ #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_CORRUPT_ENABLE_MASK 0x00004000 #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT 14 /* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */ #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_PARSE_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_PARSE_ENABLE_SHIFT 13 /* XPT_RAVE :: TPIT4_PID_TABLEi :: REC_PID [12:00] */ #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_PID_MASK 0x00001fff #define BCHP_XPT_RAVE_TPIT4_PID_TABLEi_REC_PID_SHIFT 0 /*************************************************************************** *TPIT4_PAR_TABLE%i - TPIT4 Parse Table 0..15 ***************************************************************************/ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_ARRAY_BASE 0x0021a240 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_ARRAY_START 0 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_ARRAY_END 15 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TPIT4_PAR_TABLE%i - TPIT4 Parse Table 0..15 ***************************************************************************/ /* union - case MPEG [31:00] */ /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT 24 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK 0x00800000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT 23 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK 0x00080000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK 0x00040000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT 16 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: reserved1 [15:13] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_reserved1_MASK 0x0000e000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_reserved1_SHIFT 13 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK 0x00000080 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: reserved0 [03:02] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_reserved0_MASK 0x0000000c #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_reserved0_SHIFT 2 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT 0 /* union - case DIRECTV [31:00] */ /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved2_MASK 0xc0000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved2_SHIFT 30 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK 0x20000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK 0x10000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT 28 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK 0x02000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT 25 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT 24 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK 0x00f00000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT 20 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT 16 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved1_MASK 0x0000fc00 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved1_SHIFT 10 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK 0x00000200 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT 9 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT 8 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK 0x000000f0 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT 4 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved0_MASK 0x0000000e #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_reserved0_SHIFT 1 /* XPT_RAVE :: TPIT4_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */ #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT4_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT 0 /*************************************************************************** *TPIT5_PID_TABLE%i - TPIT5 PID Table 0..15 ***************************************************************************/ #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_ARRAY_BASE 0x0021a280 #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_ARRAY_START 0 #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_ARRAY_END 15 #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TPIT5_PID_TABLE%i - TPIT5 PID Table 0..15 ***************************************************************************/ /* XPT_RAVE :: TPIT5_PID_TABLEi :: reserved_for_eco0 [31:21] */ #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_reserved_for_eco0_MASK 0xffe00000 #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_reserved_for_eco0_SHIFT 21 /* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_HD [20:17] */ #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_HD_MASK 0x001e0000 #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_HD_SHIFT 17 /* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_HD_FILT_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_HD_FILT_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_HD_FILT_EN_SHIFT 16 /* XPT_RAVE :: TPIT5_PID_TABLEi :: reserved_for_eco1 [15:15] */ #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_reserved_for_eco1_MASK 0x00008000 #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_reserved_for_eco1_SHIFT 15 /* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_CORRUPT_ENABLE [14:14] */ #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_CORRUPT_ENABLE_MASK 0x00004000 #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_CORRUPT_ENABLE_SHIFT 14 /* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_PARSE_ENABLE [13:13] */ #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_PARSE_ENABLE_MASK 0x00002000 #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_PARSE_ENABLE_SHIFT 13 /* XPT_RAVE :: TPIT5_PID_TABLEi :: REC_PID [12:00] */ #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_PID_MASK 0x00001fff #define BCHP_XPT_RAVE_TPIT5_PID_TABLEi_REC_PID_SHIFT 0 /*************************************************************************** *TPIT5_PAR_TABLE%i - TPIT5 Parse Table 0..15 ***************************************************************************/ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_ARRAY_BASE 0x0021a2c0 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_ARRAY_START 0 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_ARRAY_END 15 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TPIT5_PAR_TABLE%i - TPIT5 Parse Table 0..15 ***************************************************************************/ /* union - case MPEG [31:00] */ /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN3 [31:31] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_MASK 0x80000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN3_SHIFT 31 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN2 [30:30] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_MASK 0x40000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN2_SHIFT 30 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ECM_POLARITY_CHANGE_EN [29:29] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_MASK 0x20000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ECM_POLARITY_CHANGE_EN_SHIFT 29 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_SECTION_FILTER_EN [28:28] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_MASK 0x10000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SECTION_FILTER_EN_SHIFT 28 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_EN [27:27] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_EN_SHIFT 27 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_EN [26:26] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_EN_SHIFT 26 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_EN [25:25] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_MASK 0x02000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_EN_SHIFT 25 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_EN [24:24] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_OPCR_FLAG_EN_SHIFT 24 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_EN [23:23] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_MASK 0x00800000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PCR_FLAG_EN_SHIFT 23 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_EN [22:22] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_MASK 0x00400000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_EN_SHIFT 22 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_EN [21:21] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_MASK 0x00200000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_EN_SHIFT 21 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_EN [20:20] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_MASK 0x00100000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_EN_SHIFT 20 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_AFC_CHANGE_EN [19:19] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_MASK 0x00080000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_AFC_CHANGE_EN_SHIFT 19 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_TSC_CHANGE_EN [18:18] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_MASK 0x00040000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TSC_CHANGE_EN_SHIFT 18 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_EN [17:17] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_MASK 0x00020000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_EN_SHIFT 17 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PUSI_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PUSI_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PUSI_EN_SHIFT 16 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: reserved1 [15:13] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_reserved1_MASK 0x0000e000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_reserved1_SHIFT 13 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PACKET_PRESENT [12:12] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_MASK 0x00001000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PACKET_PRESENT_SHIFT 12 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ADAPT_FIELD_EXT_FLAG_COMP [11:11] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_MASK 0x00000800 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ADAPT_FIELD_EXT_FLAG_COMP_SHIFT 11 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PRIVATE_DATA_FLAG_COMP [10:10] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_MASK 0x00000400 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PRIVATE_DATA_FLAG_COMP_SHIFT 10 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_SPLICING_POINT_FLAG_COMP [09:09] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_MASK 0x00000200 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_SPLICING_POINT_FLAG_COMP_SHIFT 9 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_OPCR_FLAG_COMP [08:08] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_OPCR_FLAG_COMP_SHIFT 8 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PCR_FLAG_COMP [07:07] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_MASK 0x00000080 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PCR_FLAG_COMP_SHIFT 7 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_ES_PRIORITY_IND_COMP [06:06] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_MASK 0x00000040 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_ES_PRIORITY_IND_COMP_SHIFT 6 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_RANDOM_ACCESS_IND_COMP [05:05] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_MASK 0x00000020 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_RANDOM_ACCESS_IND_COMP_SHIFT 5 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_DISCONTINUITY_IND_COMP [04:04] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_MASK 0x00000010 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_DISCONTINUITY_IND_COMP_SHIFT 4 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: reserved0 [03:02] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_reserved0_MASK 0x0000000c #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_reserved0_SHIFT 2 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_TRANSPORT_PRIORITY_COMP [01:01] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_MASK 0x00000002 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_TRANSPORT_PRIORITY_COMP_SHIFT 1 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: MPEG :: RP_PUSI_COMP [00:00] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PUSI_COMP_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_MPEG_RP_PUSI_COMP_SHIFT 0 /* union - case DIRECTV [31:00] */ /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: reserved2 [31:30] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved2_MASK 0xc0000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved2_SHIFT 30 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_AUX_DET_EN [29:29] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_MASK 0x20000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_AUX_DET_EN_SHIFT 29 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_TC_DET_EN [28:28] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_MASK 0x10000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_TC_DET_EN_SHIFT 28 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CWP_DET_EN [27:27] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_MASK 0x08000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CWP_DET_EN_SHIFT 27 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_RTS_DET_EN [26:26] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_MASK 0x04000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_RTS_DET_EN_SHIFT 26 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CFF_EN [25:25] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CFF_EN_MASK 0x02000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CFF_EN_SHIFT 25 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_MF_EN [24:24] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_MF_EN_MASK 0x01000000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_MF_EN_SHIFT 24 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_HD_EN [23:20] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_HD_EN_MASK 0x00f00000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_HD_EN_SHIFT 20 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CSAUX_CHANGE_EN [19:19] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_MASK 0x00080000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CSAUX_CHANGE_EN_SHIFT 19 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CS_CHANGE_EN [18:18] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_MASK 0x00040000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CS_CHANGE_EN_SHIFT 18 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CF_CHANGE_EN [17:17] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_MASK 0x00020000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CF_CHANGE_EN_SHIFT 17 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_BB_EN [16:16] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_BB_EN_MASK 0x00010000 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_BB_EN_SHIFT 16 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: reserved1 [15:10] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved1_MASK 0x0000fc00 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved1_SHIFT 10 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_CFF_COMP [09:09] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CFF_COMP_MASK 0x00000200 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_CFF_COMP_SHIFT 9 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_MF_COMP [08:08] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_MF_COMP_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_MF_COMP_SHIFT 8 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_HD_MASK [07:04] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_HD_MASK_MASK 0x000000f0 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_HD_MASK_SHIFT 4 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: reserved0 [03:01] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved0_MASK 0x0000000e #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_reserved0_SHIFT 1 /* XPT_RAVE :: TPIT5_PAR_TABLEi :: DIRECTV :: RP_BB_COMP [00:00] */ #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_BB_COMP_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT5_PAR_TABLEi_DIRECTV_RP_BB_COMP_SHIFT 0 /*************************************************************************** *TPIT0_CTRL1 - TPIT 0 Control Register 1 ***************************************************************************/ /* XPT_RAVE :: TPIT0_CTRL1 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_TPIT0_CTRL1_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_TPIT0_CTRL1_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: TPIT0_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */ #define BCHP_XPT_RAVE_TPIT0_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT0_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT 8 /* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */ #define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_TIME_TICK_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_TIME_TICK_EN_SHIFT 7 /* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */ #define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_SPAN_SECTION_EN_MASK 0x00000060 #define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT 5 /* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_PCR_MODE [04:04] */ #define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_PCR_MODE_MASK 0x00000010 #define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_PCR_MODE_SHIFT 4 /* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */ #define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_EVENT_IDLE_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT 3 /* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_EMM_TID_EN [02:02] */ #define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_EMM_TID_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_EMM_TID_EN_SHIFT 2 /* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */ #define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_RECORD_IDLE_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT 1 /* XPT_RAVE :: TPIT0_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */ #define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_FIRST_PACKET_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT0_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT 0 /*************************************************************************** *TPIT0_COR1 - TPIT 0 Corrupt Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_COR1 :: reserved_for_eco0 [31:24] */ #define BCHP_XPT_RAVE_TPIT0_COR1_reserved_for_eco0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT0_COR1_reserved_for_eco0_SHIFT 24 /* XPT_RAVE :: TPIT0_COR1 :: REC_CORRUPT_BYTE [23:16] */ #define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_BYTE_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_BYTE_SHIFT 16 /* XPT_RAVE :: TPIT0_COR1 :: REC_CORRUPT_START [15:08] */ #define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_START_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_START_SHIFT 8 /* XPT_RAVE :: TPIT0_COR1 :: REC_CORRUPT_END [07:00] */ #define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_END_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT0_COR1_REC_CORRUPT_END_SHIFT 0 /*************************************************************************** *TPIT0_TID - TPIT TID Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_TID :: reserved_for_eco0 [31:24] */ #define BCHP_XPT_RAVE_TPIT0_TID_reserved_for_eco0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT0_TID_reserved_for_eco0_SHIFT 24 /* XPT_RAVE :: TPIT0_TID :: ECM_TID_ODD [23:16] */ #define BCHP_XPT_RAVE_TPIT0_TID_ECM_TID_ODD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT0_TID_ECM_TID_ODD_SHIFT 16 /* XPT_RAVE :: TPIT0_TID :: ECM_TID_EVEN [15:08] */ #define BCHP_XPT_RAVE_TPIT0_TID_ECM_TID_EVEN_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT0_TID_ECM_TID_EVEN_SHIFT 8 /* XPT_RAVE :: TPIT0_TID :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_TPIT0_TID_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_TPIT0_TID_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: TPIT0_TID :: EMM_TID [03:00] */ #define BCHP_XPT_RAVE_TPIT0_TID_EMM_TID_MASK 0x0000000f #define BCHP_XPT_RAVE_TPIT0_TID_EMM_TID_SHIFT 0 /*************************************************************************** *TPIT0_TID2 - TPIT TID Register 2 ***************************************************************************/ /* XPT_RAVE :: TPIT0_TID2 :: ECM_TID_ODD3 [31:24] */ #define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_ODD3_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_ODD3_SHIFT 24 /* XPT_RAVE :: TPIT0_TID2 :: ECM_TID_EVEN3 [23:16] */ #define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_EVEN3_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_EVEN3_SHIFT 16 /* XPT_RAVE :: TPIT0_TID2 :: ECM_TID_ODD2 [15:08] */ #define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_ODD2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_ODD2_SHIFT 8 /* XPT_RAVE :: TPIT0_TID2 :: ECM_TID_EVEN2 [07:00] */ #define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_EVEN2_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT0_TID2_ECM_TID_EVEN2_SHIFT 0 /*************************************************************************** *TPIT0_STATE0 - TPIT 0 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_STATE0 :: TPIT_TRACK_STATE0 [31:00] */ #define BCHP_XPT_RAVE_TPIT0_STATE0_TPIT_TRACK_STATE0_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT0_STATE0_TPIT_TRACK_STATE0_SHIFT 0 /*************************************************************************** *TPIT0_STATE1 - TPIT 0 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_STATE1 :: TPIT_TRACK_STATE1 [31:00] */ #define BCHP_XPT_RAVE_TPIT0_STATE1_TPIT_TRACK_STATE1_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT0_STATE1_TPIT_TRACK_STATE1_SHIFT 0 /*************************************************************************** *TPIT0_STATE2 - TPIT 0 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_STATE2 :: TPIT_TRACK_STATE2 [31:00] */ #define BCHP_XPT_RAVE_TPIT0_STATE2_TPIT_TRACK_STATE2_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT0_STATE2_TPIT_TRACK_STATE2_SHIFT 0 /*************************************************************************** *TPIT0_STATE2a - TPIT 0 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_STATE2a :: TPIT_TRACK_STATE2a [31:00] */ #define BCHP_XPT_RAVE_TPIT0_STATE2a_TPIT_TRACK_STATE2a_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT0_STATE2a_TPIT_TRACK_STATE2a_SHIFT 0 /*************************************************************************** *TPIT0_STATE2b - TPIT 0 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_STATE2b :: TPIT_TRACK_STATE2b [31:00] */ #define BCHP_XPT_RAVE_TPIT0_STATE2b_TPIT_TRACK_STATE2b_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT0_STATE2b_TPIT_TRACK_STATE2b_SHIFT 0 /*************************************************************************** *TPIT0_STATE2c - TPIT 0 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_STATE2c :: TPIT_TRACK_STATE2c [31:00] */ #define BCHP_XPT_RAVE_TPIT0_STATE2c_TPIT_TRACK_STATE2c_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT0_STATE2c_TPIT_TRACK_STATE2c_SHIFT 0 /*************************************************************************** *TPIT0_STATE2d - TPIT 0 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_STATE2d :: TPIT_TRACK_STATE2d [31:00] */ #define BCHP_XPT_RAVE_TPIT0_STATE2d_TPIT_TRACK_STATE2d_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT0_STATE2d_TPIT_TRACK_STATE2d_SHIFT 0 /*************************************************************************** *TPIT0_STATE3 - TPIT 0 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_STATE3 :: TPIT_TRACK_STATE3 [31:00] */ #define BCHP_XPT_RAVE_TPIT0_STATE3_TPIT_TRACK_STATE3_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT0_STATE3_TPIT_TRACK_STATE3_SHIFT 0 /*************************************************************************** *TPIT0_STATE4 - TPIT 0 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_STATE4 :: TPIT_CUR_PCR [31:00] */ #define BCHP_XPT_RAVE_TPIT0_STATE4_TPIT_CUR_PCR_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT0_STATE4_TPIT_CUR_PCR_SHIFT 0 /*************************************************************************** *TPIT0_STATE5 - TPIT 0 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT0_STATE5_TPIT_LAST_PACKET_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT0_STATE5_TPIT_LAST_PACKET_LO_SHIFT 0 /*************************************************************************** *TPIT0_STATE6 - TPIT 0 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT0_STATE6_TPIT_LAST_EVENT_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT0_STATE6_TPIT_LAST_EVENT_LO_SHIFT 0 /*************************************************************************** *TPIT0_STATE7 - TPIT 0 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_STATE7 :: reserved_for_eco0 [31:20] */ #define BCHP_XPT_RAVE_TPIT0_STATE7_reserved_for_eco0_MASK 0xfff00000 #define BCHP_XPT_RAVE_TPIT0_STATE7_reserved_for_eco0_SHIFT 20 /* XPT_RAVE :: TPIT0_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */ #define BCHP_XPT_RAVE_TPIT0_STATE7_TPIT_LAST_EVENT_HI_MASK 0x000ffc00 #define BCHP_XPT_RAVE_TPIT0_STATE7_TPIT_LAST_EVENT_HI_SHIFT 10 /* XPT_RAVE :: TPIT0_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */ #define BCHP_XPT_RAVE_TPIT0_STATE7_TPIT_LAST_PACKET_HI_MASK 0x000003ff #define BCHP_XPT_RAVE_TPIT0_STATE7_TPIT_LAST_PACKET_HI_SHIFT 0 /*************************************************************************** *TPIT0_STATE8 - TPIT 0 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_STATE8 :: TPIT_LAST_TICK_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT0_STATE8_TPIT_LAST_TICK_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT0_STATE8_TPIT_LAST_TICK_LO_SHIFT 0 /*************************************************************************** *TPIT0_STATE9 - TPIT 0 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT0_STATE9 :: reserved_for_eco0 [31:10] */ #define BCHP_XPT_RAVE_TPIT0_STATE9_reserved_for_eco0_MASK 0xfffffc00 #define BCHP_XPT_RAVE_TPIT0_STATE9_reserved_for_eco0_SHIFT 10 /* XPT_RAVE :: TPIT0_STATE9 :: TPIT_LAST_TICK_HI [09:00] */ #define BCHP_XPT_RAVE_TPIT0_STATE9_TPIT_LAST_TICK_HI_MASK 0x000003ff #define BCHP_XPT_RAVE_TPIT0_STATE9_TPIT_LAST_TICK_HI_SHIFT 0 /*************************************************************************** *TPIT1_CTRL1 - TPIT 1 Control Register 1 ***************************************************************************/ /* XPT_RAVE :: TPIT1_CTRL1 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_TPIT1_CTRL1_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_TPIT1_CTRL1_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: TPIT1_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */ #define BCHP_XPT_RAVE_TPIT1_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT1_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT 8 /* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */ #define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_TIME_TICK_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_TIME_TICK_EN_SHIFT 7 /* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */ #define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_SPAN_SECTION_EN_MASK 0x00000060 #define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT 5 /* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_PCR_MODE [04:04] */ #define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_PCR_MODE_MASK 0x00000010 #define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_PCR_MODE_SHIFT 4 /* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */ #define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_EVENT_IDLE_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT 3 /* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_EMM_TID_EN [02:02] */ #define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_EMM_TID_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_EMM_TID_EN_SHIFT 2 /* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */ #define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_RECORD_IDLE_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT 1 /* XPT_RAVE :: TPIT1_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */ #define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_FIRST_PACKET_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT1_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT 0 /*************************************************************************** *TPIT1_COR1 - TPIT 1 Corrupt Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_COR1 :: reserved_for_eco0 [31:24] */ #define BCHP_XPT_RAVE_TPIT1_COR1_reserved_for_eco0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT1_COR1_reserved_for_eco0_SHIFT 24 /* XPT_RAVE :: TPIT1_COR1 :: REC_CORRUPT_BYTE [23:16] */ #define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_BYTE_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_BYTE_SHIFT 16 /* XPT_RAVE :: TPIT1_COR1 :: REC_CORRUPT_START [15:08] */ #define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_START_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_START_SHIFT 8 /* XPT_RAVE :: TPIT1_COR1 :: REC_CORRUPT_END [07:00] */ #define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_END_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT1_COR1_REC_CORRUPT_END_SHIFT 0 /*************************************************************************** *TPIT1_TID - TPIT TID Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_TID :: reserved_for_eco0 [31:24] */ #define BCHP_XPT_RAVE_TPIT1_TID_reserved_for_eco0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT1_TID_reserved_for_eco0_SHIFT 24 /* XPT_RAVE :: TPIT1_TID :: ECM_TID_ODD [23:16] */ #define BCHP_XPT_RAVE_TPIT1_TID_ECM_TID_ODD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT1_TID_ECM_TID_ODD_SHIFT 16 /* XPT_RAVE :: TPIT1_TID :: ECM_TID_EVEN [15:08] */ #define BCHP_XPT_RAVE_TPIT1_TID_ECM_TID_EVEN_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT1_TID_ECM_TID_EVEN_SHIFT 8 /* XPT_RAVE :: TPIT1_TID :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_TPIT1_TID_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_TPIT1_TID_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: TPIT1_TID :: EMM_TID [03:00] */ #define BCHP_XPT_RAVE_TPIT1_TID_EMM_TID_MASK 0x0000000f #define BCHP_XPT_RAVE_TPIT1_TID_EMM_TID_SHIFT 0 /*************************************************************************** *TPIT1_TID2 - TPIT TID Register 2 ***************************************************************************/ /* XPT_RAVE :: TPIT1_TID2 :: ECM_TID_ODD3 [31:24] */ #define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_ODD3_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_ODD3_SHIFT 24 /* XPT_RAVE :: TPIT1_TID2 :: ECM_TID_EVEN3 [23:16] */ #define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_EVEN3_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_EVEN3_SHIFT 16 /* XPT_RAVE :: TPIT1_TID2 :: ECM_TID_ODD2 [15:08] */ #define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_ODD2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_ODD2_SHIFT 8 /* XPT_RAVE :: TPIT1_TID2 :: ECM_TID_EVEN2 [07:00] */ #define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_EVEN2_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT1_TID2_ECM_TID_EVEN2_SHIFT 0 /*************************************************************************** *TPIT1_STATE0 - TPIT 1 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_STATE0 :: TPIT_TRACK_STATE0 [31:00] */ #define BCHP_XPT_RAVE_TPIT1_STATE0_TPIT_TRACK_STATE0_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT1_STATE0_TPIT_TRACK_STATE0_SHIFT 0 /*************************************************************************** *TPIT1_STATE1 - TPIT 1 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_STATE1 :: TPIT_TRACK_STATE1 [31:00] */ #define BCHP_XPT_RAVE_TPIT1_STATE1_TPIT_TRACK_STATE1_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT1_STATE1_TPIT_TRACK_STATE1_SHIFT 0 /*************************************************************************** *TPIT1_STATE2 - TPIT 1 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_STATE2 :: TPIT_TRACK_STATE2 [31:00] */ #define BCHP_XPT_RAVE_TPIT1_STATE2_TPIT_TRACK_STATE2_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT1_STATE2_TPIT_TRACK_STATE2_SHIFT 0 /*************************************************************************** *TPIT1_STATE2a - TPIT 1 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_STATE2a :: TPIT_TRACK_STATE2a [31:00] */ #define BCHP_XPT_RAVE_TPIT1_STATE2a_TPIT_TRACK_STATE2a_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT1_STATE2a_TPIT_TRACK_STATE2a_SHIFT 0 /*************************************************************************** *TPIT1_STATE2b - TPIT 1 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_STATE2b :: TPIT_TRACK_STATE2b [31:00] */ #define BCHP_XPT_RAVE_TPIT1_STATE2b_TPIT_TRACK_STATE2b_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT1_STATE2b_TPIT_TRACK_STATE2b_SHIFT 0 /*************************************************************************** *TPIT1_STATE2c - TPIT 1 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_STATE2c :: TPIT_TRACK_STATE2c [31:00] */ #define BCHP_XPT_RAVE_TPIT1_STATE2c_TPIT_TRACK_STATE2c_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT1_STATE2c_TPIT_TRACK_STATE2c_SHIFT 0 /*************************************************************************** *TPIT1_STATE2d - TPIT 1 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_STATE2d :: TPIT_TRACK_STATE2d [31:00] */ #define BCHP_XPT_RAVE_TPIT1_STATE2d_TPIT_TRACK_STATE2d_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT1_STATE2d_TPIT_TRACK_STATE2d_SHIFT 0 /*************************************************************************** *TPIT1_STATE3 - TPIT 1 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_STATE3 :: TPIT_TRACK_STATE3 [31:00] */ #define BCHP_XPT_RAVE_TPIT1_STATE3_TPIT_TRACK_STATE3_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT1_STATE3_TPIT_TRACK_STATE3_SHIFT 0 /*************************************************************************** *TPIT1_STATE4 - TPIT 1 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_STATE4 :: TPIT_CUR_PCR [31:00] */ #define BCHP_XPT_RAVE_TPIT1_STATE4_TPIT_CUR_PCR_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT1_STATE4_TPIT_CUR_PCR_SHIFT 0 /*************************************************************************** *TPIT1_STATE5 - TPIT 1 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT1_STATE5_TPIT_LAST_PACKET_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT1_STATE5_TPIT_LAST_PACKET_LO_SHIFT 0 /*************************************************************************** *TPIT1_STATE6 - TPIT 1 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT1_STATE6_TPIT_LAST_EVENT_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT1_STATE6_TPIT_LAST_EVENT_LO_SHIFT 0 /*************************************************************************** *TPIT1_STATE7 - TPIT 1 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_STATE7 :: reserved_for_eco0 [31:20] */ #define BCHP_XPT_RAVE_TPIT1_STATE7_reserved_for_eco0_MASK 0xfff00000 #define BCHP_XPT_RAVE_TPIT1_STATE7_reserved_for_eco0_SHIFT 20 /* XPT_RAVE :: TPIT1_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */ #define BCHP_XPT_RAVE_TPIT1_STATE7_TPIT_LAST_EVENT_HI_MASK 0x000ffc00 #define BCHP_XPT_RAVE_TPIT1_STATE7_TPIT_LAST_EVENT_HI_SHIFT 10 /* XPT_RAVE :: TPIT1_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */ #define BCHP_XPT_RAVE_TPIT1_STATE7_TPIT_LAST_PACKET_HI_MASK 0x000003ff #define BCHP_XPT_RAVE_TPIT1_STATE7_TPIT_LAST_PACKET_HI_SHIFT 0 /*************************************************************************** *TPIT1_STATE8 - TPIT 1 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_STATE8 :: TPIT_LAST_TICK_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT1_STATE8_TPIT_LAST_TICK_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT1_STATE8_TPIT_LAST_TICK_LO_SHIFT 0 /*************************************************************************** *TPIT1_STATE9 - TPIT 1 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT1_STATE9 :: reserved_for_eco0 [31:10] */ #define BCHP_XPT_RAVE_TPIT1_STATE9_reserved_for_eco0_MASK 0xfffffc00 #define BCHP_XPT_RAVE_TPIT1_STATE9_reserved_for_eco0_SHIFT 10 /* XPT_RAVE :: TPIT1_STATE9 :: TPIT_LAST_TICK_HI [09:00] */ #define BCHP_XPT_RAVE_TPIT1_STATE9_TPIT_LAST_TICK_HI_MASK 0x000003ff #define BCHP_XPT_RAVE_TPIT1_STATE9_TPIT_LAST_TICK_HI_SHIFT 0 /*************************************************************************** *TPIT2_CTRL1 - TPIT 2 Control Register 1 ***************************************************************************/ /* XPT_RAVE :: TPIT2_CTRL1 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_TPIT2_CTRL1_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_TPIT2_CTRL1_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: TPIT2_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */ #define BCHP_XPT_RAVE_TPIT2_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT2_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT 8 /* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */ #define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_TIME_TICK_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_TIME_TICK_EN_SHIFT 7 /* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */ #define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_SPAN_SECTION_EN_MASK 0x00000060 #define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT 5 /* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_PCR_MODE [04:04] */ #define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_PCR_MODE_MASK 0x00000010 #define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_PCR_MODE_SHIFT 4 /* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */ #define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_EVENT_IDLE_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT 3 /* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_EMM_TID_EN [02:02] */ #define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_EMM_TID_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_EMM_TID_EN_SHIFT 2 /* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */ #define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_RECORD_IDLE_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT 1 /* XPT_RAVE :: TPIT2_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */ #define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_FIRST_PACKET_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT2_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT 0 /*************************************************************************** *TPIT2_COR1 - TPIT 2 Corrupt Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_COR1 :: reserved_for_eco0 [31:24] */ #define BCHP_XPT_RAVE_TPIT2_COR1_reserved_for_eco0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT2_COR1_reserved_for_eco0_SHIFT 24 /* XPT_RAVE :: TPIT2_COR1 :: REC_CORRUPT_BYTE [23:16] */ #define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_BYTE_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_BYTE_SHIFT 16 /* XPT_RAVE :: TPIT2_COR1 :: REC_CORRUPT_START [15:08] */ #define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_START_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_START_SHIFT 8 /* XPT_RAVE :: TPIT2_COR1 :: REC_CORRUPT_END [07:00] */ #define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_END_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT2_COR1_REC_CORRUPT_END_SHIFT 0 /*************************************************************************** *TPIT2_TID - TPIT TID Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_TID :: reserved_for_eco0 [31:24] */ #define BCHP_XPT_RAVE_TPIT2_TID_reserved_for_eco0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT2_TID_reserved_for_eco0_SHIFT 24 /* XPT_RAVE :: TPIT2_TID :: ECM_TID_ODD [23:16] */ #define BCHP_XPT_RAVE_TPIT2_TID_ECM_TID_ODD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT2_TID_ECM_TID_ODD_SHIFT 16 /* XPT_RAVE :: TPIT2_TID :: ECM_TID_EVEN [15:08] */ #define BCHP_XPT_RAVE_TPIT2_TID_ECM_TID_EVEN_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT2_TID_ECM_TID_EVEN_SHIFT 8 /* XPT_RAVE :: TPIT2_TID :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_TPIT2_TID_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_TPIT2_TID_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: TPIT2_TID :: EMM_TID [03:00] */ #define BCHP_XPT_RAVE_TPIT2_TID_EMM_TID_MASK 0x0000000f #define BCHP_XPT_RAVE_TPIT2_TID_EMM_TID_SHIFT 0 /*************************************************************************** *TPIT2_TID2 - TPIT TID Register 2 ***************************************************************************/ /* XPT_RAVE :: TPIT2_TID2 :: ECM_TID_ODD3 [31:24] */ #define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_ODD3_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_ODD3_SHIFT 24 /* XPT_RAVE :: TPIT2_TID2 :: ECM_TID_EVEN3 [23:16] */ #define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_EVEN3_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_EVEN3_SHIFT 16 /* XPT_RAVE :: TPIT2_TID2 :: ECM_TID_ODD2 [15:08] */ #define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_ODD2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_ODD2_SHIFT 8 /* XPT_RAVE :: TPIT2_TID2 :: ECM_TID_EVEN2 [07:00] */ #define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_EVEN2_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT2_TID2_ECM_TID_EVEN2_SHIFT 0 /*************************************************************************** *TPIT2_STATE0 - TPIT 2 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_STATE0 :: TPIT_TRACK_STATE0 [31:00] */ #define BCHP_XPT_RAVE_TPIT2_STATE0_TPIT_TRACK_STATE0_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT2_STATE0_TPIT_TRACK_STATE0_SHIFT 0 /*************************************************************************** *TPIT2_STATE1 - TPIT 2 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_STATE1 :: TPIT_TRACK_STATE1 [31:00] */ #define BCHP_XPT_RAVE_TPIT2_STATE1_TPIT_TRACK_STATE1_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT2_STATE1_TPIT_TRACK_STATE1_SHIFT 0 /*************************************************************************** *TPIT2_STATE2 - TPIT 2 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_STATE2 :: TPIT_TRACK_STATE2 [31:00] */ #define BCHP_XPT_RAVE_TPIT2_STATE2_TPIT_TRACK_STATE2_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT2_STATE2_TPIT_TRACK_STATE2_SHIFT 0 /*************************************************************************** *TPIT2_STATE2a - TPIT 2 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_STATE2a :: TPIT_TRACK_STATE2a [31:00] */ #define BCHP_XPT_RAVE_TPIT2_STATE2a_TPIT_TRACK_STATE2a_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT2_STATE2a_TPIT_TRACK_STATE2a_SHIFT 0 /*************************************************************************** *TPIT2_STATE2b - TPIT 2 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_STATE2b :: TPIT_TRACK_STATE2b [31:00] */ #define BCHP_XPT_RAVE_TPIT2_STATE2b_TPIT_TRACK_STATE2b_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT2_STATE2b_TPIT_TRACK_STATE2b_SHIFT 0 /*************************************************************************** *TPIT2_STATE2c - TPIT 2 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_STATE2c :: TPIT_TRACK_STATE2c [31:00] */ #define BCHP_XPT_RAVE_TPIT2_STATE2c_TPIT_TRACK_STATE2c_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT2_STATE2c_TPIT_TRACK_STATE2c_SHIFT 0 /*************************************************************************** *TPIT2_STATE2d - TPIT 2 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_STATE2d :: TPIT_TRACK_STATE2d [31:00] */ #define BCHP_XPT_RAVE_TPIT2_STATE2d_TPIT_TRACK_STATE2d_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT2_STATE2d_TPIT_TRACK_STATE2d_SHIFT 0 /*************************************************************************** *TPIT2_STATE3 - TPIT 2 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_STATE3 :: TPIT_TRACK_STATE3 [31:00] */ #define BCHP_XPT_RAVE_TPIT2_STATE3_TPIT_TRACK_STATE3_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT2_STATE3_TPIT_TRACK_STATE3_SHIFT 0 /*************************************************************************** *TPIT2_STATE4 - TPIT 2 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_STATE4 :: TPIT_CUR_PCR [31:00] */ #define BCHP_XPT_RAVE_TPIT2_STATE4_TPIT_CUR_PCR_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT2_STATE4_TPIT_CUR_PCR_SHIFT 0 /*************************************************************************** *TPIT2_STATE5 - TPIT 2 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT2_STATE5_TPIT_LAST_PACKET_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT2_STATE5_TPIT_LAST_PACKET_LO_SHIFT 0 /*************************************************************************** *TPIT2_STATE6 - TPIT 2 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT2_STATE6_TPIT_LAST_EVENT_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT2_STATE6_TPIT_LAST_EVENT_LO_SHIFT 0 /*************************************************************************** *TPIT2_STATE7 - TPIT 2 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_STATE7 :: reserved_for_eco0 [31:20] */ #define BCHP_XPT_RAVE_TPIT2_STATE7_reserved_for_eco0_MASK 0xfff00000 #define BCHP_XPT_RAVE_TPIT2_STATE7_reserved_for_eco0_SHIFT 20 /* XPT_RAVE :: TPIT2_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */ #define BCHP_XPT_RAVE_TPIT2_STATE7_TPIT_LAST_EVENT_HI_MASK 0x000ffc00 #define BCHP_XPT_RAVE_TPIT2_STATE7_TPIT_LAST_EVENT_HI_SHIFT 10 /* XPT_RAVE :: TPIT2_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */ #define BCHP_XPT_RAVE_TPIT2_STATE7_TPIT_LAST_PACKET_HI_MASK 0x000003ff #define BCHP_XPT_RAVE_TPIT2_STATE7_TPIT_LAST_PACKET_HI_SHIFT 0 /*************************************************************************** *TPIT2_STATE8 - TPIT 2 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_STATE8 :: TPIT_LAST_TICK_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT2_STATE8_TPIT_LAST_TICK_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT2_STATE8_TPIT_LAST_TICK_LO_SHIFT 0 /*************************************************************************** *TPIT2_STATE9 - TPIT 2 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT2_STATE9 :: reserved_for_eco0 [31:10] */ #define BCHP_XPT_RAVE_TPIT2_STATE9_reserved_for_eco0_MASK 0xfffffc00 #define BCHP_XPT_RAVE_TPIT2_STATE9_reserved_for_eco0_SHIFT 10 /* XPT_RAVE :: TPIT2_STATE9 :: TPIT_LAST_TICK_HI [09:00] */ #define BCHP_XPT_RAVE_TPIT2_STATE9_TPIT_LAST_TICK_HI_MASK 0x000003ff #define BCHP_XPT_RAVE_TPIT2_STATE9_TPIT_LAST_TICK_HI_SHIFT 0 /*************************************************************************** *TPIT3_CTRL1 - TPIT 3 Control Register 1 ***************************************************************************/ /* XPT_RAVE :: TPIT3_CTRL1 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_TPIT3_CTRL1_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_TPIT3_CTRL1_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: TPIT3_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */ #define BCHP_XPT_RAVE_TPIT3_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT3_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT 8 /* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */ #define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_TIME_TICK_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_TIME_TICK_EN_SHIFT 7 /* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */ #define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_SPAN_SECTION_EN_MASK 0x00000060 #define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT 5 /* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_PCR_MODE [04:04] */ #define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_PCR_MODE_MASK 0x00000010 #define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_PCR_MODE_SHIFT 4 /* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */ #define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_EVENT_IDLE_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT 3 /* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_EMM_TID_EN [02:02] */ #define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_EMM_TID_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_EMM_TID_EN_SHIFT 2 /* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */ #define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_RECORD_IDLE_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT 1 /* XPT_RAVE :: TPIT3_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */ #define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_FIRST_PACKET_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT3_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT 0 /*************************************************************************** *TPIT3_COR1 - TPIT 3 Corrupt Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_COR1 :: reserved_for_eco0 [31:24] */ #define BCHP_XPT_RAVE_TPIT3_COR1_reserved_for_eco0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT3_COR1_reserved_for_eco0_SHIFT 24 /* XPT_RAVE :: TPIT3_COR1 :: REC_CORRUPT_BYTE [23:16] */ #define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_BYTE_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_BYTE_SHIFT 16 /* XPT_RAVE :: TPIT3_COR1 :: REC_CORRUPT_START [15:08] */ #define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_START_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_START_SHIFT 8 /* XPT_RAVE :: TPIT3_COR1 :: REC_CORRUPT_END [07:00] */ #define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_END_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT3_COR1_REC_CORRUPT_END_SHIFT 0 /*************************************************************************** *TPIT3_TID - TPIT TID Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_TID :: reserved_for_eco0 [31:24] */ #define BCHP_XPT_RAVE_TPIT3_TID_reserved_for_eco0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT3_TID_reserved_for_eco0_SHIFT 24 /* XPT_RAVE :: TPIT3_TID :: ECM_TID_ODD [23:16] */ #define BCHP_XPT_RAVE_TPIT3_TID_ECM_TID_ODD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT3_TID_ECM_TID_ODD_SHIFT 16 /* XPT_RAVE :: TPIT3_TID :: ECM_TID_EVEN [15:08] */ #define BCHP_XPT_RAVE_TPIT3_TID_ECM_TID_EVEN_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT3_TID_ECM_TID_EVEN_SHIFT 8 /* XPT_RAVE :: TPIT3_TID :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_TPIT3_TID_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_TPIT3_TID_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: TPIT3_TID :: EMM_TID [03:00] */ #define BCHP_XPT_RAVE_TPIT3_TID_EMM_TID_MASK 0x0000000f #define BCHP_XPT_RAVE_TPIT3_TID_EMM_TID_SHIFT 0 /*************************************************************************** *TPIT3_TID2 - TPIT TID Register 2 ***************************************************************************/ /* XPT_RAVE :: TPIT3_TID2 :: ECM_TID_ODD3 [31:24] */ #define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_ODD3_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_ODD3_SHIFT 24 /* XPT_RAVE :: TPIT3_TID2 :: ECM_TID_EVEN3 [23:16] */ #define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_EVEN3_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_EVEN3_SHIFT 16 /* XPT_RAVE :: TPIT3_TID2 :: ECM_TID_ODD2 [15:08] */ #define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_ODD2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_ODD2_SHIFT 8 /* XPT_RAVE :: TPIT3_TID2 :: ECM_TID_EVEN2 [07:00] */ #define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_EVEN2_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT3_TID2_ECM_TID_EVEN2_SHIFT 0 /*************************************************************************** *TPIT3_STATE0 - TPIT 3 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_STATE0 :: TPIT_TRACK_STATE0 [31:00] */ #define BCHP_XPT_RAVE_TPIT3_STATE0_TPIT_TRACK_STATE0_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT3_STATE0_TPIT_TRACK_STATE0_SHIFT 0 /*************************************************************************** *TPIT3_STATE1 - TPIT 3 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_STATE1 :: TPIT_TRACK_STATE1 [31:00] */ #define BCHP_XPT_RAVE_TPIT3_STATE1_TPIT_TRACK_STATE1_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT3_STATE1_TPIT_TRACK_STATE1_SHIFT 0 /*************************************************************************** *TPIT3_STATE2 - TPIT 3 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_STATE2 :: TPIT_TRACK_STATE2 [31:00] */ #define BCHP_XPT_RAVE_TPIT3_STATE2_TPIT_TRACK_STATE2_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT3_STATE2_TPIT_TRACK_STATE2_SHIFT 0 /*************************************************************************** *TPIT3_STATE2a - TPIT 3 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_STATE2a :: TPIT_TRACK_STATE2a [31:00] */ #define BCHP_XPT_RAVE_TPIT3_STATE2a_TPIT_TRACK_STATE2a_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT3_STATE2a_TPIT_TRACK_STATE2a_SHIFT 0 /*************************************************************************** *TPIT3_STATE2b - TPIT 3 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_STATE2b :: TPIT_TRACK_STATE2b [31:00] */ #define BCHP_XPT_RAVE_TPIT3_STATE2b_TPIT_TRACK_STATE2b_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT3_STATE2b_TPIT_TRACK_STATE2b_SHIFT 0 /*************************************************************************** *TPIT3_STATE2c - TPIT 3 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_STATE2c :: TPIT_TRACK_STATE2c [31:00] */ #define BCHP_XPT_RAVE_TPIT3_STATE2c_TPIT_TRACK_STATE2c_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT3_STATE2c_TPIT_TRACK_STATE2c_SHIFT 0 /*************************************************************************** *TPIT3_STATE2d - TPIT 3 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_STATE2d :: TPIT_TRACK_STATE2d [31:00] */ #define BCHP_XPT_RAVE_TPIT3_STATE2d_TPIT_TRACK_STATE2d_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT3_STATE2d_TPIT_TRACK_STATE2d_SHIFT 0 /*************************************************************************** *TPIT3_STATE3 - TPIT 3 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_STATE3 :: TPIT_TRACK_STATE3 [31:00] */ #define BCHP_XPT_RAVE_TPIT3_STATE3_TPIT_TRACK_STATE3_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT3_STATE3_TPIT_TRACK_STATE3_SHIFT 0 /*************************************************************************** *TPIT3_STATE4 - TPIT 3 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_STATE4 :: TPIT_CUR_PCR [31:00] */ #define BCHP_XPT_RAVE_TPIT3_STATE4_TPIT_CUR_PCR_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT3_STATE4_TPIT_CUR_PCR_SHIFT 0 /*************************************************************************** *TPIT3_STATE5 - TPIT 3 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT3_STATE5_TPIT_LAST_PACKET_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT3_STATE5_TPIT_LAST_PACKET_LO_SHIFT 0 /*************************************************************************** *TPIT3_STATE6 - TPIT 3 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT3_STATE6_TPIT_LAST_EVENT_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT3_STATE6_TPIT_LAST_EVENT_LO_SHIFT 0 /*************************************************************************** *TPIT3_STATE7 - TPIT 3 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_STATE7 :: reserved_for_eco0 [31:20] */ #define BCHP_XPT_RAVE_TPIT3_STATE7_reserved_for_eco0_MASK 0xfff00000 #define BCHP_XPT_RAVE_TPIT3_STATE7_reserved_for_eco0_SHIFT 20 /* XPT_RAVE :: TPIT3_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */ #define BCHP_XPT_RAVE_TPIT3_STATE7_TPIT_LAST_EVENT_HI_MASK 0x000ffc00 #define BCHP_XPT_RAVE_TPIT3_STATE7_TPIT_LAST_EVENT_HI_SHIFT 10 /* XPT_RAVE :: TPIT3_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */ #define BCHP_XPT_RAVE_TPIT3_STATE7_TPIT_LAST_PACKET_HI_MASK 0x000003ff #define BCHP_XPT_RAVE_TPIT3_STATE7_TPIT_LAST_PACKET_HI_SHIFT 0 /*************************************************************************** *TPIT3_STATE8 - TPIT 3 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_STATE8 :: TPIT_LAST_TICK_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT3_STATE8_TPIT_LAST_TICK_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT3_STATE8_TPIT_LAST_TICK_LO_SHIFT 0 /*************************************************************************** *TPIT3_STATE9 - TPIT 3 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT3_STATE9 :: reserved_for_eco0 [31:10] */ #define BCHP_XPT_RAVE_TPIT3_STATE9_reserved_for_eco0_MASK 0xfffffc00 #define BCHP_XPT_RAVE_TPIT3_STATE9_reserved_for_eco0_SHIFT 10 /* XPT_RAVE :: TPIT3_STATE9 :: TPIT_LAST_TICK_HI [09:00] */ #define BCHP_XPT_RAVE_TPIT3_STATE9_TPIT_LAST_TICK_HI_MASK 0x000003ff #define BCHP_XPT_RAVE_TPIT3_STATE9_TPIT_LAST_TICK_HI_SHIFT 0 /*************************************************************************** *TPIT4_CTRL1 - TPIT 4 Control Register 1 ***************************************************************************/ /* XPT_RAVE :: TPIT4_CTRL1 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_TPIT4_CTRL1_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_TPIT4_CTRL1_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: TPIT4_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */ #define BCHP_XPT_RAVE_TPIT4_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT4_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT 8 /* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */ #define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_TIME_TICK_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_TIME_TICK_EN_SHIFT 7 /* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */ #define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_SPAN_SECTION_EN_MASK 0x00000060 #define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT 5 /* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_PCR_MODE [04:04] */ #define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_PCR_MODE_MASK 0x00000010 #define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_PCR_MODE_SHIFT 4 /* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */ #define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_EVENT_IDLE_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT 3 /* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_EMM_TID_EN [02:02] */ #define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_EMM_TID_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_EMM_TID_EN_SHIFT 2 /* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */ #define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_RECORD_IDLE_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT 1 /* XPT_RAVE :: TPIT4_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */ #define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_FIRST_PACKET_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT4_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT 0 /*************************************************************************** *TPIT4_COR1 - TPIT 4 Corrupt Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_COR1 :: reserved_for_eco0 [31:24] */ #define BCHP_XPT_RAVE_TPIT4_COR1_reserved_for_eco0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT4_COR1_reserved_for_eco0_SHIFT 24 /* XPT_RAVE :: TPIT4_COR1 :: REC_CORRUPT_BYTE [23:16] */ #define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_BYTE_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_BYTE_SHIFT 16 /* XPT_RAVE :: TPIT4_COR1 :: REC_CORRUPT_START [15:08] */ #define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_START_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_START_SHIFT 8 /* XPT_RAVE :: TPIT4_COR1 :: REC_CORRUPT_END [07:00] */ #define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_END_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT4_COR1_REC_CORRUPT_END_SHIFT 0 /*************************************************************************** *TPIT4_TID - TPIT TID Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_TID :: reserved_for_eco0 [31:24] */ #define BCHP_XPT_RAVE_TPIT4_TID_reserved_for_eco0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT4_TID_reserved_for_eco0_SHIFT 24 /* XPT_RAVE :: TPIT4_TID :: ECM_TID_ODD [23:16] */ #define BCHP_XPT_RAVE_TPIT4_TID_ECM_TID_ODD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT4_TID_ECM_TID_ODD_SHIFT 16 /* XPT_RAVE :: TPIT4_TID :: ECM_TID_EVEN [15:08] */ #define BCHP_XPT_RAVE_TPIT4_TID_ECM_TID_EVEN_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT4_TID_ECM_TID_EVEN_SHIFT 8 /* XPT_RAVE :: TPIT4_TID :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_TPIT4_TID_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_TPIT4_TID_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: TPIT4_TID :: EMM_TID [03:00] */ #define BCHP_XPT_RAVE_TPIT4_TID_EMM_TID_MASK 0x0000000f #define BCHP_XPT_RAVE_TPIT4_TID_EMM_TID_SHIFT 0 /*************************************************************************** *TPIT4_TID2 - TPIT TID Register 2 ***************************************************************************/ /* XPT_RAVE :: TPIT4_TID2 :: ECM_TID_ODD3 [31:24] */ #define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_ODD3_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_ODD3_SHIFT 24 /* XPT_RAVE :: TPIT4_TID2 :: ECM_TID_EVEN3 [23:16] */ #define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_EVEN3_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_EVEN3_SHIFT 16 /* XPT_RAVE :: TPIT4_TID2 :: ECM_TID_ODD2 [15:08] */ #define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_ODD2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_ODD2_SHIFT 8 /* XPT_RAVE :: TPIT4_TID2 :: ECM_TID_EVEN2 [07:00] */ #define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_EVEN2_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT4_TID2_ECM_TID_EVEN2_SHIFT 0 /*************************************************************************** *TPIT4_STATE0 - TPIT 4 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_STATE0 :: TPIT_TRACK_STATE0 [31:00] */ #define BCHP_XPT_RAVE_TPIT4_STATE0_TPIT_TRACK_STATE0_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT4_STATE0_TPIT_TRACK_STATE0_SHIFT 0 /*************************************************************************** *TPIT4_STATE1 - TPIT 4 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_STATE1 :: TPIT_TRACK_STATE1 [31:00] */ #define BCHP_XPT_RAVE_TPIT4_STATE1_TPIT_TRACK_STATE1_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT4_STATE1_TPIT_TRACK_STATE1_SHIFT 0 /*************************************************************************** *TPIT4_STATE2 - TPIT 4 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_STATE2 :: TPIT_TRACK_STATE2 [31:00] */ #define BCHP_XPT_RAVE_TPIT4_STATE2_TPIT_TRACK_STATE2_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT4_STATE2_TPIT_TRACK_STATE2_SHIFT 0 /*************************************************************************** *TPIT4_STATE2a - TPIT 4 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_STATE2a :: TPIT_TRACK_STATE2a [31:00] */ #define BCHP_XPT_RAVE_TPIT4_STATE2a_TPIT_TRACK_STATE2a_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT4_STATE2a_TPIT_TRACK_STATE2a_SHIFT 0 /*************************************************************************** *TPIT4_STATE2b - TPIT 4 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_STATE2b :: TPIT_TRACK_STATE2b [31:00] */ #define BCHP_XPT_RAVE_TPIT4_STATE2b_TPIT_TRACK_STATE2b_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT4_STATE2b_TPIT_TRACK_STATE2b_SHIFT 0 /*************************************************************************** *TPIT4_STATE2c - TPIT 4 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_STATE2c :: TPIT_TRACK_STATE2c [31:00] */ #define BCHP_XPT_RAVE_TPIT4_STATE2c_TPIT_TRACK_STATE2c_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT4_STATE2c_TPIT_TRACK_STATE2c_SHIFT 0 /*************************************************************************** *TPIT4_STATE2d - TPIT 4 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_STATE2d :: TPIT_TRACK_STATE2d [31:00] */ #define BCHP_XPT_RAVE_TPIT4_STATE2d_TPIT_TRACK_STATE2d_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT4_STATE2d_TPIT_TRACK_STATE2d_SHIFT 0 /*************************************************************************** *TPIT4_STATE3 - TPIT 4 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_STATE3 :: TPIT_TRACK_STATE3 [31:00] */ #define BCHP_XPT_RAVE_TPIT4_STATE3_TPIT_TRACK_STATE3_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT4_STATE3_TPIT_TRACK_STATE3_SHIFT 0 /*************************************************************************** *TPIT4_STATE4 - TPIT 4 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_STATE4 :: TPIT_CUR_PCR [31:00] */ #define BCHP_XPT_RAVE_TPIT4_STATE4_TPIT_CUR_PCR_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT4_STATE4_TPIT_CUR_PCR_SHIFT 0 /*************************************************************************** *TPIT4_STATE5 - TPIT 4 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT4_STATE5_TPIT_LAST_PACKET_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT4_STATE5_TPIT_LAST_PACKET_LO_SHIFT 0 /*************************************************************************** *TPIT4_STATE6 - TPIT 4 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT4_STATE6_TPIT_LAST_EVENT_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT4_STATE6_TPIT_LAST_EVENT_LO_SHIFT 0 /*************************************************************************** *TPIT4_STATE7 - TPIT 4 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_STATE7 :: reserved_for_eco0 [31:20] */ #define BCHP_XPT_RAVE_TPIT4_STATE7_reserved_for_eco0_MASK 0xfff00000 #define BCHP_XPT_RAVE_TPIT4_STATE7_reserved_for_eco0_SHIFT 20 /* XPT_RAVE :: TPIT4_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */ #define BCHP_XPT_RAVE_TPIT4_STATE7_TPIT_LAST_EVENT_HI_MASK 0x000ffc00 #define BCHP_XPT_RAVE_TPIT4_STATE7_TPIT_LAST_EVENT_HI_SHIFT 10 /* XPT_RAVE :: TPIT4_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */ #define BCHP_XPT_RAVE_TPIT4_STATE7_TPIT_LAST_PACKET_HI_MASK 0x000003ff #define BCHP_XPT_RAVE_TPIT4_STATE7_TPIT_LAST_PACKET_HI_SHIFT 0 /*************************************************************************** *TPIT4_STATE8 - TPIT 4 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_STATE8 :: TPIT_LAST_TICK_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT4_STATE8_TPIT_LAST_TICK_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT4_STATE8_TPIT_LAST_TICK_LO_SHIFT 0 /*************************************************************************** *TPIT4_STATE9 - TPIT 4 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT4_STATE9 :: reserved_for_eco0 [31:10] */ #define BCHP_XPT_RAVE_TPIT4_STATE9_reserved_for_eco0_MASK 0xfffffc00 #define BCHP_XPT_RAVE_TPIT4_STATE9_reserved_for_eco0_SHIFT 10 /* XPT_RAVE :: TPIT4_STATE9 :: TPIT_LAST_TICK_HI [09:00] */ #define BCHP_XPT_RAVE_TPIT4_STATE9_TPIT_LAST_TICK_HI_MASK 0x000003ff #define BCHP_XPT_RAVE_TPIT4_STATE9_TPIT_LAST_TICK_HI_SHIFT 0 /*************************************************************************** *TPIT5_CTRL1 - TPIT 5 Control Register 1 ***************************************************************************/ /* XPT_RAVE :: TPIT5_CTRL1 :: reserved_for_eco0 [31:09] */ #define BCHP_XPT_RAVE_TPIT5_CTRL1_reserved_for_eco0_MASK 0xfffffe00 #define BCHP_XPT_RAVE_TPIT5_CTRL1_reserved_for_eco0_SHIFT 9 /* XPT_RAVE :: TPIT5_CTRL1 :: SC_CHANGE_ADAP_IGNORE [08:08] */ #define BCHP_XPT_RAVE_TPIT5_CTRL1_SC_CHANGE_ADAP_IGNORE_MASK 0x00000100 #define BCHP_XPT_RAVE_TPIT5_CTRL1_SC_CHANGE_ADAP_IGNORE_SHIFT 8 /* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_TIME_TICK_EN [07:07] */ #define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_TIME_TICK_EN_MASK 0x00000080 #define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_TIME_TICK_EN_SHIFT 7 /* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_SPAN_SECTION_EN [06:05] */ #define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_SPAN_SECTION_EN_MASK 0x00000060 #define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_SPAN_SECTION_EN_SHIFT 5 /* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_PCR_MODE [04:04] */ #define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_PCR_MODE_MASK 0x00000010 #define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_PCR_MODE_SHIFT 4 /* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_EVENT_IDLE_EN [03:03] */ #define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_EVENT_IDLE_EN_MASK 0x00000008 #define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_EVENT_IDLE_EN_SHIFT 3 /* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_EMM_TID_EN [02:02] */ #define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_EMM_TID_EN_MASK 0x00000004 #define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_EMM_TID_EN_SHIFT 2 /* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_RECORD_IDLE_EN [01:01] */ #define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_RECORD_IDLE_EN_MASK 0x00000002 #define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_RECORD_IDLE_EN_SHIFT 1 /* XPT_RAVE :: TPIT5_CTRL1 :: TPIT_FIRST_PACKET_EN [00:00] */ #define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_FIRST_PACKET_EN_MASK 0x00000001 #define BCHP_XPT_RAVE_TPIT5_CTRL1_TPIT_FIRST_PACKET_EN_SHIFT 0 /*************************************************************************** *TPIT5_COR1 - TPIT 5 Corrupt Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_COR1 :: reserved_for_eco0 [31:24] */ #define BCHP_XPT_RAVE_TPIT5_COR1_reserved_for_eco0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT5_COR1_reserved_for_eco0_SHIFT 24 /* XPT_RAVE :: TPIT5_COR1 :: REC_CORRUPT_BYTE [23:16] */ #define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_BYTE_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_BYTE_SHIFT 16 /* XPT_RAVE :: TPIT5_COR1 :: REC_CORRUPT_START [15:08] */ #define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_START_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_START_SHIFT 8 /* XPT_RAVE :: TPIT5_COR1 :: REC_CORRUPT_END [07:00] */ #define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_END_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT5_COR1_REC_CORRUPT_END_SHIFT 0 /*************************************************************************** *TPIT5_TID - TPIT TID Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_TID :: reserved_for_eco0 [31:24] */ #define BCHP_XPT_RAVE_TPIT5_TID_reserved_for_eco0_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT5_TID_reserved_for_eco0_SHIFT 24 /* XPT_RAVE :: TPIT5_TID :: ECM_TID_ODD [23:16] */ #define BCHP_XPT_RAVE_TPIT5_TID_ECM_TID_ODD_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT5_TID_ECM_TID_ODD_SHIFT 16 /* XPT_RAVE :: TPIT5_TID :: ECM_TID_EVEN [15:08] */ #define BCHP_XPT_RAVE_TPIT5_TID_ECM_TID_EVEN_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT5_TID_ECM_TID_EVEN_SHIFT 8 /* XPT_RAVE :: TPIT5_TID :: reserved_for_eco1 [07:04] */ #define BCHP_XPT_RAVE_TPIT5_TID_reserved_for_eco1_MASK 0x000000f0 #define BCHP_XPT_RAVE_TPIT5_TID_reserved_for_eco1_SHIFT 4 /* XPT_RAVE :: TPIT5_TID :: EMM_TID [03:00] */ #define BCHP_XPT_RAVE_TPIT5_TID_EMM_TID_MASK 0x0000000f #define BCHP_XPT_RAVE_TPIT5_TID_EMM_TID_SHIFT 0 /*************************************************************************** *TPIT5_TID2 - TPIT TID Register 2 ***************************************************************************/ /* XPT_RAVE :: TPIT5_TID2 :: ECM_TID_ODD3 [31:24] */ #define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_ODD3_MASK 0xff000000 #define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_ODD3_SHIFT 24 /* XPT_RAVE :: TPIT5_TID2 :: ECM_TID_EVEN3 [23:16] */ #define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_EVEN3_MASK 0x00ff0000 #define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_EVEN3_SHIFT 16 /* XPT_RAVE :: TPIT5_TID2 :: ECM_TID_ODD2 [15:08] */ #define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_ODD2_MASK 0x0000ff00 #define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_ODD2_SHIFT 8 /* XPT_RAVE :: TPIT5_TID2 :: ECM_TID_EVEN2 [07:00] */ #define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_EVEN2_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT5_TID2_ECM_TID_EVEN2_SHIFT 0 /*************************************************************************** *TPIT5_STATE0 - TPIT 5 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_STATE0 :: TPIT_TRACK_STATE0 [31:00] */ #define BCHP_XPT_RAVE_TPIT5_STATE0_TPIT_TRACK_STATE0_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT5_STATE0_TPIT_TRACK_STATE0_SHIFT 0 /*************************************************************************** *TPIT5_STATE1 - TPIT 5 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_STATE1 :: TPIT_TRACK_STATE1 [31:00] */ #define BCHP_XPT_RAVE_TPIT5_STATE1_TPIT_TRACK_STATE1_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT5_STATE1_TPIT_TRACK_STATE1_SHIFT 0 /*************************************************************************** *TPIT5_STATE2 - TPIT 5 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_STATE2 :: TPIT_TRACK_STATE2 [31:00] */ #define BCHP_XPT_RAVE_TPIT5_STATE2_TPIT_TRACK_STATE2_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT5_STATE2_TPIT_TRACK_STATE2_SHIFT 0 /*************************************************************************** *TPIT5_STATE2a - TPIT 5 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_STATE2a :: TPIT_TRACK_STATE2a [31:00] */ #define BCHP_XPT_RAVE_TPIT5_STATE2a_TPIT_TRACK_STATE2a_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT5_STATE2a_TPIT_TRACK_STATE2a_SHIFT 0 /*************************************************************************** *TPIT5_STATE2b - TPIT 5 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_STATE2b :: TPIT_TRACK_STATE2b [31:00] */ #define BCHP_XPT_RAVE_TPIT5_STATE2b_TPIT_TRACK_STATE2b_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT5_STATE2b_TPIT_TRACK_STATE2b_SHIFT 0 /*************************************************************************** *TPIT5_STATE2c - TPIT 5 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_STATE2c :: TPIT_TRACK_STATE2c [31:00] */ #define BCHP_XPT_RAVE_TPIT5_STATE2c_TPIT_TRACK_STATE2c_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT5_STATE2c_TPIT_TRACK_STATE2c_SHIFT 0 /*************************************************************************** *TPIT5_STATE2d - TPIT 5 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_STATE2d :: TPIT_TRACK_STATE2d [31:00] */ #define BCHP_XPT_RAVE_TPIT5_STATE2d_TPIT_TRACK_STATE2d_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT5_STATE2d_TPIT_TRACK_STATE2d_SHIFT 0 /*************************************************************************** *TPIT5_STATE3 - TPIT 5 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_STATE3 :: TPIT_TRACK_STATE3 [31:00] */ #define BCHP_XPT_RAVE_TPIT5_STATE3_TPIT_TRACK_STATE3_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT5_STATE3_TPIT_TRACK_STATE3_SHIFT 0 /*************************************************************************** *TPIT5_STATE4 - TPIT 5 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_STATE4 :: TPIT_CUR_PCR [31:00] */ #define BCHP_XPT_RAVE_TPIT5_STATE4_TPIT_CUR_PCR_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT5_STATE4_TPIT_CUR_PCR_SHIFT 0 /*************************************************************************** *TPIT5_STATE5 - TPIT 5 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_STATE5 :: TPIT_LAST_PACKET_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT5_STATE5_TPIT_LAST_PACKET_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT5_STATE5_TPIT_LAST_PACKET_LO_SHIFT 0 /*************************************************************************** *TPIT5_STATE6 - TPIT 5 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_STATE6 :: TPIT_LAST_EVENT_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT5_STATE6_TPIT_LAST_EVENT_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT5_STATE6_TPIT_LAST_EVENT_LO_SHIFT 0 /*************************************************************************** *TPIT5_STATE7 - TPIT 5 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_STATE7 :: reserved_for_eco0 [31:20] */ #define BCHP_XPT_RAVE_TPIT5_STATE7_reserved_for_eco0_MASK 0xfff00000 #define BCHP_XPT_RAVE_TPIT5_STATE7_reserved_for_eco0_SHIFT 20 /* XPT_RAVE :: TPIT5_STATE7 :: TPIT_LAST_EVENT_HI [19:10] */ #define BCHP_XPT_RAVE_TPIT5_STATE7_TPIT_LAST_EVENT_HI_MASK 0x000ffc00 #define BCHP_XPT_RAVE_TPIT5_STATE7_TPIT_LAST_EVENT_HI_SHIFT 10 /* XPT_RAVE :: TPIT5_STATE7 :: TPIT_LAST_PACKET_HI [09:00] */ #define BCHP_XPT_RAVE_TPIT5_STATE7_TPIT_LAST_PACKET_HI_MASK 0x000003ff #define BCHP_XPT_RAVE_TPIT5_STATE7_TPIT_LAST_PACKET_HI_SHIFT 0 /*************************************************************************** *TPIT5_STATE8 - TPIT 5 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_STATE8 :: TPIT_LAST_TICK_LO [31:00] */ #define BCHP_XPT_RAVE_TPIT5_STATE8_TPIT_LAST_TICK_LO_MASK 0xffffffff #define BCHP_XPT_RAVE_TPIT5_STATE8_TPIT_LAST_TICK_LO_SHIFT 0 /*************************************************************************** *TPIT5_STATE9 - TPIT 5 State Register ***************************************************************************/ /* XPT_RAVE :: TPIT5_STATE9 :: reserved_for_eco0 [31:10] */ #define BCHP_XPT_RAVE_TPIT5_STATE9_reserved_for_eco0_MASK 0xfffffc00 #define BCHP_XPT_RAVE_TPIT5_STATE9_reserved_for_eco0_SHIFT 10 /* XPT_RAVE :: TPIT5_STATE9 :: TPIT_LAST_TICK_HI [09:00] */ #define BCHP_XPT_RAVE_TPIT5_STATE9_TPIT_LAST_TICK_HI_MASK 0x000003ff #define BCHP_XPT_RAVE_TPIT5_STATE9_TPIT_LAST_TICK_HI_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT0 - TPIT State Register for Context 0 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT0 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT0 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT0_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT1 - TPIT State Register for Context 1 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT1 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT1 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT1_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT2 - TPIT State Register for Context 2 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT2 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT2 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT2_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT3 - TPIT State Register for Context 3 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT3 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT3 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT3_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT4 - TPIT State Register for Context 4 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT4 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT4 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT4_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT5 - TPIT State Register for Context 5 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT5 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT5 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT5_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT6 - TPIT State Register for Context 6 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT6 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT6 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT6_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT7 - TPIT State Register for Context 7 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT7 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT7 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT7_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT8 - TPIT State Register for Context 8 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT8 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT8 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT8_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT9 - TPIT State Register for Context 9 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT9 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT9 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT9_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT10 - TPIT State Register for Context 10 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT10 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT10 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT10_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT11 - TPIT State Register for Context 11 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT11 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT11 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT11_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT12 - TPIT State Register for Context 12 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT12 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT12 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT12_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT13 - TPIT State Register for Context 13 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT13 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT13 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT13_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT14 - TPIT State Register for Context 14 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT14 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT14 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT14_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT15 - TPIT State Register for Context 15 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT15 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT15 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT15_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT16 - TPIT State Register for Context 16 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT16 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT16 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT16_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT17 - TPIT State Register for Context 17 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT17 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT17 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT17_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT18 - TPIT State Register for Context 18 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT18 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT18 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT18_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT19 - TPIT State Register for Context 19 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT19 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT19 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT19_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT20 - TPIT State Register for Context 20 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT20 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT20 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT20_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT21 - TPIT State Register for Context 21 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT21 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT21 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT21_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT22 - TPIT State Register for Context 22 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT22 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT22 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT22_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 /*************************************************************************** *TPIT_STATE_CONTEXT23 - TPIT State Register for Context 23 ***************************************************************************/ /* XPT_RAVE :: TPIT_STATE_CONTEXT23 :: reserved0 [31:08] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23_reserved0_MASK 0xffffff00 #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23_reserved0_SHIFT 8 /* XPT_RAVE :: TPIT_STATE_CONTEXT23 :: TPIT_CONTEXT_SPECIFIC_STATE [07:00] */ #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23_TPIT_CONTEXT_SPECIFIC_STATE_MASK 0x000000ff #define BCHP_XPT_RAVE_TPIT_STATE_CONTEXT23_TPIT_CONTEXT_SPECIFIC_STATE_SHIFT 0 #endif /* #ifndef BCHP_XPT_RAVE_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016100000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuregs_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000007042411610313111030770 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_cpuregs_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:02p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:23 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuregs_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:02p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_CPUREGS_0_H__ #define BCHP_DECODE_CPUREGS_0_H__ /*************************************************************************** *DECODE_CPUREGS_0 - Inner Loop CPU Registers 0 ***************************************************************************/ #define BCHP_DECODE_CPUREGS_0_REG_HST2CPU_MBX 0x00800f00 /* Host 2 CPU mailbox register */ #define BCHP_DECODE_CPUREGS_0_REG_CPU2HST_MBX 0x00800f04 /* CPU to Host mailbox register */ #define BCHP_DECODE_CPUREGS_0_REG_MBX_STAT 0x00800f08 /* Mailbox status flags */ #define BCHP_DECODE_CPUREGS_0_REG_INST_BASE 0x00800f0c /* Instruction base address register */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA 0x00800f10 /* CPU interrupt enable */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT 0x00800f14 /* CPU interrupt status */ #define BCHP_DECODE_CPUREGS_0_REG_HST2CPU_STAT 0x00800f18 /* Host to CPU status register */ #define BCHP_DECODE_CPUREGS_0_REG_CPU2HST_STAT 0x00800f1c /* CPU to Host status register */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET 0x00800f20 /* CPU interrupt set register */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR 0x00800f24 /* CPU interrupt clear register */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_ICACHE_MISS 0x00800f28 /* Instruction cache miss counter */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK 0x00800f2c /* CPU interrupt mask register */ #define BCHP_DECODE_CPUREGS_0_REG_END_OF_CODE 0x00800f34 /* End of code register */ #define BCHP_DECODE_CPUREGS_0_REG_GLOBAL_IO_BASE 0x00800f38 /* Global IO base register */ #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_WR 0x00800f3c /* CPU debug trace fifo write */ #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_RD 0x00800f40 /* CPU debug trace fifo read */ #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL 0x00800f44 /* CPU debug trace fifo control */ #define BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR 0x00800f4c /* Watchdog timer register */ #define BCHP_DECODE_CPUREGS_0_REG_SDRAM_STATUS 0x00800f50 /* SDRAM Status register */ #define BCHP_DECODE_CPUREGS_0_REG_CPUREGS_END 0x00800f7c /* Dummy end */ /*************************************************************************** *REG_HST2CPU_MBX - Host 2 CPU mailbox register ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_HST2CPU_MBX :: Value [31:00] */ #define BCHP_DECODE_CPUREGS_0_REG_HST2CPU_MBX_Value_MASK 0xffffffff #define BCHP_DECODE_CPUREGS_0_REG_HST2CPU_MBX_Value_SHIFT 0 /*************************************************************************** *REG_CPU2HST_MBX - CPU to Host mailbox register ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_CPU2HST_MBX :: Value [31:00] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU2HST_MBX_Value_MASK 0xffffffff #define BCHP_DECODE_CPUREGS_0_REG_CPU2HST_MBX_Value_SHIFT 0 /*************************************************************************** *REG_MBX_STAT - Mailbox status flags ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_MBX_STAT :: reserved0 [31:02] */ #define BCHP_DECODE_CPUREGS_0_REG_MBX_STAT_reserved0_MASK 0xfffffffc #define BCHP_DECODE_CPUREGS_0_REG_MBX_STAT_reserved0_SHIFT 2 /* DECODE_CPUREGS_0 :: REG_MBX_STAT :: C2H [01:01] */ #define BCHP_DECODE_CPUREGS_0_REG_MBX_STAT_C2H_MASK 0x00000002 #define BCHP_DECODE_CPUREGS_0_REG_MBX_STAT_C2H_SHIFT 1 /* DECODE_CPUREGS_0 :: REG_MBX_STAT :: H2C [00:00] */ #define BCHP_DECODE_CPUREGS_0_REG_MBX_STAT_H2C_MASK 0x00000001 #define BCHP_DECODE_CPUREGS_0_REG_MBX_STAT_H2C_SHIFT 0 /*************************************************************************** *REG_INST_BASE - Instruction base address register ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_INST_BASE :: InstBase [31:10] */ #define BCHP_DECODE_CPUREGS_0_REG_INST_BASE_InstBase_MASK 0xfffffc00 #define BCHP_DECODE_CPUREGS_0_REG_INST_BASE_InstBase_SHIFT 10 /* DECODE_CPUREGS_0 :: REG_INST_BASE :: reserved0 [09:00] */ #define BCHP_DECODE_CPUREGS_0_REG_INST_BASE_reserved0_MASK 0x000003ff #define BCHP_DECODE_CPUREGS_0_REG_INST_BASE_reserved0_SHIFT 0 /*************************************************************************** *REG_CPU_INT_ENA - CPU interrupt enable ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: MBx [31:31] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_MBx_MASK 0x80000000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_MBx_SHIFT 31 /* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: reserved_for_eco0 [30:11] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_reserved_for_eco0_MASK 0x7ffff800 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_reserved_for_eco0_SHIFT 11 /* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: Watchdog [10:10] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_Watchdog_MASK 0x00000400 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_Watchdog_SHIFT 10 /* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: CAB [09:09] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_CAB_MASK 0x00000200 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_CAB_SHIFT 9 /* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: SI [08:08] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_SI_MASK 0x00000100 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_SI_SHIFT 8 /* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: reserved_for_eco1 [07:02] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_reserved_for_eco1_MASK 0x000000fc #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_reserved_for_eco1_SHIFT 2 /* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: RB [01:01] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_RB_MASK 0x00000002 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_RB_SHIFT 1 /* DECODE_CPUREGS_0 :: REG_CPU_INT_ENA :: SD [00:00] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_SD_MASK 0x00000001 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_ENA_SD_SHIFT 0 /*************************************************************************** *REG_CPU_INT_STAT - CPU interrupt status ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: MBx [31:31] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_MBx_MASK 0x80000000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_MBx_SHIFT 31 /* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: reserved0 [30:11] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_reserved0_MASK 0x7ffff800 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_reserved0_SHIFT 11 /* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: Watchdog [10:10] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_Watchdog_MASK 0x00000400 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_Watchdog_SHIFT 10 /* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: CAB [09:09] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_CAB_MASK 0x00000200 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_CAB_SHIFT 9 /* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: SI [08:08] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_SI_MASK 0x00000100 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_SI_SHIFT 8 /* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: reserved1 [07:02] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_reserved1_MASK 0x000000fc #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_reserved1_SHIFT 2 /* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: RB [01:01] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_RB_MASK 0x00000002 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_RB_SHIFT 1 /* DECODE_CPUREGS_0 :: REG_CPU_INT_STAT :: SD [00:00] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_SD_MASK 0x00000001 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INT_STAT_SD_SHIFT 0 /*************************************************************************** *REG_HST2CPU_STAT - Host to CPU status register ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_HST2CPU_STAT :: Value [31:00] */ #define BCHP_DECODE_CPUREGS_0_REG_HST2CPU_STAT_Value_MASK 0xffffffff #define BCHP_DECODE_CPUREGS_0_REG_HST2CPU_STAT_Value_SHIFT 0 /*************************************************************************** *REG_CPU2HST_STAT - CPU to Host status register ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_CPU2HST_STAT :: Value [31:00] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU2HST_STAT_Value_MASK 0xffffffff #define BCHP_DECODE_CPUREGS_0_REG_CPU2HST_STAT_Value_SHIFT 0 /*************************************************************************** *REG_CPU_INTGEN_SET - CPU interrupt set register ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: reserved0 [31:16] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_reserved0_MASK 0xffff0000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_reserved0_SHIFT 16 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_15 [15:15] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_15_MASK 0x00008000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_15_SHIFT 15 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_14 [14:14] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_14_MASK 0x00004000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_14_SHIFT 14 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_13 [13:13] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_13_MASK 0x00002000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_13_SHIFT 13 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_12 [12:12] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_12_MASK 0x00001000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_12_SHIFT 12 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_11 [11:11] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_11_MASK 0x00000800 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_11_SHIFT 11 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_10 [10:10] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_10_MASK 0x00000400 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_10_SHIFT 10 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_9 [09:09] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_9_MASK 0x00000200 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_9_SHIFT 9 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_8 [08:08] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_8_MASK 0x00000100 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_8_SHIFT 8 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_7 [07:07] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_7_MASK 0x00000080 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_7_SHIFT 7 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_6 [06:06] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_6_MASK 0x00000040 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_6_SHIFT 6 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_5 [05:05] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_5_MASK 0x00000020 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_5_SHIFT 5 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_4 [04:04] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_4_MASK 0x00000010 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_4_SHIFT 4 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_3 [03:03] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_3_MASK 0x00000008 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_3_SHIFT 3 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_2 [02:02] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_2_MASK 0x00000004 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_2_SHIFT 2 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_1 [01:01] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_1_MASK 0x00000002 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_1_SHIFT 1 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_SET :: Int_0 [00:00] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_0_MASK 0x00000001 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_SET_Int_0_SHIFT 0 /*************************************************************************** *REG_CPU_INTGEN_CLR - CPU interrupt clear register ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: CPU_2_Hst_MBx [31:31] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_CPU_2_Hst_MBx_MASK 0x80000000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_CPU_2_Hst_MBx_SHIFT 31 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Watchdog_Timer [30:30] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Watchdog_Timer_MASK 0x40000000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Watchdog_Timer_SHIFT 30 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: reserved0 [29:16] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_reserved0_MASK 0x3fff0000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_reserved0_SHIFT 16 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_15 [15:15] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_15_MASK 0x00008000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_15_SHIFT 15 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_14 [14:14] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_14_MASK 0x00004000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_14_SHIFT 14 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_13 [13:13] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_13_MASK 0x00002000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_13_SHIFT 13 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_12 [12:12] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_12_MASK 0x00001000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_12_SHIFT 12 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_11 [11:11] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_11_MASK 0x00000800 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_11_SHIFT 11 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_10 [10:10] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_10_MASK 0x00000400 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_10_SHIFT 10 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_9 [09:09] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_9_MASK 0x00000200 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_9_SHIFT 9 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_8 [08:08] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_8_MASK 0x00000100 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_8_SHIFT 8 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_7 [07:07] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_7_MASK 0x00000080 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_7_SHIFT 7 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_6 [06:06] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_6_MASK 0x00000040 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_6_SHIFT 6 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_5 [05:05] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_5_MASK 0x00000020 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_5_SHIFT 5 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_4 [04:04] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_4_MASK 0x00000010 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_4_SHIFT 4 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_3 [03:03] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_3_MASK 0x00000008 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_3_SHIFT 3 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_2 [02:02] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_2_MASK 0x00000004 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_2_SHIFT 2 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_1 [01:01] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_1_MASK 0x00000002 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_1_SHIFT 1 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_CLR :: Int_0 [00:00] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_0_MASK 0x00000001 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_CLR_Int_0_SHIFT 0 /*************************************************************************** *REG_CPU_ICACHE_MISS - Instruction cache miss counter ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_CPU_ICACHE_MISS :: Count [31:00] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_ICACHE_MISS_Count_MASK 0xffffffff #define BCHP_DECODE_CPUREGS_0_REG_CPU_ICACHE_MISS_Count_SHIFT 0 /*************************************************************************** *REG_CPU_INTGEN_MASK - CPU interrupt mask register ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: CPU_2_Hst_MBx [31:31] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_CPU_2_Hst_MBx_MASK 0x80000000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_CPU_2_Hst_MBx_SHIFT 31 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Watchdog_Timer [30:30] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Watchdog_Timer_MASK 0x40000000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Watchdog_Timer_SHIFT 30 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: reserved0 [29:16] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_reserved0_MASK 0x3fff0000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_reserved0_SHIFT 16 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_15 [15:15] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_15_MASK 0x00008000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_15_SHIFT 15 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_14 [14:14] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_14_MASK 0x00004000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_14_SHIFT 14 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_13 [13:13] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_13_MASK 0x00002000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_13_SHIFT 13 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_12 [12:12] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_12_MASK 0x00001000 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_12_SHIFT 12 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_11 [11:11] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_11_MASK 0x00000800 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_11_SHIFT 11 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_10 [10:10] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_10_MASK 0x00000400 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_10_SHIFT 10 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_9 [09:09] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_9_MASK 0x00000200 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_9_SHIFT 9 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_8 [08:08] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_8_MASK 0x00000100 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_8_SHIFT 8 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_7 [07:07] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_7_MASK 0x00000080 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_7_SHIFT 7 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_6 [06:06] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_6_MASK 0x00000040 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_6_SHIFT 6 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_5 [05:05] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_5_MASK 0x00000020 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_5_SHIFT 5 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_4 [04:04] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_4_MASK 0x00000010 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_4_SHIFT 4 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_3 [03:03] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_3_MASK 0x00000008 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_3_SHIFT 3 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_2 [02:02] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_2_MASK 0x00000004 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_2_SHIFT 2 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_1 [01:01] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_1_MASK 0x00000002 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_1_SHIFT 1 /* DECODE_CPUREGS_0 :: REG_CPU_INTGEN_MASK :: Int_0 [00:00] */ #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_0_MASK 0x00000001 #define BCHP_DECODE_CPUREGS_0_REG_CPU_INTGEN_MASK_Int_0_SHIFT 0 /*************************************************************************** *REG_END_OF_CODE - End of code register ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_END_OF_CODE :: EndOfCode [31:10] */ #define BCHP_DECODE_CPUREGS_0_REG_END_OF_CODE_EndOfCode_MASK 0xfffffc00 #define BCHP_DECODE_CPUREGS_0_REG_END_OF_CODE_EndOfCode_SHIFT 10 /* DECODE_CPUREGS_0 :: REG_END_OF_CODE :: reserved0 [09:00] */ #define BCHP_DECODE_CPUREGS_0_REG_END_OF_CODE_reserved0_MASK 0x000003ff #define BCHP_DECODE_CPUREGS_0_REG_END_OF_CODE_reserved0_SHIFT 0 /*************************************************************************** *REG_GLOBAL_IO_BASE - Global IO base register ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_GLOBAL_IO_BASE :: GlobalIOBase [31:10] */ #define BCHP_DECODE_CPUREGS_0_REG_GLOBAL_IO_BASE_GlobalIOBase_MASK 0xfffffc00 #define BCHP_DECODE_CPUREGS_0_REG_GLOBAL_IO_BASE_GlobalIOBase_SHIFT 10 /* DECODE_CPUREGS_0 :: REG_GLOBAL_IO_BASE :: reserved0 [09:00] */ #define BCHP_DECODE_CPUREGS_0_REG_GLOBAL_IO_BASE_reserved0_MASK 0x000003ff #define BCHP_DECODE_CPUREGS_0_REG_GLOBAL_IO_BASE_reserved0_SHIFT 0 /*************************************************************************** *REG_DEBUG_TRACE_FIFO_WR - CPU debug trace fifo write ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_WR :: reserved0 [31:08] */ #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_WR_reserved0_MASK 0xffffff00 #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_WR_reserved0_SHIFT 8 /* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_WR :: Value [07:00] */ #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_WR_Value_MASK 0x000000ff #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_WR_Value_SHIFT 0 /*************************************************************************** *REG_DEBUG_TRACE_FIFO_RD - CPU debug trace fifo read ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_RD :: reserved0 [31:08] */ #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_RD_reserved0_MASK 0xffffff00 #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_RD_reserved0_SHIFT 8 /* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_RD :: Value [07:00] */ #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_RD_Value_MASK 0x000000ff #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_RD_Value_SHIFT 0 /*************************************************************************** *REG_DEBUG_TRACE_FIFO_CTL - CPU debug trace fifo control ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_CTL :: reserved0 [31:03] */ #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_reserved0_MASK 0xfffffff8 #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_reserved0_SHIFT 3 /* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_CTL :: Freeze [02:02] */ #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_Freeze_MASK 0x00000004 #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_Freeze_SHIFT 2 /* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_CTL :: Start_read [01:01] */ #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_Start_read_MASK 0x00000002 #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_Start_read_SHIFT 1 /* DECODE_CPUREGS_0 :: REG_DEBUG_TRACE_FIFO_CTL :: Clear [00:00] */ #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_Clear_MASK 0x00000001 #define BCHP_DECODE_CPUREGS_0_REG_DEBUG_TRACE_FIFO_CTL_Clear_SHIFT 0 /*************************************************************************** *REG_WATCHDOG_TMR - Watchdog timer register ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_WATCHDOG_TMR :: Value [31:00] */ #define BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR_Value_MASK 0xffffffff #define BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR_Value_SHIFT 0 /*************************************************************************** *REG_SDRAM_STATUS - SDRAM Status register ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_SDRAM_STATUS :: reserved0 [31:02] */ #define BCHP_DECODE_CPUREGS_0_REG_SDRAM_STATUS_reserved0_MASK 0xfffffffc #define BCHP_DECODE_CPUREGS_0_REG_SDRAM_STATUS_reserved0_SHIFT 2 /* DECODE_CPUREGS_0 :: REG_SDRAM_STATUS :: IsWrite [01:01] */ #define BCHP_DECODE_CPUREGS_0_REG_SDRAM_STATUS_IsWrite_MASK 0x00000002 #define BCHP_DECODE_CPUREGS_0_REG_SDRAM_STATUS_IsWrite_SHIFT 1 /* DECODE_CPUREGS_0 :: REG_SDRAM_STATUS :: Busy [00:00] */ #define BCHP_DECODE_CPUREGS_0_REG_SDRAM_STATUS_Busy_MASK 0x00000001 #define BCHP_DECODE_CPUREGS_0_REG_SDRAM_STATUS_Busy_SHIFT 0 /*************************************************************************** *REG_CPUREGS_END - Dummy end ***************************************************************************/ /* DECODE_CPUREGS_0 :: REG_CPUREGS_END :: reserved0 [31:00] */ #define BCHP_DECODE_CPUREGS_0_REG_CPUREGS_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_CPUREGS_0_REG_CPUREGS_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_CPUREGS_0_H__ */ /* End of File */ crystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_irq0.h0000644000175000017500000003002511610313111030637 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_irq0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:09p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:47 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_irq0.h $ * * Hydra_Software_Devel/1 7/17/09 8:09p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_IRQ0_H__ #define BCHP_IRQ0_H__ /*************************************************************************** *IRQ0 - Level 2 CPU Interrupt Enable/Status ***************************************************************************/ #define BCHP_IRQ0_IRQEN 0x00406080 /* Interrupt Enable */ #define BCHP_IRQ0_IRQSTAT 0x00406084 /* Interrupt Status */ /*************************************************************************** *IRQEN - Interrupt Enable ***************************************************************************/ /* IRQ0 :: IRQEN :: reserved_for_eco0 [31:29] */ #define BCHP_IRQ0_IRQEN_reserved_for_eco0_MASK 0xe0000000 #define BCHP_IRQ0_IRQEN_reserved_for_eco0_SHIFT 29 /* IRQ0 :: IRQEN :: iice_irqen [28:28] */ #define BCHP_IRQ0_IRQEN_iice_irqen_MASK 0x10000000 #define BCHP_IRQ0_IRQEN_iice_irqen_SHIFT 28 /* IRQ0 :: IRQEN :: iicd_irqen [27:27] */ #define BCHP_IRQ0_IRQEN_iicd_irqen_MASK 0x08000000 #define BCHP_IRQ0_IRQEN_iicd_irqen_SHIFT 27 /* IRQ0 :: IRQEN :: iicc_irqen [26:26] */ #define BCHP_IRQ0_IRQEN_iicc_irqen_MASK 0x04000000 #define BCHP_IRQ0_IRQEN_iicc_irqen_SHIFT 26 /* IRQ0 :: IRQEN :: iicb_irqen [25:25] */ #define BCHP_IRQ0_IRQEN_iicb_irqen_MASK 0x02000000 #define BCHP_IRQ0_IRQEN_iicb_irqen_SHIFT 25 /* IRQ0 :: IRQEN :: iica_irqen [24:24] */ #define BCHP_IRQ0_IRQEN_iica_irqen_MASK 0x01000000 #define BCHP_IRQ0_IRQEN_iica_irqen_SHIFT 24 /* IRQ0 :: IRQEN :: reserved_for_eco1 [23:21] */ #define BCHP_IRQ0_IRQEN_reserved_for_eco1_MASK 0x00e00000 #define BCHP_IRQ0_IRQEN_reserved_for_eco1_SHIFT 21 /* IRQ0 :: IRQEN :: spi_irqen [20:20] */ #define BCHP_IRQ0_IRQEN_spi_irqen_MASK 0x00100000 #define BCHP_IRQ0_IRQEN_spi_irqen_SHIFT 20 /* IRQ0 :: IRQEN :: uartd_irqen [19:19] */ #define BCHP_IRQ0_IRQEN_uartd_irqen_MASK 0x00080000 #define BCHP_IRQ0_IRQEN_uartd_irqen_SHIFT 19 /* IRQ0 :: IRQEN :: uartc_irqen [18:18] */ #define BCHP_IRQ0_IRQEN_uartc_irqen_MASK 0x00040000 #define BCHP_IRQ0_IRQEN_uartc_irqen_SHIFT 18 /* IRQ0 :: IRQEN :: uartb_irqen [17:17] */ #define BCHP_IRQ0_IRQEN_uartb_irqen_MASK 0x00020000 #define BCHP_IRQ0_IRQEN_uartb_irqen_SHIFT 17 /* IRQ0 :: IRQEN :: uarta_irqen [16:16] */ #define BCHP_IRQ0_IRQEN_uarta_irqen_MASK 0x00010000 #define BCHP_IRQ0_IRQEN_uarta_irqen_SHIFT 16 /* IRQ0 :: IRQEN :: reserved_for_eco2 [15:12] */ #define BCHP_IRQ0_IRQEN_reserved_for_eco2_MASK 0x0000f000 #define BCHP_IRQ0_IRQEN_reserved_for_eco2_SHIFT 12 /* IRQ0 :: IRQEN :: ud_irqen [11:11] */ #define BCHP_IRQ0_IRQEN_ud_irqen_MASK 0x00000800 #define BCHP_IRQ0_IRQEN_ud_irqen_SHIFT 11 /* IRQ0 :: IRQEN :: reserved_for_eco3 [10:10] */ #define BCHP_IRQ0_IRQEN_reserved_for_eco3_MASK 0x00000400 #define BCHP_IRQ0_IRQEN_reserved_for_eco3_SHIFT 10 /* IRQ0 :: IRQEN :: uc_irqen [09:09] */ #define BCHP_IRQ0_IRQEN_uc_irqen_MASK 0x00000200 #define BCHP_IRQ0_IRQEN_uc_irqen_SHIFT 9 /* IRQ0 :: IRQEN :: reserved_for_eco4 [08:08] */ #define BCHP_IRQ0_IRQEN_reserved_for_eco4_MASK 0x00000100 #define BCHP_IRQ0_IRQEN_reserved_for_eco4_SHIFT 8 /* IRQ0 :: IRQEN :: icap_irqen [07:07] */ #define BCHP_IRQ0_IRQEN_icap_irqen_MASK 0x00000080 #define BCHP_IRQ0_IRQEN_icap_irqen_SHIFT 7 /* IRQ0 :: IRQEN :: gio_irqen [06:06] */ #define BCHP_IRQ0_IRQEN_gio_irqen_MASK 0x00000040 #define BCHP_IRQ0_IRQEN_gio_irqen_SHIFT 6 /* IRQ0 :: IRQEN :: reserved_for_eco5 [05:05] */ #define BCHP_IRQ0_IRQEN_reserved_for_eco5_MASK 0x00000020 #define BCHP_IRQ0_IRQEN_reserved_for_eco5_SHIFT 5 /* IRQ0 :: IRQEN :: ua_irqen [04:04] */ #define BCHP_IRQ0_IRQEN_ua_irqen_MASK 0x00000010 #define BCHP_IRQ0_IRQEN_ua_irqen_SHIFT 4 /* IRQ0 :: IRQEN :: ub_irqen [03:03] */ #define BCHP_IRQ0_IRQEN_ub_irqen_MASK 0x00000008 #define BCHP_IRQ0_IRQEN_ub_irqen_SHIFT 3 /* IRQ0 :: IRQEN :: reserved_for_eco6 [02:02] */ #define BCHP_IRQ0_IRQEN_reserved_for_eco6_MASK 0x00000004 #define BCHP_IRQ0_IRQEN_reserved_for_eco6_SHIFT 2 /* IRQ0 :: IRQEN :: ldk_irqen [01:01] */ #define BCHP_IRQ0_IRQEN_ldk_irqen_MASK 0x00000002 #define BCHP_IRQ0_IRQEN_ldk_irqen_SHIFT 1 /* IRQ0 :: IRQEN :: kbd1_irqen [00:00] */ #define BCHP_IRQ0_IRQEN_kbd1_irqen_MASK 0x00000001 #define BCHP_IRQ0_IRQEN_kbd1_irqen_SHIFT 0 /*************************************************************************** *IRQSTAT - Interrupt Status ***************************************************************************/ /* IRQ0 :: IRQSTAT :: reserved0 [31:29] */ #define BCHP_IRQ0_IRQSTAT_reserved0_MASK 0xe0000000 #define BCHP_IRQ0_IRQSTAT_reserved0_SHIFT 29 /* IRQ0 :: IRQSTAT :: iiceirq [28:28] */ #define BCHP_IRQ0_IRQSTAT_iiceirq_MASK 0x10000000 #define BCHP_IRQ0_IRQSTAT_iiceirq_SHIFT 28 /* IRQ0 :: IRQSTAT :: iicdirq [27:27] */ #define BCHP_IRQ0_IRQSTAT_iicdirq_MASK 0x08000000 #define BCHP_IRQ0_IRQSTAT_iicdirq_SHIFT 27 /* IRQ0 :: IRQSTAT :: iiccirq [26:26] */ #define BCHP_IRQ0_IRQSTAT_iiccirq_MASK 0x04000000 #define BCHP_IRQ0_IRQSTAT_iiccirq_SHIFT 26 /* IRQ0 :: IRQSTAT :: iicbirq [25:25] */ #define BCHP_IRQ0_IRQSTAT_iicbirq_MASK 0x02000000 #define BCHP_IRQ0_IRQSTAT_iicbirq_SHIFT 25 /* IRQ0 :: IRQSTAT :: iicairq [24:24] */ #define BCHP_IRQ0_IRQSTAT_iicairq_MASK 0x01000000 #define BCHP_IRQ0_IRQSTAT_iicairq_SHIFT 24 /* IRQ0 :: IRQSTAT :: reserved1 [23:21] */ #define BCHP_IRQ0_IRQSTAT_reserved1_MASK 0x00e00000 #define BCHP_IRQ0_IRQSTAT_reserved1_SHIFT 21 /* IRQ0 :: IRQSTAT :: spiirq [20:20] */ #define BCHP_IRQ0_IRQSTAT_spiirq_MASK 0x00100000 #define BCHP_IRQ0_IRQSTAT_spiirq_SHIFT 20 /* IRQ0 :: IRQSTAT :: uartd_irq [19:19] */ #define BCHP_IRQ0_IRQSTAT_uartd_irq_MASK 0x00080000 #define BCHP_IRQ0_IRQSTAT_uartd_irq_SHIFT 19 /* IRQ0 :: IRQSTAT :: uartc_irq [18:18] */ #define BCHP_IRQ0_IRQSTAT_uartc_irq_MASK 0x00040000 #define BCHP_IRQ0_IRQSTAT_uartc_irq_SHIFT 18 /* IRQ0 :: IRQSTAT :: uartb_irq [17:17] */ #define BCHP_IRQ0_IRQSTAT_uartb_irq_MASK 0x00020000 #define BCHP_IRQ0_IRQSTAT_uartb_irq_SHIFT 17 /* IRQ0 :: IRQSTAT :: uarta_irq [16:16] */ #define BCHP_IRQ0_IRQSTAT_uarta_irq_MASK 0x00010000 #define BCHP_IRQ0_IRQSTAT_uarta_irq_SHIFT 16 /* IRQ0 :: IRQSTAT :: reserved2 [15:12] */ #define BCHP_IRQ0_IRQSTAT_reserved2_MASK 0x0000f000 #define BCHP_IRQ0_IRQSTAT_reserved2_SHIFT 12 /* IRQ0 :: IRQSTAT :: udirq [11:11] */ #define BCHP_IRQ0_IRQSTAT_udirq_MASK 0x00000800 #define BCHP_IRQ0_IRQSTAT_udirq_SHIFT 11 /* IRQ0 :: IRQSTAT :: reserved3 [10:10] */ #define BCHP_IRQ0_IRQSTAT_reserved3_MASK 0x00000400 #define BCHP_IRQ0_IRQSTAT_reserved3_SHIFT 10 /* IRQ0 :: IRQSTAT :: ucirq [09:09] */ #define BCHP_IRQ0_IRQSTAT_ucirq_MASK 0x00000200 #define BCHP_IRQ0_IRQSTAT_ucirq_SHIFT 9 /* IRQ0 :: IRQSTAT :: reserved4 [08:08] */ #define BCHP_IRQ0_IRQSTAT_reserved4_MASK 0x00000100 #define BCHP_IRQ0_IRQSTAT_reserved4_SHIFT 8 /* IRQ0 :: IRQSTAT :: icapirq [07:07] */ #define BCHP_IRQ0_IRQSTAT_icapirq_MASK 0x00000080 #define BCHP_IRQ0_IRQSTAT_icapirq_SHIFT 7 /* IRQ0 :: IRQSTAT :: gioirq [06:06] */ #define BCHP_IRQ0_IRQSTAT_gioirq_MASK 0x00000040 #define BCHP_IRQ0_IRQSTAT_gioirq_SHIFT 6 /* IRQ0 :: IRQSTAT :: reserved5 [05:05] */ #define BCHP_IRQ0_IRQSTAT_reserved5_MASK 0x00000020 #define BCHP_IRQ0_IRQSTAT_reserved5_SHIFT 5 /* IRQ0 :: IRQSTAT :: uairq [04:04] */ #define BCHP_IRQ0_IRQSTAT_uairq_MASK 0x00000010 #define BCHP_IRQ0_IRQSTAT_uairq_SHIFT 4 /* IRQ0 :: IRQSTAT :: ubirq [03:03] */ #define BCHP_IRQ0_IRQSTAT_ubirq_MASK 0x00000008 #define BCHP_IRQ0_IRQSTAT_ubirq_SHIFT 3 /* IRQ0 :: IRQSTAT :: reserved6 [02:02] */ #define BCHP_IRQ0_IRQSTAT_reserved6_MASK 0x00000004 #define BCHP_IRQ0_IRQSTAT_reserved6_SHIFT 2 /* IRQ0 :: IRQSTAT :: ldkirq [01:01] */ #define BCHP_IRQ0_IRQSTAT_ldkirq_MASK 0x00000002 #define BCHP_IRQ0_IRQSTAT_ldkirq_SHIFT 1 /* IRQ0 :: IRQSTAT :: kbd1irq [00:00] */ #define BCHP_IRQ0_IRQSTAT_kbd1irq_MASK 0x00000001 #define BCHP_IRQ0_IRQSTAT_kbd1irq_SHIFT 0 #endif /* #ifndef BCHP_IRQ0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016100000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudma2_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000650111610313111030763 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_cpudma2_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:00p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:26 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudma2_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:00p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_CPUDMA2_0_H__ #define BCHP_DECODE_CPUDMA2_0_H__ /*************************************************************************** *DECODE_CPUDMA2_0 ***************************************************************************/ #define BCHP_DECODE_CPUDMA2_0_REG_DMA0_SD_ADDR 0x00851800 /* SDRAM address */ #define BCHP_DECODE_CPUDMA2_0_REG_DMA0_LCL_ADDR 0x00851804 /* Local Memory Address */ #define BCHP_DECODE_CPUDMA2_0_REG_DMA0_LEN 0x00851808 /* Length */ #define BCHP_DECODE_CPUDMA2_0_REG_DMA1_SD_ADDR 0x00851810 /* REG_DMA1_SD_ADDR */ #define BCHP_DECODE_CPUDMA2_0_REG_DMA1_LCL_ADDR 0x00851814 /* REG_DMA1_LCL_ADDR */ #define BCHP_DECODE_CPUDMA2_0_REG_DMA1_LEN 0x00851818 /* REG_DMA1_LEN */ #define BCHP_DECODE_CPUDMA2_0_REG_DMA2_SD_ADDR 0x00851820 /* REG_DMA2_SD_ADDR */ #define BCHP_DECODE_CPUDMA2_0_REG_DMA2_LCL_ADDR 0x00851824 /* REG_DMA2_LCL_ADDR */ #define BCHP_DECODE_CPUDMA2_0_REG_DMA2_LEN 0x00851828 /* REG_DMA2_LEN */ #define BCHP_DECODE_CPUDMA2_0_REG_DMA3_SD_ADDR 0x00851830 /* REG_DMA3_SD_ADDR */ #define BCHP_DECODE_CPUDMA2_0_REG_DMA3_LCL_ADDR 0x00851834 /* REG_DMA3_LCL_ADDR */ #define BCHP_DECODE_CPUDMA2_0_REG_DMA3_LEN 0x00851838 /* REG_DMA3_LEN */ #define BCHP_DECODE_CPUDMA2_0_REG_DMA_STATUS 0x00851840 /* REG_DMA_STATUS */ #define BCHP_DECODE_CPUDMA2_0_REG_CPUDMA_END 0x008518fc /* REG_CPUDMA_END */ #endif /* #ifndef BCHP_DECODE_CPUDMA2_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000014600000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc1.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc1.0000644000175000017500000014065011610313111030636 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_misc1.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:11p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:40 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc1.h $ * * Hydra_Software_Devel/1 7/17/09 8:11p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_MISC1_H__ #define BCHP_MISC1_H__ /*************************************************************************** *MISC1 - Registers for DMA List Control ***************************************************************************/ #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0 0x00502000 /* Tx DMA Descriptor List0 First Descriptor lower Address */ #define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST0 0x00502004 /* Tx DMA Descriptor List0 First Descriptor Upper Address */ #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1 0x00502008 /* Tx DMA Descriptor List1 First Descriptor Lower Address */ #define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST1 0x0050200c /* Tx DMA Descriptor List1 First Descriptor Upper Address */ #define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS 0x00502010 /* Tx DMA Software Descriptor List Control and Status */ #define BCHP_MISC1_TX_DMA_ERROR_STATUS 0x00502018 /* Tx DMA Engine Error Status */ #define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR 0x0050201c /* Tx DMA List0 Current Descriptor Lower Address */ #define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR 0x00502020 /* Tx DMA List0 Current Descriptor Upper Address */ #define BCHP_MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM 0x00502024 /* Tx DMA List0 Current Descriptor Upper Address */ #define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR 0x00502028 /* Tx DMA List1 Current Descriptor Lower Address */ #define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR 0x0050202c /* Tx DMA List1 Current Descriptor Upper Address */ #define BCHP_MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM 0x00502030 /* Tx DMA List1 Current Descriptor Upper Address */ #define BCHP_MISC1_TX_DMA_CTRL 0x00502034 /* Tx DMA Flea Interface Control */ #define BCHP_MISC1_TX_DMA_STATE 0x00502038 /* Tx DMA Flea Interface State */ #define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0 0x00502040 /* Y Rx Descriptor List0 First Descriptor Lower Address */ #define BCHP_MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0 0x00502044 /* Y Rx Descriptor List0 First Descriptor Upper Address */ #define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1 0x00502048 /* Y Rx Descriptor List1 First Descriptor Lower Address */ #define BCHP_MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1 0x0050204c /* Y Rx Descriptor List1 First Descriptor Upper Address */ #define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS 0x00502050 /* Y Rx Software Descriptor List Control and Status */ #define BCHP_MISC1_Y_RX_ERROR_STATUS 0x00502054 /* Y Rx Engine Error Status */ #define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR 0x00502058 /* Y Rx List0 Current Descriptor Lower Address */ #define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR 0x0050205c /* Y Rx List0 Current Descriptor Upper Address */ #define BCHP_MISC1_Y_RX_LIST0_CUR_BYTE_CNT 0x00502060 /* Y Rx List0 Current Descriptor Byte Count */ #define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR 0x00502064 /* Y Rx List1 Current Descriptor Lower address */ #define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR 0x00502068 /* Y Rx List1 Current Descriptor Upper address */ #define BCHP_MISC1_Y_RX_LIST1_CUR_BYTE_CNT 0x0050206c /* Y Rx List1 Current Descriptor Byte Count */ #define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST0 0x00502080 /* HIF Rx Descriptor List0 First Descriptor lower Address */ #define BCHP_MISC1_HIF_RX_FIRST_DESC_U_ADDR_LIST0 0x00502084 /* HIF Rx Descriptor List0 First Descriptor Upper Address */ #define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST1 0x00502088 /* HIF Rx Descriptor List1 First Descriptor Lower Address */ #define BCHP_MISC1_HIF_RX_FIRST_DESC_U_ADDR_LIST1 0x0050208c /* HIF Rx Descriptor List1 First Descriptor Upper Address */ #define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS 0x00502090 /* HIF Rx Software Descriptor List Control and Status */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS 0x00502094 /* HIF Rx Engine Error Status */ #define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_L_ADDR 0x00502098 /* HIF Rx List0 Current Descriptor Lower Address */ #define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_U_ADDR 0x0050209c /* HIF Rx List0 Current Descriptor Upper Address */ #define BCHP_MISC1_HIF_RX_LIST0_CUR_BYTE_CNT 0x005020a0 /* HIF Rx List0 Current Descriptor Byte Count */ #define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_L_ADDR 0x005020a4 /* HIF Rx List1 Current Descriptor Lower Address */ #define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_U_ADDR 0x005020a8 /* HIF Rx List1 Current Descriptor Upper Address */ #define BCHP_MISC1_HIF_RX_LIST1_CUR_BYTE_CNT 0x005020ac /* HIF Rx List1 Current Descriptor Byte Count */ #define BCHP_MISC1_HIF_DMA_CTRL 0x005020b0 /* HIF Rx DMA Flea Interface Control */ #define BCHP_MISC1_HIF_DMA_STATE 0x005020b4 /* HIF Rx DMA Flea Interface State */ #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG 0x005020c0 /* DMA Debug Options Register */ #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS 0x005020c4 /* Read Channel Error Status */ #define BCHP_MISC1_PCIE_DMA_CTRL 0x005020c8 /* PCIE DMA Control Register */ #define BCHP_MISC1_HIF_RXDMA_BASE_ADDR 0x005020cc /* HIF Rx DMA Base DRAM Address */ #define BCHP_MISC1_HIF_RXDMA_LENGTH 0x005020d0 /* HIF Rx DMA Transfer Length */ /*************************************************************************** *TX_FIRST_DESC_L_ADDR_LIST0 - Tx DMA Descriptor List0 First Descriptor lower Address ***************************************************************************/ /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST0 :: TX_DESC_LIST0_VALID [00:00] */ #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_MASK 0x00000001 #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0_TX_DESC_LIST0_VALID_SHIFT 0 /*************************************************************************** *TX_FIRST_DESC_U_ADDR_LIST0 - Tx DMA Descriptor List0 First Descriptor Upper Address ***************************************************************************/ /* MISC1 :: TX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ #define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff #define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 /*************************************************************************** *TX_FIRST_DESC_L_ADDR_LIST1 - Tx DMA Descriptor List1 First Descriptor Lower Address ***************************************************************************/ /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 /* MISC1 :: TX_FIRST_DESC_L_ADDR_LIST1 :: TX_DESC_LIST1_VALID [00:00] */ #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_MASK 0x00000001 #define BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1_TX_DESC_LIST1_VALID_SHIFT 0 /*************************************************************************** *TX_FIRST_DESC_U_ADDR_LIST1 - Tx DMA Descriptor List1 First Descriptor Upper Address ***************************************************************************/ /* MISC1 :: TX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ #define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff #define BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 /*************************************************************************** *TX_SW_DESC_LIST_CTRL_STS - Tx DMA Software Descriptor List Control and Status ***************************************************************************/ /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ #define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 #define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ #define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 #define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ #define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 #define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_HALT_ON_ERROR [01:01] */ #define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_MASK 0x00000002 #define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_HALT_ON_ERROR_SHIFT 1 /* MISC1 :: TX_SW_DESC_LIST_CTRL_STS :: TX_DMA_RUN_STOP [00:00] */ #define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK 0x00000001 #define BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_SHIFT 0 /*************************************************************************** *TX_DMA_ERROR_STATUS - Tx DMA Engine Error Status ***************************************************************************/ /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved0 [31:10] */ #define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved0_MASK 0xfffffc00 #define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved0_SHIFT 10 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DESC_TX_ABORT_ERRORS [09:09] */ #define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 #define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved1 [08:08] */ #define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved1_MASK 0x00000100 #define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved1_SHIFT 8 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DESC_TX_ABORT_ERRORS [07:07] */ #define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 #define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved2 [06:06] */ #define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved2_MASK 0x00000040 #define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved2_SHIFT 6 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_DMA_DATA_TX_ABORT_ERRORS [05:05] */ #define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000020 #define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_SHIFT 5 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L1_FIFO_FULL_ERRORS [04:04] */ #define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 #define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_SHIFT 4 /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved3 [03:03] */ #define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved3_MASK 0x00000008 #define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved3_SHIFT 3 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_DMA_DATA_TX_ABORT_ERRORS [02:02] */ #define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK 0x00000004 #define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_SHIFT 2 /* MISC1 :: TX_DMA_ERROR_STATUS :: TX_L0_FIFO_FULL_ERRORS [01:01] */ #define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 #define BCHP_MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_SHIFT 1 /* MISC1 :: TX_DMA_ERROR_STATUS :: reserved4 [00:00] */ #define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved4_MASK 0x00000001 #define BCHP_MISC1_TX_DMA_ERROR_STATUS_reserved4_SHIFT 0 /*************************************************************************** *TX_DMA_LIST0_CUR_DESC_L_ADDR - Tx DMA List0 Current Descriptor Lower Address ***************************************************************************/ /* MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR :: TX_DMA_L0_CUR_DESC_L_ADDR [31:05] */ #define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 #define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_TX_DMA_L0_CUR_DESC_L_ADDR_SHIFT 5 /* MISC1 :: TX_DMA_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ #define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f #define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 /*************************************************************************** *TX_DMA_LIST0_CUR_DESC_U_ADDR - Tx DMA List0 Current Descriptor Upper Address ***************************************************************************/ /* MISC1 :: TX_DMA_LIST0_CUR_DESC_U_ADDR :: TX_DMA_L0_CUR_DESC_U_ADDR [31:00] */ #define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_MASK 0xffffffff #define BCHP_MISC1_TX_DMA_LIST0_CUR_DESC_U_ADDR_TX_DMA_L0_CUR_DESC_U_ADDR_SHIFT 0 /*************************************************************************** *TX_DMA_LIST0_CUR_BYTE_CNT_REM - Tx DMA List0 Current Descriptor Upper Address ***************************************************************************/ /* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: reserved0 [31:24] */ #define BCHP_MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_MASK 0xff000000 #define BCHP_MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved0_SHIFT 24 /* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: TX_DMA_L0_CUR_BYTE_CNT_REM [23:02] */ #define BCHP_MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_MASK 0x00fffffc #define BCHP_MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_TX_DMA_L0_CUR_BYTE_CNT_REM_SHIFT 2 /* MISC1 :: TX_DMA_LIST0_CUR_BYTE_CNT_REM :: reserved1 [01:00] */ #define BCHP_MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_MASK 0x00000003 #define BCHP_MISC1_TX_DMA_LIST0_CUR_BYTE_CNT_REM_reserved1_SHIFT 0 /*************************************************************************** *TX_DMA_LIST1_CUR_DESC_L_ADDR - Tx DMA List1 Current Descriptor Lower Address ***************************************************************************/ /* MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR :: TX_DMA_L1_CUR_DESC_L_ADDR [31:05] */ #define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 #define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_TX_DMA_L1_CUR_DESC_L_ADDR_SHIFT 5 /* MISC1 :: TX_DMA_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ #define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f #define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 /*************************************************************************** *TX_DMA_LIST1_CUR_DESC_U_ADDR - Tx DMA List1 Current Descriptor Upper Address ***************************************************************************/ /* MISC1 :: TX_DMA_LIST1_CUR_DESC_U_ADDR :: TX_DMA_L1_CUR_DESC_U_ADDR [31:00] */ #define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_MASK 0xffffffff #define BCHP_MISC1_TX_DMA_LIST1_CUR_DESC_U_ADDR_TX_DMA_L1_CUR_DESC_U_ADDR_SHIFT 0 /*************************************************************************** *TX_DMA_LIST1_CUR_BYTE_CNT_REM - Tx DMA List1 Current Descriptor Upper Address ***************************************************************************/ /* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: reserved0 [31:24] */ #define BCHP_MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_MASK 0xff000000 #define BCHP_MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved0_SHIFT 24 /* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: TX_DMA_L1_CUR_BYTE_CNT_REM [23:02] */ #define BCHP_MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_MASK 0x00fffffc #define BCHP_MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_TX_DMA_L1_CUR_BYTE_CNT_REM_SHIFT 2 /* MISC1 :: TX_DMA_LIST1_CUR_BYTE_CNT_REM :: reserved1 [01:00] */ #define BCHP_MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_MASK 0x00000003 #define BCHP_MISC1_TX_DMA_LIST1_CUR_BYTE_CNT_REM_reserved1_SHIFT 0 /*************************************************************************** *TX_DMA_CTRL - Tx DMA Flea Interface Control ***************************************************************************/ /* MISC1 :: TX_DMA_CTRL :: reserved0 [31:02] */ #define BCHP_MISC1_TX_DMA_CTRL_reserved0_MASK 0xfffffffc #define BCHP_MISC1_TX_DMA_CTRL_reserved0_SHIFT 2 /* MISC1 :: TX_DMA_CTRL :: TX_DMA_FLUSH_REQUEST [01:01] */ #define BCHP_MISC1_TX_DMA_CTRL_TX_DMA_FLUSH_REQUEST_MASK 0x00000002 #define BCHP_MISC1_TX_DMA_CTRL_TX_DMA_FLUSH_REQUEST_SHIFT 1 /* MISC1 :: TX_DMA_CTRL :: TX_DMA_ENABLE [00:00] */ #define BCHP_MISC1_TX_DMA_CTRL_TX_DMA_ENABLE_MASK 0x00000001 #define BCHP_MISC1_TX_DMA_CTRL_TX_DMA_ENABLE_SHIFT 0 /*************************************************************************** *TX_DMA_STATE - Tx DMA Flea Interface State ***************************************************************************/ /* MISC1 :: TX_DMA_STATE :: reserved0 [31:04] */ #define BCHP_MISC1_TX_DMA_STATE_reserved0_MASK 0xfffffff0 #define BCHP_MISC1_TX_DMA_STATE_reserved0_SHIFT 4 /* MISC1 :: TX_DMA_STATE :: TX_DMA_ERROR [03:03] */ #define BCHP_MISC1_TX_DMA_STATE_TX_DMA_ERROR_MASK 0x00000008 #define BCHP_MISC1_TX_DMA_STATE_TX_DMA_ERROR_SHIFT 3 /* MISC1 :: TX_DMA_STATE :: TX_DMA_FLUSH_ACTIVE [02:02] */ #define BCHP_MISC1_TX_DMA_STATE_TX_DMA_FLUSH_ACTIVE_MASK 0x00000004 #define BCHP_MISC1_TX_DMA_STATE_TX_DMA_FLUSH_ACTIVE_SHIFT 2 /* MISC1 :: TX_DMA_STATE :: TX_DMA_FIFO_ACTIVE [01:01] */ #define BCHP_MISC1_TX_DMA_STATE_TX_DMA_FIFO_ACTIVE_MASK 0x00000002 #define BCHP_MISC1_TX_DMA_STATE_TX_DMA_FIFO_ACTIVE_SHIFT 1 /* MISC1 :: TX_DMA_STATE :: TX_DMA_ACTIVE [00:00] */ #define BCHP_MISC1_TX_DMA_STATE_TX_DMA_ACTIVE_MASK 0x00000001 #define BCHP_MISC1_TX_DMA_STATE_TX_DMA_ACTIVE_SHIFT 0 /*************************************************************************** *Y_RX_FIRST_DESC_L_ADDR_LIST0 - Y Rx Descriptor List0 First Descriptor Lower Address ***************************************************************************/ /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ #define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 #define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ #define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e #define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */ #define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001 #define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0 /*************************************************************************** *Y_RX_FIRST_DESC_U_ADDR_LIST0 - Y Rx Descriptor List0 First Descriptor Upper Address ***************************************************************************/ /* MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ #define BCHP_MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff #define BCHP_MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 /*************************************************************************** *Y_RX_FIRST_DESC_L_ADDR_LIST1 - Y Rx Descriptor List1 First Descriptor Lower Address ***************************************************************************/ /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ #define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 #define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ #define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e #define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 /* MISC1 :: Y_RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */ #define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001 #define BCHP_MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0 /*************************************************************************** *Y_RX_FIRST_DESC_U_ADDR_LIST1 - Y Rx Descriptor List1 First Descriptor Upper Address ***************************************************************************/ /* MISC1 :: Y_RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ #define BCHP_MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff #define BCHP_MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 /*************************************************************************** *Y_RX_SW_DESC_LIST_CTRL_STS - Y Rx Software Descriptor List Control and Status ***************************************************************************/ /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ #define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 #define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ #define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 #define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ #define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 #define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: RX_HALT_ON_ERROR [01:01] */ #define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_MASK 0x00000002 #define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_SHIFT 1 /* MISC1 :: Y_RX_SW_DESC_LIST_CTRL_STS :: RX_RUN_STOP [00:00] */ #define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_MASK 0x00000001 #define BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_SHIFT 0 /*************************************************************************** *Y_RX_ERROR_STATUS - Y Rx Engine Error Status ***************************************************************************/ /* MISC1 :: Y_RX_ERROR_STATUS :: reserved0 [31:14] */ #define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 #define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved0_SHIFT 14 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 /* MISC1 :: Y_RX_ERROR_STATUS :: reserved1 [08:08] */ #define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved1_MASK 0x00000100 #define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved1_SHIFT 8 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 /* MISC1 :: Y_RX_ERROR_STATUS :: reserved2 [06:05] */ #define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved2_MASK 0x00000060 #define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved2_SHIFT 5 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 /* MISC1 :: Y_RX_ERROR_STATUS :: reserved3 [03:02] */ #define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved3_MASK 0x0000000c #define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved3_SHIFT 2 /* MISC1 :: Y_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 #define BCHP_MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 /* MISC1 :: Y_RX_ERROR_STATUS :: reserved4 [00:00] */ #define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved4_MASK 0x00000001 #define BCHP_MISC1_Y_RX_ERROR_STATUS_reserved4_SHIFT 0 /*************************************************************************** *Y_RX_LIST0_CUR_DESC_L_ADDR - Y Rx List0 Current Descriptor Lower Address ***************************************************************************/ /* MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */ #define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 #define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5 /* MISC1 :: Y_RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ #define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f #define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 /*************************************************************************** *Y_RX_LIST0_CUR_DESC_U_ADDR - Y Rx List0 Current Descriptor Upper Address ***************************************************************************/ /* MISC1 :: Y_RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */ #define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff #define BCHP_MISC1_Y_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0 /*************************************************************************** *Y_RX_LIST0_CUR_BYTE_CNT - Y Rx List0 Current Descriptor Byte Count ***************************************************************************/ /* MISC1 :: Y_RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */ #define BCHP_MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff #define BCHP_MISC1_Y_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0 /*************************************************************************** *Y_RX_LIST1_CUR_DESC_L_ADDR - Y Rx List1 Current Descriptor Lower address ***************************************************************************/ /* MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */ #define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 #define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5 /* MISC1 :: Y_RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ #define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f #define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 /*************************************************************************** *Y_RX_LIST1_CUR_DESC_U_ADDR - Y Rx List1 Current Descriptor Upper address ***************************************************************************/ /* MISC1 :: Y_RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */ #define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff #define BCHP_MISC1_Y_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0 /*************************************************************************** *Y_RX_LIST1_CUR_BYTE_CNT - Y Rx List1 Current Descriptor Byte Count ***************************************************************************/ /* MISC1 :: Y_RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */ #define BCHP_MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff #define BCHP_MISC1_Y_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0 /*************************************************************************** *HIF_RX_FIRST_DESC_L_ADDR_LIST0 - HIF Rx Descriptor List0 First Descriptor lower Address ***************************************************************************/ /* MISC1 :: HIF_RX_FIRST_DESC_L_ADDR_LIST0 :: DESC_ADDR [31:05] */ #define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_MASK 0xffffffe0 #define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST0_DESC_ADDR_SHIFT 5 /* MISC1 :: HIF_RX_FIRST_DESC_L_ADDR_LIST0 :: reserved0 [04:01] */ #define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_MASK 0x0000001e #define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST0_reserved0_SHIFT 1 /* MISC1 :: HIF_RX_FIRST_DESC_L_ADDR_LIST0 :: RX_DESC_LIST0_VALID [00:00] */ #define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_MASK 0x00000001 #define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST0_RX_DESC_LIST0_VALID_SHIFT 0 /*************************************************************************** *HIF_RX_FIRST_DESC_U_ADDR_LIST0 - HIF Rx Descriptor List0 First Descriptor Upper Address ***************************************************************************/ /* MISC1 :: HIF_RX_FIRST_DESC_U_ADDR_LIST0 :: DESC_ADDR [31:00] */ #define BCHP_MISC1_HIF_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_MASK 0xffffffff #define BCHP_MISC1_HIF_RX_FIRST_DESC_U_ADDR_LIST0_DESC_ADDR_SHIFT 0 /*************************************************************************** *HIF_RX_FIRST_DESC_L_ADDR_LIST1 - HIF Rx Descriptor List1 First Descriptor Lower Address ***************************************************************************/ /* MISC1 :: HIF_RX_FIRST_DESC_L_ADDR_LIST1 :: DESC_ADDR [31:05] */ #define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_MASK 0xffffffe0 #define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST1_DESC_ADDR_SHIFT 5 /* MISC1 :: HIF_RX_FIRST_DESC_L_ADDR_LIST1 :: reserved0 [04:01] */ #define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_MASK 0x0000001e #define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST1_reserved0_SHIFT 1 /* MISC1 :: HIF_RX_FIRST_DESC_L_ADDR_LIST1 :: RX_DESC_LIST1_VALID [00:00] */ #define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_MASK 0x00000001 #define BCHP_MISC1_HIF_RX_FIRST_DESC_L_ADDR_LIST1_RX_DESC_LIST1_VALID_SHIFT 0 /*************************************************************************** *HIF_RX_FIRST_DESC_U_ADDR_LIST1 - HIF Rx Descriptor List1 First Descriptor Upper Address ***************************************************************************/ /* MISC1 :: HIF_RX_FIRST_DESC_U_ADDR_LIST1 :: DESC_ADDR [31:00] */ #define BCHP_MISC1_HIF_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_MASK 0xffffffff #define BCHP_MISC1_HIF_RX_FIRST_DESC_U_ADDR_LIST1_DESC_ADDR_SHIFT 0 /*************************************************************************** *HIF_RX_SW_DESC_LIST_CTRL_STS - HIF Rx Software Descriptor List Control and Status ***************************************************************************/ /* MISC1 :: HIF_RX_SW_DESC_LIST_CTRL_STS :: reserved0 [31:04] */ #define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_reserved0_MASK 0xfffffff0 #define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_reserved0_SHIFT 4 /* MISC1 :: HIF_RX_SW_DESC_LIST_CTRL_STS :: DMA_DATA_SERV_PTR [03:03] */ #define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_MASK 0x00000008 #define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_DMA_DATA_SERV_PTR_SHIFT 3 /* MISC1 :: HIF_RX_SW_DESC_LIST_CTRL_STS :: DESC_SERV_PTR [02:02] */ #define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_MASK 0x00000004 #define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_DESC_SERV_PTR_SHIFT 2 /* MISC1 :: HIF_RX_SW_DESC_LIST_CTRL_STS :: RX_HALT_ON_ERROR [01:01] */ #define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_MASK 0x00000002 #define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_RX_HALT_ON_ERROR_SHIFT 1 /* MISC1 :: HIF_RX_SW_DESC_LIST_CTRL_STS :: RX_RUN_STOP [00:00] */ #define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_MASK 0x00000001 #define BCHP_MISC1_HIF_RX_SW_DESC_LIST_CTRL_STS_RX_RUN_STOP_SHIFT 0 /*************************************************************************** *HIF_RX_ERROR_STATUS - HIF Rx Engine Error Status ***************************************************************************/ /* MISC1 :: HIF_RX_ERROR_STATUS :: reserved0 [31:14] */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved0_MASK 0xffffc000 #define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved0_SHIFT 14 /* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L1_UNDERRUN_ERROR [13:13] */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK 0x00002000 #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_SHIFT 13 /* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L1_OVERRUN_ERROR [12:12] */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK 0x00001000 #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_SHIFT 12 /* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L0_UNDERRUN_ERROR [11:11] */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK 0x00000800 #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_SHIFT 11 /* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L0_OVERRUN_ERROR [10:10] */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK 0x00000400 #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_SHIFT 10 /* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L1_DESC_TX_ABORT_ERRORS [09:09] */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK 0x00000200 #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_SHIFT 9 /* MISC1 :: HIF_RX_ERROR_STATUS :: reserved1 [08:08] */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved1_MASK 0x00000100 #define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved1_SHIFT 8 /* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L0_DESC_TX_ABORT_ERRORS [07:07] */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK 0x00000080 #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_SHIFT 7 /* MISC1 :: HIF_RX_ERROR_STATUS :: reserved2 [06:05] */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved2_MASK 0x00000060 #define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved2_SHIFT 5 /* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L1_FIFO_FULL_ERRORS [04:04] */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK 0x00000010 #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_SHIFT 4 /* MISC1 :: HIF_RX_ERROR_STATUS :: reserved3 [03:02] */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved3_MASK 0x0000000c #define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved3_SHIFT 2 /* MISC1 :: HIF_RX_ERROR_STATUS :: RX_L0_FIFO_FULL_ERRORS [01:01] */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK 0x00000002 #define BCHP_MISC1_HIF_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_SHIFT 1 /* MISC1 :: HIF_RX_ERROR_STATUS :: reserved4 [00:00] */ #define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved4_MASK 0x00000001 #define BCHP_MISC1_HIF_RX_ERROR_STATUS_reserved4_SHIFT 0 /*************************************************************************** *HIF_RX_LIST0_CUR_DESC_L_ADDR - HIF Rx List0 Current Descriptor Lower Address ***************************************************************************/ /* MISC1 :: HIF_RX_LIST0_CUR_DESC_L_ADDR :: RX_L0_CUR_DESC_L_ADDR [31:05] */ #define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_MASK 0xffffffe0 #define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_L_ADDR_RX_L0_CUR_DESC_L_ADDR_SHIFT 5 /* MISC1 :: HIF_RX_LIST0_CUR_DESC_L_ADDR :: reserved0 [04:00] */ #define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f #define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_L_ADDR_reserved0_SHIFT 0 /*************************************************************************** *HIF_RX_LIST0_CUR_DESC_U_ADDR - HIF Rx List0 Current Descriptor Upper Address ***************************************************************************/ /* MISC1 :: HIF_RX_LIST0_CUR_DESC_U_ADDR :: RX_L0_CUR_DESC_U_ADDR [31:00] */ #define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_MASK 0xffffffff #define BCHP_MISC1_HIF_RX_LIST0_CUR_DESC_U_ADDR_RX_L0_CUR_DESC_U_ADDR_SHIFT 0 /*************************************************************************** *HIF_RX_LIST0_CUR_BYTE_CNT - HIF Rx List0 Current Descriptor Byte Count ***************************************************************************/ /* MISC1 :: HIF_RX_LIST0_CUR_BYTE_CNT :: RX_L0_CUR_BYTE_CNT [31:00] */ #define BCHP_MISC1_HIF_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_MASK 0xffffffff #define BCHP_MISC1_HIF_RX_LIST0_CUR_BYTE_CNT_RX_L0_CUR_BYTE_CNT_SHIFT 0 /*************************************************************************** *HIF_RX_LIST1_CUR_DESC_L_ADDR - HIF Rx List1 Current Descriptor Lower Address ***************************************************************************/ /* MISC1 :: HIF_RX_LIST1_CUR_DESC_L_ADDR :: RX_L1_CUR_DESC_L_ADDR [31:05] */ #define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_MASK 0xffffffe0 #define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_L_ADDR_RX_L1_CUR_DESC_L_ADDR_SHIFT 5 /* MISC1 :: HIF_RX_LIST1_CUR_DESC_L_ADDR :: reserved0 [04:00] */ #define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_L_ADDR_reserved0_MASK 0x0000001f #define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_L_ADDR_reserved0_SHIFT 0 /*************************************************************************** *HIF_RX_LIST1_CUR_DESC_U_ADDR - HIF Rx List1 Current Descriptor Upper Address ***************************************************************************/ /* MISC1 :: HIF_RX_LIST1_CUR_DESC_U_ADDR :: RX_L1_CUR_DESC_U_ADDR [31:00] */ #define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_MASK 0xffffffff #define BCHP_MISC1_HIF_RX_LIST1_CUR_DESC_U_ADDR_RX_L1_CUR_DESC_U_ADDR_SHIFT 0 /*************************************************************************** *HIF_RX_LIST1_CUR_BYTE_CNT - HIF Rx List1 Current Descriptor Byte Count ***************************************************************************/ /* MISC1 :: HIF_RX_LIST1_CUR_BYTE_CNT :: RX_L1_CUR_BYTE_CNT [31:00] */ #define BCHP_MISC1_HIF_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_MASK 0xffffffff #define BCHP_MISC1_HIF_RX_LIST1_CUR_BYTE_CNT_RX_L1_CUR_BYTE_CNT_SHIFT 0 /*************************************************************************** *HIF_DMA_CTRL - HIF Rx DMA Flea Interface Control ***************************************************************************/ /* MISC1 :: HIF_DMA_CTRL :: reserved0 [31:01] */ #define BCHP_MISC1_HIF_DMA_CTRL_reserved0_MASK 0xfffffffe #define BCHP_MISC1_HIF_DMA_CTRL_reserved0_SHIFT 1 /* MISC1 :: HIF_DMA_CTRL :: RX_DMA_ENABLE [00:00] */ #define BCHP_MISC1_HIF_DMA_CTRL_RX_DMA_ENABLE_MASK 0x00000001 #define BCHP_MISC1_HIF_DMA_CTRL_RX_DMA_ENABLE_SHIFT 0 /*************************************************************************** *HIF_DMA_STATE - HIF Rx DMA Flea Interface State ***************************************************************************/ /* MISC1 :: HIF_DMA_STATE :: reserved0 [31:03] */ #define BCHP_MISC1_HIF_DMA_STATE_reserved0_MASK 0xfffffff8 #define BCHP_MISC1_HIF_DMA_STATE_reserved0_SHIFT 3 /* MISC1 :: HIF_DMA_STATE :: RX_DMA_ERROR [02:02] */ #define BCHP_MISC1_HIF_DMA_STATE_RX_DMA_ERROR_MASK 0x00000004 #define BCHP_MISC1_HIF_DMA_STATE_RX_DMA_ERROR_SHIFT 2 /* MISC1 :: HIF_DMA_STATE :: RX_DMA_FIFO_ACTIVE [01:01] */ #define BCHP_MISC1_HIF_DMA_STATE_RX_DMA_FIFO_ACTIVE_MASK 0x00000002 #define BCHP_MISC1_HIF_DMA_STATE_RX_DMA_FIFO_ACTIVE_SHIFT 1 /* MISC1 :: HIF_DMA_STATE :: RX_DMA_ACTIVE [00:00] */ #define BCHP_MISC1_HIF_DMA_STATE_RX_DMA_ACTIVE_MASK 0x00000001 #define BCHP_MISC1_HIF_DMA_STATE_RX_DMA_ACTIVE_SHIFT 0 /*************************************************************************** *DMA_DEBUG_OPTIONS_REG - DMA Debug Options Register ***************************************************************************/ /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_SOFT_RST [31:31] */ #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_MASK 0x80000000 #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_SOFT_RST_SHIFT 31 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_SOFT_RST [30:30] */ #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_MASK 0x40000000 #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_SOFT_RST_SHIFT 30 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST [29:29] */ #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_MASK 0x20000000 #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_TX_DMA_RD_Q_SOFT_RST_SHIFT 29 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST [28:28] */ #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_MASK 0x10000000 #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_RX_DMA_WR_Q_SOFT_RST_SHIFT 28 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_0 [27:05] */ #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_MASK 0x0fffffe0 #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_0_SHIFT 5 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_EN_RX_DMA_XFER_CNT [04:04] */ #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_MASK 0x00000010 #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_EN_RX_DMA_XFER_CNT_SHIFT 4 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_1 [03:03] */ #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_MASK 0x00000008 #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_1_SHIFT 3 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_RD_Q [02:02] */ #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_MASK 0x00000004 #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_RD_Q_SHIFT 2 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: DMA_DEBUG_SINGLE_WR_Q [01:01] */ #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_MASK 0x00000002 #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_DMA_DEBUG_SINGLE_WR_Q_SHIFT 1 /* MISC1 :: DMA_DEBUG_OPTIONS_REG :: RSVD_DMA_DEBUG_2 [00:00] */ #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_MASK 0x00000001 #define BCHP_MISC1_DMA_DEBUG_OPTIONS_REG_RSVD_DMA_DEBUG_2_SHIFT 0 /*************************************************************************** *READ_CHANNEL_ERROR_STATUS - Read Channel Error Status ***************************************************************************/ /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_7 [31:28] */ #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_MASK 0xf0000000 #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_7_SHIFT 28 /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_6 [27:24] */ #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_MASK 0x0f000000 #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_6_SHIFT 24 /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_5 [23:20] */ #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_MASK 0x00f00000 #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_5_SHIFT 20 /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_4 [19:16] */ #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_MASK 0x000f0000 #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_4_SHIFT 16 /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_3 [15:12] */ #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_MASK 0x0000f000 #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_3_SHIFT 12 /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_2 [11:08] */ #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_MASK 0x00000f00 #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_2_SHIFT 8 /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_1 [07:04] */ #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_MASK 0x000000f0 #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_1_SHIFT 4 /* MISC1 :: READ_CHANNEL_ERROR_STATUS :: TX_ERR_STS_CHAN_0 [03:00] */ #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_MASK 0x0000000f #define BCHP_MISC1_READ_CHANNEL_ERROR_STATUS_TX_ERR_STS_CHAN_0_SHIFT 0 /*************************************************************************** *PCIE_DMA_CTRL - PCIE DMA Control Register ***************************************************************************/ /* MISC1 :: PCIE_DMA_CTRL :: reserved0 [31:18] */ #define BCHP_MISC1_PCIE_DMA_CTRL_reserved0_MASK 0xfffc0000 #define BCHP_MISC1_PCIE_DMA_CTRL_reserved0_SHIFT 18 /* MISC1 :: PCIE_DMA_CTRL :: DESC_ENDIAN_MODE [17:16] */ #define BCHP_MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_MASK 0x00030000 #define BCHP_MISC1_PCIE_DMA_CTRL_DESC_ENDIAN_MODE_SHIFT 16 /* MISC1 :: PCIE_DMA_CTRL :: reserved1 [15:09] */ #define BCHP_MISC1_PCIE_DMA_CTRL_reserved1_MASK 0x0000fe00 #define BCHP_MISC1_PCIE_DMA_CTRL_reserved1_SHIFT 9 /* MISC1 :: PCIE_DMA_CTRL :: EN_ROUND_ROBIN [08:08] */ #define BCHP_MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_MASK 0x00000100 #define BCHP_MISC1_PCIE_DMA_CTRL_EN_ROUND_ROBIN_SHIFT 8 /* MISC1 :: PCIE_DMA_CTRL :: reserved2 [07:05] */ #define BCHP_MISC1_PCIE_DMA_CTRL_reserved2_MASK 0x000000e0 #define BCHP_MISC1_PCIE_DMA_CTRL_reserved2_SHIFT 5 /* MISC1 :: PCIE_DMA_CTRL :: RELAXED_ORDERING [04:04] */ #define BCHP_MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_MASK 0x00000010 #define BCHP_MISC1_PCIE_DMA_CTRL_RELAXED_ORDERING_SHIFT 4 /* MISC1 :: PCIE_DMA_CTRL :: NO_SNOOP [03:03] */ #define BCHP_MISC1_PCIE_DMA_CTRL_NO_SNOOP_MASK 0x00000008 #define BCHP_MISC1_PCIE_DMA_CTRL_NO_SNOOP_SHIFT 3 /* MISC1 :: PCIE_DMA_CTRL :: TRAFFIC_CLASS [02:00] */ #define BCHP_MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_MASK 0x00000007 #define BCHP_MISC1_PCIE_DMA_CTRL_TRAFFIC_CLASS_SHIFT 0 /*************************************************************************** *HIF_RXDMA_BASE_ADDR - HIF Rx DMA Base DRAM Address ***************************************************************************/ /* MISC1 :: HIF_RXDMA_BASE_ADDR :: BASE_ADDR [31:00] */ #define BCHP_MISC1_HIF_RXDMA_BASE_ADDR_BASE_ADDR_MASK 0xffffffff #define BCHP_MISC1_HIF_RXDMA_BASE_ADDR_BASE_ADDR_SHIFT 0 /*************************************************************************** *HIF_RXDMA_LENGTH - HIF Rx DMA Transfer Length ***************************************************************************/ /* MISC1 :: HIF_RXDMA_LENGTH :: ACTIVE [31:31] */ #define BCHP_MISC1_HIF_RXDMA_LENGTH_ACTIVE_MASK 0x80000000 #define BCHP_MISC1_HIF_RXDMA_LENGTH_ACTIVE_SHIFT 31 /* MISC1 :: HIF_RXDMA_LENGTH :: reserved0 [30:23] */ #define BCHP_MISC1_HIF_RXDMA_LENGTH_reserved0_MASK 0x7f800000 #define BCHP_MISC1_HIF_RXDMA_LENGTH_reserved0_SHIFT 23 /* MISC1 :: HIF_RXDMA_LENGTH :: LENGTH [22:00] */ #define BCHP_MISC1_HIF_RXDMA_LENGTH_LENGTH_MASK 0x007fffff #define BCHP_MISC1_HIF_RXDMA_LENGTH_LENGTH_SHIFT 0 #endif /* #ifndef BCHP_MISC1_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015100000000000011562 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_cfg.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_c0000644000175000017500000037525011610313111030774 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pcie_cfg.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:12p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:54 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_cfg.h $ * * Hydra_Software_Devel/1 7/17/09 8:12p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PCIE_CFG_H__ #define BCHP_PCIE_CFG_H__ /*************************************************************************** *PCIE_CFG - PCIE Config related registers ***************************************************************************/ #define BCHP_PCIE_CFG_DEVICE_VENDOR_ID 0x00500000 /* DEVICE_VENDOR_ID Register */ #define BCHP_PCIE_CFG_STATUS_COMMAND 0x00500004 /* STATUS_COMMAND Register */ #define BCHP_PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID 0x00500008 /* PCI_CLASSCODE_AND_REVISION_ID Register */ #define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE 0x0050000c /* BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE Register */ #define BCHP_PCIE_CFG_BASE_ADDRESS_1 0x00500010 /* BASE_ADDRESS_1 Register */ #define BCHP_PCIE_CFG_BASE_ADDRESS_2 0x00500014 /* BASE_ADDRESS_2 Register */ #define BCHP_PCIE_CFG_BASE_ADDRESS_3 0x00500018 /* BASE_ADDRESS_3 Register */ #define BCHP_PCIE_CFG_BASE_ADDRESS_4 0x0050001c /* BASE_ADDRESS_4 Register */ #define BCHP_PCIE_CFG_CARDBUS_CIS_POINTER 0x00500028 /* CARDBUS_CIS_POINTER Register */ #define BCHP_PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID 0x0050002c /* SUBSYSTEM_DEVICE_VENDOR_ID Register */ #define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS 0x00500030 /* EXPANSION_ROM_BASE_ADDRESS Register */ #define BCHP_PCIE_CFG_CAPABILITIES_POINTER 0x00500034 /* CAPABILITIES_POINTER Register */ #define BCHP_PCIE_CFG_INTERRUPT 0x0050003c /* INTERRUPT Register */ #define BCHP_PCIE_CFG_VPD_CAPABILITIES 0x00500040 /* VPD_CAPABILITIES Register */ #define BCHP_PCIE_CFG_VPD_DATA 0x00500044 /* VPD_DATA Register */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY 0x00500048 /* POWER_MANAGEMENT_CAPABILITY Register */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS 0x0050004c /* POWER_MANAGEMENT_CONTROL_STATUS Register */ #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER 0x00500050 /* MSI_CAPABILITY_HEADER Register */ #define BCHP_PCIE_CFG_MSI_LOWER_ADDRESS 0x00500054 /* MSI_LOWER_ADDRESS Register */ #define BCHP_PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER 0x00500058 /* MSI_UPPER_ADDRESS_REGISTER Register */ #define BCHP_PCIE_CFG_MSI_DATA 0x0050005c /* MSI_DATA Register */ #define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER 0x00500060 /* BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER Register */ #define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES 0x00500064 /* RESET_COUNTERS_INITIAL_VALUES Register */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL 0x00500068 /* MISCELLANEOUS_HOST_CONTROL Register */ #define BCHP_PCIE_CFG_SPARE 0x0050006c /* SPARE Register */ #define BCHP_PCIE_CFG_PCI_STATE 0x00500070 /* PCI_STATE Register */ #define BCHP_PCIE_CFG_CLOCK_CONTROL 0x00500074 /* CLOCK_CONTROL Register */ #define BCHP_PCIE_CFG_REGISTER_BASE 0x00500078 /* REGISTER_BASE Register */ #define BCHP_PCIE_CFG_MEMORY_BASE 0x0050007c /* MEMORY_BASE Register */ #define BCHP_PCIE_CFG_REGISTER_DATA 0x00500080 /* REGISTER_DATA Register */ #define BCHP_PCIE_CFG_MEMORY_DATA 0x00500084 /* MEMORY_DATA Register */ #define BCHP_PCIE_CFG_EXPANSION_ROM_BAR_SIZE 0x00500088 /* EXPANSION_ROM_BAR_SIZE Register */ #define BCHP_PCIE_CFG_EXPANSION_ROM_ADDRESS 0x0050008c /* EXPANSION_ROM_ADDRESS Register */ #define BCHP_PCIE_CFG_EXPANSION_ROM_DATA 0x00500090 /* EXPANSION_ROM_DATA Register */ #define BCHP_PCIE_CFG_VPD_INTERFACE 0x00500094 /* VPD_INTERFACE Register */ #define BCHP_PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER 0x00500098 /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER Register */ #define BCHP_PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER 0x0050009c /* UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER Register */ #define BCHP_PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER 0x005000a0 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER Register */ #define BCHP_PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER 0x005000a4 /* UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER Register */ #define BCHP_PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER 0x005000a8 /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER Register */ #define BCHP_PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER 0x005000ac /* UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER Register */ #define BCHP_PCIE_CFG_INT_MAILBOX_UPPER 0x005000b0 /* INT_MAILBOX_UPPER Register */ #define BCHP_PCIE_CFG_INT_MAILBOX_LOWER 0x005000b4 /* INT_MAILBOX_LOWER Register */ #define BCHP_PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION 0x005000bc /* PRODUCT_ID_AND_ASIC_REVISION Register */ #define BCHP_PCIE_CFG_FUNCTION_EVENT 0x005000c0 /* FUNCTION_EVENT Register */ #define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK 0x005000c4 /* FUNCTION_EVENT_MASK Register */ #define BCHP_PCIE_CFG_FUNCTION_PRESENT 0x005000c8 /* FUNCTION_PRESENT Register */ #define BCHP_PCIE_CFG_PCIE_CAPABILITIES 0x005000cc /* PCIE_CAPABILITIES Register */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES 0x005000d0 /* DEVICE_CAPABILITIES Register */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL 0x005000d4 /* DEVICE_STATUS_CONTROL Register */ #define BCHP_PCIE_CFG_LINK_CAPABILITY 0x005000d8 /* LINK_CAPABILITY Register */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL 0x005000dc /* LINK_STATUS_CONTROL Register */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_2 0x005000f0 /* DEVICE_CAPABILITIES_2 Register */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_2 0x005000f4 /* DEVICE_STATUS_CONTROL_2 Register */ #define BCHP_PCIE_CFG_LINK_CAPABILITIES_2 0x005000f8 /* LINK_CAPABILITIES_2 Register */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_2 0x005000fc /* LINK_STATUS_CONTROL_2 Register */ #define BCHP_PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER 0x00500100 /* ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER Register */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS 0x00500104 /* UNCORRECTABLE_ERROR_STATUS Register */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK 0x00500108 /* UNCORRECTABLE_ERROR_MASK Register */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY 0x0050010c /* UNCORRECTABLE_ERROR_SEVERITY Register */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS 0x00500110 /* CORRECTABLE_ERROR_STATUS Register */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK 0x00500114 /* CORRECTABLE_ERROR_MASK Register */ #define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL 0x00500118 /* ADVANCED_ERROR_CAPABILITIES_AND_CONTROL Register */ #define BCHP_PCIE_CFG_HEADER_LOG_1 0x0050011c /* HEADER_LOG_1 Register */ #define BCHP_PCIE_CFG_HEADER_LOG_2 0x00500120 /* HEADER_LOG_2 Register */ #define BCHP_PCIE_CFG_HEADER_LOG_3 0x00500124 /* HEADER_LOG_3 Register */ #define BCHP_PCIE_CFG_HEADER_LOG_4 0x00500128 /* HEADER_LOG_4 Register */ #define BCHP_PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER 0x0050013c /* VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER Register */ #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY 0x00500140 /* PORT_VC_CAPABILITY Register */ #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_2 0x00500144 /* PORT_VC_CAPABILITY_2 Register */ #define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL 0x00500148 /* PORT_VC_STATUS_CONTROL Register */ #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY 0x0050014c /* VC_RESOURCE_CAPABILITY Register */ #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL 0x00500150 /* VC_RESOURCE_CONTROL Register */ #define BCHP_PCIE_CFG_VC_RESOURCE_STATUS 0x00500154 /* VC_RESOURCE_STATUS Register */ #define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER 0x00500160 /* DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER Register */ #define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW 0x00500164 /* DEVICE_SERIAL_NO_LOWER_DW Register */ #define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW 0x00500168 /* DEVICE_SERIAL_NO_UPPER_DW Register */ #define BCHP_PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER 0x0050016c /* POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER Register */ #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_SELECT 0x00500170 /* POWER_BUDGETING_DATA_SELECT Register */ #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA 0x00500174 /* POWER_BUDGETING_DATA Register */ #define BCHP_PCIE_CFG_POWER_BUDGETING_CAPABILITY 0x00500178 /* POWER_BUDGETING_CAPABILITY Register */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1 0x0050017c /* FIRMWARE_POWER_BUDGETING_2_1 Register */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3 0x00500180 /* FIRMWARE_POWER_BUDGETING_4_3 Register */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5 0x00500184 /* FIRMWARE_POWER_BUDGETING_6_5 Register */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7 0x00500188 /* FIRMWARE_POWER_BUDGETING_8_7 Register */ #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING 0x0050018c /* PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING Register */ /*************************************************************************** *DEVICE_VENDOR_ID - DEVICE_VENDOR_ID Register ***************************************************************************/ /* PCIE_CFG :: DEVICE_VENDOR_ID :: DEVICE_ID [31:16] */ #define BCHP_PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_MASK 0xffff0000 #define BCHP_PCIE_CFG_DEVICE_VENDOR_ID_DEVICE_ID_SHIFT 16 /* PCIE_CFG :: DEVICE_VENDOR_ID :: VENDOR_ID [15:00] */ #define BCHP_PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_MASK 0x0000ffff #define BCHP_PCIE_CFG_DEVICE_VENDOR_ID_VENDOR_ID_SHIFT 0 /*************************************************************************** *STATUS_COMMAND - STATUS_COMMAND Register ***************************************************************************/ /* PCIE_CFG :: STATUS_COMMAND :: DETECTED_PARITY_ERROR [31:31] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_MASK 0x80000000 #define BCHP_PCIE_CFG_STATUS_COMMAND_DETECTED_PARITY_ERROR_SHIFT 31 /* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_SYSTEM_ERROR [30:30] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_MASK 0x40000000 #define BCHP_PCIE_CFG_STATUS_COMMAND_SIGNALED_SYSTEM_ERROR_SHIFT 30 /* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_MASTER_ABORT [29:29] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_MASK 0x20000000 #define BCHP_PCIE_CFG_STATUS_COMMAND_RECEIVED_MASTER_ABORT_SHIFT 29 /* PCIE_CFG :: STATUS_COMMAND :: RECEIVED_TARGET_ABORT [28:28] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_MASK 0x10000000 #define BCHP_PCIE_CFG_STATUS_COMMAND_RECEIVED_TARGET_ABORT_SHIFT 28 /* PCIE_CFG :: STATUS_COMMAND :: SIGNALED_TARGET_ABORT [27:27] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_MASK 0x08000000 #define BCHP_PCIE_CFG_STATUS_COMMAND_SIGNALED_TARGET_ABORT_SHIFT 27 /* PCIE_CFG :: STATUS_COMMAND :: DEVSEL_TIMING [26:25] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_MASK 0x06000000 #define BCHP_PCIE_CFG_STATUS_COMMAND_DEVSEL_TIMING_SHIFT 25 /* PCIE_CFG :: STATUS_COMMAND :: MASTER_DATA_PARITY_ERROR [24:24] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_MASK 0x01000000 #define BCHP_PCIE_CFG_STATUS_COMMAND_MASTER_DATA_PARITY_ERROR_SHIFT 24 /* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_CAPABLE [23:23] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_MASK 0x00800000 #define BCHP_PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_CAPABLE_SHIFT 23 /* PCIE_CFG :: STATUS_COMMAND :: RESERVED_0 [22:22] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_RESERVED_0_MASK 0x00400000 #define BCHP_PCIE_CFG_STATUS_COMMAND_RESERVED_0_SHIFT 22 /* PCIE_CFG :: STATUS_COMMAND :: CAPABLE_66MHZ [21:21] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_MASK 0x00200000 #define BCHP_PCIE_CFG_STATUS_COMMAND_CAPABLE_66MHZ_SHIFT 21 /* PCIE_CFG :: STATUS_COMMAND :: CAPABILITIES_LIST [20:20] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_MASK 0x00100000 #define BCHP_PCIE_CFG_STATUS_COMMAND_CAPABILITIES_LIST_SHIFT 20 /* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_STATUS [19:19] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_MASK 0x00080000 #define BCHP_PCIE_CFG_STATUS_COMMAND_INTERRUPT_STATUS_SHIFT 19 /* PCIE_CFG :: STATUS_COMMAND :: RESERVED_1 [18:16] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_RESERVED_1_MASK 0x00070000 #define BCHP_PCIE_CFG_STATUS_COMMAND_RESERVED_1_SHIFT 16 /* PCIE_CFG :: STATUS_COMMAND :: RESERVED_2 [15:11] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_RESERVED_2_MASK 0x0000f800 #define BCHP_PCIE_CFG_STATUS_COMMAND_RESERVED_2_SHIFT 11 /* PCIE_CFG :: STATUS_COMMAND :: INTERRUPT_DISABLE [10:10] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_MASK 0x00000400 #define BCHP_PCIE_CFG_STATUS_COMMAND_INTERRUPT_DISABLE_SHIFT 10 /* PCIE_CFG :: STATUS_COMMAND :: FAST_BACK_TO_BACK_ENABLE [09:09] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_MASK 0x00000200 #define BCHP_PCIE_CFG_STATUS_COMMAND_FAST_BACK_TO_BACK_ENABLE_SHIFT 9 /* PCIE_CFG :: STATUS_COMMAND :: SYSTEM_ERROR_ENABLE [08:08] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_MASK 0x00000100 #define BCHP_PCIE_CFG_STATUS_COMMAND_SYSTEM_ERROR_ENABLE_SHIFT 8 /* PCIE_CFG :: STATUS_COMMAND :: STEPPING_CONTROL [07:07] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_MASK 0x00000080 #define BCHP_PCIE_CFG_STATUS_COMMAND_STEPPING_CONTROL_SHIFT 7 /* PCIE_CFG :: STATUS_COMMAND :: PARITY_ERROR_ENABLE [06:06] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_MASK 0x00000040 #define BCHP_PCIE_CFG_STATUS_COMMAND_PARITY_ERROR_ENABLE_SHIFT 6 /* PCIE_CFG :: STATUS_COMMAND :: VGA_PALETTE_SNOOP [05:05] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_MASK 0x00000020 #define BCHP_PCIE_CFG_STATUS_COMMAND_VGA_PALETTE_SNOOP_SHIFT 5 /* PCIE_CFG :: STATUS_COMMAND :: MEMORY_WRITE_AND_INVALIDATE [04:04] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_MASK 0x00000010 #define BCHP_PCIE_CFG_STATUS_COMMAND_MEMORY_WRITE_AND_INVALIDATE_SHIFT 4 /* PCIE_CFG :: STATUS_COMMAND :: SPECIAL_CYCLES [03:03] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_MASK 0x00000008 #define BCHP_PCIE_CFG_STATUS_COMMAND_SPECIAL_CYCLES_SHIFT 3 /* PCIE_CFG :: STATUS_COMMAND :: BUS_MASTER [02:02] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_BUS_MASTER_MASK 0x00000004 #define BCHP_PCIE_CFG_STATUS_COMMAND_BUS_MASTER_SHIFT 2 /* PCIE_CFG :: STATUS_COMMAND :: MEMORY_SPACE [01:01] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_MASK 0x00000002 #define BCHP_PCIE_CFG_STATUS_COMMAND_MEMORY_SPACE_SHIFT 1 /* PCIE_CFG :: STATUS_COMMAND :: I_O_SPACE [00:00] */ #define BCHP_PCIE_CFG_STATUS_COMMAND_I_O_SPACE_MASK 0x00000001 #define BCHP_PCIE_CFG_STATUS_COMMAND_I_O_SPACE_SHIFT 0 /*************************************************************************** *PCI_CLASSCODE_AND_REVISION_ID - PCI_CLASSCODE_AND_REVISION_ID Register ***************************************************************************/ /* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: PCI_CLASSCODE [31:08] */ #define BCHP_PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_MASK 0xffffff00 #define BCHP_PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_PCI_CLASSCODE_SHIFT 8 /* PCIE_CFG :: PCI_CLASSCODE_AND_REVISION_ID :: REVISION_ID [07:00] */ #define BCHP_PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_MASK 0x000000ff #define BCHP_PCIE_CFG_PCI_CLASSCODE_AND_REVISION_ID_REVISION_ID_SHIFT 0 /*************************************************************************** *BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE - BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE Register ***************************************************************************/ /* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: BIST [31:24] */ #define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_MASK 0xff000000 #define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_BIST_SHIFT 24 /* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: HEADER_TYPE [23:16] */ #define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_MASK 0x00ff0000 #define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_HEADER_TYPE_SHIFT 16 /* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: LATENCY_TIMER [15:08] */ #define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_MASK 0x0000ff00 #define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_LATENCY_TIMER_SHIFT 8 /* PCIE_CFG :: BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE :: CACHE_LINE_SIZE [07:00] */ #define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_MASK 0x000000ff #define BCHP_PCIE_CFG_BIST_HEADER_TYPE_LATENCY_TIMER_CACHE_LINE_SIZE_CACHE_LINE_SIZE_SHIFT 0 /*************************************************************************** *BASE_ADDRESS_1 - BASE_ADDRESS_1 Register ***************************************************************************/ /* PCIE_CFG :: BASE_ADDRESS_1 :: BASE_ADDRESS [31:16] */ #define BCHP_PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_MASK 0xffff0000 #define BCHP_PCIE_CFG_BASE_ADDRESS_1_BASE_ADDRESS_SHIFT 16 /* PCIE_CFG :: BASE_ADDRESS_1 :: RESERVED_0 [15:04] */ #define BCHP_PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_MASK 0x0000fff0 #define BCHP_PCIE_CFG_BASE_ADDRESS_1_RESERVED_0_SHIFT 4 /* PCIE_CFG :: BASE_ADDRESS_1 :: PREFETCHABLE [03:03] */ #define BCHP_PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_MASK 0x00000008 #define BCHP_PCIE_CFG_BASE_ADDRESS_1_PREFETCHABLE_SHIFT 3 /* PCIE_CFG :: BASE_ADDRESS_1 :: TYPE [02:01] */ #define BCHP_PCIE_CFG_BASE_ADDRESS_1_TYPE_MASK 0x00000006 #define BCHP_PCIE_CFG_BASE_ADDRESS_1_TYPE_SHIFT 1 /* PCIE_CFG :: BASE_ADDRESS_1 :: MEMORY_SPACE_INDICATOR [00:00] */ #define BCHP_PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_MASK 0x00000001 #define BCHP_PCIE_CFG_BASE_ADDRESS_1_MEMORY_SPACE_INDICATOR_SHIFT 0 /*************************************************************************** *BASE_ADDRESS_2 - BASE_ADDRESS_2 Register ***************************************************************************/ /* PCIE_CFG :: BASE_ADDRESS_2 :: EXTENDED_BASE_ADDRESS [31:00] */ #define BCHP_PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_MASK 0xffffffff #define BCHP_PCIE_CFG_BASE_ADDRESS_2_EXTENDED_BASE_ADDRESS_SHIFT 0 /*************************************************************************** *BASE_ADDRESS_3 - BASE_ADDRESS_3 Register ***************************************************************************/ /* PCIE_CFG :: BASE_ADDRESS_3 :: BASE_ADDRESS [31:16] */ #define BCHP_PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_MASK 0xffff0000 #define BCHP_PCIE_CFG_BASE_ADDRESS_3_BASE_ADDRESS_SHIFT 16 /* PCIE_CFG :: BASE_ADDRESS_3 :: RESERVED_0 [15:04] */ #define BCHP_PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_MASK 0x0000fff0 #define BCHP_PCIE_CFG_BASE_ADDRESS_3_RESERVED_0_SHIFT 4 /* PCIE_CFG :: BASE_ADDRESS_3 :: PREFETCHABLE [03:03] */ #define BCHP_PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_MASK 0x00000008 #define BCHP_PCIE_CFG_BASE_ADDRESS_3_PREFETCHABLE_SHIFT 3 /* PCIE_CFG :: BASE_ADDRESS_3 :: TYPE [02:01] */ #define BCHP_PCIE_CFG_BASE_ADDRESS_3_TYPE_MASK 0x00000006 #define BCHP_PCIE_CFG_BASE_ADDRESS_3_TYPE_SHIFT 1 /* PCIE_CFG :: BASE_ADDRESS_3 :: MEMORY_SPACE_INDICATOR [00:00] */ #define BCHP_PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_MASK 0x00000001 #define BCHP_PCIE_CFG_BASE_ADDRESS_3_MEMORY_SPACE_INDICATOR_SHIFT 0 /*************************************************************************** *BASE_ADDRESS_4 - BASE_ADDRESS_4 Register ***************************************************************************/ /* PCIE_CFG :: BASE_ADDRESS_4 :: EXTENDED_BASE_ADDRESS [31:00] */ #define BCHP_PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_MASK 0xffffffff #define BCHP_PCIE_CFG_BASE_ADDRESS_4_EXTENDED_BASE_ADDRESS_SHIFT 0 /*************************************************************************** *CARDBUS_CIS_POINTER - CARDBUS_CIS_POINTER Register ***************************************************************************/ /* PCIE_CFG :: CARDBUS_CIS_POINTER :: CARDBUS_CIS_POINTER [31:00] */ #define BCHP_PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_MASK 0xffffffff #define BCHP_PCIE_CFG_CARDBUS_CIS_POINTER_CARDBUS_CIS_POINTER_SHIFT 0 /*************************************************************************** *SUBSYSTEM_DEVICE_VENDOR_ID - SUBSYSTEM_DEVICE_VENDOR_ID Register ***************************************************************************/ /* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_DEVICE_ID [31:16] */ #define BCHP_PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_MASK 0xffff0000 #define BCHP_PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_DEVICE_ID_SHIFT 16 /* PCIE_CFG :: SUBSYSTEM_DEVICE_VENDOR_ID :: SUBSYSTEM_VENDOR_ID [15:00] */ #define BCHP_PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_MASK 0x0000ffff #define BCHP_PCIE_CFG_SUBSYSTEM_DEVICE_VENDOR_ID_SUBSYSTEM_VENDOR_ID_SHIFT 0 /*************************************************************************** *EXPANSION_ROM_BASE_ADDRESS - EXPANSION_ROM_BASE_ADDRESS Register ***************************************************************************/ /* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_BASE_ADDRESS [31:16] */ #define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_MASK 0xffff0000 #define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_BASE_ADDRESS_SHIFT 16 /* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: ROM_SIZE_INDICATION [15:11] */ #define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_MASK 0x0000f800 #define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_ROM_SIZE_INDICATION_SHIFT 11 /* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: RESERVED_0 [10:01] */ #define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_MASK 0x000007fe #define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_RESERVED_0_SHIFT 1 /* PCIE_CFG :: EXPANSION_ROM_BASE_ADDRESS :: EXPANSION_ROM_ENABLE [00:00] */ #define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_MASK 0x00000001 #define BCHP_PCIE_CFG_EXPANSION_ROM_BASE_ADDRESS_EXPANSION_ROM_ENABLE_SHIFT 0 /*************************************************************************** *CAPABILITIES_POINTER - CAPABILITIES_POINTER Register ***************************************************************************/ /* PCIE_CFG :: CAPABILITIES_POINTER :: CAPABILITIES_POINTER [31:00] */ #define BCHP_PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_MASK 0xffffffff #define BCHP_PCIE_CFG_CAPABILITIES_POINTER_CAPABILITIES_POINTER_SHIFT 0 /*************************************************************************** *INTERRUPT - INTERRUPT Register ***************************************************************************/ /* PCIE_CFG :: INTERRUPT :: RESERVED_0 [31:16] */ #define BCHP_PCIE_CFG_INTERRUPT_RESERVED_0_MASK 0xffff0000 #define BCHP_PCIE_CFG_INTERRUPT_RESERVED_0_SHIFT 16 /* PCIE_CFG :: INTERRUPT :: INTERRUPT_PIN [15:08] */ #define BCHP_PCIE_CFG_INTERRUPT_INTERRUPT_PIN_MASK 0x0000ff00 #define BCHP_PCIE_CFG_INTERRUPT_INTERRUPT_PIN_SHIFT 8 /* PCIE_CFG :: INTERRUPT :: INTERRUPT_LINE [07:00] */ #define BCHP_PCIE_CFG_INTERRUPT_INTERRUPT_LINE_MASK 0x000000ff #define BCHP_PCIE_CFG_INTERRUPT_INTERRUPT_LINE_SHIFT 0 /*************************************************************************** *VPD_CAPABILITIES - VPD_CAPABILITIES Register ***************************************************************************/ /* PCIE_CFG :: VPD_CAPABILITIES :: RESERVED_0 [31:00] */ #define BCHP_PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_MASK 0xffffffff #define BCHP_PCIE_CFG_VPD_CAPABILITIES_RESERVED_0_SHIFT 0 /*************************************************************************** *VPD_DATA - VPD_DATA Register ***************************************************************************/ /* PCIE_CFG :: VPD_DATA :: RESERVED_0 [31:00] */ #define BCHP_PCIE_CFG_VPD_DATA_RESERVED_0_MASK 0xffffffff #define BCHP_PCIE_CFG_VPD_DATA_RESERVED_0_SHIFT 0 /*************************************************************************** *POWER_MANAGEMENT_CAPABILITY - POWER_MANAGEMENT_CAPABILITY Register ***************************************************************************/ /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_SUPPORT [31:27] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_MASK 0xf8000000 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_SUPPORT_SHIFT 27 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D2_SUPPORT [26:26] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_MASK 0x04000000 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D2_SUPPORT_SHIFT 26 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: D1_SUPPORT [25:25] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_MASK 0x02000000 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_D1_SUPPORT_SHIFT 25 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: AUX_CURRENT [24:22] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_MASK 0x01c00000 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_AUX_CURRENT_SHIFT 22 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: DSI [21:21] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_MASK 0x00200000 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_DSI_SHIFT 21 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: RESERVED_0 [20:20] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_MASK 0x00100000 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_RESERVED_0_SHIFT 20 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: PME_CLOCK [19:19] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_MASK 0x00080000 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_PME_CLOCK_SHIFT 19 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: VERSION [18:16] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_MASK 0x00070000 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_VERSION_SHIFT 16 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: NEXT_POINTER [15:08] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_MASK 0x0000ff00 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_NEXT_POINTER_SHIFT 8 /* PCIE_CFG :: POWER_MANAGEMENT_CAPABILITY :: CAPABILITY_ID [07:00] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_MASK 0x000000ff #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CAPABILITY_CAPABILITY_ID_SHIFT 0 /*************************************************************************** *POWER_MANAGEMENT_CONTROL_STATUS - POWER_MANAGEMENT_CONTROL_STATUS Register ***************************************************************************/ /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PM_DATA [31:24] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_MASK 0xff000000 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PM_DATA_SHIFT 24 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_0 [23:16] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_MASK 0x00ff0000 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_0_SHIFT 16 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_STATUS [15:15] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_MASK 0x00008000 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_STATUS_SHIFT 15 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SCALE [14:13] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_MASK 0x00006000 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SCALE_SHIFT 13 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: DATA_SELECT [12:09] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_MASK 0x00001e00 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_DATA_SELECT_SHIFT 9 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: PME_ENABLE [08:08] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_MASK 0x00000100 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_PME_ENABLE_SHIFT 8 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_1 [07:04] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_MASK 0x000000f0 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_1_SHIFT 4 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: NO_SOFT_RESET [03:03] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_MASK 0x00000008 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_NO_SOFT_RESET_SHIFT 3 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: RESERVED_2 [02:02] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_MASK 0x00000004 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_RESERVED_2_SHIFT 2 /* PCIE_CFG :: POWER_MANAGEMENT_CONTROL_STATUS :: POWER_STATE [01:00] */ #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_MASK 0x00000003 #define BCHP_PCIE_CFG_POWER_MANAGEMENT_CONTROL_STATUS_POWER_STATE_SHIFT 0 /*************************************************************************** *MSI_CAPABILITY_HEADER - MSI_CAPABILITY_HEADER Register ***************************************************************************/ /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_CONTROL [31:24] */ #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_MASK 0xff000000 #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_CONTROL_SHIFT 24 /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: ADDRESS_CAPABLE_64_BIT [23:23] */ #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_MASK 0x00800000 #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_ADDRESS_CAPABLE_64_BIT_SHIFT 23 /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_ENABLE [22:20] */ #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_MASK 0x00700000 #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_ENABLE_SHIFT 20 /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MULTIPLE_MESSAGE_CAPABLE [19:17] */ #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_MASK 0x000e0000 #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MULTIPLE_MESSAGE_CAPABLE_SHIFT 17 /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: MSI_ENABLE [16:16] */ #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_MASK 0x00010000 #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_MSI_ENABLE_SHIFT 16 /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 /* PCIE_CFG :: MSI_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff #define BCHP_PCIE_CFG_MSI_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 /*************************************************************************** *MSI_LOWER_ADDRESS - MSI_LOWER_ADDRESS Register ***************************************************************************/ /* PCIE_CFG :: MSI_LOWER_ADDRESS :: MSI_LOWER_ADDRESS [31:02] */ #define BCHP_PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_MASK 0xfffffffc #define BCHP_PCIE_CFG_MSI_LOWER_ADDRESS_MSI_LOWER_ADDRESS_SHIFT 2 /* PCIE_CFG :: MSI_LOWER_ADDRESS :: RESERVED_0 [01:00] */ #define BCHP_PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_MASK 0x00000003 #define BCHP_PCIE_CFG_MSI_LOWER_ADDRESS_RESERVED_0_SHIFT 0 /*************************************************************************** *MSI_UPPER_ADDRESS_REGISTER - MSI_UPPER_ADDRESS_REGISTER Register ***************************************************************************/ /* PCIE_CFG :: MSI_UPPER_ADDRESS_REGISTER :: MSI_UPPER_ADDRESS [31:00] */ #define BCHP_PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_MASK 0xffffffff #define BCHP_PCIE_CFG_MSI_UPPER_ADDRESS_REGISTER_MSI_UPPER_ADDRESS_SHIFT 0 /*************************************************************************** *MSI_DATA - MSI_DATA Register ***************************************************************************/ /* PCIE_CFG :: MSI_DATA :: RESERVED_0 [31:16] */ #define BCHP_PCIE_CFG_MSI_DATA_RESERVED_0_MASK 0xffff0000 #define BCHP_PCIE_CFG_MSI_DATA_RESERVED_0_SHIFT 16 /* PCIE_CFG :: MSI_DATA :: MSI_DATA [15:00] */ #define BCHP_PCIE_CFG_MSI_DATA_MSI_DATA_MASK 0x0000ffff #define BCHP_PCIE_CFG_MSI_DATA_MSI_DATA_SHIFT 0 /*************************************************************************** *BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER - BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER Register ***************************************************************************/ /* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: RESERVED_0 [31:24] */ #define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_MASK 0xff000000 #define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_RESERVED_0_SHIFT 24 /* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: VENDOR_SPECIFIC_CAPABILITY_LENGTH [23:16] */ #define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_MASK 0x00ff0000 #define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_VENDOR_SPECIFIC_CAPABILITY_LENGTH_SHIFT 16 /* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: NEXT_POINTER [15:08] */ #define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_MASK 0x0000ff00 #define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_NEXT_POINTER_SHIFT 8 /* PCIE_CFG :: BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER :: CAPABILITY_ID [07:00] */ #define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_MASK 0x000000ff #define BCHP_PCIE_CFG_BROADCOM_VENDOR_SPECIFIC_CAPABILITY_HEADER_CAPABILITY_ID_SHIFT 0 /*************************************************************************** *RESET_COUNTERS_INITIAL_VALUES - RESET_COUNTERS_INITIAL_VALUES Register ***************************************************************************/ /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: POR_RESET_COUNTER [31:28] */ #define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_MASK 0xf0000000 #define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_POR_RESET_COUNTER_SHIFT 28 /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: HOT_RESET_COUNTER [27:24] */ #define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_MASK 0x0f000000 #define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_HOT_RESET_COUNTER_SHIFT 24 /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: GRC_RESET_COUNTER [23:16] */ #define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_MASK 0x00ff0000 #define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_GRC_RESET_COUNTER_SHIFT 16 /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: PERST_RESET_COUNTER [15:08] */ #define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_MASK 0x0000ff00 #define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_PERST_RESET_COUNTER_SHIFT 8 /* PCIE_CFG :: RESET_COUNTERS_INITIAL_VALUES :: LINKDOWN_RESET_COUNTER [07:00] */ #define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_MASK 0x000000ff #define BCHP_PCIE_CFG_RESET_COUNTERS_INITIAL_VALUES_LINKDOWN_RESET_COUNTER_SHIFT 0 /*************************************************************************** *MISCELLANEOUS_HOST_CONTROL - MISCELLANEOUS_HOST_CONTROL Register ***************************************************************************/ /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: PRODUCT_ID [31:24] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_MASK 0xff000000 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_PRODUCT_ID_SHIFT 24 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ASIC_REVISION_ID [23:16] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_MASK 0x00ff0000 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ASIC_REVISION_ID_SHIFT 16 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TLP_MINOR_ERROR_TOLERANCE [15:15] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_MASK 0x00008000 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TLP_MINOR_ERROR_TOLERANCE_SHIFT 15 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: LOG_HEADER_OVERFLOW [14:14] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_MASK 0x00004000 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_LOG_HEADER_OVERFLOW_SHIFT 14 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: BOUNDARY_CHECK [13:13] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_MASK 0x00002000 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BOUNDARY_CHECK_SHIFT 13 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: BYTE_ENABLE_RULE_CHECK [12:12] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_MASK 0x00001000 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_BYTE_ENABLE_RULE_CHECK_SHIFT 12 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: INTERRUPT_CHECK [11:11] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_MASK 0x00000800 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_INTERRUPT_CHECK_SHIFT 11 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: RCB_CHECK [10:10] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_MASK 0x00000400 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_RCB_CHECK_SHIFT 10 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_TAGGED_STATUS_MODE [09:09] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_MASK 0x00000200 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_TAGGED_STATUS_MODE_SHIFT 9 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: MASK_INTERRUPT_MODE [08:08] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_MASK 0x00000100 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MODE_SHIFT 8 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_INDIRECT_ACCESS [07:07] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_MASK 0x00000080 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_INDIRECT_ACCESS_SHIFT 7 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_REGISTER_WORD_SWAP [06:06] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_MASK 0x00000040 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_REGISTER_WORD_SWAP_SHIFT 6 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY [05:05] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_MASK 0x00000020 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_CLOCK_CONTROL_REGISTER_READ_WRITE_CAPABILITY_SHIFT 5 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY [04:04] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_MASK 0x00000010 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_PCI_STATE_REGISTER_READ_WRITE_CAPABILITY_SHIFT 4 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_ENDIAN_WORD_SWAP [03:03] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_MASK 0x00000008 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_WORD_SWAP_SHIFT 3 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: ENABLE_ENDIAN_BYTE_SWAP [02:02] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_MASK 0x00000004 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_ENABLE_ENDIAN_BYTE_SWAP_SHIFT 2 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: MASK_INTERRUPT [01:01] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_MASK 0x00000002 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_MASK_INTERRUPT_SHIFT 1 /* PCIE_CFG :: MISCELLANEOUS_HOST_CONTROL :: CLEAR_INTERRUPT [00:00] */ #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_MASK 0x00000001 #define BCHP_PCIE_CFG_MISCELLANEOUS_HOST_CONTROL_CLEAR_INTERRUPT_SHIFT 0 /*************************************************************************** *SPARE - SPARE Register ***************************************************************************/ /* PCIE_CFG :: SPARE :: UNUSED_0 [31:16] */ #define BCHP_PCIE_CFG_SPARE_UNUSED_0_MASK 0xffff0000 #define BCHP_PCIE_CFG_SPARE_UNUSED_0_SHIFT 16 /* PCIE_CFG :: SPARE :: RESERVED_0 [15:15] */ #define BCHP_PCIE_CFG_SPARE_RESERVED_0_MASK 0x00008000 #define BCHP_PCIE_CFG_SPARE_RESERVED_0_SHIFT 15 /* PCIE_CFG :: SPARE :: UNUSED_1 [14:02] */ #define BCHP_PCIE_CFG_SPARE_UNUSED_1_MASK 0x00007ffc #define BCHP_PCIE_CFG_SPARE_UNUSED_1_SHIFT 2 /* PCIE_CFG :: SPARE :: BAR2_TARGET_WORD_SWAP [01:01] */ #define BCHP_PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_MASK 0x00000002 #define BCHP_PCIE_CFG_SPARE_BAR2_TARGET_WORD_SWAP_SHIFT 1 /* PCIE_CFG :: SPARE :: BAR2_TARGET_BYTE_SWAP [00:00] */ #define BCHP_PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_MASK 0x00000001 #define BCHP_PCIE_CFG_SPARE_BAR2_TARGET_BYTE_SWAP_SHIFT 0 /*************************************************************************** *PCI_STATE - PCI_STATE Register ***************************************************************************/ /* PCIE_CFG :: PCI_STATE :: RESERVED_0 [31:16] */ #define BCHP_PCIE_CFG_PCI_STATE_RESERVED_0_MASK 0xffff0000 #define BCHP_PCIE_CFG_PCI_STATE_RESERVED_0_SHIFT 16 /* PCIE_CFG :: PCI_STATE :: CONFIG_RETRY [15:15] */ #define BCHP_PCIE_CFG_PCI_STATE_CONFIG_RETRY_MASK 0x00008000 #define BCHP_PCIE_CFG_PCI_STATE_CONFIG_RETRY_SHIFT 15 /* PCIE_CFG :: PCI_STATE :: RESERVED_1 [14:12] */ #define BCHP_PCIE_CFG_PCI_STATE_RESERVED_1_MASK 0x00007000 #define BCHP_PCIE_CFG_PCI_STATE_RESERVED_1_SHIFT 12 /* PCIE_CFG :: PCI_STATE :: MAX_PCI_TARGET_RETRY [11:09] */ #define BCHP_PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_MASK 0x00000e00 #define BCHP_PCIE_CFG_PCI_STATE_MAX_PCI_TARGET_RETRY_SHIFT 9 /* PCIE_CFG :: PCI_STATE :: FLAT_VIEW [08:08] */ #define BCHP_PCIE_CFG_PCI_STATE_FLAT_VIEW_MASK 0x00000100 #define BCHP_PCIE_CFG_PCI_STATE_FLAT_VIEW_SHIFT 8 /* PCIE_CFG :: PCI_STATE :: VPD_AVAILABLE [07:07] */ #define BCHP_PCIE_CFG_PCI_STATE_VPD_AVAILABLE_MASK 0x00000080 #define BCHP_PCIE_CFG_PCI_STATE_VPD_AVAILABLE_SHIFT 7 /* PCIE_CFG :: PCI_STATE :: PCI_EXPANSION_ROM_RETRY [06:06] */ #define BCHP_PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_MASK 0x00000040 #define BCHP_PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_RETRY_SHIFT 6 /* PCIE_CFG :: PCI_STATE :: PCI_EXPANSION_ROM_DESIRED [05:05] */ #define BCHP_PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_MASK 0x00000020 #define BCHP_PCIE_CFG_PCI_STATE_PCI_EXPANSION_ROM_DESIRED_SHIFT 5 /* PCIE_CFG :: PCI_STATE :: RESERVED_2 [04:00] */ #define BCHP_PCIE_CFG_PCI_STATE_RESERVED_2_MASK 0x0000001f #define BCHP_PCIE_CFG_PCI_STATE_RESERVED_2_SHIFT 0 /*************************************************************************** *CLOCK_CONTROL - CLOCK_CONTROL Register ***************************************************************************/ /* PCIE_CFG :: CLOCK_CONTROL :: PL_CLOCK_DISABLE [31:31] */ #define BCHP_PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_MASK 0x80000000 #define BCHP_PCIE_CFG_CLOCK_CONTROL_PL_CLOCK_DISABLE_SHIFT 31 /* PCIE_CFG :: CLOCK_CONTROL :: DLL_CLOCK_DISABLE [30:30] */ #define BCHP_PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_MASK 0x40000000 #define BCHP_PCIE_CFG_CLOCK_CONTROL_DLL_CLOCK_DISABLE_SHIFT 30 /* PCIE_CFG :: CLOCK_CONTROL :: TL_CLOCK_DISABLE [29:29] */ #define BCHP_PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_MASK 0x20000000 #define BCHP_PCIE_CFG_CLOCK_CONTROL_TL_CLOCK_DISABLE_SHIFT 29 /* PCIE_CFG :: CLOCK_CONTROL :: PCI_EXPRESS_CLOCK_TO_CORE_CLOCK [28:28] */ #define BCHP_PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_MASK 0x10000000 #define BCHP_PCIE_CFG_CLOCK_CONTROL_PCI_EXPRESS_CLOCK_TO_CORE_CLOCK_SHIFT 28 /* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_0 [27:21] */ #define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_0_MASK 0x0fe00000 #define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_0_SHIFT 21 /* PCIE_CFG :: CLOCK_CONTROL :: SELECT_FINAL_ALT_CLOCK_SOURCE [20:20] */ #define BCHP_PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_MASK 0x00100000 #define BCHP_PCIE_CFG_CLOCK_CONTROL_SELECT_FINAL_ALT_CLOCK_SOURCE_SHIFT 20 /* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_1 [19:13] */ #define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_1_MASK 0x000fe000 #define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_1_SHIFT 13 /* PCIE_CFG :: CLOCK_CONTROL :: SELECT_ALT_CLOCK [12:12] */ #define BCHP_PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_MASK 0x00001000 #define BCHP_PCIE_CFG_CLOCK_CONTROL_SELECT_ALT_CLOCK_SHIFT 12 /* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_2 [11:08] */ #define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_2_MASK 0x00000f00 #define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_2_SHIFT 8 /* PCIE_CFG :: CLOCK_CONTROL :: UNUSED_3 [07:00] */ #define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_3_MASK 0x000000ff #define BCHP_PCIE_CFG_CLOCK_CONTROL_UNUSED_3_SHIFT 0 /*************************************************************************** *REGISTER_BASE - REGISTER_BASE Register ***************************************************************************/ /* PCIE_CFG :: REGISTER_BASE :: RESERVED_0 [31:18] */ #define BCHP_PCIE_CFG_REGISTER_BASE_RESERVED_0_MASK 0xfffc0000 #define BCHP_PCIE_CFG_REGISTER_BASE_RESERVED_0_SHIFT 18 /* PCIE_CFG :: REGISTER_BASE :: REGISTER_BASE_REGISTER [17:02] */ #define BCHP_PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_MASK 0x0003fffc #define BCHP_PCIE_CFG_REGISTER_BASE_REGISTER_BASE_REGISTER_SHIFT 2 /* PCIE_CFG :: REGISTER_BASE :: RESERVED_1 [01:00] */ #define BCHP_PCIE_CFG_REGISTER_BASE_RESERVED_1_MASK 0x00000003 #define BCHP_PCIE_CFG_REGISTER_BASE_RESERVED_1_SHIFT 0 /*************************************************************************** *MEMORY_BASE - MEMORY_BASE Register ***************************************************************************/ /* PCIE_CFG :: MEMORY_BASE :: RESERVED_0 [31:24] */ #define BCHP_PCIE_CFG_MEMORY_BASE_RESERVED_0_MASK 0xff000000 #define BCHP_PCIE_CFG_MEMORY_BASE_RESERVED_0_SHIFT 24 /* PCIE_CFG :: MEMORY_BASE :: MEMORY_BASE_REGISTER [23:02] */ #define BCHP_PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_MASK 0x00fffffc #define BCHP_PCIE_CFG_MEMORY_BASE_MEMORY_BASE_REGISTER_SHIFT 2 /* PCIE_CFG :: MEMORY_BASE :: RESERVED_1 [01:00] */ #define BCHP_PCIE_CFG_MEMORY_BASE_RESERVED_1_MASK 0x00000003 #define BCHP_PCIE_CFG_MEMORY_BASE_RESERVED_1_SHIFT 0 /*************************************************************************** *REGISTER_DATA - REGISTER_DATA Register ***************************************************************************/ /* PCIE_CFG :: REGISTER_DATA :: REGISTER_DATA_REGISTER [31:00] */ #define BCHP_PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_MASK 0xffffffff #define BCHP_PCIE_CFG_REGISTER_DATA_REGISTER_DATA_REGISTER_SHIFT 0 /*************************************************************************** *MEMORY_DATA - MEMORY_DATA Register ***************************************************************************/ /* PCIE_CFG :: MEMORY_DATA :: MEMORY_DATA_REGISTER [31:00] */ #define BCHP_PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_MASK 0xffffffff #define BCHP_PCIE_CFG_MEMORY_DATA_MEMORY_DATA_REGISTER_SHIFT 0 /*************************************************************************** *EXPANSION_ROM_BAR_SIZE - EXPANSION_ROM_BAR_SIZE Register ***************************************************************************/ /* PCIE_CFG :: EXPANSION_ROM_BAR_SIZE :: RESERVED_0 [31:04] */ #define BCHP_PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_MASK 0xfffffff0 #define BCHP_PCIE_CFG_EXPANSION_ROM_BAR_SIZE_RESERVED_0_SHIFT 4 /* PCIE_CFG :: EXPANSION_ROM_BAR_SIZE :: BAR_SIZE [03:00] */ #define BCHP_PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_MASK 0x0000000f #define BCHP_PCIE_CFG_EXPANSION_ROM_BAR_SIZE_BAR_SIZE_SHIFT 0 /*************************************************************************** *EXPANSION_ROM_ADDRESS - EXPANSION_ROM_ADDRESS Register ***************************************************************************/ /* PCIE_CFG :: EXPANSION_ROM_ADDRESS :: ROM_CTL_ADDR [31:00] */ #define BCHP_PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_MASK 0xffffffff #define BCHP_PCIE_CFG_EXPANSION_ROM_ADDRESS_ROM_CTL_ADDR_SHIFT 0 /*************************************************************************** *EXPANSION_ROM_DATA - EXPANSION_ROM_DATA Register ***************************************************************************/ /* PCIE_CFG :: EXPANSION_ROM_DATA :: ROM_DATA [31:00] */ #define BCHP_PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_MASK 0xffffffff #define BCHP_PCIE_CFG_EXPANSION_ROM_DATA_ROM_DATA_SHIFT 0 /*************************************************************************** *VPD_INTERFACE - VPD_INTERFACE Register ***************************************************************************/ /* PCIE_CFG :: VPD_INTERFACE :: RESERVED_0 [31:01] */ #define BCHP_PCIE_CFG_VPD_INTERFACE_RESERVED_0_MASK 0xfffffffe #define BCHP_PCIE_CFG_VPD_INTERFACE_RESERVED_0_SHIFT 1 /* PCIE_CFG :: VPD_INTERFACE :: VPD_REQUEST [00:00] */ #define BCHP_PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_MASK 0x00000001 #define BCHP_PCIE_CFG_VPD_INTERFACE_VPD_REQUEST_SHIFT 0 /*************************************************************************** *UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER - UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER Register ***************************************************************************/ /* PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER :: UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX [31:00] */ #define BCHP_PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_MASK 0xffffffff #define BCHP_PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_SHIFT 0 /*************************************************************************** *UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER - UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER Register ***************************************************************************/ /* PCIE_CFG :: UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER :: UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX [31:00] */ #define BCHP_PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_MASK 0xffffffff #define BCHP_PCIE_CFG_UNDI_RECEIVE_BD_STANDARD_PRODUCER_RING_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_RECEIVE_BD_STANDARD_RING_PRODUCER_INDEX_SHIFT 0 /*************************************************************************** *UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER - UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER Register ***************************************************************************/ /* PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER :: UNDI_RECEIVE_RETURN_C_IDX [31:00] */ #define BCHP_PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_MASK 0xffffffff #define BCHP_PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_UPPER_UNDI_RECEIVE_RETURN_C_IDX_SHIFT 0 /*************************************************************************** *UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER - UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER Register ***************************************************************************/ /* PCIE_CFG :: UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER :: UNDI_RECEIVE_RETURN_C_IDX [31:00] */ #define BCHP_PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_MASK 0xffffffff #define BCHP_PCIE_CFG_UNDI_RECEIVE_RETURN_RING_CONSUMER_INDEX_LOWER_UNDI_RECEIVE_RETURN_C_IDX_SHIFT 0 /*************************************************************************** *UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER - UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER Register ***************************************************************************/ /* PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER :: UNDI_SEND_BD_NIC_P_IDX [31:00] */ #define BCHP_PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_MASK 0xffffffff #define BCHP_PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_UPPER_UNDI_SEND_BD_NIC_P_IDX_SHIFT 0 /*************************************************************************** *UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER - UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER Register ***************************************************************************/ /* PCIE_CFG :: UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER :: UNDI_SEND_BD_NIC_P_IDX [31:00] */ #define BCHP_PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_MASK 0xffffffff #define BCHP_PCIE_CFG_UNDI_SEND_BD_PRODUCER_INDEX_MAILBOX_LOWER_UNDI_SEND_BD_NIC_P_IDX_SHIFT 0 /*************************************************************************** *INT_MAILBOX_UPPER - INT_MAILBOX_UPPER Register ***************************************************************************/ /* PCIE_CFG :: INT_MAILBOX_UPPER :: INDIRECT_INTERRUPT_MAIL_BOX [31:00] */ #define BCHP_PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_MASK 0xffffffff #define BCHP_PCIE_CFG_INT_MAILBOX_UPPER_INDIRECT_INTERRUPT_MAIL_BOX_SHIFT 0 /*************************************************************************** *INT_MAILBOX_LOWER - INT_MAILBOX_LOWER Register ***************************************************************************/ /* PCIE_CFG :: INT_MAILBOX_LOWER :: INDIRECT_INTERRUPT_MAIL_BOX [31:00] */ #define BCHP_PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_MASK 0xffffffff #define BCHP_PCIE_CFG_INT_MAILBOX_LOWER_INDIRECT_INTERRUPT_MAIL_BOX_SHIFT 0 /*************************************************************************** *PRODUCT_ID_AND_ASIC_REVISION - PRODUCT_ID_AND_ASIC_REVISION Register ***************************************************************************/ /* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: RESERVED_0 [31:28] */ #define BCHP_PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_MASK 0xf0000000 #define BCHP_PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_RESERVED_0_SHIFT 28 /* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: PRODUCT_ID [27:08] */ #define BCHP_PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_MASK 0x0fffff00 #define BCHP_PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_PRODUCT_ID_SHIFT 8 /* PCIE_CFG :: PRODUCT_ID_AND_ASIC_REVISION :: ASIC_REVISION_ID [07:00] */ #define BCHP_PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_MASK 0x000000ff #define BCHP_PCIE_CFG_PRODUCT_ID_AND_ASIC_REVISION_ASIC_REVISION_ID_SHIFT 0 /*************************************************************************** *FUNCTION_EVENT - FUNCTION_EVENT Register ***************************************************************************/ /* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_0 [31:16] */ #define BCHP_PCIE_CFG_FUNCTION_EVENT_RESERVED_0_MASK 0xffff0000 #define BCHP_PCIE_CFG_FUNCTION_EVENT_RESERVED_0_SHIFT 16 /* PCIE_CFG :: FUNCTION_EVENT :: INTA_EVENT [15:15] */ #define BCHP_PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_MASK 0x00008000 #define BCHP_PCIE_CFG_FUNCTION_EVENT_INTA_EVENT_SHIFT 15 /* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_1 [14:05] */ #define BCHP_PCIE_CFG_FUNCTION_EVENT_RESERVED_1_MASK 0x00007fe0 #define BCHP_PCIE_CFG_FUNCTION_EVENT_RESERVED_1_SHIFT 5 /* PCIE_CFG :: FUNCTION_EVENT :: GWAKE_EVENT [04:04] */ #define BCHP_PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_MASK 0x00000010 #define BCHP_PCIE_CFG_FUNCTION_EVENT_GWAKE_EVENT_SHIFT 4 /* PCIE_CFG :: FUNCTION_EVENT :: RESERVED_2 [03:00] */ #define BCHP_PCIE_CFG_FUNCTION_EVENT_RESERVED_2_MASK 0x0000000f #define BCHP_PCIE_CFG_FUNCTION_EVENT_RESERVED_2_SHIFT 0 /*************************************************************************** *FUNCTION_EVENT_MASK - FUNCTION_EVENT_MASK Register ***************************************************************************/ /* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_0 [31:16] */ #define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_MASK 0xffff0000 #define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_0_SHIFT 16 /* PCIE_CFG :: FUNCTION_EVENT_MASK :: INTA_MASK [15:15] */ #define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_MASK 0x00008000 #define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_INTA_MASK_SHIFT 15 /* PCIE_CFG :: FUNCTION_EVENT_MASK :: WAKE_UP_MASK [14:14] */ #define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_MASK 0x00004000 #define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_WAKE_UP_MASK_SHIFT 14 /* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_1 [13:05] */ #define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_MASK 0x00003fe0 #define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_1_SHIFT 5 /* PCIE_CFG :: FUNCTION_EVENT_MASK :: GWAKE_MASK [04:04] */ #define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_MASK 0x00000010 #define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_GWAKE_MASK_SHIFT 4 /* PCIE_CFG :: FUNCTION_EVENT_MASK :: RESERVED_2 [03:00] */ #define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_MASK 0x0000000f #define BCHP_PCIE_CFG_FUNCTION_EVENT_MASK_RESERVED_2_SHIFT 0 /*************************************************************************** *FUNCTION_PRESENT - FUNCTION_PRESENT Register ***************************************************************************/ /* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_0 [31:16] */ #define BCHP_PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_MASK 0xffff0000 #define BCHP_PCIE_CFG_FUNCTION_PRESENT_RESERVED_0_SHIFT 16 /* PCIE_CFG :: FUNCTION_PRESENT :: INTA_STATUS [15:15] */ #define BCHP_PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_MASK 0x00008000 #define BCHP_PCIE_CFG_FUNCTION_PRESENT_INTA_STATUS_SHIFT 15 /* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_1 [14:05] */ #define BCHP_PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_MASK 0x00007fe0 #define BCHP_PCIE_CFG_FUNCTION_PRESENT_RESERVED_1_SHIFT 5 /* PCIE_CFG :: FUNCTION_PRESENT :: PME_STATUS [04:04] */ #define BCHP_PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_MASK 0x00000010 #define BCHP_PCIE_CFG_FUNCTION_PRESENT_PME_STATUS_SHIFT 4 /* PCIE_CFG :: FUNCTION_PRESENT :: RESERVED_2 [03:00] */ #define BCHP_PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_MASK 0x0000000f #define BCHP_PCIE_CFG_FUNCTION_PRESENT_RESERVED_2_SHIFT 0 /*************************************************************************** *PCIE_CAPABILITIES - PCIE_CAPABILITIES Register ***************************************************************************/ /* PCIE_CFG :: PCIE_CAPABILITIES :: RESERVED_0 [31:30] */ #define BCHP_PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_MASK 0xc0000000 #define BCHP_PCIE_CFG_PCIE_CAPABILITIES_RESERVED_0_SHIFT 30 /* PCIE_CFG :: PCIE_CAPABILITIES :: INTERRUPT_MESSAGE_NUMBER [29:25] */ #define BCHP_PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_MASK 0x3e000000 #define BCHP_PCIE_CFG_PCIE_CAPABILITIES_INTERRUPT_MESSAGE_NUMBER_SHIFT 25 /* PCIE_CFG :: PCIE_CAPABILITIES :: SLOT_IMPLEMENTED [24:24] */ #define BCHP_PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_MASK 0x01000000 #define BCHP_PCIE_CFG_PCIE_CAPABILITIES_SLOT_IMPLEMENTED_SHIFT 24 /* PCIE_CFG :: PCIE_CAPABILITIES :: DEVICE_PORT_TYPE [23:20] */ #define BCHP_PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_MASK 0x00f00000 #define BCHP_PCIE_CFG_PCIE_CAPABILITIES_DEVICE_PORT_TYPE_SHIFT 20 /* PCIE_CFG :: PCIE_CAPABILITIES :: CAPABILITY_VERSION [19:16] */ #define BCHP_PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_MASK 0x000f0000 #define BCHP_PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_VERSION_SHIFT 16 /* PCIE_CFG :: PCIE_CAPABILITIES :: NEXT_POINTER [15:08] */ #define BCHP_PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_MASK 0x0000ff00 #define BCHP_PCIE_CFG_PCIE_CAPABILITIES_NEXT_POINTER_SHIFT 8 /* PCIE_CFG :: PCIE_CAPABILITIES :: CAPABILITY_ID [07:00] */ #define BCHP_PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_MASK 0x000000ff #define BCHP_PCIE_CFG_PCIE_CAPABILITIES_CAPABILITY_ID_SHIFT 0 /*************************************************************************** *DEVICE_CAPABILITIES - DEVICE_CAPABILITIES Register ***************************************************************************/ /* PCIE_CFG :: DEVICE_CAPABILITIES :: RESERVED_0 [31:28] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_MASK 0xf0000000 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_0_SHIFT 28 /* PCIE_CFG :: DEVICE_CAPABILITIES :: CAPTURED_SLOT_POWER_LIMIT_SCALE [27:26] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_MASK 0x0c000000 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_SCALE_SHIFT 26 /* PCIE_CFG :: DEVICE_CAPABILITIES :: CAPTURED_SLOT_POWER_LIMIT_VALUE [25:18] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_MASK 0x03fc0000 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_CAPTURED_SLOT_POWER_LIMIT_VALUE_SHIFT 18 /* PCIE_CFG :: DEVICE_CAPABILITIES :: RESERVED_1 [17:16] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_MASK 0x00030000 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_RESERVED_1_SHIFT 16 /* PCIE_CFG :: DEVICE_CAPABILITIES :: ROLE_BASED_ERROR_SUPPORT [15:15] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_MASK 0x00008000 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ROLE_BASED_ERROR_SUPPORT_SHIFT 15 /* PCIE_CFG :: DEVICE_CAPABILITIES :: POWER_INDICATOR_PRESENT [14:14] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_MASK 0x00004000 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_POWER_INDICATOR_PRESENT_SHIFT 14 /* PCIE_CFG :: DEVICE_CAPABILITIES :: ATTENTION_INDICATOR_PRESENT [13:13] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_MASK 0x00002000 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_INDICATOR_PRESENT_SHIFT 13 /* PCIE_CFG :: DEVICE_CAPABILITIES :: ATTENTION_BUTTON_PRESENT [12:12] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_MASK 0x00001000 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ATTENTION_BUTTON_PRESENT_SHIFT 12 /* PCIE_CFG :: DEVICE_CAPABILITIES :: ENDPOINT_L1_ACCEPTABLE_LATENCY [11:09] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_MASK 0x00000e00 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L1_ACCEPTABLE_LATENCY_SHIFT 9 /* PCIE_CFG :: DEVICE_CAPABILITIES :: ENDPOINT_L0S_ACCEPTABLE_LATENCY [08:06] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_MASK 0x000001c0 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_ENDPOINT_L0S_ACCEPTABLE_LATENCY_SHIFT 6 /* PCIE_CFG :: DEVICE_CAPABILITIES :: EXTENDED_TAG_FIELD_SUPPORTED [05:05] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_MASK 0x00000020 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_EXTENDED_TAG_FIELD_SUPPORTED_SHIFT 5 /* PCIE_CFG :: DEVICE_CAPABILITIES :: PHANTOM_FUNCTIONS_SUPPORTED [04:03] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_MASK 0x00000018 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_PHANTOM_FUNCTIONS_SUPPORTED_SHIFT 3 /* PCIE_CFG :: DEVICE_CAPABILITIES :: MAX_PAYLOAD_SIZE_SUPPORTED [02:00] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_MASK 0x00000007 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_MAX_PAYLOAD_SIZE_SUPPORTED_SHIFT 0 /*************************************************************************** *DEVICE_STATUS_CONTROL - DEVICE_STATUS_CONTROL Register ***************************************************************************/ /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: RESERVED_0 [31:22] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_MASK 0xffc00000 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_0_SHIFT 22 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: TRANSACTION_PENDING [21:21] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_MASK 0x00200000 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_TRANSACTION_PENDING_SHIFT 21 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: AUX_POWER_DETECTED [20:20] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_MASK 0x00100000 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_DETECTED_SHIFT 20 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: UNSUPPORTED_REQUEST_DETECTED [19:19] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_MASK 0x00080000 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_DETECTED_SHIFT 19 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: FATAL_ERROR_DETECTED [18:18] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_MASK 0x00040000 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_DETECTED_SHIFT 18 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERROR_DETECTED [17:17] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_MASK 0x00020000 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_DETECTED_SHIFT 17 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: CORRECTABLE_ERROR_DETECTED [16:16] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_MASK 0x00010000 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_DETECTED_SHIFT 16 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: RESERVED_1 [15:15] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_MASK 0x00008000 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_RESERVED_1_SHIFT 15 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: MAX_READ_REQUEST_SIZE [14:12] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_MASK 0x00007000 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_READ_REQUEST_SIZE_SHIFT 12 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: ENABLE_NO_SNOOP [11:11] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_MASK 0x00000800 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLE_NO_SNOOP_SHIFT 11 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: AUX_POWER_PM_ENABLE [10:10] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_MASK 0x00000400 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_AUX_POWER_PM_ENABLE_SHIFT 10 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: PHANTOM_FUNCTIONS_ENABLE [09:09] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_MASK 0x00000200 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_PHANTOM_FUNCTIONS_ENABLE_SHIFT 9 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: EXTENDED_TAG_FIELD_ENABLE [08:08] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_MASK 0x00000100 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_EXTENDED_TAG_FIELD_ENABLE_SHIFT 8 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: MAX_PAYLOAD_SIZE [07:05] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_MASK 0x000000e0 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_MAX_PAYLOAD_SIZE_SHIFT 5 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: ENABLED_RELAXED_ORDERING [04:04] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_MASK 0x00000010 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_ENABLED_RELAXED_ORDERING_SHIFT 4 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: UNSUPPORTED_REQUEST_REPORTING_ENABLE [03:03] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_MASK 0x00000008 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_UNSUPPORTED_REQUEST_REPORTING_ENABLE_SHIFT 3 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: FATAL_ERROR_REPORTING_ENABLED [02:02] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_MASK 0x00000004 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_FATAL_ERROR_REPORTING_ENABLED_SHIFT 2 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: NON_FATAL_ERROR_REPORTING_ENABLED [01:01] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_MASK 0x00000002 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_NON_FATAL_ERROR_REPORTING_ENABLED_SHIFT 1 /* PCIE_CFG :: DEVICE_STATUS_CONTROL :: CORRECTABLE_ERROR_REPORTING_ENABLED [00:00] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_MASK 0x00000001 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_CORRECTABLE_ERROR_REPORTING_ENABLED_SHIFT 0 /*************************************************************************** *LINK_CAPABILITY - LINK_CAPABILITY Register ***************************************************************************/ /* PCIE_CFG :: LINK_CAPABILITY :: PORT_NUMBER [31:24] */ #define BCHP_PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_MASK 0xff000000 #define BCHP_PCIE_CFG_LINK_CAPABILITY_PORT_NUMBER_SHIFT 24 /* PCIE_CFG :: LINK_CAPABILITY :: RESERVED_0 [23:19] */ #define BCHP_PCIE_CFG_LINK_CAPABILITY_RESERVED_0_MASK 0x00f80000 #define BCHP_PCIE_CFG_LINK_CAPABILITY_RESERVED_0_SHIFT 19 /* PCIE_CFG :: LINK_CAPABILITY :: CLOCK_POWER_MANAGEMENT [18:18] */ #define BCHP_PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_MASK 0x00040000 #define BCHP_PCIE_CFG_LINK_CAPABILITY_CLOCK_POWER_MANAGEMENT_SHIFT 18 /* PCIE_CFG :: LINK_CAPABILITY :: L1_EXIT_LATENCY [17:15] */ #define BCHP_PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_MASK 0x00038000 #define BCHP_PCIE_CFG_LINK_CAPABILITY_L1_EXIT_LATENCY_SHIFT 15 /* PCIE_CFG :: LINK_CAPABILITY :: L0S_EXIT_LATENCY [14:12] */ #define BCHP_PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_MASK 0x00007000 #define BCHP_PCIE_CFG_LINK_CAPABILITY_L0S_EXIT_LATENCY_SHIFT 12 /* PCIE_CFG :: LINK_CAPABILITY :: ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT [11:10] */ #define BCHP_PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_MASK 0x00000c00 #define BCHP_PCIE_CFG_LINK_CAPABILITY_ACTIVE_STATE_POWER_MANAGEMENT_SUPPORT_SHIFT 10 /* PCIE_CFG :: LINK_CAPABILITY :: MAXIMUM_LINK_WIDTH [09:04] */ #define BCHP_PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_MASK 0x000003f0 #define BCHP_PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_WIDTH_SHIFT 4 /* PCIE_CFG :: LINK_CAPABILITY :: MAXIMUM_LINK_SPEED [03:00] */ #define BCHP_PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_MASK 0x0000000f #define BCHP_PCIE_CFG_LINK_CAPABILITY_MAXIMUM_LINK_SPEED_SHIFT 0 /*************************************************************************** *LINK_STATUS_CONTROL - LINK_STATUS_CONTROL Register ***************************************************************************/ /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_0 [31:29] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_MASK 0xe0000000 #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_0_SHIFT 29 /* PCIE_CFG :: LINK_STATUS_CONTROL :: SLOT_CLOCK_CONFIGURATION [28:28] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_MASK 0x10000000 #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_SLOT_CLOCK_CONFIGURATION_SHIFT 28 /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_1 [27:26] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_MASK 0x0c000000 #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_1_SHIFT 26 /* PCIE_CFG :: LINK_STATUS_CONTROL :: NEGOTIATED_LINK_WIDTH [25:20] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_MASK 0x03f00000 #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_NEGOTIATED_LINK_WIDTH_SHIFT 20 /* PCIE_CFG :: LINK_STATUS_CONTROL :: LINK_SPEED [19:16] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_MASK 0x000f0000 #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_LINK_SPEED_SHIFT 16 /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_2 [15:09] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_MASK 0x0000fe00 #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_2_SHIFT 9 /* PCIE_CFG :: LINK_STATUS_CONTROL :: CLOCK_REQUEST_ENABLE [08:08] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_MASK 0x00000100 #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_CLOCK_REQUEST_ENABLE_SHIFT 8 /* PCIE_CFG :: LINK_STATUS_CONTROL :: EXTENDED_SYNCH [07:07] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_MASK 0x00000080 #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_EXTENDED_SYNCH_SHIFT 7 /* PCIE_CFG :: LINK_STATUS_CONTROL :: COMMON_CLOCK_CONFIGURATION [06:06] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_MASK 0x00000040 #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_COMMON_CLOCK_CONFIGURATION_SHIFT 6 /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_3 [05:05] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_MASK 0x00000020 #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_3_SHIFT 5 /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_4 [04:04] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_MASK 0x00000010 #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_4_SHIFT 4 /* PCIE_CFG :: LINK_STATUS_CONTROL :: READ_COMPLETION_BOUNDARY [03:03] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_MASK 0x00000008 #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_READ_COMPLETION_BOUNDARY_SHIFT 3 /* PCIE_CFG :: LINK_STATUS_CONTROL :: RESERVED_5 [02:02] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_MASK 0x00000004 #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_RESERVED_5_SHIFT 2 /* PCIE_CFG :: LINK_STATUS_CONTROL :: ACTIVE_STATE_POWER_MANAGEMENT_CONTROL [01:00] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_MASK 0x00000003 #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_ACTIVE_STATE_POWER_MANAGEMENT_CONTROL_SHIFT 0 /*************************************************************************** *DEVICE_CAPABILITIES_2 - DEVICE_CAPABILITIES_2 Register ***************************************************************************/ /* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: RESERVED_0 [31:05] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_MASK 0xffffffe0 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_2_RESERVED_0_SHIFT 5 /* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: CPL_DISABLE_SUPPORTED [04:04] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_MASK 0x00000010 #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_DISABLE_SUPPORTED_SHIFT 4 /* PCIE_CFG :: DEVICE_CAPABILITIES_2 :: CPL_TIMEOUT_RANGE_SUPPORTED [03:00] */ #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_MASK 0x0000000f #define BCHP_PCIE_CFG_DEVICE_CAPABILITIES_2_CPL_TIMEOUT_RANGE_SUPPORTED_SHIFT 0 /*************************************************************************** *DEVICE_STATUS_CONTROL_2 - DEVICE_STATUS_CONTROL_2 Register ***************************************************************************/ /* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: RESERVED_0 [31:05] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_MASK 0xffffffe0 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_2_RESERVED_0_SHIFT 5 /* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: CPL_TIMEOUT_DISABLE [04:04] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_MASK 0x00000010 #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_DISABLE_SHIFT 4 /* PCIE_CFG :: DEVICE_STATUS_CONTROL_2 :: CPL_TIMEOUT_VALUE [03:00] */ #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_MASK 0x0000000f #define BCHP_PCIE_CFG_DEVICE_STATUS_CONTROL_2_CPL_TIMEOUT_VALUE_SHIFT 0 /*************************************************************************** *LINK_CAPABILITIES_2 - LINK_CAPABILITIES_2 Register ***************************************************************************/ /* PCIE_CFG :: LINK_CAPABILITIES_2 :: RESERVED_0 [31:00] */ #define BCHP_PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_MASK 0xffffffff #define BCHP_PCIE_CFG_LINK_CAPABILITIES_2_RESERVED_0_SHIFT 0 /*************************************************************************** *LINK_STATUS_CONTROL_2 - LINK_STATUS_CONTROL_2 Register ***************************************************************************/ /* PCIE_CFG :: LINK_STATUS_CONTROL_2 :: RESERVED_0 [31:00] */ #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_MASK 0xffffffff #define BCHP_PCIE_CFG_LINK_STATUS_CONTROL_2_RESERVED_0_SHIFT 0 /*************************************************************************** *ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER - ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER Register ***************************************************************************/ /* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ #define BCHP_PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 #define BCHP_PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 /* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ #define BCHP_PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 #define BCHP_PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 /* PCIE_CFG :: ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ #define BCHP_PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff #define BCHP_PCIE_CFG_ADVANCED_ERROR_REPORTING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 /*************************************************************************** *UNCORRECTABLE_ERROR_STATUS - UNCORRECTABLE_ERROR_STATUS Register ***************************************************************************/ /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_0 [31:21] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_MASK 0xffe00000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_0_SHIFT 21 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: UNSUPPORTED_REQUEST_ERROR_STATUS [20:20] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_MASK 0x00100000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNSUPPORTED_REQUEST_ERROR_STATUS_SHIFT 20 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: ECRC_ERROR_STATUS [19:19] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_MASK 0x00080000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_ECRC_ERROR_STATUS_SHIFT 19 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: MALFORMED_TLP_STATUS [18:18] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_MASK 0x00040000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_MALFORMED_TLP_STATUS_SHIFT 18 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RECEIVER_OVERFLOW_STATUS [17:17] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_MASK 0x00020000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RECEIVER_OVERFLOW_STATUS_SHIFT 17 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: UNEXPECTED_COMPLETION_STATUS [16:16] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_MASK 0x00010000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_UNEXPECTED_COMPLETION_STATUS_SHIFT 16 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: COMPLETER_ABORT_STATUS [15:15] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_MASK 0x00008000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETER_ABORT_STATUS_SHIFT 15 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: COMPLETION_TIMEOUT_STATUS [14:14] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_MASK 0x00004000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_COMPLETION_TIMEOUT_STATUS_SHIFT 14 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: FLOW_CONTROL_PROTOCOL_ERROR_STATUS [13:13] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_MASK 0x00002000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_STATUS_SHIFT 13 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: POISONED_TLP_STATUS [12:12] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_MASK 0x00001000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_POISONED_TLP_STATUS_SHIFT 12 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_1 [11:05] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_MASK 0x00000fe0 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_1_SHIFT 5 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: DATA_LINK_PROTOCOL_ERROR_STATUS [04:04] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_MASK 0x00000010 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_DATA_LINK_PROTOCOL_ERROR_STATUS_SHIFT 4 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: RESERVED_2 [03:01] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_MASK 0x0000000e #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_RESERVED_2_SHIFT 1 /* PCIE_CFG :: UNCORRECTABLE_ERROR_STATUS :: TRAINING_ERROR_STATUS [00:00] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_MASK 0x00000001 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_STATUS_TRAINING_ERROR_STATUS_SHIFT 0 /*************************************************************************** *UNCORRECTABLE_ERROR_MASK - UNCORRECTABLE_ERROR_MASK Register ***************************************************************************/ /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_0 [31:21] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_MASK 0xffe00000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_0_SHIFT 21 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: UNSUPPORTED_REQUEST_ERROR_MASK [20:20] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_MASK 0x00100000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNSUPPORTED_REQUEST_ERROR_MASK_SHIFT 20 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: ECRC_ERROR_MASK [19:19] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_MASK 0x00080000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_ECRC_ERROR_MASK_SHIFT 19 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: MALFORMED_TLP_MASK [18:18] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_MASK 0x00040000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_MALFORMED_TLP_MASK_SHIFT 18 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RECEIVER_OVERFLOW_MASK [17:17] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_MASK 0x00020000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RECEIVER_OVERFLOW_MASK_SHIFT 17 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: UNEXPECTED_COMPLETION_MASK [16:16] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_MASK 0x00010000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_UNEXPECTED_COMPLETION_MASK_SHIFT 16 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: COMPLETER_ABORT_MASK [15:15] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_MASK 0x00008000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETER_ABORT_MASK_SHIFT 15 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: COMPLETION_TIMEOUT_MASK [14:14] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_MASK 0x00004000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_COMPLETION_TIMEOUT_MASK_SHIFT 14 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: FLOW_CONTROL_PROTOCOL_ERROR_MASK [13:13] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_MASK 0x00002000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_FLOW_CONTROL_PROTOCOL_ERROR_MASK_SHIFT 13 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: POISONED_TLP_MASK [12:12] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_MASK 0x00001000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_POISONED_TLP_MASK_SHIFT 12 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_1 [11:05] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_MASK 0x00000fe0 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_1_SHIFT 5 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: DATA_LINK_PROTOCOL_ERROR_MASK [04:04] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_MASK 0x00000010 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_DATA_LINK_PROTOCOL_ERROR_MASK_SHIFT 4 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: RESERVED_2 [03:01] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_MASK 0x0000000e #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_RESERVED_2_SHIFT 1 /* PCIE_CFG :: UNCORRECTABLE_ERROR_MASK :: TRAINING_ERROR_MASK [00:00] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_MASK 0x00000001 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_MASK_TRAINING_ERROR_MASK_SHIFT 0 /*************************************************************************** *UNCORRECTABLE_ERROR_SEVERITY - UNCORRECTABLE_ERROR_SEVERITY Register ***************************************************************************/ /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_0 [31:21] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_MASK 0xffe00000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_0_SHIFT 21 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: UNSUPPORTED_REQUEST_ERROR_SEVERITY [20:20] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_MASK 0x00100000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNSUPPORTED_REQUEST_ERROR_SEVERITY_SHIFT 20 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: ECRC_ERROR_SEVERITY [19:19] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_MASK 0x00080000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_ECRC_ERROR_SEVERITY_SHIFT 19 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: MALFORMED_TLP_SEVERITY [18:18] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_MASK 0x00040000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_MALFORMED_TLP_SEVERITY_SHIFT 18 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RECEIVER_OVERFLOW_ERROR_SEVERITY [17:17] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_MASK 0x00020000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RECEIVER_OVERFLOW_ERROR_SEVERITY_SHIFT 17 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: UNEXPECTED_COMPLETION_ERROR_SEVERITY [16:16] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_MASK 0x00010000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_UNEXPECTED_COMPLETION_ERROR_SEVERITY_SHIFT 16 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: COMPLETER_ABORT_ERROR_SEVERITY [15:15] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_MASK 0x00008000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETER_ABORT_ERROR_SEVERITY_SHIFT 15 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: COMPLETION_TIMEOUT_ERROR_SEVERITY [14:14] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_MASK 0x00004000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_COMPLETION_TIMEOUT_ERROR_SEVERITY_SHIFT 14 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY [13:13] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_MASK 0x00002000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_FLOW_CONTROL_PROTOCOL_ERROR_SEVERITY_SHIFT 13 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: POISONED_TLP_SEVERITY [12:12] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_MASK 0x00001000 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_POISONED_TLP_SEVERITY_SHIFT 12 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_1 [11:05] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_MASK 0x00000fe0 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_1_SHIFT 5 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: DATA_LINK_PROTOCOL_ERROR_SEVERITY [04:04] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_MASK 0x00000010 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_DATA_LINK_PROTOCOL_ERROR_SEVERITY_SHIFT 4 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: RESERVED_2 [03:01] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_MASK 0x0000000e #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_RESERVED_2_SHIFT 1 /* PCIE_CFG :: UNCORRECTABLE_ERROR_SEVERITY :: TRAINING_ERROR_SEVERITY [00:00] */ #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_MASK 0x00000001 #define BCHP_PCIE_CFG_UNCORRECTABLE_ERROR_SEVERITY_TRAINING_ERROR_SEVERITY_SHIFT 0 /*************************************************************************** *CORRECTABLE_ERROR_STATUS - CORRECTABLE_ERROR_STATUS Register ***************************************************************************/ /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_0 [31:14] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_MASK 0xffffc000 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_0_SHIFT 14 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: ADVISORY_NON_FATAL_ERROR_STATUS [13:13] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_MASK 0x00002000 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_ADVISORY_NON_FATAL_ERROR_STATUS_SHIFT 13 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: REPLAY_TIMER_TIMEOUT_STATUS [12:12] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_MASK 0x00001000 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_TIMER_TIMEOUT_STATUS_SHIFT 12 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_1 [11:09] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_MASK 0x00000e00 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_1_SHIFT 9 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: REPLAY_NUM_ROLLOVER_STATUS [08:08] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_MASK 0x00000100 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_REPLAY_NUM_ROLLOVER_STATUS_SHIFT 8 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: BAD_DLLP_STATUS [07:07] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_MASK 0x00000080 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_DLLP_STATUS_SHIFT 7 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: BAD_TLP_STATUS [06:06] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_MASK 0x00000040 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_BAD_TLP_STATUS_SHIFT 6 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RESERVED_2 [05:01] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_MASK 0x0000003e #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RESERVED_2_SHIFT 1 /* PCIE_CFG :: CORRECTABLE_ERROR_STATUS :: RECEIVER_ERROR_STATUS [00:00] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_MASK 0x00000001 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_STATUS_RECEIVER_ERROR_STATUS_SHIFT 0 /*************************************************************************** *CORRECTABLE_ERROR_MASK - CORRECTABLE_ERROR_MASK Register ***************************************************************************/ /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_0 [31:14] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_MASK 0xffffc000 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_0_SHIFT 14 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: ADVISORY_NON_FATAL_ERROR_MASK [13:13] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_MASK 0x00002000 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_ADVISORY_NON_FATAL_ERROR_MASK_SHIFT 13 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: REPLAY_TIMER_TIMEOUT_MASK [12:12] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_MASK 0x00001000 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_TIMER_TIMEOUT_MASK_SHIFT 12 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_1 [11:09] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_MASK 0x00000e00 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_1_SHIFT 9 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: REPLAY_NUM_ROLLOVER_MASK [08:08] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_MASK 0x00000100 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_REPLAY_NUM_ROLLOVER_MASK_SHIFT 8 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: BAD_DLLP_MASK [07:07] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_MASK 0x00000080 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_DLLP_MASK_SHIFT 7 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: BAD_TLP_MASK [06:06] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_MASK 0x00000040 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_BAD_TLP_MASK_SHIFT 6 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RESERVED_2 [05:01] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_MASK 0x0000003e #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RESERVED_2_SHIFT 1 /* PCIE_CFG :: CORRECTABLE_ERROR_MASK :: RECEIVER_ERROR_MASK [00:00] */ #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_MASK 0x00000001 #define BCHP_PCIE_CFG_CORRECTABLE_ERROR_MASK_RECEIVER_ERROR_MASK_SHIFT 0 /*************************************************************************** *ADVANCED_ERROR_CAPABILITIES_AND_CONTROL - ADVANCED_ERROR_CAPABILITIES_AND_CONTROL Register ***************************************************************************/ /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: RESERVED_0 [31:09] */ #define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_MASK 0xfffffe00 #define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_RESERVED_0_SHIFT 9 /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_CHECK_ENABLE [08:08] */ #define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_MASK 0x00000100 #define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_ENABLE_SHIFT 8 /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_CHECK_CAPABLE [07:07] */ #define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_MASK 0x00000080 #define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_CHECK_CAPABLE_SHIFT 7 /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_GENERATION_ENABLE [06:06] */ #define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_MASK 0x00000040 #define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_ENABLE_SHIFT 6 /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: ECRC_GENERATION_CAPABLE [05:05] */ #define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_MASK 0x00000020 #define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_ECRC_GENERATION_CAPABLE_SHIFT 5 /* PCIE_CFG :: ADVANCED_ERROR_CAPABILITIES_AND_CONTROL :: FIRST_ERROR_POINTER [04:00] */ #define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_MASK 0x0000001f #define BCHP_PCIE_CFG_ADVANCED_ERROR_CAPABILITIES_AND_CONTROL_FIRST_ERROR_POINTER_SHIFT 0 /*************************************************************************** *HEADER_LOG_1 - HEADER_LOG_1 Register ***************************************************************************/ /* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_0 [31:24] */ #define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_MASK 0xff000000 #define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_0_SHIFT 24 /* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_1 [23:16] */ #define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_MASK 0x00ff0000 #define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_1_SHIFT 16 /* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_2 [15:08] */ #define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_MASK 0x0000ff00 #define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_2_SHIFT 8 /* PCIE_CFG :: HEADER_LOG_1 :: HEADER_BYTE_3 [07:00] */ #define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_MASK 0x000000ff #define BCHP_PCIE_CFG_HEADER_LOG_1_HEADER_BYTE_3_SHIFT 0 /*************************************************************************** *HEADER_LOG_2 - HEADER_LOG_2 Register ***************************************************************************/ /* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_4 [31:24] */ #define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_MASK 0xff000000 #define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_4_SHIFT 24 /* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_5 [23:16] */ #define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_MASK 0x00ff0000 #define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_5_SHIFT 16 /* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_6 [15:08] */ #define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_MASK 0x0000ff00 #define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_6_SHIFT 8 /* PCIE_CFG :: HEADER_LOG_2 :: HEADER_BYTE_7 [07:00] */ #define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_MASK 0x000000ff #define BCHP_PCIE_CFG_HEADER_LOG_2_HEADER_BYTE_7_SHIFT 0 /*************************************************************************** *HEADER_LOG_3 - HEADER_LOG_3 Register ***************************************************************************/ /* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_8 [31:24] */ #define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_MASK 0xff000000 #define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_8_SHIFT 24 /* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_9 [23:16] */ #define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_MASK 0x00ff0000 #define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_9_SHIFT 16 /* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_10 [15:08] */ #define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_MASK 0x0000ff00 #define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_10_SHIFT 8 /* PCIE_CFG :: HEADER_LOG_3 :: HEADER_BYTE_11 [07:00] */ #define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_MASK 0x000000ff #define BCHP_PCIE_CFG_HEADER_LOG_3_HEADER_BYTE_11_SHIFT 0 /*************************************************************************** *HEADER_LOG_4 - HEADER_LOG_4 Register ***************************************************************************/ /* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_12 [31:24] */ #define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_MASK 0xff000000 #define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_12_SHIFT 24 /* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_13 [23:16] */ #define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_MASK 0x00ff0000 #define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_13_SHIFT 16 /* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_14 [15:08] */ #define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_MASK 0x0000ff00 #define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_14_SHIFT 8 /* PCIE_CFG :: HEADER_LOG_4 :: HEADER_BYTE_15 [07:00] */ #define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_MASK 0x000000ff #define BCHP_PCIE_CFG_HEADER_LOG_4_HEADER_BYTE_15_SHIFT 0 /*************************************************************************** *VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER - VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER Register ***************************************************************************/ /* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ #define BCHP_PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 #define BCHP_PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 /* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ #define BCHP_PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 #define BCHP_PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 /* PCIE_CFG :: VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ #define BCHP_PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff #define BCHP_PCIE_CFG_VIRTUAL_CHANNEL_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 /*************************************************************************** *PORT_VC_CAPABILITY - PORT_VC_CAPABILITY Register ***************************************************************************/ /* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_0 [31:12] */ #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_MASK 0xfffff000 #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_0_SHIFT 12 /* PCIE_CFG :: PORT_VC_CAPABILITY :: PORT_ARBITRATION_TABLE_ENTRY_SIZE [11:10] */ #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_MASK 0x00000c00 #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_PORT_ARBITRATION_TABLE_ENTRY_SIZE_SHIFT 10 /* PCIE_CFG :: PORT_VC_CAPABILITY :: REFERENCE_CLOCK [09:08] */ #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_MASK 0x00000300 #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_REFERENCE_CLOCK_SHIFT 8 /* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_1 [07:07] */ #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_MASK 0x00000080 #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_1_SHIFT 7 /* PCIE_CFG :: PORT_VC_CAPABILITY :: LOW_PRIORITY_EXTENDED_VC_COUNT [06:04] */ #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_MASK 0x00000070 #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_LOW_PRIORITY_EXTENDED_VC_COUNT_SHIFT 4 /* PCIE_CFG :: PORT_VC_CAPABILITY :: RESERVED_2 [03:03] */ #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_MASK 0x00000008 #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_RESERVED_2_SHIFT 3 /* PCIE_CFG :: PORT_VC_CAPABILITY :: EXTENDED_VC_COUNT [02:00] */ #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_MASK 0x00000007 #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_EXTENDED_VC_COUNT_SHIFT 0 /*************************************************************************** *PORT_VC_CAPABILITY_2 - PORT_VC_CAPABILITY_2 Register ***************************************************************************/ /* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: VC_ARBITRATION_TABLE_OFFSET [31:24] */ #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_MASK 0xff000000 #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_TABLE_OFFSET_SHIFT 24 /* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: RESERVED_0 [23:08] */ #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_MASK 0x00ffff00 #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_2_RESERVED_0_SHIFT 8 /* PCIE_CFG :: PORT_VC_CAPABILITY_2 :: VC_ARBITRATION_CAPABILITY [07:00] */ #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_MASK 0x000000ff #define BCHP_PCIE_CFG_PORT_VC_CAPABILITY_2_VC_ARBITRATION_CAPABILITY_SHIFT 0 /*************************************************************************** *PORT_VC_STATUS_CONTROL - PORT_VC_STATUS_CONTROL Register ***************************************************************************/ /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: RESERVED_0 [31:17] */ #define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_MASK 0xfffe0000 #define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_0_SHIFT 17 /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: VC_ARBITRATION_TABLE_STATUS [16:16] */ #define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_MASK 0x00010000 #define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_TABLE_STATUS_SHIFT 16 /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: RESERVED_1 [15:04] */ #define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_MASK 0x0000fff0 #define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_RESERVED_1_SHIFT 4 /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: VC_ARBITRATION_SELECT [03:01] */ #define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_MASK 0x0000000e #define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_VC_ARBITRATION_SELECT_SHIFT 1 /* PCIE_CFG :: PORT_VC_STATUS_CONTROL :: LOAD_VC_ARBITRATION_TABLE [00:00] */ #define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_MASK 0x00000001 #define BCHP_PCIE_CFG_PORT_VC_STATUS_CONTROL_LOAD_VC_ARBITRATION_TABLE_SHIFT 0 /*************************************************************************** *VC_RESOURCE_CAPABILITY - VC_RESOURCE_CAPABILITY Register ***************************************************************************/ /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: PORT_ARBITRATION_TABLE_OFFSET [31:24] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_MASK 0xff000000 #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_TABLE_OFFSET_SHIFT 24 /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: RESERVED_0 [23:23] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_MASK 0x00800000 #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_0_SHIFT 23 /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: MAXIMUM_TIME_SLOTS [22:16] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_MASK 0x007f0000 #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_MAXIMUM_TIME_SLOTS_SHIFT 16 /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: REJECT_SNOOP_TRANSACTIONS [15:15] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_MASK 0x00008000 #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_REJECT_SNOOP_TRANSACTIONS_SHIFT 15 /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: ADVANCED_PACKET_SWITCHING [14:14] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_MASK 0x00004000 #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_ADVANCED_PACKET_SWITCHING_SHIFT 14 /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: RESERVED_1 [13:08] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_MASK 0x00003f00 #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_RESERVED_1_SHIFT 8 /* PCIE_CFG :: VC_RESOURCE_CAPABILITY :: PORT_ARBITRATION_CAPABILITY [07:00] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_MASK 0x000000ff #define BCHP_PCIE_CFG_VC_RESOURCE_CAPABILITY_PORT_ARBITRATION_CAPABILITY_SHIFT 0 /*************************************************************************** *VC_RESOURCE_CONTROL - VC_RESOURCE_CONTROL Register ***************************************************************************/ /* PCIE_CFG :: VC_RESOURCE_CONTROL :: VC_ENABLE [31:31] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_MASK 0x80000000 #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_VC_ENABLE_SHIFT 31 /* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_0 [30:27] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_MASK 0x78000000 #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_0_SHIFT 27 /* PCIE_CFG :: VC_RESOURCE_CONTROL :: VC_ID [26:24] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_MASK 0x07000000 #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_VC_ID_SHIFT 24 /* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_1 [23:20] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_MASK 0x00f00000 #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_1_SHIFT 20 /* PCIE_CFG :: VC_RESOURCE_CONTROL :: PORT_ARBITRATION_SELECT [19:17] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_MASK 0x000e0000 #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_PORT_ARBITRATION_SELECT_SHIFT 17 /* PCIE_CFG :: VC_RESOURCE_CONTROL :: LOAD_PORT_ARBITRATION_TABLE [16:16] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_MASK 0x00010000 #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_LOAD_PORT_ARBITRATION_TABLE_SHIFT 16 /* PCIE_CFG :: VC_RESOURCE_CONTROL :: RESERVED_2 [15:08] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_MASK 0x0000ff00 #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_RESERVED_2_SHIFT 8 /* PCIE_CFG :: VC_RESOURCE_CONTROL :: TC_VC_MAP [07:00] */ #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_MASK 0x000000ff #define BCHP_PCIE_CFG_VC_RESOURCE_CONTROL_TC_VC_MAP_SHIFT 0 /*************************************************************************** *VC_RESOURCE_STATUS - VC_RESOURCE_STATUS Register ***************************************************************************/ /* PCIE_CFG :: VC_RESOURCE_STATUS :: RESERVED_0 [31:18] */ #define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_MASK 0xfffc0000 #define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_0_SHIFT 18 /* PCIE_CFG :: VC_RESOURCE_STATUS :: VC_NEGOTIATION_PENDING [17:17] */ #define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_MASK 0x00020000 #define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_VC_NEGOTIATION_PENDING_SHIFT 17 /* PCIE_CFG :: VC_RESOURCE_STATUS :: PORT_ARBITRATION_TABLE_STATUS [16:16] */ #define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_MASK 0x00010000 #define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_PORT_ARBITRATION_TABLE_STATUS_SHIFT 16 /* PCIE_CFG :: VC_RESOURCE_STATUS :: RESERVED_1 [15:00] */ #define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_MASK 0x0000ffff #define BCHP_PCIE_CFG_VC_RESOURCE_STATUS_RESERVED_1_SHIFT 0 /*************************************************************************** *DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER - DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER Register ***************************************************************************/ /* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ #define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 #define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 /* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ #define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 #define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 /* PCIE_CFG :: DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ #define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff #define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 /*************************************************************************** *DEVICE_SERIAL_NO_LOWER_DW - DEVICE_SERIAL_NO_LOWER_DW Register ***************************************************************************/ /* PCIE_CFG :: DEVICE_SERIAL_NO_LOWER_DW :: SERIAL_NO_LOWER [31:00] */ #define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_MASK 0xffffffff #define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_LOWER_DW_SERIAL_NO_LOWER_SHIFT 0 /*************************************************************************** *DEVICE_SERIAL_NO_UPPER_DW - DEVICE_SERIAL_NO_UPPER_DW Register ***************************************************************************/ /* PCIE_CFG :: DEVICE_SERIAL_NO_UPPER_DW :: SERIAL_NO_UPPER [31:00] */ #define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_MASK 0xffffffff #define BCHP_PCIE_CFG_DEVICE_SERIAL_NO_UPPER_DW_SERIAL_NO_UPPER_SHIFT 0 /*************************************************************************** *POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER - POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER Register ***************************************************************************/ /* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: NEXT_CAPABILITY_OFFSET [31:20] */ #define BCHP_PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_MASK 0xfff00000 #define BCHP_PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_NEXT_CAPABILITY_OFFSET_SHIFT 20 /* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: CAPABILITY_VERSION [19:16] */ #define BCHP_PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_MASK 0x000f0000 #define BCHP_PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_CAPABILITY_VERSION_SHIFT 16 /* PCIE_CFG :: POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER :: PCIE_EXTENDED_CAPABILITY_ID [15:00] */ #define BCHP_PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_MASK 0x0000ffff #define BCHP_PCIE_CFG_POWER_BUDGETING_ENHANCED_CAPABILITY_HEADER_PCIE_EXTENDED_CAPABILITY_ID_SHIFT 0 /*************************************************************************** *POWER_BUDGETING_DATA_SELECT - POWER_BUDGETING_DATA_SELECT Register ***************************************************************************/ /* PCIE_CFG :: POWER_BUDGETING_DATA_SELECT :: RESERVED_0 [31:08] */ #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_MASK 0xffffff00 #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_SELECT_RESERVED_0_SHIFT 8 /* PCIE_CFG :: POWER_BUDGETING_DATA_SELECT :: DATA_SELECT [07:00] */ #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_MASK 0x000000ff #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_SELECT_DATA_SELECT_SHIFT 0 /*************************************************************************** *POWER_BUDGETING_DATA - POWER_BUDGETING_DATA Register ***************************************************************************/ /* PCIE_CFG :: POWER_BUDGETING_DATA :: RESERVED_0 [31:21] */ #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_MASK 0xffe00000 #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_RESERVED_0_SHIFT 21 /* PCIE_CFG :: POWER_BUDGETING_DATA :: POWER_RAIL [20:18] */ #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_MASK 0x001c0000 #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_POWER_RAIL_SHIFT 18 /* PCIE_CFG :: POWER_BUDGETING_DATA :: TYPE [17:15] */ #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_TYPE_MASK 0x00038000 #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_TYPE_SHIFT 15 /* PCIE_CFG :: POWER_BUDGETING_DATA :: PM_STATE [14:13] */ #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_MASK 0x00006000 #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_PM_STATE_SHIFT 13 /* PCIE_CFG :: POWER_BUDGETING_DATA :: PM_SUB_STATE [12:10] */ #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_MASK 0x00001c00 #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_PM_SUB_STATE_SHIFT 10 /* PCIE_CFG :: POWER_BUDGETING_DATA :: DATA_SCALE [09:08] */ #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_MASK 0x00000300 #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_DATA_SCALE_SHIFT 8 /* PCIE_CFG :: POWER_BUDGETING_DATA :: BASE_POWER [07:00] */ #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_MASK 0x000000ff #define BCHP_PCIE_CFG_POWER_BUDGETING_DATA_BASE_POWER_SHIFT 0 /*************************************************************************** *POWER_BUDGETING_CAPABILITY - POWER_BUDGETING_CAPABILITY Register ***************************************************************************/ /* PCIE_CFG :: POWER_BUDGETING_CAPABILITY :: RESERVED_0 [31:01] */ #define BCHP_PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_MASK 0xfffffffe #define BCHP_PCIE_CFG_POWER_BUDGETING_CAPABILITY_RESERVED_0_SHIFT 1 /* PCIE_CFG :: POWER_BUDGETING_CAPABILITY :: LOM_CONFIGURATION [00:00] */ #define BCHP_PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_MASK 0x00000001 #define BCHP_PCIE_CFG_POWER_BUDGETING_CAPABILITY_LOM_CONFIGURATION_SHIFT 0 /*************************************************************************** *FIRMWARE_POWER_BUDGETING_2_1 - FIRMWARE_POWER_BUDGETING_2_1 Register ***************************************************************************/ /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: POWER_RAIL_2 [31:29] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_MASK 0xe0000000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_2_SHIFT 29 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: TYPE_2 [28:26] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_MASK 0x1c000000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_2_SHIFT 26 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: PM_STATE_2 [25:24] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_MASK 0x03000000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_2_SHIFT 24 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: BASE_POWER_2 [23:16] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_MASK 0x00ff0000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_2_SHIFT 16 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: POWER_RAIL_1 [15:13] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_MASK 0x0000e000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_POWER_RAIL_1_SHIFT 13 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: TYPE_1 [12:10] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_MASK 0x00001c00 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_TYPE_1_SHIFT 10 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: PM_STATE_1 [09:08] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_MASK 0x00000300 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_PM_STATE_1_SHIFT 8 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_2_1 :: BASE_POWER_1 [07:00] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_MASK 0x000000ff #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_2_1_BASE_POWER_1_SHIFT 0 /*************************************************************************** *FIRMWARE_POWER_BUDGETING_4_3 - FIRMWARE_POWER_BUDGETING_4_3 Register ***************************************************************************/ /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: POWER_RAIL_4 [31:29] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_MASK 0xe0000000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_4_SHIFT 29 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: TYPE_4 [28:26] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_MASK 0x1c000000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_4_SHIFT 26 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: PM_STATE_4 [25:24] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_MASK 0x03000000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_4_SHIFT 24 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: BASE_POWER_4 [23:16] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_MASK 0x00ff0000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_4_SHIFT 16 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: POWER_RAIL_3 [15:13] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_MASK 0x0000e000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_POWER_RAIL_3_SHIFT 13 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: TYPE_3 [12:10] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_MASK 0x00001c00 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_TYPE_3_SHIFT 10 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: PM_STATE_3 [09:08] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_MASK 0x00000300 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_PM_STATE_3_SHIFT 8 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_4_3 :: BASE_POWER_3 [07:00] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_MASK 0x000000ff #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_4_3_BASE_POWER_3_SHIFT 0 /*************************************************************************** *FIRMWARE_POWER_BUDGETING_6_5 - FIRMWARE_POWER_BUDGETING_6_5 Register ***************************************************************************/ /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: POWER_RAIL_6 [31:29] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_MASK 0xe0000000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_6_SHIFT 29 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: TYPE_6 [28:26] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_MASK 0x1c000000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_6_SHIFT 26 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: PM_STATE_6 [25:24] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_MASK 0x03000000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_6_SHIFT 24 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: BASE_POWER_6 [23:16] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_MASK 0x00ff0000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_6_SHIFT 16 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: POWER_RAIL_5 [15:13] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_MASK 0x0000e000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_POWER_RAIL_5_SHIFT 13 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: TYPE_5 [12:10] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_MASK 0x00001c00 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_TYPE_5_SHIFT 10 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: PM_STATE_5 [09:08] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_MASK 0x00000300 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_PM_STATE_5_SHIFT 8 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_6_5 :: BASE_POWER_5 [07:00] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_MASK 0x000000ff #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_6_5_BASE_POWER_5_SHIFT 0 /*************************************************************************** *FIRMWARE_POWER_BUDGETING_8_7 - FIRMWARE_POWER_BUDGETING_8_7 Register ***************************************************************************/ /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: POWER_RAIL_8 [31:29] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_MASK 0xe0000000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_8_SHIFT 29 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: TYPE_8 [28:26] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_MASK 0x1c000000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_8_SHIFT 26 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: PM_STATE_8 [25:24] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_MASK 0x03000000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_8_SHIFT 24 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: BASE_POWER_8 [23:16] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_MASK 0x00ff0000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_8_SHIFT 16 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: POWER_RAIL_7 [15:13] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_MASK 0x0000e000 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_POWER_RAIL_7_SHIFT 13 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: TYPE_7 [12:10] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_MASK 0x00001c00 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_TYPE_7_SHIFT 10 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: PM_STATE_7 [09:08] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_MASK 0x00000300 #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_PM_STATE_7_SHIFT 8 /* PCIE_CFG :: FIRMWARE_POWER_BUDGETING_8_7 :: BASE_POWER_7 [07:00] */ #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_MASK 0x000000ff #define BCHP_PCIE_CFG_FIRMWARE_POWER_BUDGETING_8_7_BASE_POWER_7_SHIFT 0 /*************************************************************************** *PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING - PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING Register ***************************************************************************/ /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: UNUSED_0 [31:07] */ #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_MASK 0xffffff80 #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNUSED_0_SHIFT 7 /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: D3HOT_MEMORY_READ_ADVISORY_NON_FATAL [06:06] */ #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_MASK 0x00000040 #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_D3HOT_MEMORY_READ_ADVISORY_NON_FATAL_SHIFT 6 /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: RETRY_POISON_ENABLE [05:05] */ #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_MASK 0x00000020 #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_RETRY_POISON_ENABLE_SHIFT 5 /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: POISON_ADVISORY_NON_FATAL_ENABLE [04:04] */ #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000010 #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_POISON_ADVISORY_NON_FATAL_ENABLE_SHIFT 4 /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: UNEXPECTED_ADVISORY_NON_FATAL_ENABLE [03:03] */ #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000008 #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_UNEXPECTED_ADVISORY_NON_FATAL_ENABLE_SHIFT 3 /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE [02:02] */ #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000004 #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NON_POSTED_CFG_ADVISORY_NON_FATAL_ENABLE_SHIFT 2 /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE [01:01] */ #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000002 #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_NP_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_SHIFT 1 /* PCIE_CFG :: PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING :: COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE [00:00] */ #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_MASK 0x00000001 #define BCHP_PCIE_CFG_PCIE_1_1_ADVISORY_NON_FATAL_ERROR_MASKING_COMPLETION_ABORT_MEMORY_READ_ADVISORY_NON_FATAL_ENABLE_SHIFT 0 #endif /* #ifndef BCHP_PCIE_CFG_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016400000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_starch_regs.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_ar0000644000175000017500000002544611610313111031025 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_arb_starch_regs.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:15p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:16 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_starch_regs.h $ * * Hydra_Software_Devel/1 7/17/09 8:15p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_ARB_STARCH_REGS_H__ #define BCHP_PRI_ARB_STARCH_REGS_H__ /*************************************************************************** *PRI_ARB_STARCH_REGS - PRIMARY_ARB secure static address range checker registers ***************************************************************************/ #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG 0x00461200 /* Address Range Checker control register */ #define BCHP_PRI_ARB_STARCH_REGS_ADRS_RANGE_LOW 0x00461220 /* Address Range Checker memory range lower address register */ #define BCHP_PRI_ARB_STARCH_REGS_ADRS_RANGE_HIGH 0x00461240 /* Address Range Checker memory range upper address register */ #define BCHP_PRI_ARB_STARCH_REGS_READ_RIGHTS_0_ 0x00461260 /* Address Range Checker read access rights for clients #0 through #19. */ #define BCHP_PRI_ARB_STARCH_REGS_WRITE_RIGHTS_0_ 0x004612c0 /* Address Range Checker write access rights for clients #0 through #19. */ #define BCHP_PRI_ARB_STARCH_REGS_VIOL_ADDR 0x00461340 /* Address Range Checker violating command address. */ #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO 0x00461360 /* Address Range Checker violating command information. */ #define BCHP_PRI_ARB_STARCH_REGS_STATUS_CLEAR 0x00461380 /* Address Range Checker violating command status release. */ #define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE 0x004613c0 /* Memory Size register */ /*************************************************************************** *CNTRL_REG - Address Range Checker control register ***************************************************************************/ /* PRI_ARB_STARCH_REGS :: CNTRL_REG :: reserved0 [31:06] */ #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_reserved0_MASK 0xffffffc0 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_reserved0_SHIFT 6 /* PRI_ARB_STARCH_REGS :: CNTRL_REG :: READ_ABORT [05:05] */ #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_ABORT_MASK 0x00000020 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_ABORT_SHIFT 5 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_ABORT_DISABLED 0 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_ABORT_ENABLED 1 /* PRI_ARB_STARCH_REGS :: CNTRL_REG :: WRITE_ABORT [04:04] */ #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_ABORT_MASK 0x00000010 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_ABORT_SHIFT 4 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_ABORT_DISABLED 0 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_ABORT_ENABLED 1 /* PRI_ARB_STARCH_REGS :: CNTRL_REG :: WRITE_CHECK [03:03] */ #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_CHECK_MASK 0x00000008 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_CHECK_SHIFT 3 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_CHECK_DISABLED 0 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_WRITE_CHECK_ENABLED 1 /* PRI_ARB_STARCH_REGS :: CNTRL_REG :: READ_CHECK [02:02] */ #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_CHECK_MASK 0x00000004 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_CHECK_SHIFT 2 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_CHECK_DISABLED 0 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_READ_CHECK_ENABLED 1 /* PRI_ARB_STARCH_REGS :: CNTRL_REG :: MODE [01:00] */ #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_MODE_MASK 0x00000003 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_MODE_SHIFT 0 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_MODE_NON_EXCLUSIVE 0 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_MODE_EXCLUSIVE 1 #define BCHP_PRI_ARB_STARCH_REGS_CNTRL_REG_MODE_ULTRA_EXCLUSIVE 2 /*************************************************************************** *ADRS_RANGE_LOW - Address Range Checker memory range lower address register ***************************************************************************/ /* PRI_ARB_STARCH_REGS :: ADRS_RANGE_LOW :: ADDRESS [31:00] */ #define BCHP_PRI_ARB_STARCH_REGS_ADRS_RANGE_LOW_ADDRESS_MASK 0xffffffff #define BCHP_PRI_ARB_STARCH_REGS_ADRS_RANGE_LOW_ADDRESS_SHIFT 0 /*************************************************************************** *ADRS_RANGE_HIGH - Address Range Checker memory range upper address register ***************************************************************************/ /* PRI_ARB_STARCH_REGS :: ADRS_RANGE_HIGH :: ADDRESS [31:00] */ #define BCHP_PRI_ARB_STARCH_REGS_ADRS_RANGE_HIGH_ADDRESS_MASK 0xffffffff #define BCHP_PRI_ARB_STARCH_REGS_ADRS_RANGE_HIGH_ADDRESS_SHIFT 0 /*************************************************************************** *READ_RIGHTS_0_ - Address Range Checker read access rights for clients #0 through #19. ***************************************************************************/ /* PRI_ARB_STARCH_REGS :: READ_RIGHTS_0_ :: ACCESS_RIGHT [31:00] */ #define BCHP_PRI_ARB_STARCH_REGS_READ_RIGHTS_0__ACCESS_RIGHT_MASK 0xffffffff #define BCHP_PRI_ARB_STARCH_REGS_READ_RIGHTS_0__ACCESS_RIGHT_SHIFT 0 /*************************************************************************** *WRITE_RIGHTS_0_ - Address Range Checker write access rights for clients #0 through #19. ***************************************************************************/ /* PRI_ARB_STARCH_REGS :: WRITE_RIGHTS_0_ :: ACCESS_RIGHT [31:00] */ #define BCHP_PRI_ARB_STARCH_REGS_WRITE_RIGHTS_0__ACCESS_RIGHT_MASK 0xffffffff #define BCHP_PRI_ARB_STARCH_REGS_WRITE_RIGHTS_0__ACCESS_RIGHT_SHIFT 0 /*************************************************************************** *VIOL_ADDR - Address Range Checker violating command address. ***************************************************************************/ /* PRI_ARB_STARCH_REGS :: VIOL_ADDR :: ADDRESS [31:00] */ #define BCHP_PRI_ARB_STARCH_REGS_VIOL_ADDR_ADDRESS_MASK 0xffffffff #define BCHP_PRI_ARB_STARCH_REGS_VIOL_ADDR_ADDRESS_SHIFT 0 /*************************************************************************** *VIOL_INFO - Address Range Checker violating command information. ***************************************************************************/ /* PRI_ARB_STARCH_REGS :: VIOL_INFO :: CLIENTID [31:24] */ #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_CLIENTID_MASK 0xff000000 #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_CLIENTID_SHIFT 24 /* PRI_ARB_STARCH_REGS :: VIOL_INFO :: reserved0 [23:22] */ #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_reserved0_MASK 0x00c00000 #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_reserved0_SHIFT 22 /* PRI_ARB_STARCH_REGS :: VIOL_INFO :: LENGTH [21:12] */ #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_LENGTH_MASK 0x003ff000 #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_LENGTH_SHIFT 12 /* PRI_ARB_STARCH_REGS :: VIOL_INFO :: MODE [11:09] */ #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_MODE_MASK 0x00000e00 #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_MODE_SHIFT 9 /* PRI_ARB_STARCH_REGS :: VIOL_INFO :: WRITE [08:08] */ #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_WRITE_MASK 0x00000100 #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_WRITE_SHIFT 8 /* PRI_ARB_STARCH_REGS :: VIOL_INFO :: reserved1 [07:01] */ #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_reserved1_MASK 0x000000fe #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_reserved1_SHIFT 1 /* PRI_ARB_STARCH_REGS :: VIOL_INFO :: STATUS [00:00] */ #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_STATUS_MASK 0x00000001 #define BCHP_PRI_ARB_STARCH_REGS_VIOL_INFO_STATUS_SHIFT 0 /*************************************************************************** *STATUS_CLEAR - Address Range Checker violating command status release. ***************************************************************************/ /* PRI_ARB_STARCH_REGS :: STATUS_CLEAR :: reserved0 [31:01] */ #define BCHP_PRI_ARB_STARCH_REGS_STATUS_CLEAR_reserved0_MASK 0xfffffffe #define BCHP_PRI_ARB_STARCH_REGS_STATUS_CLEAR_reserved0_SHIFT 1 /* PRI_ARB_STARCH_REGS :: STATUS_CLEAR :: CLEAR [00:00] */ #define BCHP_PRI_ARB_STARCH_REGS_STATUS_CLEAR_CLEAR_MASK 0x00000001 #define BCHP_PRI_ARB_STARCH_REGS_STATUS_CLEAR_CLEAR_SHIFT 0 /*************************************************************************** *MEMORY_SIZE - Memory Size register ***************************************************************************/ /* PRI_ARB_STARCH_REGS :: MEMORY_SIZE :: reserved0 [31:02] */ #define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_reserved0_MASK 0xfffffffc #define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_reserved0_SHIFT 2 /* PRI_ARB_STARCH_REGS :: MEMORY_SIZE :: DDR_SIZE [01:00] */ #define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_DDR_SIZE_MASK 0x00000003 #define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_DDR_SIZE_SHIFT 0 #define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_DDR_SIZE_SIZE_64_MB 0 #define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_DDR_SIZE_SIZE_128_MB 1 #define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_DDR_SIZE_SIZE_256_MB 2 #define BCHP_PRI_ARB_STARCH_REGS_MEMORY_SIZE_DDR_SIZE_SIZE_512_MB 3 #endif /* #ifndef BCHP_PRI_ARB_STARCH_REGS_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016200000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuregs2_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000001005611610313111030763 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_cpuregs2_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:02p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:17 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuregs2_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:02p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_CPUREGS2_0_H__ #define BCHP_DECODE_CPUREGS2_0_H__ /*************************************************************************** *DECODE_CPUREGS2_0 - Outer Loop CPU Registers 0 ***************************************************************************/ #define BCHP_DECODE_CPUREGS2_0_REG_HST2CPU_MBX 0x00800f80 /* Host 2 CPU mailbox register */ #define BCHP_DECODE_CPUREGS2_0_REG_CPU2HST_MBX 0x00800f84 /* CPU to Host mailbox register */ #define BCHP_DECODE_CPUREGS2_0_REG_MBX_STAT 0x00800f88 /* Mailbox status flags */ #define BCHP_DECODE_CPUREGS2_0_REG_INST_BASE 0x00800f8c /* Instruction base address register */ #define BCHP_DECODE_CPUREGS2_0_REG_CPU_INT_ENA 0x00800f90 /* CPU interrupt enable */ #define BCHP_DECODE_CPUREGS2_0_REG_CPU_INT_STAT 0x00800f94 /* CPU interrupt status */ #define BCHP_DECODE_CPUREGS2_0_REG_HST2CPU_STAT 0x00800f98 /* Host to CPU status register */ #define BCHP_DECODE_CPUREGS2_0_REG_CPU2HST_STAT 0x00800f9c /* CPU to Host status register */ #define BCHP_DECODE_CPUREGS2_0_REG_CPU_INTGEN_SET 0x00800fa0 /* CPU interrupt set register */ #define BCHP_DECODE_CPUREGS2_0_REG_CPU_INTGEN_CLR 0x00800fa4 /* CPU interrupt clear register */ #define BCHP_DECODE_CPUREGS2_0_REG_CPU_ICACHE_MISS 0x00800fa8 /* Instruction cache miss counter */ #define BCHP_DECODE_CPUREGS2_0_REG_CPU_INTGEN_MASK 0x00800fac /* CPU interrupt mask register */ #define BCHP_DECODE_CPUREGS2_0_REG_END_OF_CODE 0x00800fb4 /* End of code register */ #define BCHP_DECODE_CPUREGS2_0_REG_GLOBAL_IO_BASE 0x00800fb8 /* Global IO base register */ #define BCHP_DECODE_CPUREGS2_0_REG_DEBUG_TRACE_FIFO_WR 0x00800fbc /* CPU debug trace fifo write */ #define BCHP_DECODE_CPUREGS2_0_REG_DEBUG_TRACE_FIFO_RD 0x00800fc0 /* CPU debug trace fifo read */ #define BCHP_DECODE_CPUREGS2_0_REG_DEBUG_TRACE_FIFO_CTL 0x00800fc4 /* CPU debug trace fifo control */ #define BCHP_DECODE_CPUREGS2_0_REG_WATCHDOG_TMR 0x00800fcc /* Watchdog timer register */ #define BCHP_DECODE_CPUREGS2_0_REG_SDRAM_STATUS 0x00800fd0 /* SDRAM Status register */ #define BCHP_DECODE_CPUREGS2_0_REG_CPUREGS_END 0x00800ffc /* Dummy end */ #endif /* #ifndef BCHP_DECODE_CPUREGS2_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016400000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_gr_bridge.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_m0000644000175000017500000001237311610313111031031 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_wrap_misc_gr_bridge.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:22p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:38 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_gr_bridge.h $ * * Hydra_Software_Devel/1 7/17/09 8:22p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_WRAP_MISC_GR_BRIDGE_H__ #define BCHP_WRAP_MISC_GR_BRIDGE_H__ /*************************************************************************** *WRAP_MISC_GR_BRIDGE ***************************************************************************/ #define BCHP_WRAP_MISC_GR_BRIDGE_REVISION 0x000f1000 /* GR Bridge Revision */ #define BCHP_WRAP_MISC_GR_BRIDGE_CTRL 0x000f1004 /* GR Bridge Control Register */ #define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_0 0x000f1008 /* GR Bridge Software Reset 0 Register */ #define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_1 0x000f100c /* GR Bridge Software Reset 1 Register */ /*************************************************************************** *REVISION - GR Bridge Revision ***************************************************************************/ /* WRAP_MISC_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define BCHP_WRAP_MISC_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define BCHP_WRAP_MISC_GR_BRIDGE_REVISION_reserved0_SHIFT 16 /* WRAP_MISC_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define BCHP_WRAP_MISC_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_WRAP_MISC_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* WRAP_MISC_GR_BRIDGE :: REVISION :: MINOR [07:00] */ #define BCHP_WRAP_MISC_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define BCHP_WRAP_MISC_GR_BRIDGE_REVISION_MINOR_SHIFT 0 /*************************************************************************** *CTRL - GR Bridge Control Register ***************************************************************************/ /* WRAP_MISC_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ #define BCHP_WRAP_MISC_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe #define BCHP_WRAP_MISC_GR_BRIDGE_CTRL_reserved0_SHIFT 1 /* WRAP_MISC_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ #define BCHP_WRAP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 #define BCHP_WRAP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 #define BCHP_WRAP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 #define BCHP_WRAP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 /*************************************************************************** *SW_RESET_0 - GR Bridge Software Reset 0 Register ***************************************************************************/ /* WRAP_MISC_GR_BRIDGE :: SW_RESET_0 :: reserved0 [31:01] */ #define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_0_reserved0_MASK 0xfffffffe #define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_0_reserved0_SHIFT 1 /* WRAP_MISC_GR_BRIDGE :: SW_RESET_0 :: SW_RESET [00:00] */ #define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_0_SW_RESET_MASK 0x00000001 #define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_0_SW_RESET_SHIFT 0 #define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_0_SW_RESET_DEASSERT 0 #define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_0_SW_RESET_ASSERT 1 /*************************************************************************** *SW_RESET_1 - GR Bridge Software Reset 1 Register ***************************************************************************/ /* WRAP_MISC_GR_BRIDGE :: SW_RESET_1 :: reserved0 [31:00] */ #define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_1_reserved0_MASK 0xffffffff #define BCHP_WRAP_MISC_GR_BRIDGE_SW_RESET_1_reserved0_SHIFT 0 #endif /* #ifndef BCHP_WRAP_MISC_GR_BRIDGE_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016000000000000011562 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_intr2.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_m0000644000175000017500000021116311610313111031027 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_wrap_misc_intr2.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:23p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:21 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_intr2.h $ * * Hydra_Software_Devel/1 7/17/09 8:23p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_WRAP_MISC_INTR2_H__ #define BCHP_WRAP_MISC_INTR2_H__ /*************************************************************************** *WRAP_MISC_INTR2 - MISC block Level 2 Interrupt Controller ***************************************************************************/ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS 0x000f2000 /* CPU interrupt Status Register */ #define BCHP_WRAP_MISC_INTR2_CPU_SET 0x000f2004 /* CPU interrupt Set Register */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR 0x000f2008 /* CPU interrupt Clear Register */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS 0x000f200c /* CPU interrupt Mask Status Register */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET 0x000f2010 /* CPU interrupt Mask Set Register */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR 0x000f2014 /* CPU interrupt Mask Clear Register */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS 0x000f2018 /* PCI interrupt Status Register */ #define BCHP_WRAP_MISC_INTR2_PCI_SET 0x000f201c /* PCI interrupt Set Register */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR 0x000f2020 /* PCI interrupt Clear Register */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS 0x000f2024 /* PCI interrupt Mask Status Register */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET 0x000f2028 /* PCI interrupt Mask Set Register */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR 0x000f202c /* PCI interrupt Mask Clear Register */ /*************************************************************************** *CPU_STATUS - CPU interrupt Status Register ***************************************************************************/ /* WRAP_MISC_INTR2 :: CPU_STATUS :: reserved0 [31:24] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_reserved0_MASK 0xff000000 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_reserved0_SHIFT 24 /* WRAP_MISC_INTR2 :: CPU_STATUS :: BOOT_VER_FAIL_INTR [23:23] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_FAIL_INTR_MASK 0x00800000 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_FAIL_INTR_SHIFT 23 /* WRAP_MISC_INTR2 :: CPU_STATUS :: BOOT_VER_DONE_INTR [22:22] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_DONE_INTR_MASK 0x00400000 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_DONE_INTR_SHIFT 22 /* WRAP_MISC_INTR2 :: CPU_STATUS :: PREMATURE_ARM_REQ_INTR [21:21] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PREMATURE_ARM_REQ_INTR_MASK 0x00200000 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PREMATURE_ARM_REQ_INTR_SHIFT 21 /* WRAP_MISC_INTR2 :: CPU_STATUS :: BAD_STARCH_CFG_INTR [20:20] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BAD_STARCH_CFG_INTR_MASK 0x00100000 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BAD_STARCH_CFG_INTR_SHIFT 20 /* WRAP_MISC_INTR2 :: CPU_STATUS :: SCRM_KEY_DONE_INTR [19:19] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SCRM_KEY_DONE_INTR_MASK 0x00080000 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SCRM_KEY_DONE_INTR_SHIFT 19 /* WRAP_MISC_INTR2 :: CPU_STATUS :: BORCH_ERROR_INTR [18:18] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BORCH_ERROR_INTR_MASK 0x00040000 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_BORCH_ERROR_INTR_SHIFT 18 /* WRAP_MISC_INTR2 :: CPU_STATUS :: GR_BRIDGE_ERROR_INTR [17:17] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_GR_BRIDGE_ERROR_INTR_MASK 0x00020000 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_GR_BRIDGE_ERROR_INTR_SHIFT 17 /* WRAP_MISC_INTR2 :: CPU_STATUS :: MEM_DMA_INTR [16:16] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_MEM_DMA_INTR_MASK 0x00010000 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_MEM_DMA_INTR_SHIFT 16 /* WRAP_MISC_INTR2 :: CPU_STATUS :: PCI_MBOX4_INTR [15:15] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX4_INTR_MASK 0x00008000 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX4_INTR_SHIFT 15 /* WRAP_MISC_INTR2 :: CPU_STATUS :: PCI_MBOX3_INTR [14:14] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX3_INTR_MASK 0x00004000 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX3_INTR_SHIFT 14 /* WRAP_MISC_INTR2 :: CPU_STATUS :: PCI_MBOX2_INTR [13:13] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX2_INTR_MASK 0x00002000 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX2_INTR_SHIFT 13 /* WRAP_MISC_INTR2 :: CPU_STATUS :: PCI_MBOX1_INTR [12:12] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX1_INTR_MASK 0x00001000 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_PCI_MBOX1_INTR_SHIFT 12 /* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_MBOX4_INTR [11:11] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX4_INTR_MASK 0x00000800 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX4_INTR_SHIFT 11 /* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_MBOX3_INTR [10:10] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX3_INTR_MASK 0x00000400 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX3_INTR_SHIFT 10 /* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_MBOX2_INTR [09:09] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX2_INTR_MASK 0x00000200 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX2_INTR_SHIFT 9 /* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_MBOX1_INTR [08:08] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX1_INTR_MASK 0x00000100 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_MBOX1_INTR_SHIFT 8 /* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_FAIL2_INTR [07:07] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL2_INTR_MASK 0x00000080 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL2_INTR_SHIFT 7 /* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_FAIL1_INTR [06:06] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL1_INTR_MASK 0x00000040 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL1_INTR_SHIFT 6 /* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_FAIL0_INTR [05:05] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL0_INTR_MASK 0x00000020 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_FAIL0_INTR_SHIFT 5 /* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_ERR_INTR [04:04] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_ERR_INTR_MASK 0x00000010 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_ERR_INTR_SHIFT 4 /* WRAP_MISC_INTR2 :: CPU_STATUS :: SHARF_MEM_DMA0_DONE [03:03] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_MEM_DMA0_DONE_MASK 0x00000008 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_MEM_DMA0_DONE_SHIFT 3 /* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_UART_INTR [02:02] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_INTR_MASK 0x00000004 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_INTR_SHIFT 2 /* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_UART_RCV_INTR [01:01] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_RCV_INTR_MASK 0x00000002 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_RCV_INTR_SHIFT 1 /* WRAP_MISC_INTR2 :: CPU_STATUS :: ARM_UART_XMIT_INTR [00:00] */ #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_XMIT_INTR_MASK 0x00000001 #define BCHP_WRAP_MISC_INTR2_CPU_STATUS_ARM_UART_XMIT_INTR_SHIFT 0 /*************************************************************************** *CPU_SET - CPU interrupt Set Register ***************************************************************************/ /* WRAP_MISC_INTR2 :: CPU_SET :: reserved0 [31:24] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_reserved0_MASK 0xff000000 #define BCHP_WRAP_MISC_INTR2_CPU_SET_reserved0_SHIFT 24 /* WRAP_MISC_INTR2 :: CPU_SET :: BOOT_VER_FAIL_INTR [23:23] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_BOOT_VER_FAIL_INTR_MASK 0x00800000 #define BCHP_WRAP_MISC_INTR2_CPU_SET_BOOT_VER_FAIL_INTR_SHIFT 23 /* WRAP_MISC_INTR2 :: CPU_SET :: BOOT_VER_DONE_INTR [22:22] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_BOOT_VER_DONE_INTR_MASK 0x00400000 #define BCHP_WRAP_MISC_INTR2_CPU_SET_BOOT_VER_DONE_INTR_SHIFT 22 /* WRAP_MISC_INTR2 :: CPU_SET :: PREMATURE_ARM_REQ_INTR [21:21] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_PREMATURE_ARM_REQ_INTR_MASK 0x00200000 #define BCHP_WRAP_MISC_INTR2_CPU_SET_PREMATURE_ARM_REQ_INTR_SHIFT 21 /* WRAP_MISC_INTR2 :: CPU_SET :: BAD_STARCH_CFG_INTR [20:20] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_BAD_STARCH_CFG_INTR_MASK 0x00100000 #define BCHP_WRAP_MISC_INTR2_CPU_SET_BAD_STARCH_CFG_INTR_SHIFT 20 /* WRAP_MISC_INTR2 :: CPU_SET :: SCRM_KEY_DONE_INTR [19:19] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_SCRM_KEY_DONE_INTR_MASK 0x00080000 #define BCHP_WRAP_MISC_INTR2_CPU_SET_SCRM_KEY_DONE_INTR_SHIFT 19 /* WRAP_MISC_INTR2 :: CPU_SET :: BORCH_ERROR_INTR [18:18] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_BORCH_ERROR_INTR_MASK 0x00040000 #define BCHP_WRAP_MISC_INTR2_CPU_SET_BORCH_ERROR_INTR_SHIFT 18 /* WRAP_MISC_INTR2 :: CPU_SET :: GR_BRIDGE_ERROR_INTR [17:17] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_GR_BRIDGE_ERROR_INTR_MASK 0x00020000 #define BCHP_WRAP_MISC_INTR2_CPU_SET_GR_BRIDGE_ERROR_INTR_SHIFT 17 /* WRAP_MISC_INTR2 :: CPU_SET :: MEM_DMA_INTR [16:16] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_MEM_DMA_INTR_MASK 0x00010000 #define BCHP_WRAP_MISC_INTR2_CPU_SET_MEM_DMA_INTR_SHIFT 16 /* WRAP_MISC_INTR2 :: CPU_SET :: PCI_MBOX4_INTR [15:15] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX4_INTR_MASK 0x00008000 #define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX4_INTR_SHIFT 15 /* WRAP_MISC_INTR2 :: CPU_SET :: PCI_MBOX3_INTR [14:14] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX3_INTR_MASK 0x00004000 #define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX3_INTR_SHIFT 14 /* WRAP_MISC_INTR2 :: CPU_SET :: PCI_MBOX2_INTR [13:13] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX2_INTR_MASK 0x00002000 #define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX2_INTR_SHIFT 13 /* WRAP_MISC_INTR2 :: CPU_SET :: PCI_MBOX1_INTR [12:12] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX1_INTR_MASK 0x00001000 #define BCHP_WRAP_MISC_INTR2_CPU_SET_PCI_MBOX1_INTR_SHIFT 12 /* WRAP_MISC_INTR2 :: CPU_SET :: ARM_MBOX4_INTR [11:11] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX4_INTR_MASK 0x00000800 #define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX4_INTR_SHIFT 11 /* WRAP_MISC_INTR2 :: CPU_SET :: ARM_MBOX3_INTR [10:10] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX3_INTR_MASK 0x00000400 #define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX3_INTR_SHIFT 10 /* WRAP_MISC_INTR2 :: CPU_SET :: ARM_MBOX2_INTR [09:09] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX2_INTR_MASK 0x00000200 #define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX2_INTR_SHIFT 9 /* WRAP_MISC_INTR2 :: CPU_SET :: ARM_MBOX1_INTR [08:08] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX1_INTR_MASK 0x00000100 #define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_MBOX1_INTR_SHIFT 8 /* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_FAIL2_INTR [07:07] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL2_INTR_MASK 0x00000080 #define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL2_INTR_SHIFT 7 /* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_FAIL1_INTR [06:06] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL1_INTR_MASK 0x00000040 #define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL1_INTR_SHIFT 6 /* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_FAIL0_INTR [05:05] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL0_INTR_MASK 0x00000020 #define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_FAIL0_INTR_SHIFT 5 /* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_ERR_INTR [04:04] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_ERR_INTR_MASK 0x00000010 #define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_ERR_INTR_SHIFT 4 /* WRAP_MISC_INTR2 :: CPU_SET :: SHARF_MEM_DMA0_DONE [03:03] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_MEM_DMA0_DONE_MASK 0x00000008 #define BCHP_WRAP_MISC_INTR2_CPU_SET_SHARF_MEM_DMA0_DONE_SHIFT 3 /* WRAP_MISC_INTR2 :: CPU_SET :: ARM_UART_INTR [02:02] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_INTR_MASK 0x00000004 #define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_INTR_SHIFT 2 /* WRAP_MISC_INTR2 :: CPU_SET :: ARM_UART_RCV_INTR [01:01] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_RCV_INTR_MASK 0x00000002 #define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_RCV_INTR_SHIFT 1 /* WRAP_MISC_INTR2 :: CPU_SET :: ARM_UART_XMIT_INTR [00:00] */ #define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_XMIT_INTR_MASK 0x00000001 #define BCHP_WRAP_MISC_INTR2_CPU_SET_ARM_UART_XMIT_INTR_SHIFT 0 /*************************************************************************** *CPU_CLEAR - CPU interrupt Clear Register ***************************************************************************/ /* WRAP_MISC_INTR2 :: CPU_CLEAR :: reserved0 [31:24] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_reserved0_MASK 0xff000000 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_reserved0_SHIFT 24 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: BOOT_VER_FAIL_INTR [23:23] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BOOT_VER_FAIL_INTR_MASK 0x00800000 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BOOT_VER_FAIL_INTR_SHIFT 23 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: BOOT_VER_DONE_INTR [22:22] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BOOT_VER_DONE_INTR_MASK 0x00400000 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BOOT_VER_DONE_INTR_SHIFT 22 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: PREMATURE_ARM_REQ_INTR [21:21] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PREMATURE_ARM_REQ_INTR_MASK 0x00200000 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PREMATURE_ARM_REQ_INTR_SHIFT 21 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: BAD_STARCH_CFG_INTR [20:20] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BAD_STARCH_CFG_INTR_MASK 0x00100000 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BAD_STARCH_CFG_INTR_SHIFT 20 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: SCRM_KEY_DONE_INTR [19:19] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SCRM_KEY_DONE_INTR_MASK 0x00080000 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SCRM_KEY_DONE_INTR_SHIFT 19 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: BORCH_ERROR_INTR [18:18] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BORCH_ERROR_INTR_MASK 0x00040000 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_BORCH_ERROR_INTR_SHIFT 18 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: GR_BRIDGE_ERROR_INTR [17:17] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_GR_BRIDGE_ERROR_INTR_MASK 0x00020000 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_GR_BRIDGE_ERROR_INTR_SHIFT 17 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: MEM_DMA_INTR [16:16] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_MEM_DMA_INTR_MASK 0x00010000 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_MEM_DMA_INTR_SHIFT 16 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: PCI_MBOX4_INTR [15:15] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX4_INTR_MASK 0x00008000 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX4_INTR_SHIFT 15 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: PCI_MBOX3_INTR [14:14] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX3_INTR_MASK 0x00004000 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX3_INTR_SHIFT 14 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: PCI_MBOX2_INTR [13:13] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX2_INTR_MASK 0x00002000 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX2_INTR_SHIFT 13 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: PCI_MBOX1_INTR [12:12] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX1_INTR_MASK 0x00001000 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_PCI_MBOX1_INTR_SHIFT 12 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_MBOX4_INTR [11:11] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX4_INTR_MASK 0x00000800 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX4_INTR_SHIFT 11 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_MBOX3_INTR [10:10] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX3_INTR_MASK 0x00000400 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX3_INTR_SHIFT 10 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_MBOX2_INTR [09:09] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX2_INTR_MASK 0x00000200 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX2_INTR_SHIFT 9 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_MBOX1_INTR [08:08] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX1_INTR_MASK 0x00000100 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_MBOX1_INTR_SHIFT 8 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_FAIL2_INTR [07:07] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL2_INTR_MASK 0x00000080 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL2_INTR_SHIFT 7 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_FAIL1_INTR [06:06] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL1_INTR_MASK 0x00000040 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL1_INTR_SHIFT 6 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_FAIL0_INTR [05:05] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL0_INTR_MASK 0x00000020 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_FAIL0_INTR_SHIFT 5 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_ERR_INTR [04:04] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_ERR_INTR_MASK 0x00000010 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_ERR_INTR_SHIFT 4 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: SHARF_MEM_DMA0_DONE [03:03] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_MEM_DMA0_DONE_MASK 0x00000008 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_SHARF_MEM_DMA0_DONE_SHIFT 3 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_UART_INTR [02:02] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_INTR_MASK 0x00000004 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_INTR_SHIFT 2 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_UART_RCV_INTR [01:01] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_RCV_INTR_MASK 0x00000002 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_RCV_INTR_SHIFT 1 /* WRAP_MISC_INTR2 :: CPU_CLEAR :: ARM_UART_XMIT_INTR [00:00] */ #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_XMIT_INTR_MASK 0x00000001 #define BCHP_WRAP_MISC_INTR2_CPU_CLEAR_ARM_UART_XMIT_INTR_SHIFT 0 /*************************************************************************** *CPU_MASK_STATUS - CPU interrupt Mask Status Register ***************************************************************************/ /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:24] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_reserved0_MASK 0xff000000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_reserved0_SHIFT 24 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: BOOT_VER_FAIL_MASK [23:23] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BOOT_VER_FAIL_MASK_MASK 0x00800000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BOOT_VER_FAIL_MASK_SHIFT 23 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: BOOT_VER_DONE_MASK [22:22] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BOOT_VER_DONE_MASK_MASK 0x00400000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BOOT_VER_DONE_MASK_SHIFT 22 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PREMATURE_ARM_REQ_MASK [21:21] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PREMATURE_ARM_REQ_MASK_MASK 0x00200000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PREMATURE_ARM_REQ_MASK_SHIFT 21 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: BAD_STARCH_CFG_MASK [20:20] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BAD_STARCH_CFG_MASK_MASK 0x00100000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BAD_STARCH_CFG_MASK_SHIFT 20 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SCRM_KEY_DONE_MASK [19:19] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SCRM_KEY_DONE_MASK_MASK 0x00080000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SCRM_KEY_DONE_MASK_SHIFT 19 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: BORCH_ERROR_MASK [18:18] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BORCH_ERROR_MASK_MASK 0x00040000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_BORCH_ERROR_MASK_SHIFT 18 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: GR_BRIDGE_ERROR_MASK [17:17] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_GR_BRIDGE_ERROR_MASK_MASK 0x00020000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_GR_BRIDGE_ERROR_MASK_SHIFT 17 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: MEM_DMA_MASK [16:16] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_MEM_DMA_MASK_MASK 0x00010000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_MEM_DMA_MASK_SHIFT 16 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PCI_MBOX4_MASK [15:15] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX4_MASK_MASK 0x00008000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX4_MASK_SHIFT 15 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PCI_MBOX3_MASK [14:14] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX3_MASK_MASK 0x00004000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX3_MASK_SHIFT 14 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PCI_MBOX2_MASK [13:13] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX2_MASK_MASK 0x00002000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX2_MASK_SHIFT 13 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: PCI_MBOX1_MASK [12:12] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX1_MASK_MASK 0x00001000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_PCI_MBOX1_MASK_SHIFT 12 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_MBOX4_MASK [11:11] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX4_MASK_MASK 0x00000800 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX4_MASK_SHIFT 11 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_MBOX3_MASK [10:10] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX3_MASK_MASK 0x00000400 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX3_MASK_SHIFT 10 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_MBOX2_MASK [09:09] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX2_MASK_MASK 0x00000200 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX2_MASK_SHIFT 9 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_MBOX1_MASK [08:08] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX1_MASK_MASK 0x00000100 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_MBOX1_MASK_SHIFT 8 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_FAIL2_MASK [07:07] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL2_MASK_MASK 0x00000080 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL2_MASK_SHIFT 7 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_FAIL1_MASK [06:06] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL1_MASK_MASK 0x00000040 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL1_MASK_SHIFT 6 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_FAIL0_MASK [05:05] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL0_MASK_MASK 0x00000020 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_FAIL0_MASK_SHIFT 5 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_ERR_MASK [04:04] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_ERR_MASK_MASK 0x00000010 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_ERR_MASK_SHIFT 4 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: SHARF_MEM_DMA0_DONE_MASK [03:03] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_UART_MASK [02:02] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_MASK_MASK 0x00000004 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_MASK_SHIFT 2 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_UART_RCV_MASK [01:01] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_RCV_MASK_MASK 0x00000002 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_RCV_MASK_SHIFT 1 /* WRAP_MISC_INTR2 :: CPU_MASK_STATUS :: ARM_UART_XMIT_MASK [00:00] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_XMIT_MASK_MASK 0x00000001 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_STATUS_ARM_UART_XMIT_MASK_SHIFT 0 /*************************************************************************** *CPU_MASK_SET - CPU interrupt Mask Set Register ***************************************************************************/ /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: reserved0 [31:24] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_reserved0_MASK 0xff000000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_reserved0_SHIFT 24 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: BOOT_VER_FAIL_MASK [23:23] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BOOT_VER_FAIL_MASK_MASK 0x00800000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BOOT_VER_FAIL_MASK_SHIFT 23 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: BOOT_VER_DONE_MASK [22:22] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BOOT_VER_DONE_MASK_MASK 0x00400000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BOOT_VER_DONE_MASK_SHIFT 22 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PREMATURE_ARM_REQ_MASK [21:21] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PREMATURE_ARM_REQ_MASK_MASK 0x00200000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PREMATURE_ARM_REQ_MASK_SHIFT 21 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: BAD_STARCH_CFG_MASK [20:20] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BAD_STARCH_CFG_MASK_MASK 0x00100000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BAD_STARCH_CFG_MASK_SHIFT 20 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SCRM_KEY_DONE_MASK [19:19] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SCRM_KEY_DONE_MASK_MASK 0x00080000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SCRM_KEY_DONE_MASK_SHIFT 19 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: BORCH_ERROR_MASK [18:18] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BORCH_ERROR_MASK_MASK 0x00040000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_BORCH_ERROR_MASK_SHIFT 18 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: GR_BRIDGE_ERROR_MASK [17:17] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_GR_BRIDGE_ERROR_MASK_MASK 0x00020000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_GR_BRIDGE_ERROR_MASK_SHIFT 17 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: MEM_DMA_MASK [16:16] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_MEM_DMA_MASK_MASK 0x00010000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_MEM_DMA_MASK_SHIFT 16 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PCI_MBOX4_MASK [15:15] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX4_MASK_MASK 0x00008000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX4_MASK_SHIFT 15 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PCI_MBOX3_MASK [14:14] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX3_MASK_MASK 0x00004000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX3_MASK_SHIFT 14 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PCI_MBOX2_MASK [13:13] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX2_MASK_MASK 0x00002000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX2_MASK_SHIFT 13 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: PCI_MBOX1_MASK [12:12] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX1_MASK_MASK 0x00001000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_PCI_MBOX1_MASK_SHIFT 12 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_MBOX4_MASK [11:11] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX4_MASK_MASK 0x00000800 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX4_MASK_SHIFT 11 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_MBOX3_MASK [10:10] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX3_MASK_MASK 0x00000400 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX3_MASK_SHIFT 10 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_MBOX2_MASK [09:09] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX2_MASK_MASK 0x00000200 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX2_MASK_SHIFT 9 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_MBOX1_MASK [08:08] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX1_MASK_MASK 0x00000100 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_MBOX1_MASK_SHIFT 8 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_FAIL2_MASK [07:07] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL2_MASK_MASK 0x00000080 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL2_MASK_SHIFT 7 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_FAIL1_MASK [06:06] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL1_MASK_MASK 0x00000040 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL1_MASK_SHIFT 6 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_FAIL0_MASK [05:05] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL0_MASK_MASK 0x00000020 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_FAIL0_MASK_SHIFT 5 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_ERR_MASK [04:04] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_ERR_MASK_MASK 0x00000010 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_ERR_MASK_SHIFT 4 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: SHARF_MEM_DMA0_DONE_MASK [03:03] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_UART_MASK [02:02] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_MASK_MASK 0x00000004 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_MASK_SHIFT 2 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_UART_RCV_MASK [01:01] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_RCV_MASK_MASK 0x00000002 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_RCV_MASK_SHIFT 1 /* WRAP_MISC_INTR2 :: CPU_MASK_SET :: ARM_UART_XMIT_MASK [00:00] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_XMIT_MASK_MASK 0x00000001 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_SET_ARM_UART_XMIT_MASK_SHIFT 0 /*************************************************************************** *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register ***************************************************************************/ /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:24] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_reserved0_MASK 0xff000000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT 24 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: BOOT_VER_FAIL_MASK [23:23] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BOOT_VER_FAIL_MASK_MASK 0x00800000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BOOT_VER_FAIL_MASK_SHIFT 23 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: BOOT_VER_DONE_MASK [22:22] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BOOT_VER_DONE_MASK_MASK 0x00400000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BOOT_VER_DONE_MASK_SHIFT 22 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PREMATURE_ARM_REQ_MASK [21:21] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PREMATURE_ARM_REQ_MASK_MASK 0x00200000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PREMATURE_ARM_REQ_MASK_SHIFT 21 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: BAD_STARCH_CFG_MASK [20:20] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BAD_STARCH_CFG_MASK_MASK 0x00100000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BAD_STARCH_CFG_MASK_SHIFT 20 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SCRM_KEY_DONE_MASK [19:19] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SCRM_KEY_DONE_MASK_MASK 0x00080000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SCRM_KEY_DONE_MASK_SHIFT 19 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: BORCH_ERROR_MASK [18:18] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BORCH_ERROR_MASK_MASK 0x00040000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_BORCH_ERROR_MASK_SHIFT 18 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: GR_BRIDGE_ERROR_MASK [17:17] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_GR_BRIDGE_ERROR_MASK_MASK 0x00020000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_GR_BRIDGE_ERROR_MASK_SHIFT 17 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: MEM_DMA_MASK [16:16] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_MEM_DMA_MASK_MASK 0x00010000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_MEM_DMA_MASK_SHIFT 16 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PCI_MBOX4_MASK [15:15] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX4_MASK_MASK 0x00008000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX4_MASK_SHIFT 15 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PCI_MBOX3_MASK [14:14] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX3_MASK_MASK 0x00004000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX3_MASK_SHIFT 14 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PCI_MBOX2_MASK [13:13] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX2_MASK_MASK 0x00002000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX2_MASK_SHIFT 13 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: PCI_MBOX1_MASK [12:12] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX1_MASK_MASK 0x00001000 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_PCI_MBOX1_MASK_SHIFT 12 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_MBOX4_MASK [11:11] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX4_MASK_MASK 0x00000800 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX4_MASK_SHIFT 11 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_MBOX3_MASK [10:10] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX3_MASK_MASK 0x00000400 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX3_MASK_SHIFT 10 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_MBOX2_MASK [09:09] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX2_MASK_MASK 0x00000200 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX2_MASK_SHIFT 9 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_MBOX1_MASK [08:08] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX1_MASK_MASK 0x00000100 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_MBOX1_MASK_SHIFT 8 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_FAIL2_MASK [07:07] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL2_MASK_MASK 0x00000080 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL2_MASK_SHIFT 7 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_FAIL1_MASK [06:06] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL1_MASK_MASK 0x00000040 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL1_MASK_SHIFT 6 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_FAIL0_MASK [05:05] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL0_MASK_MASK 0x00000020 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_FAIL0_MASK_SHIFT 5 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_ERR_MASK [04:04] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_ERR_MASK_MASK 0x00000010 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_ERR_MASK_SHIFT 4 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: SHARF_MEM_DMA0_DONE_MASK [03:03] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_UART_MASK [02:02] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_MASK_MASK 0x00000004 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_MASK_SHIFT 2 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_UART_RCV_MASK [01:01] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_RCV_MASK_MASK 0x00000002 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_RCV_MASK_SHIFT 1 /* WRAP_MISC_INTR2 :: CPU_MASK_CLEAR :: ARM_UART_XMIT_MASK [00:00] */ #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_XMIT_MASK_MASK 0x00000001 #define BCHP_WRAP_MISC_INTR2_CPU_MASK_CLEAR_ARM_UART_XMIT_MASK_SHIFT 0 /*************************************************************************** *PCI_STATUS - PCI interrupt Status Register ***************************************************************************/ /* WRAP_MISC_INTR2 :: PCI_STATUS :: reserved0 [31:24] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_reserved0_MASK 0xff000000 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_reserved0_SHIFT 24 /* WRAP_MISC_INTR2 :: PCI_STATUS :: BOOT_VER_FAIL_INTR [23:23] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BOOT_VER_FAIL_INTR_MASK 0x00800000 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BOOT_VER_FAIL_INTR_SHIFT 23 /* WRAP_MISC_INTR2 :: PCI_STATUS :: BOOT_VER_DONE_INTR [22:22] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BOOT_VER_DONE_INTR_MASK 0x00400000 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BOOT_VER_DONE_INTR_SHIFT 22 /* WRAP_MISC_INTR2 :: PCI_STATUS :: PREMATURE_ARM_REQ_INTR [21:21] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PREMATURE_ARM_REQ_INTR_MASK 0x00200000 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PREMATURE_ARM_REQ_INTR_SHIFT 21 /* WRAP_MISC_INTR2 :: PCI_STATUS :: BAD_STARCH_CFG_INTR [20:20] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BAD_STARCH_CFG_INTR_MASK 0x00100000 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BAD_STARCH_CFG_INTR_SHIFT 20 /* WRAP_MISC_INTR2 :: PCI_STATUS :: SCRM_KEY_DONE_INTR [19:19] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SCRM_KEY_DONE_INTR_MASK 0x00080000 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SCRM_KEY_DONE_INTR_SHIFT 19 /* WRAP_MISC_INTR2 :: PCI_STATUS :: BORCH_ERROR_INTR [18:18] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BORCH_ERROR_INTR_MASK 0x00040000 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_BORCH_ERROR_INTR_SHIFT 18 /* WRAP_MISC_INTR2 :: PCI_STATUS :: GR_BRIDGE_ERROR_INTR [17:17] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_GR_BRIDGE_ERROR_INTR_MASK 0x00020000 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_GR_BRIDGE_ERROR_INTR_SHIFT 17 /* WRAP_MISC_INTR2 :: PCI_STATUS :: MEM_DMA_INTR [16:16] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_MEM_DMA_INTR_MASK 0x00010000 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_MEM_DMA_INTR_SHIFT 16 /* WRAP_MISC_INTR2 :: PCI_STATUS :: PCI_MBOX4_INTR [15:15] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX4_INTR_MASK 0x00008000 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX4_INTR_SHIFT 15 /* WRAP_MISC_INTR2 :: PCI_STATUS :: PCI_MBOX3_INTR [14:14] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX3_INTR_MASK 0x00004000 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX3_INTR_SHIFT 14 /* WRAP_MISC_INTR2 :: PCI_STATUS :: PCI_MBOX2_INTR [13:13] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX2_INTR_MASK 0x00002000 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX2_INTR_SHIFT 13 /* WRAP_MISC_INTR2 :: PCI_STATUS :: PCI_MBOX1_INTR [12:12] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX1_INTR_MASK 0x00001000 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_PCI_MBOX1_INTR_SHIFT 12 /* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_MBOX4_INTR [11:11] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX4_INTR_MASK 0x00000800 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX4_INTR_SHIFT 11 /* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_MBOX3_INTR [10:10] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX3_INTR_MASK 0x00000400 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX3_INTR_SHIFT 10 /* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_MBOX2_INTR [09:09] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX2_INTR_MASK 0x00000200 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX2_INTR_SHIFT 9 /* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_MBOX1_INTR [08:08] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX1_INTR_MASK 0x00000100 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_MBOX1_INTR_SHIFT 8 /* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_FAIL2_INTR [07:07] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL2_INTR_MASK 0x00000080 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL2_INTR_SHIFT 7 /* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_FAIL1_INTR [06:06] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL1_INTR_MASK 0x00000040 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL1_INTR_SHIFT 6 /* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_FAIL0_INTR [05:05] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL0_INTR_MASK 0x00000020 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_FAIL0_INTR_SHIFT 5 /* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_ERR_INTR [04:04] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_ERR_INTR_MASK 0x00000010 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_ERR_INTR_SHIFT 4 /* WRAP_MISC_INTR2 :: PCI_STATUS :: SHARF_MEM_DMA0_DONE [03:03] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_MEM_DMA0_DONE_MASK 0x00000008 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_SHARF_MEM_DMA0_DONE_SHIFT 3 /* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_UART_INTR [02:02] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_INTR_MASK 0x00000004 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_INTR_SHIFT 2 /* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_UART_RCV_INTR [01:01] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_RCV_INTR_MASK 0x00000002 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_RCV_INTR_SHIFT 1 /* WRAP_MISC_INTR2 :: PCI_STATUS :: ARM_UART_XMIT_INTR [00:00] */ #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_XMIT_INTR_MASK 0x00000001 #define BCHP_WRAP_MISC_INTR2_PCI_STATUS_ARM_UART_XMIT_INTR_SHIFT 0 /*************************************************************************** *PCI_SET - PCI interrupt Set Register ***************************************************************************/ /* WRAP_MISC_INTR2 :: PCI_SET :: reserved0 [31:24] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_reserved0_MASK 0xff000000 #define BCHP_WRAP_MISC_INTR2_PCI_SET_reserved0_SHIFT 24 /* WRAP_MISC_INTR2 :: PCI_SET :: BOOT_VER_FAIL_INTR [23:23] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_BOOT_VER_FAIL_INTR_MASK 0x00800000 #define BCHP_WRAP_MISC_INTR2_PCI_SET_BOOT_VER_FAIL_INTR_SHIFT 23 /* WRAP_MISC_INTR2 :: PCI_SET :: BOOT_VER_DONE_INTR [22:22] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_BOOT_VER_DONE_INTR_MASK 0x00400000 #define BCHP_WRAP_MISC_INTR2_PCI_SET_BOOT_VER_DONE_INTR_SHIFT 22 /* WRAP_MISC_INTR2 :: PCI_SET :: PREMATURE_ARM_REQ_INTR [21:21] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_PREMATURE_ARM_REQ_INTR_MASK 0x00200000 #define BCHP_WRAP_MISC_INTR2_PCI_SET_PREMATURE_ARM_REQ_INTR_SHIFT 21 /* WRAP_MISC_INTR2 :: PCI_SET :: BAD_STARCH_CFG_INTR [20:20] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_BAD_STARCH_CFG_INTR_MASK 0x00100000 #define BCHP_WRAP_MISC_INTR2_PCI_SET_BAD_STARCH_CFG_INTR_SHIFT 20 /* WRAP_MISC_INTR2 :: PCI_SET :: SCRM_KEY_DONE_INTR [19:19] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_SCRM_KEY_DONE_INTR_MASK 0x00080000 #define BCHP_WRAP_MISC_INTR2_PCI_SET_SCRM_KEY_DONE_INTR_SHIFT 19 /* WRAP_MISC_INTR2 :: PCI_SET :: BORCH_ERROR_INTR [18:18] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_BORCH_ERROR_INTR_MASK 0x00040000 #define BCHP_WRAP_MISC_INTR2_PCI_SET_BORCH_ERROR_INTR_SHIFT 18 /* WRAP_MISC_INTR2 :: PCI_SET :: GR_BRIDGE_ERROR_INTR [17:17] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_GR_BRIDGE_ERROR_INTR_MASK 0x00020000 #define BCHP_WRAP_MISC_INTR2_PCI_SET_GR_BRIDGE_ERROR_INTR_SHIFT 17 /* WRAP_MISC_INTR2 :: PCI_SET :: MEM_DMA_INTR [16:16] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_MEM_DMA_INTR_MASK 0x00010000 #define BCHP_WRAP_MISC_INTR2_PCI_SET_MEM_DMA_INTR_SHIFT 16 /* WRAP_MISC_INTR2 :: PCI_SET :: PCI_MBOX4_INTR [15:15] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX4_INTR_MASK 0x00008000 #define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX4_INTR_SHIFT 15 /* WRAP_MISC_INTR2 :: PCI_SET :: PCI_MBOX3_INTR [14:14] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX3_INTR_MASK 0x00004000 #define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX3_INTR_SHIFT 14 /* WRAP_MISC_INTR2 :: PCI_SET :: PCI_MBOX2_INTR [13:13] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX2_INTR_MASK 0x00002000 #define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX2_INTR_SHIFT 13 /* WRAP_MISC_INTR2 :: PCI_SET :: PCI_MBOX1_INTR [12:12] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX1_INTR_MASK 0x00001000 #define BCHP_WRAP_MISC_INTR2_PCI_SET_PCI_MBOX1_INTR_SHIFT 12 /* WRAP_MISC_INTR2 :: PCI_SET :: ARM_MBOX4_INTR [11:11] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX4_INTR_MASK 0x00000800 #define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX4_INTR_SHIFT 11 /* WRAP_MISC_INTR2 :: PCI_SET :: ARM_MBOX3_INTR [10:10] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX3_INTR_MASK 0x00000400 #define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX3_INTR_SHIFT 10 /* WRAP_MISC_INTR2 :: PCI_SET :: ARM_MBOX2_INTR [09:09] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX2_INTR_MASK 0x00000200 #define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX2_INTR_SHIFT 9 /* WRAP_MISC_INTR2 :: PCI_SET :: ARM_MBOX1_INTR [08:08] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX1_INTR_MASK 0x00000100 #define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_MBOX1_INTR_SHIFT 8 /* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_FAIL2_INTR [07:07] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL2_INTR_MASK 0x00000080 #define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL2_INTR_SHIFT 7 /* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_FAIL1_INTR [06:06] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL1_INTR_MASK 0x00000040 #define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL1_INTR_SHIFT 6 /* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_FAIL0_INTR [05:05] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL0_INTR_MASK 0x00000020 #define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_FAIL0_INTR_SHIFT 5 /* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_ERR_INTR [04:04] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_ERR_INTR_MASK 0x00000010 #define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_ERR_INTR_SHIFT 4 /* WRAP_MISC_INTR2 :: PCI_SET :: SHARF_MEM_DMA0_DONE [03:03] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_MEM_DMA0_DONE_MASK 0x00000008 #define BCHP_WRAP_MISC_INTR2_PCI_SET_SHARF_MEM_DMA0_DONE_SHIFT 3 /* WRAP_MISC_INTR2 :: PCI_SET :: ARM_UART_INTR [02:02] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_INTR_MASK 0x00000004 #define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_INTR_SHIFT 2 /* WRAP_MISC_INTR2 :: PCI_SET :: ARM_UART_RCV_INTR [01:01] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_RCV_INTR_MASK 0x00000002 #define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_RCV_INTR_SHIFT 1 /* WRAP_MISC_INTR2 :: PCI_SET :: ARM_UART_XMIT_INTR [00:00] */ #define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_XMIT_INTR_MASK 0x00000001 #define BCHP_WRAP_MISC_INTR2_PCI_SET_ARM_UART_XMIT_INTR_SHIFT 0 /*************************************************************************** *PCI_CLEAR - PCI interrupt Clear Register ***************************************************************************/ /* WRAP_MISC_INTR2 :: PCI_CLEAR :: reserved0 [31:24] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_reserved0_MASK 0xff000000 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_reserved0_SHIFT 24 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: BOOT_VER_FAIL_INTR [23:23] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BOOT_VER_FAIL_INTR_MASK 0x00800000 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BOOT_VER_FAIL_INTR_SHIFT 23 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: BOOT_VER_DONE_INTR [22:22] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BOOT_VER_DONE_INTR_MASK 0x00400000 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BOOT_VER_DONE_INTR_SHIFT 22 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: PREMATURE_ARM_REQ_INTR [21:21] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PREMATURE_ARM_REQ_INTR_MASK 0x00200000 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PREMATURE_ARM_REQ_INTR_SHIFT 21 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: BAD_STARCH_CFG_INTR [20:20] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BAD_STARCH_CFG_INTR_MASK 0x00100000 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BAD_STARCH_CFG_INTR_SHIFT 20 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: SCRM_KEY_DONE_INTR [19:19] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SCRM_KEY_DONE_INTR_MASK 0x00080000 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SCRM_KEY_DONE_INTR_SHIFT 19 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: BORCH_ERROR_INTR [18:18] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BORCH_ERROR_INTR_MASK 0x00040000 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_BORCH_ERROR_INTR_SHIFT 18 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: GR_BRIDGE_ERROR_INTR [17:17] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_GR_BRIDGE_ERROR_INTR_MASK 0x00020000 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_GR_BRIDGE_ERROR_INTR_SHIFT 17 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: MEM_DMA_INTR [16:16] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_MEM_DMA_INTR_MASK 0x00010000 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_MEM_DMA_INTR_SHIFT 16 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: PCI_MBOX4_INTR [15:15] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX4_INTR_MASK 0x00008000 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX4_INTR_SHIFT 15 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: PCI_MBOX3_INTR [14:14] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX3_INTR_MASK 0x00004000 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX3_INTR_SHIFT 14 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: PCI_MBOX2_INTR [13:13] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX2_INTR_MASK 0x00002000 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX2_INTR_SHIFT 13 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: PCI_MBOX1_INTR [12:12] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX1_INTR_MASK 0x00001000 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_PCI_MBOX1_INTR_SHIFT 12 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_MBOX4_INTR [11:11] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX4_INTR_MASK 0x00000800 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX4_INTR_SHIFT 11 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_MBOX3_INTR [10:10] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX3_INTR_MASK 0x00000400 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX3_INTR_SHIFT 10 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_MBOX2_INTR [09:09] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX2_INTR_MASK 0x00000200 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX2_INTR_SHIFT 9 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_MBOX1_INTR [08:08] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX1_INTR_MASK 0x00000100 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_MBOX1_INTR_SHIFT 8 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_FAIL2_INTR [07:07] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL2_INTR_MASK 0x00000080 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL2_INTR_SHIFT 7 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_FAIL1_INTR [06:06] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL1_INTR_MASK 0x00000040 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL1_INTR_SHIFT 6 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_FAIL0_INTR [05:05] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL0_INTR_MASK 0x00000020 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_FAIL0_INTR_SHIFT 5 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_ERR_INTR [04:04] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_ERR_INTR_MASK 0x00000010 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_ERR_INTR_SHIFT 4 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: SHARF_MEM_DMA0_DONE [03:03] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_MEM_DMA0_DONE_MASK 0x00000008 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_SHARF_MEM_DMA0_DONE_SHIFT 3 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_UART_INTR [02:02] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_INTR_MASK 0x00000004 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_INTR_SHIFT 2 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_UART_RCV_INTR [01:01] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_RCV_INTR_MASK 0x00000002 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_RCV_INTR_SHIFT 1 /* WRAP_MISC_INTR2 :: PCI_CLEAR :: ARM_UART_XMIT_INTR [00:00] */ #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_XMIT_INTR_MASK 0x00000001 #define BCHP_WRAP_MISC_INTR2_PCI_CLEAR_ARM_UART_XMIT_INTR_SHIFT 0 /*************************************************************************** *PCI_MASK_STATUS - PCI interrupt Mask Status Register ***************************************************************************/ /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:24] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_reserved0_MASK 0xff000000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_reserved0_SHIFT 24 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: BOOT_VER_FAIL_MASK [23:23] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BOOT_VER_FAIL_MASK_MASK 0x00800000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BOOT_VER_FAIL_MASK_SHIFT 23 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: BOOT_VER_DONE_MASK [22:22] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BOOT_VER_DONE_MASK_MASK 0x00400000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BOOT_VER_DONE_MASK_SHIFT 22 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PREMATURE_ARM_REQ_MASK [21:21] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PREMATURE_ARM_REQ_MASK_MASK 0x00200000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PREMATURE_ARM_REQ_MASK_SHIFT 21 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: BAD_STARCH_CFG_MASK [20:20] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BAD_STARCH_CFG_MASK_MASK 0x00100000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BAD_STARCH_CFG_MASK_SHIFT 20 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SCRM_KEY_DONE_MASK [19:19] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SCRM_KEY_DONE_MASK_MASK 0x00080000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SCRM_KEY_DONE_MASK_SHIFT 19 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: BORCH_ERROR_MASK [18:18] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BORCH_ERROR_MASK_MASK 0x00040000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_BORCH_ERROR_MASK_SHIFT 18 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: GR_BRIDGE_ERROR_MASK [17:17] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_GR_BRIDGE_ERROR_MASK_MASK 0x00020000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_GR_BRIDGE_ERROR_MASK_SHIFT 17 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: MEM_DMA_MASK [16:16] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_MEM_DMA_MASK_MASK 0x00010000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_MEM_DMA_MASK_SHIFT 16 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PCI_MBOX4_MASK [15:15] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX4_MASK_MASK 0x00008000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX4_MASK_SHIFT 15 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PCI_MBOX3_MASK [14:14] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX3_MASK_MASK 0x00004000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX3_MASK_SHIFT 14 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PCI_MBOX2_MASK [13:13] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX2_MASK_MASK 0x00002000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX2_MASK_SHIFT 13 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: PCI_MBOX1_MASK [12:12] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX1_MASK_MASK 0x00001000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_PCI_MBOX1_MASK_SHIFT 12 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_MBOX4_MASK [11:11] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX4_MASK_MASK 0x00000800 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX4_MASK_SHIFT 11 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_MBOX3_MASK [10:10] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX3_MASK_MASK 0x00000400 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX3_MASK_SHIFT 10 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_MBOX2_MASK [09:09] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX2_MASK_MASK 0x00000200 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX2_MASK_SHIFT 9 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_MBOX1_MASK [08:08] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX1_MASK_MASK 0x00000100 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_MBOX1_MASK_SHIFT 8 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_FAIL2_MASK [07:07] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL2_MASK_MASK 0x00000080 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL2_MASK_SHIFT 7 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_FAIL1_MASK [06:06] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL1_MASK_MASK 0x00000040 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL1_MASK_SHIFT 6 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_FAIL0_MASK [05:05] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL0_MASK_MASK 0x00000020 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_FAIL0_MASK_SHIFT 5 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_ERR_MASK [04:04] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_ERR_MASK_MASK 0x00000010 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_ERR_MASK_SHIFT 4 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: SHARF_MEM_DMA0_DONE_MASK [03:03] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_UART_MASK [02:02] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_MASK_MASK 0x00000004 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_MASK_SHIFT 2 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_UART_RCV_MASK [01:01] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_RCV_MASK_MASK 0x00000002 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_RCV_MASK_SHIFT 1 /* WRAP_MISC_INTR2 :: PCI_MASK_STATUS :: ARM_UART_XMIT_MASK [00:00] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_XMIT_MASK_MASK 0x00000001 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_STATUS_ARM_UART_XMIT_MASK_SHIFT 0 /*************************************************************************** *PCI_MASK_SET - PCI interrupt Mask Set Register ***************************************************************************/ /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: reserved0 [31:24] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_reserved0_MASK 0xff000000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_reserved0_SHIFT 24 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: BOOT_VER_FAIL_MASK [23:23] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BOOT_VER_FAIL_MASK_MASK 0x00800000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BOOT_VER_FAIL_MASK_SHIFT 23 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: BOOT_VER_DONE_MASK [22:22] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BOOT_VER_DONE_MASK_MASK 0x00400000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BOOT_VER_DONE_MASK_SHIFT 22 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PREMATURE_ARM_REQ_MASK [21:21] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PREMATURE_ARM_REQ_MASK_MASK 0x00200000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PREMATURE_ARM_REQ_MASK_SHIFT 21 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: BAD_STARCH_CFG_MASK [20:20] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BAD_STARCH_CFG_MASK_MASK 0x00100000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BAD_STARCH_CFG_MASK_SHIFT 20 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SCRM_KEY_DONE_MASK [19:19] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SCRM_KEY_DONE_MASK_MASK 0x00080000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SCRM_KEY_DONE_MASK_SHIFT 19 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: BORCH_ERROR_MASK [18:18] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BORCH_ERROR_MASK_MASK 0x00040000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_BORCH_ERROR_MASK_SHIFT 18 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: GR_BRIDGE_ERROR_MASK [17:17] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_GR_BRIDGE_ERROR_MASK_MASK 0x00020000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_GR_BRIDGE_ERROR_MASK_SHIFT 17 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: MEM_DMA_MASK [16:16] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_MEM_DMA_MASK_MASK 0x00010000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_MEM_DMA_MASK_SHIFT 16 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PCI_MBOX4_MASK [15:15] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX4_MASK_MASK 0x00008000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX4_MASK_SHIFT 15 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PCI_MBOX3_MASK [14:14] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX3_MASK_MASK 0x00004000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX3_MASK_SHIFT 14 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PCI_MBOX2_MASK [13:13] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX2_MASK_MASK 0x00002000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX2_MASK_SHIFT 13 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: PCI_MBOX1_MASK [12:12] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX1_MASK_MASK 0x00001000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_PCI_MBOX1_MASK_SHIFT 12 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_MBOX4_MASK [11:11] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX4_MASK_MASK 0x00000800 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX4_MASK_SHIFT 11 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_MBOX3_MASK [10:10] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX3_MASK_MASK 0x00000400 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX3_MASK_SHIFT 10 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_MBOX2_MASK [09:09] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX2_MASK_MASK 0x00000200 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX2_MASK_SHIFT 9 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_MBOX1_MASK [08:08] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX1_MASK_MASK 0x00000100 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_MBOX1_MASK_SHIFT 8 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_FAIL2_MASK [07:07] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL2_MASK_MASK 0x00000080 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL2_MASK_SHIFT 7 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_FAIL1_MASK [06:06] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL1_MASK_MASK 0x00000040 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL1_MASK_SHIFT 6 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_FAIL0_MASK [05:05] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL0_MASK_MASK 0x00000020 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_FAIL0_MASK_SHIFT 5 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_ERR_MASK [04:04] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_ERR_MASK_MASK 0x00000010 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_ERR_MASK_SHIFT 4 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: SHARF_MEM_DMA0_DONE_MASK [03:03] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_UART_MASK [02:02] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_MASK_MASK 0x00000004 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_MASK_SHIFT 2 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_UART_RCV_MASK [01:01] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_RCV_MASK_MASK 0x00000002 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_RCV_MASK_SHIFT 1 /* WRAP_MISC_INTR2 :: PCI_MASK_SET :: ARM_UART_XMIT_MASK [00:00] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_XMIT_MASK_MASK 0x00000001 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_SET_ARM_UART_XMIT_MASK_SHIFT 0 /*************************************************************************** *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register ***************************************************************************/ /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:24] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_reserved0_MASK 0xff000000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT 24 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: BOOT_VER_FAIL_MASK [23:23] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BOOT_VER_FAIL_MASK_MASK 0x00800000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BOOT_VER_FAIL_MASK_SHIFT 23 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: BOOT_VER_DONE_MASK [22:22] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BOOT_VER_DONE_MASK_MASK 0x00400000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BOOT_VER_DONE_MASK_SHIFT 22 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PREMATURE_ARM_REQ_MASK [21:21] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PREMATURE_ARM_REQ_MASK_MASK 0x00200000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PREMATURE_ARM_REQ_MASK_SHIFT 21 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: BAD_STARCH_CFG_MASK [20:20] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BAD_STARCH_CFG_MASK_MASK 0x00100000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BAD_STARCH_CFG_MASK_SHIFT 20 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SCRM_KEY_DONE_MASK [19:19] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SCRM_KEY_DONE_MASK_MASK 0x00080000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SCRM_KEY_DONE_MASK_SHIFT 19 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: BORCH_ERROR_MASK [18:18] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BORCH_ERROR_MASK_MASK 0x00040000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_BORCH_ERROR_MASK_SHIFT 18 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: GR_BRIDGE_ERROR_MASK [17:17] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_GR_BRIDGE_ERROR_MASK_MASK 0x00020000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_GR_BRIDGE_ERROR_MASK_SHIFT 17 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: MEM_DMA_MASK [16:16] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_MEM_DMA_MASK_MASK 0x00010000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_MEM_DMA_MASK_SHIFT 16 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PCI_MBOX4_MASK [15:15] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX4_MASK_MASK 0x00008000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX4_MASK_SHIFT 15 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PCI_MBOX3_MASK [14:14] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX3_MASK_MASK 0x00004000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX3_MASK_SHIFT 14 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PCI_MBOX2_MASK [13:13] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX2_MASK_MASK 0x00002000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX2_MASK_SHIFT 13 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: PCI_MBOX1_MASK [12:12] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX1_MASK_MASK 0x00001000 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_PCI_MBOX1_MASK_SHIFT 12 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_MBOX4_MASK [11:11] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX4_MASK_MASK 0x00000800 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX4_MASK_SHIFT 11 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_MBOX3_MASK [10:10] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX3_MASK_MASK 0x00000400 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX3_MASK_SHIFT 10 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_MBOX2_MASK [09:09] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX2_MASK_MASK 0x00000200 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX2_MASK_SHIFT 9 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_MBOX1_MASK [08:08] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX1_MASK_MASK 0x00000100 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_MBOX1_MASK_SHIFT 8 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_FAIL2_MASK [07:07] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL2_MASK_MASK 0x00000080 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL2_MASK_SHIFT 7 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_FAIL1_MASK [06:06] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL1_MASK_MASK 0x00000040 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL1_MASK_SHIFT 6 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_FAIL0_MASK [05:05] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL0_MASK_MASK 0x00000020 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_FAIL0_MASK_SHIFT 5 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_ERR_MASK [04:04] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_ERR_MASK_MASK 0x00000010 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_ERR_MASK_SHIFT 4 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: SHARF_MEM_DMA0_DONE_MASK [03:03] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_MEM_DMA0_DONE_MASK_MASK 0x00000008 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_SHARF_MEM_DMA0_DONE_MASK_SHIFT 3 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_UART_MASK [02:02] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_MASK_MASK 0x00000004 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_MASK_SHIFT 2 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_UART_RCV_MASK [01:01] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_RCV_MASK_MASK 0x00000002 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_RCV_MASK_SHIFT 1 /* WRAP_MISC_INTR2 :: PCI_MASK_CLEAR :: ARM_UART_XMIT_MASK [00:00] */ #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_XMIT_MASK_MASK 0x00000001 #define BCHP_WRAP_MISC_INTR2_PCI_MASK_CLEAR_ARM_UART_XMIT_MASK_SHIFT 0 #endif /* #ifndef BCHP_WRAP_MISC_INTR2_H__ */ /* End of File */ crystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_clk.h0000644000175000017500000007703411610313111030550 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_clk.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:58p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:39 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_clk.h $ * * Hydra_Software_Devel/1 7/17/09 7:58p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_CLK_H__ #define BCHP_CLK_H__ /*************************************************************************** *CLK - CLOCK_GEN Registers ***************************************************************************/ #define BCHP_CLK_REVISION 0x00070000 /* clock_gen Revision register */ #define BCHP_CLK_PM_CTRL 0x00070004 /* Software power management control to turn off clocks */ #define BCHP_CLK_REGULATOR_2P5_VOLTS 0x0007003c /* 2.5V Regulator Voltage Adjustment */ #define BCHP_CLK_TEMP_MON_CTRL 0x00070040 /* Temperature monitor control. */ #define BCHP_CLK_TEMP_MON_STATUS 0x00070044 /* Temperature monitor status. */ #define BCHP_CLK_SCRATCH 0x00070070 /* clock_gen Scratch register */ #define BCHP_CLK_PLL0_ARM_DIV 0x00070110 /* Main PLL0 channel 3 ARM clock divider settings */ #define BCHP_CLK_PLL0_LOCK_CNT 0x0007011c /* Main PLL0 Lock Counter */ #define BCHP_CLK_PLL1_CTRL 0x00070120 /* Main PLL1 reset, enable, powerdown, and control */ #define BCHP_CLK_PLL1_CTRL_LO 0x00070124 /* Main PLL1 pll_ctrl low 32 bits */ #define BCHP_CLK_PLL1_AVD_DIV 0x00070128 /* Main PLL1 divider settings for VCO and channel 1 AVD clock */ #define BCHP_CLK_PLL1_SPARE2_DIV 0x0007012c /* Main PLL1 divider settings for channel 2 spare clock */ #define BCHP_CLK_PLL1_SPARE3_DIV 0x00070130 /* Main PLL1 divider settings for channel 3 spare clock */ #define BCHP_CLK_PLL1_LOCK_CNT 0x0007013c /* Main PLL1 Lock Counter */ #define BCHP_CLK_PLL_LOCK 0x00070200 /* PLL lock status */ #define BCHP_CLK_PLL_LOCK_CNTR_RESET 0x00070204 /* PLL Lock Counter Resets */ #define BCHP_CLK_PLL_TEST_SEL 0x00070208 /* PLL core test select */ #define BCHP_CLK_CLK_OBS_CTRL 0x0007020c /* Clock observation logic select */ #define BCHP_CLK_GPIO_PAD_CTRL 0x00070300 /* GPIO pad control */ #define BCHP_CLK_MISC_PAD_CTRL 0x00070304 /* MISC pad control */ /*************************************************************************** *REVISION - clock_gen Revision register ***************************************************************************/ /* CLK :: REVISION :: reserved0 [31:16] */ #define BCHP_CLK_REVISION_reserved0_MASK 0xffff0000 #define BCHP_CLK_REVISION_reserved0_SHIFT 16 /* CLK :: REVISION :: MAJOR [15:08] */ #define BCHP_CLK_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_CLK_REVISION_MAJOR_SHIFT 8 /* CLK :: REVISION :: MINOR [07:00] */ #define BCHP_CLK_REVISION_MINOR_MASK 0x000000ff #define BCHP_CLK_REVISION_MINOR_SHIFT 0 /*************************************************************************** *PM_CTRL - Software power management control to turn off clocks ***************************************************************************/ /* CLK :: PM_CTRL :: reserved_for_eco0 [31:26] */ #define BCHP_CLK_PM_CTRL_reserved_for_eco0_MASK 0xfc000000 #define BCHP_CLK_PM_CTRL_reserved_for_eco0_SHIFT 26 /* CLK :: PM_CTRL :: DIS_SUN_27_LOW_PWR [25:25] */ #define BCHP_CLK_PM_CTRL_DIS_SUN_27_LOW_PWR_MASK 0x02000000 #define BCHP_CLK_PM_CTRL_DIS_SUN_27_LOW_PWR_SHIFT 25 /* CLK :: PM_CTRL :: DIS_SUN_108_LOW_PWR [24:24] */ #define BCHP_CLK_PM_CTRL_DIS_SUN_108_LOW_PWR_MASK 0x01000000 #define BCHP_CLK_PM_CTRL_DIS_SUN_108_LOW_PWR_SHIFT 24 /* CLK :: PM_CTRL :: reserved1 [23:20] */ #define BCHP_CLK_PM_CTRL_reserved1_MASK 0x00f00000 #define BCHP_CLK_PM_CTRL_reserved1_SHIFT 20 /* CLK :: PM_CTRL :: DIS_MISC_OTP_9_CLK [19:19] */ #define BCHP_CLK_PM_CTRL_DIS_MISC_OTP_9_CLK_MASK 0x00080000 #define BCHP_CLK_PM_CTRL_DIS_MISC_OTP_9_CLK_SHIFT 19 #define BCHP_CLK_PM_CTRL_DIS_MISC_OTP_9_CLK_Enable 0 #define BCHP_CLK_PM_CTRL_DIS_MISC_OTP_9_CLK_Disable 1 /* CLK :: PM_CTRL :: DIS_ARM_CLK [18:18] */ #define BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK 0x00040000 #define BCHP_CLK_PM_CTRL_DIS_ARM_CLK_SHIFT 18 #define BCHP_CLK_PM_CTRL_DIS_ARM_CLK_Enable 0 #define BCHP_CLK_PM_CTRL_DIS_ARM_CLK_Disable 1 /* CLK :: PM_CTRL :: DIS_AVD_CLK [17:17] */ #define BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK 0x00020000 #define BCHP_CLK_PM_CTRL_DIS_AVD_CLK_SHIFT 17 #define BCHP_CLK_PM_CTRL_DIS_AVD_CLK_Enable 0 #define BCHP_CLK_PM_CTRL_DIS_AVD_CLK_Disable 1 /* CLK :: PM_CTRL :: reserved2 [16:13] */ #define BCHP_CLK_PM_CTRL_reserved2_MASK 0x0001e000 #define BCHP_CLK_PM_CTRL_reserved2_SHIFT 13 /* CLK :: PM_CTRL :: DIS_BLINK_108_CLK [12:12] */ #define BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK 0x00001000 #define BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_SHIFT 12 #define BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_Enable 0 #define BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_Disable 1 /* CLK :: PM_CTRL :: DIS_DDR_108_CLK [11:11] */ #define BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_MASK 0x00000800 #define BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_SHIFT 11 #define BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_Enable 0 #define BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_Disable 1 /* CLK :: PM_CTRL :: DIS_AVD_108_CLK [10:10] */ #define BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK 0x00000400 #define BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_SHIFT 10 #define BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_Enable 0 #define BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_Disable 1 /* CLK :: PM_CTRL :: DIS_MISC_108_CLK [09:09] */ #define BCHP_CLK_PM_CTRL_DIS_MISC_108_CLK_MASK 0x00000200 #define BCHP_CLK_PM_CTRL_DIS_MISC_108_CLK_SHIFT 9 #define BCHP_CLK_PM_CTRL_DIS_MISC_108_CLK_Enable 0 #define BCHP_CLK_PM_CTRL_DIS_MISC_108_CLK_Disable 1 /* CLK :: PM_CTRL :: reserved3 [08:05] */ #define BCHP_CLK_PM_CTRL_reserved3_MASK 0x000001e0 #define BCHP_CLK_PM_CTRL_reserved3_SHIFT 5 /* CLK :: PM_CTRL :: DIS_BLINK_216_CLK [04:04] */ #define BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK 0x00000010 #define BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_SHIFT 4 #define BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_Enable 0 #define BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_Disable 1 /* CLK :: PM_CTRL :: DIS_DDR_216_CLK [03:03] */ #define BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_MASK 0x00000008 #define BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_SHIFT 3 #define BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_Enable 0 #define BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_Disable 1 /* CLK :: PM_CTRL :: DIS_AVD_216_CLK [02:02] */ #define BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK 0x00000004 #define BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_SHIFT 2 #define BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_Enable 0 #define BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_Disable 1 /* CLK :: PM_CTRL :: DIS_MISC_216_CLK [01:01] */ #define BCHP_CLK_PM_CTRL_DIS_MISC_216_CLK_MASK 0x00000002 #define BCHP_CLK_PM_CTRL_DIS_MISC_216_CLK_SHIFT 1 #define BCHP_CLK_PM_CTRL_DIS_MISC_216_CLK_Enable 0 #define BCHP_CLK_PM_CTRL_DIS_MISC_216_CLK_Disable 1 /* CLK :: PM_CTRL :: DIS_SUN_216_CLK [00:00] */ #define BCHP_CLK_PM_CTRL_DIS_SUN_216_CLK_MASK 0x00000001 #define BCHP_CLK_PM_CTRL_DIS_SUN_216_CLK_SHIFT 0 #define BCHP_CLK_PM_CTRL_DIS_SUN_216_CLK_Enable 0 #define BCHP_CLK_PM_CTRL_DIS_SUN_216_CLK_Disable 1 /*************************************************************************** *REGULATOR_2P5_VOLTS - 2.5V Regulator Voltage Adjustment ***************************************************************************/ /* CLK :: REGULATOR_2P5_VOLTS :: reserved0 [31:04] */ #define BCHP_CLK_REGULATOR_2P5_VOLTS_reserved0_MASK 0xfffffff0 #define BCHP_CLK_REGULATOR_2P5_VOLTS_reserved0_SHIFT 4 /* CLK :: REGULATOR_2P5_VOLTS :: ADJUST [03:00] */ #define BCHP_CLK_REGULATOR_2P5_VOLTS_ADJUST_MASK 0x0000000f #define BCHP_CLK_REGULATOR_2P5_VOLTS_ADJUST_SHIFT 0 /*************************************************************************** *TEMP_MON_CTRL - Temperature monitor control. ***************************************************************************/ /* CLK :: TEMP_MON_CTRL :: reserved0 [31:10] */ #define BCHP_CLK_TEMP_MON_CTRL_reserved0_MASK 0xfffffc00 #define BCHP_CLK_TEMP_MON_CTRL_reserved0_SHIFT 10 /* CLK :: TEMP_MON_CTRL :: RESETB [09:09] */ #define BCHP_CLK_TEMP_MON_CTRL_RESETB_MASK 0x00000200 #define BCHP_CLK_TEMP_MON_CTRL_RESETB_SHIFT 9 #define BCHP_CLK_TEMP_MON_CTRL_RESETB_Reset 0 #define BCHP_CLK_TEMP_MON_CTRL_RESETB_Normal 1 /* CLK :: TEMP_MON_CTRL :: PWRDN [08:08] */ #define BCHP_CLK_TEMP_MON_CTRL_PWRDN_MASK 0x00000100 #define BCHP_CLK_TEMP_MON_CTRL_PWRDN_SHIFT 8 #define BCHP_CLK_TEMP_MON_CTRL_PWRDN_Powered_Up 0 #define BCHP_CLK_TEMP_MON_CTRL_PWRDN_Powered_Down 1 /* union - case Combined [07:00] */ /* CLK :: TEMP_MON_CTRL :: Combined :: CTRL [07:00] */ #define BCHP_CLK_TEMP_MON_CTRL_Combined_CTRL_MASK 0x000000ff #define BCHP_CLK_TEMP_MON_CTRL_Combined_CTRL_SHIFT 0 /* union - case Separate [07:00] */ /* CLK :: TEMP_MON_CTRL :: Separate :: BIAS_ADJUST [07:02] */ #define BCHP_CLK_TEMP_MON_CTRL_Separate_BIAS_ADJUST_MASK 0x000000fc #define BCHP_CLK_TEMP_MON_CTRL_Separate_BIAS_ADJUST_SHIFT 2 /* CLK :: TEMP_MON_CTRL :: Separate :: REF_PWRDN [01:01] */ #define BCHP_CLK_TEMP_MON_CTRL_Separate_REF_PWRDN_MASK 0x00000002 #define BCHP_CLK_TEMP_MON_CTRL_Separate_REF_PWRDN_SHIFT 1 #define BCHP_CLK_TEMP_MON_CTRL_Separate_REF_PWRDN_Powered_Up 0 #define BCHP_CLK_TEMP_MON_CTRL_Separate_REF_PWRDN_Powered_Down 1 /* CLK :: TEMP_MON_CTRL :: Separate :: BGAP_PWRDN [00:00] */ #define BCHP_CLK_TEMP_MON_CTRL_Separate_BGAP_PWRDN_MASK 0x00000001 #define BCHP_CLK_TEMP_MON_CTRL_Separate_BGAP_PWRDN_SHIFT 0 #define BCHP_CLK_TEMP_MON_CTRL_Separate_BGAP_PWRDN_Powered_Up 0 #define BCHP_CLK_TEMP_MON_CTRL_Separate_BGAP_PWRDN_Powered_Down 1 /*************************************************************************** *TEMP_MON_STATUS - Temperature monitor status. ***************************************************************************/ /* CLK :: TEMP_MON_STATUS :: CLK25K [31:31] */ #define BCHP_CLK_TEMP_MON_STATUS_CLK25K_MASK 0x80000000 #define BCHP_CLK_TEMP_MON_STATUS_CLK25K_SHIFT 31 /* CLK :: TEMP_MON_STATUS :: reserved0 [30:24] */ #define BCHP_CLK_TEMP_MON_STATUS_reserved0_MASK 0x7f000000 #define BCHP_CLK_TEMP_MON_STATUS_reserved0_SHIFT 24 /* CLK :: TEMP_MON_STATUS :: STROBE_COUNT [23:16] */ #define BCHP_CLK_TEMP_MON_STATUS_STROBE_COUNT_MASK 0x00ff0000 #define BCHP_CLK_TEMP_MON_STATUS_STROBE_COUNT_SHIFT 16 /* CLK :: TEMP_MON_STATUS :: reserved1 [15:09] */ #define BCHP_CLK_TEMP_MON_STATUS_reserved1_MASK 0x0000fe00 #define BCHP_CLK_TEMP_MON_STATUS_reserved1_SHIFT 9 /* CLK :: TEMP_MON_STATUS :: DATA [08:00] */ #define BCHP_CLK_TEMP_MON_STATUS_DATA_MASK 0x000001ff #define BCHP_CLK_TEMP_MON_STATUS_DATA_SHIFT 0 /*************************************************************************** *SCRATCH - clock_gen Scratch register ***************************************************************************/ /* CLK :: SCRATCH :: VALUE [31:00] */ #define BCHP_CLK_SCRATCH_VALUE_MASK 0xffffffff #define BCHP_CLK_SCRATCH_VALUE_SHIFT 0 /*************************************************************************** *PLL0_ARM_DIV - Main PLL0 channel 3 ARM clock divider settings ***************************************************************************/ /* CLK :: PLL0_ARM_DIV :: reserved0 [31:08] */ #define BCHP_CLK_PLL0_ARM_DIV_reserved0_MASK 0xffffff00 #define BCHP_CLK_PLL0_ARM_DIV_reserved0_SHIFT 8 /* CLK :: PLL0_ARM_DIV :: M3DIV [07:00] */ #define BCHP_CLK_PLL0_ARM_DIV_M3DIV_MASK 0x000000ff #define BCHP_CLK_PLL0_ARM_DIV_M3DIV_SHIFT 0 /*************************************************************************** *PLL0_LOCK_CNT - Main PLL0 Lock Counter ***************************************************************************/ /* CLK :: PLL0_LOCK_CNT :: reserved0 [31:12] */ #define BCHP_CLK_PLL0_LOCK_CNT_reserved0_MASK 0xfffff000 #define BCHP_CLK_PLL0_LOCK_CNT_reserved0_SHIFT 12 /* CLK :: PLL0_LOCK_CNT :: COUNT [11:00] */ #define BCHP_CLK_PLL0_LOCK_CNT_COUNT_MASK 0x00000fff #define BCHP_CLK_PLL0_LOCK_CNT_COUNT_SHIFT 0 /*************************************************************************** *PLL1_CTRL - Main PLL1 reset, enable, powerdown, and control ***************************************************************************/ /* CLK :: PLL1_CTRL :: CTRL_BITS_37_32 [31:26] */ #define BCHP_CLK_PLL1_CTRL_CTRL_BITS_37_32_MASK 0xfc000000 #define BCHP_CLK_PLL1_CTRL_CTRL_BITS_37_32_SHIFT 26 /* CLK :: PLL1_CTRL :: reserved0 [25:04] */ #define BCHP_CLK_PLL1_CTRL_reserved0_MASK 0x03fffff0 #define BCHP_CLK_PLL1_CTRL_reserved0_SHIFT 4 /* CLK :: PLL1_CTRL :: POWERDOWN [03:03] */ #define BCHP_CLK_PLL1_CTRL_POWERDOWN_MASK 0x00000008 #define BCHP_CLK_PLL1_CTRL_POWERDOWN_SHIFT 3 #define BCHP_CLK_PLL1_CTRL_POWERDOWN_Powerdown 1 #define BCHP_CLK_PLL1_CTRL_POWERDOWN_Normal 0 /* CLK :: PLL1_CTRL :: CLOCK_ENA [02:02] */ #define BCHP_CLK_PLL1_CTRL_CLOCK_ENA_MASK 0x00000004 #define BCHP_CLK_PLL1_CTRL_CLOCK_ENA_SHIFT 2 #define BCHP_CLK_PLL1_CTRL_CLOCK_ENA_Enable 1 #define BCHP_CLK_PLL1_CTRL_CLOCK_ENA_Disable 0 /* CLK :: PLL1_CTRL :: RESET [01:01] */ #define BCHP_CLK_PLL1_CTRL_RESET_MASK 0x00000002 #define BCHP_CLK_PLL1_CTRL_RESET_SHIFT 1 #define BCHP_CLK_PLL1_CTRL_RESET_Reset 1 #define BCHP_CLK_PLL1_CTRL_RESET_Normal 0 /* CLK :: PLL1_CTRL :: reserved1 [00:00] */ #define BCHP_CLK_PLL1_CTRL_reserved1_MASK 0x00000001 #define BCHP_CLK_PLL1_CTRL_reserved1_SHIFT 0 /*************************************************************************** *PLL1_CTRL_LO - Main PLL1 pll_ctrl low 32 bits ***************************************************************************/ /* CLK :: PLL1_CTRL_LO :: CTRL_BITS_31_0 [31:00] */ #define BCHP_CLK_PLL1_CTRL_LO_CTRL_BITS_31_0_MASK 0xffffffff #define BCHP_CLK_PLL1_CTRL_LO_CTRL_BITS_31_0_SHIFT 0 #define BCHP_CLK_PLL1_CTRL_LO_CTRL_BITS_31_0_VCO_Range0 536872384 #define BCHP_CLK_PLL1_CTRL_LO_CTRL_BITS_31_0_VCO_Range1 939525888 /*************************************************************************** *PLL1_AVD_DIV - Main PLL1 divider settings for VCO and channel 1 AVD clock ***************************************************************************/ /* CLK :: PLL1_AVD_DIV :: reserved0 [31:26] */ #define BCHP_CLK_PLL1_AVD_DIV_reserved0_MASK 0xfc000000 #define BCHP_CLK_PLL1_AVD_DIV_reserved0_SHIFT 26 /* CLK :: PLL1_AVD_DIV :: VCORNG [25:24] */ #define BCHP_CLK_PLL1_AVD_DIV_VCORNG_MASK 0x03000000 #define BCHP_CLK_PLL1_AVD_DIV_VCORNG_SHIFT 24 /* CLK :: PLL1_AVD_DIV :: reserved1 [23:17] */ #define BCHP_CLK_PLL1_AVD_DIV_reserved1_MASK 0x00fe0000 #define BCHP_CLK_PLL1_AVD_DIV_reserved1_SHIFT 17 /* CLK :: PLL1_AVD_DIV :: NDIV_INT [16:08] */ #define BCHP_CLK_PLL1_AVD_DIV_NDIV_INT_MASK 0x0001ff00 #define BCHP_CLK_PLL1_AVD_DIV_NDIV_INT_SHIFT 8 /* CLK :: PLL1_AVD_DIV :: M1DIV [07:00] */ #define BCHP_CLK_PLL1_AVD_DIV_M1DIV_MASK 0x000000ff #define BCHP_CLK_PLL1_AVD_DIV_M1DIV_SHIFT 0 /*************************************************************************** *PLL1_SPARE2_DIV - Main PLL1 divider settings for channel 2 spare clock ***************************************************************************/ /* CLK :: PLL1_SPARE2_DIV :: reserved0 [31:08] */ #define BCHP_CLK_PLL1_SPARE2_DIV_reserved0_MASK 0xffffff00 #define BCHP_CLK_PLL1_SPARE2_DIV_reserved0_SHIFT 8 /* CLK :: PLL1_SPARE2_DIV :: M2DIV [07:00] */ #define BCHP_CLK_PLL1_SPARE2_DIV_M2DIV_MASK 0x000000ff #define BCHP_CLK_PLL1_SPARE2_DIV_M2DIV_SHIFT 0 /*************************************************************************** *PLL1_SPARE3_DIV - Main PLL1 divider settings for channel 3 spare clock ***************************************************************************/ /* CLK :: PLL1_SPARE3_DIV :: reserved0 [31:08] */ #define BCHP_CLK_PLL1_SPARE3_DIV_reserved0_MASK 0xffffff00 #define BCHP_CLK_PLL1_SPARE3_DIV_reserved0_SHIFT 8 /* CLK :: PLL1_SPARE3_DIV :: M3DIV [07:00] */ #define BCHP_CLK_PLL1_SPARE3_DIV_M3DIV_MASK 0x000000ff #define BCHP_CLK_PLL1_SPARE3_DIV_M3DIV_SHIFT 0 /*************************************************************************** *PLL1_LOCK_CNT - Main PLL1 Lock Counter ***************************************************************************/ /* CLK :: PLL1_LOCK_CNT :: reserved0 [31:12] */ #define BCHP_CLK_PLL1_LOCK_CNT_reserved0_MASK 0xfffff000 #define BCHP_CLK_PLL1_LOCK_CNT_reserved0_SHIFT 12 /* CLK :: PLL1_LOCK_CNT :: COUNT [11:00] */ #define BCHP_CLK_PLL1_LOCK_CNT_COUNT_MASK 0x00000fff #define BCHP_CLK_PLL1_LOCK_CNT_COUNT_SHIFT 0 /*************************************************************************** *PLL_LOCK - PLL lock status ***************************************************************************/ /* CLK :: PLL_LOCK :: reserved0 [31:02] */ #define BCHP_CLK_PLL_LOCK_reserved0_MASK 0xfffffffc #define BCHP_CLK_PLL_LOCK_reserved0_SHIFT 2 /* CLK :: PLL_LOCK :: PLL1 [01:01] */ #define BCHP_CLK_PLL_LOCK_PLL1_MASK 0x00000002 #define BCHP_CLK_PLL_LOCK_PLL1_SHIFT 1 /* CLK :: PLL_LOCK :: PLL0 [00:00] */ #define BCHP_CLK_PLL_LOCK_PLL0_MASK 0x00000001 #define BCHP_CLK_PLL_LOCK_PLL0_SHIFT 0 /*************************************************************************** *PLL_LOCK_CNTR_RESET - PLL Lock Counter Resets ***************************************************************************/ /* CLK :: PLL_LOCK_CNTR_RESET :: reserved0 [31:02] */ #define BCHP_CLK_PLL_LOCK_CNTR_RESET_reserved0_MASK 0xfffffffc #define BCHP_CLK_PLL_LOCK_CNTR_RESET_reserved0_SHIFT 2 /* CLK :: PLL_LOCK_CNTR_RESET :: PLL1 [01:01] */ #define BCHP_CLK_PLL_LOCK_CNTR_RESET_PLL1_MASK 0x00000002 #define BCHP_CLK_PLL_LOCK_CNTR_RESET_PLL1_SHIFT 1 /* CLK :: PLL_LOCK_CNTR_RESET :: PLL0 [00:00] */ #define BCHP_CLK_PLL_LOCK_CNTR_RESET_PLL0_MASK 0x00000001 #define BCHP_CLK_PLL_LOCK_CNTR_RESET_PLL0_SHIFT 0 /*************************************************************************** *PLL_TEST_SEL - PLL core test select ***************************************************************************/ /* CLK :: PLL_TEST_SEL :: reserved0 [31:08] */ #define BCHP_CLK_PLL_TEST_SEL_reserved0_MASK 0xffffff00 #define BCHP_CLK_PLL_TEST_SEL_reserved0_SHIFT 8 /* CLK :: PLL_TEST_SEL :: PLL_SEL [07:04] */ #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_MASK 0x000000f0 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_SHIFT 4 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_None 0 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_MAIN_PLL0 1 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_MAIN_PLL1 2 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_3 3 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_4 4 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_5 5 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_6 6 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_7 7 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_8 8 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_9 9 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_10 10 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_11 11 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_12 12 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_13 13 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_14 14 #define BCHP_CLK_PLL_TEST_SEL_PLL_SEL_Reserved_15 15 /* CLK :: PLL_TEST_SEL :: SUB_SEL [03:00] */ #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_MASK 0x0000000f #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_SHIFT 0 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_VCO_Vcontrol 0 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_VCO_div_8 1 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Frefi 2 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Fdbki 3 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Watchdog 4 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Clkout_1 5 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Clkout_2 6 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Clkout_3 7 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_1 8 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_2 9 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_3 10 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_4 11 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_5 12 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_6 13 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_7 14 #define BCHP_CLK_PLL_TEST_SEL_SUB_SEL_Reserved_8 15 /*************************************************************************** *CLK_OBS_CTRL - Clock observation logic select ***************************************************************************/ /* CLK :: CLK_OBS_CTRL :: reserved0 [31:05] */ #define BCHP_CLK_CLK_OBS_CTRL_reserved0_MASK 0xffffffe0 #define BCHP_CLK_CLK_OBS_CTRL_reserved0_SHIFT 5 /* CLK :: CLK_OBS_CTRL :: DIV_SEL [04:03] */ #define BCHP_CLK_CLK_OBS_CTRL_DIV_SEL_MASK 0x00000018 #define BCHP_CLK_CLK_OBS_CTRL_DIV_SEL_SHIFT 3 #define BCHP_CLK_CLK_OBS_CTRL_DIV_SEL_Dont_divide 0 #define BCHP_CLK_CLK_OBS_CTRL_DIV_SEL_Divide_by_2 1 #define BCHP_CLK_CLK_OBS_CTRL_DIV_SEL_Divide_by_4 2 #define BCHP_CLK_CLK_OBS_CTRL_DIV_SEL_Reserved_3 3 /* CLK :: CLK_OBS_CTRL :: CLK_SEL [02:00] */ #define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_MASK 0x00000007 #define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_SHIFT 0 #define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Zero 0 #define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Clk_216_pll 1 #define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Clk_arm_pll 2 #define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Clk_avd_pll 3 #define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Clk_serdes_pll 4 #define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Reserved_5 5 #define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Reserved_6 6 #define BCHP_CLK_CLK_OBS_CTRL_CLK_SEL_Reserved_7 7 /*************************************************************************** *GPIO_PAD_CTRL - GPIO pad control ***************************************************************************/ /* CLK :: GPIO_PAD_CTRL :: reserved0 [31:07] */ #define BCHP_CLK_GPIO_PAD_CTRL_reserved0_MASK 0xffffff80 #define BCHP_CLK_GPIO_PAD_CTRL_reserved0_SHIFT 7 /* CLK :: GPIO_PAD_CTRL :: GPIO_PDN [06:06] */ #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PDN_MASK 0x00000040 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PDN_SHIFT 6 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PDN_Disable 0 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PDN_Enable 1 /* CLK :: GPIO_PAD_CTRL :: GPIO_PUP [05:05] */ #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PUP_MASK 0x00000020 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PUP_SHIFT 5 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PUP_Disable 0 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_PUP_Enable 1 /* CLK :: GPIO_PAD_CTRL :: GPIO_HYS_EN [04:04] */ #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_HYS_EN_MASK 0x00000010 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_HYS_EN_SHIFT 4 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_HYS_EN_TTL_input 0 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_HYS_EN_Schmitt_trigger_input 1 /* CLK :: GPIO_PAD_CTRL :: GPIO_SEL [03:01] */ #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_MASK 0x0000000e #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_SHIFT 1 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_Drive_Tri_State 0 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_Drive_2_mA 1 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_Drive_4_mA 2 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_Drive_6_mA 4 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_Drive_8_mA 5 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_Drive_10_mA 6 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SEL_Drive_12_mA 7 /* CLK :: GPIO_PAD_CTRL :: GPIO_SLEW [00:00] */ #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SLEW_MASK 0x00000001 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SLEW_SHIFT 0 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SLEW_High_Speed 0 #define BCHP_CLK_GPIO_PAD_CTRL_GPIO_SLEW_Normal 1 /*************************************************************************** *MISC_PAD_CTRL - MISC pad control ***************************************************************************/ /* CLK :: MISC_PAD_CTRL :: reserved0 [31:07] */ #define BCHP_CLK_MISC_PAD_CTRL_reserved0_MASK 0xffffff80 #define BCHP_CLK_MISC_PAD_CTRL_reserved0_SHIFT 7 /* CLK :: MISC_PAD_CTRL :: MISC_PDN [06:06] */ #define BCHP_CLK_MISC_PAD_CTRL_MISC_PDN_MASK 0x00000040 #define BCHP_CLK_MISC_PAD_CTRL_MISC_PDN_SHIFT 6 #define BCHP_CLK_MISC_PAD_CTRL_MISC_PDN_Disable 0 #define BCHP_CLK_MISC_PAD_CTRL_MISC_PDN_Enable 1 /* CLK :: MISC_PAD_CTRL :: MISC_PUP [05:05] */ #define BCHP_CLK_MISC_PAD_CTRL_MISC_PUP_MASK 0x00000020 #define BCHP_CLK_MISC_PAD_CTRL_MISC_PUP_SHIFT 5 #define BCHP_CLK_MISC_PAD_CTRL_MISC_PUP_Disable 0 #define BCHP_CLK_MISC_PAD_CTRL_MISC_PUP_Enable 1 /* CLK :: MISC_PAD_CTRL :: MISC_HYS_EN [04:04] */ #define BCHP_CLK_MISC_PAD_CTRL_MISC_HYS_EN_MASK 0x00000010 #define BCHP_CLK_MISC_PAD_CTRL_MISC_HYS_EN_SHIFT 4 #define BCHP_CLK_MISC_PAD_CTRL_MISC_HYS_EN_TTL_input 0 #define BCHP_CLK_MISC_PAD_CTRL_MISC_HYS_EN_Schmitt_trigger_input 1 /* CLK :: MISC_PAD_CTRL :: MISC_SEL [03:01] */ #define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_MASK 0x0000000e #define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_SHIFT 1 #define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_Drive_Tri_State 0 #define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_Drive_2_mA 1 #define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_Drive_4_mA 2 #define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_Drive_6_mA 4 #define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_Drive_8_mA 5 #define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_Drive_10_mA 6 #define BCHP_CLK_MISC_PAD_CTRL_MISC_SEL_Drive_12_mA 7 /* CLK :: MISC_PAD_CTRL :: MISC_SLEW [00:00] */ #define BCHP_CLK_MISC_PAD_CTRL_MISC_SLEW_MASK 0x00000001 #define BCHP_CLK_MISC_PAD_CTRL_MISC_SLEW_SHIFT 0 #define BCHP_CLK_MISC_PAD_CTRL_MISC_SLEW_High_Speed 0 #define BCHP_CLK_MISC_PAD_CTRL_MISC_SLEW_Normal 1 #endif /* #ifndef BCHP_CLK_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015700000000000011570 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_gr_bridge.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_g0000644000175000017500000001313011610313111031013 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_bvnt_gr_bridge.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:57p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:06 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_gr_bridge.h $ * * Hydra_Software_Devel/1 7/17/09 7:57p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_BVNT_GR_BRIDGE_H__ #define BCHP_BVNT_GR_BRIDGE_H__ /*************************************************************************** *BVNT_GR_BRIDGE - BVN GR Bridge Registers ***************************************************************************/ #define BCHP_BVNT_GR_BRIDGE_REVISION 0x00541800 /* GR Bridge Revision */ #define BCHP_BVNT_GR_BRIDGE_CTRL 0x00541804 /* GR Bridge Control Register */ #define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_0 0x00541808 /* GR Bridge Software Reset 0 Register */ #define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_1 0x0054180c /* GR Bridge Software Reset 1 Register */ /*************************************************************************** *REVISION - GR Bridge Revision ***************************************************************************/ /* BVNT_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define BCHP_BVNT_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define BCHP_BVNT_GR_BRIDGE_REVISION_reserved0_SHIFT 16 /* BVNT_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define BCHP_BVNT_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_BVNT_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* BVNT_GR_BRIDGE :: REVISION :: MINOR [07:00] */ #define BCHP_BVNT_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define BCHP_BVNT_GR_BRIDGE_REVISION_MINOR_SHIFT 0 /*************************************************************************** *CTRL - GR Bridge Control Register ***************************************************************************/ /* BVNT_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ #define BCHP_BVNT_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe #define BCHP_BVNT_GR_BRIDGE_CTRL_reserved0_SHIFT 1 /* BVNT_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ #define BCHP_BVNT_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 #define BCHP_BVNT_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 #define BCHP_BVNT_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 #define BCHP_BVNT_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 /*************************************************************************** *SPARE_SW_RESET_0 - GR Bridge Software Reset 0 Register ***************************************************************************/ /* BVNT_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ #define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe #define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 /* BVNT_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 #define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 #define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 /*************************************************************************** *SPARE_SW_RESET_1 - GR Bridge Software Reset 1 Register ***************************************************************************/ /* BVNT_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ #define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe #define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 /* BVNT_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ #define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 #define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 #define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 #define BCHP_BVNT_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 #endif /* #ifndef BCHP_BVNT_GR_BRIDGE_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015100000000000011562 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_gr_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_gr0000644000175000017500000001142211610313111031000 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_avd_gr_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:56p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:03 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_avd_gr_0.h $ * * Hydra_Software_Devel/1 7/17/09 7:56p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_AVD_GR_0_H__ #define BCHP_AVD_GR_0_H__ /*************************************************************************** *AVD_GR_0 ***************************************************************************/ #define BCHP_AVD_GR_0_REVISION 0x00900400 /* GR Bridge Revision */ #define BCHP_AVD_GR_0_CTRL 0x00900404 /* GR Bridge Control Register */ #define BCHP_AVD_GR_0_SW_RESET_0 0x00900408 /* GR Bridge Software Reset 0 Register */ #define BCHP_AVD_GR_0_SW_RESET_1 0x0090040c /* GR Bridge Software Reset 1 Register */ /*************************************************************************** *REVISION - GR Bridge Revision ***************************************************************************/ /* AVD_GR_0 :: REVISION :: reserved0 [31:16] */ #define BCHP_AVD_GR_0_REVISION_reserved0_MASK 0xffff0000 #define BCHP_AVD_GR_0_REVISION_reserved0_SHIFT 16 /* AVD_GR_0 :: REVISION :: MAJOR [15:08] */ #define BCHP_AVD_GR_0_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_AVD_GR_0_REVISION_MAJOR_SHIFT 8 /* AVD_GR_0 :: REVISION :: MINOR [07:00] */ #define BCHP_AVD_GR_0_REVISION_MINOR_MASK 0x000000ff #define BCHP_AVD_GR_0_REVISION_MINOR_SHIFT 0 /*************************************************************************** *CTRL - GR Bridge Control Register ***************************************************************************/ /* AVD_GR_0 :: CTRL :: reserved0 [31:01] */ #define BCHP_AVD_GR_0_CTRL_reserved0_MASK 0xfffffffe #define BCHP_AVD_GR_0_CTRL_reserved0_SHIFT 1 /* AVD_GR_0 :: CTRL :: gisb_error_intr [00:00] */ #define BCHP_AVD_GR_0_CTRL_gisb_error_intr_MASK 0x00000001 #define BCHP_AVD_GR_0_CTRL_gisb_error_intr_SHIFT 0 #define BCHP_AVD_GR_0_CTRL_gisb_error_intr_INTR_DISABLE 0 #define BCHP_AVD_GR_0_CTRL_gisb_error_intr_INTR_ENABLE 1 /*************************************************************************** *SW_RESET_0 - GR Bridge Software Reset 0 Register ***************************************************************************/ /* AVD_GR_0 :: SW_RESET_0 :: reserved0 [31:00] */ #define BCHP_AVD_GR_0_SW_RESET_0_reserved0_MASK 0xffffffff #define BCHP_AVD_GR_0_SW_RESET_0_reserved0_SHIFT 0 /*************************************************************************** *SW_RESET_1 - GR Bridge Software Reset 1 Register ***************************************************************************/ /* AVD_GR_0 :: SW_RESET_1 :: reserved0 [31:00] */ #define BCHP_AVD_GR_0_SW_RESET_1_reserved0_MASK 0xffffffff #define BCHP_AVD_GR_0_SW_RESET_1_reserved0_SHIFT 0 #endif /* #ifndef BCHP_AVD_GR_0_H__ */ /* End of File */ crystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_gio.h0000644000175000017500000001707711610313111030556 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_gio.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:07p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:13 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_gio.h $ * * Hydra_Software_Devel/1 7/17/09 8:07p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_GIO_H__ #define BCHP_GIO_H__ /*************************************************************************** *GIO - GPIO ***************************************************************************/ #define BCHP_GIO_ODEN_LO 0x00406000 /* GENERAL PURPOSE I/O OPEN DRAIN ENABLE [31:0] */ #define BCHP_GIO_DATA_LO 0x00406004 /* GENERAL PURPOSE I/O DATA [31:0] */ #define BCHP_GIO_IODIR_LO 0x00406008 /* GENERAL PURPOSE I/O DIRECTION [31:0] */ #define BCHP_GIO_EC_LO 0x0040600c /* GENERAL PURPOSE I/O EDGE CONFIGURATION [31:0] */ #define BCHP_GIO_EI_LO 0x00406010 /* GENERAL PURPOSE I/O EDGE INSENSITIVE [31:0] */ #define BCHP_GIO_MASK_LO 0x00406014 /* GENERAL PURPOSE I/O INTERRUPT MASK [31:0] */ #define BCHP_GIO_LEVEL_LO 0x00406018 /* GENERAL PURPOSE I/O INTERRUPT TYPE [31:0] */ #define BCHP_GIO_STAT_LO 0x0040601c /* GENERAL PURPOSE I/O INTERRUPT STATUS [31:0] */ /*************************************************************************** *ODEN_LO - GENERAL PURPOSE I/O OPEN DRAIN ENABLE [31:0] ***************************************************************************/ /* GIO :: ODEN_LO :: reserved0 [31:12] */ #define BCHP_GIO_ODEN_LO_reserved0_MASK 0xfffff000 #define BCHP_GIO_ODEN_LO_reserved0_SHIFT 12 /* GIO :: ODEN_LO :: oden [11:00] */ #define BCHP_GIO_ODEN_LO_oden_MASK 0x00000fff #define BCHP_GIO_ODEN_LO_oden_SHIFT 0 /*************************************************************************** *DATA_LO - GENERAL PURPOSE I/O DATA [31:0] ***************************************************************************/ /* GIO :: DATA_LO :: reserved0 [31:12] */ #define BCHP_GIO_DATA_LO_reserved0_MASK 0xfffff000 #define BCHP_GIO_DATA_LO_reserved0_SHIFT 12 /* GIO :: DATA_LO :: data [11:00] */ #define BCHP_GIO_DATA_LO_data_MASK 0x00000fff #define BCHP_GIO_DATA_LO_data_SHIFT 0 /*************************************************************************** *IODIR_LO - GENERAL PURPOSE I/O DIRECTION [31:0] ***************************************************************************/ /* GIO :: IODIR_LO :: reserved0 [31:12] */ #define BCHP_GIO_IODIR_LO_reserved0_MASK 0xfffff000 #define BCHP_GIO_IODIR_LO_reserved0_SHIFT 12 /* GIO :: IODIR_LO :: iodir [11:00] */ #define BCHP_GIO_IODIR_LO_iodir_MASK 0x00000fff #define BCHP_GIO_IODIR_LO_iodir_SHIFT 0 /*************************************************************************** *EC_LO - GENERAL PURPOSE I/O EDGE CONFIGURATION [31:0] ***************************************************************************/ /* GIO :: EC_LO :: reserved0 [31:12] */ #define BCHP_GIO_EC_LO_reserved0_MASK 0xfffff000 #define BCHP_GIO_EC_LO_reserved0_SHIFT 12 /* GIO :: EC_LO :: edge_config [11:00] */ #define BCHP_GIO_EC_LO_edge_config_MASK 0x00000fff #define BCHP_GIO_EC_LO_edge_config_SHIFT 0 /*************************************************************************** *EI_LO - GENERAL PURPOSE I/O EDGE INSENSITIVE [31:0] ***************************************************************************/ /* GIO :: EI_LO :: reserved0 [31:12] */ #define BCHP_GIO_EI_LO_reserved0_MASK 0xfffff000 #define BCHP_GIO_EI_LO_reserved0_SHIFT 12 /* GIO :: EI_LO :: edge_insensitive [11:00] */ #define BCHP_GIO_EI_LO_edge_insensitive_MASK 0x00000fff #define BCHP_GIO_EI_LO_edge_insensitive_SHIFT 0 /*************************************************************************** *MASK_LO - GENERAL PURPOSE I/O INTERRUPT MASK [31:0] ***************************************************************************/ /* GIO :: MASK_LO :: reserved0 [31:12] */ #define BCHP_GIO_MASK_LO_reserved0_MASK 0xfffff000 #define BCHP_GIO_MASK_LO_reserved0_SHIFT 12 /* GIO :: MASK_LO :: irq_mask [11:00] */ #define BCHP_GIO_MASK_LO_irq_mask_MASK 0x00000fff #define BCHP_GIO_MASK_LO_irq_mask_SHIFT 0 /*************************************************************************** *LEVEL_LO - GENERAL PURPOSE I/O INTERRUPT TYPE [31:0] ***************************************************************************/ /* GIO :: LEVEL_LO :: reserved0 [31:12] */ #define BCHP_GIO_LEVEL_LO_reserved0_MASK 0xfffff000 #define BCHP_GIO_LEVEL_LO_reserved0_SHIFT 12 /* GIO :: LEVEL_LO :: level [11:00] */ #define BCHP_GIO_LEVEL_LO_level_MASK 0x00000fff #define BCHP_GIO_LEVEL_LO_level_SHIFT 0 /*************************************************************************** *STAT_LO - GENERAL PURPOSE I/O INTERRUPT STATUS [31:0] ***************************************************************************/ /* GIO :: STAT_LO :: reserved0 [31:12] */ #define BCHP_GIO_STAT_LO_reserved0_MASK 0xfffff000 #define BCHP_GIO_STAT_LO_reserved0_SHIFT 12 /* GIO :: STAT_LO :: irq_status [11:00] */ #define BCHP_GIO_STAT_LO_irq_status_MASK 0x00000fff #define BCHP_GIO_STAT_LO_irq_status_SHIFT 0 #endif /* #ifndef BCHP_GIO_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015500000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_top_ctrl.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_to0000644000175000017500000031307311610313111031054 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_sun_top_ctrl.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:20p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:07 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_top_ctrl.h $ * * Hydra_Software_Devel/1 7/17/09 8:20p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_SUN_TOP_CTRL_H__ #define BCHP_SUN_TOP_CTRL_H__ /*************************************************************************** *SUN_TOP_CTRL - Top Control registers ***************************************************************************/ #define BCHP_SUN_TOP_CTRL_PROD_REVISION 0x00404000 /* Product Revision ID */ #define BCHP_SUN_TOP_CTRL_SUN_REVISION 0x00404004 /* Sundry Revision ID */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL 0x00404008 /* Reset control */ #define BCHP_SUN_TOP_CTRL_NMI_CTRL 0x00404010 /* Control register for NMI */ #define BCHP_SUN_TOP_CTRL_SW_RESET 0x00404014 /* Software reset register */ #define BCHP_SUN_TOP_CTRL_RESET_HISTORY 0x00404018 /* Reset history */ #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0 0x0040401c /* Strapping values */ #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1 0x00404020 /* Strapping values */ #define BCHP_SUN_TOP_CTRL_BOND_STATUS 0x00404024 /* Bond option value register */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0 0x00404028 /* OTP option test register */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1 0x0040402c /* OTP option test register */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0 0x00404030 /* OTP option status register */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1 0x00404034 /* OTP option status register */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0 0x00404038 /* Semaphore channel 0 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1 0x0040403c /* Semaphore channel 1 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2 0x00404040 /* Semaphore channel 2 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3 0x00404044 /* Semaphore channel 3 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4 0x00404048 /* Semaphore channel 4 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5 0x0040404c /* Semaphore channel 5 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6 0x00404050 /* Semaphore channel 6 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7 0x00404054 /* Semaphore channel 7 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8 0x00404058 /* Semaphore channel 8 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9 0x0040405c /* Semaphore channel 9 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10 0x00404060 /* Semaphore channel 10 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11 0x00404064 /* Semaphore channel 11 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12 0x00404068 /* Semaphore channel 12 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13 0x0040406c /* Semaphore channel 13 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14 0x00404070 /* Semaphore channel 14 */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15 0x00404074 /* Semaphore channel 15 */ #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0 0x00404078 /* General watchdog timer 0 */ #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1 0x0040407c /* General watchdog timer 1 */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0 0x00404080 /* General control register 0 */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1 0x00404084 /* General control register 1 */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2 0x00404088 /* General control register 2 */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3 0x0040408c /* General control register 3 */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4 0x00404090 /* General control register 4 */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5 0x00404094 /* General control register 5 */ #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0 0x00404098 /* General status register 0 */ #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1 0x0040409c /* General status register 1 */ #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2 0x004040a0 /* General status register 2 */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0 0x004040a4 /* General control register without scan 0 */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1 0x004040a8 /* General control register without scan 1 */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2 0x004040ac /* General control register without scan 2 */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3 0x004040b0 /* General control register without scan 3 */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4 0x004040b4 /* General control register without scan 4 */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5 0x004040b8 /* General control register without scan 5 */ #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH 0x004040bc /* Scratch register */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL 0x004040c0 /* Spare control bits reserved for future use */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0 0x00404100 /* Pinmux control register 0 */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1 0x00404104 /* Pinmux control register 1 */ #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0 0x00404180 /* Bypass clock unselect register 0 */ #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL 0x00404200 /* Test port control */ #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK 0x00404204 /* Testport peek register */ #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE 0x00404208 /* Testport poke register */ #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK 0x0040420c /* Testport peek register */ #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE 0x00404210 /* Testport poke register */ #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN 0x00404214 /* EJTAG input bus enables */ #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL 0x00404218 /* EJTAG output select */ #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL 0x0040421c /* UART Router select */ #define BCHP_SUN_TOP_CTRL_SSP_CONFIG 0x00404300 /* Serial Slave Port configuration register */ #define BCHP_SUN_TOP_CTRL_SERS_REV 0x00404320 /* SERS Revision Register */ #define BCHP_SUN_TOP_CTRL_SERS_CFG 0x00404324 /* SERS Configuration Register */ #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL 0x00404400 /* Block select for RO testmode */ #define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL 0x00404500 /* Test_mode control register */ #define BCHP_SUN_TOP_CTRL_TEST_MODE 0x00404504 /* Register source for test_mode */ #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE 0x00404508 /* Register source for sub_test_mode */ #define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE 0x0040450c /* Final latched testmode value */ #define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE 0x00404510 /* Final latched sub-testmode value */ #define BCHP_SUN_TOP_CTRL_PM_CTRL 0x00404600 /* Control register for Power Controller */ #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS 0x00404604 /* Power Management IRQ input status */ #define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT 0x00404608 /* Power Management Wait counter in place of Wait for MIPS IRQ */ /*************************************************************************** *PROD_REVISION - Product Revision ID ***************************************************************************/ /* SUN_TOP_CTRL :: PROD_REVISION :: product_revision [31:00] */ #define BCHP_SUN_TOP_CTRL_PROD_REVISION_product_revision_MASK 0xffffffff #define BCHP_SUN_TOP_CTRL_PROD_REVISION_product_revision_SHIFT 0 /*************************************************************************** *SUN_REVISION - Sundry Revision ID ***************************************************************************/ /* SUN_TOP_CTRL :: SUN_REVISION :: reserved0 [31:16] */ #define BCHP_SUN_TOP_CTRL_SUN_REVISION_reserved0_MASK 0xffff0000 #define BCHP_SUN_TOP_CTRL_SUN_REVISION_reserved0_SHIFT 16 /* SUN_TOP_CTRL :: SUN_REVISION :: sundry_revision [15:00] */ #define BCHP_SUN_TOP_CTRL_SUN_REVISION_sundry_revision_MASK 0x0000ffff #define BCHP_SUN_TOP_CTRL_SUN_REVISION_sundry_revision_SHIFT 0 /*************************************************************************** *RESET_CTRL - Reset control ***************************************************************************/ /* SUN_TOP_CTRL :: RESET_CTRL :: reset_outb_monitor [31:31] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_monitor_MASK 0x80000000 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_monitor_SHIFT 31 /* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_monitor [30:30] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_monitor_MASK 0x40000000 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_monitor_SHIFT 30 /* SUN_TOP_CTRL :: RESET_CTRL :: reset_outb_def_val_monitor [29:29] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_def_val_monitor_MASK 0x20000000 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_outb_def_val_monitor_SHIFT 29 /* SUN_TOP_CTRL :: RESET_CTRL :: reset_ext_mode_monitor [28:28] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_ext_mode_monitor_MASK 0x10000000 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_ext_mode_monitor_SHIFT 28 /* SUN_TOP_CTRL :: RESET_CTRL :: reset_timer_205_monitor [27:27] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_205_monitor_MASK 0x08000000 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_205_monitor_SHIFT 27 /* SUN_TOP_CTRL :: RESET_CTRL :: reset_timer_200_monitor [26:26] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_200_monitor_MASK 0x04000000 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reset_timer_200_monitor_SHIFT 26 /* SUN_TOP_CTRL :: RESET_CTRL :: reserved0 [25:12] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_MASK 0x03fff000 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved0_SHIFT 12 /* SUN_TOP_CTRL :: RESET_CTRL :: clear_reset_history [11:11] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_MASK 0x00000800 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_clear_reset_history_SHIFT 11 /* SUN_TOP_CTRL :: RESET_CTRL :: aux_chip_edge_reset_enable_lock [10:10] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_lock_MASK 0x00000400 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_lock_SHIFT 10 /* SUN_TOP_CTRL :: RESET_CTRL :: aux_chip_edge_reset_enable [09:09] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_MASK 0x00000200 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_aux_chip_edge_reset_enable_SHIFT 9 /* SUN_TOP_CTRL :: RESET_CTRL :: watchdog_reset_enable_lock [08:08] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_lock_MASK 0x00000100 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_lock_SHIFT 8 /* SUN_TOP_CTRL :: RESET_CTRL :: watchdog_reset_enable [07:07] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_MASK 0x00000080 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_watchdog_reset_enable_SHIFT 7 /* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_enable_lock [06:06] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_lock_MASK 0x00000040 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_lock_SHIFT 6 /* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_enable [05:05] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_MASK 0x00000020 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_enable_SHIFT 5 /* SUN_TOP_CTRL :: RESET_CTRL :: front_panel_reset_polarity [04:04] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_polarity_MASK 0x00000010 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_front_panel_reset_polarity_SHIFT 4 /* SUN_TOP_CTRL :: RESET_CTRL :: master_reset_en [03:03] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_master_reset_en_MASK 0x00000008 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_master_reset_en_SHIFT 3 /* SUN_TOP_CTRL :: RESET_CTRL :: reserved1 [02:01] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved1_MASK 0x00000006 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_reserved1_SHIFT 1 /* SUN_TOP_CTRL :: RESET_CTRL :: sc_insert_reset_en [00:00] */ #define BCHP_SUN_TOP_CTRL_RESET_CTRL_sc_insert_reset_en_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_RESET_CTRL_sc_insert_reset_en_SHIFT 0 /*************************************************************************** *NMI_CTRL - Control register for NMI ***************************************************************************/ /* SUN_TOP_CTRL :: NMI_CTRL :: nmi_config_lock [31:31] */ #define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_config_lock_MASK 0x80000000 #define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_config_lock_SHIFT 31 /* SUN_TOP_CTRL :: NMI_CTRL :: reserved0 [30:03] */ #define BCHP_SUN_TOP_CTRL_NMI_CTRL_reserved0_MASK 0x7ffffff8 #define BCHP_SUN_TOP_CTRL_NMI_CTRL_reserved0_SHIFT 3 /* SUN_TOP_CTRL :: NMI_CTRL :: nmi_pad_monitor [02:02] */ #define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_pad_monitor_MASK 0x00000004 #define BCHP_SUN_TOP_CTRL_NMI_CTRL_nmi_pad_monitor_SHIFT 2 /* SUN_TOP_CTRL :: NMI_CTRL :: config_nmi_polarity [01:01] */ #define BCHP_SUN_TOP_CTRL_NMI_CTRL_config_nmi_polarity_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_NMI_CTRL_config_nmi_polarity_SHIFT 1 /* SUN_TOP_CTRL :: NMI_CTRL :: disable_pad_nmi [00:00] */ #define BCHP_SUN_TOP_CTRL_NMI_CTRL_disable_pad_nmi_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_NMI_CTRL_disable_pad_nmi_SHIFT 0 /*************************************************************************** *SW_RESET - Software reset register ***************************************************************************/ /* SUN_TOP_CTRL :: SW_RESET :: chip_master_reset [31:31] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_chip_master_reset_MASK 0x80000000 #define BCHP_SUN_TOP_CTRL_SW_RESET_chip_master_reset_SHIFT 31 /* SUN_TOP_CTRL :: SW_RESET :: cpu_sw_reset_1shot [30:30] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_1shot_MASK 0x40000000 #define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_1shot_SHIFT 30 /* SUN_TOP_CTRL :: SW_RESET :: ext_sys_reset_1shot [29:29] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_1shot_MASK 0x20000000 #define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_1shot_SHIFT 29 /* SUN_TOP_CTRL :: SW_RESET :: reserved0 [28:22] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_reserved0_MASK 0x1fc00000 #define BCHP_SUN_TOP_CTRL_SW_RESET_reserved0_SHIFT 22 /* SUN_TOP_CTRL :: SW_RESET :: ext_sys_reset_level [21:21] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_level_MASK 0x00200000 #define BCHP_SUN_TOP_CTRL_SW_RESET_ext_sys_reset_level_SHIFT 21 /* SUN_TOP_CTRL :: SW_RESET :: reserved1 [20:12] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_reserved1_MASK 0x001ff000 #define BCHP_SUN_TOP_CTRL_SW_RESET_reserved1_SHIFT 12 /* SUN_TOP_CTRL :: SW_RESET :: xpt_sw_reset [11:11] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_xpt_sw_reset_MASK 0x00000800 #define BCHP_SUN_TOP_CTRL_SW_RESET_xpt_sw_reset_SHIFT 11 /* SUN_TOP_CTRL :: SW_RESET :: bvn_sw_reset [10:10] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_sw_reset_MASK 0x00000400 #define BCHP_SUN_TOP_CTRL_SW_RESET_bvn_sw_reset_SHIFT 10 /* SUN_TOP_CTRL :: SW_RESET :: sharf_sw_reset [09:09] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_sharf_sw_reset_MASK 0x00000200 #define BCHP_SUN_TOP_CTRL_SW_RESET_sharf_sw_reset_SHIFT 9 /* SUN_TOP_CTRL :: SW_RESET :: avd0_sw_reset [08:08] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_avd0_sw_reset_MASK 0x00000100 #define BCHP_SUN_TOP_CTRL_SW_RESET_avd0_sw_reset_SHIFT 8 /* SUN_TOP_CTRL :: SW_RESET :: misc_sw_reset [07:07] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_misc_sw_reset_MASK 0x00000080 #define BCHP_SUN_TOP_CTRL_SW_RESET_misc_sw_reset_SHIFT 7 /* SUN_TOP_CTRL :: SW_RESET :: ddr0_sw_reset [06:06] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_ddr0_sw_reset_MASK 0x00000040 #define BCHP_SUN_TOP_CTRL_SW_RESET_ddr0_sw_reset_SHIFT 6 /* SUN_TOP_CTRL :: SW_RESET :: blink_sw_reset [05:05] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_blink_sw_reset_MASK 0x00000020 #define BCHP_SUN_TOP_CTRL_SW_RESET_blink_sw_reset_SHIFT 5 /* SUN_TOP_CTRL :: SW_RESET :: jtag_otp_sw_reset [04:04] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_jtag_otp_sw_reset_MASK 0x00000010 #define BCHP_SUN_TOP_CTRL_SW_RESET_jtag_otp_sw_reset_SHIFT 4 /* SUN_TOP_CTRL :: SW_RESET :: cpu_sw_reset_level [03:03] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_level_MASK 0x00000008 #define BCHP_SUN_TOP_CTRL_SW_RESET_cpu_sw_reset_level_SHIFT 3 /* SUN_TOP_CTRL :: SW_RESET :: reserved2 [02:01] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_reserved2_MASK 0x00000006 #define BCHP_SUN_TOP_CTRL_SW_RESET_reserved2_SHIFT 1 /* SUN_TOP_CTRL :: SW_RESET :: sundry_sw_reset [00:00] */ #define BCHP_SUN_TOP_CTRL_SW_RESET_sundry_sw_reset_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_SW_RESET_sundry_sw_reset_SHIFT 0 /*************************************************************************** *RESET_HISTORY - Reset history ***************************************************************************/ /* SUN_TOP_CTRL :: RESET_HISTORY :: reserved0 [31:12] */ #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_MASK 0xfffff000 #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved0_SHIFT 12 /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_edge_reset [11:11] */ #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_MASK 0x00000800 #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_edge_reset_SHIFT 11 /* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_chip_sft_sft_rst_b [10:10] */ #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_sft_sft_rst_b_MASK 0x00000400 #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_sft_sft_rst_b_SHIFT 10 /* SUN_TOP_CTRL :: RESET_HISTORY :: cpu_chip_hrd_sft_rst_b [09:09] */ #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_hrd_sft_rst_b_MASK 0x00000200 #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_cpu_chip_hrd_sft_rst_b_SHIFT 9 /* SUN_TOP_CTRL :: RESET_HISTORY :: smartcard_insert_reset [08:08] */ #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_MASK 0x00000100 #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_smartcard_insert_reset_SHIFT 8 /* SUN_TOP_CTRL :: RESET_HISTORY :: aux_chip_level_reset [07:07] */ #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_MASK 0x00000080 #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_aux_chip_level_reset_SHIFT 7 /* SUN_TOP_CTRL :: RESET_HISTORY :: special_sw_reset [06:06] */ #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_special_sw_reset_MASK 0x00000040 #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_special_sw_reset_SHIFT 6 /* SUN_TOP_CTRL :: RESET_HISTORY :: reserved1 [05:05] */ #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved1_MASK 0x00000020 #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_reserved1_SHIFT 5 /* SUN_TOP_CTRL :: RESET_HISTORY :: watchdog_timer_reset [04:04] */ #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_MASK 0x00000010 #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_watchdog_timer_reset_SHIFT 4 /* SUN_TOP_CTRL :: RESET_HISTORY :: software_master_reset [03:03] */ #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_MASK 0x00000008 #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_software_master_reset_SHIFT 3 /* SUN_TOP_CTRL :: RESET_HISTORY :: front_panel_4sec_reset [02:02] */ #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_MASK 0x00000004 #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_front_panel_4sec_reset_SHIFT 2 /* SUN_TOP_CTRL :: RESET_HISTORY :: main_chip_reset_input [01:01] */ #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_main_chip_reset_input_SHIFT 1 /* SUN_TOP_CTRL :: RESET_HISTORY :: power_on_reset [00:00] */ #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_RESET_HISTORY_power_on_reset_SHIFT 0 /*************************************************************************** *STRAP_VALUE_0 - Strapping values ***************************************************************************/ /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: reserved0 [31:04] */ #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_MASK 0xfffffff0 #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_reserved0_SHIFT 4 /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_test_enable [03:03] */ #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_test_enable_MASK 0x00000008 #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_test_enable_SHIFT 3 /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_config_use_default [02:02] */ #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_config_use_default_MASK 0x00000004 #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_config_use_default_SHIFT 2 /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_eeprom_16_bit [01:01] */ #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_eeprom_16_bit_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_eeprom_16_bit_SHIFT 1 /* SUN_TOP_CTRL :: STRAP_VALUE_0 :: strap_config_use_otp [00:00] */ #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_config_use_otp_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_0_strap_config_use_otp_SHIFT 0 /*************************************************************************** *STRAP_VALUE_1 - Strapping values ***************************************************************************/ /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: reserved0 [31:03] */ #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_MASK 0xfffffff8 #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_reserved0_SHIFT 3 /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_2 [02:02] */ #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_2_MASK 0x00000004 #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_2_SHIFT 2 /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_1 [01:01] */ #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_1_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_1_SHIFT 1 /* SUN_TOP_CTRL :: STRAP_VALUE_1 :: strap_reserved_for_ECO_0 [00:00] */ #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_0_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_STRAP_VALUE_1_strap_reserved_for_ECO_0_SHIFT 0 /*************************************************************************** *BOND_STATUS - Bond option value register ***************************************************************************/ /* SUN_TOP_CTRL :: BOND_STATUS :: reserved0 [31:01] */ #define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_MASK 0xfffffffe #define BCHP_SUN_TOP_CTRL_BOND_STATUS_reserved0_SHIFT 1 /* SUN_TOP_CTRL :: BOND_STATUS :: bond_reserved [00:00] */ #define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_BOND_STATUS_bond_reserved_SHIFT 0 /*************************************************************************** *OTP_OPTION_TEST_0 - OTP option test register ***************************************************************************/ /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: reserved0 [31:05] */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_MASK 0xffffffe0 #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_reserved0_SHIFT 5 /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option0_spare_1 [04:04] */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option0_spare_1_MASK 0x00000010 #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option0_spare_1_SHIFT 4 /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option0_spare_0 [03:03] */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option0_spare_0_MASK 0x00000008 #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option0_spare_0_SHIFT 3 /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_cr [02:01] */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_MASK 0x00000006 #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_cr_SHIFT 1 /* SUN_TOP_CTRL :: OTP_OPTION_TEST_0 :: otp_option_en_testport [00:00] */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_0_otp_option_en_testport_SHIFT 0 /*************************************************************************** *OTP_OPTION_TEST_1 - OTP option test register ***************************************************************************/ /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: reserved0 [31:01] */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved0_MASK 0xfffffffe #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_reserved0_SHIFT 1 /* SUN_TOP_CTRL :: OTP_OPTION_TEST_1 :: otp_option1_spare_0 [00:00] */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_0_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_OTP_OPTION_TEST_1_otp_option1_spare_0_SHIFT 0 /*************************************************************************** *OTP_OPTION_STATUS_0 - OTP option status register ***************************************************************************/ /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: reserved0 [31:05] */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_MASK 0xffffffe0 #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_reserved0_SHIFT 5 /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option0_spare_1 [04:04] */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option0_spare_1_MASK 0x00000010 #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option0_spare_1_SHIFT 4 /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option0_spare_0 [03:03] */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option0_spare_0_MASK 0x00000008 #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option0_spare_0_SHIFT 3 /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_cr [02:01] */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_MASK 0x00000006 #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_cr_SHIFT 1 /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_0 :: otp_option_en_testport [00:00] */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_0_otp_option_en_testport_SHIFT 0 /*************************************************************************** *OTP_OPTION_STATUS_1 - OTP option status register ***************************************************************************/ /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: reserved0 [31:01] */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved0_MASK 0xfffffffe #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_reserved0_SHIFT 1 /* SUN_TOP_CTRL :: OTP_OPTION_STATUS_1 :: otp_option1_spare_0 [00:00] */ #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_0_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_OTP_OPTION_STATUS_1_otp_option1_spare_0_SHIFT 0 /*************************************************************************** *SEMAPHORE_0 - Semaphore channel 0 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_0 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_0 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_0_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_1 - Semaphore channel 1 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_1 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_1 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_1_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_2 - Semaphore channel 2 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_2 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_2 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_2_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_3 - Semaphore channel 3 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_3 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_3 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_3_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_4 - Semaphore channel 4 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_4 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_4 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_4_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_5 - Semaphore channel 5 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_5 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_5 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_5_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_6 - Semaphore channel 6 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_6 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_6 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_6_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_7 - Semaphore channel 7 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_7 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_7 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_7_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_8 - Semaphore channel 8 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_8 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_8 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_8_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_9 - Semaphore channel 9 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_9 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_9 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_9_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_10 - Semaphore channel 10 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_10 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_10 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_10_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_11 - Semaphore channel 11 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_11 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_11 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_11_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_12 - Semaphore channel 12 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_12 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_12 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_12_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_13 - Semaphore channel 13 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_13 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_13 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_13_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_14 - Semaphore channel 14 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_14 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_14 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_14_semaphore_ctrl_SHIFT 0 /*************************************************************************** *SEMAPHORE_15 - Semaphore channel 15 ***************************************************************************/ /* SUN_TOP_CTRL :: SEMAPHORE_15 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: SEMAPHORE_15 :: semaphore_ctrl [07:00] */ #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SEMAPHORE_15_semaphore_ctrl_SHIFT 0 /*************************************************************************** *GEN_WATCHDOG_0 - General watchdog timer 0 ***************************************************************************/ /* SUN_TOP_CTRL :: GEN_WATCHDOG_0 :: watchdog_timeout_value [31:00] */ #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_MASK 0xffffffff #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_0_watchdog_timeout_value_SHIFT 0 /*************************************************************************** *GEN_WATCHDOG_1 - General watchdog timer 1 ***************************************************************************/ /* SUN_TOP_CTRL :: GEN_WATCHDOG_1 :: watchdog_timeout_value [31:00] */ #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_MASK 0xffffffff #define BCHP_SUN_TOP_CTRL_GEN_WATCHDOG_1_watchdog_timeout_value_SHIFT 0 /*************************************************************************** *GENERAL_CTRL_0 - General control register 0 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_reserved [31:25] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_reserved_MASK 0xfe000000 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_reserved_SHIFT 25 /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_burst_stat_sel [24:24] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_burst_stat_sel_MASK 0x01000000 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_burst_stat_sel_SHIFT 24 /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_access_mode [23:22] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_access_mode_MASK 0x00c00000 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_access_mode_SHIFT 22 /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_otp_prog_en [21:21] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_prog_en_MASK 0x00200000 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_prog_en_SHIFT 21 /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_otp_debug_mode [20:20] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_debug_mode_MASK 0x00100000 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_otp_debug_mode_SHIFT 20 /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_continue_on_fail [19:19] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_continue_on_fail_MASK 0x00080000 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_continue_on_fail_SHIFT 19 /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_time_margin [18:16] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_time_margin_MASK 0x00070000 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_time_margin_SHIFT 16 /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_sadbyp [15:15] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_sadbyp_MASK 0x00008000 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_sadbyp_SHIFT 15 /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_unused [14:14] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_unused_MASK 0x00004000 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_unused_SHIFT 14 /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_pbyp [13:13] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pbyp_MASK 0x00002000 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pbyp_SHIFT 13 /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_pcount [12:10] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pcount_MASK 0x00001c00 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_pcount_SHIFT 10 /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_vsel [09:06] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_vsel_MASK 0x000003c0 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_vsel_SHIFT 6 /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_wrp_prog_sel [05:05] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_prog_sel_MASK 0x00000020 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_wrp_prog_sel_SHIFT 5 /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_command [04:01] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_command_MASK 0x0000001e #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_command_SHIFT 1 /* SUN_TOP_CTRL :: GENERAL_CTRL_0 :: jtag_otp_ctrl_start [00:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_start_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_0_jtag_otp_ctrl_start_SHIFT 0 /*************************************************************************** *GENERAL_CTRL_1 - General control register 1 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: jtag_otp_cpu_addr [31:16] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_addr_MASK 0xffff0000 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_addr_SHIFT 16 /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: reserved0 [15:01] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_MASK 0x0000fffe #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_reserved0_SHIFT 1 /* SUN_TOP_CTRL :: GENERAL_CTRL_1 :: jtag_otp_cpu_mode [00:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_mode_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_1_jtag_otp_cpu_mode_SHIFT 0 /*************************************************************************** *GENERAL_CTRL_2 - General control register 2 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_CTRL_2 :: general_ctrl_2 [31:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl_2_MASK 0xffffffff #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_2_general_ctrl_2_SHIFT 0 /*************************************************************************** *GENERAL_CTRL_3 - General control register 3 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: reserved0 [31:04] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_MASK 0xfffffff0 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_reserved0_SHIFT 4 /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_3 [03:03] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_3_MASK 0x00000008 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_3_SHIFT 3 /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_2 [02:02] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_2_MASK 0x00000004 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_2_SHIFT 2 /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_1 [01:01] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_1_SHIFT 1 /* SUN_TOP_CTRL :: GENERAL_CTRL_3 :: general_ctrl3_0 [00:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_3_general_ctrl3_0_SHIFT 0 /*************************************************************************** *GENERAL_CTRL_4 - General control register 4 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: reserved0 [31:01] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_MASK 0xfffffffe #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_reserved0_SHIFT 1 /* SUN_TOP_CTRL :: GENERAL_CTRL_4 :: general_ctrl4_0 [00:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_4_general_ctrl4_0_SHIFT 0 /*************************************************************************** *GENERAL_CTRL_5 - General control register 5 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_7 [07:07] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_7_MASK 0x00000080 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_7_SHIFT 7 /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_6 [06:06] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_6_MASK 0x00000040 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_6_SHIFT 6 /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_5 [05:05] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_5_MASK 0x00000020 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_5_SHIFT 5 /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_4 [04:04] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_4_MASK 0x00000010 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_4_SHIFT 4 /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_3 [03:03] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_3_MASK 0x00000008 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_3_SHIFT 3 /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_2 [02:02] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_2_MASK 0x00000004 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_2_SHIFT 2 /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_1 [01:01] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_1_SHIFT 1 /* SUN_TOP_CTRL :: GENERAL_CTRL_5 :: general_ctrl5_0 [00:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_5_general_ctrl5_0_SHIFT 0 /*************************************************************************** *GENERAL_STATUS_0 - General status register 0 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_STATUS_0 :: jtag_otp_data_out [31:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_jtag_otp_data_out_MASK 0xffffffff #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_0_jtag_otp_data_out_SHIFT 0 /*************************************************************************** *GENERAL_STATUS_1 - General status register 1 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: reserved0 [31:08] */ #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_MASK 0xffffff00 #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_reserved0_SHIFT 8 /* SUN_TOP_CTRL :: GENERAL_STATUS_1 :: jtag_otp_status [07:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_jtag_otp_status_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_1_jtag_otp_status_SHIFT 0 /*************************************************************************** *GENERAL_STATUS_2 - General status register 2 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: reserved0 [31:04] */ #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_MASK 0xfffffff0 #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_reserved0_SHIFT 4 /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_03 [03:03] */ #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_03_MASK 0x00000008 #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_03_SHIFT 3 /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_02 [02:02] */ #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_02_MASK 0x00000004 #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_02_SHIFT 2 /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_01 [01:01] */ #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_01_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_01_SHIFT 1 /* SUN_TOP_CTRL :: GENERAL_STATUS_2 :: general_status2_00 [00:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_00_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_GENERAL_STATUS_2_general_status2_00_SHIFT 0 /*************************************************************************** *GENERAL_CTRL_NO_SCAN_0 - General control register without scan 0 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: reserved0 [31:02] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_MASK 0xfffffffc #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_reserved0_SHIFT 2 /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_1 [01:01] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_1_SHIFT 1 /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_0 :: general_ctrl_no_scan0_0 [00:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_0_general_ctrl_no_scan0_0_SHIFT 0 /*************************************************************************** *GENERAL_CTRL_NO_SCAN_1 - General control register without scan 1 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: reserved0 [31:02] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_MASK 0xfffffffc #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_reserved0_SHIFT 2 /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_1 [01:01] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_1_SHIFT 1 /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_1 :: general_ctrl_no_scan1_0 [00:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_1_general_ctrl_no_scan1_0_SHIFT 0 /*************************************************************************** *GENERAL_CTRL_NO_SCAN_2 - General control register without scan 2 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: reserved0 [31:02] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_MASK 0xfffffffc #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_reserved0_SHIFT 2 /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_1 [01:01] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_1_SHIFT 1 /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_2 :: general_ctrl_no_scan2_0 [00:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_2_general_ctrl_no_scan2_0_SHIFT 0 /*************************************************************************** *GENERAL_CTRL_NO_SCAN_3 - General control register without scan 3 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: reserved0 [31:02] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_MASK 0xfffffffc #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_reserved0_SHIFT 2 /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_1 [01:01] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_1_SHIFT 1 /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_3 :: general_ctrl_no_scan3_0 [00:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_3_general_ctrl_no_scan3_0_SHIFT 0 /*************************************************************************** *GENERAL_CTRL_NO_SCAN_4 - General control register without scan 4 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: reserved0 [31:02] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_MASK 0xfffffffc #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_reserved0_SHIFT 2 /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_1 [01:01] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_1_SHIFT 1 /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_4 :: general_ctrl_no_scan4_0 [00:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_4_general_ctrl_no_scan4_0_SHIFT 0 /*************************************************************************** *GENERAL_CTRL_NO_SCAN_5 - General control register without scan 5 ***************************************************************************/ /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: reserved0 [31:02] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_MASK 0xfffffffc #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_reserved0_SHIFT 2 /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_1 [01:01] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_1_SHIFT 1 /* SUN_TOP_CTRL :: GENERAL_CTRL_NO_SCAN_5 :: general_ctrl_no_scan5_0 [00:00] */ #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_GENERAL_CTRL_NO_SCAN_5_general_ctrl_no_scan5_0_SHIFT 0 /*************************************************************************** *UNCLEARED_SCRATCH - Scratch register ***************************************************************************/ /* SUN_TOP_CTRL :: UNCLEARED_SCRATCH :: uncleared_scratch [31:00] */ #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_MASK 0xffffffff #define BCHP_SUN_TOP_CTRL_UNCLEARED_SCRATCH_uncleared_scratch_SHIFT 0 /*************************************************************************** *SPARE_CTRL - Spare control bits reserved for future use ***************************************************************************/ /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_31 [31:31] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_MASK 0x80000000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_31_SHIFT 31 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_30 [30:30] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_MASK 0x40000000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_30_SHIFT 30 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_29 [29:29] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_MASK 0x20000000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_29_SHIFT 29 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_28 [28:28] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_MASK 0x10000000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_28_SHIFT 28 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_27 [27:27] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_MASK 0x08000000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_27_SHIFT 27 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_26 [26:26] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_MASK 0x04000000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_26_SHIFT 26 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_25 [25:25] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_MASK 0x02000000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_25_SHIFT 25 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_24 [24:24] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_MASK 0x01000000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_24_SHIFT 24 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_23 [23:23] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_MASK 0x00800000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_23_SHIFT 23 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_22 [22:22] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_MASK 0x00400000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_22_SHIFT 22 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_21 [21:21] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_MASK 0x00200000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_21_SHIFT 21 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_20 [20:20] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_MASK 0x00100000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_20_SHIFT 20 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_19 [19:19] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_MASK 0x00080000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_19_SHIFT 19 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_18 [18:18] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_MASK 0x00040000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_18_SHIFT 18 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_17 [17:17] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_MASK 0x00020000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_17_SHIFT 17 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_16 [16:16] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_MASK 0x00010000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_16_SHIFT 16 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_15 [15:15] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_MASK 0x00008000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_15_SHIFT 15 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_14 [14:14] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_MASK 0x00004000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_14_SHIFT 14 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_13 [13:13] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_MASK 0x00002000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_13_SHIFT 13 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_12 [12:12] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_MASK 0x00001000 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_12_SHIFT 12 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_11 [11:11] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_MASK 0x00000800 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_11_SHIFT 11 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_10 [10:10] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_MASK 0x00000400 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_10_SHIFT 10 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_09 [09:09] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_MASK 0x00000200 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_09_SHIFT 9 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_08 [08:08] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_MASK 0x00000100 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_08_SHIFT 8 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_07 [07:07] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_MASK 0x00000080 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_07_SHIFT 7 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_06 [06:06] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_MASK 0x00000040 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_06_SHIFT 6 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_05 [05:05] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_MASK 0x00000020 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_05_SHIFT 5 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_04 [04:04] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_MASK 0x00000010 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_04_SHIFT 4 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_03 [03:03] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_MASK 0x00000008 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_03_SHIFT 3 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_02 [02:02] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_MASK 0x00000004 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_02_SHIFT 2 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_01 [01:01] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_01_SHIFT 1 /* SUN_TOP_CTRL :: SPARE_CTRL :: spare_ctrl_00 [00:00] */ #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_SPARE_CTRL_spare_ctrl_00_SHIFT 0 /*************************************************************************** *PIN_MUX_CTRL_0 - Pinmux control register 0 ***************************************************************************/ /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_07 [31:28] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_MASK 0xf0000000 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_SHIFT 28 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_GPIO_07 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_SPARE0_ON_GPIO_07 1 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_TEST_OUT0 2 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_TP_IN7 3 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_TP_OUT7 4 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_07_RC_TP_OUT7 5 /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_06 [27:24] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_MASK 0x0f000000 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_SHIFT 24 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_GPIO_06 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_SPARE0_ON_GPIO_06 1 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_TEST_ACK 2 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_TP_IN6 3 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_TP_OUT6 4 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_06_RC_TP_OUT6 5 /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_05 [23:20] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_MASK 0x00f00000 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_SHIFT 20 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_GPIO_05 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_DBG_UART2_RX 1 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_TEST_REQ 2 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_TP_IN5 3 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_TP_OUT5 4 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_05_RC_TP_OUT5 5 /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_04 [19:16] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_MASK 0x000f0000 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_SHIFT 16 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_GPIO_04 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_DBG_UART2_TX 1 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_TEST_CLK 2 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_TP_IN4 3 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_TP_OUT4 4 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_04_RC_TP_OUT4 5 /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_03 [15:12] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_MASK 0x0000f000 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_SHIFT 12 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_GPIO_03 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_DBG_UART1_RX 1 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_TEST_IN3 2 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_TP_IN3 3 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_TP_OUT3 4 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_03_RC_TP_OUT3 5 /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_02 [11:08] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_MASK 0x00000f00 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_SHIFT 8 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_GPIO_02 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_DBG_UART1_TX 1 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_TEST_IN2 2 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_TP_IN2 3 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_TP_OUT2 4 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_02_RC_TP_OUT2 5 /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_01 [07:04] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_MASK 0x000000f0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_SHIFT 4 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_GPIO_01 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_DBG_UART0_RX 1 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_TEST_IN1 2 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_TP_IN1 3 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_TP_OUT1 4 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_01_RC_TP_OUT1 5 /* SUN_TOP_CTRL :: PIN_MUX_CTRL_0 :: gpio_00 [03:00] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_MASK 0x0000000f #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_SHIFT 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_GPIO_00 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_DBG_UART0_TX 1 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_TEST_IN0 2 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_TP_IN0 3 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_TP_OUT0 4 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0_gpio_00_RC_TP_OUT0 5 /*************************************************************************** *PIN_MUX_CTRL_1 - Pinmux control register 1 ***************************************************************************/ /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: reserved0 [31:24] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_reserved0_MASK 0xff000000 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_reserved0_SHIFT 24 /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: eeprom_data [23:20] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_data_MASK 0x00f00000 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_data_SHIFT 20 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_data_EEPROM_DATA 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_data_PCIE_MDIO_RST 1 /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: eeprom_clk [19:16] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_clk_MASK 0x000f0000 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_clk_SHIFT 16 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_clk_EEPROM_CLK 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_eeprom_clk_PCIE_MDC 1 /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_11 [15:12] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_MASK 0x0000f000 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_SHIFT 12 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_GPIO_11 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_PCIE_MDIO 1 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_SPARE0_ON_GPIO_11 2 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_TP_IN11 3 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_TP_OUT11 4 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_11_RC_TP_OUT11 5 /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_10 [11:08] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_MASK 0x00000f00 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_SHIFT 8 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_GPIO_10 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_RO_IO_TESTOUT 1 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_TEST_OUT3 2 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_TP_IN10 3 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_TP_OUT10 4 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_10_RC_TP_OUT10 5 /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_09 [07:04] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_MASK 0x000000f0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_SHIFT 4 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_GPIO_09 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_RO_CORE_TESTOUT 1 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_TEST_OUT2 2 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_TP_IN9 3 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_TP_OUT9 4 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_09_RC_TP_OUT9 5 /* SUN_TOP_CTRL :: PIN_MUX_CTRL_1 :: gpio_08 [03:00] */ #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_MASK 0x0000000f #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SHIFT 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_GPIO_08 0 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_SPARE0_ON_GPIO_08 1 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_TEST_OUT1 2 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_TP_IN8 3 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_TP_OUT8 4 #define BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_1_gpio_08_RC_TP_OUT8 5 /*************************************************************************** *BYP_CLK_UNSELECT_0 - Bypass clock unselect register 0 ***************************************************************************/ /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: reserved0 [31:04] */ #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_MASK 0xfffffff0 #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_reserved0_SHIFT 4 /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_low_pwr_n [03:03] */ #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_low_pwr_n_MASK 0x00000008 #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_low_pwr_n_SHIFT 3 /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_eeprom_clk [02:02] */ #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_eeprom_clk_MASK 0x00000004 #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_eeprom_clk_SHIFT 2 /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_bsc_s_sda [01:01] */ #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_bsc_s_sda_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_bsc_s_sda_SHIFT 1 /* SUN_TOP_CTRL :: BYP_CLK_UNSELECT_0 :: unsel_byp_clk_on_bsc_s_scl [00:00] */ #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_bsc_s_scl_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_BYP_CLK_UNSELECT_0_unsel_byp_clk_on_bsc_s_scl_SHIFT 0 /*************************************************************************** *TEST_PORT_CTRL - Test port control ***************************************************************************/ /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: sundry_local_tp_out_sel [31:28] */ #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_MASK 0xf0000000 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SHIFT 28 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SEMAPHORE_0 0 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SEMAPHORE_1 1 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_FP_RST_CNT 2 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_MISC_TEST 3 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_SSP 4 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TP_OUT_POKE_REG 5 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TP_IN 6 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_ARB_TP_0 7 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_ARB_TP_1 8 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_ARB_TP_2 9 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_ARB_TP_3 10 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_PWR_CTRL_STATUS 11 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_PWR_CTRL_IRQ_IN 12 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_13 13 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_UNUSED_14 14 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_sundry_local_tp_out_sel_TOP_AUX_TP_OUT 15 /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: reserved0 [27:10] */ #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_MASK 0x0ffffc00 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_reserved0_SHIFT 10 /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_in_source_select [09:09] */ #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_MASK 0x00000200 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_in_source_select_SHIFT 9 /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: tp_select [08:07] */ #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_MASK 0x00000180 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_tp_select_SHIFT 7 /* SUN_TOP_CTRL :: TEST_PORT_CTRL :: encoded_tp_enable [06:00] */ #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MASK 0x0000007f #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SHIFT 0 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_AVD 0 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_MISC 1 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_BLINK 2 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_DDR_IF0 3 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_SUN 4 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_CLK 5 #define BCHP_SUN_TOP_CTRL_TEST_PORT_CTRL_encoded_tp_enable_UNUSED_31 31 /*************************************************************************** *TEST_PORT_OUT_PEEK - Testport peek register ***************************************************************************/ /* SUN_TOP_CTRL :: TEST_PORT_OUT_PEEK :: test_port_out_peek_value [31:00] */ #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_MASK 0xffffffff #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_PEEK_test_port_out_peek_value_SHIFT 0 /*************************************************************************** *TEST_PORT_OUT_POKE - Testport poke register ***************************************************************************/ /* SUN_TOP_CTRL :: TEST_PORT_OUT_POKE :: test_port_out_poke_value [31:00] */ #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_MASK 0xffffffff #define BCHP_SUN_TOP_CTRL_TEST_PORT_OUT_POKE_test_port_out_poke_value_SHIFT 0 /*************************************************************************** *TEST_PORT_IN_PEEK - Testport peek register ***************************************************************************/ /* SUN_TOP_CTRL :: TEST_PORT_IN_PEEK :: test_port_in_peek_value [31:00] */ #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_MASK 0xffffffff #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_PEEK_test_port_in_peek_value_SHIFT 0 /*************************************************************************** *TEST_PORT_IN_POKE - Testport poke register ***************************************************************************/ /* SUN_TOP_CTRL :: TEST_PORT_IN_POKE :: test_port_in_poke_value [31:00] */ #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_MASK 0xffffffff #define BCHP_SUN_TOP_CTRL_TEST_PORT_IN_POKE_test_port_in_poke_value_SHIFT 0 /*************************************************************************** *EJTAG_INPUT_EN - EJTAG input bus enables ***************************************************************************/ /* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: reserved0 [31:02] */ #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_MASK 0xfffffffc #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_reserved0_SHIFT 2 /* SUN_TOP_CTRL :: EJTAG_INPUT_EN :: ejtag_input_enable [01:00] */ #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_MASK 0x00000003 #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_SHIFT 0 #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_DO_NOT_USE_CPU_ONE_HOT 1 #define BCHP_SUN_TOP_CTRL_EJTAG_INPUT_EN_ejtag_input_enable_ARM_CPU_ONE_HOT 2 /*************************************************************************** *EJTAG_OUTPUT_SEL - EJTAG output select ***************************************************************************/ /* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: reserved0 [31:02] */ #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_MASK 0xfffffffc #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_reserved0_SHIFT 2 /* SUN_TOP_CTRL :: EJTAG_OUTPUT_SEL :: ejtag_output_sel [01:00] */ #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_MASK 0x00000003 #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_SHIFT 0 #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_DO_NOT_USE_CPU 0 #define BCHP_SUN_TOP_CTRL_EJTAG_OUTPUT_SEL_ejtag_output_sel_ARM_CPU 1 /*************************************************************************** *UART_ROUTER_SEL - UART Router select ***************************************************************************/ /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_7_cpu_sel [31:28] */ #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_MASK 0xf0000000 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_7_cpu_sel_SHIFT 28 /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_6_cpu_sel [27:24] */ #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_MASK 0x0f000000 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_6_cpu_sel_SHIFT 24 /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_5_cpu_sel [23:20] */ #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_MASK 0x00f00000 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_5_cpu_sel_SHIFT 20 /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_4_cpu_sel [19:16] */ #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_MASK 0x000f0000 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_4_cpu_sel_SHIFT 16 /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_3_cpu_sel [15:12] */ #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_MASK 0x0000f000 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_3_cpu_sel_SHIFT 12 /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_2_cpu_sel [11:08] */ #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_MASK 0x00000f00 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_SHIFT 8 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_NO_CPU 0 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_ARM 1 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_OL 2 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_AVD0_IL 3 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_04 4 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_05 5 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_06 6 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_07 7 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_08 8 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_09 9 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_10 10 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_11 11 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_12 12 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_13 13 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_14 14 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_2_cpu_sel_UNUSED_15 15 /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_1_cpu_sel [07:04] */ #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_MASK 0x000000f0 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_SHIFT 4 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_NO_CPU 0 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_ARM 1 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_OL 2 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_AVD0_IL 3 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_04 4 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_05 5 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_06 6 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_07 7 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_08 8 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_09 9 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_10 10 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_11 11 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_12 12 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_13 13 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_14 14 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_1_cpu_sel_UNUSED_15 15 /* SUN_TOP_CTRL :: UART_ROUTER_SEL :: port_0_cpu_sel [03:00] */ #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_MASK 0x0000000f #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_SHIFT 0 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_NO_CPU 0 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_ARM 1 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_OL 2 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_AVD0_IL 3 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_04 4 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_05 5 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_06 6 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_07 7 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_08 8 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_09 9 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_10 10 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_11 11 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_12 12 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_13 13 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_14 14 #define BCHP_SUN_TOP_CTRL_UART_ROUTER_SEL_port_0_cpu_sel_UNUSED_15 15 /*************************************************************************** *SSP_CONFIG - Serial Slave Port configuration register ***************************************************************************/ /* SUN_TOP_CTRL :: SSP_CONFIG :: reserved0 [31:11] */ #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_MASK 0xfffff800 #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_reserved0_SHIFT 11 /* SUN_TOP_CTRL :: SSP_CONFIG :: serial_adr_cfg [10:07] */ #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_MASK 0x00000780 #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_serial_adr_cfg_SHIFT 7 /* SUN_TOP_CTRL :: SSP_CONFIG :: probe_mux_sel [06:03] */ #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_MASK 0x00000078 #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_probe_mux_sel_SHIFT 3 /* SUN_TOP_CTRL :: SSP_CONFIG :: dly_disable [02:02] */ #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_MASK 0x00000004 #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_dly_disable_SHIFT 2 /* SUN_TOP_CTRL :: SSP_CONFIG :: spi_mode [01:01] */ #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_spi_mode_SHIFT 1 /* SUN_TOP_CTRL :: SSP_CONFIG :: ssp_module_enable [00:00] */ #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_SSP_CONFIG_ssp_module_enable_SHIFT 0 /*************************************************************************** *SERS_REV - SERS Revision Register ***************************************************************************/ /* SUN_TOP_CTRL :: SERS_REV :: reserved0 [31:16] */ #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_MASK 0xffff0000 #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved0_SHIFT 16 /* SUN_TOP_CTRL :: SERS_REV :: reserved_for_eco1 [15:08] */ #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_MASK 0x0000ff00 #define BCHP_SUN_TOP_CTRL_SERS_REV_reserved_for_eco1_SHIFT 8 /* SUN_TOP_CTRL :: SERS_REV :: BLOCK_SERS_REVISION [07:00] */ #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_MASK 0x000000ff #define BCHP_SUN_TOP_CTRL_SERS_REV_BLOCK_SERS_REVISION_SHIFT 0 /*************************************************************************** *SERS_CFG - SERS Configuration Register ***************************************************************************/ /* SUN_TOP_CTRL :: SERS_CFG :: reserved_for_eco0 [31:29] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_MASK 0xe0000000 #define BCHP_SUN_TOP_CTRL_SERS_CFG_reserved_for_eco0_SHIFT 29 /* SUN_TOP_CTRL :: SERS_CFG :: CMD_MODE [28:28] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_MASK 0x10000000 #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_SHIFT 28 #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_mapped_buffer_mode 0 #define BCHP_SUN_TOP_CTRL_SERS_CFG_CMD_MODE_cmd_fifo_mode 1 /* SUN_TOP_CTRL :: SERS_CFG :: Little_Endian [27:27] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_MASK 0x08000000 #define BCHP_SUN_TOP_CTRL_SERS_CFG_Little_Endian_SHIFT 27 /* union - case mapped_buffer_mode [26:08] */ /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_4 [26:22] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_MASK 0x07c00000 #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_4_SHIFT 22 /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_3 [21:17] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_MASK 0x003e0000 #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_3_SHIFT 17 /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: W_PKT_OFFSET_2 [16:12] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_MASK 0x0001f000 #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_W_PKT_OFFSET_2_SHIFT 12 /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_4 [11:11] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_MASK 0x00000800 #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_4_SHIFT 11 /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_3 [10:10] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_MASK 0x00000400 #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_3_SHIFT 10 /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_2 [09:09] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_MASK 0x00000200 #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_2_SHIFT 9 /* SUN_TOP_CTRL :: SERS_CFG :: mapped_buffer_mode :: DATA_CHG_IRQ_ONLY_1 [08:08] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_MASK 0x00000100 #define BCHP_SUN_TOP_CTRL_SERS_CFG_mapped_buffer_mode_DATA_CHG_IRQ_ONLY_1_SHIFT 8 /* union - case cmd_fifo_mode [26:08] */ /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_W_PTR [26:22] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_MASK 0x07c00000 #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_W_PTR_SHIFT 22 /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_R_PTR [21:17] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_MASK 0x003e0000 #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_R_PTR_SHIFT 17 /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: FIFO_THRESHOLD [16:12] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_MASK 0x0001f000 #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_FIFO_THRESHOLD_SHIFT 12 /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: NOT_USED [11:10] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_MASK 0x00000c00 #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_NOT_USED_SHIFT 10 /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: CMD_FIFO_OV [09:09] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_MASK 0x00000200 #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_CMD_FIFO_OV_SHIFT 9 /* SUN_TOP_CTRL :: SERS_CFG :: cmd_fifo_mode :: DROP_CMDS [08:08] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_MASK 0x00000100 #define BCHP_SUN_TOP_CTRL_SERS_CFG_cmd_fifo_mode_DROP_CMDS_SHIFT 8 /* SUN_TOP_CTRL :: SERS_CFG :: SER_ADR [07:01] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_MASK 0x000000fe #define BCHP_SUN_TOP_CTRL_SERS_CFG_SER_ADR_SHIFT 1 /* SUN_TOP_CTRL :: SERS_CFG :: SOFT_SER_ADR [00:00] */ #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_SERS_CFG_SOFT_SER_ADR_SHIFT 0 /*************************************************************************** *SERS_CMD_BUF_%i - Host Serial Write Command Buffer ***************************************************************************/ #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_BASE 0x00404328 #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_START 0 #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_END 7 #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *SERS_CMD_BUF_%i - Host Serial Write Command Buffer ***************************************************************************/ /* SUN_TOP_CTRL :: SERS_CMD_BUF_i :: SERS_CMD_BUF [31:00] */ #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_MASK 0xffffffff #define BCHP_SUN_TOP_CTRL_SERS_CMD_BUF_i_SERS_CMD_BUF_SHIFT 0 /*************************************************************************** *SERS_STAT_BUF_%i - Host Serial Read Status Buffer ***************************************************************************/ #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_BASE 0x00404348 #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_START 0 #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_END 1 #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *SERS_STAT_BUF_%i - Host Serial Read Status Buffer ***************************************************************************/ /* SUN_TOP_CTRL :: SERS_STAT_BUF_i :: SERS_STAT_BUF [31:00] */ #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_MASK 0xffffffff #define BCHP_SUN_TOP_CTRL_SERS_STAT_BUF_i_SERS_STAT_BUF_SHIFT 0 /*************************************************************************** *RO_TEST_BLOCK_SEL - Block select for RO testmode ***************************************************************************/ /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: reserved0 [31:05] */ #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_MASK 0xffffffe0 #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_reserved0_SHIFT 5 /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_sub_block_select [04:03] */ #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_MASK 0x00000018 #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_sub_block_select_SHIFT 3 /* SUN_TOP_CTRL :: RO_TEST_BLOCK_SEL :: ro_test_block_select [02:00] */ #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MASK 0x00000007 #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SHIFT 0 #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DO_NOT_USE_RO_TEST_ID 0 #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_SUN_RO_TEST_ID 1 #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_DDR_IF_RO_TEST_ID 2 #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_MISC_RO_TEST_ID 3 #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_BLINK_RO_TEST_ID 4 #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_AVD_RO_TEST_ID 5 #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_RES0_RO_TEST_ID 6 #define BCHP_SUN_TOP_CTRL_RO_TEST_BLOCK_SEL_ro_test_block_select_CLK_GEN_RO_TEST_ID 7 /*************************************************************************** *TEST_MODE_CTRL - Test_mode control register ***************************************************************************/ /* SUN_TOP_CTRL :: TEST_MODE_CTRL :: reserved0 [31:01] */ #define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_reserved0_MASK 0xfffffffe #define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_reserved0_SHIFT 1 /* SUN_TOP_CTRL :: TEST_MODE_CTRL :: use_test_mode_reg_src [00:00] */ #define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_use_test_mode_reg_src_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_TEST_MODE_CTRL_use_test_mode_reg_src_SHIFT 0 /*************************************************************************** *TEST_MODE - Register source for test_mode ***************************************************************************/ /* SUN_TOP_CTRL :: TEST_MODE :: reserved0 [31:04] */ #define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved0_MASK 0xfffffff0 #define BCHP_SUN_TOP_CTRL_TEST_MODE_reserved0_SHIFT 4 /* SUN_TOP_CTRL :: TEST_MODE :: test_mode [03:00] */ #define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_MASK 0x0000000f #define BCHP_SUN_TOP_CTRL_TEST_MODE_test_mode_SHIFT 0 /*************************************************************************** *SUB_TEST_MODE - Register source for sub_test_mode ***************************************************************************/ /* SUN_TOP_CTRL :: SUB_TEST_MODE :: reserved0 [31:02] */ #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_reserved0_MASK 0xfffffffc #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_reserved0_SHIFT 2 /* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_1 [01:01] */ #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_1_SHIFT 1 /* SUN_TOP_CTRL :: SUB_TEST_MODE :: sub_test_mode_spare_0 [00:00] */ #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_SUB_TEST_MODE_sub_test_mode_spare_0_SHIFT 0 /*************************************************************************** *LATCHED_TEST_MODE - Final latched testmode value ***************************************************************************/ /* SUN_TOP_CTRL :: LATCHED_TEST_MODE :: latched_test_mode [31:00] */ #define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE_latched_test_mode_MASK 0xffffffff #define BCHP_SUN_TOP_CTRL_LATCHED_TEST_MODE_latched_test_mode_SHIFT 0 /*************************************************************************** *LATCHED_SUB_TEST_MODE - Final latched sub-testmode value ***************************************************************************/ /* SUN_TOP_CTRL :: LATCHED_SUB_TEST_MODE :: latched_sub_test_mode [31:00] */ #define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_MASK 0xffffffff #define BCHP_SUN_TOP_CTRL_LATCHED_SUB_TEST_MODE_latched_sub_test_mode_SHIFT 0 /*************************************************************************** *PM_CTRL - Control register for Power Controller ***************************************************************************/ /* SUN_TOP_CTRL :: PM_CTRL :: pm_wait_count_upper_bits [31:20] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_count_upper_bits_MASK 0xfff00000 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_count_upper_bits_SHIFT 20 /* SUN_TOP_CTRL :: PM_CTRL :: pm_wait_counter_active [19:19] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_counter_active_MASK 0x00080000 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_wait_counter_active_SHIFT 19 /* SUN_TOP_CTRL :: PM_CTRL :: pm_rst_clock_div [18:18] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_rst_clock_div_MASK 0x00040000 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_rst_clock_div_SHIFT 18 /* SUN_TOP_CTRL :: PM_CTRL :: pm_pwrdn_pll_req [17:17] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pwrdn_pll_req_MASK 0x00020000 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pwrdn_pll_req_SHIFT 17 /* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_cml_clocks [16:16] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cml_clocks_MASK 0x00010000 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cml_clocks_SHIFT 16 /* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_all_clocks [15:15] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_all_clocks_MASK 0x00008000 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_all_clocks_SHIFT 15 /* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_cpu_clock [14:14] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cpu_clock_MASK 0x00004000 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_cpu_clock_SHIFT 14 /* SUN_TOP_CTRL :: PM_CTRL :: pm_dis_avd_rptd_clock [13:13] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_avd_rptd_clock_MASK 0x00002000 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dis_avd_rptd_clock_SHIFT 13 /* SUN_TOP_CTRL :: PM_CTRL :: pm_pll_lock [12:12] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pll_lock_MASK 0x00001000 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_pll_lock_SHIFT 12 /* SUN_TOP_CTRL :: PM_CTRL :: pm_dram_ready_for_pwrdn [11:11] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dram_ready_for_pwrdn_MASK 0x00000800 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_dram_ready_for_pwrdn_SHIFT 11 /* SUN_TOP_CTRL :: PM_CTRL :: pm_bsp_ready_for_pwrdn [10:10] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_bsp_ready_for_pwrdn_MASK 0x00000400 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_bsp_ready_for_pwrdn_SHIFT 10 /* SUN_TOP_CTRL :: PM_CTRL :: pm_mips_ready_for_pwrdn [09:09] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_mips_ready_for_pwrdn_MASK 0x00000200 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_mips_ready_for_pwrdn_SHIFT 9 /* SUN_TOP_CTRL :: PM_CTRL :: pm_sec_avd_rptd_clk_disable [08:08] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_sec_avd_rptd_clk_disable_MASK 0x00000100 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_sec_avd_rptd_clk_disable_SHIFT 8 /* SUN_TOP_CTRL :: PM_CTRL :: pm_state [07:04] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_MASK 0x000000f0 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_SHIFT 4 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_ACTIVE 0 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_PWRDN_RDY 1 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_DISABLE_AVD_RPTD 2 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_DISABLE_CPU 3 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_TRANSITION_TO_STANDBY 4 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_STANDBY 5 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_STANDBY_WITH_PLLS_ON 6 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_RESET_216_108_CLKS 7 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_state_PM_TRANSITION_TO_ACTIVE 8 /* SUN_TOP_CTRL :: PM_CTRL :: pm_power_ctrl_disable [03:03] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_power_ctrl_disable_MASK 0x00000008 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_power_ctrl_disable_SHIFT 3 /* SUN_TOP_CTRL :: PM_CTRL :: pm_use_mips_ready_ctrl [02:02] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_MASK 0x00000004 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_use_mips_ready_ctrl_SHIFT 2 /* SUN_TOP_CTRL :: PM_CTRL :: pm_enable_pll_pwrdn [01:01] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_enable_pll_pwrdn_MASK 0x00000002 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_enable_pll_pwrdn_SHIFT 1 /* SUN_TOP_CTRL :: PM_CTRL :: pm_start_pwrdn [00:00] */ #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_start_pwrdn_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_PM_CTRL_pm_start_pwrdn_SHIFT 0 /*************************************************************************** *PM_IRQ_INPUT_STATUS - Power Management IRQ input status ***************************************************************************/ /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: reserved0 [31:01] */ #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_reserved0_MASK 0xfffffffe #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_reserved0_SHIFT 1 /* SUN_TOP_CTRL :: PM_IRQ_INPUT_STATUS :: spare_wakeup_event_0 [00:00] */ #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_spare_wakeup_event_0_MASK 0x00000001 #define BCHP_SUN_TOP_CTRL_PM_IRQ_INPUT_STATUS_spare_wakeup_event_0_SHIFT 0 /*************************************************************************** *PM_MIPS_WAIT_COUNT - Power Management Wait counter in place of Wait for MIPS IRQ ***************************************************************************/ /* SUN_TOP_CTRL :: PM_MIPS_WAIT_COUNT :: reserved0 [31:16] */ #define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_reserved0_MASK 0xffff0000 #define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_reserved0_SHIFT 16 /* SUN_TOP_CTRL :: PM_MIPS_WAIT_COUNT :: counter_start_value [15:00] */ #define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_MASK 0x0000ffff #define BCHP_SUN_TOP_CTRL_PM_MIPS_WAIT_COUNT_counter_start_value_SHIFT 0 #endif /* #ifndef BCHP_SUN_TOP_CTRL_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015700000000000011570 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_cce_rgr_bridge.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_cce_rg0000644000175000017500000001520411610313111030762 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_cce_rgr_bridge.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:58p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:58 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_cce_rgr_bridge.h $ * * Hydra_Software_Devel/1 7/17/09 7:58p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_CCE_RGR_BRIDGE_H__ #define BCHP_CCE_RGR_BRIDGE_H__ /*************************************************************************** *CCE_RGR_BRIDGE - CCE RGR-bridge related registers ***************************************************************************/ #define BCHP_CCE_RGR_BRIDGE_REVISION 0x005033e0 /* RGR Bridge Revision */ #define BCHP_CCE_RGR_BRIDGE_CTRL 0x005033e4 /* RGR Bridge Control Register */ #define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER 0x005033e8 /* RGR Bridge RBUS Timer Register */ #define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0 0x005033ec /* RGR Bridge Software Reset 0 Register */ #define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1 0x005033f0 /* RGR Bridge Software Reset 1 Register */ /*************************************************************************** *REVISION - RGR Bridge Revision ***************************************************************************/ /* CCE_RGR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define BCHP_CCE_RGR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define BCHP_CCE_RGR_BRIDGE_REVISION_reserved0_SHIFT 16 /* CCE_RGR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define BCHP_CCE_RGR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_CCE_RGR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* CCE_RGR_BRIDGE :: REVISION :: MINOR [07:00] */ #define BCHP_CCE_RGR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define BCHP_CCE_RGR_BRIDGE_REVISION_MINOR_SHIFT 0 /*************************************************************************** *CTRL - RGR Bridge Control Register ***************************************************************************/ /* CCE_RGR_BRIDGE :: CTRL :: reserved0 [31:02] */ #define BCHP_CCE_RGR_BRIDGE_CTRL_reserved0_MASK 0xfffffffc #define BCHP_CCE_RGR_BRIDGE_CTRL_reserved0_SHIFT 2 /* CCE_RGR_BRIDGE :: CTRL :: rbus_error_intr [01:01] */ #define BCHP_CCE_RGR_BRIDGE_CTRL_rbus_error_intr_MASK 0x00000002 #define BCHP_CCE_RGR_BRIDGE_CTRL_rbus_error_intr_SHIFT 1 #define BCHP_CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_DISABLE 0 #define BCHP_CCE_RGR_BRIDGE_CTRL_rbus_error_intr_INTR_ENABLE 1 /* CCE_RGR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ #define BCHP_CCE_RGR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 #define BCHP_CCE_RGR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 #define BCHP_CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 #define BCHP_CCE_RGR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 /*************************************************************************** *RBUS_TIMER - RGR Bridge RBUS Timer Register ***************************************************************************/ /* CCE_RGR_BRIDGE :: RBUS_TIMER :: reserved0 [31:16] */ #define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_MASK 0xffff0000 #define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER_reserved0_SHIFT 16 /* CCE_RGR_BRIDGE :: RBUS_TIMER :: timer_value [15:00] */ #define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_MASK 0x0000ffff #define BCHP_CCE_RGR_BRIDGE_RBUS_TIMER_timer_value_SHIFT 0 /*************************************************************************** *SPARE_SW_RESET_0 - RGR Bridge Software Reset 0 Register ***************************************************************************/ /* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ #define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe #define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 /* CCE_RGR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 #define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 #define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 /*************************************************************************** *SPARE_SW_RESET_1 - RGR Bridge Software Reset 1 Register ***************************************************************************/ /* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ #define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe #define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 /* CCE_RGR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ #define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 #define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 #define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 #define BCHP_CCE_RGR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 #endif /* #ifndef BCHP_CCE_RGR_BRIDGE_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015700000000000011570 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb2.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id0000644000175000017500000000633511610313111031013 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_int_id_xpt_pb2.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:09p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:41 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility unknown * RDB Parser 3.0 * generate_int_id.pl 1.0 * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb2.h $ * * Hydra_Software_Devel/1 7/17/09 8:09p albertl * PR56880: Initial revision. * ***************************************************************************/ #include "bchp.h" #include "bchp_xpt_pb0.h" #include "bchp_xpt_pb2.h" #ifndef BCHP_INT_ID_XPT_PB2_H__ #define BCHP_INT_ID_XPT_PB2_H__ #define BCHP_INT_ID_XPT_PB2_DONE_INT BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_DONE_INT_SHIFT) #define BCHP_INT_ID_XPT_PB2_PARSER_CONTINUITY_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_PARSER_CONTINUITY_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB2_PARSER_LENGTH_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_PARSER_LENGTH_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB2_PARSER_SEC_CC_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_PARSER_SEC_CC_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB2_PARSER_TRANSPORT_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_PARSER_TRANSPORT_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB2_PB_COPYRIGHT_CHANGE BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_PB_COPYRIGHT_CHANGE_SHIFT) #define BCHP_INT_ID_XPT_PB2_SE_OUT_OF_SYNC_INT BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_SE_OUT_OF_SYNC_INT_SHIFT) #define BCHP_INT_ID_XPT_PB2_TS_PARITY_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_TS_PARITY_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB2_TS_RANGE_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB2_INTR, BCHP_XPT_PB0_INTR_TS_RANGE_ERROR_SHIFT) #endif /* #ifndef BCHP_INT_ID_XPT_PB2_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016500000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_control_regs.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_ar0000644000175000017500000004471511610313111031025 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_arb_control_regs.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:14p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:12 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_control_regs.h $ * * Hydra_Software_Devel/1 7/17/09 8:14p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_ARB_CONTROL_REGS_H__ #define BCHP_PRI_ARB_CONTROL_REGS_H__ /*************************************************************************** *PRI_ARB_CONTROL_REGS - PRIMARY_ARB control registers ***************************************************************************/ #define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0 0x0040cb00 /* Refresh client control for ddr interface #0 */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0 0x0040cb04 /* Write timeout control for ddr interface #0 */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0 0x0040cb08 /* Write timeout status for ddr interface #0 */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0 0x0040cb0c /* Write timeout status clear for ddr interface #0 */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC 0x0040cb10 /* Write timeout bad concentrators */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL 0x0040cb14 /* Performance Monitor Control */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR 0x0040cb18 /* Performance Monitor Clear Counts */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_EVENTS_0 0x0040cb1c /* Performance Monitor Events for ddr interface #0 */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SUM_0 0x0040cb20 /* Performance Monitor Sum of Latencies for ddr interface #0 */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SIZE_SUM_0 0x0040cb24 /* Performance Monitor Sum of Request Sizes for ddr interface #0 */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_MAX_0 0x0040cb28 /* Performance Monitor Maximum Latency for ddr interface #0 */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A 0x0040cb2c /* Performance Monitor Client Access bits 19:0 for ddr interface #0 */ #define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL 0x0040cb30 /* Master Control */ /*************************************************************************** *REFRESH_CTL_0 - Refresh client control for ddr interface #0 ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: REFRESH_CTL_0 :: reserved0 [31:13] */ #define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_reserved0_MASK 0xffffe000 #define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_reserved0_SHIFT 13 /* PRI_ARB_CONTROL_REGS :: REFRESH_CTL_0 :: enable [12:12] */ #define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_enable_MASK 0x00001000 #define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_enable_SHIFT 12 /* PRI_ARB_CONTROL_REGS :: REFRESH_CTL_0 :: period [11:00] */ #define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_period_MASK 0x00000fff #define BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_period_SHIFT 0 /*************************************************************************** *WR_TIMEOUT_CTL_0 - Write timeout control for ddr interface #0 ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CTL_0 :: reserved0 [31:13] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_reserved0_MASK 0xffffe000 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_reserved0_SHIFT 13 /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CTL_0 :: enable [12:12] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_enable_MASK 0x00001000 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_enable_SHIFT 12 /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CTL_0 :: period [11:00] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_period_MASK 0x00000fff #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CTL_0_period_SHIFT 0 /*************************************************************************** *WR_TIMEOUT_STS_0 - Write timeout status for ddr interface #0 ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: reserved0 [31:10] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_reserved0_MASK 0xfffffc00 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_reserved0_SHIFT 10 /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: long [09:09] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_long_MASK 0x00000200 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_long_SHIFT 9 /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: short [08:08] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_short_MASK 0x00000100 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_short_SHIFT 8 /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: reserved1 [07:07] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_reserved1_MASK 0x00000080 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_reserved1_SHIFT 7 /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_STS_0 :: client [06:00] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_client_MASK 0x0000007f #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_STS_0_client_SHIFT 0 /*************************************************************************** *WR_TIMEOUT_CLR_0 - Write timeout status clear for ddr interface #0 ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CLR_0 :: reserved0 [31:01] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0_reserved0_MASK 0xfffffffe #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0_reserved0_SHIFT 1 /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_CLR_0 :: clear [00:00] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0_clear_MASK 0x00000001 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_CLR_0_clear_SHIFT 0 /*************************************************************************** *WR_TIMEOUT_BAD_CONC - Write timeout bad concentrators ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: reserved0 [31:07] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_reserved0_MASK 0xffffff80 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_reserved0_SHIFT 7 /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_06 [06:06] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_06_MASK 0x00000040 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_06_SHIFT 6 /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_05 [05:05] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_05_MASK 0x00000020 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_05_SHIFT 5 /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_04 [04:04] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_04_MASK 0x00000010 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_04_SHIFT 4 /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_03 [03:03] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_03_MASK 0x00000008 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_03_SHIFT 3 /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_02 [02:02] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_02_MASK 0x00000004 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_02_SHIFT 2 /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_01 [01:01] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_01_MASK 0x00000002 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_01_SHIFT 1 /* PRI_ARB_CONTROL_REGS :: WR_TIMEOUT_BAD_CONC :: CONC_00 [00:00] */ #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_00_MASK 0x00000001 #define BCHP_PRI_ARB_CONTROL_REGS_WR_TIMEOUT_BAD_CONC_CONC_00_SHIFT 0 /*************************************************************************** *PERF_MON_CTL - Performance Monitor Control ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: reserved0 [31:16] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_reserved0_MASK 0xffff0000 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_reserved0_SHIFT 16 /* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: client_sel [15:08] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_client_sel_MASK 0x0000ff00 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_client_sel_SHIFT 8 /* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: reserved1 [07:03] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_reserved1_MASK 0x000000f8 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_reserved1_SHIFT 3 /* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: wr_enable [02:02] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_wr_enable_MASK 0x00000004 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_wr_enable_SHIFT 2 /* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: rd_enable [01:01] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_rd_enable_MASK 0x00000002 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_rd_enable_SHIFT 1 /* PRI_ARB_CONTROL_REGS :: PERF_MON_CTL :: enable [00:00] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_enable_MASK 0x00000001 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CTL_enable_SHIFT 0 /*************************************************************************** *PERF_MON_CLR - Performance Monitor Clear Counts ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: PERF_MON_CLR :: reserved0 [31:01] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR_reserved0_MASK 0xfffffffe #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR_reserved0_SHIFT 1 /* PRI_ARB_CONTROL_REGS :: PERF_MON_CLR :: clear [00:00] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR_clear_MASK 0x00000001 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_CLR_clear_SHIFT 0 /*************************************************************************** *PERF_MON_EVENTS_0 - Performance Monitor Events for ddr interface #0 ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: PERF_MON_EVENTS_0 :: count [31:00] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_EVENTS_0_count_MASK 0xffffffff #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_EVENTS_0_count_SHIFT 0 /*************************************************************************** *PERF_MON_SUM_0 - Performance Monitor Sum of Latencies for ddr interface #0 ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: PERF_MON_SUM_0 :: count [31:00] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SUM_0_count_MASK 0xffffffff #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SUM_0_count_SHIFT 0 /*************************************************************************** *PERF_MON_SIZE_SUM_0 - Performance Monitor Sum of Request Sizes for ddr interface #0 ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: PERF_MON_SIZE_SUM_0 :: count [31:00] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SIZE_SUM_0_count_MASK 0xffffffff #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_SIZE_SUM_0_count_SHIFT 0 /*************************************************************************** *PERF_MON_MAX_0 - Performance Monitor Maximum Latency for ddr interface #0 ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: PERF_MON_MAX_0 :: count [31:00] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_MAX_0_count_MASK 0xffffffff #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_MAX_0_count_SHIFT 0 /*************************************************************************** *PERF_MON_ACCESS_0A - Performance Monitor Client Access bits 19:0 for ddr interface #0 ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: reserved0 [31:20] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_reserved0_MASK 0xfff00000 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_reserved0_SHIFT 20 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_19 [19:19] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_19_MASK 0x00080000 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_19_SHIFT 19 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_18 [18:18] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_18_MASK 0x00040000 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_18_SHIFT 18 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_17 [17:17] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_17_MASK 0x00020000 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_17_SHIFT 17 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_16 [16:16] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_16_MASK 0x00010000 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_16_SHIFT 16 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_15 [15:15] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_15_MASK 0x00008000 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_15_SHIFT 15 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_14 [14:14] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_14_MASK 0x00004000 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_14_SHIFT 14 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_13 [13:13] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_13_MASK 0x00002000 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_13_SHIFT 13 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_12 [12:12] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_12_MASK 0x00001000 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_12_SHIFT 12 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_11 [11:11] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_11_MASK 0x00000800 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_11_SHIFT 11 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_10 [10:10] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_10_MASK 0x00000400 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_10_SHIFT 10 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_09 [09:09] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_09_MASK 0x00000200 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_09_SHIFT 9 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_08 [08:08] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_08_MASK 0x00000100 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_08_SHIFT 8 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_07 [07:07] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_07_MASK 0x00000080 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_07_SHIFT 7 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_06 [06:06] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_06_MASK 0x00000040 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_06_SHIFT 6 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_05 [05:05] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_05_MASK 0x00000020 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_05_SHIFT 5 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_04 [04:04] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_04_MASK 0x00000010 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_04_SHIFT 4 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_03 [03:03] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_03_MASK 0x00000008 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_03_SHIFT 3 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_02 [02:02] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_02_MASK 0x00000004 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_02_SHIFT 2 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_01 [01:01] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_01_MASK 0x00000002 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_01_SHIFT 1 /* PRI_ARB_CONTROL_REGS :: PERF_MON_ACCESS_0A :: CLIENT_00 [00:00] */ #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_00_MASK 0x00000001 #define BCHP_PRI_ARB_CONTROL_REGS_PERF_MON_ACCESS_0A_CLIENT_00_SHIFT 0 /*************************************************************************** *MASTER_CTL - Master Control ***************************************************************************/ /* PRI_ARB_CONTROL_REGS :: MASTER_CTL :: reserved0 [31:01] */ #define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_reserved0_MASK 0xfffffffe #define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_reserved0_SHIFT 1 /* PRI_ARB_CONTROL_REGS :: MASTER_CTL :: arb_disable [00:00] */ #define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_MASK 0x00000001 #define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_SHIFT 0 #define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Enable 0 #define BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Disable 1 #endif /* #ifndef BCHP_PRI_ARB_CONTROL_REGS_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015100000000000011562 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_arm_uart.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_arm_ua0000644000175000017500000001375711610313111031017 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_arm_uart.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:28p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:25 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_arm_uart.h $ * * Hydra_Software_Devel/1 7/17/09 8:28p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_ARM_UART_H__ #define BCHP_ARM_UART_H__ /*************************************************************************** *ARM_UART - ARM UART ***************************************************************************/ #define BCHP_ARM_UART_DATA 0x000f3000 /* Transmit/receive data */ #define BCHP_ARM_UART_CTL 0x000f3004 /* Control register and Clock Divider */ #define BCHP_ARM_UART_STATUS 0x000f3008 /* Status register */ /*************************************************************************** *DATA - Transmit/receive data ***************************************************************************/ /* ARM_UART :: DATA :: reserved0 [31:09] */ #define BCHP_ARM_UART_DATA_reserved0_MASK 0xfffffe00 #define BCHP_ARM_UART_DATA_reserved0_SHIFT 9 /* ARM_UART :: DATA :: PErr [08:08] */ #define BCHP_ARM_UART_DATA_PErr_MASK 0x00000100 #define BCHP_ARM_UART_DATA_PErr_SHIFT 8 /* ARM_UART :: DATA :: Data [07:00] */ #define BCHP_ARM_UART_DATA_Data_MASK 0x000000ff #define BCHP_ARM_UART_DATA_Data_SHIFT 0 /*************************************************************************** *CTL - Control register and Clock Divider ***************************************************************************/ /* ARM_UART :: CTL :: ClkDiv [31:16] */ #define BCHP_ARM_UART_CTL_ClkDiv_MASK 0xffff0000 #define BCHP_ARM_UART_CTL_ClkDiv_SHIFT 16 /* ARM_UART :: CTL :: reserved0 [15:05] */ #define BCHP_ARM_UART_CTL_reserved0_MASK 0x0000ffe0 #define BCHP_ARM_UART_CTL_reserved0_SHIFT 5 /* ARM_UART :: CTL :: RcvIntEna [04:04] */ #define BCHP_ARM_UART_CTL_RcvIntEna_MASK 0x00000010 #define BCHP_ARM_UART_CTL_RcvIntEna_SHIFT 4 /* ARM_UART :: CTL :: XmitIntEna [03:03] */ #define BCHP_ARM_UART_CTL_XmitIntEna_MASK 0x00000008 #define BCHP_ARM_UART_CTL_XmitIntEna_SHIFT 3 /* ARM_UART :: CTL :: EvenParity [02:02] */ #define BCHP_ARM_UART_CTL_EvenParity_MASK 0x00000004 #define BCHP_ARM_UART_CTL_EvenParity_SHIFT 2 /* ARM_UART :: CTL :: UseParity [01:01] */ #define BCHP_ARM_UART_CTL_UseParity_MASK 0x00000002 #define BCHP_ARM_UART_CTL_UseParity_SHIFT 1 /* ARM_UART :: CTL :: UartEna [00:00] */ #define BCHP_ARM_UART_CTL_UartEna_MASK 0x00000001 #define BCHP_ARM_UART_CTL_UartEna_SHIFT 0 /*************************************************************************** *STATUS - Status register ***************************************************************************/ /* ARM_UART :: STATUS :: reserved0 [31:05] */ #define BCHP_ARM_UART_STATUS_reserved0_MASK 0xffffffe0 #define BCHP_ARM_UART_STATUS_reserved0_SHIFT 5 /* ARM_UART :: STATUS :: XmitOverflow [04:04] */ #define BCHP_ARM_UART_STATUS_XmitOverflow_MASK 0x00000010 #define BCHP_ARM_UART_STATUS_XmitOverflow_SHIFT 4 /* ARM_UART :: STATUS :: XmitActive [03:03] */ #define BCHP_ARM_UART_STATUS_XmitActive_MASK 0x00000008 #define BCHP_ARM_UART_STATUS_XmitActive_SHIFT 3 /* ARM_UART :: STATUS :: RcvOverflow [02:02] */ #define BCHP_ARM_UART_STATUS_RcvOverflow_MASK 0x00000004 #define BCHP_ARM_UART_STATUS_RcvOverflow_SHIFT 2 /* ARM_UART :: STATUS :: reserved1 [01:01] */ #define BCHP_ARM_UART_STATUS_reserved1_MASK 0x00000002 #define BCHP_ARM_UART_STATUS_reserved1_SHIFT 1 /* ARM_UART :: STATUS :: RcvFifoEmpty [00:00] */ #define BCHP_ARM_UART_STATUS_RcvFifoEmpty_MASK 0x00000001 #define BCHP_ARM_UART_STATUS_RcvFifoEmpty_SHIFT 0 #endif /* #ifndef BCHP_ARM_UART_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016500000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_mips_l2_regs.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_ar0000644000175000017500000007617511610313111031032 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_arb_mips_l2_regs.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:14p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:15 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_mips_l2_regs.h $ * * Hydra_Software_Devel/1 7/17/09 8:14p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_ARB_MIPS_L2_REGS_H__ #define BCHP_PRI_ARB_MIPS_L2_REGS_H__ /*************************************************************************** *PRI_ARB_MIPS_L2_REGS - PRIMARY_ARB L2 (MIPS) Interrupt Registers ***************************************************************************/ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS 0x0040ce00 /* CPU interrupt Status Register */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET 0x0040ce04 /* CPU interrupt Set Register */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR 0x0040ce08 /* CPU interrupt Clear Register */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS 0x0040ce0c /* CPU interrupt Mask Status Register */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET 0x0040ce10 /* CPU interrupt Mask Set Register */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR 0x0040ce14 /* CPU interrupt Mask Clear Register */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS 0x0040ce18 /* PCI interrupt Status Register */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET 0x0040ce1c /* PCI interrupt Set Register */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR 0x0040ce20 /* PCI interrupt Clear Register */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS 0x0040ce24 /* PCI interrupt Mask Status Register */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET 0x0040ce28 /* PCI interrupt Mask Set Register */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR 0x0040ce2c /* PCI interrupt Mask Clear Register */ /*************************************************************************** *CPU_STATUS - CPU interrupt Status Register ***************************************************************************/ /* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: reserved0 [31:09] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_reserved0_MASK 0xfffffe00 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_reserved0_SHIFT 9 /* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ALIAS_INTR [08:08] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ALIAS_INTR_MASK 0x00000100 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ALIAS_INTR_SHIFT 8 /* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: WR_TIMEOUT_1_INTR [07:07] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_WR_TIMEOUT_1_INTR_MASK 0x00000080 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_WR_TIMEOUT_1_INTR_SHIFT 7 /* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: WR_TIMEOUT_0_INTR [06:06] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_WR_TIMEOUT_0_INTR_MASK 0x00000040 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_WR_TIMEOUT_0_INTR_SHIFT 6 /* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: TRACE_DONE_INTR [05:05] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_TRACE_DONE_INTR_MASK 0x00000020 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_TRACE_DONE_INTR_SHIFT 5 /* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: TRACE_TRIG_INTR [04:04] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_TRACE_TRIG_INTR_MASK 0x00000010 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_TRACE_TRIG_INTR_SHIFT 4 /* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ARCH3_INTR [03:03] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH3_INTR_MASK 0x00000008 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH3_INTR_SHIFT 3 /* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ARCH2_INTR [02:02] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH2_INTR_MASK 0x00000004 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH2_INTR_SHIFT 2 /* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ARCH1_INTR [01:01] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH1_INTR_MASK 0x00000002 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH1_INTR_SHIFT 1 /* PRI_ARB_MIPS_L2_REGS :: CPU_STATUS :: ARCH0_INTR [00:00] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH0_INTR_MASK 0x00000001 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_STATUS_ARCH0_INTR_SHIFT 0 /*************************************************************************** *CPU_SET - CPU interrupt Set Register ***************************************************************************/ /* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: reserved0 [31:09] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_reserved0_MASK 0xfffffe00 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_reserved0_SHIFT 9 /* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ALIAS_INTR [08:08] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ALIAS_INTR_MASK 0x00000100 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ALIAS_INTR_SHIFT 8 /* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: WR_TIMEOUT_1_INTR [07:07] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_WR_TIMEOUT_1_INTR_MASK 0x00000080 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_WR_TIMEOUT_1_INTR_SHIFT 7 /* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: WR_TIMEOUT_0_INTR [06:06] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_WR_TIMEOUT_0_INTR_MASK 0x00000040 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_WR_TIMEOUT_0_INTR_SHIFT 6 /* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: TRACE_DONE_INTR [05:05] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_TRACE_DONE_INTR_MASK 0x00000020 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_TRACE_DONE_INTR_SHIFT 5 /* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: TRACE_TRIG_INTR [04:04] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_TRACE_TRIG_INTR_MASK 0x00000010 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_TRACE_TRIG_INTR_SHIFT 4 /* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ARCH3_INTR [03:03] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH3_INTR_MASK 0x00000008 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH3_INTR_SHIFT 3 /* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ARCH2_INTR [02:02] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH2_INTR_MASK 0x00000004 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH2_INTR_SHIFT 2 /* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ARCH1_INTR [01:01] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH1_INTR_MASK 0x00000002 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH1_INTR_SHIFT 1 /* PRI_ARB_MIPS_L2_REGS :: CPU_SET :: ARCH0_INTR [00:00] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH0_INTR_MASK 0x00000001 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_SET_ARCH0_INTR_SHIFT 0 /*************************************************************************** *CPU_CLEAR - CPU interrupt Clear Register ***************************************************************************/ /* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: reserved0 [31:09] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_reserved0_MASK 0xfffffe00 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_reserved0_SHIFT 9 /* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ALIAS_INTR [08:08] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ALIAS_INTR_MASK 0x00000100 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ALIAS_INTR_SHIFT 8 /* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: WR_TIMEOUT_1_INTR [07:07] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_WR_TIMEOUT_1_INTR_MASK 0x00000080 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_WR_TIMEOUT_1_INTR_SHIFT 7 /* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: WR_TIMEOUT_0_INTR [06:06] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_WR_TIMEOUT_0_INTR_MASK 0x00000040 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_WR_TIMEOUT_0_INTR_SHIFT 6 /* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: TRACE_DONE_INTR [05:05] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_TRACE_DONE_INTR_MASK 0x00000020 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_TRACE_DONE_INTR_SHIFT 5 /* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: TRACE_TRIG_INTR [04:04] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_TRACE_TRIG_INTR_MASK 0x00000010 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_TRACE_TRIG_INTR_SHIFT 4 /* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ARCH3_INTR [03:03] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH3_INTR_MASK 0x00000008 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH3_INTR_SHIFT 3 /* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ARCH2_INTR [02:02] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH2_INTR_MASK 0x00000004 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH2_INTR_SHIFT 2 /* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ARCH1_INTR [01:01] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH1_INTR_MASK 0x00000002 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH1_INTR_SHIFT 1 /* PRI_ARB_MIPS_L2_REGS :: CPU_CLEAR :: ARCH0_INTR [00:00] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH0_INTR_MASK 0x00000001 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_CLEAR_ARCH0_INTR_SHIFT 0 /*************************************************************************** *CPU_MASK_STATUS - CPU interrupt Mask Status Register ***************************************************************************/ /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: reserved0 [31:09] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_reserved0_MASK 0xfffffe00 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_reserved0_SHIFT 9 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ALIAS_MASK [08:08] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ALIAS_MASK_MASK 0x00000100 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ALIAS_MASK_SHIFT 8 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: WR_TIMEOUT_1_MASK [07:07] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_WR_TIMEOUT_1_MASK_MASK 0x00000080 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_WR_TIMEOUT_1_MASK_SHIFT 7 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: WR_TIMEOUT_0_MASK [06:06] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_WR_TIMEOUT_0_MASK_MASK 0x00000040 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_WR_TIMEOUT_0_MASK_SHIFT 6 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: TRACE_DONE_MASK [05:05] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_TRACE_DONE_MASK_MASK 0x00000020 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_TRACE_DONE_MASK_SHIFT 5 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: TRACE_TRIG_MASK [04:04] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_TRACE_TRIG_MASK_MASK 0x00000010 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_TRACE_TRIG_MASK_SHIFT 4 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ARCH3_MASK [03:03] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH3_MASK_MASK 0x00000008 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH3_MASK_SHIFT 3 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ARCH2_MASK [02:02] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH2_MASK_MASK 0x00000004 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH2_MASK_SHIFT 2 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ARCH1_MASK [01:01] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH1_MASK_MASK 0x00000002 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH1_MASK_SHIFT 1 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_STATUS :: ARCH0_MASK [00:00] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH0_MASK_MASK 0x00000001 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_STATUS_ARCH0_MASK_SHIFT 0 /*************************************************************************** *CPU_MASK_SET - CPU interrupt Mask Set Register ***************************************************************************/ /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: reserved0 [31:09] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_reserved0_MASK 0xfffffe00 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_reserved0_SHIFT 9 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ALIAS_MASK [08:08] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ALIAS_MASK_MASK 0x00000100 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ALIAS_MASK_SHIFT 8 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: WR_TIMEOUT_1_MASK [07:07] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_WR_TIMEOUT_1_MASK_MASK 0x00000080 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_WR_TIMEOUT_1_MASK_SHIFT 7 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: WR_TIMEOUT_0_MASK [06:06] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_WR_TIMEOUT_0_MASK_MASK 0x00000040 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_WR_TIMEOUT_0_MASK_SHIFT 6 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: TRACE_DONE_MASK [05:05] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_TRACE_DONE_MASK_MASK 0x00000020 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_TRACE_DONE_MASK_SHIFT 5 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: TRACE_TRIG_MASK [04:04] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_TRACE_TRIG_MASK_MASK 0x00000010 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_TRACE_TRIG_MASK_SHIFT 4 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ARCH3_MASK [03:03] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH3_MASK_MASK 0x00000008 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH3_MASK_SHIFT 3 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ARCH2_MASK [02:02] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH2_MASK_MASK 0x00000004 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH2_MASK_SHIFT 2 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ARCH1_MASK [01:01] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH1_MASK_MASK 0x00000002 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH1_MASK_SHIFT 1 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_SET :: ARCH0_MASK [00:00] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH0_MASK_MASK 0x00000001 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_SET_ARCH0_MASK_SHIFT 0 /*************************************************************************** *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register ***************************************************************************/ /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: reserved0 [31:09] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_reserved0_MASK 0xfffffe00 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_reserved0_SHIFT 9 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ALIAS_MASK [08:08] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ALIAS_MASK_MASK 0x00000100 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ALIAS_MASK_SHIFT 8 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: WR_TIMEOUT_1_MASK [07:07] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_WR_TIMEOUT_1_MASK_MASK 0x00000080 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_WR_TIMEOUT_1_MASK_SHIFT 7 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: WR_TIMEOUT_0_MASK [06:06] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_WR_TIMEOUT_0_MASK_MASK 0x00000040 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_WR_TIMEOUT_0_MASK_SHIFT 6 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: TRACE_DONE_MASK [05:05] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_TRACE_DONE_MASK_MASK 0x00000020 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_TRACE_DONE_MASK_SHIFT 5 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: TRACE_TRIG_MASK [04:04] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_TRACE_TRIG_MASK_MASK 0x00000010 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_TRACE_TRIG_MASK_SHIFT 4 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ARCH3_MASK [03:03] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH3_MASK_MASK 0x00000008 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH3_MASK_SHIFT 3 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ARCH2_MASK [02:02] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH2_MASK_MASK 0x00000004 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH2_MASK_SHIFT 2 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ARCH1_MASK [01:01] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH1_MASK_MASK 0x00000002 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH1_MASK_SHIFT 1 /* PRI_ARB_MIPS_L2_REGS :: CPU_MASK_CLEAR :: ARCH0_MASK [00:00] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH0_MASK_MASK 0x00000001 #define BCHP_PRI_ARB_MIPS_L2_REGS_CPU_MASK_CLEAR_ARCH0_MASK_SHIFT 0 /*************************************************************************** *PCI_STATUS - PCI interrupt Status Register ***************************************************************************/ /* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: reserved0 [31:09] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_reserved0_MASK 0xfffffe00 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_reserved0_SHIFT 9 /* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ALIAS_INTR [08:08] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ALIAS_INTR_MASK 0x00000100 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ALIAS_INTR_SHIFT 8 /* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: WR_TIMEOUT_1_INTR [07:07] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_WR_TIMEOUT_1_INTR_MASK 0x00000080 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_WR_TIMEOUT_1_INTR_SHIFT 7 /* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: WR_TIMEOUT_0_INTR [06:06] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_WR_TIMEOUT_0_INTR_MASK 0x00000040 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_WR_TIMEOUT_0_INTR_SHIFT 6 /* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: TRACE_DONE_INTR [05:05] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_TRACE_DONE_INTR_MASK 0x00000020 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_TRACE_DONE_INTR_SHIFT 5 /* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: TRACE_TRIG_INTR [04:04] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_TRACE_TRIG_INTR_MASK 0x00000010 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_TRACE_TRIG_INTR_SHIFT 4 /* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ARCH3_INTR [03:03] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH3_INTR_MASK 0x00000008 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH3_INTR_SHIFT 3 /* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ARCH2_INTR [02:02] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH2_INTR_MASK 0x00000004 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH2_INTR_SHIFT 2 /* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ARCH1_INTR [01:01] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH1_INTR_MASK 0x00000002 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH1_INTR_SHIFT 1 /* PRI_ARB_MIPS_L2_REGS :: PCI_STATUS :: ARCH0_INTR [00:00] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH0_INTR_MASK 0x00000001 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_STATUS_ARCH0_INTR_SHIFT 0 /*************************************************************************** *PCI_SET - PCI interrupt Set Register ***************************************************************************/ /* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: reserved0 [31:09] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_reserved0_MASK 0xfffffe00 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_reserved0_SHIFT 9 /* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ALIAS_INTR [08:08] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ALIAS_INTR_MASK 0x00000100 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ALIAS_INTR_SHIFT 8 /* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: WR_TIMEOUT_1_INTR [07:07] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_WR_TIMEOUT_1_INTR_MASK 0x00000080 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_WR_TIMEOUT_1_INTR_SHIFT 7 /* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: WR_TIMEOUT_0_INTR [06:06] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_WR_TIMEOUT_0_INTR_MASK 0x00000040 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_WR_TIMEOUT_0_INTR_SHIFT 6 /* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: TRACE_DONE_INTR [05:05] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_TRACE_DONE_INTR_MASK 0x00000020 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_TRACE_DONE_INTR_SHIFT 5 /* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: TRACE_TRIG_INTR [04:04] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_TRACE_TRIG_INTR_MASK 0x00000010 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_TRACE_TRIG_INTR_SHIFT 4 /* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ARCH3_INTR [03:03] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH3_INTR_MASK 0x00000008 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH3_INTR_SHIFT 3 /* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ARCH2_INTR [02:02] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH2_INTR_MASK 0x00000004 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH2_INTR_SHIFT 2 /* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ARCH1_INTR [01:01] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH1_INTR_MASK 0x00000002 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH1_INTR_SHIFT 1 /* PRI_ARB_MIPS_L2_REGS :: PCI_SET :: ARCH0_INTR [00:00] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH0_INTR_MASK 0x00000001 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_SET_ARCH0_INTR_SHIFT 0 /*************************************************************************** *PCI_CLEAR - PCI interrupt Clear Register ***************************************************************************/ /* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: reserved0 [31:09] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_reserved0_MASK 0xfffffe00 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_reserved0_SHIFT 9 /* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ALIAS_INTR [08:08] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ALIAS_INTR_MASK 0x00000100 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ALIAS_INTR_SHIFT 8 /* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: WR_TIMEOUT_1_INTR [07:07] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_WR_TIMEOUT_1_INTR_MASK 0x00000080 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_WR_TIMEOUT_1_INTR_SHIFT 7 /* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: WR_TIMEOUT_0_INTR [06:06] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_WR_TIMEOUT_0_INTR_MASK 0x00000040 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_WR_TIMEOUT_0_INTR_SHIFT 6 /* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: TRACE_DONE_INTR [05:05] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_TRACE_DONE_INTR_MASK 0x00000020 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_TRACE_DONE_INTR_SHIFT 5 /* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: TRACE_TRIG_INTR [04:04] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_TRACE_TRIG_INTR_MASK 0x00000010 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_TRACE_TRIG_INTR_SHIFT 4 /* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ARCH3_INTR [03:03] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH3_INTR_MASK 0x00000008 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH3_INTR_SHIFT 3 /* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ARCH2_INTR [02:02] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH2_INTR_MASK 0x00000004 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH2_INTR_SHIFT 2 /* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ARCH1_INTR [01:01] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH1_INTR_MASK 0x00000002 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH1_INTR_SHIFT 1 /* PRI_ARB_MIPS_L2_REGS :: PCI_CLEAR :: ARCH0_INTR [00:00] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH0_INTR_MASK 0x00000001 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_CLEAR_ARCH0_INTR_SHIFT 0 /*************************************************************************** *PCI_MASK_STATUS - PCI interrupt Mask Status Register ***************************************************************************/ /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: reserved0 [31:09] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_reserved0_MASK 0xfffffe00 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_reserved0_SHIFT 9 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ALIAS_MASK [08:08] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ALIAS_MASK_MASK 0x00000100 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ALIAS_MASK_SHIFT 8 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: WR_TIMEOUT_1_MASK [07:07] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_WR_TIMEOUT_1_MASK_MASK 0x00000080 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_WR_TIMEOUT_1_MASK_SHIFT 7 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: WR_TIMEOUT_0_MASK [06:06] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_WR_TIMEOUT_0_MASK_MASK 0x00000040 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_WR_TIMEOUT_0_MASK_SHIFT 6 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: TRACE_DONE_MASK [05:05] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_TRACE_DONE_MASK_MASK 0x00000020 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_TRACE_DONE_MASK_SHIFT 5 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: TRACE_TRIG_MASK [04:04] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_TRACE_TRIG_MASK_MASK 0x00000010 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_TRACE_TRIG_MASK_SHIFT 4 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ARCH3_MASK [03:03] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH3_MASK_MASK 0x00000008 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH3_MASK_SHIFT 3 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ARCH2_MASK [02:02] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH2_MASK_MASK 0x00000004 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH2_MASK_SHIFT 2 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ARCH1_MASK [01:01] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH1_MASK_MASK 0x00000002 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH1_MASK_SHIFT 1 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_STATUS :: ARCH0_MASK [00:00] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH0_MASK_MASK 0x00000001 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_STATUS_ARCH0_MASK_SHIFT 0 /*************************************************************************** *PCI_MASK_SET - PCI interrupt Mask Set Register ***************************************************************************/ /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: reserved0 [31:09] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_reserved0_MASK 0xfffffe00 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_reserved0_SHIFT 9 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ALIAS_MASK [08:08] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ALIAS_MASK_MASK 0x00000100 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ALIAS_MASK_SHIFT 8 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: WR_TIMEOUT_1_MASK [07:07] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_WR_TIMEOUT_1_MASK_MASK 0x00000080 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_WR_TIMEOUT_1_MASK_SHIFT 7 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: WR_TIMEOUT_0_MASK [06:06] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_WR_TIMEOUT_0_MASK_MASK 0x00000040 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_WR_TIMEOUT_0_MASK_SHIFT 6 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: TRACE_DONE_MASK [05:05] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_TRACE_DONE_MASK_MASK 0x00000020 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_TRACE_DONE_MASK_SHIFT 5 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: TRACE_TRIG_MASK [04:04] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_TRACE_TRIG_MASK_MASK 0x00000010 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_TRACE_TRIG_MASK_SHIFT 4 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ARCH3_MASK [03:03] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH3_MASK_MASK 0x00000008 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH3_MASK_SHIFT 3 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ARCH2_MASK [02:02] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH2_MASK_MASK 0x00000004 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH2_MASK_SHIFT 2 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ARCH1_MASK [01:01] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH1_MASK_MASK 0x00000002 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH1_MASK_SHIFT 1 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_SET :: ARCH0_MASK [00:00] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH0_MASK_MASK 0x00000001 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_SET_ARCH0_MASK_SHIFT 0 /*************************************************************************** *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register ***************************************************************************/ /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: reserved0 [31:09] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_reserved0_MASK 0xfffffe00 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_reserved0_SHIFT 9 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ALIAS_MASK [08:08] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ALIAS_MASK_MASK 0x00000100 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ALIAS_MASK_SHIFT 8 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: WR_TIMEOUT_1_MASK [07:07] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_WR_TIMEOUT_1_MASK_MASK 0x00000080 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_WR_TIMEOUT_1_MASK_SHIFT 7 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: WR_TIMEOUT_0_MASK [06:06] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_WR_TIMEOUT_0_MASK_MASK 0x00000040 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_WR_TIMEOUT_0_MASK_SHIFT 6 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: TRACE_DONE_MASK [05:05] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_TRACE_DONE_MASK_MASK 0x00000020 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_TRACE_DONE_MASK_SHIFT 5 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: TRACE_TRIG_MASK [04:04] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_TRACE_TRIG_MASK_MASK 0x00000010 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_TRACE_TRIG_MASK_SHIFT 4 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ARCH3_MASK [03:03] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH3_MASK_MASK 0x00000008 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH3_MASK_SHIFT 3 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ARCH2_MASK [02:02] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH2_MASK_MASK 0x00000004 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH2_MASK_SHIFT 2 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ARCH1_MASK [01:01] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH1_MASK_MASK 0x00000002 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH1_MASK_SHIFT 1 /* PRI_ARB_MIPS_L2_REGS :: PCI_MASK_CLEAR :: ARCH0_MASK [00:00] */ #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH0_MASK_MASK 0x00000001 #define BCHP_PRI_ARB_MIPS_L2_REGS_PCI_MASK_CLEAR_ARCH0_MASK_SHIFT 0 #endif /* #ifndef BCHP_PRI_ARB_MIPS_L2_REGS_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000014600000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_tmisc.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_tmisc.0000644000175000017500000001613711610313111030743 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_tmisc.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:21p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:17 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_tmisc.h $ * * Hydra_Software_Devel/1 7/17/09 8:21p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_TMISC_H__ #define BCHP_TMISC_H__ /*************************************************************************** *TMISC - BVN Top Control Registers ***************************************************************************/ #define BCHP_TMISC_SOFT_RESET 0x00541400 /* BVN TOP Soft Reset */ #define BCHP_TMISC_TEST_PORT_DATA 0x00541404 /* BVN TOP Test Port Status */ #define BCHP_TMISC_TEST_PORT_CTRL 0x00541408 /* BVN TOP Test Port Control */ #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_MFD 0x00541410 /* BVN TOP MBIST TM Control for MFD */ #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_DNR 0x00541414 /* BVN TOP MBIST TM Control for DNR */ #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_SCL 0x00541418 /* BVN TOP MBIST TM Control for SCL */ #define BCHP_TMISC_SCRATCH_0 0x0054143c /* Scratch Register */ /*************************************************************************** *SOFT_RESET - BVN TOP Soft Reset ***************************************************************************/ /* TMISC :: SOFT_RESET :: reserved0 [31:04] */ #define BCHP_TMISC_SOFT_RESET_reserved0_MASK 0xfffffff0 #define BCHP_TMISC_SOFT_RESET_reserved0_SHIFT 4 /* TMISC :: SOFT_RESET :: CSC [03:03] */ #define BCHP_TMISC_SOFT_RESET_CSC_MASK 0x00000008 #define BCHP_TMISC_SOFT_RESET_CSC_SHIFT 3 /* TMISC :: SOFT_RESET :: SCL [02:02] */ #define BCHP_TMISC_SOFT_RESET_SCL_MASK 0x00000004 #define BCHP_TMISC_SOFT_RESET_SCL_SHIFT 2 /* TMISC :: SOFT_RESET :: DNR [01:01] */ #define BCHP_TMISC_SOFT_RESET_DNR_MASK 0x00000002 #define BCHP_TMISC_SOFT_RESET_DNR_SHIFT 1 /* TMISC :: SOFT_RESET :: MFD [00:00] */ #define BCHP_TMISC_SOFT_RESET_MFD_MASK 0x00000001 #define BCHP_TMISC_SOFT_RESET_MFD_SHIFT 0 /*************************************************************************** *TEST_PORT_DATA - BVN TOP Test Port Status ***************************************************************************/ /* TMISC :: TEST_PORT_DATA :: TEST_PORT_DATA [31:00] */ #define BCHP_TMISC_TEST_PORT_DATA_TEST_PORT_DATA_MASK 0xffffffff #define BCHP_TMISC_TEST_PORT_DATA_TEST_PORT_DATA_SHIFT 0 /*************************************************************************** *TEST_PORT_CTRL - BVN TOP Test Port Control ***************************************************************************/ /* TMISC :: TEST_PORT_CTRL :: reserved0 [31:24] */ #define BCHP_TMISC_TEST_PORT_CTRL_reserved0_MASK 0xff000000 #define BCHP_TMISC_TEST_PORT_CTRL_reserved0_SHIFT 24 /* TMISC :: TEST_PORT_CTRL :: TM_CTRL [23:00] */ #define BCHP_TMISC_TEST_PORT_CTRL_TM_CTRL_MASK 0x00ffffff #define BCHP_TMISC_TEST_PORT_CTRL_TM_CTRL_SHIFT 0 /*************************************************************************** *BVNT_MBIST_TM_CTRL_MFD - BVN TOP MBIST TM Control for MFD ***************************************************************************/ /* TMISC :: BVNT_MBIST_TM_CTRL_MFD :: reserved0 [31:24] */ #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_MFD_reserved0_MASK 0xff000000 #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_MFD_reserved0_SHIFT 24 /* TMISC :: BVNT_MBIST_TM_CTRL_MFD :: TM_CTRL [23:00] */ #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_MFD_TM_CTRL_MASK 0x00ffffff #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_MFD_TM_CTRL_SHIFT 0 /*************************************************************************** *BVNT_MBIST_TM_CTRL_DNR - BVN TOP MBIST TM Control for DNR ***************************************************************************/ /* TMISC :: BVNT_MBIST_TM_CTRL_DNR :: reserved0 [31:24] */ #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_DNR_reserved0_MASK 0xff000000 #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_DNR_reserved0_SHIFT 24 /* TMISC :: BVNT_MBIST_TM_CTRL_DNR :: TM_CTRL [23:00] */ #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_DNR_TM_CTRL_MASK 0x00ffffff #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_DNR_TM_CTRL_SHIFT 0 /*************************************************************************** *BVNT_MBIST_TM_CTRL_SCL - BVN TOP MBIST TM Control for SCL ***************************************************************************/ /* TMISC :: BVNT_MBIST_TM_CTRL_SCL :: reserved0 [31:24] */ #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_SCL_reserved0_MASK 0xff000000 #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_SCL_reserved0_SHIFT 24 /* TMISC :: BVNT_MBIST_TM_CTRL_SCL :: TM_CTRL [23:00] */ #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_SCL_TM_CTRL_MASK 0x00ffffff #define BCHP_TMISC_BVNT_MBIST_TM_CTRL_SCL_TM_CTRL_SHIFT 0 /*************************************************************************** *SCRATCH_0 - Scratch Register ***************************************************************************/ /* TMISC :: SCRATCH_0 :: VALUE [31:00] */ #define BCHP_TMISC_SCRATCH_0_VALUE_MASK 0xffffffff #define BCHP_TMISC_SCRATCH_0_VALUE_SHIFT 0 #endif /* #ifndef BCHP_TMISC_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016000000000000011562 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_client_regs.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_cl0000644000175000017500000035140411610313111031015 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_client_regs.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:16p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:12 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_client_regs.h $ * * Hydra_Software_Devel/1 7/17/09 8:16p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_CLIENT_REGS_H__ #define BCHP_PRI_CLIENT_REGS_H__ /*************************************************************************** *PRI_CLIENT_REGS - PRIMARY_ARB_CLIENTS client configuration registers ***************************************************************************/ #define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT 0x0040c000 /* Arbiter Client DEBLOCK Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL 0x0040c004 /* Arbiter Client DEBLOCK Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT 0x0040c008 /* Arbiter Client CABAC Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL 0x0040c00c /* Arbiter Client CABAC Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT 0x0040c010 /* Arbiter Client ILOOP Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL 0x0040c014 /* Arbiter Client ILOOP Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT 0x0040c018 /* Arbiter Client OLOOP Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL 0x0040c01c /* Arbiter Client OLOOP Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT 0x0040c020 /* Arbiter Client SYMB_INT Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL 0x0040c024 /* Arbiter Client SYMB_INT Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT 0x0040c028 /* Arbiter Client MOCOMP Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL 0x0040c02c /* Arbiter Client MOCOMP Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT 0x0040c030 /* Arbiter Client XPT1 Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL 0x0040c034 /* Arbiter Client XPT1 Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT 0x0040c038 /* Arbiter Client XPT2 Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL 0x0040c03c /* Arbiter Client XPT2 Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT 0x0040c040 /* Arbiter Client XPT3 Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL 0x0040c044 /* Arbiter Client XPT3 Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT 0x0040c048 /* Arbiter Client ARM Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL 0x0040c04c /* Arbiter Client ARM Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT 0x0040c050 /* Arbiter Client M2M Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL 0x0040c054 /* Arbiter Client M2M Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT 0x0040c058 /* Arbiter Client SHARF Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL 0x0040c05c /* Arbiter Client SHARF Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT 0x0040c060 /* Arbiter Client MFD0 Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL 0x0040c064 /* Arbiter Client MFD0 Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT 0x0040c068 /* Arbiter Client RXDMA Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL 0x0040c06c /* Arbiter Client RXDMA Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT 0x0040c070 /* Arbiter Client TXDMA Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL 0x0040c074 /* Arbiter Client TXDMA Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT 0x0040c078 /* Arbiter Client META Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL 0x0040c07c /* Arbiter Client META Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT 0x0040c080 /* Arbiter Client DIRECT Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL 0x0040c084 /* Arbiter Client DIRECT Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT 0x0040c088 /* Arbiter Client MSA Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL 0x0040c08c /* Arbiter Client MSA Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT 0x0040c090 /* Arbiter Client TRACE Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL 0x0040c094 /* Arbiter Client TRACE Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT 0x0040c098 /* Arbiter Client REFRESH0 Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL 0x0040c09c /* Arbiter Client REFRESH0 Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_20_COUNT 0x0040c0a0 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_20_CONTROL 0x0040c0a4 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_21_COUNT 0x0040c0a8 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_21_CONTROL 0x0040c0ac /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_22_COUNT 0x0040c0b0 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_22_CONTROL 0x0040c0b4 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_23_COUNT 0x0040c0b8 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_23_CONTROL 0x0040c0bc /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_24_COUNT 0x0040c0c0 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_24_CONTROL 0x0040c0c4 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_25_COUNT 0x0040c0c8 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_25_CONTROL 0x0040c0cc /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_26_COUNT 0x0040c0d0 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_26_CONTROL 0x0040c0d4 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_27_COUNT 0x0040c0d8 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_27_CONTROL 0x0040c0dc /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_28_COUNT 0x0040c0e0 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_28_CONTROL 0x0040c0e4 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_29_COUNT 0x0040c0e8 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_29_CONTROL 0x0040c0ec /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_30_COUNT 0x0040c0f0 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_30_CONTROL 0x0040c0f4 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_31_COUNT 0x0040c0f8 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_31_CONTROL 0x0040c0fc /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_32_COUNT 0x0040c100 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_32_CONTROL 0x0040c104 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_33_COUNT 0x0040c108 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_33_CONTROL 0x0040c10c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_34_COUNT 0x0040c110 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_34_CONTROL 0x0040c114 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_35_COUNT 0x0040c118 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_35_CONTROL 0x0040c11c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_36_COUNT 0x0040c120 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_36_CONTROL 0x0040c124 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_37_COUNT 0x0040c128 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_37_CONTROL 0x0040c12c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_38_COUNT 0x0040c130 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_38_CONTROL 0x0040c134 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_39_COUNT 0x0040c138 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_39_CONTROL 0x0040c13c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_40_COUNT 0x0040c140 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_40_CONTROL 0x0040c144 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_41_COUNT 0x0040c148 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_41_CONTROL 0x0040c14c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_42_COUNT 0x0040c150 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_42_CONTROL 0x0040c154 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_43_COUNT 0x0040c158 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_43_CONTROL 0x0040c15c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_44_COUNT 0x0040c160 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_44_CONTROL 0x0040c164 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_45_COUNT 0x0040c168 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_45_CONTROL 0x0040c16c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_46_COUNT 0x0040c170 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_46_CONTROL 0x0040c174 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_47_COUNT 0x0040c178 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_47_CONTROL 0x0040c17c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_48_COUNT 0x0040c180 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_48_CONTROL 0x0040c184 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_49_COUNT 0x0040c188 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_49_CONTROL 0x0040c18c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_50_COUNT 0x0040c190 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_50_CONTROL 0x0040c194 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_51_COUNT 0x0040c198 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_51_CONTROL 0x0040c19c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_52_COUNT 0x0040c1a0 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_52_CONTROL 0x0040c1a4 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_53_COUNT 0x0040c1a8 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_53_CONTROL 0x0040c1ac /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_54_COUNT 0x0040c1b0 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_54_CONTROL 0x0040c1b4 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_55_COUNT 0x0040c1b8 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_55_CONTROL 0x0040c1bc /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_56_COUNT 0x0040c1c0 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_56_CONTROL 0x0040c1c4 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_57_COUNT 0x0040c1c8 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_57_CONTROL 0x0040c1cc /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_58_COUNT 0x0040c1d0 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_58_CONTROL 0x0040c1d4 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_59_COUNT 0x0040c1d8 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_59_CONTROL 0x0040c1dc /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_60_COUNT 0x0040c1e0 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_60_CONTROL 0x0040c1e4 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_61_COUNT 0x0040c1e8 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_61_CONTROL 0x0040c1ec /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_62_COUNT 0x0040c1f0 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_62_CONTROL 0x0040c1f4 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_63_COUNT 0x0040c1f8 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_63_CONTROL 0x0040c1fc /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_64_COUNT 0x0040c200 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_64_CONTROL 0x0040c204 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_65_COUNT 0x0040c208 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_65_CONTROL 0x0040c20c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_66_COUNT 0x0040c210 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_66_CONTROL 0x0040c214 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_67_COUNT 0x0040c218 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_67_CONTROL 0x0040c21c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_68_COUNT 0x0040c220 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_68_CONTROL 0x0040c224 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_69_COUNT 0x0040c228 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_69_CONTROL 0x0040c22c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_70_COUNT 0x0040c230 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_70_CONTROL 0x0040c234 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_71_COUNT 0x0040c238 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_71_CONTROL 0x0040c23c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_72_COUNT 0x0040c240 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_72_CONTROL 0x0040c244 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_73_COUNT 0x0040c248 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_73_CONTROL 0x0040c24c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_74_COUNT 0x0040c250 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_74_CONTROL 0x0040c254 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_75_COUNT 0x0040c258 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_75_CONTROL 0x0040c25c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_76_COUNT 0x0040c260 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_76_CONTROL 0x0040c264 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_77_COUNT 0x0040c268 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_77_CONTROL 0x0040c26c /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_78_COUNT 0x0040c270 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_78_CONTROL 0x0040c274 /* Arbiter Client RESERVED Configuration Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_79_COUNT 0x0040c278 /* Arbiter Client RESERVED Blockout Counter Register */ #define BCHP_PRI_CLIENT_REGS_CLIENT_79_CONTROL 0x0040c27c /* Arbiter Client RESERVED Configuration Register */ /*************************************************************************** *CLIENT_00_COUNT - Arbiter Client DEBLOCK Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_00_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_00_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_00_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_00_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_00_CONTROL - Arbiter Client DEBLOCK Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_00_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_00_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_00_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_00_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_00_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_01_COUNT - Arbiter Client CABAC Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_01_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_01_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_01_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_01_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_01_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_01_CONTROL - Arbiter Client CABAC Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_01_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_01_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_01_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_01_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_01_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_01_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_02_COUNT - Arbiter Client ILOOP Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_02_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_02_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_02_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_02_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_02_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_02_CONTROL - Arbiter Client ILOOP Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_02_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_02_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_02_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_02_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_02_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_02_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_03_COUNT - Arbiter Client OLOOP Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_03_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_03_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_03_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_03_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_03_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_03_CONTROL - Arbiter Client OLOOP Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_03_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_03_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_03_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_03_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_03_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_03_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_04_COUNT - Arbiter Client SYMB_INT Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_04_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_04_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_04_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_04_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_04_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_04_CONTROL - Arbiter Client SYMB_INT Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_04_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_04_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_04_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_04_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_04_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_04_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_05_COUNT - Arbiter Client MOCOMP Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_05_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_05_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_05_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_05_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_05_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_05_CONTROL - Arbiter Client MOCOMP Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_05_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_05_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_05_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_05_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_05_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_05_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_06_COUNT - Arbiter Client XPT1 Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_06_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_06_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_06_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_06_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_06_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_06_CONTROL - Arbiter Client XPT1 Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_06_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_06_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_06_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_06_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_06_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_06_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_07_COUNT - Arbiter Client XPT2 Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_07_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_07_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_07_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_07_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_07_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_07_CONTROL - Arbiter Client XPT2 Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_07_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_07_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_07_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_07_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_07_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_07_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_08_COUNT - Arbiter Client XPT3 Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_08_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_08_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_08_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_08_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_08_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_08_CONTROL - Arbiter Client XPT3 Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_08_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_08_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_08_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_08_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_08_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_08_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_09_COUNT - Arbiter Client ARM Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_09_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_09_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_09_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_09_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_09_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_09_CONTROL - Arbiter Client ARM Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_09_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_09_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_09_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_09_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_09_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_09_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_10_COUNT - Arbiter Client M2M Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_10_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_10_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_10_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_10_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_10_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_10_CONTROL - Arbiter Client M2M Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_10_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_10_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_10_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_10_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_10_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_10_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_11_COUNT - Arbiter Client SHARF Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_11_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_11_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_11_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_11_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_11_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_11_CONTROL - Arbiter Client SHARF Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_11_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_11_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_11_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_11_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_11_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_11_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_12_COUNT - Arbiter Client MFD0 Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_12_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_12_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_12_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_12_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_12_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_12_CONTROL - Arbiter Client MFD0 Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_12_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_12_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_12_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_12_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_12_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_12_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_13_COUNT - Arbiter Client RXDMA Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_13_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_13_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_13_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_13_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_13_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_13_CONTROL - Arbiter Client RXDMA Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_13_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_13_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_13_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_13_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_13_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_13_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_14_COUNT - Arbiter Client TXDMA Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_14_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_14_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_14_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_14_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_14_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_14_CONTROL - Arbiter Client TXDMA Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_14_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_14_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_14_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_14_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_14_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_14_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_15_COUNT - Arbiter Client META Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_15_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_15_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_15_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_15_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_15_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_15_CONTROL - Arbiter Client META Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_15_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_15_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_15_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_15_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_15_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_15_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_16_COUNT - Arbiter Client DIRECT Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_16_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_16_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_16_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_16_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_16_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_16_CONTROL - Arbiter Client DIRECT Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_16_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_16_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_16_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_16_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_16_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_16_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_17_COUNT - Arbiter Client MSA Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_17_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_17_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_17_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_17_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_17_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_17_CONTROL - Arbiter Client MSA Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_17_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_17_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_17_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_17_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_17_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_17_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_18_COUNT - Arbiter Client TRACE Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_18_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_18_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_18_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_18_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_18_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_18_CONTROL - Arbiter Client TRACE Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_18_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_18_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_18_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_18_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_18_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_18_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_19_COUNT - Arbiter Client REFRESH0 Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_19_COUNT :: reserved_for_eco0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_reserved_for_eco0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_reserved_for_eco0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_19_COUNT :: cr [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_cr_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_cr_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_19_COUNT :: reserved_for_eco1 [15:14] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_reserved_for_eco1_MASK 0x0000c000 #define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_reserved_for_eco1_SHIFT 14 /* PRI_CLIENT_REGS :: CLIENT_19_COUNT :: bo [13:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_bo_MASK 0x00003fff #define BCHP_PRI_CLIENT_REGS_CLIENT_19_COUNT_bo_SHIFT 0 /*************************************************************************** *CLIENT_19_CONTROL - Arbiter Client REFRESH0 Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_19_CONTROL :: reserved0 [31:30] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_reserved0_MASK 0xc0000000 #define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_reserved0_SHIFT 30 /* PRI_CLIENT_REGS :: CLIENT_19_CONTROL :: bo_count [29:16] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_bo_count_MASK 0x3fff0000 #define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_bo_count_SHIFT 16 /* PRI_CLIENT_REGS :: CLIENT_19_CONTROL :: reserved1 [15:11] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_reserved1_MASK 0x0000f800 #define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_reserved1_SHIFT 11 /* PRI_CLIENT_REGS :: CLIENT_19_CONTROL :: mode [10:08] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_mode_MASK 0x00000700 #define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_mode_SHIFT 8 /* PRI_CLIENT_REGS :: CLIENT_19_CONTROL :: prio [07:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_prio_MASK 0x000000ff #define BCHP_PRI_CLIENT_REGS_CLIENT_19_CONTROL_prio_SHIFT 0 /*************************************************************************** *CLIENT_20_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_20_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_20_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_20_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_20_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_20_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_20_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_20_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_21_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_21_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_21_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_21_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_21_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_21_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_21_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_21_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_22_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_22_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_22_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_22_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_22_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_22_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_22_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_22_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_23_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_23_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_23_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_23_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_23_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_23_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_23_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_23_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_24_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_24_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_24_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_24_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_24_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_24_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_24_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_24_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_25_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_25_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_25_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_25_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_25_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_25_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_25_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_25_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_26_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_26_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_26_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_26_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_26_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_26_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_26_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_26_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_27_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_27_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_27_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_27_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_27_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_27_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_27_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_27_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_28_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_28_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_28_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_28_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_28_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_28_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_28_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_28_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_29_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_29_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_29_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_29_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_29_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_29_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_29_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_29_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_30_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_30_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_30_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_30_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_30_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_30_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_30_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_30_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_31_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_31_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_31_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_31_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_31_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_31_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_31_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_31_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_32_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_32_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_32_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_32_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_32_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_32_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_32_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_32_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_33_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_33_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_33_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_33_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_33_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_33_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_33_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_33_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_34_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_34_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_34_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_34_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_34_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_34_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_34_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_34_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_35_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_35_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_35_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_35_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_35_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_35_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_35_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_35_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_36_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_36_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_36_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_36_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_36_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_36_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_36_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_36_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_37_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_37_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_37_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_37_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_37_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_37_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_37_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_37_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_38_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_38_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_38_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_38_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_38_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_38_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_38_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_38_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_39_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_39_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_39_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_39_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_39_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_39_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_39_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_39_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_40_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_40_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_40_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_40_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_40_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_40_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_40_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_40_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_41_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_41_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_41_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_41_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_41_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_41_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_41_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_41_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_42_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_42_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_42_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_42_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_42_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_42_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_42_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_42_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_43_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_43_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_43_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_43_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_43_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_43_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_43_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_43_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_44_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_44_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_44_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_44_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_44_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_44_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_44_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_44_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_45_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_45_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_45_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_45_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_45_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_45_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_45_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_45_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_46_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_46_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_46_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_46_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_46_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_46_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_46_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_46_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_47_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_47_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_47_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_47_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_47_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_47_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_47_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_47_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_48_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_48_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_48_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_48_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_48_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_48_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_48_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_48_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_49_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_49_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_49_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_49_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_49_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_49_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_49_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_49_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_50_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_50_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_50_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_50_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_50_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_50_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_50_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_50_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_51_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_51_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_51_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_51_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_51_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_51_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_51_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_51_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_52_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_52_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_52_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_52_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_52_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_52_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_52_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_52_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_53_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_53_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_53_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_53_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_53_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_53_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_53_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_53_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_54_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_54_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_54_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_54_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_54_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_54_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_54_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_54_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_55_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_55_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_55_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_55_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_55_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_55_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_55_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_55_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_56_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_56_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_56_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_56_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_56_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_56_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_56_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_56_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_57_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_57_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_57_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_57_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_57_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_57_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_57_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_57_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_58_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_58_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_58_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_58_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_58_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_58_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_58_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_58_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_59_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_59_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_59_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_59_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_59_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_59_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_59_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_59_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_60_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_60_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_60_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_60_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_60_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_60_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_60_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_60_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_61_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_61_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_61_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_61_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_61_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_61_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_61_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_61_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_62_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_62_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_62_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_62_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_62_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_62_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_62_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_62_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_63_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_63_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_63_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_63_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_63_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_63_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_63_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_63_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_64_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_64_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_64_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_64_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_64_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_64_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_64_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_64_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_65_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_65_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_65_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_65_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_65_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_65_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_65_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_65_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_66_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_66_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_66_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_66_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_66_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_66_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_66_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_66_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_67_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_67_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_67_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_67_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_67_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_67_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_67_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_67_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_68_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_68_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_68_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_68_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_68_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_68_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_68_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_68_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_69_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_69_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_69_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_69_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_69_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_69_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_69_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_69_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_70_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_70_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_70_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_70_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_70_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_70_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_70_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_70_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_71_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_71_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_71_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_71_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_71_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_71_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_71_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_71_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_72_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_72_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_72_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_72_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_72_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_72_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_72_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_72_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_73_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_73_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_73_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_73_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_73_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_73_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_73_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_73_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_74_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_74_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_74_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_74_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_74_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_74_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_74_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_74_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_75_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_75_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_75_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_75_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_75_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_75_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_75_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_75_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_76_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_76_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_76_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_76_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_76_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_76_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_76_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_76_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_77_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_77_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_77_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_77_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_77_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_77_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_77_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_77_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_78_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_78_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_78_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_78_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_78_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_78_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_78_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_78_CONTROL_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_79_COUNT - Arbiter Client RESERVED Blockout Counter Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_79_COUNT :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_79_COUNT_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_79_COUNT_RESERVED_SHIFT 0 /*************************************************************************** *CLIENT_79_CONTROL - Arbiter Client RESERVED Configuration Register ***************************************************************************/ /* PRI_CLIENT_REGS :: CLIENT_79_CONTROL :: RESERVED [31:00] */ #define BCHP_PRI_CLIENT_REGS_CLIENT_79_CONTROL_RESERVED_MASK 0xffffffff #define BCHP_PRI_CLIENT_REGS_CLIENT_79_CONTROL_RESERVED_SHIFT 0 #endif /* #ifndef BCHP_PRI_CLIENT_REGS_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000014700000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_scl_hd.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_scl_hd0000644000175000017500000117727511610313111031016 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_scl_hd.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:18p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:12 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_scl_hd.h $ * * Hydra_Software_Devel/1 7/17/09 8:18p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_SCL_HD_H__ #define BCHP_SCL_HD_H__ /*************************************************************************** *SCL_HD - Video Scaler Registers ***************************************************************************/ #define BCHP_SCL_HD_REVISION_ID 0x00540800 /* Scaler Revision register */ #define BCHP_SCL_HD_TOP_CONTROL 0x00540804 /* Scaler Top Level Control register */ #define BCHP_SCL_HD_VERT_CONTROL 0x00540808 /* Video Vertical Scaler Control register */ #define BCHP_SCL_HD_HORIZ_CONTROL 0x0054080c /* Video Horizontal Scaler Control register */ #define BCHP_SCL_HD_BVB_IN_SIZE 0x00540810 /* BVB Input Picture Size Information */ #define BCHP_SCL_HD_PIC_OFFSET 0x00540814 /* BVB Input Picture OFFSET Information */ #define BCHP_SCL_HD_SRC_PIC_SIZE 0x00540818 /* Scaler Source Picture Size Information */ #define BCHP_SCL_HD_DEST_PIC_SIZE 0x0054081c /* Scaler Destination Picture Size Information */ #define BCHP_SCL_HD_SRC_PIC_VERT_PAN_SCAN 0x00540820 /* Scaler Source Picture Vertical Pan/Scan Information */ #define BCHP_SCL_HD_VERT_FIR_SRC_PIC_OFFSET 0x00540824 /* Vertical 8 Taps Poly-Phase Filter Source Picture Offset */ #define BCHP_SCL_HD_VERT_FIR_SRC_PIC_STEP 0x00540828 /* Vertical 8 Taps Poly-Phase Filter Source Picture Stepping Size */ #define BCHP_SCL_HD_SRC_PIC_HORIZ_PAN_SCAN 0x0054082c /* Scaler Source Picture Horizontal Pan/Scan Information */ #define BCHP_SCL_HD_HORIZ_FIR_LUMA_SRC_PIC_OFFSET 0x00540830 /* Horizontal 16 Taps Poly-Phase Filter Source Picture Luma Offset */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_SRC_PIC_OFFSET 0x00540834 /* Horizontal 16 Taps Poly-Phase Filter Source Picture Chroma Offset */ #define BCHP_SCL_HD_HORIZ_FIR_INIT_PHASE_ACC 0x00540838 /* Horizontal 16 Taps Poly-Phase Filter Initial Phase Accumulate Value */ #define BCHP_SCL_HD_HORIZ_FIR_INIT_STEP 0x0054083c /* Horizontal Poly-Phase Filter Initial Stepping Size for Region 0 */ #define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA 0x00540840 /* Horizontal Poly-Phase Filter Picture Delta Increment for Region 0 Stepping Size */ #define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA 0x00540844 /* Horizontal Poly-Phase Filter Picture Delta Increment for Region 2 Stepping Size */ #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_0_END 0x00540848 /* Horizontal Poly-Phase Filter Destination Region 0 Ending Position */ #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_1_END 0x0054084c /* Horizontal Poly-Phase Filter Destination Region 1 Ending Position */ #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_2_END 0x00540850 /* Horizontal Poly-Phase Filter Destination Region 2 Ending Position */ #define BCHP_SCL_HD_ENABLE 0x00540854 /* Video Scaler Enable */ #define BCHP_SCL_HD_TEST_PORT_CONTROL 0x00540880 /* Testportl control register */ #define BCHP_SCL_HD_TEST_PORT_DATA 0x00540884 /* Testport data register */ #define BCHP_SCL_HD_SCRATCH_0 0x00540888 /* Scaler Scratch register 0 */ #define BCHP_SCL_HD_SCRATCH_1 0x0054088c /* Scaler Scratch register 1 */ #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR 0x005408a0 /* Scaler Broadcom Video Bus Input Status Clear */ #define BCHP_SCL_HD_BVB_IN_STATUS 0x005408a4 /* Scaler Broadcom Video Bus Input Status */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01 0x00540900 /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03 0x00540904 /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05 0x00540908 /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07 0x0054090c /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01 0x00540910 /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03 0x00540914 /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05 0x00540918 /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07 0x0054091c /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01 0x00540920 /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03 0x00540924 /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05 0x00540928 /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07 0x0054092c /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01 0x00540930 /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03 0x00540934 /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05 0x00540938 /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07 0x0054093c /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01 0x00540940 /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03 0x00540944 /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05 0x00540948 /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07 0x0054094c /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01 0x00540950 /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03 0x00540954 /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05 0x00540958 /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07 0x0054095c /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01 0x00540960 /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03 0x00540964 /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05 0x00540968 /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07 0x0054096c /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01 0x00540970 /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03 0x00540974 /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05 0x00540978 /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07 0x0054097c /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01 0x00540980 /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03 0x00540984 /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05 0x00540988 /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07 0x0054098c /* Vertical Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01 0x00540990 /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03 0x00540994 /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05 0x00540998 /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07 0x0054099c /* Vertical Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01 0x005409a0 /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03 0x005409a4 /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05 0x005409a8 /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07 0x005409ac /* Vertical Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01 0x005409b0 /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03 0x005409b4 /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05 0x005409b8 /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07 0x005409bc /* Vertical Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01 0x005409c0 /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03 0x005409c4 /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05 0x005409c8 /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07 0x005409cc /* Vertical Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01 0x005409d0 /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03 0x005409d4 /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05 0x005409d8 /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07 0x005409dc /* Vertical Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01 0x005409e0 /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03 0x005409e4 /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05 0x005409e8 /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07 0x005409ec /* Vertical Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01 0x005409f0 /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03 0x005409f4 /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05 0x005409f8 /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07 0x005409fc /* Vertical Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01 0x00540a00 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03 0x00540a04 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05 0x00540a08 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07 0x00540a0c /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09 0x00540a10 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 8 and 9 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11 0x00540a14 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 10 and 11 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13 0x00540a18 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 12 and 13 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15 0x00540a1c /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 14 and 15 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01 0x00540a20 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03 0x00540a24 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05 0x00540a28 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07 0x00540a2c /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09 0x00540a30 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 8 and 9 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11 0x00540a34 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 10 and 11 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13 0x00540a38 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 12 and 13 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15 0x00540a3c /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 14 and 15 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01 0x00540a40 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03 0x00540a44 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05 0x00540a48 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07 0x00540a4c /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09 0x00540a50 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 8 and 9 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11 0x00540a54 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 10 and 11 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13 0x00540a58 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 12 and 13 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15 0x00540a5c /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 14 and 15 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01 0x00540a60 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03 0x00540a64 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05 0x00540a68 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07 0x00540a6c /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09 0x00540a70 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 8 and 9 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11 0x00540a74 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 10 and 11 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13 0x00540a78 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 12 and 13 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15 0x00540a7c /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 14 and 15 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01 0x00540a80 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03 0x00540a84 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05 0x00540a88 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07 0x00540a8c /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09 0x00540a90 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 8 and 9 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11 0x00540a94 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 10 and 11 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13 0x00540a98 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 12 and 13 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15 0x00540a9c /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 14 and 15 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01 0x00540aa0 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03 0x00540aa4 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05 0x00540aa8 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07 0x00540aac /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09 0x00540ab0 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 8 and 9 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11 0x00540ab4 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 10 and 11 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13 0x00540ab8 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 12 and 13 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15 0x00540abc /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 14 and 15 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01 0x00540ac0 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03 0x00540ac4 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05 0x00540ac8 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07 0x00540acc /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09 0x00540ad0 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 8 and 9 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11 0x00540ad4 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 10 and 11 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13 0x00540ad8 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 12 and 13 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15 0x00540adc /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 14 and 15 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01 0x00540ae0 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03 0x00540ae4 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05 0x00540ae8 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07 0x00540aec /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09 0x00540af0 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 8 and 9 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11 0x00540af4 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 10 and 11 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13 0x00540af8 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 12 and 13 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15 0x00540afc /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 14 and 15 Luma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01 0x00540b00 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03 0x00540b04 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05 0x00540b08 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07 0x00540b0c /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09 0x00540b10 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 8 and 9 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11 0x00540b14 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 10 and 11 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13 0x00540b18 /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 12 and 13 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15 0x00540b1c /* Horizontal Scaler Poly-Phase Filter Phase 0 Tap 14 and 15 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01 0x00540b20 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03 0x00540b24 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05 0x00540b28 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07 0x00540b2c /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09 0x00540b30 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 8 and 9 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11 0x00540b34 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 10 and 11 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13 0x00540b38 /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 12 and 13 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15 0x00540b3c /* Horizontal Scaler Poly-Phase Filter Phase 1 Tap 14 and 15 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01 0x00540b40 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03 0x00540b44 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05 0x00540b48 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07 0x00540b4c /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09 0x00540b50 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 8 and 9 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11 0x00540b54 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 10 and 11 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13 0x00540b58 /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 12 and 13 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15 0x00540b5c /* Horizontal Scaler Poly-Phase Filter Phase 2 Tap 14 and 15 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01 0x00540b60 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03 0x00540b64 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05 0x00540b68 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07 0x00540b6c /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09 0x00540b70 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 8 and 9 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11 0x00540b74 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 10 and 11 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13 0x00540b78 /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 12 and 13 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15 0x00540b7c /* Horizontal Scaler Poly-Phase Filter Phase 3 Tap 14 and 15 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01 0x00540b80 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03 0x00540b84 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05 0x00540b88 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07 0x00540b8c /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09 0x00540b90 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 8 and 9 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11 0x00540b94 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 10 and 11 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13 0x00540b98 /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 12 and 13 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15 0x00540b9c /* Horizontal Scaler Poly-Phase Filter Phase 4 Tap 14 and 15 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01 0x00540ba0 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03 0x00540ba4 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05 0x00540ba8 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07 0x00540bac /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09 0x00540bb0 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 8 and 9 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11 0x00540bb4 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 10 and 11 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13 0x00540bb8 /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 12 and 13 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15 0x00540bbc /* Horizontal Scaler Poly-Phase Filter Phase 5 Tap 14 and 15 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01 0x00540bc0 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03 0x00540bc4 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05 0x00540bc8 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07 0x00540bcc /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09 0x00540bd0 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 8 and 9 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11 0x00540bd4 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 10 and 11 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13 0x00540bd8 /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 12 and 13 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15 0x00540bdc /* Horizontal Scaler Poly-Phase Filter Phase 6 Tap 14 and 15 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01 0x00540be0 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03 0x00540be4 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05 0x00540be8 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07 0x00540bec /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09 0x00540bf0 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 8 and 9 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11 0x00540bf4 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 10 and 11 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13 0x00540bf8 /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 12 and 13 Chroma Coefficients */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15 0x00540bfc /* Horizontal Scaler Poly-Phase Filter Phase 7 Tap 14 and 15 Chroma Coefficients */ /*************************************************************************** *REVISION_ID - Scaler Revision register ***************************************************************************/ /* SCL_HD :: REVISION_ID :: reserved0 [31:16] */ #define BCHP_SCL_HD_REVISION_ID_reserved0_MASK 0xffff0000 #define BCHP_SCL_HD_REVISION_ID_reserved0_SHIFT 16 /* SCL_HD :: REVISION_ID :: MAJOR [15:08] */ #define BCHP_SCL_HD_REVISION_ID_MAJOR_MASK 0x0000ff00 #define BCHP_SCL_HD_REVISION_ID_MAJOR_SHIFT 8 /* SCL_HD :: REVISION_ID :: MINOR [07:00] */ #define BCHP_SCL_HD_REVISION_ID_MINOR_MASK 0x000000ff #define BCHP_SCL_HD_REVISION_ID_MINOR_SHIFT 0 /*************************************************************************** *TOP_CONTROL - Scaler Top Level Control register ***************************************************************************/ /* SCL_HD :: TOP_CONTROL :: reserved0 [31:04] */ #define BCHP_SCL_HD_TOP_CONTROL_reserved0_MASK 0xfffffff0 #define BCHP_SCL_HD_TOP_CONTROL_reserved0_SHIFT 4 /* SCL_HD :: TOP_CONTROL :: ENABLE_CTRL [03:03] */ #define BCHP_SCL_HD_TOP_CONTROL_ENABLE_CTRL_MASK 0x00000008 #define BCHP_SCL_HD_TOP_CONTROL_ENABLE_CTRL_SHIFT 3 #define BCHP_SCL_HD_TOP_CONTROL_ENABLE_CTRL_ENABLE_BY_PICTURE 1 #define BCHP_SCL_HD_TOP_CONTROL_ENABLE_CTRL_ALWAYS_ENABLE 0 /* SCL_HD :: TOP_CONTROL :: UPDATE_SEL [02:02] */ #define BCHP_SCL_HD_TOP_CONTROL_UPDATE_SEL_MASK 0x00000004 #define BCHP_SCL_HD_TOP_CONTROL_UPDATE_SEL_SHIFT 2 #define BCHP_SCL_HD_TOP_CONTROL_UPDATE_SEL_UPDATE_BY_PICTURE 1 #define BCHP_SCL_HD_TOP_CONTROL_UPDATE_SEL_ALWAYS_UPDATE 0 /* SCL_HD :: TOP_CONTROL :: FILTER_ORDER [01:01] */ #define BCHP_SCL_HD_TOP_CONTROL_FILTER_ORDER_MASK 0x00000002 #define BCHP_SCL_HD_TOP_CONTROL_FILTER_ORDER_SHIFT 1 #define BCHP_SCL_HD_TOP_CONTROL_FILTER_ORDER_VERT_FIRST 1 #define BCHP_SCL_HD_TOP_CONTROL_FILTER_ORDER_HORIZ_FIRST 0 /* SCL_HD :: TOP_CONTROL :: reserved1 [00:00] */ #define BCHP_SCL_HD_TOP_CONTROL_reserved1_MASK 0x00000001 #define BCHP_SCL_HD_TOP_CONTROL_reserved1_SHIFT 0 /*************************************************************************** *VERT_CONTROL - Video Vertical Scaler Control register ***************************************************************************/ /* SCL_HD :: VERT_CONTROL :: reserved0 [31:09] */ #define BCHP_SCL_HD_VERT_CONTROL_reserved0_MASK 0xfffffe00 #define BCHP_SCL_HD_VERT_CONTROL_reserved0_SHIFT 9 /* SCL_HD :: VERT_CONTROL :: BAVG_BLK_SIZE [08:04] */ #define BCHP_SCL_HD_VERT_CONTROL_BAVG_BLK_SIZE_MASK 0x000001f0 #define BCHP_SCL_HD_VERT_CONTROL_BAVG_BLK_SIZE_SHIFT 4 /* SCL_HD :: VERT_CONTROL :: reserved1 [03:03] */ #define BCHP_SCL_HD_VERT_CONTROL_reserved1_MASK 0x00000008 #define BCHP_SCL_HD_VERT_CONTROL_reserved1_SHIFT 3 /* SCL_HD :: VERT_CONTROL :: MODE [02:00] */ #define BCHP_SCL_HD_VERT_CONTROL_MODE_MASK 0x00000007 #define BCHP_SCL_HD_VERT_CONTROL_MODE_SHIFT 0 #define BCHP_SCL_HD_VERT_CONTROL_MODE_BYPASS 0 #define BCHP_SCL_HD_VERT_CONTROL_MODE_TYPE_1 1 #define BCHP_SCL_HD_VERT_CONTROL_MODE_FIR4 2 #define BCHP_SCL_HD_VERT_CONTROL_MODE_TYPE_3 3 #define BCHP_SCL_HD_VERT_CONTROL_MODE_AV4 4 #define BCHP_SCL_HD_VERT_CONTROL_MODE_FIR8 5 #define BCHP_SCL_HD_VERT_CONTROL_MODE_AV8 6 #define BCHP_SCL_HD_VERT_CONTROL_MODE_TYPE_7 7 /*************************************************************************** *HORIZ_CONTROL - Video Horizontal Scaler Control register ***************************************************************************/ /* SCL_HD :: HORIZ_CONTROL :: reserved0 [31:08] */ #define BCHP_SCL_HD_HORIZ_CONTROL_reserved0_MASK 0xffffff00 #define BCHP_SCL_HD_HORIZ_CONTROL_reserved0_SHIFT 8 /* SCL_HD :: HORIZ_CONTROL :: CHROMA_DERINGING [07:07] */ #define BCHP_SCL_HD_HORIZ_CONTROL_CHROMA_DERINGING_MASK 0x00000080 #define BCHP_SCL_HD_HORIZ_CONTROL_CHROMA_DERINGING_SHIFT 7 #define BCHP_SCL_HD_HORIZ_CONTROL_CHROMA_DERINGING_OFF 0 #define BCHP_SCL_HD_HORIZ_CONTROL_CHROMA_DERINGING_ON 1 /* SCL_HD :: HORIZ_CONTROL :: LUMA_DERINGING [06:06] */ #define BCHP_SCL_HD_HORIZ_CONTROL_LUMA_DERINGING_MASK 0x00000040 #define BCHP_SCL_HD_HORIZ_CONTROL_LUMA_DERINGING_SHIFT 6 #define BCHP_SCL_HD_HORIZ_CONTROL_LUMA_DERINGING_OFF 0 #define BCHP_SCL_HD_HORIZ_CONTROL_LUMA_DERINGING_ON 1 /* SCL_HD :: HORIZ_CONTROL :: MASK_HSCL_LONG_LINE [05:05] */ #define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_LONG_LINE_MASK 0x00000020 #define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_LONG_LINE_SHIFT 5 #define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_LONG_LINE_OFF 0 #define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_LONG_LINE_ON 1 /* SCL_HD :: HORIZ_CONTROL :: MASK_HSCL_SHORT_LINE [04:04] */ #define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_SHORT_LINE_MASK 0x00000010 #define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_SHORT_LINE_SHIFT 4 #define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_SHORT_LINE_OFF 0 #define BCHP_SCL_HD_HORIZ_CONTROL_MASK_HSCL_SHORT_LINE_ON 1 /* SCL_HD :: HORIZ_CONTROL :: STALL_DRAIN_ENABLE [03:03] */ #define BCHP_SCL_HD_HORIZ_CONTROL_STALL_DRAIN_ENABLE_MASK 0x00000008 #define BCHP_SCL_HD_HORIZ_CONTROL_STALL_DRAIN_ENABLE_SHIFT 3 #define BCHP_SCL_HD_HORIZ_CONTROL_STALL_DRAIN_ENABLE_OFF 0 #define BCHP_SCL_HD_HORIZ_CONTROL_STALL_DRAIN_ENABLE_ON 1 /* SCL_HD :: HORIZ_CONTROL :: FIR_ENABLE [02:02] */ #define BCHP_SCL_HD_HORIZ_CONTROL_FIR_ENABLE_MASK 0x00000004 #define BCHP_SCL_HD_HORIZ_CONTROL_FIR_ENABLE_SHIFT 2 #define BCHP_SCL_HD_HORIZ_CONTROL_FIR_ENABLE_OFF 0 #define BCHP_SCL_HD_HORIZ_CONTROL_FIR_ENABLE_ON 1 /* SCL_HD :: HORIZ_CONTROL :: HWF1_ENABLE [01:01] */ #define BCHP_SCL_HD_HORIZ_CONTROL_HWF1_ENABLE_MASK 0x00000002 #define BCHP_SCL_HD_HORIZ_CONTROL_HWF1_ENABLE_SHIFT 1 #define BCHP_SCL_HD_HORIZ_CONTROL_HWF1_ENABLE_OFF 0 #define BCHP_SCL_HD_HORIZ_CONTROL_HWF1_ENABLE_ON 1 /* SCL_HD :: HORIZ_CONTROL :: HWF0_ENABLE [00:00] */ #define BCHP_SCL_HD_HORIZ_CONTROL_HWF0_ENABLE_MASK 0x00000001 #define BCHP_SCL_HD_HORIZ_CONTROL_HWF0_ENABLE_SHIFT 0 #define BCHP_SCL_HD_HORIZ_CONTROL_HWF0_ENABLE_OFF 0 #define BCHP_SCL_HD_HORIZ_CONTROL_HWF0_ENABLE_ON 1 /*************************************************************************** *BVB_IN_SIZE - BVB Input Picture Size Information ***************************************************************************/ /* SCL_HD :: BVB_IN_SIZE :: reserved0 [31:27] */ #define BCHP_SCL_HD_BVB_IN_SIZE_reserved0_MASK 0xf8000000 #define BCHP_SCL_HD_BVB_IN_SIZE_reserved0_SHIFT 27 /* SCL_HD :: BVB_IN_SIZE :: HSIZE [26:16] */ #define BCHP_SCL_HD_BVB_IN_SIZE_HSIZE_MASK 0x07ff0000 #define BCHP_SCL_HD_BVB_IN_SIZE_HSIZE_SHIFT 16 /* SCL_HD :: BVB_IN_SIZE :: reserved1 [15:11] */ #define BCHP_SCL_HD_BVB_IN_SIZE_reserved1_MASK 0x0000f800 #define BCHP_SCL_HD_BVB_IN_SIZE_reserved1_SHIFT 11 /* SCL_HD :: BVB_IN_SIZE :: VSIZE [10:00] */ #define BCHP_SCL_HD_BVB_IN_SIZE_VSIZE_MASK 0x000007ff #define BCHP_SCL_HD_BVB_IN_SIZE_VSIZE_SHIFT 0 /*************************************************************************** *PIC_OFFSET - BVB Input Picture OFFSET Information ***************************************************************************/ /* SCL_HD :: PIC_OFFSET :: reserved0 [31:27] */ #define BCHP_SCL_HD_PIC_OFFSET_reserved0_MASK 0xf8000000 #define BCHP_SCL_HD_PIC_OFFSET_reserved0_SHIFT 27 /* SCL_HD :: PIC_OFFSET :: HSIZE [26:16] */ #define BCHP_SCL_HD_PIC_OFFSET_HSIZE_MASK 0x07ff0000 #define BCHP_SCL_HD_PIC_OFFSET_HSIZE_SHIFT 16 /* SCL_HD :: PIC_OFFSET :: reserved1 [15:11] */ #define BCHP_SCL_HD_PIC_OFFSET_reserved1_MASK 0x0000f800 #define BCHP_SCL_HD_PIC_OFFSET_reserved1_SHIFT 11 /* SCL_HD :: PIC_OFFSET :: VSIZE [10:00] */ #define BCHP_SCL_HD_PIC_OFFSET_VSIZE_MASK 0x000007ff #define BCHP_SCL_HD_PIC_OFFSET_VSIZE_SHIFT 0 /*************************************************************************** *SRC_PIC_SIZE - Scaler Source Picture Size Information ***************************************************************************/ /* SCL_HD :: SRC_PIC_SIZE :: reserved0 [31:27] */ #define BCHP_SCL_HD_SRC_PIC_SIZE_reserved0_MASK 0xf8000000 #define BCHP_SCL_HD_SRC_PIC_SIZE_reserved0_SHIFT 27 /* SCL_HD :: SRC_PIC_SIZE :: HSIZE [26:16] */ #define BCHP_SCL_HD_SRC_PIC_SIZE_HSIZE_MASK 0x07ff0000 #define BCHP_SCL_HD_SRC_PIC_SIZE_HSIZE_SHIFT 16 /* SCL_HD :: SRC_PIC_SIZE :: reserved1 [15:11] */ #define BCHP_SCL_HD_SRC_PIC_SIZE_reserved1_MASK 0x0000f800 #define BCHP_SCL_HD_SRC_PIC_SIZE_reserved1_SHIFT 11 /* SCL_HD :: SRC_PIC_SIZE :: VSIZE [10:00] */ #define BCHP_SCL_HD_SRC_PIC_SIZE_VSIZE_MASK 0x000007ff #define BCHP_SCL_HD_SRC_PIC_SIZE_VSIZE_SHIFT 0 /*************************************************************************** *DEST_PIC_SIZE - Scaler Destination Picture Size Information ***************************************************************************/ /* SCL_HD :: DEST_PIC_SIZE :: reserved0 [31:27] */ #define BCHP_SCL_HD_DEST_PIC_SIZE_reserved0_MASK 0xf8000000 #define BCHP_SCL_HD_DEST_PIC_SIZE_reserved0_SHIFT 27 /* SCL_HD :: DEST_PIC_SIZE :: HSIZE [26:16] */ #define BCHP_SCL_HD_DEST_PIC_SIZE_HSIZE_MASK 0x07ff0000 #define BCHP_SCL_HD_DEST_PIC_SIZE_HSIZE_SHIFT 16 /* SCL_HD :: DEST_PIC_SIZE :: reserved1 [15:11] */ #define BCHP_SCL_HD_DEST_PIC_SIZE_reserved1_MASK 0x0000f800 #define BCHP_SCL_HD_DEST_PIC_SIZE_reserved1_SHIFT 11 /* SCL_HD :: DEST_PIC_SIZE :: VSIZE [10:00] */ #define BCHP_SCL_HD_DEST_PIC_SIZE_VSIZE_MASK 0x000007ff #define BCHP_SCL_HD_DEST_PIC_SIZE_VSIZE_SHIFT 0 /*************************************************************************** *SRC_PIC_VERT_PAN_SCAN - Scaler Source Picture Vertical Pan/Scan Information ***************************************************************************/ /* SCL_HD :: SRC_PIC_VERT_PAN_SCAN :: reserved0 [31:22] */ #define BCHP_SCL_HD_SRC_PIC_VERT_PAN_SCAN_reserved0_MASK 0xffc00000 #define BCHP_SCL_HD_SRC_PIC_VERT_PAN_SCAN_reserved0_SHIFT 22 /* SCL_HD :: SRC_PIC_VERT_PAN_SCAN :: OFFSET [21:16] */ #define BCHP_SCL_HD_SRC_PIC_VERT_PAN_SCAN_OFFSET_MASK 0x003f0000 #define BCHP_SCL_HD_SRC_PIC_VERT_PAN_SCAN_OFFSET_SHIFT 16 /* SCL_HD :: SRC_PIC_VERT_PAN_SCAN :: reserved1 [15:00] */ #define BCHP_SCL_HD_SRC_PIC_VERT_PAN_SCAN_reserved1_MASK 0x0000ffff #define BCHP_SCL_HD_SRC_PIC_VERT_PAN_SCAN_reserved1_SHIFT 0 /*************************************************************************** *VERT_FIR_SRC_PIC_OFFSET - Vertical 8 Taps Poly-Phase Filter Source Picture Offset ***************************************************************************/ /* SCL_HD :: VERT_FIR_SRC_PIC_OFFSET :: VALUE [31:03] */ #define BCHP_SCL_HD_VERT_FIR_SRC_PIC_OFFSET_VALUE_MASK 0xfffffff8 #define BCHP_SCL_HD_VERT_FIR_SRC_PIC_OFFSET_VALUE_SHIFT 3 /* SCL_HD :: VERT_FIR_SRC_PIC_OFFSET :: reserved0 [02:00] */ #define BCHP_SCL_HD_VERT_FIR_SRC_PIC_OFFSET_reserved0_MASK 0x00000007 #define BCHP_SCL_HD_VERT_FIR_SRC_PIC_OFFSET_reserved0_SHIFT 0 /*************************************************************************** *VERT_FIR_SRC_PIC_STEP - Vertical 8 Taps Poly-Phase Filter Source Picture Stepping Size ***************************************************************************/ /* SCL_HD :: VERT_FIR_SRC_PIC_STEP :: reserved0 [31:26] */ #define BCHP_SCL_HD_VERT_FIR_SRC_PIC_STEP_reserved0_MASK 0xfc000000 #define BCHP_SCL_HD_VERT_FIR_SRC_PIC_STEP_reserved0_SHIFT 26 /* SCL_HD :: VERT_FIR_SRC_PIC_STEP :: SIZE [25:03] */ #define BCHP_SCL_HD_VERT_FIR_SRC_PIC_STEP_SIZE_MASK 0x03fffff8 #define BCHP_SCL_HD_VERT_FIR_SRC_PIC_STEP_SIZE_SHIFT 3 /* SCL_HD :: VERT_FIR_SRC_PIC_STEP :: reserved1 [02:00] */ #define BCHP_SCL_HD_VERT_FIR_SRC_PIC_STEP_reserved1_MASK 0x00000007 #define BCHP_SCL_HD_VERT_FIR_SRC_PIC_STEP_reserved1_SHIFT 0 /*************************************************************************** *SRC_PIC_HORIZ_PAN_SCAN - Scaler Source Picture Horizontal Pan/Scan Information ***************************************************************************/ /* SCL_HD :: SRC_PIC_HORIZ_PAN_SCAN :: reserved0 [31:21] */ #define BCHP_SCL_HD_SRC_PIC_HORIZ_PAN_SCAN_reserved0_MASK 0xffe00000 #define BCHP_SCL_HD_SRC_PIC_HORIZ_PAN_SCAN_reserved0_SHIFT 21 /* SCL_HD :: SRC_PIC_HORIZ_PAN_SCAN :: OFFSET [20:14] */ #define BCHP_SCL_HD_SRC_PIC_HORIZ_PAN_SCAN_OFFSET_MASK 0x001fc000 #define BCHP_SCL_HD_SRC_PIC_HORIZ_PAN_SCAN_OFFSET_SHIFT 14 /* SCL_HD :: SRC_PIC_HORIZ_PAN_SCAN :: reserved1 [13:00] */ #define BCHP_SCL_HD_SRC_PIC_HORIZ_PAN_SCAN_reserved1_MASK 0x00003fff #define BCHP_SCL_HD_SRC_PIC_HORIZ_PAN_SCAN_reserved1_SHIFT 0 /*************************************************************************** *HORIZ_FIR_LUMA_SRC_PIC_OFFSET - Horizontal 16 Taps Poly-Phase Filter Source Picture Luma Offset ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_LUMA_SRC_PIC_OFFSET :: VALUE [31:14] */ #define BCHP_SCL_HD_HORIZ_FIR_LUMA_SRC_PIC_OFFSET_VALUE_MASK 0xffffc000 #define BCHP_SCL_HD_HORIZ_FIR_LUMA_SRC_PIC_OFFSET_VALUE_SHIFT 14 /* SCL_HD :: HORIZ_FIR_LUMA_SRC_PIC_OFFSET :: reserved0 [13:00] */ #define BCHP_SCL_HD_HORIZ_FIR_LUMA_SRC_PIC_OFFSET_reserved0_MASK 0x00003fff #define BCHP_SCL_HD_HORIZ_FIR_LUMA_SRC_PIC_OFFSET_reserved0_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_SRC_PIC_OFFSET - Horizontal 16 Taps Poly-Phase Filter Source Picture Chroma Offset ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_SRC_PIC_OFFSET :: VALUE [31:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_SRC_PIC_OFFSET_VALUE_MASK 0xffffc000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_SRC_PIC_OFFSET_VALUE_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_SRC_PIC_OFFSET :: reserved0 [13:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_SRC_PIC_OFFSET_reserved0_MASK 0x00003fff #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_SRC_PIC_OFFSET_reserved0_SHIFT 0 /*************************************************************************** *HORIZ_FIR_INIT_PHASE_ACC - Horizontal 16 Taps Poly-Phase Filter Initial Phase Accumulate Value ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_INIT_PHASE_ACC :: SIZE [31:00] */ #define BCHP_SCL_HD_HORIZ_FIR_INIT_PHASE_ACC_SIZE_MASK 0xffffffff #define BCHP_SCL_HD_HORIZ_FIR_INIT_PHASE_ACC_SIZE_SHIFT 0 /*************************************************************************** *HORIZ_FIR_INIT_STEP - Horizontal Poly-Phase Filter Initial Stepping Size for Region 0 ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_INIT_STEP :: reserved0 [31:31] */ #define BCHP_SCL_HD_HORIZ_FIR_INIT_STEP_reserved0_MASK 0x80000000 #define BCHP_SCL_HD_HORIZ_FIR_INIT_STEP_reserved0_SHIFT 31 /* SCL_HD :: HORIZ_FIR_INIT_STEP :: SIZE [30:00] */ #define BCHP_SCL_HD_HORIZ_FIR_INIT_STEP_SIZE_MASK 0x7fffffff #define BCHP_SCL_HD_HORIZ_FIR_INIT_STEP_SIZE_SHIFT 0 /*************************************************************************** *HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA - Horizontal Poly-Phase Filter Picture Delta Increment for Region 0 Stepping Size ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA :: SIZE [29:02] */ #define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA_SIZE_MASK 0x3ffffffc #define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA_SIZE_SHIFT 2 /* SCL_HD :: HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA :: reserved1 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA_reserved1_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_0_STEP_DELTA_reserved1_SHIFT 0 /*************************************************************************** *HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA - Horizontal Poly-Phase Filter Picture Delta Increment for Region 2 Stepping Size ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA :: SIZE [29:02] */ #define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA_SIZE_MASK 0x3ffffffc #define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA_SIZE_SHIFT 2 /* SCL_HD :: HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA :: reserved1 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA_reserved1_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_DEST_PIC_REGION_2_STEP_DELTA_reserved1_SHIFT 0 /*************************************************************************** *HORIZ_DEST_PIC_REGION_0_END - Horizontal Poly-Phase Filter Destination Region 0 Ending Position ***************************************************************************/ /* SCL_HD :: HORIZ_DEST_PIC_REGION_0_END :: reserved0 [31:27] */ #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_0_END_reserved0_MASK 0xf8000000 #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_0_END_reserved0_SHIFT 27 /* SCL_HD :: HORIZ_DEST_PIC_REGION_0_END :: POSITION [26:16] */ #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_0_END_POSITION_MASK 0x07ff0000 #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_0_END_POSITION_SHIFT 16 /* SCL_HD :: HORIZ_DEST_PIC_REGION_0_END :: reserved1 [15:00] */ #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_0_END_reserved1_MASK 0x0000ffff #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_0_END_reserved1_SHIFT 0 /*************************************************************************** *HORIZ_DEST_PIC_REGION_1_END - Horizontal Poly-Phase Filter Destination Region 1 Ending Position ***************************************************************************/ /* SCL_HD :: HORIZ_DEST_PIC_REGION_1_END :: reserved0 [31:27] */ #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_1_END_reserved0_MASK 0xf8000000 #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_1_END_reserved0_SHIFT 27 /* SCL_HD :: HORIZ_DEST_PIC_REGION_1_END :: POSITION [26:16] */ #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_1_END_POSITION_MASK 0x07ff0000 #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_1_END_POSITION_SHIFT 16 /* SCL_HD :: HORIZ_DEST_PIC_REGION_1_END :: reserved1 [15:00] */ #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_1_END_reserved1_MASK 0x0000ffff #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_1_END_reserved1_SHIFT 0 /*************************************************************************** *HORIZ_DEST_PIC_REGION_2_END - Horizontal Poly-Phase Filter Destination Region 2 Ending Position ***************************************************************************/ /* SCL_HD :: HORIZ_DEST_PIC_REGION_2_END :: reserved0 [31:27] */ #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_2_END_reserved0_MASK 0xf8000000 #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_2_END_reserved0_SHIFT 27 /* SCL_HD :: HORIZ_DEST_PIC_REGION_2_END :: POSITION [26:16] */ #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_2_END_POSITION_MASK 0x07ff0000 #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_2_END_POSITION_SHIFT 16 /* SCL_HD :: HORIZ_DEST_PIC_REGION_2_END :: reserved1 [15:00] */ #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_2_END_reserved1_MASK 0x0000ffff #define BCHP_SCL_HD_HORIZ_DEST_PIC_REGION_2_END_reserved1_SHIFT 0 /*************************************************************************** *ENABLE - Video Scaler Enable ***************************************************************************/ /* SCL_HD :: ENABLE :: reserved0 [31:01] */ #define BCHP_SCL_HD_ENABLE_reserved0_MASK 0xfffffffe #define BCHP_SCL_HD_ENABLE_reserved0_SHIFT 1 /* SCL_HD :: ENABLE :: SCALER_ENABLE [00:00] */ #define BCHP_SCL_HD_ENABLE_SCALER_ENABLE_MASK 0x00000001 #define BCHP_SCL_HD_ENABLE_SCALER_ENABLE_SHIFT 0 #define BCHP_SCL_HD_ENABLE_SCALER_ENABLE_OFF 0 #define BCHP_SCL_HD_ENABLE_SCALER_ENABLE_ON 1 /*************************************************************************** *TEST_PORT_CONTROL - Testportl control register ***************************************************************************/ /* SCL_HD :: TEST_PORT_CONTROL :: reserved0 [31:02] */ #define BCHP_SCL_HD_TEST_PORT_CONTROL_reserved0_MASK 0xfffffffc #define BCHP_SCL_HD_TEST_PORT_CONTROL_reserved0_SHIFT 2 /* SCL_HD :: TEST_PORT_CONTROL :: TP_ADDR [01:00] */ #define BCHP_SCL_HD_TEST_PORT_CONTROL_TP_ADDR_MASK 0x00000003 #define BCHP_SCL_HD_TEST_PORT_CONTROL_TP_ADDR_SHIFT 0 #define BCHP_SCL_HD_TEST_PORT_CONTROL_TP_ADDR_SCL_0 0 #define BCHP_SCL_HD_TEST_PORT_CONTROL_TP_ADDR_SCL_1 1 #define BCHP_SCL_HD_TEST_PORT_CONTROL_TP_ADDR_SCL_2 2 #define BCHP_SCL_HD_TEST_PORT_CONTROL_TP_ADDR_SCL_3 3 /*************************************************************************** *TEST_PORT_DATA - Testport data register ***************************************************************************/ /* union - case SCL_0 [31:00] */ /* SCL_HD :: TEST_PORT_DATA :: SCL_0 :: PPF_DBG [31:10] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_0_PPF_DBG_MASK 0xfffffc00 #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_0_PPF_DBG_SHIFT 10 /* SCL_HD :: TEST_PORT_DATA :: SCL_0 :: HWF_DBG [09:00] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_0_HWF_DBG_MASK 0x000003ff #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_0_HWF_DBG_SHIFT 0 /* union - case SCL_1 [31:00] */ /* SCL_HD :: TEST_PORT_DATA :: SCL_1 :: RE_ORDER_LINE_ADDR [31:20] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_1_RE_ORDER_LINE_ADDR_MASK 0xfff00000 #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_1_RE_ORDER_LINE_ADDR_SHIFT 20 /* SCL_HD :: TEST_PORT_DATA :: SCL_1 :: LB_RD_STATUS [19:12] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_1_LB_RD_STATUS_MASK 0x000ff000 #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_1_LB_RD_STATUS_SHIFT 12 /* SCL_HD :: TEST_PORT_DATA :: SCL_1 :: LB_RD_LINE_ADDR [11:00] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_1_LB_RD_LINE_ADDR_MASK 0x00000fff #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_1_LB_RD_LINE_ADDR_SHIFT 0 /* union - case SCL_2 [31:00] */ /* SCL_HD :: TEST_PORT_DATA :: SCL_2 :: IB_WR_STATUS_1 [31:27] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_WR_STATUS_1_MASK 0xf8000000 #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_WR_STATUS_1_SHIFT 27 /* SCL_HD :: TEST_PORT_DATA :: SCL_2 :: IB_WR_LINE_ADDR [26:16] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_WR_LINE_ADDR_MASK 0x07ff0000 #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_WR_LINE_ADDR_SHIFT 16 /* SCL_HD :: TEST_PORT_DATA :: SCL_2 :: IB_WR_STATUS_0 [15:12] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_WR_STATUS_0_MASK 0x0000f000 #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_WR_STATUS_0_SHIFT 12 /* SCL_HD :: TEST_PORT_DATA :: SCL_2 :: IB_RD_LINE_ADDR [11:00] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_RD_LINE_ADDR_MASK 0x00000fff #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_2_IB_RD_LINE_ADDR_SHIFT 0 /* union - case SCL_3 [31:00] */ /* SCL_HD :: TEST_PORT_DATA :: SCL_3 :: HSCL_BVB_IN_STATUS [31:26] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_HSCL_BVB_IN_STATUS_MASK 0xfc000000 #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_HSCL_BVB_IN_STATUS_SHIFT 26 /* SCL_HD :: TEST_PORT_DATA :: SCL_3 :: VSCL_BVB_IN_STATUS [25:20] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_VSCL_BVB_IN_STATUS_MASK 0x03f00000 #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_VSCL_BVB_IN_STATUS_SHIFT 20 /* SCL_HD :: TEST_PORT_DATA :: SCL_3 :: TOP_CTRL_STATUS [19:17] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_TOP_CTRL_STATUS_MASK 0x000e0000 #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_TOP_CTRL_STATUS_SHIFT 17 /* SCL_HD :: TEST_PORT_DATA :: SCL_3 :: OB_RD_STATUS [16:15] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_OB_RD_STATUS_MASK 0x00018000 #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_OB_RD_STATUS_SHIFT 15 /* SCL_HD :: TEST_PORT_DATA :: SCL_3 :: TIME_CTRL_STATUS [14:12] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_TIME_CTRL_STATUS_MASK 0x00007000 #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_TIME_CTRL_STATUS_SHIFT 12 /* SCL_HD :: TEST_PORT_DATA :: SCL_3 :: FIR_LINE_ADDR [11:00] */ #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_FIR_LINE_ADDR_MASK 0x00000fff #define BCHP_SCL_HD_TEST_PORT_DATA_SCL_3_FIR_LINE_ADDR_SHIFT 0 /*************************************************************************** *SCRATCH_0 - Scaler Scratch register 0 ***************************************************************************/ /* SCL_HD :: SCRATCH_0 :: VALUE [31:00] */ #define BCHP_SCL_HD_SCRATCH_0_VALUE_MASK 0xffffffff #define BCHP_SCL_HD_SCRATCH_0_VALUE_SHIFT 0 /*************************************************************************** *SCRATCH_1 - Scaler Scratch register 1 ***************************************************************************/ /* SCL_HD :: SCRATCH_1 :: VALUE [31:00] */ #define BCHP_SCL_HD_SCRATCH_1_VALUE_MASK 0xffffffff #define BCHP_SCL_HD_SCRATCH_1_VALUE_SHIFT 0 /*************************************************************************** *BVB_IN_STATUS_CLEAR - Scaler Broadcom Video Bus Input Status Clear ***************************************************************************/ /* SCL_HD :: BVB_IN_STATUS_CLEAR :: reserved0 [31:08] */ #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_reserved0_MASK 0xffffff00 #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_reserved0_SHIFT 8 /* SCL_HD :: BVB_IN_STATUS_CLEAR :: ENABLE_ERROR [07:07] */ #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_ENABLE_ERROR_MASK 0x00000080 #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_ENABLE_ERROR_SHIFT 7 /* SCL_HD :: BVB_IN_STATUS_CLEAR :: HSCL_LONG_LINE [06:06] */ #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_HSCL_LONG_LINE_MASK 0x00000040 #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_HSCL_LONG_LINE_SHIFT 6 /* SCL_HD :: BVB_IN_STATUS_CLEAR :: HSCL_SHORT_LINE [05:05] */ #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_HSCL_SHORT_LINE_MASK 0x00000020 #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_HSCL_SHORT_LINE_SHIFT 5 /* SCL_HD :: BVB_IN_STATUS_CLEAR :: MISSING_SYNC [04:04] */ #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_MISSING_SYNC_MASK 0x00000010 #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_MISSING_SYNC_SHIFT 4 /* SCL_HD :: BVB_IN_STATUS_CLEAR :: LONG_SOURCE [03:03] */ #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_LONG_SOURCE_MASK 0x00000008 #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_LONG_SOURCE_SHIFT 3 /* SCL_HD :: BVB_IN_STATUS_CLEAR :: SHORT_SOURCE [02:02] */ #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_SHORT_SOURCE_MASK 0x00000004 #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_SHORT_SOURCE_SHIFT 2 /* SCL_HD :: BVB_IN_STATUS_CLEAR :: LONG_LINE [01:01] */ #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_LONG_LINE_MASK 0x00000002 #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_LONG_LINE_SHIFT 1 /* SCL_HD :: BVB_IN_STATUS_CLEAR :: SHORT_LINE [00:00] */ #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_SHORT_LINE_MASK 0x00000001 #define BCHP_SCL_HD_BVB_IN_STATUS_CLEAR_SHORT_LINE_SHIFT 0 /*************************************************************************** *BVB_IN_STATUS - Scaler Broadcom Video Bus Input Status ***************************************************************************/ /* SCL_HD :: BVB_IN_STATUS :: reserved0 [31:08] */ #define BCHP_SCL_HD_BVB_IN_STATUS_reserved0_MASK 0xffffff00 #define BCHP_SCL_HD_BVB_IN_STATUS_reserved0_SHIFT 8 /* SCL_HD :: BVB_IN_STATUS :: ENABLE_ERROR [07:07] */ #define BCHP_SCL_HD_BVB_IN_STATUS_ENABLE_ERROR_MASK 0x00000080 #define BCHP_SCL_HD_BVB_IN_STATUS_ENABLE_ERROR_SHIFT 7 /* SCL_HD :: BVB_IN_STATUS :: HSCL_LONG_LINE [06:06] */ #define BCHP_SCL_HD_BVB_IN_STATUS_HSCL_LONG_LINE_MASK 0x00000040 #define BCHP_SCL_HD_BVB_IN_STATUS_HSCL_LONG_LINE_SHIFT 6 /* SCL_HD :: BVB_IN_STATUS :: HSCL_SHORT_LINE [05:05] */ #define BCHP_SCL_HD_BVB_IN_STATUS_HSCL_SHORT_LINE_MASK 0x00000020 #define BCHP_SCL_HD_BVB_IN_STATUS_HSCL_SHORT_LINE_SHIFT 5 /* SCL_HD :: BVB_IN_STATUS :: MISSING_SYNC [04:04] */ #define BCHP_SCL_HD_BVB_IN_STATUS_MISSING_SYNC_MASK 0x00000010 #define BCHP_SCL_HD_BVB_IN_STATUS_MISSING_SYNC_SHIFT 4 /* SCL_HD :: BVB_IN_STATUS :: LONG_SOURCE [03:03] */ #define BCHP_SCL_HD_BVB_IN_STATUS_LONG_SOURCE_MASK 0x00000008 #define BCHP_SCL_HD_BVB_IN_STATUS_LONG_SOURCE_SHIFT 3 /* SCL_HD :: BVB_IN_STATUS :: SHORT_SOURCE [02:02] */ #define BCHP_SCL_HD_BVB_IN_STATUS_SHORT_SOURCE_MASK 0x00000004 #define BCHP_SCL_HD_BVB_IN_STATUS_SHORT_SOURCE_SHIFT 2 /* SCL_HD :: BVB_IN_STATUS :: LONG_LINE [01:01] */ #define BCHP_SCL_HD_BVB_IN_STATUS_LONG_LINE_MASK 0x00000002 #define BCHP_SCL_HD_BVB_IN_STATUS_LONG_LINE_SHIFT 1 /* SCL_HD :: BVB_IN_STATUS :: SHORT_LINE [00:00] */ #define BCHP_SCL_HD_BVB_IN_STATUS_SHORT_LINE_MASK 0x00000001 #define BCHP_SCL_HD_BVB_IN_STATUS_SHORT_LINE_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE0_00_01 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE0_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE0_02_03 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE0_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE0_04_05 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE0_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE0_06_07 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE0_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE0_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE0_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE1_00_01 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE1_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE1_02_03 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE1_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE1_04_05 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE1_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE1_06_07 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE1_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE1_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE1_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE2_00_01 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE2_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE2_02_03 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE2_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE2_04_05 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE2_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE2_06_07 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE2_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE2_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE2_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE3_00_01 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE3_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE3_02_03 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE3_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE3_04_05 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE3_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE3_06_07 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE3_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE3_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE3_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE4_00_01 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE4_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE4_02_03 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE4_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE4_04_05 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE4_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE4_06_07 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE4_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE4_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE4_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE5_00_01 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE5_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE5_02_03 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE5_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE5_04_05 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE5_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE5_06_07 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE5_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE5_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE5_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE6_00_01 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE6_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE6_02_03 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE6_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE6_04_05 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE6_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE6_06_07 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE6_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE6_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE6_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE7_00_01 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE7_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE7_02_03 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE7_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE7_04_05 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE7_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_COEFF_PHASE7_06_07 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_COEFF_PHASE7_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_COEFF_PHASE7_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_COEFF_PHASE7_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE0_00_01 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE0_02_03 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE0_04_05 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE0_06_07 - Vertical Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE0_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE0_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE1_00_01 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE1_02_03 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE1_04_05 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE1_06_07 - Vertical Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE1_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE1_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE2_00_01 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE2_02_03 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE2_04_05 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE2_06_07 - Vertical Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE2_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE2_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE3_00_01 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE3_02_03 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE3_04_05 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE3_06_07 - Vertical Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE3_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE3_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE4_00_01 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE4_02_03 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE4_04_05 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE4_06_07 - Vertical Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE4_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE4_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE5_00_01 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE5_02_03 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE5_04_05 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE5_06_07 - Vertical Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE5_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE5_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE6_00_01 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE6_02_03 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE6_04_05 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE6_06_07 - Vertical Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE6_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE6_06_07_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE7_00_01 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_00_01_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE7_02_03 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_02_03_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE7_04_05 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_04_05_reserved2_SHIFT 0 /*************************************************************************** *VERT_FIR_CHROMA_COEFF_PHASE7_06_07 - Vertical Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_reserved0_SHIFT 30 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_reserved1_SHIFT 14 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: VERT_FIR_CHROMA_COEFF_PHASE7_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_VERT_FIR_CHROMA_COEFF_PHASE7_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE0_00_01 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE0_02_03 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE0_04_05 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE0_06_07 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE0_08_09 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 8 and 9 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE0_10_11 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 10 and 11 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE0_12_13 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 12 and 13 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE0_14_15 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 14 and 15 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE0_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE0_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE1_00_01 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE1_02_03 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE1_04_05 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE1_06_07 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE1_08_09 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 8 and 9 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE1_10_11 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 10 and 11 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE1_12_13 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 12 and 13 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE1_14_15 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 14 and 15 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE1_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE1_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE2_00_01 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE2_02_03 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE2_04_05 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE2_06_07 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE2_08_09 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 8 and 9 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE2_10_11 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 10 and 11 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE2_12_13 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 12 and 13 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE2_14_15 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 14 and 15 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE2_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE2_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE3_00_01 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE3_02_03 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE3_04_05 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE3_06_07 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE3_08_09 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 8 and 9 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE3_10_11 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 10 and 11 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE3_12_13 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 12 and 13 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE3_14_15 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 14 and 15 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE3_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE3_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE4_00_01 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE4_02_03 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE4_04_05 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE4_06_07 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE4_08_09 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 8 and 9 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE4_10_11 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 10 and 11 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE4_12_13 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 12 and 13 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE4_14_15 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 14 and 15 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE4_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE4_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE5_00_01 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE5_02_03 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE5_04_05 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE5_06_07 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE5_08_09 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 8 and 9 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE5_10_11 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 10 and 11 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE5_12_13 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 12 and 13 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE5_14_15 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 14 and 15 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE5_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE5_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE6_00_01 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE6_02_03 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE6_04_05 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE6_06_07 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE6_08_09 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 8 and 9 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE6_10_11 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 10 and 11 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE6_12_13 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 12 and 13 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE6_14_15 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 14 and 15 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE6_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE6_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE7_00_01 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE7_02_03 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE7_04_05 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE7_06_07 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE7_08_09 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 8 and 9 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE7_10_11 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 10 and 11 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE7_12_13 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 12 and 13 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_COEFF_PHASE7_14_15 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 14 and 15 Luma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_COEFF_PHASE7_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_COEFF_PHASE7_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 8 and 9 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 10 and 11 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 12 and 13 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15 - Horizontal Scaler Poly-Phase Filter Phase 0 Tap 14 and 15 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE0_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 8 and 9 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 10 and 11 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 12 and 13 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15 - Horizontal Scaler Poly-Phase Filter Phase 1 Tap 14 and 15 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE1_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 8 and 9 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 10 and 11 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 12 and 13 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15 - Horizontal Scaler Poly-Phase Filter Phase 2 Tap 14 and 15 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE2_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 8 and 9 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 10 and 11 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 12 and 13 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15 - Horizontal Scaler Poly-Phase Filter Phase 3 Tap 14 and 15 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE3_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 8 and 9 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 10 and 11 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 12 and 13 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15 - Horizontal Scaler Poly-Phase Filter Phase 4 Tap 14 and 15 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE4_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 8 and 9 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 10 and 11 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 12 and 13 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15 - Horizontal Scaler Poly-Phase Filter Phase 5 Tap 14 and 15 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE5_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 8 and 9 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 10 and 11 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 12 and 13 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15 - Horizontal Scaler Poly-Phase Filter Phase 6 Tap 14 and 15 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE6_14_15_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 0 and 1 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01 :: COEFF_0 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_0_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_0_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01 :: COEFF_1 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_1_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_COEFF_1_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_00_01_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 2 and 3 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03 :: COEFF_2 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_2_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_2_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03 :: COEFF_3 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_3_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_COEFF_3_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_02_03_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 4 and 5 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05 :: COEFF_4 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_4_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_4_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05 :: COEFF_5 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_5_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_COEFF_5_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_04_05_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 6 and 7 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07 :: COEFF_6 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_6_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_6_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07 :: COEFF_7 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_7_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_COEFF_7_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_06_07_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 8 and 9 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09 :: COEFF_8 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_COEFF_8_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_COEFF_8_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09 :: COEFF_9 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_COEFF_9_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_COEFF_9_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_08_09_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 10 and 11 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11 :: COEFF_10 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_COEFF_10_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_COEFF_10_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11 :: COEFF_11 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_COEFF_11_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_COEFF_11_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_10_11_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 12 and 13 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13 :: COEFF_12 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_COEFF_12_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_COEFF_12_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13 :: COEFF_13 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_COEFF_13_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_COEFF_13_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_12_13_reserved2_SHIFT 0 /*************************************************************************** *HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15 - Horizontal Scaler Poly-Phase Filter Phase 7 Tap 14 and 15 Chroma Coefficients ***************************************************************************/ /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15 :: reserved0 [31:30] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_reserved0_MASK 0xc0000000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_reserved0_SHIFT 30 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15 :: COEFF_14 [29:18] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_COEFF_14_MASK 0x3ffc0000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_COEFF_14_SHIFT 18 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15 :: reserved1 [17:14] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_reserved1_MASK 0x0003c000 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_reserved1_SHIFT 14 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15 :: COEFF_15 [13:02] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_COEFF_15_MASK 0x00003ffc #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_COEFF_15_SHIFT 2 /* SCL_HD :: HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15 :: reserved2 [01:00] */ #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_reserved2_MASK 0x00000003 #define BCHP_SCL_HD_HORIZ_FIR_CHROMA_COEFF_PHASE7_14_15_reserved2_SHIFT 0 #endif /* #ifndef BCHP_SCL_HD_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015600000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_i2c_gr_bridge.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_i2c_gr0000644000175000017500000001310711610313111030705 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_i2c_gr_bridge.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:08p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:01 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_i2c_gr_bridge.h $ * * Hydra_Software_Devel/1 7/17/09 8:08p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_I2C_GR_BRIDGE_H__ #define BCHP_I2C_GR_BRIDGE_H__ /*************************************************************************** *I2C_GR_BRIDGE - I2C GR bridge registers ***************************************************************************/ #define BCHP_I2C_GR_BRIDGE_REVISION 0x005013e0 /* GR Bridge Revision */ #define BCHP_I2C_GR_BRIDGE_CTRL 0x005013e4 /* GR Bridge Control Register */ #define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_0 0x005013e8 /* GR Bridge Software Reset 0 Register */ #define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_1 0x005013ec /* GR Bridge Software Reset 1 Register */ /*************************************************************************** *REVISION - GR Bridge Revision ***************************************************************************/ /* I2C_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define BCHP_I2C_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define BCHP_I2C_GR_BRIDGE_REVISION_reserved0_SHIFT 16 /* I2C_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define BCHP_I2C_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_I2C_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* I2C_GR_BRIDGE :: REVISION :: MINOR [07:00] */ #define BCHP_I2C_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define BCHP_I2C_GR_BRIDGE_REVISION_MINOR_SHIFT 0 /*************************************************************************** *CTRL - GR Bridge Control Register ***************************************************************************/ /* I2C_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ #define BCHP_I2C_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe #define BCHP_I2C_GR_BRIDGE_CTRL_reserved0_SHIFT 1 /* I2C_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ #define BCHP_I2C_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 #define BCHP_I2C_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 #define BCHP_I2C_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 #define BCHP_I2C_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 /*************************************************************************** *SPARE_SW_RESET_0 - GR Bridge Software Reset 0 Register ***************************************************************************/ /* I2C_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ #define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe #define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 /* I2C_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 #define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 #define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 /*************************************************************************** *SPARE_SW_RESET_1 - GR Bridge Software Reset 1 Register ***************************************************************************/ /* I2C_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ #define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe #define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 /* I2C_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ #define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 #define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 #define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 #define BCHP_I2C_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 #endif /* #ifndef BCHP_I2C_GR_BRIDGE_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015300000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc_perst.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc_p0000644000175000017500000002673711610313111031027 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_misc_perst.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:12p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:23 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc_perst.h $ * * Hydra_Software_Devel/1 7/17/09 8:12p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_MISC_PERST_H__ #define BCHP_MISC_PERST_H__ /*************************************************************************** *MISC_PERST - Registers for Link reset on PERST_N ***************************************************************************/ #define BCHP_MISC_PERST_ECO_CTRL_PERST 0x00502280 /* ECO PCIE Reset Control Register */ #define BCHP_MISC_PERST_DECODER_CTRL 0x00502284 /* Decoder Control Register */ #define BCHP_MISC_PERST_CCE_STATUS 0x00502288 /* Config Copy Engine Status */ #define BCHP_MISC_PERST_PCIE_DEBUG 0x0050228c /* PCIE Debug Control Register */ #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS 0x00502290 /* PCIE Debug Status Register */ #define BCHP_MISC_PERST_PCIE_LTSSM_STATUS 0x00502294 /* PCIE LTSSM Status Register */ #define BCHP_MISC_PERST_CLOCK_CTRL 0x0050229c /* Clock Control Register */ /*************************************************************************** *ECO_CTRL_PERST - ECO PCIE Reset Control Register ***************************************************************************/ /* MISC_PERST :: ECO_CTRL_PERST :: reserved0 [31:16] */ #define BCHP_MISC_PERST_ECO_CTRL_PERST_reserved0_MASK 0xffff0000 #define BCHP_MISC_PERST_ECO_CTRL_PERST_reserved0_SHIFT 16 /* MISC_PERST :: ECO_CTRL_PERST :: ECO_PERST_N [15:00] */ #define BCHP_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_MASK 0x0000ffff #define BCHP_MISC_PERST_ECO_CTRL_PERST_ECO_PERST_N_SHIFT 0 /*************************************************************************** *DECODER_CTRL - Decoder Control Register ***************************************************************************/ /* MISC_PERST :: DECODER_CTRL :: reserved0 [31:05] */ #define BCHP_MISC_PERST_DECODER_CTRL_reserved0_MASK 0xffffffe0 #define BCHP_MISC_PERST_DECODER_CTRL_reserved0_SHIFT 5 /* MISC_PERST :: DECODER_CTRL :: STOP_CLK_OUT [04:04] */ #define BCHP_MISC_PERST_DECODER_CTRL_STOP_CLK_OUT_MASK 0x00000010 #define BCHP_MISC_PERST_DECODER_CTRL_STOP_CLK_OUT_SHIFT 4 /* MISC_PERST :: DECODER_CTRL :: reserved1 [03:01] */ #define BCHP_MISC_PERST_DECODER_CTRL_reserved1_MASK 0x0000000e #define BCHP_MISC_PERST_DECODER_CTRL_reserved1_SHIFT 1 /* MISC_PERST :: DECODER_CTRL :: BCM2727_RUN [00:00] */ #define BCHP_MISC_PERST_DECODER_CTRL_BCM2727_RUN_MASK 0x00000001 #define BCHP_MISC_PERST_DECODER_CTRL_BCM2727_RUN_SHIFT 0 /*************************************************************************** *CCE_STATUS - Config Copy Engine Status ***************************************************************************/ /* MISC_PERST :: CCE_STATUS :: CCE_DONE [31:31] */ #define BCHP_MISC_PERST_CCE_STATUS_CCE_DONE_MASK 0x80000000 #define BCHP_MISC_PERST_CCE_STATUS_CCE_DONE_SHIFT 31 /* MISC_PERST :: CCE_STATUS :: reserved0 [30:03] */ #define BCHP_MISC_PERST_CCE_STATUS_reserved0_MASK 0x7ffffff8 #define BCHP_MISC_PERST_CCE_STATUS_reserved0_SHIFT 3 /* MISC_PERST :: CCE_STATUS :: CCE_BAD_GISB_ACCESS [02:02] */ #define BCHP_MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_MASK 0x00000004 #define BCHP_MISC_PERST_CCE_STATUS_CCE_BAD_GISB_ACCESS_SHIFT 2 /* MISC_PERST :: CCE_STATUS :: CCE_BAD_I2C_ACCESS [01:01] */ #define BCHP_MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_MASK 0x00000002 #define BCHP_MISC_PERST_CCE_STATUS_CCE_BAD_I2C_ACCESS_SHIFT 1 /* MISC_PERST :: CCE_STATUS :: CCE_BAD_SECTION_ID [00:00] */ #define BCHP_MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_MASK 0x00000001 #define BCHP_MISC_PERST_CCE_STATUS_CCE_BAD_SECTION_ID_SHIFT 0 /*************************************************************************** *PCIE_DEBUG - PCIE Debug Control Register ***************************************************************************/ /* MISC_PERST :: PCIE_DEBUG :: SERDES_TERM_CNT [31:16] */ #define BCHP_MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_MASK 0xffff0000 #define BCHP_MISC_PERST_PCIE_DEBUG_SERDES_TERM_CNT_SHIFT 16 /* MISC_PERST :: PCIE_DEBUG :: reserved0 [15:13] */ #define BCHP_MISC_PERST_PCIE_DEBUG_reserved0_MASK 0x0000e000 #define BCHP_MISC_PERST_PCIE_DEBUG_reserved0_SHIFT 13 /* MISC_PERST :: PCIE_DEBUG :: FORCE_CLOCK_SWITCH [12:12] */ #define BCHP_MISC_PERST_PCIE_DEBUG_FORCE_CLOCK_SWITCH_MASK 0x00001000 #define BCHP_MISC_PERST_PCIE_DEBUG_FORCE_CLOCK_SWITCH_SHIFT 12 /* MISC_PERST :: PCIE_DEBUG :: CLKREQ_PLLPD_EXTEND_DISABLE [11:11] */ #define BCHP_MISC_PERST_PCIE_DEBUG_CLKREQ_PLLPD_EXTEND_DISABLE_MASK 0x00000800 #define BCHP_MISC_PERST_PCIE_DEBUG_CLKREQ_PLLPD_EXTEND_DISABLE_SHIFT 11 /* MISC_PERST :: PCIE_DEBUG :: PLL_VCO_RESCUE [10:10] */ #define BCHP_MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_MASK 0x00000400 #define BCHP_MISC_PERST_PCIE_DEBUG_PLL_VCO_RESCUE_SHIFT 10 /* MISC_PERST :: PCIE_DEBUG :: PLL_PDN_OVERRIDE [09:09] */ #define BCHP_MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_MASK 0x00000200 #define BCHP_MISC_PERST_PCIE_DEBUG_PLL_PDN_OVERRIDE_SHIFT 9 /* MISC_PERST :: PCIE_DEBUG :: CORE_CLOCK_OVR [08:08] */ #define BCHP_MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_MASK 0x00000100 #define BCHP_MISC_PERST_PCIE_DEBUG_CORE_CLOCK_OVR_SHIFT 8 /* MISC_PERST :: PCIE_DEBUG :: reserved1 [07:04] */ #define BCHP_MISC_PERST_PCIE_DEBUG_reserved1_MASK 0x000000f0 #define BCHP_MISC_PERST_PCIE_DEBUG_reserved1_SHIFT 4 /* MISC_PERST :: PCIE_DEBUG :: PCIE_TMUX_SEL [03:00] */ #define BCHP_MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_MASK 0x0000000f #define BCHP_MISC_PERST_PCIE_DEBUG_PCIE_TMUX_SEL_SHIFT 0 /*************************************************************************** *PCIE_DEBUG_STATUS - PCIE Debug Status Register ***************************************************************************/ /* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved0 [31:20] */ #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_reserved0_MASK 0xfff00000 #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_reserved0_SHIFT 20 /* MISC_PERST :: PCIE_DEBUG_STATUS :: PCS_LINK_IN_L2 [19:19] */ #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCS_LINK_IN_L2_MASK 0x00080000 #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCS_LINK_IN_L2_SHIFT 19 /* MISC_PERST :: PCIE_DEBUG_STATUS :: PCS_LINK_IN_L1 [18:18] */ #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCS_LINK_IN_L1_MASK 0x00040000 #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCS_LINK_IN_L1_SHIFT 18 /* MISC_PERST :: PCIE_DEBUG_STATUS :: PCS_LINK_IN_L0S [17:17] */ #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCS_LINK_IN_L0S_MASK 0x00020000 #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCS_LINK_IN_L0S_SHIFT 17 /* MISC_PERST :: PCIE_DEBUG_STATUS :: PCIE_IDLE [16:16] */ #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCIE_IDLE_MASK 0x00010000 #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PCIE_IDLE_SHIFT 16 /* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved1 [15:06] */ #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_reserved1_MASK 0x0000ffc0 #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_reserved1_SHIFT 6 /* MISC_PERST :: PCIE_DEBUG_STATUS :: DATALINKATTN [05:05] */ #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_MASK 0x00000020 #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_DATALINKATTN_SHIFT 5 /* MISC_PERST :: PCIE_DEBUG_STATUS :: PHYLINKATTN [04:04] */ #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_MASK 0x00000010 #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PHYLINKATTN_SHIFT 4 /* MISC_PERST :: PCIE_DEBUG_STATUS :: reserved2 [03:02] */ #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_reserved2_MASK 0x0000000c #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_reserved2_SHIFT 2 /* MISC_PERST :: PCIE_DEBUG_STATUS :: DATA_LINKUP [01:01] */ #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_MASK 0x00000002 #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_DATA_LINKUP_SHIFT 1 /* MISC_PERST :: PCIE_DEBUG_STATUS :: PHY_LINKUP [00:00] */ #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_MASK 0x00000001 #define BCHP_MISC_PERST_PCIE_DEBUG_STATUS_PHY_LINKUP_SHIFT 0 /*************************************************************************** *PCIE_LTSSM_STATUS - PCIE LTSSM Status Register ***************************************************************************/ /* MISC_PERST :: PCIE_LTSSM_STATUS :: LTSSM_VECTOR [31:00] */ #define BCHP_MISC_PERST_PCIE_LTSSM_STATUS_LTSSM_VECTOR_MASK 0xffffffff #define BCHP_MISC_PERST_PCIE_LTSSM_STATUS_LTSSM_VECTOR_SHIFT 0 /*************************************************************************** *CLOCK_CTRL - Clock Control Register ***************************************************************************/ /* MISC_PERST :: CLOCK_CTRL :: reserved0 [31:03] */ #define BCHP_MISC_PERST_CLOCK_CTRL_reserved0_MASK 0xfffffff8 #define BCHP_MISC_PERST_CLOCK_CTRL_reserved0_SHIFT 3 /* MISC_PERST :: CLOCK_CTRL :: EARLY_L1_EXIT [02:02] */ #define BCHP_MISC_PERST_CLOCK_CTRL_EARLY_L1_EXIT_MASK 0x00000004 #define BCHP_MISC_PERST_CLOCK_CTRL_EARLY_L1_EXIT_SHIFT 2 /* MISC_PERST :: CLOCK_CTRL :: STOP_CORE_CLK [01:01] */ #define BCHP_MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_MASK 0x00000002 #define BCHP_MISC_PERST_CLOCK_CTRL_STOP_CORE_CLK_SHIFT 1 /* MISC_PERST :: CLOCK_CTRL :: SEL_ALT_CLK [00:00] */ #define BCHP_MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_MASK 0x00000001 #define BCHP_MISC_PERST_CLOCK_CTRL_SEL_ALT_CLK_SHIFT 0 #endif /* #ifndef BCHP_MISC_PERST_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016100000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ip_shim_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000011312411610313111030763 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_ip_shim_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:04p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:04 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ip_shim_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:04p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_IP_SHIM_0_H__ #define BCHP_DECODE_IP_SHIM_0_H__ /*************************************************************************** *DECODE_IP_SHIM_0 - AVD Shim Registers 0 ***************************************************************************/ #define BCHP_DECODE_IP_SHIM_0_STC0_REG 0x00860000 /* Serial Time Stamp PTS register */ #define BCHP_DECODE_IP_SHIM_0_STC1_REG 0x00860004 /* Serial Time Stamp PTS register */ #define BCHP_DECODE_IP_SHIM_0_ENDIAN_REG 0x00860008 /* Stream Endian Control Register */ #define BCHP_DECODE_IP_SHIM_0_BVN_INT_REG 0x0086000c /* BVN Interrupt Register */ #define BCHP_DECODE_IP_SHIM_0_CPU_ID 0x00860010 /* Chip ID Regsiter */ #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE 0x00860014 /* Clock Gate Register */ #define BCHP_DECODE_IP_SHIM_0_DBI_TM_REG 0x00860034 /* Deblock Intercept Buffer TM register */ #define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG 0x00860038 /* ARC TM Register */ #define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG 0x0086003c /* ARC TM Register */ #define BCHP_DECODE_IP_SHIM_0_CPU_DBG_TM_REG 0x00860040 /* CPU Debug FIFO TM Register */ #define BCHP_DECODE_IP_SHIM_0_CABAC_TM_REG 0x00860044 /* CABAC TM Register */ #define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG 0x00860048 /* Decode TM Register */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG 0x0086004c /* Frontend FSRF TM Register */ #define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG 0x00860050 /* ARC FSRF TM Register */ #define BCHP_DECODE_IP_SHIM_0_SHIM_FSRF_TM_REG 0x00860054 /* SHIM FSRF TM Register */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG 0x00860058 /* DECODE FSRF TM Register */ #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG 0x0086005c /* DEBLOCK FSRF TM Register */ #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG 0x00860060 /* IXFORM FSRF TM Register */ #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG 0x00860064 /* SI FSRF TM Register */ #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG 0x00860068 /* FGTAVE FSRF TM Register */ #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG 0x0086006c /* PCACHE FSRF TM Register */ #define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_ADDR_REG 0x00860070 /* Scratch RAM Address */ #define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_ADDR_REG 0x00860074 /* Scratch RAM Address */ #define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_DATA_REG 0x00860078 /* Scratch RAM Data */ #define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_DATA_REG 0x0086007c /* Scratch RAM Data */ /*************************************************************************** *STC0_REG - Serial Time Stamp PTS register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: STC0_REG :: STC [31:00] */ #define BCHP_DECODE_IP_SHIM_0_STC0_REG_STC_MASK 0xffffffff #define BCHP_DECODE_IP_SHIM_0_STC0_REG_STC_SHIFT 0 /*************************************************************************** *STC1_REG - Serial Time Stamp PTS register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: STC1_REG :: STC [31:00] */ #define BCHP_DECODE_IP_SHIM_0_STC1_REG_STC_MASK 0xffffffff #define BCHP_DECODE_IP_SHIM_0_STC1_REG_STC_SHIFT 0 /*************************************************************************** *ENDIAN_REG - Stream Endian Control Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: ENDIAN_REG :: reserved0 [31:01] */ #define BCHP_DECODE_IP_SHIM_0_ENDIAN_REG_reserved0_MASK 0xfffffffe #define BCHP_DECODE_IP_SHIM_0_ENDIAN_REG_reserved0_SHIFT 1 /* DECODE_IP_SHIM_0 :: ENDIAN_REG :: B1L0 [00:00] */ #define BCHP_DECODE_IP_SHIM_0_ENDIAN_REG_B1L0_MASK 0x00000001 #define BCHP_DECODE_IP_SHIM_0_ENDIAN_REG_B1L0_SHIFT 0 /*************************************************************************** *BVN_INT_REG - BVN Interrupt Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: BVN_INT_REG :: reserved0 [31:02] */ #define BCHP_DECODE_IP_SHIM_0_BVN_INT_REG_reserved0_MASK 0xfffffffc #define BCHP_DECODE_IP_SHIM_0_BVN_INT_REG_reserved0_SHIFT 2 /* DECODE_IP_SHIM_0 :: BVN_INT_REG :: desc [01:01] */ #define BCHP_DECODE_IP_SHIM_0_BVN_INT_REG_desc_MASK 0x00000002 #define BCHP_DECODE_IP_SHIM_0_BVN_INT_REG_desc_SHIFT 1 /* DECODE_IP_SHIM_0 :: BVN_INT_REG :: trigger [00:00] */ #define BCHP_DECODE_IP_SHIM_0_BVN_INT_REG_trigger_MASK 0x00000001 #define BCHP_DECODE_IP_SHIM_0_BVN_INT_REG_trigger_SHIFT 0 /*************************************************************************** *CPU_ID - Chip ID Regsiter ***************************************************************************/ /* DECODE_IP_SHIM_0 :: CPU_ID :: reserved0 [31:17] */ #define BCHP_DECODE_IP_SHIM_0_CPU_ID_reserved0_MASK 0xfffe0000 #define BCHP_DECODE_IP_SHIM_0_CPU_ID_reserved0_SHIFT 17 /* DECODE_IP_SHIM_0 :: CPU_ID :: AVD_ID [16:16] */ #define BCHP_DECODE_IP_SHIM_0_CPU_ID_AVD_ID_MASK 0x00010000 #define BCHP_DECODE_IP_SHIM_0_CPU_ID_AVD_ID_SHIFT 16 /* DECODE_IP_SHIM_0 :: CPU_ID :: IL_CPU_ID [15:08] */ #define BCHP_DECODE_IP_SHIM_0_CPU_ID_IL_CPU_ID_MASK 0x0000ff00 #define BCHP_DECODE_IP_SHIM_0_CPU_ID_IL_CPU_ID_SHIFT 8 /* DECODE_IP_SHIM_0 :: CPU_ID :: OL_CPU_ID [07:00] */ #define BCHP_DECODE_IP_SHIM_0_CPU_ID_OL_CPU_ID_MASK 0x000000ff #define BCHP_DECODE_IP_SHIM_0_CPU_ID_OL_CPU_ID_SHIFT 0 /*************************************************************************** *REG_AVD_CLK_GATE - Clock Gate Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: reserved0 [31:10] */ #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_reserved0_MASK 0xfffffc00 #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_reserved0_SHIFT 10 /* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_ka [09:09] */ #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_ka_MASK 0x00000200 #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_ka_SHIFT 9 /* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_fgt [08:08] */ #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_fgt_MASK 0x00000100 #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_fgt_SHIFT 8 /* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_cab [07:07] */ #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_cab_MASK 0x00000080 #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_cab_SHIFT 7 /* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_intra [06:06] */ #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_intra_MASK 0x00000040 #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_intra_SHIFT 6 /* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_vframe [05:05] */ #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_vframe_MASK 0x00000020 #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_vframe_SHIFT 5 /* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_avc [04:04] */ #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_avc_MASK 0x00000010 #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_avc_SHIFT 4 /* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_vc1 [03:03] */ #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_vc1_MASK 0x00000008 #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_vc1_SHIFT 3 /* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_vc1_db [02:02] */ #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_vc1_db_MASK 0x00000004 #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_vc1_db_SHIFT 2 /* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_mp4 [01:01] */ #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_mp4_MASK 0x00000002 #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_mp4_SHIFT 1 /* DECODE_IP_SHIM_0 :: REG_AVD_CLK_GATE :: clk_mp2 [00:00] */ #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_mp2_MASK 0x00000001 #define BCHP_DECODE_IP_SHIM_0_REG_AVD_CLK_GATE_clk_mp2_SHIFT 0 /*************************************************************************** *DBI_TM_REG - Deblock Intercept Buffer TM register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: DBI_TM_REG :: reserved0 [31:08] */ #define BCHP_DECODE_IP_SHIM_0_DBI_TM_REG_reserved0_MASK 0xffffff00 #define BCHP_DECODE_IP_SHIM_0_DBI_TM_REG_reserved0_SHIFT 8 /* DECODE_IP_SHIM_0 :: DBI_TM_REG :: Y_TM [07:04] */ #define BCHP_DECODE_IP_SHIM_0_DBI_TM_REG_Y_TM_MASK 0x000000f0 #define BCHP_DECODE_IP_SHIM_0_DBI_TM_REG_Y_TM_SHIFT 4 /* DECODE_IP_SHIM_0 :: DBI_TM_REG :: UV_TM [03:00] */ #define BCHP_DECODE_IP_SHIM_0_DBI_TM_REG_UV_TM_MASK 0x0000000f #define BCHP_DECODE_IP_SHIM_0_DBI_TM_REG_UV_TM_SHIFT 0 /*************************************************************************** *ARC0_TM_REG - ARC TM Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: ARC0_TM_REG :: reserved0 [31:12] */ #define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_reserved0_MASK 0xfffff000 #define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_reserved0_SHIFT 12 /* DECODE_IP_SHIM_0 :: ARC0_TM_REG :: ISTORE_TM [11:08] */ #define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_ISTORE_TM_MASK 0x00000f00 #define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_ISTORE_TM_SHIFT 8 /* DECODE_IP_SHIM_0 :: ARC0_TM_REG :: DSTORE_TM [07:04] */ #define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_DSTORE_TM_MASK 0x000000f0 #define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_DSTORE_TM_SHIFT 4 /* DECODE_IP_SHIM_0 :: ARC0_TM_REG :: TAG_TM [03:00] */ #define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_TAG_TM_MASK 0x0000000f #define BCHP_DECODE_IP_SHIM_0_ARC0_TM_REG_TAG_TM_SHIFT 0 /*************************************************************************** *ARC1_TM_REG - ARC TM Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: ARC1_TM_REG :: reserved0 [31:12] */ #define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_reserved0_MASK 0xfffff000 #define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_reserved0_SHIFT 12 /* DECODE_IP_SHIM_0 :: ARC1_TM_REG :: ISTORE_TM [11:08] */ #define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_ISTORE_TM_MASK 0x00000f00 #define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_ISTORE_TM_SHIFT 8 /* DECODE_IP_SHIM_0 :: ARC1_TM_REG :: DSTORE_TM [07:04] */ #define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_DSTORE_TM_MASK 0x000000f0 #define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_DSTORE_TM_SHIFT 4 /* DECODE_IP_SHIM_0 :: ARC1_TM_REG :: TAG_TM [03:00] */ #define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_TAG_TM_MASK 0x0000000f #define BCHP_DECODE_IP_SHIM_0_ARC1_TM_REG_TAG_TM_SHIFT 0 /*************************************************************************** *CPU_DBG_TM_REG - CPU Debug FIFO TM Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: CPU_DBG_TM_REG :: reserved0 [31:04] */ #define BCHP_DECODE_IP_SHIM_0_CPU_DBG_TM_REG_reserved0_MASK 0xfffffff0 #define BCHP_DECODE_IP_SHIM_0_CPU_DBG_TM_REG_reserved0_SHIFT 4 /* DECODE_IP_SHIM_0 :: CPU_DBG_TM_REG :: TM [03:00] */ #define BCHP_DECODE_IP_SHIM_0_CPU_DBG_TM_REG_TM_MASK 0x0000000f #define BCHP_DECODE_IP_SHIM_0_CPU_DBG_TM_REG_TM_SHIFT 0 /*************************************************************************** *CABAC_TM_REG - CABAC TM Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: CABAC_TM_REG :: reserved0 [31:04] */ #define BCHP_DECODE_IP_SHIM_0_CABAC_TM_REG_reserved0_MASK 0xfffffff0 #define BCHP_DECODE_IP_SHIM_0_CABAC_TM_REG_reserved0_SHIFT 4 /* DECODE_IP_SHIM_0 :: CABAC_TM_REG :: TM [03:00] */ #define BCHP_DECODE_IP_SHIM_0_CABAC_TM_REG_TM_MASK 0x0000000f #define BCHP_DECODE_IP_SHIM_0_CABAC_TM_REG_TM_SHIFT 0 /*************************************************************************** *DECODE_TM_REG - Decode TM Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: DECODE_TM_REG :: reserved0 [31:16] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_reserved0_MASK 0xffff0000 #define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_reserved0_SHIFT 16 /* DECODE_IP_SHIM_0 :: DECODE_TM_REG :: LBYUV_TM [15:12] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_LBYUV_TM_MASK 0x0000f000 #define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_LBYUV_TM_SHIFT 12 /* DECODE_IP_SHIM_0 :: DECODE_TM_REG :: PPBUF_2_TM [11:08] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_PPBUF_2_TM_MASK 0x00000f00 #define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_PPBUF_2_TM_SHIFT 8 /* DECODE_IP_SHIM_0 :: DECODE_TM_REG :: PPBUF_1_TM [07:04] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_PPBUF_1_TM_MASK 0x000000f0 #define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_PPBUF_1_TM_SHIFT 4 /* DECODE_IP_SHIM_0 :: DECODE_TM_REG :: PPBUF_0_TM [03:00] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_PPBUF_0_TM_MASK 0x0000000f #define BCHP_DECODE_IP_SHIM_0_DECODE_TM_REG_PPBUF_0_TM_SHIFT 0 /*************************************************************************** *FRONTEND_FSRF_TM_REG - Frontend FSRF TM Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: reserved0 [31:28] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_reserved0_MASK 0xf0000000 #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_reserved0_SHIFT 28 /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_1K_256X8_3 [27:26] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_3_MASK 0x0c000000 #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_3_SHIFT 26 /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_1K_256X8_2 [25:24] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_2_MASK 0x03000000 #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_2_SHIFT 24 /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_1K_256X8_1 [23:22] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_1_MASK 0x00c00000 #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_1_SHIFT 22 /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_1K_256X8_0 [21:20] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_0_MASK 0x00300000 #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_1K_256X8_0_SHIFT 20 /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_512_128X8_3 [19:18] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_3_MASK 0x000c0000 #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_3_SHIFT 18 /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_512_128X8_2 [17:16] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_2_MASK 0x00030000 #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_2_SHIFT 16 /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_512_128X8_1 [15:14] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_1_MASK 0x0000c000 #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_1_SHIFT 14 /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CPUDMA_512_128X8_0 [13:12] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_0_MASK 0x00003000 #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CPUDMA_512_128X8_0_SHIFT 12 /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CABAC_32X32 [11:10] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_32X32_MASK 0x00000c00 #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_32X32_SHIFT 10 /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CABAC_464X7 [09:08] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_464X7_MASK 0x00000300 #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_464X7_SHIFT 8 /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CABAC_64X32_2 [07:06] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_64X32_2_MASK 0x000000c0 #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_64X32_2_SHIFT 6 /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CABAC_64X32_1 [05:04] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_64X32_1_MASK 0x00000030 #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_64X32_1_SHIFT 4 /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: CABAC_64X32_0 [03:02] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_64X32_0_MASK 0x0000000c #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_CABAC_64X32_0_SHIFT 2 /* DECODE_IP_SHIM_0 :: FRONTEND_FSRF_TM_REG :: RVC_64X32 [01:00] */ #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_RVC_64X32_MASK 0x00000003 #define BCHP_DECODE_IP_SHIM_0_FRONTEND_FSRF_TM_REG_RVC_64X32_SHIFT 0 /*************************************************************************** *ARC_FSRF_TM_REG - ARC FSRF TM Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: ARC_FSRF_TM_REG :: reserved0 [31:08] */ #define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_reserved0_MASK 0xffffff00 #define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_reserved0_SHIFT 8 /* DECODE_IP_SHIM_0 :: ARC_FSRF_TM_REG :: OLARC_32X32_1 [07:06] */ #define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_OLARC_32X32_1_MASK 0x000000c0 #define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_OLARC_32X32_1_SHIFT 6 /* DECODE_IP_SHIM_0 :: ARC_FSRF_TM_REG :: OLARC_32X32_0 [05:04] */ #define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_OLARC_32X32_0_MASK 0x00000030 #define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_OLARC_32X32_0_SHIFT 4 /* DECODE_IP_SHIM_0 :: ARC_FSRF_TM_REG :: ILARC_32X32_1 [03:02] */ #define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_ILARC_32X32_1_MASK 0x0000000c #define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_ILARC_32X32_1_SHIFT 2 /* DECODE_IP_SHIM_0 :: ARC_FSRF_TM_REG :: ILARC_32X32_0 [01:00] */ #define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_ILARC_32X32_0_MASK 0x00000003 #define BCHP_DECODE_IP_SHIM_0_ARC_FSRF_TM_REG_ILARC_32X32_0_SHIFT 0 /*************************************************************************** *SHIM_FSRF_TM_REG - SHIM FSRF TM Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: SHIM_FSRF_TM_REG :: AVD_REGS_96X32 [31:30] */ #define BCHP_DECODE_IP_SHIM_0_SHIM_FSRF_TM_REG_AVD_REGS_96X32_MASK 0xc0000000 #define BCHP_DECODE_IP_SHIM_0_SHIM_FSRF_TM_REG_AVD_REGS_96X32_SHIFT 30 /* DECODE_IP_SHIM_0 :: SHIM_FSRF_TM_REG :: reserved0 [29:00] */ #define BCHP_DECODE_IP_SHIM_0_SHIM_FSRF_TM_REG_reserved0_MASK 0x3fffffff #define BCHP_DECODE_IP_SHIM_0_SHIM_FSRF_TM_REG_reserved0_SHIFT 0 /*************************************************************************** *DECODE_FSRF_TM_REG - DECODE FSRF TM Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_64X8 [31:30] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X8_MASK 0xc0000000 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X8_SHIFT 30 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_64X32_1 [29:28] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X32_1_MASK 0x30000000 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X32_1_SHIFT 28 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_64X32_0 [27:26] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X32_0_MASK 0x0c000000 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X32_0_SHIFT 26 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_64X16_3 [25:24] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_3_MASK 0x03000000 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_3_SHIFT 24 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_64X16_2 [23:22] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_2_MASK 0x00c00000 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_2_SHIFT 22 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_64X16_1 [21:20] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_1_MASK 0x00300000 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_1_SHIFT 20 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_64X16_0 [19:18] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_0_MASK 0x000c0000 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_64X16_0_SHIFT 18 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_128X40_1 [17:16] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_128X40_1_MASK 0x00030000 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_128X40_1_SHIFT 16 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_128X40_0 [15:14] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_128X40_0_MASK 0x0000c000 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_128X40_0_SHIFT 14 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_128X32 [13:12] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_128X32_MASK 0x00003000 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_128X32_SHIFT 12 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: QPEL_256x32_1 [11:10] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_QPEL_256x32_1_MASK 0x00000c00 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_QPEL_256x32_1_SHIFT 10 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_256X16_1 [09:08] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_256X16_1_MASK 0x00000300 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_256X16_1_SHIFT 8 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: DECODE_256X16_0 [07:06] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_256X16_0_MASK 0x000000c0 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_DECODE_256X16_0_SHIFT 6 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: PPBUF_256_256X36 [05:04] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_PPBUF_256_256X36_MASK 0x00000030 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_PPBUF_256_256X36_SHIFT 4 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: PPBUF_128_128X36 [03:02] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_PPBUF_128_128X36_MASK 0x0000000c #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_PPBUF_128_128X36_SHIFT 2 /* DECODE_IP_SHIM_0 :: DECODE_FSRF_TM_REG :: QPEL_256x32_0 [01:00] */ #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_QPEL_256x32_0_MASK 0x00000003 #define BCHP_DECODE_IP_SHIM_0_DECODE_FSRF_TM_REG_QPEL_256x32_0_SHIFT 0 /*************************************************************************** *DEBLOCK_FSRF_TM_REG - DEBLOCK FSRF TM Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: reserved0 [31:16] */ #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_reserved0_MASK 0xffff0000 #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_reserved0_SHIFT 16 /* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_128X36 [15:14] */ #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_128X36_MASK 0x0000c000 #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_128X36_SHIFT 14 /* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_64X32_1 [13:12] */ #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_64X32_1_MASK 0x00003000 #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_64X32_1_SHIFT 12 /* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_64X32_0 [11:10] */ #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_64X32_0_MASK 0x00000c00 #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_64X32_0_SHIFT 10 /* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_336X32_1 [09:08] */ #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_336X32_1_MASK 0x00000300 #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_336X32_1_SHIFT 8 /* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_336X32_0 [07:06] */ #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_336X32_0_MASK 0x000000c0 #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_336X32_0_SHIFT 6 /* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_32X24 [05:04] */ #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_32X24_MASK 0x00000030 #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_32X24_SHIFT 4 /* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_192X44_1 [03:02] */ #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_192X44_1_MASK 0x0000000c #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_192X44_1_SHIFT 2 /* DECODE_IP_SHIM_0 :: DEBLOCK_FSRF_TM_REG :: DB_192X44_0 [01:00] */ #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_192X44_0_MASK 0x00000003 #define BCHP_DECODE_IP_SHIM_0_DEBLOCK_FSRF_TM_REG_DB_192X44_0_SHIFT 0 /*************************************************************************** *IXFORM_FSRF_TM_REG - IXFORM FSRF TM Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: reserved0 [31:18] */ #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_reserved0_MASK 0xfffc0000 #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_reserved0_SHIFT 18 /* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: QPEL_128X14 [17:16] */ #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_QPEL_128X14_MASK 0x00030000 #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_QPEL_128X14_SHIFT 16 /* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: IXFRM_128X20 [15:14] */ #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IXFRM_128X20_MASK 0x0000c000 #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IXFRM_128X20_SHIFT 14 /* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: VC1_128X12 [13:12] */ #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_VC1_128X12_MASK 0x00003000 #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_VC1_128X12_SHIFT 12 /* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: VC1_128X18 [11:10] */ #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_VC1_128X18_MASK 0x00000c00 #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_VC1_128X18_SHIFT 10 /* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: IXFRM_256X20 [09:08] */ #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IXFRM_256X20_MASK 0x00000300 #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IXFRM_256X20_SHIFT 8 /* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: IDCT_128X16 [07:06] */ #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IDCT_128X16_MASK 0x000000c0 #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IDCT_128X16_SHIFT 6 /* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: IDCT_128X24 [05:04] */ #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IDCT_128X24_MASK 0x00000030 #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IDCT_128X24_SHIFT 4 /* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: IDCT_32X32 [03:02] */ #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IDCT_32X32_MASK 0x0000000c #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IDCT_32X32_SHIFT 2 /* DECODE_IP_SHIM_0 :: IXFORM_FSRF_TM_REG :: IXFRM_32X32 [01:00] */ #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IXFRM_32X32_MASK 0x00000003 #define BCHP_DECODE_IP_SHIM_0_IXFORM_FSRF_TM_REG_IXFRM_32X32_SHIFT 0 /*************************************************************************** *SI_FSRF_TM_REG - SI FSRF TM Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: reserved0 [31:18] */ #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_reserved0_MASK 0xfffc0000 #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_reserved0_SHIFT 18 /* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: OLSI_128X32 [17:16] */ #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_OLSI_128X32_MASK 0x00030000 #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_OLSI_128X32_SHIFT 16 /* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_128X32 [15:14] */ #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X32_MASK 0x0000c000 #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X32_SHIFT 14 /* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_128X8_2 [13:12] */ #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X8_2_MASK 0x00003000 #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X8_2_SHIFT 12 /* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_128X8_1 [11:10] */ #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X8_1_MASK 0x00000c00 #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X8_1_SHIFT 10 /* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_128X8_0 [09:08] */ #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X8_0_MASK 0x00000300 #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_128X8_0_SHIFT 8 /* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_256X32 [07:06] */ #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_256X32_MASK 0x000000c0 #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_256X32_SHIFT 6 /* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_32X32 [05:04] */ #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_32X32_MASK 0x00000030 #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_32X32_SHIFT 4 /* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_64X32_1 [03:02] */ #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_64X32_1_MASK 0x0000000c #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_64X32_1_SHIFT 2 /* DECODE_IP_SHIM_0 :: SI_FSRF_TM_REG :: ILSI_64X32_0 [01:00] */ #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_64X32_0_MASK 0x00000003 #define BCHP_DECODE_IP_SHIM_0_SI_FSRF_TM_REG_ILSI_64X32_0_SHIFT 0 /*************************************************************************** *FGTAVE_FSRF_TM_REG - FGTAVE FSRF TM Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: reserved0 [31:20] */ #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_reserved0_MASK 0xfff00000 #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_reserved0_SHIFT 20 /* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_128X32 [19:18] */ #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_128X32_MASK 0x000c0000 #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_128X32_SHIFT 18 /* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_128X16_1 [17:16] */ #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_128X16_1_MASK 0x00030000 #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_128X16_1_SHIFT 16 /* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_128X16_0 [15:14] */ #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_128X16_0_MASK 0x0000c000 #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_128X16_0_SHIFT 14 /* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_16X28 [13:12] */ #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_16X28_MASK 0x00003000 #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_16X28_SHIFT 12 /* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_240X32_5 [11:10] */ #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_5_MASK 0x00000c00 #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_5_SHIFT 10 /* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_240X32_4 [09:08] */ #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_4_MASK 0x00000300 #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_4_SHIFT 8 /* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_240X32_3 [07:06] */ #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_3_MASK 0x000000c0 #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_3_SHIFT 6 /* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_240X32_2 [05:04] */ #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_2_MASK 0x00000030 #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_2_SHIFT 4 /* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_240X32_1 [03:02] */ #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_1_MASK 0x0000000c #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_1_SHIFT 2 /* DECODE_IP_SHIM_0 :: FGTAVE_FSRF_TM_REG :: FGTAVE_240X32_0 [01:00] */ #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_0_MASK 0x00000003 #define BCHP_DECODE_IP_SHIM_0_FGTAVE_FSRF_TM_REG_FGTAVE_240X32_0_SHIFT 0 /*************************************************************************** *PCACHE_FSRF_TM_REG - PCACHE FSRF TM Register ***************************************************************************/ /* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: reserved0 [31:16] */ #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_reserved0_MASK 0xffff0000 #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_reserved0_SHIFT 16 /* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: PCACHE_6 [15:14] */ #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_6_MASK 0x0000c000 #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_6_SHIFT 14 /* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: PCACHE_5 [13:12] */ #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_5_MASK 0x00003000 #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_5_SHIFT 12 /* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: PCACHE_4 [11:08] */ #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_4_MASK 0x00000f00 #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_4_SHIFT 8 /* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: PCACHE_3 [07:06] */ #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_3_MASK 0x000000c0 #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_3_SHIFT 6 /* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: PCACHE_2 [05:04] */ #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_2_MASK 0x00000030 #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_2_SHIFT 4 /* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: PCACHE_1 [03:02] */ #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_1_MASK 0x0000000c #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_1_SHIFT 2 /* DECODE_IP_SHIM_0 :: PCACHE_FSRF_TM_REG :: PCACHE_0 [01:00] */ #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_0_MASK 0x00000003 #define BCHP_DECODE_IP_SHIM_0_PCACHE_FSRF_TM_REG_PCACHE_0_SHIFT 0 /*************************************************************************** *HST_SCRATCH_RAM_ADDR_REG - Scratch RAM Address ***************************************************************************/ /* DECODE_IP_SHIM_0 :: HST_SCRATCH_RAM_ADDR_REG :: reserved0 [31:07] */ #define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_ADDR_REG_reserved0_MASK 0xffffff80 #define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_ADDR_REG_reserved0_SHIFT 7 /* DECODE_IP_SHIM_0 :: HST_SCRATCH_RAM_ADDR_REG :: Addr [06:00] */ #define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_ADDR_REG_Addr_MASK 0x0000007f #define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_ADDR_REG_Addr_SHIFT 0 /*************************************************************************** *ARC_SCRATCH_RAM_ADDR_REG - Scratch RAM Address ***************************************************************************/ /* DECODE_IP_SHIM_0 :: ARC_SCRATCH_RAM_ADDR_REG :: reserved0 [31:07] */ #define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_ADDR_REG_reserved0_MASK 0xffffff80 #define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_ADDR_REG_reserved0_SHIFT 7 /* DECODE_IP_SHIM_0 :: ARC_SCRATCH_RAM_ADDR_REG :: Addr [06:00] */ #define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_ADDR_REG_Addr_MASK 0x0000007f #define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_ADDR_REG_Addr_SHIFT 0 /*************************************************************************** *HST_SCRATCH_RAM_DATA_REG - Scratch RAM Data ***************************************************************************/ /* DECODE_IP_SHIM_0 :: HST_SCRATCH_RAM_DATA_REG :: Data [31:00] */ #define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_DATA_REG_Data_MASK 0xffffffff #define BCHP_DECODE_IP_SHIM_0_HST_SCRATCH_RAM_DATA_REG_Data_SHIFT 0 /*************************************************************************** *ARC_SCRATCH_RAM_DATA_REG - Scratch RAM Data ***************************************************************************/ /* DECODE_IP_SHIM_0 :: ARC_SCRATCH_RAM_DATA_REG :: Data [31:00] */ #define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_DATA_REG_Data_MASK 0xffffffff #define BCHP_DECODE_IP_SHIM_0_ARC_SCRATCH_RAM_DATA_REG_Data_SHIFT 0 #endif /* #ifndef BCHP_DECODE_IP_SHIM_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015300000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_scrub_ctrl.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_scrub_0000644000175000017500000004177011610313111031024 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_scrub_ctrl.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:18p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:19 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_scrub_ctrl.h $ * * Hydra_Software_Devel/1 7/17/09 8:18p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_SCRUB_CTRL_H__ #define BCHP_SCRUB_CTRL_H__ /*************************************************************************** *SCRUB_CTRL - Scrub Control Registers ***************************************************************************/ #define BCHP_SCRUB_CTRL_SCRUB_ENABLE 0x000f6000 /* Secure Sequencer Enable */ #define BCHP_SCRUB_CTRL_BORCH_END_ADDRESS 0x000f6004 /* ARM Bridge Out-of-Range Checker End Address */ #define BCHP_SCRUB_CTRL_STARCH_END_ADDRESS 0x000f6008 /* Static ARCH End Address */ #define BCHP_SCRUB_CTRL_BI_CMAC_31_0 0x000f600c /* Boot Image CMAC value[31:0] */ #define BCHP_SCRUB_CTRL_BI_CMAC_63_32 0x000f6010 /* Boot Image CMAC value[63:32] */ #define BCHP_SCRUB_CTRL_BI_CMAC_95_64 0x000f6014 /* Boot Image CMAC value[95:64] */ #define BCHP_SCRUB_CTRL_BI_CMAC_127_96 0x000f6018 /* Boot Image CMAC value[127:96] */ #define BCHP_SCRUB_CTRL_SCRUB_STATUS 0x000f601c /* Secure Data Scrubber Status Register */ #define BCHP_SCRUB_CTRL_CR 0x000f6024 /* CR Word Register */ #define BCHP_SCRUB_CTRL_ECC_DONE 0x000f6030 /* OTP ECC Done Register */ #define BCHP_SCRUB_CTRL_ECC_FAULT 0x000f6034 /* OTP ECC Fault Register */ #define BCHP_SCRUB_CTRL_ECC_FAIL 0x000f6038 /* OTP ECC Fail Register */ #define BCHP_SCRUB_CTRL_KEY0_31_0 0x000f603c /* Key0 [31:0] */ #define BCHP_SCRUB_CTRL_KEY0_63_32 0x000f6040 /* Key0 [63:32] */ #define BCHP_SCRUB_CTRL_KEY0_95_64 0x000f6044 /* Key0 [95:64] */ #define BCHP_SCRUB_CTRL_KEY0_127_96 0x000f6048 /* Key0 [127:96] */ #define BCHP_SCRUB_CTRL_KEY0_PS_31_0 0x000f604c /* Key0 Post scramble [31:0] */ #define BCHP_SCRUB_CTRL_KEY0_PS_63_32 0x000f6050 /* Key0 Post scramble [63:32] */ #define BCHP_SCRUB_CTRL_KEY0_PS_95_64 0x000f6054 /* Key0 Post scramble [95:64] */ #define BCHP_SCRUB_CTRL_KEY0_PS_127_96 0x000f6058 /* Key0 Post scramble [127:96] */ #define BCHP_SCRUB_CTRL_KEY1_31_0 0x000f605c /* Key1 [31:0] */ #define BCHP_SCRUB_CTRL_KEY1_63_32 0x000f6060 /* Key1 [63:32] */ #define BCHP_SCRUB_CTRL_KEY1_95_64 0x000f6064 /* Key1 [95:64] */ #define BCHP_SCRUB_CTRL_KEY1_127_96 0x000f6068 /* Key1 [127:96] */ #define BCHP_SCRUB_CTRL_KEY1_PS_31_0 0x000f606c /* Key1 Post scramble [31:0] */ #define BCHP_SCRUB_CTRL_KEY1_PS_63_32 0x000f6070 /* Key1 Post scramble [63:32] */ #define BCHP_SCRUB_CTRL_KEY1_PS_95_64 0x000f6074 /* Key1 Post scramble [95:64] */ #define BCHP_SCRUB_CTRL_KEY1_PS_127_96 0x000f6078 /* Key1 Post scramble [127:96] */ /*************************************************************************** *SCRUB_ENABLE - Secure Sequencer Enable ***************************************************************************/ /* SCRUB_CTRL :: SCRUB_ENABLE :: reserved0 [31:02] */ #define BCHP_SCRUB_CTRL_SCRUB_ENABLE_reserved0_MASK 0xfffffffc #define BCHP_SCRUB_CTRL_SCRUB_ENABLE_reserved0_SHIFT 2 /* SCRUB_CTRL :: SCRUB_ENABLE :: DSCRAM_EN [01:01] */ #define BCHP_SCRUB_CTRL_SCRUB_ENABLE_DSCRAM_EN_MASK 0x00000002 #define BCHP_SCRUB_CTRL_SCRUB_ENABLE_DSCRAM_EN_SHIFT 1 /* SCRUB_CTRL :: SCRUB_ENABLE :: SCRUB_EN [00:00] */ #define BCHP_SCRUB_CTRL_SCRUB_ENABLE_SCRUB_EN_MASK 0x00000001 #define BCHP_SCRUB_CTRL_SCRUB_ENABLE_SCRUB_EN_SHIFT 0 /*************************************************************************** *BORCH_END_ADDRESS - ARM Bridge Out-of-Range Checker End Address ***************************************************************************/ /* SCRUB_CTRL :: BORCH_END_ADDRESS :: reserved0 [31:27] */ #define BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_reserved0_MASK 0xf8000000 #define BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_reserved0_SHIFT 27 /* SCRUB_CTRL :: BORCH_END_ADDRESS :: BORCH_END_ADDR [26:00] */ #define BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_BORCH_END_ADDR_MASK 0x07ffffff #define BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_BORCH_END_ADDR_SHIFT 0 /*************************************************************************** *STARCH_END_ADDRESS - Static ARCH End Address ***************************************************************************/ /* SCRUB_CTRL :: STARCH_END_ADDRESS :: reserved0 [31:27] */ #define BCHP_SCRUB_CTRL_STARCH_END_ADDRESS_reserved0_MASK 0xf8000000 #define BCHP_SCRUB_CTRL_STARCH_END_ADDRESS_reserved0_SHIFT 27 /* SCRUB_CTRL :: STARCH_END_ADDRESS :: STARCH_END_ADDR [26:00] */ #define BCHP_SCRUB_CTRL_STARCH_END_ADDRESS_STARCH_END_ADDR_MASK 0x07ffffff #define BCHP_SCRUB_CTRL_STARCH_END_ADDRESS_STARCH_END_ADDR_SHIFT 0 /*************************************************************************** *BI_CMAC_31_0 - Boot Image CMAC value[31:0] ***************************************************************************/ /* SCRUB_CTRL :: BI_CMAC_31_0 :: CMAC_WORD [31:00] */ #define BCHP_SCRUB_CTRL_BI_CMAC_31_0_CMAC_WORD_MASK 0xffffffff #define BCHP_SCRUB_CTRL_BI_CMAC_31_0_CMAC_WORD_SHIFT 0 /*************************************************************************** *BI_CMAC_63_32 - Boot Image CMAC value[63:32] ***************************************************************************/ /* SCRUB_CTRL :: BI_CMAC_63_32 :: CMAC_WORD [31:00] */ #define BCHP_SCRUB_CTRL_BI_CMAC_63_32_CMAC_WORD_MASK 0xffffffff #define BCHP_SCRUB_CTRL_BI_CMAC_63_32_CMAC_WORD_SHIFT 0 /*************************************************************************** *BI_CMAC_95_64 - Boot Image CMAC value[95:64] ***************************************************************************/ /* SCRUB_CTRL :: BI_CMAC_95_64 :: CMAC_WORD [31:00] */ #define BCHP_SCRUB_CTRL_BI_CMAC_95_64_CMAC_WORD_MASK 0xffffffff #define BCHP_SCRUB_CTRL_BI_CMAC_95_64_CMAC_WORD_SHIFT 0 /*************************************************************************** *BI_CMAC_127_96 - Boot Image CMAC value[127:96] ***************************************************************************/ /* SCRUB_CTRL :: BI_CMAC_127_96 :: CMAC_WORD [31:00] */ #define BCHP_SCRUB_CTRL_BI_CMAC_127_96_CMAC_WORD_MASK 0xffffffff #define BCHP_SCRUB_CTRL_BI_CMAC_127_96_CMAC_WORD_SHIFT 0 /*************************************************************************** *SCRUB_STATUS - Secure Data Scrubber Status Register ***************************************************************************/ /* SCRUB_CTRL :: SCRUB_STATUS :: reserved0 [31:04] */ #define BCHP_SCRUB_CTRL_SCRUB_STATUS_reserved0_MASK 0xfffffff0 #define BCHP_SCRUB_CTRL_SCRUB_STATUS_reserved0_SHIFT 4 /* SCRUB_CTRL :: SCRUB_STATUS :: CMAC_WORDS_SWAPPED [03:03] */ #define BCHP_SCRUB_CTRL_SCRUB_STATUS_CMAC_WORDS_SWAPPED_MASK 0x00000008 #define BCHP_SCRUB_CTRL_SCRUB_STATUS_CMAC_WORDS_SWAPPED_SHIFT 3 /* SCRUB_CTRL :: SCRUB_STATUS :: SHARF_REG_RD_FAIL [02:02] */ #define BCHP_SCRUB_CTRL_SCRUB_STATUS_SHARF_REG_RD_FAIL_MASK 0x00000004 #define BCHP_SCRUB_CTRL_SCRUB_STATUS_SHARF_REG_RD_FAIL_SHIFT 2 /* SCRUB_CTRL :: SCRUB_STATUS :: SCRUB_BUSY [01:01] */ #define BCHP_SCRUB_CTRL_SCRUB_STATUS_SCRUB_BUSY_MASK 0x00000002 #define BCHP_SCRUB_CTRL_SCRUB_STATUS_SCRUB_BUSY_SHIFT 1 /* SCRUB_CTRL :: SCRUB_STATUS :: SCRAM_KEY_BUSY [00:00] */ #define BCHP_SCRUB_CTRL_SCRUB_STATUS_SCRAM_KEY_BUSY_MASK 0x00000001 #define BCHP_SCRUB_CTRL_SCRUB_STATUS_SCRAM_KEY_BUSY_SHIFT 0 /*************************************************************************** *CR - CR Word Register ***************************************************************************/ /* SCRUB_CTRL :: CR :: CR_WORD [31:00] */ #define BCHP_SCRUB_CTRL_CR_CR_WORD_MASK 0xffffffff #define BCHP_SCRUB_CTRL_CR_CR_WORD_SHIFT 0 /*************************************************************************** *ECC_DONE - OTP ECC Done Register ***************************************************************************/ /* SCRUB_CTRL :: ECC_DONE :: ECC_STATUS [31:00] */ #define BCHP_SCRUB_CTRL_ECC_DONE_ECC_STATUS_MASK 0xffffffff #define BCHP_SCRUB_CTRL_ECC_DONE_ECC_STATUS_SHIFT 0 /*************************************************************************** *ECC_FAULT - OTP ECC Fault Register ***************************************************************************/ /* SCRUB_CTRL :: ECC_FAULT :: ECC_STATUS [31:00] */ #define BCHP_SCRUB_CTRL_ECC_FAULT_ECC_STATUS_MASK 0xffffffff #define BCHP_SCRUB_CTRL_ECC_FAULT_ECC_STATUS_SHIFT 0 /*************************************************************************** *ECC_FAIL - OTP ECC Fail Register ***************************************************************************/ /* SCRUB_CTRL :: ECC_FAIL :: ECC_STATUS [31:00] */ #define BCHP_SCRUB_CTRL_ECC_FAIL_ECC_STATUS_MASK 0xffffffff #define BCHP_SCRUB_CTRL_ECC_FAIL_ECC_STATUS_SHIFT 0 /*************************************************************************** *KEY0_31_0 - Key0 [31:0] ***************************************************************************/ /* SCRUB_CTRL :: KEY0_31_0 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY0_31_0_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY0_31_0_KEY_SHIFT 0 /*************************************************************************** *KEY0_63_32 - Key0 [63:32] ***************************************************************************/ /* SCRUB_CTRL :: KEY0_63_32 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY0_63_32_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY0_63_32_KEY_SHIFT 0 /*************************************************************************** *KEY0_95_64 - Key0 [95:64] ***************************************************************************/ /* SCRUB_CTRL :: KEY0_95_64 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY0_95_64_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY0_95_64_KEY_SHIFT 0 /*************************************************************************** *KEY0_127_96 - Key0 [127:96] ***************************************************************************/ /* SCRUB_CTRL :: KEY0_127_96 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY0_127_96_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY0_127_96_KEY_SHIFT 0 /*************************************************************************** *KEY0_PS_31_0 - Key0 Post scramble [31:0] ***************************************************************************/ /* SCRUB_CTRL :: KEY0_PS_31_0 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY0_PS_31_0_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY0_PS_31_0_KEY_SHIFT 0 /*************************************************************************** *KEY0_PS_63_32 - Key0 Post scramble [63:32] ***************************************************************************/ /* SCRUB_CTRL :: KEY0_PS_63_32 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY0_PS_63_32_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY0_PS_63_32_KEY_SHIFT 0 /*************************************************************************** *KEY0_PS_95_64 - Key0 Post scramble [95:64] ***************************************************************************/ /* SCRUB_CTRL :: KEY0_PS_95_64 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY0_PS_95_64_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY0_PS_95_64_KEY_SHIFT 0 /*************************************************************************** *KEY0_PS_127_96 - Key0 Post scramble [127:96] ***************************************************************************/ /* SCRUB_CTRL :: KEY0_PS_127_96 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY0_PS_127_96_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY0_PS_127_96_KEY_SHIFT 0 /*************************************************************************** *KEY1_31_0 - Key1 [31:0] ***************************************************************************/ /* SCRUB_CTRL :: KEY1_31_0 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY1_31_0_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY1_31_0_KEY_SHIFT 0 /*************************************************************************** *KEY1_63_32 - Key1 [63:32] ***************************************************************************/ /* SCRUB_CTRL :: KEY1_63_32 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY1_63_32_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY1_63_32_KEY_SHIFT 0 /*************************************************************************** *KEY1_95_64 - Key1 [95:64] ***************************************************************************/ /* SCRUB_CTRL :: KEY1_95_64 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY1_95_64_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY1_95_64_KEY_SHIFT 0 /*************************************************************************** *KEY1_127_96 - Key1 [127:96] ***************************************************************************/ /* SCRUB_CTRL :: KEY1_127_96 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY1_127_96_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY1_127_96_KEY_SHIFT 0 /*************************************************************************** *KEY1_PS_31_0 - Key1 Post scramble [31:0] ***************************************************************************/ /* SCRUB_CTRL :: KEY1_PS_31_0 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY1_PS_31_0_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY1_PS_31_0_KEY_SHIFT 0 /*************************************************************************** *KEY1_PS_63_32 - Key1 Post scramble [63:32] ***************************************************************************/ /* SCRUB_CTRL :: KEY1_PS_63_32 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY1_PS_63_32_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY1_PS_63_32_KEY_SHIFT 0 /*************************************************************************** *KEY1_PS_95_64 - Key1 Post scramble [95:64] ***************************************************************************/ /* SCRUB_CTRL :: KEY1_PS_95_64 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY1_PS_95_64_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY1_PS_95_64_KEY_SHIFT 0 /*************************************************************************** *KEY1_PS_127_96 - Key1 Post scramble [127:96] ***************************************************************************/ /* SCRUB_CTRL :: KEY1_PS_127_96 :: KEY [31:00] */ #define BCHP_SCRUB_CTRL_KEY1_PS_127_96_KEY_MASK 0xffffffff #define BCHP_SCRUB_CTRL_KEY1_PS_127_96_KEY_SHIFT 0 #endif /* #ifndef BCHP_SCRUB_CTRL_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015600000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_spre_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000001543711610313111030773 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_spre_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:06p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:47 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_spre_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:06p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_SPRE_0_H__ #define BCHP_DECODE_SPRE_0_H__ /*************************************************************************** *DECODE_SPRE_0 ***************************************************************************/ #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL 0x00800320 /* Spatial Prediction Control */ #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE 0x00800324 /* Spatial Prediction Luma Mode */ #define BCHP_DECODE_SPRE_0_REG_SPRE_END 0x0080033c /* REG_SPRE_END */ /*************************************************************************** *REG_SPRE_CTL - Spatial Prediction Control ***************************************************************************/ /* DECODE_SPRE_0 :: REG_SPRE_CTL :: reserved0 [31:18] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_reserved0_MASK 0xfffc0000 #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_reserved0_SHIFT 18 /* DECODE_SPRE_0 :: REG_SPRE_CTL :: CluMode [17:16] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_CluMode_MASK 0x00030000 #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_CluMode_SHIFT 16 /* DECODE_SPRE_0 :: REG_SPRE_CTL :: reserved1 [15:10] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_reserved1_MASK 0x0000fc00 #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_reserved1_SHIFT 10 /* DECODE_SPRE_0 :: REG_SPRE_CTL :: PredType [09:08] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_PredType_MASK 0x00000300 #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_PredType_SHIFT 8 /* DECODE_SPRE_0 :: REG_SPRE_CTL :: reserved2 [07:05] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_reserved2_MASK 0x000000e0 #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_reserved2_SHIFT 5 /* DECODE_SPRE_0 :: REG_SPRE_CTL :: CNST_INTRA [04:04] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_CNST_INTRA_MASK 0x00000010 #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_CNST_INTRA_SHIFT 4 /* DECODE_SPRE_0 :: REG_SPRE_CTL :: Ulft [03:03] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Ulft_MASK 0x00000008 #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Ulft_SHIFT 3 /* DECODE_SPRE_0 :: REG_SPRE_CTL :: Top [02:02] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Top_MASK 0x00000004 #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Top_SHIFT 2 /* DECODE_SPRE_0 :: REG_SPRE_CTL :: Left [01:01] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Left_MASK 0x00000002 #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Left_SHIFT 1 /* DECODE_SPRE_0 :: REG_SPRE_CTL :: Urt [00:00] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Urt_MASK 0x00000001 #define BCHP_DECODE_SPRE_0_REG_SPRE_CTL_Urt_SHIFT 0 /*************************************************************************** *REG_SPRE_MODE - Spatial Prediction Luma Mode ***************************************************************************/ /* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode7 [31:28] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode7_MASK 0xf0000000 #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode7_SHIFT 28 /* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode6 [27:24] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode6_MASK 0x0f000000 #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode6_SHIFT 24 /* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode5 [23:20] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode5_MASK 0x00f00000 #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode5_SHIFT 20 /* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode4 [19:16] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode4_MASK 0x000f0000 #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode4_SHIFT 16 /* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode3 [15:12] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode3_MASK 0x0000f000 #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode3_SHIFT 12 /* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode2 [11:08] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode2_MASK 0x00000f00 #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode2_SHIFT 8 /* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode1 [07:04] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode1_MASK 0x000000f0 #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode1_SHIFT 4 /* DECODE_SPRE_0 :: REG_SPRE_MODE :: Mode0 [03:00] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode0_MASK 0x0000000f #define BCHP_DECODE_SPRE_0_REG_SPRE_MODE_Mode0_SHIFT 0 /*************************************************************************** *REG_SPRE_END - REG_SPRE_END ***************************************************************************/ /* DECODE_SPRE_0 :: REG_SPRE_END :: reserved0 [31:00] */ #define BCHP_DECODE_SPRE_0_REG_SPRE_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_SPRE_0_REG_SPRE_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_SPRE_0_H__ */ /* End of File */ crystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_csc.h0000644000175000017500000002567411610313111030552 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_csc.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:58p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:17 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_csc.h $ * * Hydra_Software_Devel/1 7/17/09 7:58p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_CSC_H__ #define BCHP_CSC_H__ /*************************************************************************** *CSC - Color Space Converter Registers ***************************************************************************/ #define BCHP_CSC_CSC_CTRL 0x00541000 /* Color Matrix Control */ #define BCHP_CSC_CSC_COEFF_C00 0x00541010 /* Color Matrix coefficients c00 */ #define BCHP_CSC_CSC_COEFF_C01 0x00541014 /* Color Matrix coefficients c01 */ #define BCHP_CSC_CSC_COEFF_C02 0x00541018 /* Color Matrix coefficients c02 */ #define BCHP_CSC_CSC_COEFF_C03 0x0054101c /* Color Matrix coefficients c03 */ #define BCHP_CSC_CSC_COEFF_C10 0x00541020 /* Color Matrix coefficients c10 */ #define BCHP_CSC_CSC_COEFF_C11 0x00541024 /* Color Matrix coefficients c11 */ #define BCHP_CSC_CSC_COEFF_C12 0x00541028 /* Color Matrix coefficients c12 */ #define BCHP_CSC_CSC_COEFF_C13 0x0054102c /* Color Matrix coefficients c13 */ #define BCHP_CSC_CSC_COEFF_C20 0x00541030 /* Color Matrix coefficients c20 */ #define BCHP_CSC_CSC_COEFF_C21 0x00541034 /* Color Matrix coefficients c21 */ #define BCHP_CSC_CSC_COEFF_C22 0x00541038 /* Color Matrix coefficients c22 */ #define BCHP_CSC_CSC_COEFF_C23 0x0054103c /* Color Matrix coefficients c23 */ /*************************************************************************** *CSC_CTRL - Color Matrix Control ***************************************************************************/ /* CSC :: CSC_CTRL :: reserved0 [31:01] */ #define BCHP_CSC_CSC_CTRL_reserved0_MASK 0xfffffffe #define BCHP_CSC_CSC_CTRL_reserved0_SHIFT 1 /* CSC :: CSC_CTRL :: CSC_ENABLE [00:00] */ #define BCHP_CSC_CSC_CTRL_CSC_ENABLE_MASK 0x00000001 #define BCHP_CSC_CSC_CTRL_CSC_ENABLE_SHIFT 0 /*************************************************************************** *CSC_COEFF_C00 - Color Matrix coefficients c00 ***************************************************************************/ /* CSC :: CSC_COEFF_C00 :: reserved0 [31:16] */ #define BCHP_CSC_CSC_COEFF_C00_reserved0_MASK 0xffff0000 #define BCHP_CSC_CSC_COEFF_C00_reserved0_SHIFT 16 /* CSC :: CSC_COEFF_C00 :: COEFF_MUL [15:00] */ #define BCHP_CSC_CSC_COEFF_C00_COEFF_MUL_MASK 0x0000ffff #define BCHP_CSC_CSC_COEFF_C00_COEFF_MUL_SHIFT 0 /*************************************************************************** *CSC_COEFF_C01 - Color Matrix coefficients c01 ***************************************************************************/ /* CSC :: CSC_COEFF_C01 :: reserved0 [31:16] */ #define BCHP_CSC_CSC_COEFF_C01_reserved0_MASK 0xffff0000 #define BCHP_CSC_CSC_COEFF_C01_reserved0_SHIFT 16 /* CSC :: CSC_COEFF_C01 :: COEFF_MUL [15:00] */ #define BCHP_CSC_CSC_COEFF_C01_COEFF_MUL_MASK 0x0000ffff #define BCHP_CSC_CSC_COEFF_C01_COEFF_MUL_SHIFT 0 /*************************************************************************** *CSC_COEFF_C02 - Color Matrix coefficients c02 ***************************************************************************/ /* CSC :: CSC_COEFF_C02 :: reserved0 [31:16] */ #define BCHP_CSC_CSC_COEFF_C02_reserved0_MASK 0xffff0000 #define BCHP_CSC_CSC_COEFF_C02_reserved0_SHIFT 16 /* CSC :: CSC_COEFF_C02 :: COEFF_MUL [15:00] */ #define BCHP_CSC_CSC_COEFF_C02_COEFF_MUL_MASK 0x0000ffff #define BCHP_CSC_CSC_COEFF_C02_COEFF_MUL_SHIFT 0 /*************************************************************************** *CSC_COEFF_C03 - Color Matrix coefficients c03 ***************************************************************************/ /* CSC :: CSC_COEFF_C03 :: reserved0 [31:16] */ #define BCHP_CSC_CSC_COEFF_C03_reserved0_MASK 0xffff0000 #define BCHP_CSC_CSC_COEFF_C03_reserved0_SHIFT 16 /* CSC :: CSC_COEFF_C03 :: COEFF_ADD [15:00] */ #define BCHP_CSC_CSC_COEFF_C03_COEFF_ADD_MASK 0x0000ffff #define BCHP_CSC_CSC_COEFF_C03_COEFF_ADD_SHIFT 0 /*************************************************************************** *CSC_COEFF_C10 - Color Matrix coefficients c10 ***************************************************************************/ /* CSC :: CSC_COEFF_C10 :: reserved0 [31:16] */ #define BCHP_CSC_CSC_COEFF_C10_reserved0_MASK 0xffff0000 #define BCHP_CSC_CSC_COEFF_C10_reserved0_SHIFT 16 /* CSC :: CSC_COEFF_C10 :: COEFF_MUL [15:00] */ #define BCHP_CSC_CSC_COEFF_C10_COEFF_MUL_MASK 0x0000ffff #define BCHP_CSC_CSC_COEFF_C10_COEFF_MUL_SHIFT 0 /*************************************************************************** *CSC_COEFF_C11 - Color Matrix coefficients c11 ***************************************************************************/ /* CSC :: CSC_COEFF_C11 :: reserved0 [31:16] */ #define BCHP_CSC_CSC_COEFF_C11_reserved0_MASK 0xffff0000 #define BCHP_CSC_CSC_COEFF_C11_reserved0_SHIFT 16 /* CSC :: CSC_COEFF_C11 :: COEFF_MUL [15:00] */ #define BCHP_CSC_CSC_COEFF_C11_COEFF_MUL_MASK 0x0000ffff #define BCHP_CSC_CSC_COEFF_C11_COEFF_MUL_SHIFT 0 /*************************************************************************** *CSC_COEFF_C12 - Color Matrix coefficients c12 ***************************************************************************/ /* CSC :: CSC_COEFF_C12 :: reserved0 [31:16] */ #define BCHP_CSC_CSC_COEFF_C12_reserved0_MASK 0xffff0000 #define BCHP_CSC_CSC_COEFF_C12_reserved0_SHIFT 16 /* CSC :: CSC_COEFF_C12 :: COEFF_MUL [15:00] */ #define BCHP_CSC_CSC_COEFF_C12_COEFF_MUL_MASK 0x0000ffff #define BCHP_CSC_CSC_COEFF_C12_COEFF_MUL_SHIFT 0 /*************************************************************************** *CSC_COEFF_C13 - Color Matrix coefficients c13 ***************************************************************************/ /* CSC :: CSC_COEFF_C13 :: reserved0 [31:16] */ #define BCHP_CSC_CSC_COEFF_C13_reserved0_MASK 0xffff0000 #define BCHP_CSC_CSC_COEFF_C13_reserved0_SHIFT 16 /* CSC :: CSC_COEFF_C13 :: COEFF_ADD [15:00] */ #define BCHP_CSC_CSC_COEFF_C13_COEFF_ADD_MASK 0x0000ffff #define BCHP_CSC_CSC_COEFF_C13_COEFF_ADD_SHIFT 0 /*************************************************************************** *CSC_COEFF_C20 - Color Matrix coefficients c20 ***************************************************************************/ /* CSC :: CSC_COEFF_C20 :: reserved0 [31:16] */ #define BCHP_CSC_CSC_COEFF_C20_reserved0_MASK 0xffff0000 #define BCHP_CSC_CSC_COEFF_C20_reserved0_SHIFT 16 /* CSC :: CSC_COEFF_C20 :: COEFF_MUL [15:00] */ #define BCHP_CSC_CSC_COEFF_C20_COEFF_MUL_MASK 0x0000ffff #define BCHP_CSC_CSC_COEFF_C20_COEFF_MUL_SHIFT 0 /*************************************************************************** *CSC_COEFF_C21 - Color Matrix coefficients c21 ***************************************************************************/ /* CSC :: CSC_COEFF_C21 :: reserved0 [31:16] */ #define BCHP_CSC_CSC_COEFF_C21_reserved0_MASK 0xffff0000 #define BCHP_CSC_CSC_COEFF_C21_reserved0_SHIFT 16 /* CSC :: CSC_COEFF_C21 :: COEFF_MUL [15:00] */ #define BCHP_CSC_CSC_COEFF_C21_COEFF_MUL_MASK 0x0000ffff #define BCHP_CSC_CSC_COEFF_C21_COEFF_MUL_SHIFT 0 /*************************************************************************** *CSC_COEFF_C22 - Color Matrix coefficients c22 ***************************************************************************/ /* CSC :: CSC_COEFF_C22 :: reserved0 [31:16] */ #define BCHP_CSC_CSC_COEFF_C22_reserved0_MASK 0xffff0000 #define BCHP_CSC_CSC_COEFF_C22_reserved0_SHIFT 16 /* CSC :: CSC_COEFF_C22 :: COEFF_MUL [15:00] */ #define BCHP_CSC_CSC_COEFF_C22_COEFF_MUL_MASK 0x0000ffff #define BCHP_CSC_CSC_COEFF_C22_COEFF_MUL_SHIFT 0 /*************************************************************************** *CSC_COEFF_C23 - Color Matrix coefficients c23 ***************************************************************************/ /* CSC :: CSC_COEFF_C23 :: reserved0 [31:16] */ #define BCHP_CSC_CSC_COEFF_C23_reserved0_MASK 0xffff0000 #define BCHP_CSC_CSC_COEFF_C23_reserved0_SHIFT 16 /* CSC :: CSC_COEFF_C23 :: COEFF_ADD [15:00] */ #define BCHP_CSC_CSC_COEFF_C23_COEFF_ADD_MASK 0x0000ffff #define BCHP_CSC_CSC_COEFF_C23_COEFF_ADD_SHIFT 0 #endif /* #ifndef BCHP_CSC_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015700000000000011570 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc_gr_bridge.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc_g0000644000175000017500000001314311610313111031001 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_misc_gr_bridge.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:12p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:46 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc_gr_bridge.h $ * * Hydra_Software_Devel/1 7/17/09 8:12p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_MISC_GR_BRIDGE_H__ #define BCHP_MISC_GR_BRIDGE_H__ /*************************************************************************** *MISC_GR_BRIDGE - MISC's GR-Bridge related registers ***************************************************************************/ #define BCHP_MISC_GR_BRIDGE_REVISION 0x005023e0 /* GR Bridge Revision */ #define BCHP_MISC_GR_BRIDGE_CTRL 0x005023e4 /* GR Bridge Control Register */ #define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_0 0x005023e8 /* GR Bridge Software Reset 0 Register */ #define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_1 0x005023ec /* GR Bridge Software Reset 1 Register */ /*************************************************************************** *REVISION - GR Bridge Revision ***************************************************************************/ /* MISC_GR_BRIDGE :: REVISION :: reserved0 [31:16] */ #define BCHP_MISC_GR_BRIDGE_REVISION_reserved0_MASK 0xffff0000 #define BCHP_MISC_GR_BRIDGE_REVISION_reserved0_SHIFT 16 /* MISC_GR_BRIDGE :: REVISION :: MAJOR [15:08] */ #define BCHP_MISC_GR_BRIDGE_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_MISC_GR_BRIDGE_REVISION_MAJOR_SHIFT 8 /* MISC_GR_BRIDGE :: REVISION :: MINOR [07:00] */ #define BCHP_MISC_GR_BRIDGE_REVISION_MINOR_MASK 0x000000ff #define BCHP_MISC_GR_BRIDGE_REVISION_MINOR_SHIFT 0 /*************************************************************************** *CTRL - GR Bridge Control Register ***************************************************************************/ /* MISC_GR_BRIDGE :: CTRL :: reserved0 [31:01] */ #define BCHP_MISC_GR_BRIDGE_CTRL_reserved0_MASK 0xfffffffe #define BCHP_MISC_GR_BRIDGE_CTRL_reserved0_SHIFT 1 /* MISC_GR_BRIDGE :: CTRL :: gisb_error_intr [00:00] */ #define BCHP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_MASK 0x00000001 #define BCHP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_SHIFT 0 #define BCHP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_DISABLE 0 #define BCHP_MISC_GR_BRIDGE_CTRL_gisb_error_intr_INTR_ENABLE 1 /*************************************************************************** *SPARE_SW_RESET_0 - GR Bridge Software Reset 0 Register ***************************************************************************/ /* MISC_GR_BRIDGE :: SPARE_SW_RESET_0 :: reserved0 [31:01] */ #define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_MASK 0xfffffffe #define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_0_reserved0_SHIFT 1 /* MISC_GR_BRIDGE :: SPARE_SW_RESET_0 :: SPARE_SW_RESET [00:00] */ #define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_MASK 0x00000001 #define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_SHIFT 0 #define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_DEASSERT 0 #define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_0_SPARE_SW_RESET_ASSERT 1 /*************************************************************************** *SPARE_SW_RESET_1 - GR Bridge Software Reset 1 Register ***************************************************************************/ /* MISC_GR_BRIDGE :: SPARE_SW_RESET_1 :: reserved0 [31:01] */ #define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_MASK 0xfffffffe #define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_1_reserved0_SHIFT 1 /* MISC_GR_BRIDGE :: SPARE_SW_RESET_1 :: SPARE_SW_RESET [00:00] */ #define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_MASK 0x00000001 #define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_SHIFT 0 #define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_DEASSERT 0 #define BCHP_MISC_GR_BRIDGE_SPARE_SW_RESET_1_SPARE_SW_RESET_ASSERT 1 #endif /* #ifndef BCHP_MISC_GR_BRIDGE_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016700000000000011571 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_control_regs.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_0000644000175000017500000007340611610313111030625 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_ddr23_phy_control_regs.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:59p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:21 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_control_regs.h $ * * Hydra_Software_Devel/1 7/17/09 7:59p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DDR23_PHY_CONTROL_REGS_H__ #define BCHP_DDR23_PHY_CONTROL_REGS_H__ /*************************************************************************** *DDR23_PHY_CONTROL_REGS - DDR23 DDR23 physical interface control registers ***************************************************************************/ #define BCHP_DDR23_PHY_CONTROL_REGS_REVISION 0x01801000 /* Address & Control revision register */ #define BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL 0x01801004 /* PHY clock power management control register */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS 0x01801010 /* PHY PLL status register */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG 0x01801014 /* PHY PLL configuration register */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER 0x01801018 /* PHY PLL pre-divider control register */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER 0x0180101c /* PHY PLL divider control register */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1 0x01801020 /* PHY PLL analog control register #1 */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2 0x01801024 /* PHY PLL analog control register #2 */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_EN 0x01801028 /* PHY PLL spread spectrum config register */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_CFG 0x0180102c /* PHY PLL spread spectrum config register */ #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE 0x01801030 /* Address & Control VDL static override control register */ #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE 0x01801034 /* Address & Control VDL dynamic override control register */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL 0x01801038 /* Idle mode SSTL pad control register */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL 0x0180103c /* PVT Compensation control and status register */ #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL 0x01801040 /* SSTL pad drive characteristics control register */ #define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL 0x01801044 /* Clock Regulator control register */ /*************************************************************************** *REVISION - Address & Control revision register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: REVISION :: reserved0 [31:16] */ #define BCHP_DDR23_PHY_CONTROL_REGS_REVISION_reserved0_MASK 0xffff0000 #define BCHP_DDR23_PHY_CONTROL_REGS_REVISION_reserved0_SHIFT 16 /* DDR23_PHY_CONTROL_REGS :: REVISION :: MAJOR [15:08] */ #define BCHP_DDR23_PHY_CONTROL_REGS_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_DDR23_PHY_CONTROL_REGS_REVISION_MAJOR_SHIFT 8 /* DDR23_PHY_CONTROL_REGS :: REVISION :: MINOR [07:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_REVISION_MINOR_MASK 0x000000ff #define BCHP_DDR23_PHY_CONTROL_REGS_REVISION_MINOR_SHIFT 0 /*************************************************************************** *CLK_PM_CTRL - PHY clock power management control register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: CLK_PM_CTRL :: reserved0 [31:01] */ #define BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_reserved0_MASK 0xfffffffe #define BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_reserved0_SHIFT 1 /* DDR23_PHY_CONTROL_REGS :: CLK_PM_CTRL :: DIS_DDR_CLK [00:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK 0x00000001 #define BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_SHIFT 0 /*************************************************************************** *PLL_STATUS - PHY PLL status register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: PLL_STATUS :: reserved0 [31:01] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS_reserved0_MASK 0xfffffffe #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS_reserved0_SHIFT 1 /* DDR23_PHY_CONTROL_REGS :: PLL_STATUS :: LOCK [00:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS_LOCK_MASK 0x00000001 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS_LOCK_SHIFT 0 /*************************************************************************** *PLL_CONFIG - PHY PLL configuration register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: DIV2_CLK_RESET [31:31] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_DIV2_CLK_RESET_MASK 0x80000000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_DIV2_CLK_RESET_SHIFT 31 /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved0 [30:22] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_MASK 0x7fc00000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_reserved0_SHIFT 22 /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: TEST_SEL [21:17] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_TEST_SEL_MASK 0x003e0000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_TEST_SEL_SHIFT 17 /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: TEST_EN [16:16] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_TEST_EN_MASK 0x00010000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_TEST_EN_SHIFT 16 /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: BGAP_ADJ [15:12] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_BGAP_ADJ_MASK 0x0000f000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_BGAP_ADJ_SHIFT 12 /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved1 [11:08] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_reserved1_MASK 0x00000f00 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_reserved1_SHIFT 8 /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: VCO_RNG [07:07] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_VCO_RNG_MASK 0x00000080 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_VCO_RNG_SHIFT 7 /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: PWRDN_CH1 [06:06] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_CH1_MASK 0x00000040 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_CH1_SHIFT 6 /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: BYPEN [05:05] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_BYPEN_MASK 0x00000020 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_BYPEN_SHIFT 5 /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: ENB_CLKOUT [04:04] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_ENB_CLKOUT_MASK 0x00000010 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_ENB_CLKOUT_SHIFT 4 /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: DRESET [03:03] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_DRESET_MASK 0x00000008 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_DRESET_SHIFT 3 /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: ARESET [02:02] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_ARESET_MASK 0x00000004 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_ARESET_SHIFT 2 /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: reserved2 [01:01] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_reserved2_MASK 0x00000002 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_reserved2_SHIFT 1 /* DDR23_PHY_CONTROL_REGS :: PLL_CONFIG :: PWRDN [00:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK 0x00000001 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_SHIFT 0 /*************************************************************************** *PLL_PRE_DIVIDER - PHY PLL pre-divider control register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: reserved0 [31:27] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_reserved0_MASK 0xf8000000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_reserved0_SHIFT 27 /* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: NDIV_DITHER_MFB [26:26] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_DITHER_MFB_MASK 0x04000000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_DITHER_MFB_SHIFT 26 /* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: NDIV_PWRDN [25:25] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_PWRDN_MASK 0x02000000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_PWRDN_SHIFT 25 /* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: reserved1 [24:23] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_reserved1_MASK 0x01800000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_reserved1_SHIFT 23 /* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: NDIV_MODE [22:20] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_MODE_MASK 0x00700000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_MODE_SHIFT 20 /* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: reserved2 [19:17] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_reserved2_MASK 0x000e0000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_reserved2_SHIFT 17 /* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: NDIV_INT [16:08] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_INT_MASK 0x0001ff00 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_NDIV_INT_SHIFT 8 /* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: P2DIV [07:04] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_P2DIV_MASK 0x000000f0 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_P2DIV_SHIFT 4 /* DDR23_PHY_CONTROL_REGS :: PLL_PRE_DIVIDER :: P1DIV [03:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_P1DIV_MASK 0x0000000f #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER_P1DIV_SHIFT 0 /*************************************************************************** *PLL_DIVIDER - PHY PLL divider control register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: PLL_DIVIDER :: M1DIV [31:24] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER_M1DIV_MASK 0xff000000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER_M1DIV_SHIFT 24 /* DDR23_PHY_CONTROL_REGS :: PLL_DIVIDER :: NDIV_FRAC [23:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER_NDIV_FRAC_MASK 0x00ffffff #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER_NDIV_FRAC_SHIFT 0 /*************************************************************************** *PLL_CONTROL1 - PHY PLL analog control register #1 ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: TESTA_SEL [31:30] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_TESTA_SEL_MASK 0xc0000000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_TESTA_SEL_SHIFT 30 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: KVCO_XS [29:27] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_KVCO_XS_MASK 0x38000000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_KVCO_XS_SHIFT 27 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: KVCO_XF [26:24] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_KVCO_XF_MASK 0x07000000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_KVCO_XF_SHIFT 24 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: LPF_BW [23:22] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_LPF_BW_MASK 0x00c00000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_LPF_BW_SHIFT 22 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: LF_ORDER [21:21] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_LF_ORDER_MASK 0x00200000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_LF_ORDER_SHIFT 21 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: CN [20:19] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_CN_MASK 0x00180000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_CN_SHIFT 19 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: RN [18:17] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_RN_MASK 0x00060000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_RN_SHIFT 17 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: CP [16:15] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_CP_MASK 0x00018000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_CP_SHIFT 15 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: CZ [14:13] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_CZ_MASK 0x00006000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_CZ_SHIFT 13 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: RZ [12:10] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_RZ_MASK 0x00001c00 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_RZ_SHIFT 10 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: ICPX [09:05] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_ICPX_MASK 0x000003e0 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_ICPX_SHIFT 5 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL1 :: ICP_OFF [04:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_ICP_OFF_MASK 0x0000001f #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL1_ICP_OFF_SHIFT 0 /*************************************************************************** *PLL_CONTROL2 - PHY PLL analog control register #2 ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL2 :: reserved0 [31:06] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_reserved0_MASK 0xffffffc0 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_reserved0_SHIFT 6 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL2 :: PTAP_ADJ [05:04] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_PTAP_ADJ_MASK 0x00000030 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_PTAP_ADJ_SHIFT 4 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL2 :: CTAP_ADJ [03:02] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_CTAP_ADJ_MASK 0x0000000c #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_CTAP_ADJ_SHIFT 2 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL2 :: LOWCUR_EN [01:01] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_LOWCUR_EN_MASK 0x00000002 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_LOWCUR_EN_SHIFT 1 /* DDR23_PHY_CONTROL_REGS :: PLL_CONTROL2 :: BIASIN_EN [00:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_BIASIN_EN_MASK 0x00000001 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONTROL2_BIASIN_EN_SHIFT 0 /*************************************************************************** *PLL_SS_EN - PHY PLL spread spectrum config register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: PLL_SS_EN :: reserved0 [31:01] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_EN_reserved0_MASK 0xfffffffe #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_EN_reserved0_SHIFT 1 /* DDR23_PHY_CONTROL_REGS :: PLL_SS_EN :: SS_EN [00:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_EN_SS_EN_MASK 0x00000001 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_EN_SS_EN_SHIFT 0 /*************************************************************************** *PLL_SS_CFG - PHY PLL spread spectrum config register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: PLL_SS_CFG :: REF_CYC_PER_TICK [31:16] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_CFG_REF_CYC_PER_TICK_MASK 0xffff0000 #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_CFG_REF_CYC_PER_TICK_SHIFT 16 /* DDR23_PHY_CONTROL_REGS :: PLL_SS_CFG :: NDIV_AMP [15:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_CFG_NDIV_AMP_MASK 0x0000ffff #define BCHP_DDR23_PHY_CONTROL_REGS_PLL_SS_CFG_NDIV_AMP_SHIFT 0 /*************************************************************************** *STATIC_VDL_OVERRIDE - Address & Control VDL static override control register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: reserved0 [31:21] */ #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved0_MASK 0xffe00000 #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved0_SHIFT 21 /* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: ovr_force [20:20] */ #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_force_MASK 0x00100000 #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_force_SHIFT 20 /* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: reserved1 [19:17] */ #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved1_MASK 0x000e0000 #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved1_SHIFT 17 /* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_en_SHIFT 16 /* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: reserved2 [15:14] */ #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved2_MASK 0x0000c000 #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved2_SHIFT 14 /* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: reserved3 [11:10] */ #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved3_MASK 0x00000c00 #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved3_SHIFT 10 /* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: reserved4 [07:06] */ #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved4_MASK 0x000000c0 #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_reserved4_SHIFT 6 /* DDR23_PHY_CONTROL_REGS :: STATIC_VDL_OVERRIDE :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE_ovr_step_SHIFT 0 /*************************************************************************** *DYNAMIC_VDL_OVERRIDE - Address & Control VDL dynamic override control register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved0_SHIFT 17 /* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_en_SHIFT 16 /* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved1_SHIFT 14 /* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved2_SHIFT 10 /* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_reserved3_SHIFT 6 /* DDR23_PHY_CONTROL_REGS :: DYNAMIC_VDL_OVERRIDE :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_CONTROL_REGS_DYNAMIC_VDL_OVERRIDE_ovr_step_SHIFT 0 /*************************************************************************** *IDLE_PAD_CONTROL - Idle mode SSTL pad control register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: idle [31:31] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_MASK 0x80000000 #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_SHIFT 31 /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved0 [30:09] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_MASK 0x7ffffe00 #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved0_SHIFT 9 /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: rxenb [08:08] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_rxenb_MASK 0x00000100 #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_rxenb_SHIFT 8 /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved1 [07:07] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved1_MASK 0x00000080 #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved1_SHIFT 7 /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: ctl_iddq [06:06] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_MASK 0x00000040 #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_SHIFT 6 /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: ctl_reb [05:05] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_reb_MASK 0x00000020 #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_reb_SHIFT 5 /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: ctl_oeb [04:04] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_oeb_MASK 0x00000010 #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_oeb_SHIFT 4 /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: reserved2 [03:03] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved2_MASK 0x00000008 #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_reserved2_SHIFT 3 /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: cke_iddq [02:02] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_iddq_MASK 0x00000004 #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_iddq_SHIFT 2 /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: cke_reb [01:01] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_reb_MASK 0x00000002 #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_reb_SHIFT 1 /* DDR23_PHY_CONTROL_REGS :: IDLE_PAD_CONTROL :: cke_oeb [00:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_oeb_MASK 0x00000001 #define BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_oeb_SHIFT 0 /*************************************************************************** *ZQ_PVT_COMP_CTL - PVT Compensation control and status register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: reserved0 [31:31] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_reserved0_MASK 0x80000000 #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_reserved0_SHIFT 31 /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: pd_done [30:30] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_done_MASK 0x40000000 #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_done_SHIFT 30 /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: nd_done [29:29] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_done_MASK 0x20000000 #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_done_SHIFT 29 /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: sample_done [28:28] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_done_MASK 0x10000000 #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_done_SHIFT 28 /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: auto_sample_en [27:27] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_auto_sample_en_MASK 0x08000000 #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_auto_sample_en_SHIFT 27 /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: sample_en [26:26] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_en_MASK 0x04000000 #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_en_SHIFT 26 /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: addr_ovr_en [25:25] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_ovr_en_MASK 0x02000000 #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_ovr_en_SHIFT 25 /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: dq_ovr_en [24:24] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_ovr_en_MASK 0x01000000 #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_ovr_en_SHIFT 24 /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: pd_comp [23:20] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_comp_MASK 0x00f00000 #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_pd_comp_SHIFT 20 /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: nd_comp [19:16] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_comp_MASK 0x000f0000 #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_nd_comp_SHIFT 16 /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: addr_pd_override_val [15:12] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_pd_override_val_MASK 0x0000f000 #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_pd_override_val_SHIFT 12 /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: addr_nd_override_val [11:08] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_nd_override_val_MASK 0x00000f00 #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_addr_nd_override_val_SHIFT 8 /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: dq_pd_override_val [07:04] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_pd_override_val_MASK 0x000000f0 #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_pd_override_val_SHIFT 4 /* DDR23_PHY_CONTROL_REGS :: ZQ_PVT_COMP_CTL :: dq_nd_override_val [03:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_nd_override_val_MASK 0x0000000f #define BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_dq_nd_override_val_SHIFT 0 /*************************************************************************** *DRIVE_PAD_CTL - SSTL pad drive characteristics control register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: reserved0 [31:05] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_MASK 0xffffffe0 #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_reserved0_SHIFT 5 /* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: rt60b [04:04] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt60b_MASK 0x00000010 #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_rt60b_SHIFT 4 /* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_sel_sstl18_MASK 0x00000008 #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_sel_sstl18_SHIFT 3 /* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_seltxdrv_ci_MASK 0x00000004 #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_seltxdrv_ci_SHIFT 2 /* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: selrxdrv [01:01] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_selrxdrv_MASK 0x00000002 #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_selrxdrv_SHIFT 1 /* DDR23_PHY_CONTROL_REGS :: DRIVE_PAD_CTL :: slew [00:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_slew_MASK 0x00000001 #define BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL_slew_SHIFT 0 /*************************************************************************** *CLOCK_REG_CONTROL - Clock Regulator control register ***************************************************************************/ /* DDR23_PHY_CONTROL_REGS :: CLOCK_REG_CONTROL :: reserved0 [31:02] */ #define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_reserved0_MASK 0xfffffffc #define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_reserved0_SHIFT 2 /* DDR23_PHY_CONTROL_REGS :: CLOCK_REG_CONTROL :: half_power [01:01] */ #define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_half_power_MASK 0x00000002 #define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_half_power_SHIFT 1 /* DDR23_PHY_CONTROL_REGS :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ #define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_MASK 0x00000001 #define BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_SHIFT 0 #endif /* #ifndef BCHP_DDR23_PHY_CONTROL_REGS_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015500000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gi0000644000175000017500000030127611610313111031033 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_sun_gisb_arb.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:19p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:30 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb.h $ * * Hydra_Software_Devel/1 7/17/09 8:19p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_SUN_GISB_ARB_H__ #define BCHP_SUN_GISB_ARB_H__ /*************************************************************************** *SUN_GISB_ARB - GISB Arbiter registers ***************************************************************************/ #define BCHP_SUN_GISB_ARB_REVISION 0x00400000 /* GISB ARBITER REVISION */ #define BCHP_SUN_GISB_ARB_SCRATCH 0x00400004 /* GISB ARBITER Scratch Register */ #define BCHP_SUN_GISB_ARB_REQ_MASK 0x00400008 /* GISB ARBITER Master Request Mask Register */ #define BCHP_SUN_GISB_ARB_TIMER 0x0040000c /* GISB ARBITER Timer Value Register */ #define BCHP_SUN_GISB_ARB_BP_CTRL 0x00400010 /* GISB ARBITER Breakpoint Control Register */ #define BCHP_SUN_GISB_ARB_BP_CAP_CLR 0x00400014 /* GISB ARBITER Breakpoint Capture Clear Register */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_0 0x00400018 /* GISB ARBITER Breakpoint Start Address 0 Register */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_0 0x0040001c /* GISB ARBITER Breakpoint End Address 0 Register */ #define BCHP_SUN_GISB_ARB_BP_READ_0 0x00400020 /* GISB ARBITER Breakpoint Master Read Control 0 Register */ #define BCHP_SUN_GISB_ARB_BP_WRITE_0 0x00400024 /* GISB ARBITER Breakpoint Master Write Control 0 Register */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_0 0x00400028 /* GISB ARBITER Breakpoint Enable 0 Register */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_1 0x0040002c /* GISB ARBITER Breakpoint Start Address 1 Register */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_1 0x00400030 /* GISB ARBITER Breakpoint End Address 1 Register */ #define BCHP_SUN_GISB_ARB_BP_READ_1 0x00400034 /* GISB ARBITER Breakpoint Master Read Control 1 Register */ #define BCHP_SUN_GISB_ARB_BP_WRITE_1 0x00400038 /* GISB ARBITER Breakpoint Master Write Control 1 Register */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_1 0x0040003c /* GISB ARBITER Breakpoint Enable 1 Register */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_2 0x00400040 /* GISB ARBITER Breakpoint Start Address 2 Register */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_2 0x00400044 /* GISB ARBITER Breakpoint End Address 2 Register */ #define BCHP_SUN_GISB_ARB_BP_READ_2 0x00400048 /* GISB ARBITER Breakpoint Master Read Control 2 Register */ #define BCHP_SUN_GISB_ARB_BP_WRITE_2 0x0040004c /* GISB ARBITER Breakpoint Master Write Control 2 Register */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_2 0x00400050 /* GISB ARBITER Breakpoint Enable 2 Register */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_3 0x00400054 /* GISB ARBITER Breakpoint Start Address 3 Register */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_3 0x00400058 /* GISB ARBITER Breakpoint End Address 3 Register */ #define BCHP_SUN_GISB_ARB_BP_READ_3 0x0040005c /* GISB ARBITER Breakpoint Master Read Control 3 Register */ #define BCHP_SUN_GISB_ARB_BP_WRITE_3 0x00400060 /* GISB ARBITER Breakpoint Master Write Control 3 Register */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_3 0x00400064 /* GISB ARBITER Breakpoint Enable 3 Register */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_4 0x00400068 /* GISB ARBITER Breakpoint Start Address 4 Register */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_4 0x0040006c /* GISB ARBITER Breakpoint End Address 4 Register */ #define BCHP_SUN_GISB_ARB_BP_READ_4 0x00400070 /* GISB ARBITER Breakpoint Master Read Control 4 Register */ #define BCHP_SUN_GISB_ARB_BP_WRITE_4 0x00400074 /* GISB ARBITER Breakpoint Master Write Control 4 Register */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_4 0x00400078 /* GISB ARBITER Breakpoint Enable 4 Register */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_5 0x0040007c /* GISB ARBITER Breakpoint Start Address 5 Register */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_5 0x00400080 /* GISB ARBITER Breakpoint End Address 5 Register */ #define BCHP_SUN_GISB_ARB_BP_READ_5 0x00400084 /* GISB ARBITER Breakpoint Master Read Control 5 Register */ #define BCHP_SUN_GISB_ARB_BP_WRITE_5 0x00400088 /* GISB ARBITER Breakpoint Master Write Control 5 Register */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_5 0x0040008c /* GISB ARBITER Breakpoint Enable 5 Register */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_6 0x00400090 /* GISB ARBITER Breakpoint Start Address 6 Register */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_6 0x00400094 /* GISB ARBITER Breakpoint End Address 6 Register */ #define BCHP_SUN_GISB_ARB_BP_READ_6 0x00400098 /* GISB ARBITER Breakpoint Master Read Control 6 Register */ #define BCHP_SUN_GISB_ARB_BP_WRITE_6 0x0040009c /* GISB ARBITER Breakpoint Master Write Control 6 Register */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_6 0x004000a0 /* GISB ARBITER Breakpoint Enable 6 Register */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_7 0x004000a4 /* GISB ARBITER Breakpoint Start Address 7 Register */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_7 0x004000a8 /* GISB ARBITER Breakpoint End Address 7 Register */ #define BCHP_SUN_GISB_ARB_BP_READ_7 0x004000ac /* GISB ARBITER Breakpoint Master Read Control 7 Register */ #define BCHP_SUN_GISB_ARB_BP_WRITE_7 0x004000b0 /* GISB ARBITER Breakpoint Master Write Control 7 Register */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_7 0x004000b4 /* GISB ARBITER Breakpoint Enable 7 Register */ #define BCHP_SUN_GISB_ARB_BP_CAP_ADDR 0x004000b8 /* GISB ARBITER Breakpoint Capture Address Register */ #define BCHP_SUN_GISB_ARB_BP_CAP_DATA 0x004000bc /* GISB ARBITER Breakpoint Capture Data Register */ #define BCHP_SUN_GISB_ARB_BP_CAP_STATUS 0x004000c0 /* GISB ARBITER Breakpoint Capture Status Register */ #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER 0x004000c4 /* GISB ARBITER Breakpoint Capture GISB MASTER Register */ #define BCHP_SUN_GISB_ARB_ERR_CAP_CLR 0x004000c8 /* GISB ARBITER Error Capture Clear Register */ #define BCHP_SUN_GISB_ARB_ERR_CAP_ADDR 0x004000cc /* GISB ARBITER Error Capture Address Register */ #define BCHP_SUN_GISB_ARB_ERR_CAP_DATA 0x004000d0 /* GISB ARBITER Error Capture Data Register */ #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS 0x004000d4 /* GISB ARBITER Error Capture Status Register */ #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER 0x004000d8 /* GISB ARBITER Error Capture GISB MASTER Register */ /*************************************************************************** *REVISION - GISB ARBITER REVISION ***************************************************************************/ /* SUN_GISB_ARB :: REVISION :: reserved0 [31:16] */ #define BCHP_SUN_GISB_ARB_REVISION_reserved0_MASK 0xffff0000 #define BCHP_SUN_GISB_ARB_REVISION_reserved0_SHIFT 16 /* SUN_GISB_ARB :: REVISION :: MAJOR [15:08] */ #define BCHP_SUN_GISB_ARB_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_SUN_GISB_ARB_REVISION_MAJOR_SHIFT 8 /* SUN_GISB_ARB :: REVISION :: MINOR [07:00] */ #define BCHP_SUN_GISB_ARB_REVISION_MINOR_MASK 0x000000ff #define BCHP_SUN_GISB_ARB_REVISION_MINOR_SHIFT 0 /*************************************************************************** *SCRATCH - GISB ARBITER Scratch Register ***************************************************************************/ /* SUN_GISB_ARB :: SCRATCH :: scratch_bit [31:00] */ #define BCHP_SUN_GISB_ARB_SCRATCH_scratch_bit_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_SCRATCH_scratch_bit_SHIFT 0 /*************************************************************************** *REQ_MASK - GISB ARBITER Master Request Mask Register ***************************************************************************/ /* SUN_GISB_ARB :: REQ_MASK :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_REQ_MASK_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_REQ_MASK_reserved0_SHIFT 12 /* SUN_GISB_ARB :: REQ_MASK :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_REQ_MASK_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_REQ_MASK_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_REQ_MASK_trb_UNMASK 0 /* SUN_GISB_ARB :: REQ_MASK :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_REQ_MASK_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_REQ_MASK_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_REQ_MASK_jtag_UNMASK 0 /* SUN_GISB_ARB :: REQ_MASK :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_REQ_MASK_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_REQ_MASK_reserved1_SHIFT 8 /* SUN_GISB_ARB :: REQ_MASK :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_REQ_MASK_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_REQ_MASK_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_REQ_MASK_avd0_UNMASK 0 /* SUN_GISB_ARB :: REQ_MASK :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_REQ_MASK_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_REQ_MASK_reserved2_SHIFT 5 /* SUN_GISB_ARB :: REQ_MASK :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_REQ_MASK_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_REQ_MASK_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_REQ_MASK_bsp_UNMASK 0 /* SUN_GISB_ARB :: REQ_MASK :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_REQ_MASK_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_REQ_MASK_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_REQ_MASK_cce_UNMASK 0 /* SUN_GISB_ARB :: REQ_MASK :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_REQ_MASK_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_REQ_MASK_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_REQ_MASK_pcie_UNMASK 0 /* SUN_GISB_ARB :: REQ_MASK :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_REQ_MASK_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_REQ_MASK_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_REQ_MASK_arm_UNMASK 0 /* SUN_GISB_ARB :: REQ_MASK :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_REQ_MASK_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_REQ_MASK_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_REQ_MASK_ssp_UNMASK 0 /*************************************************************************** *TIMER - GISB ARBITER Timer Value Register ***************************************************************************/ /* SUN_GISB_ARB :: TIMER :: hi_count [31:16] */ #define BCHP_SUN_GISB_ARB_TIMER_hi_count_MASK 0xffff0000 #define BCHP_SUN_GISB_ARB_TIMER_hi_count_SHIFT 16 /* SUN_GISB_ARB :: TIMER :: lo_count [15:00] */ #define BCHP_SUN_GISB_ARB_TIMER_lo_count_MASK 0x0000ffff #define BCHP_SUN_GISB_ARB_TIMER_lo_count_SHIFT 0 /*************************************************************************** *BP_CTRL - GISB ARBITER Breakpoint Control Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_CTRL :: reserved0 [31:02] */ #define BCHP_SUN_GISB_ARB_BP_CTRL_reserved0_MASK 0xfffffffc #define BCHP_SUN_GISB_ARB_BP_CTRL_reserved0_SHIFT 2 /* SUN_GISB_ARB :: BP_CTRL :: breakpoint_tea [01:01] */ #define BCHP_SUN_GISB_ARB_BP_CTRL_breakpoint_tea_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_CTRL_breakpoint_tea_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_CTRL_breakpoint_tea_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_CTRL_breakpoint_tea_ENABLE 1 /* SUN_GISB_ARB :: BP_CTRL :: repeat_capture [00:00] */ #define BCHP_SUN_GISB_ARB_BP_CTRL_repeat_capture_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_CTRL_repeat_capture_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_CTRL_repeat_capture_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_CTRL_repeat_capture_ENABLE 1 /*************************************************************************** *BP_CAP_CLR - GISB ARBITER Breakpoint Capture Clear Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_CAP_CLR :: reserved0 [31:01] */ #define BCHP_SUN_GISB_ARB_BP_CAP_CLR_reserved0_MASK 0xfffffffe #define BCHP_SUN_GISB_ARB_BP_CAP_CLR_reserved0_SHIFT 1 /* SUN_GISB_ARB :: BP_CAP_CLR :: clear [00:00] */ #define BCHP_SUN_GISB_ARB_BP_CAP_CLR_clear_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_CAP_CLR_clear_SHIFT 0 /*************************************************************************** *BP_START_ADDR_0 - GISB ARBITER Breakpoint Start Address 0 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_START_ADDR_0 :: start [31:00] */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_0_start_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_START_ADDR_0_start_SHIFT 0 /*************************************************************************** *BP_END_ADDR_0 - GISB ARBITER Breakpoint End Address 0 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_END_ADDR_0 :: end [31:00] */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_0_end_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_END_ADDR_0_end_SHIFT 0 /*************************************************************************** *BP_READ_0 - GISB ARBITER Breakpoint Master Read Control 0 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_READ_0 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_READ_0_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_READ_0_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_READ_0 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_READ_0_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_READ_0_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_READ_0_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_0_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_0 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_READ_0_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_READ_0_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_READ_0_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_0_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_0 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_READ_0_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_READ_0_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_READ_0 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_READ_0_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_READ_0_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_READ_0_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_0_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_0 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_READ_0_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_READ_0_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_READ_0 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_READ_0_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_READ_0_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_READ_0_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_0_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_0 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_READ_0_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_READ_0_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_READ_0_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_0_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_0 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_READ_0_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_READ_0_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_READ_0_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_0_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_0 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_READ_0_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_READ_0_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_READ_0_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_0_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_0 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_READ_0_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_READ_0_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_READ_0_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_0_ssp_ENABLE 1 /*************************************************************************** *BP_WRITE_0 - GISB ARBITER Breakpoint Master Write Control 0 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_WRITE_0 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_0_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_WRITE_0 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_0_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_0 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_0_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_0 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_0_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_WRITE_0 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_0_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_0 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_0_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_WRITE_0 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_0_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_0 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_0_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_0 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_0_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_0 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_0_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_0 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_0_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_0_ssp_ENABLE 1 /*************************************************************************** *BP_ENABLE_0 - GISB ARBITER Breakpoint Enable 0 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_ENABLE_0 :: reserved0 [31:03] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_0_reserved0_MASK 0xfffffff8 #define BCHP_SUN_GISB_ARB_BP_ENABLE_0_reserved0_SHIFT 3 /* SUN_GISB_ARB :: BP_ENABLE_0 :: block [02:02] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_0_block_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_ENABLE_0_block_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_ENABLE_0_block_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_0_block_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_0 :: address [01:01] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_0_address_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_ENABLE_0_address_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_ENABLE_0_address_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_0_address_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_0 :: access [00:00] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_0_access_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_ENABLE_0_access_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_0_access_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_0_access_ENABLE 1 /*************************************************************************** *BP_START_ADDR_1 - GISB ARBITER Breakpoint Start Address 1 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_START_ADDR_1 :: start [31:00] */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_1_start_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_START_ADDR_1_start_SHIFT 0 /*************************************************************************** *BP_END_ADDR_1 - GISB ARBITER Breakpoint End Address 1 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_END_ADDR_1 :: end [31:00] */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_1_end_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_END_ADDR_1_end_SHIFT 0 /*************************************************************************** *BP_READ_1 - GISB ARBITER Breakpoint Master Read Control 1 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_READ_1 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_READ_1_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_READ_1_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_READ_1 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_READ_1_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_READ_1_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_READ_1_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_1_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_1 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_READ_1_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_READ_1_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_READ_1_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_1_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_1 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_READ_1_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_READ_1_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_READ_1 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_READ_1_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_READ_1_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_READ_1_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_1_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_1 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_READ_1_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_READ_1_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_READ_1 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_READ_1_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_READ_1_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_READ_1_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_1_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_1 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_READ_1_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_READ_1_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_READ_1_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_1_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_1 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_READ_1_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_READ_1_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_READ_1_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_1_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_1 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_READ_1_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_READ_1_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_READ_1_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_1_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_1 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_READ_1_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_READ_1_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_READ_1_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_1_ssp_ENABLE 1 /*************************************************************************** *BP_WRITE_1 - GISB ARBITER Breakpoint Master Write Control 1 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_WRITE_1 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_1_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_WRITE_1 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_1_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_1 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_1_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_1 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_1_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_WRITE_1 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_1_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_1 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_1_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_WRITE_1 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_1_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_1 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_1_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_1 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_1_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_1 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_1_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_1 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_1_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_1_ssp_ENABLE 1 /*************************************************************************** *BP_ENABLE_1 - GISB ARBITER Breakpoint Enable 1 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_ENABLE_1 :: reserved0 [31:03] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_1_reserved0_MASK 0xfffffff8 #define BCHP_SUN_GISB_ARB_BP_ENABLE_1_reserved0_SHIFT 3 /* SUN_GISB_ARB :: BP_ENABLE_1 :: block [02:02] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_1_block_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_ENABLE_1_block_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_ENABLE_1_block_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_1_block_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_1 :: address [01:01] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_1_address_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_ENABLE_1_address_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_ENABLE_1_address_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_1_address_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_1 :: access [00:00] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_1_access_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_ENABLE_1_access_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_1_access_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_1_access_ENABLE 1 /*************************************************************************** *BP_START_ADDR_2 - GISB ARBITER Breakpoint Start Address 2 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_START_ADDR_2 :: start [31:00] */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_2_start_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_START_ADDR_2_start_SHIFT 0 /*************************************************************************** *BP_END_ADDR_2 - GISB ARBITER Breakpoint End Address 2 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_END_ADDR_2 :: end [31:00] */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_2_end_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_END_ADDR_2_end_SHIFT 0 /*************************************************************************** *BP_READ_2 - GISB ARBITER Breakpoint Master Read Control 2 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_READ_2 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_READ_2_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_READ_2_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_READ_2 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_READ_2_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_READ_2_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_READ_2_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_2_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_2 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_READ_2_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_READ_2_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_READ_2_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_2_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_2 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_READ_2_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_READ_2_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_READ_2 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_READ_2_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_READ_2_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_READ_2_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_2_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_2 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_READ_2_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_READ_2_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_READ_2 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_READ_2_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_READ_2_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_READ_2_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_2_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_2 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_READ_2_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_READ_2_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_READ_2_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_2_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_2 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_READ_2_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_READ_2_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_READ_2_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_2_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_2 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_READ_2_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_READ_2_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_READ_2_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_2_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_2 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_READ_2_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_READ_2_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_READ_2_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_2_ssp_ENABLE 1 /*************************************************************************** *BP_WRITE_2 - GISB ARBITER Breakpoint Master Write Control 2 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_WRITE_2 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_2_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_WRITE_2 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_2_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_2 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_2_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_2 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_2_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_WRITE_2 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_2_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_2 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_2_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_WRITE_2 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_2_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_2 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_2_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_2 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_2_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_2 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_2_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_2 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_2_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_2_ssp_ENABLE 1 /*************************************************************************** *BP_ENABLE_2 - GISB ARBITER Breakpoint Enable 2 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_ENABLE_2 :: reserved0 [31:03] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_2_reserved0_MASK 0xfffffff8 #define BCHP_SUN_GISB_ARB_BP_ENABLE_2_reserved0_SHIFT 3 /* SUN_GISB_ARB :: BP_ENABLE_2 :: block [02:02] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_2_block_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_ENABLE_2_block_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_ENABLE_2_block_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_2_block_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_2 :: address [01:01] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_2_address_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_ENABLE_2_address_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_ENABLE_2_address_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_2_address_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_2 :: access [00:00] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_2_access_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_ENABLE_2_access_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_2_access_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_2_access_ENABLE 1 /*************************************************************************** *BP_START_ADDR_3 - GISB ARBITER Breakpoint Start Address 3 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_START_ADDR_3 :: start [31:00] */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_3_start_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_START_ADDR_3_start_SHIFT 0 /*************************************************************************** *BP_END_ADDR_3 - GISB ARBITER Breakpoint End Address 3 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_END_ADDR_3 :: end [31:00] */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_3_end_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_END_ADDR_3_end_SHIFT 0 /*************************************************************************** *BP_READ_3 - GISB ARBITER Breakpoint Master Read Control 3 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_READ_3 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_READ_3_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_READ_3_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_READ_3 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_READ_3_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_READ_3_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_READ_3_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_3_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_3 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_READ_3_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_READ_3_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_READ_3_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_3_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_3 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_READ_3_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_READ_3_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_READ_3 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_READ_3_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_READ_3_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_READ_3_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_3_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_3 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_READ_3_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_READ_3_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_READ_3 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_READ_3_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_READ_3_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_READ_3_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_3_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_3 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_READ_3_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_READ_3_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_READ_3_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_3_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_3 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_READ_3_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_READ_3_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_READ_3_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_3_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_3 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_READ_3_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_READ_3_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_READ_3_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_3_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_3 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_READ_3_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_READ_3_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_READ_3_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_3_ssp_ENABLE 1 /*************************************************************************** *BP_WRITE_3 - GISB ARBITER Breakpoint Master Write Control 3 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_WRITE_3 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_3_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_WRITE_3 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_3_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_3 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_3_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_3 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_3_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_WRITE_3 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_3_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_3 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_3_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_WRITE_3 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_3_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_3 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_3_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_3 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_3_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_3 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_3_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_3 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_3_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_3_ssp_ENABLE 1 /*************************************************************************** *BP_ENABLE_3 - GISB ARBITER Breakpoint Enable 3 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_ENABLE_3 :: reserved0 [31:03] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_3_reserved0_MASK 0xfffffff8 #define BCHP_SUN_GISB_ARB_BP_ENABLE_3_reserved0_SHIFT 3 /* SUN_GISB_ARB :: BP_ENABLE_3 :: block [02:02] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_3_block_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_ENABLE_3_block_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_ENABLE_3_block_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_3_block_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_3 :: address [01:01] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_3_address_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_ENABLE_3_address_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_ENABLE_3_address_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_3_address_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_3 :: access [00:00] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_3_access_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_ENABLE_3_access_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_3_access_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_3_access_ENABLE 1 /*************************************************************************** *BP_START_ADDR_4 - GISB ARBITER Breakpoint Start Address 4 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_START_ADDR_4 :: start [31:00] */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_4_start_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_START_ADDR_4_start_SHIFT 0 /*************************************************************************** *BP_END_ADDR_4 - GISB ARBITER Breakpoint End Address 4 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_END_ADDR_4 :: end [31:00] */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_4_end_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_END_ADDR_4_end_SHIFT 0 /*************************************************************************** *BP_READ_4 - GISB ARBITER Breakpoint Master Read Control 4 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_READ_4 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_READ_4_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_READ_4_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_READ_4 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_READ_4_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_READ_4_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_READ_4_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_4_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_4 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_READ_4_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_READ_4_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_READ_4_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_4_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_4 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_READ_4_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_READ_4_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_READ_4 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_READ_4_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_READ_4_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_READ_4_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_4_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_4 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_READ_4_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_READ_4_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_READ_4 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_READ_4_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_READ_4_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_READ_4_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_4_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_4 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_READ_4_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_READ_4_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_READ_4_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_4_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_4 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_READ_4_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_READ_4_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_READ_4_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_4_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_4 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_READ_4_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_READ_4_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_READ_4_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_4_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_4 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_READ_4_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_READ_4_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_READ_4_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_4_ssp_ENABLE 1 /*************************************************************************** *BP_WRITE_4 - GISB ARBITER Breakpoint Master Write Control 4 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_WRITE_4 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_4_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_WRITE_4 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_4_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_4 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_4_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_4 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_4_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_WRITE_4 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_4_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_4 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_4_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_WRITE_4 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_4_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_4 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_4_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_4 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_4_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_4 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_4_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_4 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_4_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_4_ssp_ENABLE 1 /*************************************************************************** *BP_ENABLE_4 - GISB ARBITER Breakpoint Enable 4 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_ENABLE_4 :: reserved0 [31:03] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_4_reserved0_MASK 0xfffffff8 #define BCHP_SUN_GISB_ARB_BP_ENABLE_4_reserved0_SHIFT 3 /* SUN_GISB_ARB :: BP_ENABLE_4 :: block [02:02] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_4_block_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_ENABLE_4_block_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_ENABLE_4_block_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_4_block_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_4 :: address [01:01] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_4_address_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_ENABLE_4_address_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_ENABLE_4_address_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_4_address_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_4 :: access [00:00] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_4_access_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_ENABLE_4_access_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_4_access_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_4_access_ENABLE 1 /*************************************************************************** *BP_START_ADDR_5 - GISB ARBITER Breakpoint Start Address 5 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_START_ADDR_5 :: start [31:00] */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_5_start_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_START_ADDR_5_start_SHIFT 0 /*************************************************************************** *BP_END_ADDR_5 - GISB ARBITER Breakpoint End Address 5 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_END_ADDR_5 :: end [31:00] */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_5_end_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_END_ADDR_5_end_SHIFT 0 /*************************************************************************** *BP_READ_5 - GISB ARBITER Breakpoint Master Read Control 5 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_READ_5 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_READ_5_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_READ_5_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_READ_5 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_READ_5_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_READ_5_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_READ_5_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_5_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_5 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_READ_5_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_READ_5_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_READ_5_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_5_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_5 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_READ_5_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_READ_5_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_READ_5 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_READ_5_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_READ_5_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_READ_5_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_5_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_5 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_READ_5_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_READ_5_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_READ_5 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_READ_5_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_READ_5_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_READ_5_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_5_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_5 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_READ_5_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_READ_5_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_READ_5_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_5_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_5 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_READ_5_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_READ_5_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_READ_5_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_5_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_5 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_READ_5_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_READ_5_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_READ_5_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_5_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_5 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_READ_5_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_READ_5_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_READ_5_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_5_ssp_ENABLE 1 /*************************************************************************** *BP_WRITE_5 - GISB ARBITER Breakpoint Master Write Control 5 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_WRITE_5 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_5_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_WRITE_5 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_5_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_5 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_5_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_5 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_5_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_WRITE_5 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_5_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_5 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_5_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_WRITE_5 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_5_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_5 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_5_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_5 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_5_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_5 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_5_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_5 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_5_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_5_ssp_ENABLE 1 /*************************************************************************** *BP_ENABLE_5 - GISB ARBITER Breakpoint Enable 5 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_ENABLE_5 :: reserved0 [31:03] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_5_reserved0_MASK 0xfffffff8 #define BCHP_SUN_GISB_ARB_BP_ENABLE_5_reserved0_SHIFT 3 /* SUN_GISB_ARB :: BP_ENABLE_5 :: block [02:02] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_5_block_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_ENABLE_5_block_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_ENABLE_5_block_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_5_block_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_5 :: address [01:01] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_5_address_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_ENABLE_5_address_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_ENABLE_5_address_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_5_address_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_5 :: access [00:00] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_5_access_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_ENABLE_5_access_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_5_access_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_5_access_ENABLE 1 /*************************************************************************** *BP_START_ADDR_6 - GISB ARBITER Breakpoint Start Address 6 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_START_ADDR_6 :: start [31:00] */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_6_start_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_START_ADDR_6_start_SHIFT 0 /*************************************************************************** *BP_END_ADDR_6 - GISB ARBITER Breakpoint End Address 6 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_END_ADDR_6 :: end [31:00] */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_6_end_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_END_ADDR_6_end_SHIFT 0 /*************************************************************************** *BP_READ_6 - GISB ARBITER Breakpoint Master Read Control 6 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_READ_6 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_READ_6_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_READ_6_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_READ_6 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_READ_6_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_READ_6_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_READ_6_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_6_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_6 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_READ_6_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_READ_6_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_READ_6_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_6_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_6 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_READ_6_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_READ_6_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_READ_6 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_READ_6_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_READ_6_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_READ_6_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_6_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_6 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_READ_6_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_READ_6_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_READ_6 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_READ_6_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_READ_6_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_READ_6_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_6_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_6 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_READ_6_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_READ_6_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_READ_6_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_6_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_6 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_READ_6_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_READ_6_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_READ_6_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_6_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_6 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_READ_6_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_READ_6_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_READ_6_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_6_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_6 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_READ_6_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_READ_6_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_READ_6_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_6_ssp_ENABLE 1 /*************************************************************************** *BP_WRITE_6 - GISB ARBITER Breakpoint Master Write Control 6 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_WRITE_6 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_6_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_WRITE_6 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_6_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_6 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_6_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_6 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_6_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_WRITE_6 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_6_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_6 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_6_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_WRITE_6 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_6_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_6 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_6_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_6 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_6_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_6 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_6_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_6 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_6_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_6_ssp_ENABLE 1 /*************************************************************************** *BP_ENABLE_6 - GISB ARBITER Breakpoint Enable 6 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_ENABLE_6 :: reserved0 [31:03] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_6_reserved0_MASK 0xfffffff8 #define BCHP_SUN_GISB_ARB_BP_ENABLE_6_reserved0_SHIFT 3 /* SUN_GISB_ARB :: BP_ENABLE_6 :: block [02:02] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_6_block_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_ENABLE_6_block_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_ENABLE_6_block_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_6_block_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_6 :: address [01:01] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_6_address_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_ENABLE_6_address_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_ENABLE_6_address_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_6_address_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_6 :: access [00:00] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_6_access_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_ENABLE_6_access_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_6_access_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_6_access_ENABLE 1 /*************************************************************************** *BP_START_ADDR_7 - GISB ARBITER Breakpoint Start Address 7 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_START_ADDR_7 :: start [31:00] */ #define BCHP_SUN_GISB_ARB_BP_START_ADDR_7_start_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_START_ADDR_7_start_SHIFT 0 /*************************************************************************** *BP_END_ADDR_7 - GISB ARBITER Breakpoint End Address 7 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_END_ADDR_7 :: end [31:00] */ #define BCHP_SUN_GISB_ARB_BP_END_ADDR_7_end_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_END_ADDR_7_end_SHIFT 0 /*************************************************************************** *BP_READ_7 - GISB ARBITER Breakpoint Master Read Control 7 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_READ_7 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_READ_7_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_READ_7_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_READ_7 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_READ_7_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_READ_7_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_READ_7_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_7_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_7 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_READ_7_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_READ_7_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_READ_7_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_7_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_7 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_READ_7_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_READ_7_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_READ_7 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_READ_7_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_READ_7_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_READ_7_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_7_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_7 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_READ_7_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_READ_7_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_READ_7 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_READ_7_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_READ_7_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_READ_7_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_7_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_7 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_READ_7_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_READ_7_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_READ_7_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_7_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_7 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_READ_7_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_READ_7_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_READ_7_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_7_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_7 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_READ_7_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_READ_7_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_READ_7_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_7_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_READ_7 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_READ_7_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_READ_7_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_READ_7_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_READ_7_ssp_ENABLE 1 /*************************************************************************** *BP_WRITE_7 - GISB ARBITER Breakpoint Master Write Control 7 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_WRITE_7 :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_7_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_WRITE_7 :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_7_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_trb_SHIFT 11 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_trb_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_trb_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_7 :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_7_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_jtag_SHIFT 10 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_jtag_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_jtag_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_7 :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_7_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_WRITE_7 :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_7_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_avd0_SHIFT 7 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_avd0_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_avd0_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_7 :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_7_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_WRITE_7 :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_7_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_bsp_SHIFT 4 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_bsp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_bsp_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_7 :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_7_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_cce_SHIFT 3 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_cce_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_cce_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_7 :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_7_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_pcie_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_pcie_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_pcie_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_7 :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_7_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_arm_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_arm_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_arm_ENABLE 1 /* SUN_GISB_ARB :: BP_WRITE_7 :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_WRITE_7_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_ssp_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_ssp_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_WRITE_7_ssp_ENABLE 1 /*************************************************************************** *BP_ENABLE_7 - GISB ARBITER Breakpoint Enable 7 Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_ENABLE_7 :: reserved0 [31:03] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_7_reserved0_MASK 0xfffffff8 #define BCHP_SUN_GISB_ARB_BP_ENABLE_7_reserved0_SHIFT 3 /* SUN_GISB_ARB :: BP_ENABLE_7 :: block [02:02] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_7_block_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_ENABLE_7_block_SHIFT 2 #define BCHP_SUN_GISB_ARB_BP_ENABLE_7_block_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_7_block_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_7 :: address [01:01] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_7_address_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_ENABLE_7_address_SHIFT 1 #define BCHP_SUN_GISB_ARB_BP_ENABLE_7_address_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_7_address_ENABLE 1 /* SUN_GISB_ARB :: BP_ENABLE_7 :: access [00:00] */ #define BCHP_SUN_GISB_ARB_BP_ENABLE_7_access_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_ENABLE_7_access_SHIFT 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_7_access_DISABLE 0 #define BCHP_SUN_GISB_ARB_BP_ENABLE_7_access_ENABLE 1 /*************************************************************************** *BP_CAP_ADDR - GISB ARBITER Breakpoint Capture Address Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_CAP_ADDR :: address [31:00] */ #define BCHP_SUN_GISB_ARB_BP_CAP_ADDR_address_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_CAP_ADDR_address_SHIFT 0 /*************************************************************************** *BP_CAP_DATA - GISB ARBITER Breakpoint Capture Data Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_CAP_DATA :: data [31:00] */ #define BCHP_SUN_GISB_ARB_BP_CAP_DATA_data_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_BP_CAP_DATA_data_SHIFT 0 /*************************************************************************** *BP_CAP_STATUS - GISB ARBITER Breakpoint Capture Status Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_CAP_STATUS :: reserved0 [31:06] */ #define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_reserved0_MASK 0xffffffc0 #define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_reserved0_SHIFT 6 /* SUN_GISB_ARB :: BP_CAP_STATUS :: bs_b [05:02] */ #define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_bs_b_MASK 0x0000003c #define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_bs_b_SHIFT 2 /* SUN_GISB_ARB :: BP_CAP_STATUS :: write [01:01] */ #define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_write_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_write_SHIFT 1 /* SUN_GISB_ARB :: BP_CAP_STATUS :: valid [00:00] */ #define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_valid_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_CAP_STATUS_valid_SHIFT 0 /*************************************************************************** *BP_CAP_MASTER - GISB ARBITER Breakpoint Capture GISB MASTER Register ***************************************************************************/ /* SUN_GISB_ARB :: BP_CAP_MASTER :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_reserved0_SHIFT 12 /* SUN_GISB_ARB :: BP_CAP_MASTER :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_trb_SHIFT 11 /* SUN_GISB_ARB :: BP_CAP_MASTER :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_jtag_SHIFT 10 /* SUN_GISB_ARB :: BP_CAP_MASTER :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_reserved1_SHIFT 8 /* SUN_GISB_ARB :: BP_CAP_MASTER :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_avd0_SHIFT 7 /* SUN_GISB_ARB :: BP_CAP_MASTER :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_reserved2_SHIFT 5 /* SUN_GISB_ARB :: BP_CAP_MASTER :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_bsp_SHIFT 4 /* SUN_GISB_ARB :: BP_CAP_MASTER :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_cce_SHIFT 3 /* SUN_GISB_ARB :: BP_CAP_MASTER :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_pcie_SHIFT 2 /* SUN_GISB_ARB :: BP_CAP_MASTER :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_arm_SHIFT 1 /* SUN_GISB_ARB :: BP_CAP_MASTER :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_BP_CAP_MASTER_ssp_SHIFT 0 /*************************************************************************** *ERR_CAP_CLR - GISB ARBITER Error Capture Clear Register ***************************************************************************/ /* SUN_GISB_ARB :: ERR_CAP_CLR :: reserved0 [31:01] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_CLR_reserved0_MASK 0xfffffffe #define BCHP_SUN_GISB_ARB_ERR_CAP_CLR_reserved0_SHIFT 1 /* SUN_GISB_ARB :: ERR_CAP_CLR :: clear [00:00] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_CLR_clear_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_ERR_CAP_CLR_clear_SHIFT 0 /*************************************************************************** *ERR_CAP_ADDR - GISB ARBITER Error Capture Address Register ***************************************************************************/ /* SUN_GISB_ARB :: ERR_CAP_ADDR :: address [31:00] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_ADDR_address_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_ERR_CAP_ADDR_address_SHIFT 0 /*************************************************************************** *ERR_CAP_DATA - GISB ARBITER Error Capture Data Register ***************************************************************************/ /* SUN_GISB_ARB :: ERR_CAP_DATA :: data [31:00] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_DATA_data_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_ERR_CAP_DATA_data_SHIFT 0 /*************************************************************************** *ERR_CAP_STATUS - GISB ARBITER Error Capture Status Register ***************************************************************************/ /* SUN_GISB_ARB :: ERR_CAP_STATUS :: reserved0 [31:13] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_reserved0_MASK 0xffffe000 #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_reserved0_SHIFT 13 /* SUN_GISB_ARB :: ERR_CAP_STATUS :: timeout [12:12] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_timeout_MASK 0x00001000 #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_timeout_SHIFT 12 /* SUN_GISB_ARB :: ERR_CAP_STATUS :: tea [11:11] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_tea_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_tea_SHIFT 11 /* SUN_GISB_ARB :: ERR_CAP_STATUS :: reserved1 [10:06] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_reserved1_MASK 0x000007c0 #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_reserved1_SHIFT 6 /* SUN_GISB_ARB :: ERR_CAP_STATUS :: bs_b [05:02] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_bs_b_MASK 0x0000003c #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_bs_b_SHIFT 2 /* SUN_GISB_ARB :: ERR_CAP_STATUS :: write [01:01] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_write_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_write_SHIFT 1 /* SUN_GISB_ARB :: ERR_CAP_STATUS :: valid [00:00] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_valid_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_ERR_CAP_STATUS_valid_SHIFT 0 /*************************************************************************** *ERR_CAP_MASTER - GISB ARBITER Error Capture GISB MASTER Register ***************************************************************************/ /* SUN_GISB_ARB :: ERR_CAP_MASTER :: reserved0 [31:12] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_reserved0_MASK 0xfffff000 #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_reserved0_SHIFT 12 /* SUN_GISB_ARB :: ERR_CAP_MASTER :: trb [11:11] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_trb_MASK 0x00000800 #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_trb_SHIFT 11 /* SUN_GISB_ARB :: ERR_CAP_MASTER :: jtag [10:10] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_jtag_MASK 0x00000400 #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_jtag_SHIFT 10 /* SUN_GISB_ARB :: ERR_CAP_MASTER :: reserved1 [09:08] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_reserved1_MASK 0x00000300 #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_reserved1_SHIFT 8 /* SUN_GISB_ARB :: ERR_CAP_MASTER :: avd0 [07:07] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_avd0_MASK 0x00000080 #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_avd0_SHIFT 7 /* SUN_GISB_ARB :: ERR_CAP_MASTER :: reserved2 [06:05] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_reserved2_MASK 0x00000060 #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_reserved2_SHIFT 5 /* SUN_GISB_ARB :: ERR_CAP_MASTER :: bsp [04:04] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_bsp_MASK 0x00000010 #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_bsp_SHIFT 4 /* SUN_GISB_ARB :: ERR_CAP_MASTER :: cce [03:03] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_cce_MASK 0x00000008 #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_cce_SHIFT 3 /* SUN_GISB_ARB :: ERR_CAP_MASTER :: pcie [02:02] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_pcie_MASK 0x00000004 #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_pcie_SHIFT 2 /* SUN_GISB_ARB :: ERR_CAP_MASTER :: arm [01:01] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_arm_MASK 0x00000002 #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_arm_SHIFT 1 /* SUN_GISB_ARB :: ERR_CAP_MASTER :: ssp [00:00] */ #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_ssp_MASK 0x00000001 #define BCHP_SUN_GISB_ARB_ERR_CAP_MASTER_ssp_SHIFT 0 #endif /* #ifndef BCHP_SUN_GISB_ARB_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016400000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arc_l1_regs.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_ar0000644000175000017500000002513211610313111031015 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_arb_arc_l1_regs.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:14p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:14 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arc_l1_regs.h $ * * Hydra_Software_Devel/1 7/17/09 8:14p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_ARB_ARC_L1_REGS_H__ #define BCHP_PRI_ARB_ARC_L1_REGS_H__ /*************************************************************************** *PRI_ARB_ARC_L1_REGS - PRIMARY_ARB L1 (ARCs) Interrupt Registers ***************************************************************************/ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS 0x0040cf00 /* Interrupt Status Register */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_STATUS 0x0040cf04 /* Interrupt Status Register */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS 0x0040cf08 /* Interrupt Mask Status Register */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_STATUS 0x0040cf0c /* Interrupt Mask Status Register */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET 0x0040cf10 /* Interrupt Mask Set Register */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_SET 0x0040cf14 /* Interrupt Mask Set Register */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR 0x0040cf18 /* Interrupt Mask Clear Register */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_CLEAR 0x0040cf1c /* Interrupt Mask Clear Register */ /*************************************************************************** *INTR_W0_STATUS - Interrupt Status Register ***************************************************************************/ /* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: reserved0 [31:05] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_reserved0_MASK 0xffffffe0 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_reserved0_SHIFT 5 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ALIAS_INTR [04:04] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ALIAS_INTR_MASK 0x00000010 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ALIAS_INTR_SHIFT 4 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ARCH3_INTR [03:03] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH3_INTR_MASK 0x00000008 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH3_INTR_SHIFT 3 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ARCH2_INTR [02:02] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH2_INTR_MASK 0x00000004 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH2_INTR_SHIFT 2 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ARCH1_INTR [01:01] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH1_INTR_MASK 0x00000002 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH1_INTR_SHIFT 1 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_STATUS :: ARCH0_INTR [00:00] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH0_INTR_MASK 0x00000001 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_STATUS_ARCH0_INTR_SHIFT 0 /*************************************************************************** *INTR_W1_STATUS - Interrupt Status Register ***************************************************************************/ /* PRI_ARB_ARC_L1_REGS :: INTR_W1_STATUS :: reserved0 [31:00] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_STATUS_reserved0_MASK 0xffffffff #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_STATUS_reserved0_SHIFT 0 /*************************************************************************** *INTR_W0_MASK_STATUS - Interrupt Mask Status Register ***************************************************************************/ /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: reserved0 [31:05] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_reserved0_MASK 0xffffffe0 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_reserved0_SHIFT 5 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ALIAS_MASK [04:04] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ALIAS_MASK_MASK 0x00000010 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ALIAS_MASK_SHIFT 4 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ARCH3_MASK [03:03] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH3_MASK_MASK 0x00000008 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH3_MASK_SHIFT 3 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ARCH2_MASK [02:02] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH2_MASK_MASK 0x00000004 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH2_MASK_SHIFT 2 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ARCH1_MASK [01:01] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH1_MASK_MASK 0x00000002 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH1_MASK_SHIFT 1 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_STATUS :: ARCH0_MASK [00:00] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH0_MASK_MASK 0x00000001 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_STATUS_ARCH0_MASK_SHIFT 0 /*************************************************************************** *INTR_W1_MASK_STATUS - Interrupt Mask Status Register ***************************************************************************/ /* PRI_ARB_ARC_L1_REGS :: INTR_W1_MASK_STATUS :: reserved0 [31:00] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_STATUS_reserved0_MASK 0xffffffff #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_STATUS_reserved0_SHIFT 0 /*************************************************************************** *INTR_W0_MASK_SET - Interrupt Mask Set Register ***************************************************************************/ /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: reserved0 [31:05] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_reserved0_MASK 0xffffffe0 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_reserved0_SHIFT 5 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ALIAS_MASK [04:04] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ALIAS_MASK_MASK 0x00000010 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ALIAS_MASK_SHIFT 4 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ARCH3_MASK [03:03] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH3_MASK_MASK 0x00000008 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH3_MASK_SHIFT 3 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ARCH2_MASK [02:02] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH2_MASK_MASK 0x00000004 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH2_MASK_SHIFT 2 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ARCH1_MASK [01:01] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH1_MASK_MASK 0x00000002 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH1_MASK_SHIFT 1 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_SET :: ARCH0_MASK [00:00] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH0_MASK_MASK 0x00000001 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_SET_ARCH0_MASK_SHIFT 0 /*************************************************************************** *INTR_W1_MASK_SET - Interrupt Mask Set Register ***************************************************************************/ /* PRI_ARB_ARC_L1_REGS :: INTR_W1_MASK_SET :: reserved0 [31:00] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_SET_reserved0_MASK 0xffffffff #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_SET_reserved0_SHIFT 0 /*************************************************************************** *INTR_W0_MASK_CLEAR - Interrupt Mask Clear Register ***************************************************************************/ /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: reserved0 [31:05] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_reserved0_MASK 0xffffffe0 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_reserved0_SHIFT 5 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ALIAS_MASK [04:04] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ALIAS_MASK_MASK 0x00000010 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ALIAS_MASK_SHIFT 4 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ARCH3_MASK [03:03] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH3_MASK_MASK 0x00000008 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH3_MASK_SHIFT 3 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ARCH2_MASK [02:02] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH2_MASK_MASK 0x00000004 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH2_MASK_SHIFT 2 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ARCH1_MASK [01:01] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH1_MASK_MASK 0x00000002 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH1_MASK_SHIFT 1 /* PRI_ARB_ARC_L1_REGS :: INTR_W0_MASK_CLEAR :: ARCH0_MASK [00:00] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH0_MASK_MASK 0x00000001 #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W0_MASK_CLEAR_ARCH0_MASK_SHIFT 0 /*************************************************************************** *INTR_W1_MASK_CLEAR - Interrupt Mask Clear Register ***************************************************************************/ /* PRI_ARB_ARC_L1_REGS :: INTR_W1_MASK_CLEAR :: reserved0 [31:00] */ #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_CLEAR_reserved0_MASK 0xffffffff #define BCHP_PRI_ARB_ARC_L1_REGS_INTR_W1_MASK_CLEAR_reserved0_SHIFT 0 #endif /* #ifndef BCHP_PRI_ARB_ARC_L1_REGS_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016200000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arch_regs.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_ar0000644000175000017500000004451611610313111031024 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_arb_arch_regs.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:14p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:53 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_arch_regs.h $ * * Hydra_Software_Devel/1 7/17/09 8:14p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_ARB_ARCH_REGS_H__ #define BCHP_PRI_ARB_ARCH_REGS_H__ /*************************************************************************** *PRI_ARB_ARCH_REGS - PRIMARY_ARB address range and alias checker registers ***************************************************************************/ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG 0x0040cda0 /* Address Alias Checker control register */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_ADDR 0x0040cda4 /* Address Alias Checker violating command address. */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO 0x0040cda8 /* Address Alias Checker violating command information. */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_STATUS_CLEAR 0x0040cdac /* Address Alias Checker violating command status release. */ /*************************************************************************** *CNTRL_REG%i - Address Range Checker (ARCH0..3) control register ***************************************************************************/ #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_ARRAY_BASE 0x0040cc00 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_ARRAY_START 0 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_ARRAY_END 3 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *CNTRL_REG%i - Address Range Checker (ARCH0..3) control register ***************************************************************************/ /* PRI_ARB_ARCH_REGS :: CNTRL_REGi :: reserved0 [31:06] */ #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_reserved0_MASK 0xffffffc0 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_reserved0_SHIFT 6 /* PRI_ARB_ARCH_REGS :: CNTRL_REGi :: READ_ABORT [05:05] */ #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_ABORT_MASK 0x00000020 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_ABORT_SHIFT 5 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_ABORT_DISABLED 0 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_ABORT_ENABLED 1 /* PRI_ARB_ARCH_REGS :: CNTRL_REGi :: WRITE_ABORT [04:04] */ #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_ABORT_MASK 0x00000010 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_ABORT_SHIFT 4 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_ABORT_DISABLED 0 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_ABORT_ENABLED 1 /* PRI_ARB_ARCH_REGS :: CNTRL_REGi :: WRITE_CHECK [03:03] */ #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_CHECK_MASK 0x00000008 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_CHECK_SHIFT 3 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_CHECK_DISABLED 0 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_WRITE_CHECK_ENABLED 1 /* PRI_ARB_ARCH_REGS :: CNTRL_REGi :: READ_CHECK [02:02] */ #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_CHECK_MASK 0x00000004 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_CHECK_SHIFT 2 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_CHECK_DISABLED 0 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_READ_CHECK_ENABLED 1 /* PRI_ARB_ARCH_REGS :: CNTRL_REGi :: MODE [01:00] */ #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_MODE_MASK 0x00000003 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_MODE_SHIFT 0 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_MODE_NON_EXCLUSIVE 0 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_MODE_EXCLUSIVE 1 #define BCHP_PRI_ARB_ARCH_REGS_CNTRL_REGi_MODE_ULTRA_EXCLUSIVE 2 /*************************************************************************** *ADRS_RANGE_LOW%i - Address Range Checker (ARCH0..3) memory range lower address register ***************************************************************************/ #define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_LOWi_ARRAY_BASE 0x0040cc20 #define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_LOWi_ARRAY_START 0 #define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_LOWi_ARRAY_END 3 #define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_LOWi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *ADRS_RANGE_LOW%i - Address Range Checker (ARCH0..3) memory range lower address register ***************************************************************************/ /* PRI_ARB_ARCH_REGS :: ADRS_RANGE_LOWi :: ADDRESS [31:00] */ #define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_LOWi_ADDRESS_MASK 0xffffffff #define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_LOWi_ADDRESS_SHIFT 0 /*************************************************************************** *ADRS_RANGE_HIGH%i - Address Range Checker (ARCH0..3) memory range upper address register ***************************************************************************/ #define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_BASE 0x0040cc40 #define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_START 0 #define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_END 3 #define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_HIGHi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *ADRS_RANGE_HIGH%i - Address Range Checker (ARCH0..3) memory range upper address register ***************************************************************************/ /* PRI_ARB_ARCH_REGS :: ADRS_RANGE_HIGHi :: ADDRESS [31:00] */ #define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_HIGHi_ADDRESS_MASK 0xffffffff #define BCHP_PRI_ARB_ARCH_REGS_ADRS_RANGE_HIGHi_ADDRESS_SHIFT 0 /*************************************************************************** *READ_RIGHTS_0_%i - Address Range Checker (ARCH0..3) read access rights for clients #0 through #19. ***************************************************************************/ #define BCHP_PRI_ARB_ARCH_REGS_READ_RIGHTS_0_i_ARRAY_BASE 0x0040cc60 #define BCHP_PRI_ARB_ARCH_REGS_READ_RIGHTS_0_i_ARRAY_START 0 #define BCHP_PRI_ARB_ARCH_REGS_READ_RIGHTS_0_i_ARRAY_END 3 #define BCHP_PRI_ARB_ARCH_REGS_READ_RIGHTS_0_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *READ_RIGHTS_0_%i - Address Range Checker (ARCH0..3) read access rights for clients #0 through #19. ***************************************************************************/ /* PRI_ARB_ARCH_REGS :: READ_RIGHTS_0_i :: ACCESS_RIGHT [31:00] */ #define BCHP_PRI_ARB_ARCH_REGS_READ_RIGHTS_0_i_ACCESS_RIGHT_MASK 0xffffffff #define BCHP_PRI_ARB_ARCH_REGS_READ_RIGHTS_0_i_ACCESS_RIGHT_SHIFT 0 /*************************************************************************** *WRITE_RIGHTS_0_%i - Address Range Checker (ARCH0..3) write access rights for clients #0 through #19. ***************************************************************************/ #define BCHP_PRI_ARB_ARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_BASE 0x0040ccc0 #define BCHP_PRI_ARB_ARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_START 0 #define BCHP_PRI_ARB_ARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_END 3 #define BCHP_PRI_ARB_ARCH_REGS_WRITE_RIGHTS_0_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *WRITE_RIGHTS_0_%i - Address Range Checker (ARCH0..3) write access rights for clients #0 through #19. ***************************************************************************/ /* PRI_ARB_ARCH_REGS :: WRITE_RIGHTS_0_i :: ACCESS_RIGHT [31:00] */ #define BCHP_PRI_ARB_ARCH_REGS_WRITE_RIGHTS_0_i_ACCESS_RIGHT_MASK 0xffffffff #define BCHP_PRI_ARB_ARCH_REGS_WRITE_RIGHTS_0_i_ACCESS_RIGHT_SHIFT 0 /*************************************************************************** *VIOL_ADDR%i - Address Range Checker (ARCH0..3) violating command address. ***************************************************************************/ #define BCHP_PRI_ARB_ARCH_REGS_VIOL_ADDRi_ARRAY_BASE 0x0040cd40 #define BCHP_PRI_ARB_ARCH_REGS_VIOL_ADDRi_ARRAY_START 0 #define BCHP_PRI_ARB_ARCH_REGS_VIOL_ADDRi_ARRAY_END 3 #define BCHP_PRI_ARB_ARCH_REGS_VIOL_ADDRi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *VIOL_ADDR%i - Address Range Checker (ARCH0..3) violating command address. ***************************************************************************/ /* PRI_ARB_ARCH_REGS :: VIOL_ADDRi :: ADDRESS [31:00] */ #define BCHP_PRI_ARB_ARCH_REGS_VIOL_ADDRi_ADDRESS_MASK 0xffffffff #define BCHP_PRI_ARB_ARCH_REGS_VIOL_ADDRi_ADDRESS_SHIFT 0 /*************************************************************************** *VIOL_INFO%i - Address Range Checker (ARCH0..3) violating command information. ***************************************************************************/ #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_ARRAY_BASE 0x0040cd60 #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_ARRAY_START 0 #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_ARRAY_END 3 #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *VIOL_INFO%i - Address Range Checker (ARCH0..3) violating command information. ***************************************************************************/ /* PRI_ARB_ARCH_REGS :: VIOL_INFOi :: CLIENTID [31:24] */ #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_CLIENTID_MASK 0xff000000 #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_CLIENTID_SHIFT 24 /* PRI_ARB_ARCH_REGS :: VIOL_INFOi :: reserved0 [23:22] */ #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_reserved0_MASK 0x00c00000 #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_reserved0_SHIFT 22 /* PRI_ARB_ARCH_REGS :: VIOL_INFOi :: LENGTH [21:12] */ #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_LENGTH_MASK 0x003ff000 #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_LENGTH_SHIFT 12 /* PRI_ARB_ARCH_REGS :: VIOL_INFOi :: MODE [11:09] */ #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_MODE_MASK 0x00000e00 #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_MODE_SHIFT 9 /* PRI_ARB_ARCH_REGS :: VIOL_INFOi :: WRITE [08:08] */ #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_WRITE_MASK 0x00000100 #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_WRITE_SHIFT 8 /* PRI_ARB_ARCH_REGS :: VIOL_INFOi :: reserved1 [07:01] */ #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_reserved1_MASK 0x000000fe #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_reserved1_SHIFT 1 /* PRI_ARB_ARCH_REGS :: VIOL_INFOi :: STATUS [00:00] */ #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_STATUS_MASK 0x00000001 #define BCHP_PRI_ARB_ARCH_REGS_VIOL_INFOi_STATUS_SHIFT 0 /*************************************************************************** *STATUS_CLEAR%i - Address Range Checker (ARCH0..3) violating command status release. ***************************************************************************/ #define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_ARRAY_BASE 0x0040cd80 #define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_ARRAY_START 0 #define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_ARRAY_END 3 #define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *STATUS_CLEAR%i - Address Range Checker (ARCH0..3) violating command status release. ***************************************************************************/ /* PRI_ARB_ARCH_REGS :: STATUS_CLEARi :: reserved0 [31:01] */ #define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_reserved0_MASK 0xfffffffe #define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_reserved0_SHIFT 1 /* PRI_ARB_ARCH_REGS :: STATUS_CLEARi :: CLEAR [00:00] */ #define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_CLEAR_MASK 0x00000001 #define BCHP_PRI_ARB_ARCH_REGS_STATUS_CLEARi_CLEAR_SHIFT 0 /*************************************************************************** *ALIAS_CNTRL_REG - Address Alias Checker control register ***************************************************************************/ /* PRI_ARB_ARCH_REGS :: ALIAS_CNTRL_REG :: reserved0 [31:06] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_reserved0_MASK 0xffffffc0 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_reserved0_SHIFT 6 /* PRI_ARB_ARCH_REGS :: ALIAS_CNTRL_REG :: WRITE_ABORT [05:05] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_WRITE_ABORT_MASK 0x00000020 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_WRITE_ABORT_SHIFT 5 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_WRITE_ABORT_DISABLED 0 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_WRITE_ABORT_ENABLED 1 /* PRI_ARB_ARCH_REGS :: ALIAS_CNTRL_REG :: CHECK [04:04] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_CHECK_MASK 0x00000010 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_CHECK_SHIFT 4 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_CHECK_DISABLED 0 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_CHECK_ENABLED 1 /* PRI_ARB_ARCH_REGS :: ALIAS_CNTRL_REG :: DDR1_SIZE [03:02] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR1_SIZE_MASK 0x0000000c #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR1_SIZE_SHIFT 2 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR1_SIZE_SIZE_64_MB 0 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR1_SIZE_SIZE_128_MB 1 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR1_SIZE_SIZE_256_MB 2 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR1_SIZE_SIZE_512_MB 3 /* PRI_ARB_ARCH_REGS :: ALIAS_CNTRL_REG :: DDR0_SIZE [01:00] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR0_SIZE_MASK 0x00000003 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR0_SIZE_SHIFT 0 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR0_SIZE_SIZE_64_MB 0 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR0_SIZE_SIZE_128_MB 1 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR0_SIZE_SIZE_256_MB 2 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_CNTRL_REG_DDR0_SIZE_SIZE_512_MB 3 /*************************************************************************** *ALIAS_VIOL_ADDR - Address Alias Checker violating command address. ***************************************************************************/ /* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_ADDR :: ADDRESS [31:00] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_ADDR_ADDRESS_MASK 0xffffffff #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_ADDR_ADDRESS_SHIFT 0 /*************************************************************************** *ALIAS_VIOL_INFO - Address Alias Checker violating command information. ***************************************************************************/ /* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_INFO :: CLIENTID [31:24] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_CLIENTID_MASK 0xff000000 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_CLIENTID_SHIFT 24 /* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_INFO :: reserved0 [23:22] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_reserved0_MASK 0x00c00000 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_reserved0_SHIFT 22 /* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_INFO :: LENGTH [21:12] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_LENGTH_MASK 0x003ff000 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_LENGTH_SHIFT 12 /* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_INFO :: MODE [11:09] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_MODE_MASK 0x00000e00 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_MODE_SHIFT 9 /* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_INFO :: WRITE [08:08] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_WRITE_MASK 0x00000100 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_WRITE_SHIFT 8 /* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_INFO :: reserved1 [07:01] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_reserved1_MASK 0x000000fe #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_reserved1_SHIFT 1 /* PRI_ARB_ARCH_REGS :: ALIAS_VIOL_INFO :: STATUS [00:00] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_STATUS_MASK 0x00000001 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_VIOL_INFO_STATUS_SHIFT 0 /*************************************************************************** *ALIAS_STATUS_CLEAR - Address Alias Checker violating command status release. ***************************************************************************/ /* PRI_ARB_ARCH_REGS :: ALIAS_STATUS_CLEAR :: reserved0 [31:01] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_STATUS_CLEAR_reserved0_MASK 0xfffffffe #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_STATUS_CLEAR_reserved0_SHIFT 1 /* PRI_ARB_ARCH_REGS :: ALIAS_STATUS_CLEAR :: CLEAR [00:00] */ #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_STATUS_CLEAR_CLEAR_MASK 0x00000001 #define BCHP_PRI_ARB_ARCH_REGS_ALIAS_STATUS_CLEAR_CLEAR_SHIFT 0 #endif /* #ifndef BCHP_PRI_ARB_ARCH_REGS_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000017000000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000001331511610313111030764 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_ind_sdram_regs_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:04p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:26 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_ind_sdram_regs_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:04p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_IND_SDRAM_REGS_0_H__ #define BCHP_DECODE_IND_SDRAM_REGS_0_H__ /*************************************************************************** *DECODE_IND_SDRAM_REGS_0 ***************************************************************************/ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC 0x00841000 /* REG_SDRAM_INC */ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR 0x00841004 /* REG_SDRAM_ADDR */ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_DATA 0x00841008 /* REG_SDRAM_DATA */ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG 0x00841010 /* REG_CPU_DBG */ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_STAT 0x00841014 /* REG_SDRAM_STAT */ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_END 0x0084107c /* REG_SDRAM_END */ /*************************************************************************** *REG_SDRAM_INC - REG_SDRAM_INC ***************************************************************************/ /* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_INC :: reserved0 [31:01] */ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC_reserved0_MASK 0xfffffffe #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC_reserved0_SHIFT 1 /* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_INC :: Inc [00:00] */ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC_Inc_MASK 0x00000001 #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_INC_Inc_SHIFT 0 /*************************************************************************** *REG_SDRAM_ADDR - REG_SDRAM_ADDR ***************************************************************************/ /* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_ADDR :: Addr [31:02] */ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR_Addr_MASK 0xfffffffc #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR_Addr_SHIFT 2 /* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_ADDR :: reserved0 [01:00] */ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR_reserved0_MASK 0x00000003 #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_ADDR_reserved0_SHIFT 0 /*************************************************************************** *REG_SDRAM_DATA - REG_SDRAM_DATA ***************************************************************************/ /* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_DATA :: Data [31:00] */ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_DATA_Data_MASK 0xffffffff #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_DATA_Data_SHIFT 0 /*************************************************************************** *REG_CPU_DBG - REG_CPU_DBG ***************************************************************************/ /* DECODE_IND_SDRAM_REGS_0 :: REG_CPU_DBG :: reserved0 [31:01] */ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG_reserved0_MASK 0xfffffffe #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG_reserved0_SHIFT 1 /* DECODE_IND_SDRAM_REGS_0 :: REG_CPU_DBG :: Hst [00:00] */ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG_Hst_MASK 0x00000001 #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_CPU_DBG_Hst_SHIFT 0 /*************************************************************************** *REG_SDRAM_STAT - REG_SDRAM_STAT ***************************************************************************/ /* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_STAT :: reserved0 [31:00] */ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_STAT_reserved0_MASK 0xffffffff #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_STAT_reserved0_SHIFT 0 /*************************************************************************** *REG_SDRAM_END - REG_SDRAM_END ***************************************************************************/ /* DECODE_IND_SDRAM_REGS_0 :: REG_SDRAM_END :: reserved0 [31:00] */ #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_IND_SDRAM_REGS_0_REG_SDRAM_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_IND_SDRAM_REGS_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015500000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_rvc_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000001331511610313111030764 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_rvc_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:05p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:24 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_rvc_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:05p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_RVC_0_H__ #define BCHP_DECODE_RVC_0_H__ /*************************************************************************** *DECODE_RVC_0 ***************************************************************************/ #define BCHP_DECODE_RVC_0_REG_RVC_CTL 0x00800e00 /* REG_RVC_CTL */ #define BCHP_DECODE_RVC_0_REG_RVC_PUT 0x00800e04 /* REG_RVC_PUT */ #define BCHP_DECODE_RVC_0_REG_RVC_GET 0x00800e08 /* REG_RVC_GET */ #define BCHP_DECODE_RVC_0_REG_RVC_BASE 0x00800e0c /* REG_RVC_BASE */ #define BCHP_DECODE_RVC_0_REG_RVC_END 0x00800e10 /* REG_RVC_END */ #define BCHP_DECODE_RVC_0_REG_RVC_END_END 0x00800efc /* REG_RVC_END_END */ /*************************************************************************** *REG_RVC_CTL - REG_RVC_CTL ***************************************************************************/ /* DECODE_RVC_0 :: REG_RVC_CTL :: reserved0 [31:01] */ #define BCHP_DECODE_RVC_0_REG_RVC_CTL_reserved0_MASK 0xfffffffe #define BCHP_DECODE_RVC_0_REG_RVC_CTL_reserved0_SHIFT 1 /* DECODE_RVC_0 :: REG_RVC_CTL :: Ena [00:00] */ #define BCHP_DECODE_RVC_0_REG_RVC_CTL_Ena_MASK 0x00000001 #define BCHP_DECODE_RVC_0_REG_RVC_CTL_Ena_SHIFT 0 /*************************************************************************** *REG_RVC_PUT - REG_RVC_PUT ***************************************************************************/ /* DECODE_RVC_0 :: REG_RVC_PUT :: Put_Ptr [31:00] */ #define BCHP_DECODE_RVC_0_REG_RVC_PUT_Put_Ptr_MASK 0xffffffff #define BCHP_DECODE_RVC_0_REG_RVC_PUT_Put_Ptr_SHIFT 0 /*************************************************************************** *REG_RVC_GET - REG_RVC_GET ***************************************************************************/ /* DECODE_RVC_0 :: REG_RVC_GET :: Get_Ptr [31:05] */ #define BCHP_DECODE_RVC_0_REG_RVC_GET_Get_Ptr_MASK 0xffffffe0 #define BCHP_DECODE_RVC_0_REG_RVC_GET_Get_Ptr_SHIFT 5 /* DECODE_RVC_0 :: REG_RVC_GET :: reserved0 [04:00] */ #define BCHP_DECODE_RVC_0_REG_RVC_GET_reserved0_MASK 0x0000001f #define BCHP_DECODE_RVC_0_REG_RVC_GET_reserved0_SHIFT 0 /*************************************************************************** *REG_RVC_BASE - REG_RVC_BASE ***************************************************************************/ /* DECODE_RVC_0 :: REG_RVC_BASE :: Base_Addr [31:20] */ #define BCHP_DECODE_RVC_0_REG_RVC_BASE_Base_Addr_MASK 0xfff00000 #define BCHP_DECODE_RVC_0_REG_RVC_BASE_Base_Addr_SHIFT 20 /* DECODE_RVC_0 :: REG_RVC_BASE :: reserved0 [19:00] */ #define BCHP_DECODE_RVC_0_REG_RVC_BASE_reserved0_MASK 0x000fffff #define BCHP_DECODE_RVC_0_REG_RVC_BASE_reserved0_SHIFT 0 /*************************************************************************** *REG_RVC_END - REG_RVC_END ***************************************************************************/ /* DECODE_RVC_0 :: REG_RVC_END :: End_Addr [31:20] */ #define BCHP_DECODE_RVC_0_REG_RVC_END_End_Addr_MASK 0xfff00000 #define BCHP_DECODE_RVC_0_REG_RVC_END_End_Addr_SHIFT 20 /* DECODE_RVC_0 :: REG_RVC_END :: reserved0 [19:00] */ #define BCHP_DECODE_RVC_0_REG_RVC_END_reserved0_MASK 0x000fffff #define BCHP_DECODE_RVC_0_REG_RVC_END_reserved0_SHIFT 0 /*************************************************************************** *REG_RVC_END_END - REG_RVC_END_END ***************************************************************************/ /* DECODE_RVC_0 :: REG_RVC_END_END :: reserved0 [31:00] */ #define BCHP_DECODE_RVC_0_REG_RVC_END_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_RVC_0_REG_RVC_END_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_RVC_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016100000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudmem_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000616011610313111030764 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_cpudmem_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:01p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:12 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpudmem_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:01p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_CPUDMEM_0_H__ #define BCHP_DECODE_CPUDMEM_0_H__ /*************************************************************************** *DECODE_CPUDMEM_0 ***************************************************************************/ #define BCHP_DECODE_CPUDMEM_0_CPUDMEM_REG 0x00848000 /* CPUDMEM_REG */ #define BCHP_DECODE_CPUDMEM_0_CPUDMEM_END 0x0084fffc /* CPUDMEM_END */ /*************************************************************************** *CPUDMEM_REG - CPUDMEM_REG ***************************************************************************/ /* DECODE_CPUDMEM_0 :: CPUDMEM_REG :: Addr [31:00] */ #define BCHP_DECODE_CPUDMEM_0_CPUDMEM_REG_Addr_MASK 0xffffffff #define BCHP_DECODE_CPUDMEM_0_CPUDMEM_REG_Addr_SHIFT 0 /*************************************************************************** *CPUDMEM_END - CPUDMEM_END ***************************************************************************/ /* DECODE_CPUDMEM_0 :: CPUDMEM_END :: reserved0 [31:00] */ #define BCHP_DECODE_CPUDMEM_0_CPUDMEM_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_CPUDMEM_0_CPUDMEM_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_CPUDMEM_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016100000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dmamem2_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000454411610313111030770 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_dmamem2_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:03p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:40 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dmamem2_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:03p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_DMAMEM2_0_H__ #define BCHP_DECODE_DMAMEM2_0_H__ /*************************************************************************** *DECODE_DMAMEM2_0 ***************************************************************************/ #define BCHP_DECODE_DMAMEM2_0_DMA_MEM 0x00851a00 /* DMA_MEM */ #define BCHP_DECODE_DMAMEM2_0_DMA_MEM_END 0x008521fc /* REGION_END */ #endif /* #ifndef BCHP_DECODE_DMAMEM2_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000014600000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pm_l2.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pm_l2.0000644000175000017500000002470211610313111030632 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pm_l2.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:13p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:04 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pm_l2.h $ * * Hydra_Software_Devel/1 7/17/09 8:13p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PM_L2_H__ #define BCHP_PM_L2_H__ /*************************************************************************** *PM_L2 - Registers for the power management block's L2 interrupt controller ***************************************************************************/ #define BCHP_PM_L2_CPU_STATUS 0x00401c00 /* CPU interrupt Status Register */ #define BCHP_PM_L2_CPU_SET 0x00401c04 /* CPU interrupt Set Register */ #define BCHP_PM_L2_CPU_CLEAR 0x00401c08 /* CPU interrupt Clear Register */ #define BCHP_PM_L2_CPU_MASK_STATUS 0x00401c0c /* CPU interrupt Mask Status Register */ #define BCHP_PM_L2_CPU_MASK_SET 0x00401c10 /* CPU interrupt Mask Set Register */ #define BCHP_PM_L2_CPU_MASK_CLEAR 0x00401c14 /* CPU interrupt Mask Clear Register */ #define BCHP_PM_L2_PCI_STATUS 0x00401c18 /* PCI interrupt Status Register */ #define BCHP_PM_L2_PCI_SET 0x00401c1c /* PCI interrupt Set Register */ #define BCHP_PM_L2_PCI_CLEAR 0x00401c20 /* PCI interrupt Clear Register */ #define BCHP_PM_L2_PCI_MASK_STATUS 0x00401c24 /* PCI interrupt Mask Status Register */ #define BCHP_PM_L2_PCI_MASK_SET 0x00401c28 /* PCI interrupt Mask Set Register */ #define BCHP_PM_L2_PCI_MASK_CLEAR 0x00401c2c /* PCI interrupt Mask Clear Register */ /*************************************************************************** *CPU_STATUS - CPU interrupt Status Register ***************************************************************************/ /* PM_L2 :: CPU_STATUS :: reserved0 [31:01] */ #define BCHP_PM_L2_CPU_STATUS_reserved0_MASK 0xfffffffe #define BCHP_PM_L2_CPU_STATUS_reserved0_SHIFT 1 /* PM_L2 :: CPU_STATUS :: SPARE_WAKEUP_EVENT_0 [00:00] */ #define BCHP_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 #define BCHP_PM_L2_CPU_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 0 /*************************************************************************** *CPU_SET - CPU interrupt Set Register ***************************************************************************/ /* PM_L2 :: CPU_SET :: reserved0 [31:01] */ #define BCHP_PM_L2_CPU_SET_reserved0_MASK 0xfffffffe #define BCHP_PM_L2_CPU_SET_reserved0_SHIFT 1 /* PM_L2 :: CPU_SET :: SPARE_WAKEUP_EVENT_0 [00:00] */ #define BCHP_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 #define BCHP_PM_L2_CPU_SET_SPARE_WAKEUP_EVENT_0_SHIFT 0 /*************************************************************************** *CPU_CLEAR - CPU interrupt Clear Register ***************************************************************************/ /* PM_L2 :: CPU_CLEAR :: reserved0 [31:01] */ #define BCHP_PM_L2_CPU_CLEAR_reserved0_MASK 0xfffffffe #define BCHP_PM_L2_CPU_CLEAR_reserved0_SHIFT 1 /* PM_L2 :: CPU_CLEAR :: SPARE_WAKEUP_EVENT_0 [00:00] */ #define BCHP_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 #define BCHP_PM_L2_CPU_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 0 /*************************************************************************** *CPU_MASK_STATUS - CPU interrupt Mask Status Register ***************************************************************************/ /* PM_L2 :: CPU_MASK_STATUS :: reserved0 [31:01] */ #define BCHP_PM_L2_CPU_MASK_STATUS_reserved0_MASK 0xfffffffe #define BCHP_PM_L2_CPU_MASK_STATUS_reserved0_SHIFT 1 /* PM_L2 :: CPU_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [00:00] */ #define BCHP_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 #define BCHP_PM_L2_CPU_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 0 /*************************************************************************** *CPU_MASK_SET - CPU interrupt Mask Set Register ***************************************************************************/ /* PM_L2 :: CPU_MASK_SET :: reserved0 [31:01] */ #define BCHP_PM_L2_CPU_MASK_SET_reserved0_MASK 0xfffffffe #define BCHP_PM_L2_CPU_MASK_SET_reserved0_SHIFT 1 /* PM_L2 :: CPU_MASK_SET :: SPARE_WAKEUP_EVENT_0 [00:00] */ #define BCHP_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 #define BCHP_PM_L2_CPU_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT 0 /*************************************************************************** *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register ***************************************************************************/ /* PM_L2 :: CPU_MASK_CLEAR :: reserved0 [31:01] */ #define BCHP_PM_L2_CPU_MASK_CLEAR_reserved0_MASK 0xfffffffe #define BCHP_PM_L2_CPU_MASK_CLEAR_reserved0_SHIFT 1 /* PM_L2 :: CPU_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [00:00] */ #define BCHP_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 #define BCHP_PM_L2_CPU_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 0 /*************************************************************************** *PCI_STATUS - PCI interrupt Status Register ***************************************************************************/ /* PM_L2 :: PCI_STATUS :: reserved0 [31:01] */ #define BCHP_PM_L2_PCI_STATUS_reserved0_MASK 0xfffffffe #define BCHP_PM_L2_PCI_STATUS_reserved0_SHIFT 1 /* PM_L2 :: PCI_STATUS :: SPARE_WAKEUP_EVENT_0 [00:00] */ #define BCHP_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 #define BCHP_PM_L2_PCI_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 0 /*************************************************************************** *PCI_SET - PCI interrupt Set Register ***************************************************************************/ /* PM_L2 :: PCI_SET :: reserved0 [31:01] */ #define BCHP_PM_L2_PCI_SET_reserved0_MASK 0xfffffffe #define BCHP_PM_L2_PCI_SET_reserved0_SHIFT 1 /* PM_L2 :: PCI_SET :: SPARE_WAKEUP_EVENT_0 [00:00] */ #define BCHP_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 #define BCHP_PM_L2_PCI_SET_SPARE_WAKEUP_EVENT_0_SHIFT 0 /*************************************************************************** *PCI_CLEAR - PCI interrupt Clear Register ***************************************************************************/ /* PM_L2 :: PCI_CLEAR :: reserved0 [31:01] */ #define BCHP_PM_L2_PCI_CLEAR_reserved0_MASK 0xfffffffe #define BCHP_PM_L2_PCI_CLEAR_reserved0_SHIFT 1 /* PM_L2 :: PCI_CLEAR :: SPARE_WAKEUP_EVENT_0 [00:00] */ #define BCHP_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 #define BCHP_PM_L2_PCI_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 0 /*************************************************************************** *PCI_MASK_STATUS - PCI interrupt Mask Status Register ***************************************************************************/ /* PM_L2 :: PCI_MASK_STATUS :: reserved0 [31:01] */ #define BCHP_PM_L2_PCI_MASK_STATUS_reserved0_MASK 0xfffffffe #define BCHP_PM_L2_PCI_MASK_STATUS_reserved0_SHIFT 1 /* PM_L2 :: PCI_MASK_STATUS :: SPARE_WAKEUP_EVENT_0 [00:00] */ #define BCHP_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 #define BCHP_PM_L2_PCI_MASK_STATUS_SPARE_WAKEUP_EVENT_0_SHIFT 0 /*************************************************************************** *PCI_MASK_SET - PCI interrupt Mask Set Register ***************************************************************************/ /* PM_L2 :: PCI_MASK_SET :: reserved0 [31:01] */ #define BCHP_PM_L2_PCI_MASK_SET_reserved0_MASK 0xfffffffe #define BCHP_PM_L2_PCI_MASK_SET_reserved0_SHIFT 1 /* PM_L2 :: PCI_MASK_SET :: SPARE_WAKEUP_EVENT_0 [00:00] */ #define BCHP_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 #define BCHP_PM_L2_PCI_MASK_SET_SPARE_WAKEUP_EVENT_0_SHIFT 0 /*************************************************************************** *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register ***************************************************************************/ /* PM_L2 :: PCI_MASK_CLEAR :: reserved0 [31:01] */ #define BCHP_PM_L2_PCI_MASK_CLEAR_reserved0_MASK 0xfffffffe #define BCHP_PM_L2_PCI_MASK_CLEAR_reserved0_SHIFT 1 /* PM_L2 :: PCI_MASK_CLEAR :: SPARE_WAKEUP_EVENT_0 [00:00] */ #define BCHP_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_MASK 0x00000001 #define BCHP_PM_L2_PCI_MASK_CLEAR_SPARE_WAKEUP_EVENT_0_SHIFT 0 #endif /* #ifndef BCHP_PM_L2_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015000000000000011561 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_tl.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_t0000644000175000017500000011171711610313111031011 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pcie_tl.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:13p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:28 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_tl.h $ * * Hydra_Software_Devel/1 7/17/09 8:13p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PCIE_TL_H__ #define BCHP_PCIE_TL_H__ /*************************************************************************** *PCIE_TL - PCIE TL related registers ***************************************************************************/ #define BCHP_PCIE_TL_TL_CONTROL 0x00500400 /* TL_CONTROL Register */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION 0x00500404 /* TRANSACTION_CONFIGURATION Register */ #define BCHP_PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00500408 /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ #define BCHP_PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 0x0050040c /* WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 Register */ #define BCHP_PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC 0x00500410 /* DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register */ #define BCHP_PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 0x00500414 /* DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 Register */ #define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC 0x00500418 /* DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC Register */ #define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC 0x0050041c /* DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC Register */ #define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC 0x00500420 /* READ_DMA_SPLIT_IDS_DIAGNOSTIC Register */ #define BCHP_PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC 0x00500424 /* READ_DMA_SPLIT_LENGTH_DIAGNOSTIC Register */ #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC 0x0050043c /* XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC Register */ #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC 0x00500458 /* DMA_COMPLETION_MISC__DIAGNOSTIC Register */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC 0x0050045c /* SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC Register */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC 0x00500460 /* SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC Register */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC 0x00500464 /* SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC Register */ #define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO 0x00500468 /* TL_BUS_NO_DEV__NO__FUNC__NO Register */ #define BCHP_PCIE_TL_TL_DEBUG 0x0050046c /* TL_DEBUG Register */ /*************************************************************************** *TL_CONTROL - TL_CONTROL Register ***************************************************************************/ /* PCIE_TL :: TL_CONTROL :: RESERVED_0 [31:31] */ #define BCHP_PCIE_TL_TL_CONTROL_RESERVED_0_MASK 0x80000000 #define BCHP_PCIE_TL_TL_CONTROL_RESERVED_0_SHIFT 31 /* PCIE_TL :: TL_CONTROL :: CQ14298_FIX_ENA_N [30:30] */ #define BCHP_PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_MASK 0x40000000 #define BCHP_PCIE_TL_TL_CONTROL_CQ14298_FIX_ENA_N_SHIFT 30 /* PCIE_TL :: TL_CONTROL :: RESERVED_1 [29:29] */ #define BCHP_PCIE_TL_TL_CONTROL_RESERVED_1_MASK 0x20000000 #define BCHP_PCIE_TL_TL_CONTROL_RESERVED_1_SHIFT 29 /* PCIE_TL :: TL_CONTROL :: INTA_WAKEUP_LINK_CLKREQ_DA [28:28] */ #define BCHP_PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_MASK 0x10000000 #define BCHP_PCIE_TL_TL_CONTROL_INTA_WAKEUP_LINK_CLKREQ_DA_SHIFT 28 /* PCIE_TL :: TL_CONTROL :: RESERVED_2 [27:27] */ #define BCHP_PCIE_TL_TL_CONTROL_RESERVED_2_MASK 0x08000000 #define BCHP_PCIE_TL_TL_CONTROL_RESERVED_2_SHIFT 27 /* PCIE_TL :: TL_CONTROL :: CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX [26:26] */ #define BCHP_PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_MASK 0x04000000 #define BCHP_PCIE_TL_TL_CONTROL_CQ9583_TYPE_1_VENDOR_DEFINED_MESSAGE_FIX_SHIFT 26 /* PCIE_TL :: TL_CONTROL :: RESERVED_3 [25:25] */ #define BCHP_PCIE_TL_TL_CONTROL_RESERVED_3_MASK 0x02000000 #define BCHP_PCIE_TL_TL_CONTROL_RESERVED_3_SHIFT 25 /* PCIE_TL :: TL_CONTROL :: RESERVED_4 [24:24] */ #define BCHP_PCIE_TL_TL_CONTROL_RESERVED_4_MASK 0x01000000 #define BCHP_PCIE_TL_TL_CONTROL_RESERVED_4_SHIFT 24 /* PCIE_TL :: TL_CONTROL :: RESERVED_5 [23:23] */ #define BCHP_PCIE_TL_TL_CONTROL_RESERVED_5_MASK 0x00800000 #define BCHP_PCIE_TL_TL_CONTROL_RESERVED_5_SHIFT 23 /* PCIE_TL :: TL_CONTROL :: CRC_SWAP [22:22] */ #define BCHP_PCIE_TL_TL_CONTROL_CRC_SWAP_MASK 0x00400000 #define BCHP_PCIE_TL_TL_CONTROL_CRC_SWAP_SHIFT 22 /* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_CA_ERROR [21:21] */ #define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_MASK 0x00200000 #define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_CA_ERROR_SHIFT 21 /* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_UR_ERROR [20:20] */ #define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_MASK 0x00100000 #define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_UR_ERROR_SHIFT 20 /* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_RSV_ERROR [19:19] */ #define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_MASK 0x00080000 #define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_RSV_ERROR_SHIFT 19 /* PCIE_TL :: TL_CONTROL :: RESERVED_6 [18:18] */ #define BCHP_PCIE_TL_TL_CONTROL_RESERVED_6_MASK 0x00040000 #define BCHP_PCIE_TL_TL_CONTROL_RESERVED_6_SHIFT 18 /* PCIE_TL :: TL_CONTROL :: SLV_CMP_DIS_EP_ERROR [17:17] */ #define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_MASK 0x00020000 #define BCHP_PCIE_TL_TL_CONTROL_SLV_CMP_DIS_EP_ERROR_SHIFT 17 /* PCIE_TL :: TL_CONTROL :: ENABLE_BYTECOUNT_CHECK [16:16] */ #define BCHP_PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_MASK 0x00010000 #define BCHP_PCIE_TL_TL_CONTROL_ENABLE_BYTECOUNT_CHECK_SHIFT 16 /* PCIE_TL :: TL_CONTROL :: NOT_USED [15:14] */ #define BCHP_PCIE_TL_TL_CONTROL_NOT_USED_MASK 0x0000c000 #define BCHP_PCIE_TL_TL_CONTROL_NOT_USED_SHIFT 14 /* PCIE_TL :: TL_CONTROL :: TRAFFIC_CLASS_DR [13:11] */ #define BCHP_PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_MASK 0x00003800 #define BCHP_PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DR_SHIFT 11 /* PCIE_TL :: TL_CONTROL :: TRAFFIC_CLASS_DW [10:08] */ #define BCHP_PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_MASK 0x00000700 #define BCHP_PCIE_TL_TL_CONTROL_TRAFFIC_CLASS_DW_SHIFT 8 /* PCIE_TL :: TL_CONTROL :: NOT_USED_0 [07:06] */ #define BCHP_PCIE_TL_TL_CONTROL_NOT_USED_0_MASK 0x000000c0 #define BCHP_PCIE_TL_TL_CONTROL_NOT_USED_0_SHIFT 6 /* PCIE_TL :: TL_CONTROL :: NOT_USED_1 [05:00] */ #define BCHP_PCIE_TL_TL_CONTROL_NOT_USED_1_MASK 0x0000003f #define BCHP_PCIE_TL_TL_CONTROL_NOT_USED_1_SHIFT 0 /*************************************************************************** *TRANSACTION_CONFIGURATION - TRANSACTION_CONFIGURATION Register ***************************************************************************/ /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_RETRY_BUFFER_TIMING_MOD [31:31] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_MASK 0x80000000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_RETRY_BUFFER_TIMING_MOD_SHIFT 31 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_0 [30:30] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_MASK 0x40000000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_0_SHIFT 30 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: MSI_SINGLE_SHOT_ENABLE [29:29] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_MASK 0x20000000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_MSI_SINGLE_SHOT_ENABLE_SHIFT 29 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_1 [28:28] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_MASK 0x10000000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_1_SHIFT 28 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: SELECT_CORE_CLOCK_OVERRIDE [27:27] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_MASK 0x08000000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_SELECT_CORE_CLOCK_OVERRIDE_SHIFT 27 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: CQ9139_FIX_ENABLE [26:26] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_MASK 0x04000000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_CQ9139_FIX_ENABLE_SHIFT 26 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CMPT_PWR_CHECK [25:25] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_MASK 0x02000000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CMPT_PWR_CHECK_SHIFT 25 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CQ12696_FIX [24:24] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_MASK 0x01000000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12696_FIX_SHIFT 24 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: DEVICE_SERIAL_NO_OVERRIDE [23:23] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_MASK 0x00800000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_NO_OVERRIDE_SHIFT 23 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_CQ12455_FIX [22:22] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_MASK 0x00400000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_CQ12455_FIX_SHIFT 22 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_TC_VC_FILTERING_CHECK [21:21] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_MASK 0x00200000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_TC_VC_FILTERING_CHECK_SHIFT 21 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: DONT_GEN_HOT_PLUG_MSG [20:20] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_MASK 0x00100000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DONT_GEN_HOT_PLUG_MSG_SHIFT 20 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: IGNORE_HOTPLUG_MSG [19:19] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_MASK 0x00080000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_IGNORE_HOTPLUG_MSG_SHIFT 19 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: MSI_MULTMSG_CAPABLE [18:16] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_MASK 0x00070000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_MSI_MULTMSG_CAPABLE_SHIFT 16 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: DATA_SELECT_LIMIT [15:12] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_MASK 0x0000f000 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DATA_SELECT_LIMIT_SHIFT 12 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_PL [11:11] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_MASK 0x00000800 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_PL_SHIFT 11 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_DL [10:10] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_MASK 0x00000400 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_DL_SHIFT 10 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_PCIE_1_1_TL [09:09] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_MASK 0x00000200 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_PCIE_1_1_TL_SHIFT 9 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_2 [08:08] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_MASK 0x00000100 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_2_SHIFT 8 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: DEVICE_SERIAL_CAP_ENABLE [07:07] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_CAP_ENABLE_MASK 0x00000080 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_DEVICE_SERIAL_CAP_ENABLE_SHIFT 7 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: PCIE_POWER_BUDGET_CAP_ENABLE [06:06] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_MASK 0x00000040 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_PCIE_POWER_BUDGET_CAP_ENABLE_SHIFT 6 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: LOM_CONFIGURATION [05:05] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_MASK 0x00000020 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_LOM_CONFIGURATION_SHIFT 5 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: CONCATE_SELECT [04:04] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_MASK 0x00000010 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_CONCATE_SELECT_SHIFT 4 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: RESERVED_3 [03:03] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_MASK 0x00000008 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_RESERVED_3_SHIFT 3 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_9468_FIX [02:02] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_MASK 0x00000004 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9468_FIX_SHIFT 2 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: POWER_STATE_WRITE_MEM_ENABLE [01:01] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_MASK 0x00000002 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_POWER_STATE_WRITE_MEM_ENABLE_SHIFT 1 /* PCIE_TL :: TRANSACTION_CONFIGURATION :: ENABLE_9709_ENABLE [00:00] */ #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_MASK 0x00000001 #define BCHP_PCIE_TL_TRANSACTION_CONFIGURATION_ENABLE_9709_ENABLE_SHIFT 0 /*************************************************************************** *WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC - WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register ***************************************************************************/ /* PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC :: RESERVED_0 [31:00] */ #define BCHP_PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_MASK 0xffffffff #define BCHP_PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_RESERVED_0_SHIFT 0 /*************************************************************************** *WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 - WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 Register ***************************************************************************/ /* PCIE_TL :: WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2 :: RESERVED_0 [31:00] */ #define BCHP_PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_MASK 0xffffffff #define BCHP_PCIE_TL_WRITE_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_2_RESERVED_0_SHIFT 0 /*************************************************************************** *DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC - DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC Register ***************************************************************************/ /* PCIE_TL :: DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC :: REG_MADDR_UPR [31:00] */ #define BCHP_PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_MASK 0xffffffff #define BCHP_PCIE_TL_DMA_REQUEST_UPPER_ADDRESS_DIAGNOSTIC_REG_MADDR_UPR_SHIFT 0 /*************************************************************************** *DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 - DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 Register ***************************************************************************/ /* PCIE_TL :: DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2 :: REG_MADDR_LWR [31:00] */ #define BCHP_PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_MASK 0xffffffff #define BCHP_PCIE_TL_DMA_REQUEST_LOWER_ADDRESS_DIAGNOSTIC_2_REG_MADDR_LWR_SHIFT 0 /*************************************************************************** *DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC - DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC Register ***************************************************************************/ /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: REG_MLEN_BE [31:24] */ #define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_MASK 0xff000000 #define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_REG_MLEN_BE_SHIFT 24 /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_FIRST_DW_BYTE_ENABLES [23:20] */ #define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_MASK 0x00f00000 #define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_FIRST_DW_BYTE_ENABLES_SHIFT 20 /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_LAST_DW_BYTE_ENABLES [19:16] */ #define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_MASK 0x000f0000 #define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_LAST_DW_BYTE_ENABLES_SHIFT 16 /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: RESERVED_0 [15:11] */ #define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_MASK 0x0000f800 #define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_RESERVED_0_SHIFT 11 /* PCIE_TL :: DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC :: DMA_REQUEST_DW_LENGTH [10:00] */ #define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_MASK 0x000007ff #define BCHP_PCIE_TL_DMA_REQUEST_LENGTH_BYTE_ENABLE_DIAGNOSTIC_DMA_REQUEST_DW_LENGTH_SHIFT 0 /*************************************************************************** *DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC - DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC Register ***************************************************************************/ /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: REG_MTAG_ATTR [31:19] */ #define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_MASK 0xfff80000 #define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_REG_MTAG_ATTR_SHIFT 19 /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_FUNCTION [18:16] */ #define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_MASK 0x00070000 #define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_FUNCTION_SHIFT 16 /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: RESERVED_0 [15:13] */ #define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_MASK 0x0000e000 #define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_0_SHIFT 13 /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_ATTRIBUTES [12:08] */ #define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_MASK 0x00001f00 #define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_ATTRIBUTES_SHIFT 8 /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: RESERVED_1 [07:05] */ #define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_MASK 0x000000e0 #define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_RESERVED_1_SHIFT 5 /* PCIE_TL :: DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC :: DMA_REQUEST_TAG [04:00] */ #define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_MASK 0x0000001f #define BCHP_PCIE_TL_DMA_REQUEST_TAG_ATTRIBUTE_FUNCTION_DIAGNOSTIC_DMA_REQUEST_TAG_SHIFT 0 /*************************************************************************** *READ_DMA_SPLIT_IDS_DIAGNOSTIC - READ_DMA_SPLIT_IDS_DIAGNOSTIC Register ***************************************************************************/ /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: REG_SPLIT_ID [31:16] */ #define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_MASK 0xffff0000 #define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_REG_SPLIT_ID_SHIFT 16 /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: RESERVED_0 [15:13] */ #define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_MASK 0x0000e000 #define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_0_SHIFT 13 /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_ATTRIBUTES [12:11] */ #define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_MASK 0x00001800 #define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_ATTRIBUTES_SHIFT 11 /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_TC [10:08] */ #define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_MASK 0x00000700 #define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TC_SHIFT 8 /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: RESERVED_1 [07:05] */ #define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_MASK 0x000000e0 #define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_RESERVED_1_SHIFT 5 /* PCIE_TL :: READ_DMA_SPLIT_IDS_DIAGNOSTIC :: READ_DMA_SPLIT_TAG [04:00] */ #define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_MASK 0x0000001f #define BCHP_PCIE_TL_READ_DMA_SPLIT_IDS_DIAGNOSTIC_READ_DMA_SPLIT_TAG_SHIFT 0 /*************************************************************************** *READ_DMA_SPLIT_LENGTH_DIAGNOSTIC - READ_DMA_SPLIT_LENGTH_DIAGNOSTIC Register ***************************************************************************/ /* PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC :: REG_SPLIT_LEN [31:13] */ #define BCHP_PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_MASK 0xffffe000 #define BCHP_PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_REG_SPLIT_LEN_SHIFT 13 /* PCIE_TL :: READ_DMA_SPLIT_LENGTH_DIAGNOSTIC :: READ_DMA_SPLIT_INITIAL_BYTE_COUNT [12:00] */ #define BCHP_PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_MASK 0x00001fff #define BCHP_PCIE_TL_READ_DMA_SPLIT_LENGTH_DIAGNOSTIC_READ_DMA_SPLIT_INITIAL_BYTE_COUNT_SHIFT 0 /*************************************************************************** *XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC - XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC Register ***************************************************************************/ /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: REG_SM_R0_R3 [31:31] */ #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_MASK 0x80000000 #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_REG_SM_R0_R3_SHIFT 31 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TLP_TRANSMITTER_DATA_STATE_MACHINE [30:28] */ #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_MASK 0x70000000 #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_DATA_STATE_MACHINE_SHIFT 28 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE [27:23] */ #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_MASK 0x0f800000 #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TLP_TRANSMITTER_ARBITRATION_STATE_MACHINE_SHIFT 23 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: RESERVED_0 [22:07] */ #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_MASK 0x007fff80 #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_RESERVED_0_SHIFT 7 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: READ_DMA_RAW_REQUEST [06:06] */ #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_MASK 0x00000040 #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_RAW_REQUEST_SHIFT 6 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: WRITE_DMA_RAW_REQUEST [05:05] */ #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_MASK 0x00000020 #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_RAW_REQUEST_SHIFT 5 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: INTERRUPT_MSG_GATED_REQUEST [04:04] */ #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_MASK 0x00000010 #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_INTERRUPT_MSG_GATED_REQUEST_SHIFT 4 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: MSI_DMA_GATED_REQUEST [03:03] */ #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_MASK 0x00000008 #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_MSI_DMA_GATED_REQUEST_SHIFT 3 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: TARGET_COMPLETION_OR_MSG_GATED_REQUEST [02:02] */ #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_MASK 0x00000004 #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_TARGET_COMPLETION_OR_MSG_GATED_REQUEST_SHIFT 2 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: READ_DMA_GATED_REQUEST [01:01] */ #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_MASK 0x00000002 #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_READ_DMA_GATED_REQUEST_SHIFT 1 /* PCIE_TL :: XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC :: WRITE_DMA_GATED_REQUEST [00:00] */ #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_MASK 0x00000001 #define BCHP_PCIE_TL_XMT_STATE_MACHINES_AND_REQUEST_DIAGNOSTIC_WRITE_DMA_GATED_REQUEST_SHIFT 0 /*************************************************************************** *DMA_COMPLETION_MISC__DIAGNOSTIC - DMA_COMPLETION_MISC__DIAGNOSTIC Register ***************************************************************************/ /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: REG_DMA_CMPT_MISC2 [31:29] */ #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_MASK 0xe0000000 #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_REG_DMA_CMPT_MISC2_SHIFT 29 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_BYTE_LENGTH_REMAINING [28:16] */ #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_MASK 0x1fff0000 #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_BYTE_LENGTH_REMAINING_SHIFT 16 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: NOT_USED [15:15] */ #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_MASK 0x00008000 #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_NOT_USED_SHIFT 15 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED [14:14] */ #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_MASK 0x00004000 #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_SPLITCTL_GENERATED_SHIFT 14 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED [13:13] */ #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_MASK 0x00002000 #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_LAST_COMPLETION_TLP_INDICATOR_DMA_CMPT_GENERATED_SHIFT 13 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1 [12:12] */ #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_MASK 0x00001000 #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_DW_LENGTH_REMAINING_IN_CURRENT_COMPLETION_TLP_IS_GREATER_THAN_1_SHIFT 12 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST [11:11] */ #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_MASK 0x00000800 #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_TRANSACTION_ACTIVE_SPLIT_PENDING_BLOCK_REQUEST_SHIFT 11 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS [10:10] */ #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_MASK 0x00000400 #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_WITHOUT_BC_LADDR_CHECKS_SHIFT 10 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TLP_MATCHES_REQUEST_FULLY [09:09] */ #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_MASK 0x00000200 #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TLP_MATCHES_REQUEST_FULLY_SHIFT 9 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: SPLIT_DW_DATA_VALID_ADDRESS_ACK [08:08] */ #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_MASK 0x00000100 #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_SPLIT_DW_DATA_VALID_ADDRESS_ACK_SHIFT 8 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER [07:04] */ #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_MASK 0x000000f0 #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_COMPLETION_TOO_MUCH_DATA_ERROR_COUNTER_SHIFT 4 /* PCIE_TL :: DMA_COMPLETION_MISC__DIAGNOSTIC :: FRAME_DEAD_TIME_ERROR_COUNTER [03:00] */ #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_MASK 0x0000000f #define BCHP_PCIE_TL_DMA_COMPLETION_MISC__DIAGNOSTIC_FRAME_DEAD_TIME_ERROR_COUNTER_SHIFT 0 /*************************************************************************** *SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC - SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC Register ***************************************************************************/ /* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: REG_SPLITCTL_MISC0 [31:29] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_MASK 0xe0000000 #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_REG_SPLITCTL_MISC0_SHIFT 29 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING [28:16] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_MASK 0x1fff0000 #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_BYTE_COUNT_REMAINING_SHIFT 16 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID [15:00] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_MASK 0x0000ffff #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_0_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_REQUESTER_ID_SHIFT 0 /*************************************************************************** *SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC - SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC Register ***************************************************************************/ /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: REG_SPLITCTL_MISC1 [31:16] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_MASK 0xffff0000 #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_REG_SPLITCTL_MISC1_SHIFT 16 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: RESERVED_0 [15:15] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_MASK 0x00008000 #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_0_SHIFT 15 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS [14:08] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_MASK 0x00007f00 #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_LOWER_ADDRESS_SHIFT 8 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: RESERVED_1 [07:07] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_MASK 0x00000080 #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_RESERVED_1_SHIFT 7 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE [06:05] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_MASK 0x00000060 #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_RESULT_FOR_EXPECTED_ATTRIBUTE_SHIFT 5 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC :: LOOKUP_TAG [04:00] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_MASK 0x0000001f #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_1_DIAGNOSTIC_LOOKUP_TAG_SHIFT 0 /*************************************************************************** *SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC - SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC Register ***************************************************************************/ /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: REG_SPLITCTL_MISC2 [31:31] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_MASK 0x80000000 #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_REG_SPLITCTL_MISC2_SHIFT 31 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS [30:30] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_MASK 0x40000000 #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_EXPECTED_LOWER_ADDRESS_SHIFT 30 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: COMPLETION_TLP_MATCHES_VALID_TAG [29:29] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_MASK 0x20000000 #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_COMPLETION_TLP_MATCHES_VALID_TAG_SHIFT 29 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: UPDATED_BYTE_COUNT [28:16] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_MASK 0x1fff0000 #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_UPDATED_BYTE_COUNT_SHIFT 16 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: RESERVED_0 [15:08] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_MASK 0x0000ff00 #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_RESERVED_0_SHIFT 8 /* PCIE_TL :: SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC :: SPLIT_TABLE_VALID_ARRAY [07:00] */ #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_MASK 0x000000ff #define BCHP_PCIE_TL_SPLIT_CONTROLLER_MISC_2_DIAGNOSTIC_SPLIT_TABLE_VALID_ARRAY_SHIFT 0 /*************************************************************************** *TL_BUS_NO_DEV__NO__FUNC__NO - TL_BUS_NO_DEV__NO__FUNC__NO Register ***************************************************************************/ /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: RESERVED_0 [31:17] */ #define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_MASK 0xfffe0000 #define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_RESERVED_0_SHIFT 17 /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: CONFIG_WRITE_INDICATER [16:16] */ #define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_MASK 0x00010000 #define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_CONFIG_WRITE_INDICATER_SHIFT 16 /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: BUS_NUMBER [15:08] */ #define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_MASK 0x0000ff00 #define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_BUS_NUMBER_SHIFT 8 /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: DEVICE_NUMBER [07:03] */ #define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_MASK 0x000000f8 #define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_DEVICE_NUMBER_SHIFT 3 /* PCIE_TL :: TL_BUS_NO_DEV__NO__FUNC__NO :: FUNCTION_NUMBER [02:00] */ #define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_MASK 0x00000007 #define BCHP_PCIE_TL_TL_BUS_NO_DEV__NO__FUNC__NO_FUNCTION_NUMBER_SHIFT 0 /*************************************************************************** *TL_DEBUG - TL_DEBUG Register ***************************************************************************/ /* PCIE_TL :: TL_DEBUG :: A4_DEVICE_INDICATION_BIT [31:31] */ #define BCHP_PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_MASK 0x80000000 #define BCHP_PCIE_TL_TL_DEBUG_A4_DEVICE_INDICATION_BIT_SHIFT 31 /* PCIE_TL :: TL_DEBUG :: B1_DEVICE_INDICATION_BIT [30:30] */ #define BCHP_PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_MASK 0x40000000 #define BCHP_PCIE_TL_TL_DEBUG_B1_DEVICE_INDICATION_BIT_SHIFT 30 /* PCIE_TL :: TL_DEBUG :: RESERVED_0 [29:00] */ #define BCHP_PCIE_TL_TL_DEBUG_RESERVED_0_MASK 0x3fffffff #define BCHP_PCIE_TL_TL_DEBUG_RESERVED_0_SHIFT 0 #endif /* #ifndef BCHP_PCIE_TL_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016700000000000011571 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_secure_intr2.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_m0000644000175000017500000006720611610313111031036 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_wrap_misc_secure_intr2.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:23p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:01 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_wrap_misc_secure_intr2.h $ * * Hydra_Software_Devel/1 7/17/09 8:23p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_WRAP_MISC_SECURE_INTR2_H__ #define BCHP_WRAP_MISC_SECURE_INTR2_H__ /*************************************************************************** *WRAP_MISC_SECURE_INTR2 - MISC block secure Level 2 Interrupt Controller ***************************************************************************/ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS 0x000ff500 /* CPU interrupt Status Register */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET 0x000ff504 /* CPU interrupt Set Register */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR 0x000ff508 /* CPU interrupt Clear Register */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS 0x000ff50c /* CPU interrupt Mask Status Register */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET 0x000ff510 /* CPU interrupt Mask Set Register */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR 0x000ff514 /* CPU interrupt Mask Clear Register */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS 0x000ff518 /* PCI interrupt Status Register */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET 0x000ff51c /* PCI interrupt Set Register */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR 0x000ff520 /* PCI interrupt Clear Register */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS 0x000ff524 /* PCI interrupt Mask Status Register */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET 0x000ff528 /* PCI interrupt Mask Set Register */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR 0x000ff52c /* PCI interrupt Mask Clear Register */ /*************************************************************************** *CPU_STATUS - CPU interrupt Status Register ***************************************************************************/ /* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: reserved0 [31:09] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_reserved0_MASK 0xfffffe00 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_reserved0_SHIFT 9 /* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: STARCH_SECURE_INTR [08:08] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_STARCH_SECURE_INTR_MASK 0x00000100 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_STARCH_SECURE_INTR_SHIFT 8 /* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: GISB_SECURE_BREAKPOINT_INTR [07:07] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_GISB_SECURE_BREAKPOINT_INTR_MASK 0x00000080 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_GISB_SECURE_BREAKPOINT_INTR_SHIFT 7 /* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: SHARF_SECURE_INTR [06:06] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_SHARF_SECURE_INTR_MASK 0x00000040 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_SHARF_SECURE_INTR_SHIFT 6 /* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: XPT_WR_CHECKER_INTR [05:05] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_XPT_WR_CHECKER_INTR_MASK 0x00000020 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_XPT_WR_CHECKER_INTR_SHIFT 5 /* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: AVD_VICH_INTR [04:02] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_AVD_VICH_INTR_MASK 0x0000001c #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_AVD_VICH_INTR_SHIFT 2 /* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: ARB_WRITE_CHECKER_INTR [01:01] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_ARB_WRITE_CHECKER_INTR_MASK 0x00000002 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_ARB_WRITE_CHECKER_INTR_SHIFT 1 /* WRAP_MISC_SECURE_INTR2 :: CPU_STATUS :: ARB_SARCH_INTR [00:00] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_ARB_SARCH_INTR_MASK 0x00000001 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_STATUS_ARB_SARCH_INTR_SHIFT 0 /*************************************************************************** *CPU_SET - CPU interrupt Set Register ***************************************************************************/ /* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: reserved0 [31:09] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_reserved0_MASK 0xfffffe00 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_reserved0_SHIFT 9 /* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: STARCH_SECURE_INTR [08:08] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_STARCH_SECURE_INTR_MASK 0x00000100 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_STARCH_SECURE_INTR_SHIFT 8 /* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: GISB_SECURE_BREAKPOINT_INTR [07:07] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_GISB_SECURE_BREAKPOINT_INTR_MASK 0x00000080 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_GISB_SECURE_BREAKPOINT_INTR_SHIFT 7 /* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: SHARF_SECURE_INTR [06:06] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_SHARF_SECURE_INTR_MASK 0x00000040 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_SHARF_SECURE_INTR_SHIFT 6 /* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: XPT_WR_CHECKER_INTR [05:05] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_XPT_WR_CHECKER_INTR_MASK 0x00000020 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_XPT_WR_CHECKER_INTR_SHIFT 5 /* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: AVD_VICH_INTR [04:02] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_AVD_VICH_INTR_MASK 0x0000001c #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_AVD_VICH_INTR_SHIFT 2 /* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: ARB_WRITE_CHECKER_INTR [01:01] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_ARB_WRITE_CHECKER_INTR_MASK 0x00000002 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_ARB_WRITE_CHECKER_INTR_SHIFT 1 /* WRAP_MISC_SECURE_INTR2 :: CPU_SET :: ARB_SARCH_INTR [00:00] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_ARB_SARCH_INTR_MASK 0x00000001 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_SET_ARB_SARCH_INTR_SHIFT 0 /*************************************************************************** *CPU_CLEAR - CPU interrupt Clear Register ***************************************************************************/ /* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: reserved0 [31:09] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_reserved0_MASK 0xfffffe00 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_reserved0_SHIFT 9 /* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: STARCH_SECURE_INTR [08:08] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_STARCH_SECURE_INTR_MASK 0x00000100 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_STARCH_SECURE_INTR_SHIFT 8 /* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: GISB_SECURE_BREAKPOINT_INTR [07:07] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_GISB_SECURE_BREAKPOINT_INTR_MASK 0x00000080 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_GISB_SECURE_BREAKPOINT_INTR_SHIFT 7 /* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: SHARF_SECURE_INTR [06:06] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_SHARF_SECURE_INTR_MASK 0x00000040 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_SHARF_SECURE_INTR_SHIFT 6 /* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: XPT_WR_CHECKER_INTR [05:05] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_XPT_WR_CHECKER_INTR_MASK 0x00000020 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_XPT_WR_CHECKER_INTR_SHIFT 5 /* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: AVD_VICH_INTR [04:02] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_AVD_VICH_INTR_MASK 0x0000001c #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_AVD_VICH_INTR_SHIFT 2 /* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: ARB_WRITE_CHECKER_INTR [01:01] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_ARB_WRITE_CHECKER_INTR_MASK 0x00000002 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_ARB_WRITE_CHECKER_INTR_SHIFT 1 /* WRAP_MISC_SECURE_INTR2 :: CPU_CLEAR :: ARB_SARCH_INTR [00:00] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_ARB_SARCH_INTR_MASK 0x00000001 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_CLEAR_ARB_SARCH_INTR_SHIFT 0 /*************************************************************************** *CPU_MASK_STATUS - CPU interrupt Mask Status Register ***************************************************************************/ /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:09] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_reserved0_MASK 0xfffffe00 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_reserved0_SHIFT 9 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: STARCH_SECURE_MASK [08:08] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_STARCH_SECURE_MASK_MASK 0x00000100 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_STARCH_SECURE_MASK_SHIFT 8 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: GISB_SECURE_BREAKPOINT_MASK [07:07] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_GISB_SECURE_BREAKPOINT_MASK_MASK 0x00000080 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_GISB_SECURE_BREAKPOINT_MASK_SHIFT 7 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: SHARF_SECURE_MASK [06:06] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_SHARF_SECURE_MASK_MASK 0x00000040 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_SHARF_SECURE_MASK_SHIFT 6 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: XPT_WR_CHECKER_MASK [05:05] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_XPT_WR_CHECKER_MASK_MASK 0x00000020 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_XPT_WR_CHECKER_MASK_SHIFT 5 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: AVD_VICH_MASK [04:02] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_AVD_VICH_MASK_MASK 0x0000001c #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_AVD_VICH_MASK_SHIFT 2 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: ARB_WRITE_CHECKER_MASK [01:01] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_ARB_WRITE_CHECKER_MASK_MASK 0x00000002 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_ARB_WRITE_CHECKER_MASK_SHIFT 1 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_STATUS :: ARB_SARCH_MASK [00:00] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_ARB_SARCH_MASK_MASK 0x00000001 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_STATUS_ARB_SARCH_MASK_SHIFT 0 /*************************************************************************** *CPU_MASK_SET - CPU interrupt Mask Set Register ***************************************************************************/ /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: reserved0 [31:09] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_reserved0_MASK 0xfffffe00 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_reserved0_SHIFT 9 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: STARCH_SECURE_MASK [08:08] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_STARCH_SECURE_MASK_MASK 0x00000100 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_STARCH_SECURE_MASK_SHIFT 8 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: GISB_SECURE_BREAKPOINT_MASK [07:07] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_GISB_SECURE_BREAKPOINT_MASK_MASK 0x00000080 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_GISB_SECURE_BREAKPOINT_MASK_SHIFT 7 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: SHARF_SECURE_MASK [06:06] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_SHARF_SECURE_MASK_MASK 0x00000040 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_SHARF_SECURE_MASK_SHIFT 6 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: XPT_WR_CHECKER_MASK [05:05] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_XPT_WR_CHECKER_MASK_MASK 0x00000020 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_XPT_WR_CHECKER_MASK_SHIFT 5 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: AVD_VICH_MASK [04:02] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_AVD_VICH_MASK_MASK 0x0000001c #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_AVD_VICH_MASK_SHIFT 2 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: ARB_WRITE_CHECKER_MASK [01:01] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_ARB_WRITE_CHECKER_MASK_MASK 0x00000002 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_ARB_WRITE_CHECKER_MASK_SHIFT 1 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_SET :: ARB_SARCH_MASK [00:00] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_ARB_SARCH_MASK_MASK 0x00000001 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_SET_ARB_SARCH_MASK_SHIFT 0 /*************************************************************************** *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register ***************************************************************************/ /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:09] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_reserved0_MASK 0xfffffe00 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT 9 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: STARCH_SECURE_MASK [08:08] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_STARCH_SECURE_MASK_MASK 0x00000100 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_STARCH_SECURE_MASK_SHIFT 8 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: GISB_SECURE_BREAKPOINT_MASK [07:07] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_GISB_SECURE_BREAKPOINT_MASK_MASK 0x00000080 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_GISB_SECURE_BREAKPOINT_MASK_SHIFT 7 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: SHARF_SECURE_MASK [06:06] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_SHARF_SECURE_MASK_MASK 0x00000040 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_SHARF_SECURE_MASK_SHIFT 6 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: XPT_WR_CHECKER_MASK [05:05] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_XPT_WR_CHECKER_MASK_MASK 0x00000020 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_XPT_WR_CHECKER_MASK_SHIFT 5 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: AVD_VICH_MASK [04:02] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_AVD_VICH_MASK_MASK 0x0000001c #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_AVD_VICH_MASK_SHIFT 2 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: ARB_WRITE_CHECKER_MASK [01:01] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_ARB_WRITE_CHECKER_MASK_MASK 0x00000002 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_ARB_WRITE_CHECKER_MASK_SHIFT 1 /* WRAP_MISC_SECURE_INTR2 :: CPU_MASK_CLEAR :: ARB_SARCH_MASK [00:00] */ #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_ARB_SARCH_MASK_MASK 0x00000001 #define BCHP_WRAP_MISC_SECURE_INTR2_CPU_MASK_CLEAR_ARB_SARCH_MASK_SHIFT 0 /*************************************************************************** *PCI_STATUS - PCI interrupt Status Register ***************************************************************************/ /* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: reserved0 [31:09] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_reserved0_MASK 0xfffffe00 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_reserved0_SHIFT 9 /* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: STARCH_SECURE_INTR [08:08] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_STARCH_SECURE_INTR_MASK 0x00000100 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_STARCH_SECURE_INTR_SHIFT 8 /* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: GISB_SECURE_BREAKPOINT_INTR [07:07] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_GISB_SECURE_BREAKPOINT_INTR_MASK 0x00000080 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_GISB_SECURE_BREAKPOINT_INTR_SHIFT 7 /* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: SHARF_SECURE_INTR [06:06] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_SHARF_SECURE_INTR_MASK 0x00000040 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_SHARF_SECURE_INTR_SHIFT 6 /* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: XPT_WR_CHECKER_INTR [05:05] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_XPT_WR_CHECKER_INTR_MASK 0x00000020 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_XPT_WR_CHECKER_INTR_SHIFT 5 /* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: AVD_VICH_INTR [04:02] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_AVD_VICH_INTR_MASK 0x0000001c #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_AVD_VICH_INTR_SHIFT 2 /* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: ARB_WRITE_CHECKER_INTR [01:01] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_ARB_WRITE_CHECKER_INTR_MASK 0x00000002 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_ARB_WRITE_CHECKER_INTR_SHIFT 1 /* WRAP_MISC_SECURE_INTR2 :: PCI_STATUS :: ARB_SARCH_INTR [00:00] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_ARB_SARCH_INTR_MASK 0x00000001 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_STATUS_ARB_SARCH_INTR_SHIFT 0 /*************************************************************************** *PCI_SET - PCI interrupt Set Register ***************************************************************************/ /* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: reserved0 [31:09] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_reserved0_MASK 0xfffffe00 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_reserved0_SHIFT 9 /* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: STARCH_SECURE_INTR [08:08] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_STARCH_SECURE_INTR_MASK 0x00000100 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_STARCH_SECURE_INTR_SHIFT 8 /* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: GISB_SECURE_BREAKPOINT_INTR [07:07] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_GISB_SECURE_BREAKPOINT_INTR_MASK 0x00000080 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_GISB_SECURE_BREAKPOINT_INTR_SHIFT 7 /* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: SHARF_SECURE_INTR [06:06] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_SHARF_SECURE_INTR_MASK 0x00000040 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_SHARF_SECURE_INTR_SHIFT 6 /* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: XPT_WR_CHECKER_INTR [05:05] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_XPT_WR_CHECKER_INTR_MASK 0x00000020 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_XPT_WR_CHECKER_INTR_SHIFT 5 /* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: AVD_VICH_INTR [04:02] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_AVD_VICH_INTR_MASK 0x0000001c #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_AVD_VICH_INTR_SHIFT 2 /* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: ARB_WRITE_CHECKER_INTR [01:01] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_ARB_WRITE_CHECKER_INTR_MASK 0x00000002 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_ARB_WRITE_CHECKER_INTR_SHIFT 1 /* WRAP_MISC_SECURE_INTR2 :: PCI_SET :: ARB_SARCH_INTR [00:00] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_ARB_SARCH_INTR_MASK 0x00000001 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_SET_ARB_SARCH_INTR_SHIFT 0 /*************************************************************************** *PCI_CLEAR - PCI interrupt Clear Register ***************************************************************************/ /* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: reserved0 [31:09] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_reserved0_MASK 0xfffffe00 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_reserved0_SHIFT 9 /* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: STARCH_SECURE_INTR [08:08] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_STARCH_SECURE_INTR_MASK 0x00000100 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_STARCH_SECURE_INTR_SHIFT 8 /* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: GISB_SECURE_BREAKPOINT_INTR [07:07] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_GISB_SECURE_BREAKPOINT_INTR_MASK 0x00000080 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_GISB_SECURE_BREAKPOINT_INTR_SHIFT 7 /* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: SHARF_SECURE_INTR [06:06] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_SHARF_SECURE_INTR_MASK 0x00000040 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_SHARF_SECURE_INTR_SHIFT 6 /* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: XPT_WR_CHECKER_INTR [05:05] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_XPT_WR_CHECKER_INTR_MASK 0x00000020 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_XPT_WR_CHECKER_INTR_SHIFT 5 /* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: AVD_VICH_INTR [04:02] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_AVD_VICH_INTR_MASK 0x0000001c #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_AVD_VICH_INTR_SHIFT 2 /* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: ARB_WRITE_CHECKER_INTR [01:01] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_ARB_WRITE_CHECKER_INTR_MASK 0x00000002 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_ARB_WRITE_CHECKER_INTR_SHIFT 1 /* WRAP_MISC_SECURE_INTR2 :: PCI_CLEAR :: ARB_SARCH_INTR [00:00] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_ARB_SARCH_INTR_MASK 0x00000001 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_CLEAR_ARB_SARCH_INTR_SHIFT 0 /*************************************************************************** *PCI_MASK_STATUS - PCI interrupt Mask Status Register ***************************************************************************/ /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:09] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_reserved0_MASK 0xfffffe00 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_reserved0_SHIFT 9 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: STARCH_SECURE_MASK [08:08] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_STARCH_SECURE_MASK_MASK 0x00000100 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_STARCH_SECURE_MASK_SHIFT 8 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: GISB_SECURE_BREAKPOINT_MASK [07:07] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_GISB_SECURE_BREAKPOINT_MASK_MASK 0x00000080 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_GISB_SECURE_BREAKPOINT_MASK_SHIFT 7 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: SHARF_SECURE_MASK [06:06] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_SHARF_SECURE_MASK_MASK 0x00000040 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_SHARF_SECURE_MASK_SHIFT 6 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: XPT_WR_CHECKER_MASK [05:05] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_XPT_WR_CHECKER_MASK_MASK 0x00000020 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_XPT_WR_CHECKER_MASK_SHIFT 5 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: AVD_VICH_MASK [04:02] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_AVD_VICH_MASK_MASK 0x0000001c #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_AVD_VICH_MASK_SHIFT 2 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: ARB_WRITE_CHECKER_MASK [01:01] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_ARB_WRITE_CHECKER_MASK_MASK 0x00000002 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_ARB_WRITE_CHECKER_MASK_SHIFT 1 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_STATUS :: ARB_SARCH_MASK [00:00] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_ARB_SARCH_MASK_MASK 0x00000001 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_STATUS_ARB_SARCH_MASK_SHIFT 0 /*************************************************************************** *PCI_MASK_SET - PCI interrupt Mask Set Register ***************************************************************************/ /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: reserved0 [31:09] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_reserved0_MASK 0xfffffe00 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_reserved0_SHIFT 9 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: STARCH_SECURE_MASK [08:08] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_STARCH_SECURE_MASK_MASK 0x00000100 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_STARCH_SECURE_MASK_SHIFT 8 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: GISB_SECURE_BREAKPOINT_MASK [07:07] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_GISB_SECURE_BREAKPOINT_MASK_MASK 0x00000080 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_GISB_SECURE_BREAKPOINT_MASK_SHIFT 7 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: SHARF_SECURE_MASK [06:06] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_SHARF_SECURE_MASK_MASK 0x00000040 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_SHARF_SECURE_MASK_SHIFT 6 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: XPT_WR_CHECKER_MASK [05:05] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_XPT_WR_CHECKER_MASK_MASK 0x00000020 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_XPT_WR_CHECKER_MASK_SHIFT 5 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: AVD_VICH_MASK [04:02] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_AVD_VICH_MASK_MASK 0x0000001c #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_AVD_VICH_MASK_SHIFT 2 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: ARB_WRITE_CHECKER_MASK [01:01] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_ARB_WRITE_CHECKER_MASK_MASK 0x00000002 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_ARB_WRITE_CHECKER_MASK_SHIFT 1 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_SET :: ARB_SARCH_MASK [00:00] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_ARB_SARCH_MASK_MASK 0x00000001 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_SET_ARB_SARCH_MASK_SHIFT 0 /*************************************************************************** *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register ***************************************************************************/ /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:09] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_reserved0_MASK 0xfffffe00 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT 9 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: STARCH_SECURE_MASK [08:08] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_STARCH_SECURE_MASK_MASK 0x00000100 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_STARCH_SECURE_MASK_SHIFT 8 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: GISB_SECURE_BREAKPOINT_MASK [07:07] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_GISB_SECURE_BREAKPOINT_MASK_MASK 0x00000080 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_GISB_SECURE_BREAKPOINT_MASK_SHIFT 7 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: SHARF_SECURE_MASK [06:06] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_SHARF_SECURE_MASK_MASK 0x00000040 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_SHARF_SECURE_MASK_SHIFT 6 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: XPT_WR_CHECKER_MASK [05:05] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_XPT_WR_CHECKER_MASK_MASK 0x00000020 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_XPT_WR_CHECKER_MASK_SHIFT 5 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: AVD_VICH_MASK [04:02] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_AVD_VICH_MASK_MASK 0x0000001c #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_AVD_VICH_MASK_SHIFT 2 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: ARB_WRITE_CHECKER_MASK [01:01] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_ARB_WRITE_CHECKER_MASK_MASK 0x00000002 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_ARB_WRITE_CHECKER_MASK_SHIFT 1 /* WRAP_MISC_SECURE_INTR2 :: PCI_MASK_CLEAR :: ARB_SARCH_MASK [00:00] */ #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_ARB_SARCH_MASK_MASK 0x00000001 #define BCHP_WRAP_MISC_SECURE_INTR2_PCI_MASK_CLEAR_ARB_SARCH_MASK_SHIFT 0 #endif /* #ifndef BCHP_WRAP_MISC_SECURE_INTR2_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016100000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb_sec.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gi0000644000175000017500000000616111610313111031026 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_sun_gisb_arb_sec.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:19p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:22 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_gisb_arb_sec.h $ * * Hydra_Software_Devel/1 7/17/09 8:19p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_SUN_GISB_ARB_SEC_H__ #define BCHP_SUN_GISB_ARB_SEC_H__ /*************************************************************************** *SUN_GISB_ARB_SEC - GISB Arbiter secure registers ***************************************************************************/ #define BCHP_SUN_GISB_ARB_SEC_RSV_S 0x00460000 /* RESERVED */ #define BCHP_SUN_GISB_ARB_SEC_RSV_E 0x00460064 /* RESERVED */ /*************************************************************************** *RSV_S - RESERVED ***************************************************************************/ /* SUN_GISB_ARB_SEC :: RSV_S :: reserved0 [31:00] */ #define BCHP_SUN_GISB_ARB_SEC_RSV_S_reserved0_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_SEC_RSV_S_reserved0_SHIFT 0 /*************************************************************************** *RSV_E - RESERVED ***************************************************************************/ /* SUN_GISB_ARB_SEC :: RSV_E :: reserved0 [31:00] */ #define BCHP_SUN_GISB_ARB_SEC_RSV_E_reserved0_MASK 0xffffffff #define BCHP_SUN_GISB_ARB_SEC_RSV_E_reserved0_SHIFT 0 #endif /* #ifndef BCHP_SUN_GISB_ARB_SEC_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000017000000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge_axi_slave.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_armcr40000644000175000017500000001013211610313111030723 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_armcr4_bridge_axi_slave.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:28p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:10 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_armcr4_bridge_axi_slave.h $ * * Hydra_Software_Devel/1 7/17/09 8:28p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_ARMCR4_BRIDGE_AXI_SLAVE_H__ #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_H__ /*************************************************************************** *ARMCR4_BRIDGE_AXI_SLAVE - AXI Slave indirect registers ***************************************************************************/ #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR 0x000e1000 /* AXI Slave address register */ #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ACCESS 0x000e1004 /* AXI Slave write/read access register */ /*************************************************************************** *REG_ADDR - AXI Slave address register ***************************************************************************/ /* ARMCR4_BRIDGE_AXI_SLAVE :: REG_ADDR :: reserved0 [31:27] */ #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_reserved0_MASK 0xf8000000 #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_reserved0_SHIFT 27 /* ARMCR4_BRIDGE_AXI_SLAVE :: REG_ADDR :: RAM_sel [26:23] */ #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_RAM_sel_MASK 0x07800000 #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_RAM_sel_SHIFT 23 /* ARMCR4_BRIDGE_AXI_SLAVE :: REG_ADDR :: Type_sel [22:19] */ #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_Type_sel_MASK 0x00780000 #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_Type_sel_SHIFT 19 /* ARMCR4_BRIDGE_AXI_SLAVE :: REG_ADDR :: Way_sel [18:15] */ #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_Way_sel_MASK 0x00078000 #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_Way_sel_SHIFT 15 /* ARMCR4_BRIDGE_AXI_SLAVE :: REG_ADDR :: Address [14:00] */ #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_Address_MASK 0x00007fff #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ADDR_Address_SHIFT 0 /*************************************************************************** *REG_ACCESS - AXI Slave write/read access register ***************************************************************************/ /* ARMCR4_BRIDGE_AXI_SLAVE :: REG_ACCESS :: Access [31:00] */ #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ACCESS_Access_MASK 0xffffffff #define BCHP_ARMCR4_BRIDGE_AXI_SLAVE_REG_ACCESS_Access_SHIFT 0 #endif /* #ifndef BCHP_ARMCR4_BRIDGE_AXI_SLAVE_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015300000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xmemif.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xm0000644000175000017500000002774011610313111031067 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_xpt_xmemif.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:27p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:10 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_xmemif.h $ * * Hydra_Software_Devel/1 7/17/09 8:27p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_XPT_XMEMIF_H__ #define BCHP_XPT_XMEMIF_H__ /*************************************************************************** *XPT_XMEMIF - XPT XMEMIF Control Registers ***************************************************************************/ #define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_CDB 0x00202008 /* SCB Write Client select register for RAVE CDB */ #define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_ITB 0x0020200c /* SCB Write Client select register for RAVE ITB */ #define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE 0x00202040 /* SCB Write Client Arbiter Mode Control */ #define BCHP_XPT_XMEMIF_SCB_RD_ARB_MODE 0x00202044 /* SCB Read Client Arbiter Mode Control */ #define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF0 0x00202048 /* TM Control */ #define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF1 0x0020204c /* TM Control */ #define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF0 0x00202050 /* TM Control */ #define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF1 0x00202054 /* TM Control */ #define BCHP_XPT_XMEMIF_WR_DEBUG 0x00202058 /* Debug and Test register for XMEMIF write */ #define BCHP_XPT_XMEMIF_RD_DEBUG 0x0020205c /* Debug and Test register for XMEMIF read */ #define BCHP_XPT_XMEMIF_INTR_STATUS_REG 0x00202060 /* Interrupt Status Register */ #define BCHP_XPT_XMEMIF_INTR_STATUS_REG_EN 0x00202064 /* Interrupt Status Enable Register */ /*************************************************************************** *SCB_WR_ARB_SEL_RAVE_CDB - SCB Write Client select register for RAVE CDB ***************************************************************************/ /* XPT_XMEMIF :: SCB_WR_ARB_SEL_RAVE_CDB :: reserved0 [31:02] */ #define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_CDB_reserved0_MASK 0xfffffffc #define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_CDB_reserved0_SHIFT 2 /* XPT_XMEMIF :: SCB_WR_ARB_SEL_RAVE_CDB :: SCB_WR_CLIENT_SEL [01:00] */ #define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_CDB_SCB_WR_CLIENT_SEL_MASK 0x00000003 #define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_CDB_SCB_WR_CLIENT_SEL_SHIFT 0 /*************************************************************************** *SCB_WR_ARB_SEL_RAVE_ITB - SCB Write Client select register for RAVE ITB ***************************************************************************/ /* XPT_XMEMIF :: SCB_WR_ARB_SEL_RAVE_ITB :: reserved0 [31:02] */ #define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_ITB_reserved0_MASK 0xfffffffc #define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_ITB_reserved0_SHIFT 2 /* XPT_XMEMIF :: SCB_WR_ARB_SEL_RAVE_ITB :: SCB_WR_CLIENT_SEL [01:00] */ #define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_ITB_SCB_WR_CLIENT_SEL_MASK 0x00000003 #define BCHP_XPT_XMEMIF_SCB_WR_ARB_SEL_RAVE_ITB_SCB_WR_CLIENT_SEL_SHIFT 0 /*************************************************************************** *SCB_WR_ARB_MODE - SCB Write Client Arbiter Mode Control ***************************************************************************/ /* XPT_XMEMIF :: SCB_WR_ARB_MODE :: reserved0 [31:10] */ #define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_reserved0_MASK 0xfffffc00 #define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_reserved0_SHIFT 10 /* XPT_XMEMIF :: SCB_WR_ARB_MODE :: SCB_WR_1_ARB_MODE [09:08] */ #define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_SCB_WR_1_ARB_MODE_MASK 0x00000300 #define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_SCB_WR_1_ARB_MODE_SHIFT 8 /* XPT_XMEMIF :: SCB_WR_ARB_MODE :: reserved1 [07:02] */ #define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_reserved1_MASK 0x000000fc #define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_reserved1_SHIFT 2 /* XPT_XMEMIF :: SCB_WR_ARB_MODE :: SCB_WR_0_ARB_MODE [01:00] */ #define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_SCB_WR_0_ARB_MODE_MASK 0x00000003 #define BCHP_XPT_XMEMIF_SCB_WR_ARB_MODE_SCB_WR_0_ARB_MODE_SHIFT 0 /*************************************************************************** *SCB_RD_ARB_MODE - SCB Read Client Arbiter Mode Control ***************************************************************************/ /* XPT_XMEMIF :: SCB_RD_ARB_MODE :: reserved0 [31:02] */ #define BCHP_XPT_XMEMIF_SCB_RD_ARB_MODE_reserved0_MASK 0xfffffffc #define BCHP_XPT_XMEMIF_SCB_RD_ARB_MODE_reserved0_SHIFT 2 /* XPT_XMEMIF :: SCB_RD_ARB_MODE :: SCB_RD_0_ARB_MODE [01:00] */ #define BCHP_XPT_XMEMIF_SCB_RD_ARB_MODE_SCB_RD_0_ARB_MODE_MASK 0x00000003 #define BCHP_XPT_XMEMIF_SCB_RD_ARB_MODE_SCB_RD_0_ARB_MODE_SHIFT 0 /*************************************************************************** *TM_SCB_WR_DBUF0 - TM Control ***************************************************************************/ /* XPT_XMEMIF :: TM_SCB_WR_DBUF0 :: reserved0 [31:08] */ #define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF0_reserved0_MASK 0xffffff00 #define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF0_reserved0_SHIFT 8 /* XPT_XMEMIF :: TM_SCB_WR_DBUF0 :: TM [07:00] */ #define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF0_TM_MASK 0x000000ff #define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF0_TM_SHIFT 0 /*************************************************************************** *TM_SCB_WR_DBUF1 - TM Control ***************************************************************************/ /* XPT_XMEMIF :: TM_SCB_WR_DBUF1 :: reserved0 [31:08] */ #define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF1_reserved0_MASK 0xffffff00 #define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF1_reserved0_SHIFT 8 /* XPT_XMEMIF :: TM_SCB_WR_DBUF1 :: TM [07:00] */ #define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF1_TM_MASK 0x000000ff #define BCHP_XPT_XMEMIF_TM_SCB_WR_DBUF1_TM_SHIFT 0 /*************************************************************************** *TM_SCB_RD_DBUF0 - TM Control ***************************************************************************/ /* XPT_XMEMIF :: TM_SCB_RD_DBUF0 :: reserved0 [31:08] */ #define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF0_reserved0_MASK 0xffffff00 #define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF0_reserved0_SHIFT 8 /* XPT_XMEMIF :: TM_SCB_RD_DBUF0 :: TM [07:00] */ #define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF0_TM_MASK 0x000000ff #define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF0_TM_SHIFT 0 /*************************************************************************** *TM_SCB_RD_DBUF1 - TM Control ***************************************************************************/ /* XPT_XMEMIF :: TM_SCB_RD_DBUF1 :: reserved0 [31:08] */ #define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF1_reserved0_MASK 0xffffff00 #define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF1_reserved0_SHIFT 8 /* XPT_XMEMIF :: TM_SCB_RD_DBUF1 :: TM [07:00] */ #define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF1_TM_MASK 0x000000ff #define BCHP_XPT_XMEMIF_TM_SCB_RD_DBUF1_TM_SHIFT 0 /*************************************************************************** *WR_DEBUG - Debug and Test register for XMEMIF write ***************************************************************************/ /* XPT_XMEMIF :: WR_DEBUG :: reserved0 [31:17] */ #define BCHP_XPT_XMEMIF_WR_DEBUG_reserved0_MASK 0xfffe0000 #define BCHP_XPT_XMEMIF_WR_DEBUG_reserved0_SHIFT 17 /* XPT_XMEMIF :: WR_DEBUG :: SOFT_RESET [16:16] */ #define BCHP_XPT_XMEMIF_WR_DEBUG_SOFT_RESET_MASK 0x00010000 #define BCHP_XPT_XMEMIF_WR_DEBUG_SOFT_RESET_SHIFT 16 /* XPT_XMEMIF :: WR_DEBUG :: reserved1 [15:02] */ #define BCHP_XPT_XMEMIF_WR_DEBUG_reserved1_MASK 0x0000fffc #define BCHP_XPT_XMEMIF_WR_DEBUG_reserved1_SHIFT 2 /* XPT_XMEMIF :: WR_DEBUG :: WR_LCIF_ERROR [01:00] */ #define BCHP_XPT_XMEMIF_WR_DEBUG_WR_LCIF_ERROR_MASK 0x00000003 #define BCHP_XPT_XMEMIF_WR_DEBUG_WR_LCIF_ERROR_SHIFT 0 /*************************************************************************** *RD_DEBUG - Debug and Test register for XMEMIF read ***************************************************************************/ /* XPT_XMEMIF :: RD_DEBUG :: reserved0 [31:17] */ #define BCHP_XPT_XMEMIF_RD_DEBUG_reserved0_MASK 0xfffe0000 #define BCHP_XPT_XMEMIF_RD_DEBUG_reserved0_SHIFT 17 /* XPT_XMEMIF :: RD_DEBUG :: SOFT_RESET [16:16] */ #define BCHP_XPT_XMEMIF_RD_DEBUG_SOFT_RESET_MASK 0x00010000 #define BCHP_XPT_XMEMIF_RD_DEBUG_SOFT_RESET_SHIFT 16 /* XPT_XMEMIF :: RD_DEBUG :: reserved1 [15:03] */ #define BCHP_XPT_XMEMIF_RD_DEBUG_reserved1_MASK 0x0000fff8 #define BCHP_XPT_XMEMIF_RD_DEBUG_reserved1_SHIFT 3 /* XPT_XMEMIF :: RD_DEBUG :: RD_LCIF_ERROR [02:00] */ #define BCHP_XPT_XMEMIF_RD_DEBUG_RD_LCIF_ERROR_MASK 0x00000007 #define BCHP_XPT_XMEMIF_RD_DEBUG_RD_LCIF_ERROR_SHIFT 0 /*************************************************************************** *INTR_STATUS_REG - Interrupt Status Register ***************************************************************************/ /* XPT_XMEMIF :: INTR_STATUS_REG :: reserved0 [31:02] */ #define BCHP_XPT_XMEMIF_INTR_STATUS_REG_reserved0_MASK 0xfffffffc #define BCHP_XPT_XMEMIF_INTR_STATUS_REG_reserved0_SHIFT 2 /* XPT_XMEMIF :: INTR_STATUS_REG :: XMEMIF_WRITE_ERROR [01:01] */ #define BCHP_XPT_XMEMIF_INTR_STATUS_REG_XMEMIF_WRITE_ERROR_MASK 0x00000002 #define BCHP_XPT_XMEMIF_INTR_STATUS_REG_XMEMIF_WRITE_ERROR_SHIFT 1 /* XPT_XMEMIF :: INTR_STATUS_REG :: XMEMIF_READ_ERROR [00:00] */ #define BCHP_XPT_XMEMIF_INTR_STATUS_REG_XMEMIF_READ_ERROR_MASK 0x00000001 #define BCHP_XPT_XMEMIF_INTR_STATUS_REG_XMEMIF_READ_ERROR_SHIFT 0 /*************************************************************************** *INTR_STATUS_REG_EN - Interrupt Status Enable Register ***************************************************************************/ /* XPT_XMEMIF :: INTR_STATUS_REG_EN :: reserved0 [31:02] */ #define BCHP_XPT_XMEMIF_INTR_STATUS_REG_EN_reserved0_MASK 0xfffffffc #define BCHP_XPT_XMEMIF_INTR_STATUS_REG_EN_reserved0_SHIFT 2 /* XPT_XMEMIF :: INTR_STATUS_REG_EN :: INTR_STATUS_REG_EN [01:00] */ #define BCHP_XPT_XMEMIF_INTR_STATUS_REG_EN_INTR_STATUS_REG_EN_MASK 0x00000003 #define BCHP_XPT_XMEMIF_INTR_STATUS_REG_EN_INTR_STATUS_REG_EN_SHIFT 0 #endif /* #ifndef BCHP_XPT_XMEMIF_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015600000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_mcom_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000003416411610313111030771 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_mcom_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:05p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:36 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_mcom_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:05p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_MCOM_0_H__ #define BCHP_DECODE_MCOM_0_H__ /*************************************************************************** *DECODE_MCOM_0 ***************************************************************************/ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL 0x00800300 /* Motion Compensation Control */ #define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_A 0x00800304 /* Motion Compensation Source A */ #define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_B 0x00800308 /* Motion Compensation Source */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC 0x0080030c /* VC-1 Mocomp Picture-Level Control */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC 0x00800310 /* VC-1 Mocomp Bottom Pic */ #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL 0x00800314 /* Weighted Prediction Selection */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC 0x00800318 /* VC-1 Mocomp Back Pic */ #define BCHP_DECODE_MCOM_0_REG_MCOM_END 0x0080031c /* REG_MCOM_END */ /*************************************************************************** *REG_MCOM_CTL - Motion Compensation Control ***************************************************************************/ /* DECODE_MCOM_0 :: REG_MCOM_CTL :: Bintl [31:31] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Bintl_MASK 0x80000000 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Bintl_SHIFT 31 /* DECODE_MCOM_0 :: REG_MCOM_CTL :: Bref [30:24] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Bref_MASK 0x7f000000 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Bref_SHIFT 24 /* DECODE_MCOM_0 :: REG_MCOM_CTL :: Aintl [23:23] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Aintl_MASK 0x00800000 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Aintl_SHIFT 23 /* DECODE_MCOM_0 :: REG_MCOM_CTL :: ARef [22:16] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_ARef_MASK 0x007f0000 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_ARef_SHIFT 16 /* DECODE_MCOM_0 :: REG_MCOM_CTL :: SubBlock [15:12] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_SubBlock_MASK 0x0000f000 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_SubBlock_SHIFT 12 /* DECODE_MCOM_0 :: REG_MCOM_CTL :: BBot [11:11] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_BBot_MASK 0x00000800 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_BBot_SHIFT 11 /* DECODE_MCOM_0 :: REG_MCOM_CTL :: BFld [10:10] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_BFld_MASK 0x00000400 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_BFld_SHIFT 10 /* DECODE_MCOM_0 :: REG_MCOM_CTL :: ABot [09:09] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_ABot_MASK 0x00000200 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_ABot_SHIFT 9 /* DECODE_MCOM_0 :: REG_MCOM_CTL :: AFld [08:08] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_AFld_MASK 0x00000100 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_AFld_SHIFT 8 /* DECODE_MCOM_0 :: REG_MCOM_CTL :: YSize [07:06] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_YSize_MASK 0x000000c0 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_YSize_SHIFT 6 /* DECODE_MCOM_0 :: REG_MCOM_CTL :: XSize [05:04] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_XSize_MASK 0x00000030 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_XSize_SHIFT 4 /* DECODE_MCOM_0 :: REG_MCOM_CTL :: Luma [03:03] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Luma_MASK 0x00000008 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Luma_SHIFT 3 /* DECODE_MCOM_0 :: REG_MCOM_CTL :: Filter261 [02:02] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Filter261_MASK 0x00000004 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Filter261_SHIFT 2 /* DECODE_MCOM_0 :: REG_MCOM_CTL :: Mde [01:01] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Mde_MASK 0x00000002 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Mde_SHIFT 1 /* DECODE_MCOM_0 :: REG_MCOM_CTL :: Back [00:00] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Back_MASK 0x00000001 #define BCHP_DECODE_MCOM_0_REG_MCOM_CTL_Back_SHIFT 0 /*************************************************************************** *REG_MCOM_SRC_A - Motion Compensation Source A ***************************************************************************/ /* DECODE_MCOM_0 :: REG_MCOM_SRC_A :: YSrc [31:16] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_A_YSrc_MASK 0xffff0000 #define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_A_YSrc_SHIFT 16 /* DECODE_MCOM_0 :: REG_MCOM_SRC_A :: XSrc [15:00] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_A_XSrc_MASK 0x0000ffff #define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_A_XSrc_SHIFT 0 /*************************************************************************** *REG_MCOM_SRC_B - Motion Compensation Source ***************************************************************************/ /* DECODE_MCOM_0 :: REG_MCOM_SRC_B :: YSrc [31:16] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_B_YSrc_MASK 0xffff0000 #define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_B_YSrc_SHIFT 16 /* DECODE_MCOM_0 :: REG_MCOM_SRC_B :: XSrc [15:00] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_B_XSrc_MASK 0x0000ffff #define BCHP_DECODE_MCOM_0_REG_MCOM_SRC_B_XSrc_SHIFT 0 /*************************************************************************** *REG_WPRD_VC1_PIC - VC-1 Mocomp Picture-Level Control ***************************************************************************/ /* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: reserved0 [31:30] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_reserved0_MASK 0xc0000000 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_reserved0_SHIFT 30 /* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: ALT_PAD [29:29] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_ALT_PAD_MASK 0x20000000 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_ALT_PAD_SHIFT 29 /* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: reserved1 [28:28] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_reserved1_MASK 0x10000000 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_reserved1_SHIFT 28 /* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: SHIFT2 [27:22] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SHIFT2_MASK 0x0fc00000 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SHIFT2_SHIFT 22 /* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: SCALE2 [21:16] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SCALE2_MASK 0x003f0000 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SCALE2_SHIFT 16 /* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: SHIFT1 [15:10] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SHIFT1_MASK 0x0000fc00 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SHIFT1_SHIFT 10 /* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: SCALE1 [09:04] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SCALE1_MASK 0x000003f0 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_SCALE1_SHIFT 4 /* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: reserved2 [03:02] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_reserved2_MASK 0x0000000c #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_reserved2_SHIFT 2 /* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: BICUBIC [01:01] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_BICUBIC_MASK 0x00000002 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_BICUBIC_SHIFT 1 /* DECODE_MCOM_0 :: REG_WPRD_VC1_PIC :: RND [00:00] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_RND_MASK 0x00000001 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_PIC_RND_SHIFT 0 /*************************************************************************** *REG_WPRD_VC1_BOT_PIC - VC-1 Mocomp Bottom Pic ***************************************************************************/ /* DECODE_MCOM_0 :: REG_WPRD_VC1_BOT_PIC :: reserved0 [31:28] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_reserved0_MASK 0xf0000000 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_reserved0_SHIFT 28 /* DECODE_MCOM_0 :: REG_WPRD_VC1_BOT_PIC :: SHIFT2 [27:22] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SHIFT2_MASK 0x0fc00000 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SHIFT2_SHIFT 22 /* DECODE_MCOM_0 :: REG_WPRD_VC1_BOT_PIC :: SCALE2 [21:16] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SCALE2_MASK 0x003f0000 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SCALE2_SHIFT 16 /* DECODE_MCOM_0 :: REG_WPRD_VC1_BOT_PIC :: SHIFT1 [15:10] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SHIFT1_MASK 0x0000fc00 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SHIFT1_SHIFT 10 /* DECODE_MCOM_0 :: REG_WPRD_VC1_BOT_PIC :: SCALE1 [09:04] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SCALE1_MASK 0x000003f0 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_SCALE1_SHIFT 4 /* DECODE_MCOM_0 :: REG_WPRD_VC1_BOT_PIC :: reserved1 [03:00] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_reserved1_MASK 0x0000000f #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BOT_PIC_reserved1_SHIFT 0 /*************************************************************************** *REG_WPRD_SEL - Weighted Prediction Selection ***************************************************************************/ /* DECODE_MCOM_0 :: REG_WPRD_SEL :: reserved0 [31:30] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_reserved0_MASK 0xc0000000 #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_reserved0_SHIFT 30 /* DECODE_MCOM_0 :: REG_WPRD_SEL :: VecAWtSel0 [29:25] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecAWtSel0_MASK 0x3e000000 #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecAWtSel0_SHIFT 25 /* DECODE_MCOM_0 :: REG_WPRD_SEL :: VecBWtSel0 [24:16] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecBWtSel0_MASK 0x01ff0000 #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecBWtSel0_SHIFT 16 /* DECODE_MCOM_0 :: REG_WPRD_SEL :: Wt1 [15:15] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_Wt1_MASK 0x00008000 #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_Wt1_SHIFT 15 /* DECODE_MCOM_0 :: REG_WPRD_SEL :: reserved1 [14:14] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_reserved1_MASK 0x00004000 #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_reserved1_SHIFT 14 /* DECODE_MCOM_0 :: REG_WPRD_SEL :: VecAWtSel1 [13:09] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecAWtSel1_MASK 0x00003e00 #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecAWtSel1_SHIFT 9 /* DECODE_MCOM_0 :: REG_WPRD_SEL :: VecBWtSel1 [08:00] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecBWtSel1_MASK 0x000001ff #define BCHP_DECODE_MCOM_0_REG_WPRD_SEL_VecBWtSel1_SHIFT 0 /*************************************************************************** *REG_WPRD_VC1_BACK_PIC - VC-1 Mocomp Back Pic ***************************************************************************/ /* DECODE_MCOM_0 :: REG_WPRD_VC1_BACK_PIC :: reserved0 [31:16] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_reserved0_MASK 0xffff0000 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_reserved0_SHIFT 16 /* DECODE_MCOM_0 :: REG_WPRD_VC1_BACK_PIC :: Shift1 [15:10] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_Shift1_MASK 0x0000fc00 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_Shift1_SHIFT 10 /* DECODE_MCOM_0 :: REG_WPRD_VC1_BACK_PIC :: Scale1 [09:04] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_Scale1_MASK 0x000003f0 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_Scale1_SHIFT 4 /* DECODE_MCOM_0 :: REG_WPRD_VC1_BACK_PIC :: reserved1 [03:01] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_reserved1_MASK 0x0000000e #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_reserved1_SHIFT 1 /* DECODE_MCOM_0 :: REG_WPRD_VC1_BACK_PIC :: Bot [00:00] */ #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_Bot_MASK 0x00000001 #define BCHP_DECODE_MCOM_0_REG_WPRD_VC1_BACK_PIC_Bot_SHIFT 0 /*************************************************************************** *REG_MCOM_END - REG_MCOM_END ***************************************************************************/ /* DECODE_MCOM_0 :: REG_MCOM_END :: reserved0 [31:00] */ #define BCHP_DECODE_MCOM_0_REG_MCOM_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_MCOM_0_REG_MCOM_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_MCOM_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000014700000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_fe.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_fe0000644000175000017500000006323311610313111031032 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_xpt_fe.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:23p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:20 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_fe.h $ * * Hydra_Software_Devel/1 7/17/09 8:23p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_XPT_FE_H__ #define BCHP_XPT_FE_H__ /*************************************************************************** *XPT_FE - XPT FRONTEND Control Registers ***************************************************************************/ #define BCHP_XPT_FE_INTR_STATUS_REG 0x00208010 /* Interrupt Status Register */ #define BCHP_XPT_FE_INTR_STATUS_REG_EN 0x00208014 /* Interrupt Status Enable Register */ #define BCHP_XPT_FE_MAX_PID_CHANNEL 0x0020801c /* Maximum Pid Channel number register */ #define BCHP_XPT_FE_PSG_CFG 0x00208300 /* Passage Config Register */ #define BCHP_XPT_FE_PSG_RESET0 0x0020831c /* Passage Per PID Reset for Secondary PID Channels 0-31 Register */ #define BCHP_XPT_FE_PSG_RESET1 0x00208320 /* Passage Per PID Reset for Secondary PID Channels 32-63 Register */ #define BCHP_XPT_FE_PSG_RESET2 0x0020835c /* Passage Per PID Reset for Secondary PID Channels 64-95 Register */ #define BCHP_XPT_FE_PSG_RESET3 0x00208360 /* Passage Per PID Reset for Secondary PID Channels 96-127 Register */ #define BCHP_XPT_FE_PSG_PR_ERR0 0x00208374 /* Passage Per PID Protocol Error for PID Channels 0-31 Register */ #define BCHP_XPT_FE_PSG_PR_ERR1 0x00208378 /* Passage Per PID Protocol Error for PID Channels 32-63 Register */ #define BCHP_XPT_FE_PSG_PR_ERR2 0x0020837c /* Passage Per PID Protocol Error for PID Channels 95-64 Register */ #define BCHP_XPT_FE_PSG_PR_ERR3 0x00208380 /* Passage Per PID Protocol Error for PID Channels 127-96 Register */ #define BCHP_XPT_FE_PSG_PR_ERR_EN0 0x00208394 /* Passage Per PID Protocol Error Enable for PID Channels 0-31 Register */ #define BCHP_XPT_FE_PSG_PR_ERR_EN1 0x00208398 /* Passage Per PID Protocol Error Enable for PID Channels 32-63 Register */ #define BCHP_XPT_FE_PSG_PR_ERR_EN2 0x0020839c /* Passage Per PID Protocol Error Enable for PID Channels 64-95 Register */ #define BCHP_XPT_FE_PSG_PR_ERR_EN3 0x002083a0 /* Passage Per PID Protocol Error Enable for PID Channels 96-127 Register */ #define BCHP_XPT_FE_SCC_ERROR0 0x002083b4 /* Per PID Secondary CC Error for PID Channels 0-31 Register */ #define BCHP_XPT_FE_SCC_ERROR1 0x002083b8 /* Per PID Secondary CC Error for PID Channels 32-63 Register */ #define BCHP_XPT_FE_SCC_ERROR2 0x002083bc /* Per PID Secondary CC Error for PID Channels 64-95 Register */ #define BCHP_XPT_FE_SCC_ERROR3 0x002083c0 /* Per PID Secondary CC Error for PID Channels 96-127 Register */ #define BCHP_XPT_FE_PCC_ERROR0 0x002083d4 /* Per PID Primary CC Error for PID Channels 0-31 Register */ #define BCHP_XPT_FE_PCC_ERROR1 0x002083d8 /* Per PID Primary CC Error for PID Channels 32-63 Register */ #define BCHP_XPT_FE_PCC_ERROR2 0x002083dc /* Per PID Primary CC Error for PID Channels 64-95 Register */ #define BCHP_XPT_FE_PCC_ERROR3 0x002083e0 /* Per PID Primary CC Error for PID Channels 96-127 Register */ #define BCHP_XPT_FE_PID_ERR_SNIFFER 0x002083f4 /* PID Error Sniffer Register */ /*************************************************************************** *INTR_STATUS_REG - Interrupt Status Register ***************************************************************************/ /* XPT_FE :: INTR_STATUS_REG :: reserved0 [31:30] */ #define BCHP_XPT_FE_INTR_STATUS_REG_reserved0_MASK 0xc0000000 #define BCHP_XPT_FE_INTR_STATUS_REG_reserved0_SHIFT 30 /* XPT_FE :: INTR_STATUS_REG :: PSG_PROTOCOL_ERROR [29:29] */ #define BCHP_XPT_FE_INTR_STATUS_REG_PSG_PROTOCOL_ERROR_MASK 0x20000000 #define BCHP_XPT_FE_INTR_STATUS_REG_PSG_PROTOCOL_ERROR_SHIFT 29 /* XPT_FE :: INTR_STATUS_REG :: reserved1 [28:00] */ #define BCHP_XPT_FE_INTR_STATUS_REG_reserved1_MASK 0x1fffffff #define BCHP_XPT_FE_INTR_STATUS_REG_reserved1_SHIFT 0 /*************************************************************************** *INTR_STATUS_REG_EN - Interrupt Status Enable Register ***************************************************************************/ /* XPT_FE :: INTR_STATUS_REG_EN :: reserved0 [31:30] */ #define BCHP_XPT_FE_INTR_STATUS_REG_EN_reserved0_MASK 0xc0000000 #define BCHP_XPT_FE_INTR_STATUS_REG_EN_reserved0_SHIFT 30 /* XPT_FE :: INTR_STATUS_REG_EN :: INTR_STATUS_REG_EN [29:29] */ #define BCHP_XPT_FE_INTR_STATUS_REG_EN_INTR_STATUS_REG_EN_MASK 0x20000000 #define BCHP_XPT_FE_INTR_STATUS_REG_EN_INTR_STATUS_REG_EN_SHIFT 29 /* XPT_FE :: INTR_STATUS_REG_EN :: reserved1 [28:00] */ #define BCHP_XPT_FE_INTR_STATUS_REG_EN_reserved1_MASK 0x1fffffff #define BCHP_XPT_FE_INTR_STATUS_REG_EN_reserved1_SHIFT 0 /*************************************************************************** *MAX_PID_CHANNEL - Maximum Pid Channel number register ***************************************************************************/ /* XPT_FE :: MAX_PID_CHANNEL :: reserved0 [31:07] */ #define BCHP_XPT_FE_MAX_PID_CHANNEL_reserved0_MASK 0xffffff80 #define BCHP_XPT_FE_MAX_PID_CHANNEL_reserved0_SHIFT 7 /* XPT_FE :: MAX_PID_CHANNEL :: MAX_PID_CHANNEL [06:00] */ #define BCHP_XPT_FE_MAX_PID_CHANNEL_MAX_PID_CHANNEL_MASK 0x0000007f #define BCHP_XPT_FE_MAX_PID_CHANNEL_MAX_PID_CHANNEL_SHIFT 0 /*************************************************************************** *PSG_CFG - Passage Config Register ***************************************************************************/ /* XPT_FE :: PSG_CFG :: reserved0 [31:12] */ #define BCHP_XPT_FE_PSG_CFG_reserved0_MASK 0xfffff000 #define BCHP_XPT_FE_PSG_CFG_reserved0_SHIFT 12 /* XPT_FE :: PSG_CFG :: PSG_PBP2_DROP_ON_SCC_ERR [11:11] */ #define BCHP_XPT_FE_PSG_CFG_PSG_PBP2_DROP_ON_SCC_ERR_MASK 0x00000800 #define BCHP_XPT_FE_PSG_CFG_PSG_PBP2_DROP_ON_SCC_ERR_SHIFT 11 /* XPT_FE :: PSG_CFG :: PSG_PBP1_DROP_ON_SCC_ERR [10:10] */ #define BCHP_XPT_FE_PSG_CFG_PSG_PBP1_DROP_ON_SCC_ERR_MASK 0x00000400 #define BCHP_XPT_FE_PSG_CFG_PSG_PBP1_DROP_ON_SCC_ERR_SHIFT 10 /* XPT_FE :: PSG_CFG :: PSG_PBP0_DROP_ON_SCC_ERR [09:09] */ #define BCHP_XPT_FE_PSG_CFG_PSG_PBP0_DROP_ON_SCC_ERR_MASK 0x00000200 #define BCHP_XPT_FE_PSG_CFG_PSG_PBP0_DROP_ON_SCC_ERR_SHIFT 9 /* XPT_FE :: PSG_CFG :: reserved1 [08:02] */ #define BCHP_XPT_FE_PSG_CFG_reserved1_MASK 0x000001fc #define BCHP_XPT_FE_PSG_CFG_reserved1_SHIFT 2 /* XPT_FE :: PSG_CFG :: PSG_START_IMMEDIATE [01:01] */ #define BCHP_XPT_FE_PSG_CFG_PSG_START_IMMEDIATE_MASK 0x00000002 #define BCHP_XPT_FE_PSG_CFG_PSG_START_IMMEDIATE_SHIFT 1 /* XPT_FE :: PSG_CFG :: PSG_MASTER_EN [00:00] */ #define BCHP_XPT_FE_PSG_CFG_PSG_MASTER_EN_MASK 0x00000001 #define BCHP_XPT_FE_PSG_CFG_PSG_MASTER_EN_SHIFT 0 /*************************************************************************** *PSG_RESET0 - Passage Per PID Reset for Secondary PID Channels 0-31 Register ***************************************************************************/ /* XPT_FE :: PSG_RESET0 :: PSG_RST [31:00] */ #define BCHP_XPT_FE_PSG_RESET0_PSG_RST_MASK 0xffffffff #define BCHP_XPT_FE_PSG_RESET0_PSG_RST_SHIFT 0 /*************************************************************************** *PSG_RESET1 - Passage Per PID Reset for Secondary PID Channels 32-63 Register ***************************************************************************/ /* XPT_FE :: PSG_RESET1 :: PSG_RST [31:00] */ #define BCHP_XPT_FE_PSG_RESET1_PSG_RST_MASK 0xffffffff #define BCHP_XPT_FE_PSG_RESET1_PSG_RST_SHIFT 0 /*************************************************************************** *PSG_RESET2 - Passage Per PID Reset for Secondary PID Channels 64-95 Register ***************************************************************************/ /* XPT_FE :: PSG_RESET2 :: PSG_RST [31:00] */ #define BCHP_XPT_FE_PSG_RESET2_PSG_RST_MASK 0xffffffff #define BCHP_XPT_FE_PSG_RESET2_PSG_RST_SHIFT 0 /*************************************************************************** *PSG_RESET3 - Passage Per PID Reset for Secondary PID Channels 96-127 Register ***************************************************************************/ /* XPT_FE :: PSG_RESET3 :: PSG_RST [31:00] */ #define BCHP_XPT_FE_PSG_RESET3_PSG_RST_MASK 0xffffffff #define BCHP_XPT_FE_PSG_RESET3_PSG_RST_SHIFT 0 /*************************************************************************** *PSG_PR_ERR0 - Passage Per PID Protocol Error for PID Channels 0-31 Register ***************************************************************************/ /* XPT_FE :: PSG_PR_ERR0 :: PSG_PR_ERROR [31:00] */ #define BCHP_XPT_FE_PSG_PR_ERR0_PSG_PR_ERROR_MASK 0xffffffff #define BCHP_XPT_FE_PSG_PR_ERR0_PSG_PR_ERROR_SHIFT 0 /*************************************************************************** *PSG_PR_ERR1 - Passage Per PID Protocol Error for PID Channels 32-63 Register ***************************************************************************/ /* XPT_FE :: PSG_PR_ERR1 :: PSG_PR_ERROR [31:00] */ #define BCHP_XPT_FE_PSG_PR_ERR1_PSG_PR_ERROR_MASK 0xffffffff #define BCHP_XPT_FE_PSG_PR_ERR1_PSG_PR_ERROR_SHIFT 0 /*************************************************************************** *PSG_PR_ERR2 - Passage Per PID Protocol Error for PID Channels 95-64 Register ***************************************************************************/ /* XPT_FE :: PSG_PR_ERR2 :: PSG_PR_ERROR [31:00] */ #define BCHP_XPT_FE_PSG_PR_ERR2_PSG_PR_ERROR_MASK 0xffffffff #define BCHP_XPT_FE_PSG_PR_ERR2_PSG_PR_ERROR_SHIFT 0 /*************************************************************************** *PSG_PR_ERR3 - Passage Per PID Protocol Error for PID Channels 127-96 Register ***************************************************************************/ /* XPT_FE :: PSG_PR_ERR3 :: PSG_PR_ERROR [31:00] */ #define BCHP_XPT_FE_PSG_PR_ERR3_PSG_PR_ERROR_MASK 0xffffffff #define BCHP_XPT_FE_PSG_PR_ERR3_PSG_PR_ERROR_SHIFT 0 /*************************************************************************** *PSG_PR_ERR_EN0 - Passage Per PID Protocol Error Enable for PID Channels 0-31 Register ***************************************************************************/ /* XPT_FE :: PSG_PR_ERR_EN0 :: PSG_PR_ERROR_EN [31:00] */ #define BCHP_XPT_FE_PSG_PR_ERR_EN0_PSG_PR_ERROR_EN_MASK 0xffffffff #define BCHP_XPT_FE_PSG_PR_ERR_EN0_PSG_PR_ERROR_EN_SHIFT 0 /*************************************************************************** *PSG_PR_ERR_EN1 - Passage Per PID Protocol Error Enable for PID Channels 32-63 Register ***************************************************************************/ /* XPT_FE :: PSG_PR_ERR_EN1 :: PSG_PR_ERROR_EN [31:00] */ #define BCHP_XPT_FE_PSG_PR_ERR_EN1_PSG_PR_ERROR_EN_MASK 0xffffffff #define BCHP_XPT_FE_PSG_PR_ERR_EN1_PSG_PR_ERROR_EN_SHIFT 0 /*************************************************************************** *PSG_PR_ERR_EN2 - Passage Per PID Protocol Error Enable for PID Channels 64-95 Register ***************************************************************************/ /* XPT_FE :: PSG_PR_ERR_EN2 :: PSG_PR_ERROR_EN [31:00] */ #define BCHP_XPT_FE_PSG_PR_ERR_EN2_PSG_PR_ERROR_EN_MASK 0xffffffff #define BCHP_XPT_FE_PSG_PR_ERR_EN2_PSG_PR_ERROR_EN_SHIFT 0 /*************************************************************************** *PSG_PR_ERR_EN3 - Passage Per PID Protocol Error Enable for PID Channels 96-127 Register ***************************************************************************/ /* XPT_FE :: PSG_PR_ERR_EN3 :: PSG_PR_ERROR_EN [31:00] */ #define BCHP_XPT_FE_PSG_PR_ERR_EN3_PSG_PR_ERROR_EN_MASK 0xffffffff #define BCHP_XPT_FE_PSG_PR_ERR_EN3_PSG_PR_ERROR_EN_SHIFT 0 /*************************************************************************** *SCC_ERROR0 - Per PID Secondary CC Error for PID Channels 0-31 Register ***************************************************************************/ /* XPT_FE :: SCC_ERROR0 :: SCC_ERROR [31:00] */ #define BCHP_XPT_FE_SCC_ERROR0_SCC_ERROR_MASK 0xffffffff #define BCHP_XPT_FE_SCC_ERROR0_SCC_ERROR_SHIFT 0 /*************************************************************************** *SCC_ERROR1 - Per PID Secondary CC Error for PID Channels 32-63 Register ***************************************************************************/ /* XPT_FE :: SCC_ERROR1 :: SCC_ERROR [31:00] */ #define BCHP_XPT_FE_SCC_ERROR1_SCC_ERROR_MASK 0xffffffff #define BCHP_XPT_FE_SCC_ERROR1_SCC_ERROR_SHIFT 0 /*************************************************************************** *SCC_ERROR2 - Per PID Secondary CC Error for PID Channels 64-95 Register ***************************************************************************/ /* XPT_FE :: SCC_ERROR2 :: SCC_ERROR [31:00] */ #define BCHP_XPT_FE_SCC_ERROR2_SCC_ERROR_MASK 0xffffffff #define BCHP_XPT_FE_SCC_ERROR2_SCC_ERROR_SHIFT 0 /*************************************************************************** *SCC_ERROR3 - Per PID Secondary CC Error for PID Channels 96-127 Register ***************************************************************************/ /* XPT_FE :: SCC_ERROR3 :: SCC_ERROR [31:00] */ #define BCHP_XPT_FE_SCC_ERROR3_SCC_ERROR_MASK 0xffffffff #define BCHP_XPT_FE_SCC_ERROR3_SCC_ERROR_SHIFT 0 /*************************************************************************** *PCC_ERROR0 - Per PID Primary CC Error for PID Channels 0-31 Register ***************************************************************************/ /* XPT_FE :: PCC_ERROR0 :: PCC_ERROR [31:00] */ #define BCHP_XPT_FE_PCC_ERROR0_PCC_ERROR_MASK 0xffffffff #define BCHP_XPT_FE_PCC_ERROR0_PCC_ERROR_SHIFT 0 /*************************************************************************** *PCC_ERROR1 - Per PID Primary CC Error for PID Channels 32-63 Register ***************************************************************************/ /* XPT_FE :: PCC_ERROR1 :: PCC_ERROR [31:00] */ #define BCHP_XPT_FE_PCC_ERROR1_PCC_ERROR_MASK 0xffffffff #define BCHP_XPT_FE_PCC_ERROR1_PCC_ERROR_SHIFT 0 /*************************************************************************** *PCC_ERROR2 - Per PID Primary CC Error for PID Channels 64-95 Register ***************************************************************************/ /* XPT_FE :: PCC_ERROR2 :: PCC_ERROR [31:00] */ #define BCHP_XPT_FE_PCC_ERROR2_PCC_ERROR_MASK 0xffffffff #define BCHP_XPT_FE_PCC_ERROR2_PCC_ERROR_SHIFT 0 /*************************************************************************** *PCC_ERROR3 - Per PID Primary CC Error for PID Channels 96-127 Register ***************************************************************************/ /* XPT_FE :: PCC_ERROR3 :: PCC_ERROR [31:00] */ #define BCHP_XPT_FE_PCC_ERROR3_PCC_ERROR_MASK 0xffffffff #define BCHP_XPT_FE_PCC_ERROR3_PCC_ERROR_SHIFT 0 /*************************************************************************** *PID_ERR_SNIFFER - PID Error Sniffer Register ***************************************************************************/ /* XPT_FE :: PID_ERR_SNIFFER :: SNIF_ERROR_COUNT [31:16] */ #define BCHP_XPT_FE_PID_ERR_SNIFFER_SNIF_ERROR_COUNT_MASK 0xffff0000 #define BCHP_XPT_FE_PID_ERR_SNIFFER_SNIF_ERROR_COUNT_SHIFT 16 /* XPT_FE :: PID_ERR_SNIFFER :: reserved0 [15:07] */ #define BCHP_XPT_FE_PID_ERR_SNIFFER_reserved0_MASK 0x0000ff80 #define BCHP_XPT_FE_PID_ERR_SNIFFER_reserved0_SHIFT 7 /* XPT_FE :: PID_ERR_SNIFFER :: SNIF_PID_CHANNEL_NUMBER [06:00] */ #define BCHP_XPT_FE_PID_ERR_SNIFFER_SNIF_PID_CHANNEL_NUMBER_MASK 0x0000007f #define BCHP_XPT_FE_PID_ERR_SNIFFER_SNIF_PID_CHANNEL_NUMBER_SHIFT 0 /*************************************************************************** *PID_TABLE_%i - Data Transport Primary PID Table ***************************************************************************/ #define BCHP_XPT_FE_PID_TABLE_i_ARRAY_BASE 0x00208800 #define BCHP_XPT_FE_PID_TABLE_i_ARRAY_START 0 #define BCHP_XPT_FE_PID_TABLE_i_ARRAY_END 127 #define BCHP_XPT_FE_PID_TABLE_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *PID_TABLE_%i - Data Transport Primary PID Table ***************************************************************************/ /* XPT_FE :: PID_TABLE_i :: reserved0 [31:29] */ #define BCHP_XPT_FE_PID_TABLE_i_reserved0_MASK 0xe0000000 #define BCHP_XPT_FE_PID_TABLE_i_reserved0_SHIFT 29 /* XPT_FE :: PID_TABLE_i :: IGNORE_PID_VERSION [28:28] */ #define BCHP_XPT_FE_PID_TABLE_i_IGNORE_PID_VERSION_MASK 0x10000000 #define BCHP_XPT_FE_PID_TABLE_i_IGNORE_PID_VERSION_SHIFT 28 /* XPT_FE :: PID_TABLE_i :: PLAYBACK_FE_SEL [27:27] */ #define BCHP_XPT_FE_PID_TABLE_i_PLAYBACK_FE_SEL_MASK 0x08000000 #define BCHP_XPT_FE_PID_TABLE_i_PLAYBACK_FE_SEL_SHIFT 27 /* XPT_FE :: PID_TABLE_i :: PID_VERSION [26:24] */ #define BCHP_XPT_FE_PID_TABLE_i_PID_VERSION_MASK 0x07000000 #define BCHP_XPT_FE_PID_TABLE_i_PID_VERSION_SHIFT 24 /* XPT_FE :: PID_TABLE_i :: reserved1 [23:21] */ #define BCHP_XPT_FE_PID_TABLE_i_reserved1_MASK 0x00e00000 #define BCHP_XPT_FE_PID_TABLE_i_reserved1_SHIFT 21 /* XPT_FE :: PID_TABLE_i :: PID_CHANNEL_ENABLE [20:20] */ #define BCHP_XPT_FE_PID_TABLE_i_PID_CHANNEL_ENABLE_MASK 0x00100000 #define BCHP_XPT_FE_PID_TABLE_i_PID_CHANNEL_ENABLE_SHIFT 20 /* XPT_FE :: PID_TABLE_i :: PID_CHANNEL_INPUT_SELECT [19:16] */ #define BCHP_XPT_FE_PID_TABLE_i_PID_CHANNEL_INPUT_SELECT_MASK 0x000f0000 #define BCHP_XPT_FE_PID_TABLE_i_PID_CHANNEL_INPUT_SELECT_SHIFT 16 /* XPT_FE :: PID_TABLE_i :: reserved2 [15:14] */ #define BCHP_XPT_FE_PID_TABLE_i_reserved2_MASK 0x0000c000 #define BCHP_XPT_FE_PID_TABLE_i_reserved2_SHIFT 14 /* XPT_FE :: PID_TABLE_i :: ENABLE_HD_FILTER [13:13] */ #define BCHP_XPT_FE_PID_TABLE_i_ENABLE_HD_FILTER_MASK 0x00002000 #define BCHP_XPT_FE_PID_TABLE_i_ENABLE_HD_FILTER_SHIFT 13 /* union - case HD_FILT_EN [12:00] */ /* XPT_FE :: PID_TABLE_i :: HD_FILT_EN :: HD_FILTER_TYPE [12:12] */ #define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_HD_FILTER_TYPE_MASK 0x00001000 #define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_HD_FILTER_TYPE_SHIFT 12 /* XPT_FE :: PID_TABLE_i :: HD_FILT_EN :: PID_CHANNEL_SCID [11:00] */ #define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_PID_CHANNEL_SCID_MASK 0x00000fff #define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_EN_PID_CHANNEL_SCID_SHIFT 0 /* union - case HD_FILT_DIS [12:00] */ /* XPT_FE :: PID_TABLE_i :: HD_FILT_DIS :: PID_CHANNEL_PID [12:00] */ #define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_DIS_PID_CHANNEL_PID_MASK 0x00001fff #define BCHP_XPT_FE_PID_TABLE_i_HD_FILT_DIS_PID_CHANNEL_PID_SHIFT 0 /*************************************************************************** *SPID_TABLE_%i - Data Transport Secondary PID Table ***************************************************************************/ #define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_BASE 0x00208c00 #define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_START 0 #define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_END 127 #define BCHP_XPT_FE_SPID_TABLE_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *SPID_TABLE_%i - Data Transport Secondary PID Table ***************************************************************************/ /* XPT_FE :: SPID_TABLE_i :: PID_DESTINATION [31:24] */ #define BCHP_XPT_FE_SPID_TABLE_i_PID_DESTINATION_MASK 0xff000000 #define BCHP_XPT_FE_SPID_TABLE_i_PID_DESTINATION_SHIFT 24 /* XPT_FE :: SPID_TABLE_i :: reserved0 [23:20] */ #define BCHP_XPT_FE_SPID_TABLE_i_reserved0_MASK 0x00f00000 #define BCHP_XPT_FE_SPID_TABLE_i_reserved0_SHIFT 20 /* XPT_FE :: SPID_TABLE_i :: SPID_MODE [19:16] */ #define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_MASK 0x000f0000 #define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_SHIFT 16 #define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_DISABLE_SPID 0 #define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PID_INSERTION 5 #define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PID_MERGE 6 #define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_PID_REMAP 7 #define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_STREAM_ID_FILTER 8 #define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_STREAM_ID_RANGE 10 #define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_STREAM_ID_EXTENSION_FILTER 12 #define BCHP_XPT_FE_SPID_TABLE_i_SPID_MODE_SUBSTREAM_ID_FILTER 14 /* union - case STREAM_ID_FILTER [15:00] */ /* XPT_FE :: SPID_TABLE_i :: STREAM_ID_FILTER :: STREAM_ID [15:08] */ #define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_STREAM_ID_MASK 0x0000ff00 #define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_STREAM_ID_SHIFT 8 /* XPT_FE :: SPID_TABLE_i :: STREAM_ID_FILTER :: reserved0 [07:00] */ #define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_reserved0_MASK 0x000000ff #define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_FILTER_reserved0_SHIFT 0 /* union - case STREAM_ID_RANGE [15:00] */ /* XPT_FE :: SPID_TABLE_i :: STREAM_ID_RANGE :: STREAM_ID_HI [15:08] */ #define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_HI_MASK 0x0000ff00 #define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_HI_SHIFT 8 /* XPT_FE :: SPID_TABLE_i :: STREAM_ID_RANGE :: STREAM_ID_LO [07:00] */ #define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_LO_MASK 0x000000ff #define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_RANGE_STREAM_ID_LO_SHIFT 0 /* union - case STREAM_ID_EXTENSION_FILTER [15:00] */ /* XPT_FE :: SPID_TABLE_i :: STREAM_ID_EXTENSION_FILTER :: STREAM_ID [15:08] */ #define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_MASK 0x0000ff00 #define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_SHIFT 8 /* XPT_FE :: SPID_TABLE_i :: STREAM_ID_EXTENSION_FILTER :: STREAM_ID_EXTENSION [07:00] */ #define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_EXTENSION_MASK 0x000000ff #define BCHP_XPT_FE_SPID_TABLE_i_STREAM_ID_EXTENSION_FILTER_STREAM_ID_EXTENSION_SHIFT 0 /* union - case SUBSTREAM_ID_FILTER [15:00] */ /* XPT_FE :: SPID_TABLE_i :: SUBSTREAM_ID_FILTER :: STREAM_ID [15:08] */ #define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_STREAM_ID_MASK 0x0000ff00 #define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_STREAM_ID_SHIFT 8 /* XPT_FE :: SPID_TABLE_i :: SUBSTREAM_ID_FILTER :: SUBSTREAM_ID [07:00] */ #define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_SUBSTREAM_ID_MASK 0x000000ff #define BCHP_XPT_FE_SPID_TABLE_i_SUBSTREAM_ID_FILTER_SUBSTREAM_ID_SHIFT 0 /* union - case PID_FUNCTIONS [15:00] */ /* XPT_FE :: SPID_TABLE_i :: PID_FUNCTIONS :: reserved0 [15:13] */ #define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_reserved0_MASK 0x0000e000 #define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_reserved0_SHIFT 13 /* XPT_FE :: SPID_TABLE_i :: PID_FUNCTIONS :: SPID_CHANNEL_PID [12:00] */ #define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_SPID_CHANNEL_PID_MASK 0x00001fff #define BCHP_XPT_FE_SPID_TABLE_i_PID_FUNCTIONS_SPID_CHANNEL_PID_SHIFT 0 #endif /* #ifndef BCHP_XPT_FE_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016100000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_reg_cabac2bins_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_reg_ca0000644000175000017500000001054311610313111030761 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_reg_cabac2bins_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:18p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:54 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_reg_cabac2bins_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:18p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_REG_CABAC2BINS_0_H__ #define BCHP_REG_CABAC2BINS_0_H__ /*************************************************************************** *REG_CABAC2BINS_0 ***************************************************************************/ #define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_IMG__CTX_LAST 0x00800bbc /* REG_CABAC2BINS_IMG__CTX_LAST */ #define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR 0x00800bd0 /* REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR */ #define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_END_END 0x00800bfc /* REG_CABAC2BINS_END_END */ /*************************************************************************** *REG_CABAC2BINS_IMG__CTX_LAST - REG_CABAC2BINS_IMG__CTX_LAST ***************************************************************************/ /* REG_CABAC2BINS_0 :: REG_CABAC2BINS_IMG__CTX_LAST :: reserved0 [31:09] */ #define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_IMG__CTX_LAST_reserved0_MASK 0xfffffe00 #define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_IMG__CTX_LAST_reserved0_SHIFT 9 /* REG_CABAC2BINS_0 :: REG_CABAC2BINS_IMG__CTX_LAST :: CtxLast [08:00] */ #define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_IMG__CTX_LAST_CtxLast_MASK 0x000001ff #define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_IMG__CTX_LAST_CtxLast_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR - REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR ***************************************************************************/ /* REG_CABAC2BINS_0 :: REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR :: Addr [31:04] */ #define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR_Addr_MASK 0xfffffff0 #define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR_Addr_SHIFT 4 /* REG_CABAC2BINS_0 :: REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR :: reserved0 [03:00] */ #define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR_reserved0_MASK 0x0000000f #define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_CONTEXT_TABLE_BASE_ADDR_reserved0_SHIFT 0 /*************************************************************************** *REG_CABAC2BINS_END_END - REG_CABAC2BINS_END_END ***************************************************************************/ /* REG_CABAC2BINS_0 :: REG_CABAC2BINS_END_END :: reserved0 [31:00] */ #define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_END_END_reserved0_MASK 0xffffffff #define BCHP_REG_CABAC2BINS_0_REG_CABAC2BINS_END_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_REG_CABAC2BINS_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016300000000000011565 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_3.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_cr0000644000175000017500000002037311610313111031021 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_crit_l2_regs_3.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:16p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:45 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_3.h $ * * Hydra_Software_Devel/1 7/17/09 8:16p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_CRIT_L2_REGS_3_H__ #define BCHP_PRI_CRIT_L2_REGS_3_H__ /*************************************************************************** *PRI_CRIT_L2_REGS_3 - PRIMARY_ARB_CLIENTS L2 (Mips) critical interrupt controller 3 registers ***************************************************************************/ #define BCHP_PRI_CRIT_L2_REGS_3_CPU_STATUS 0x0040c480 /* CPU interrupt Status Register */ #define BCHP_PRI_CRIT_L2_REGS_3_CPU_SET 0x0040c484 /* CPU interrupt Set Register */ #define BCHP_PRI_CRIT_L2_REGS_3_CPU_CLEAR 0x0040c488 /* CPU interrupt Clear Register */ #define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_STATUS 0x0040c48c /* CPU interrupt Mask Status Register */ #define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_SET 0x0040c490 /* CPU interrupt Mask Set Register */ #define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_CLEAR 0x0040c494 /* CPU interrupt Mask Clear Register */ #define BCHP_PRI_CRIT_L2_REGS_3_PCI_STATUS 0x0040c498 /* PCI interrupt Status Register */ #define BCHP_PRI_CRIT_L2_REGS_3_PCI_SET 0x0040c49c /* PCI interrupt Set Register */ #define BCHP_PRI_CRIT_L2_REGS_3_PCI_CLEAR 0x0040c4a0 /* PCI interrupt Clear Register */ #define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_STATUS 0x0040c4a4 /* PCI interrupt Mask Status Register */ #define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_SET 0x0040c4a8 /* PCI interrupt Mask Set Register */ #define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_CLEAR 0x0040c4ac /* PCI interrupt Mask Clear Register */ /*************************************************************************** *CPU_STATUS - CPU interrupt Status Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_3 :: CPU_STATUS :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_3_CPU_STATUS_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_3_CPU_STATUS_reserved0_SHIFT 0 /*************************************************************************** *CPU_SET - CPU interrupt Set Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_3 :: CPU_SET :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_3_CPU_SET_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_3_CPU_SET_reserved0_SHIFT 0 /*************************************************************************** *CPU_CLEAR - CPU interrupt Clear Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_3 :: CPU_CLEAR :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_3_CPU_CLEAR_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_3_CPU_CLEAR_reserved0_SHIFT 0 /*************************************************************************** *CPU_MASK_STATUS - CPU interrupt Mask Status Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_3 :: CPU_MASK_STATUS :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_STATUS_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_STATUS_reserved0_SHIFT 0 /*************************************************************************** *CPU_MASK_SET - CPU interrupt Mask Set Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_3 :: CPU_MASK_SET :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_SET_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_SET_reserved0_SHIFT 0 /*************************************************************************** *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_3 :: CPU_MASK_CLEAR :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_CLEAR_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_3_CPU_MASK_CLEAR_reserved0_SHIFT 0 /*************************************************************************** *PCI_STATUS - PCI interrupt Status Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_3 :: PCI_STATUS :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_3_PCI_STATUS_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_3_PCI_STATUS_reserved0_SHIFT 0 /*************************************************************************** *PCI_SET - PCI interrupt Set Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_3 :: PCI_SET :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_3_PCI_SET_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_3_PCI_SET_reserved0_SHIFT 0 /*************************************************************************** *PCI_CLEAR - PCI interrupt Clear Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_3 :: PCI_CLEAR :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_3_PCI_CLEAR_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_3_PCI_CLEAR_reserved0_SHIFT 0 /*************************************************************************** *PCI_MASK_STATUS - PCI interrupt Mask Status Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_3 :: PCI_MASK_STATUS :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_STATUS_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_STATUS_reserved0_SHIFT 0 /*************************************************************************** *PCI_MASK_SET - PCI interrupt Mask Set Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_3 :: PCI_MASK_SET :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_SET_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_SET_reserved0_SHIFT 0 /*************************************************************************** *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_3 :: PCI_MASK_CLEAR :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_CLEAR_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_3_PCI_MASK_CLEAR_reserved0_SHIFT 0 #endif /* #ifndef BCHP_PRI_CRIT_L2_REGS_3_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015300000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_intr2.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_i0000644000175000017500000007260411610313111031030 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_bvnt_intr2.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:57p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:21 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_bvnt_intr2.h $ * * Hydra_Software_Devel/1 7/17/09 7:57p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_BVNT_INTR2_H__ #define BCHP_BVNT_INTR2_H__ /*************************************************************************** *BVNT_INTR2 - BVN Interrupt Controller Registers ***************************************************************************/ #define BCHP_BVNT_INTR2_CPU_STATUS 0x00541200 /* CPU interrupt Status Register */ #define BCHP_BVNT_INTR2_CPU_SET 0x00541204 /* CPU interrupt Set Register */ #define BCHP_BVNT_INTR2_CPU_CLEAR 0x00541208 /* CPU interrupt Clear Register */ #define BCHP_BVNT_INTR2_CPU_MASK_STATUS 0x0054120c /* CPU interrupt Mask Status Register */ #define BCHP_BVNT_INTR2_CPU_MASK_SET 0x00541210 /* CPU interrupt Mask Set Register */ #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR 0x00541214 /* CPU interrupt Mask Clear Register */ #define BCHP_BVNT_INTR2_PCI_STATUS 0x00541218 /* PCI interrupt Status Register */ #define BCHP_BVNT_INTR2_PCI_SET 0x0054121c /* PCI interrupt Set Register */ #define BCHP_BVNT_INTR2_PCI_CLEAR 0x00541220 /* PCI interrupt Clear Register */ #define BCHP_BVNT_INTR2_PCI_MASK_STATUS 0x00541224 /* PCI interrupt Mask Status Register */ #define BCHP_BVNT_INTR2_PCI_MASK_SET 0x00541228 /* PCI interrupt Mask Set Register */ #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR 0x0054122c /* PCI interrupt Mask Clear Register */ /*************************************************************************** *CPU_STATUS - CPU interrupt Status Register ***************************************************************************/ /* BVNT_INTR2 :: CPU_STATUS :: reserved0 [31:09] */ #define BCHP_BVNT_INTR2_CPU_STATUS_reserved0_MASK 0xfffffe00 #define BCHP_BVNT_INTR2_CPU_STATUS_reserved0_SHIFT 9 /* BVNT_INTR2 :: CPU_STATUS :: BOP_EOF_INTR [08:08] */ #define BCHP_BVNT_INTR2_CPU_STATUS_BOP_EOF_INTR_MASK 0x00000100 #define BCHP_BVNT_INTR2_CPU_STATUS_BOP_EOF_INTR_SHIFT 8 /* BVNT_INTR2 :: CPU_STATUS :: BVN_EOF_INTR [07:07] */ #define BCHP_BVNT_INTR2_CPU_STATUS_BVN_EOF_INTR_MASK 0x00000080 #define BCHP_BVNT_INTR2_CPU_STATUS_BVN_EOF_INTR_SHIFT 7 /* BVNT_INTR2 :: CPU_STATUS :: METADMA_INTR [06:06] */ #define BCHP_BVNT_INTR2_CPU_STATUS_METADMA_INTR_MASK 0x00000040 #define BCHP_BVNT_INTR2_CPU_STATUS_METADMA_INTR_SHIFT 6 /* BVNT_INTR2 :: CPU_STATUS :: RXDMA3_INTR [05:05] */ #define BCHP_BVNT_INTR2_CPU_STATUS_RXDMA3_INTR_MASK 0x00000020 #define BCHP_BVNT_INTR2_CPU_STATUS_RXDMA3_INTR_SHIFT 5 /* BVNT_INTR2 :: CPU_STATUS :: TXDMA_INTR [04:04] */ #define BCHP_BVNT_INTR2_CPU_STATUS_TXDMA_INTR_MASK 0x00000010 #define BCHP_BVNT_INTR2_CPU_STATUS_TXDMA_INTR_SHIFT 4 /* BVNT_INTR2 :: CPU_STATUS :: SCL_INTR [03:03] */ #define BCHP_BVNT_INTR2_CPU_STATUS_SCL_INTR_MASK 0x00000008 #define BCHP_BVNT_INTR2_CPU_STATUS_SCL_INTR_SHIFT 3 /* BVNT_INTR2 :: CPU_STATUS :: DNR_INTR [02:02] */ #define BCHP_BVNT_INTR2_CPU_STATUS_DNR_INTR_MASK 0x00000004 #define BCHP_BVNT_INTR2_CPU_STATUS_DNR_INTR_SHIFT 2 /* BVNT_INTR2 :: CPU_STATUS :: EOF_INTR [01:01] */ #define BCHP_BVNT_INTR2_CPU_STATUS_EOF_INTR_MASK 0x00000002 #define BCHP_BVNT_INTR2_CPU_STATUS_EOF_INTR_SHIFT 1 /* BVNT_INTR2 :: CPU_STATUS :: MFD_INTR [00:00] */ #define BCHP_BVNT_INTR2_CPU_STATUS_MFD_INTR_MASK 0x00000001 #define BCHP_BVNT_INTR2_CPU_STATUS_MFD_INTR_SHIFT 0 /*************************************************************************** *CPU_SET - CPU interrupt Set Register ***************************************************************************/ /* BVNT_INTR2 :: CPU_SET :: reserved0 [31:09] */ #define BCHP_BVNT_INTR2_CPU_SET_reserved0_MASK 0xfffffe00 #define BCHP_BVNT_INTR2_CPU_SET_reserved0_SHIFT 9 /* BVNT_INTR2 :: CPU_SET :: BOP_EOF_INTR [08:08] */ #define BCHP_BVNT_INTR2_CPU_SET_BOP_EOF_INTR_MASK 0x00000100 #define BCHP_BVNT_INTR2_CPU_SET_BOP_EOF_INTR_SHIFT 8 /* BVNT_INTR2 :: CPU_SET :: BVN_EOF_INTR [07:07] */ #define BCHP_BVNT_INTR2_CPU_SET_BVN_EOF_INTR_MASK 0x00000080 #define BCHP_BVNT_INTR2_CPU_SET_BVN_EOF_INTR_SHIFT 7 /* BVNT_INTR2 :: CPU_SET :: METADMA_INTR [06:06] */ #define BCHP_BVNT_INTR2_CPU_SET_METADMA_INTR_MASK 0x00000040 #define BCHP_BVNT_INTR2_CPU_SET_METADMA_INTR_SHIFT 6 /* BVNT_INTR2 :: CPU_SET :: RXDMA3_INTR [05:05] */ #define BCHP_BVNT_INTR2_CPU_SET_RXDMA3_INTR_MASK 0x00000020 #define BCHP_BVNT_INTR2_CPU_SET_RXDMA3_INTR_SHIFT 5 /* BVNT_INTR2 :: CPU_SET :: TXDMA_INTR [04:04] */ #define BCHP_BVNT_INTR2_CPU_SET_TXDMA_INTR_MASK 0x00000010 #define BCHP_BVNT_INTR2_CPU_SET_TXDMA_INTR_SHIFT 4 /* BVNT_INTR2 :: CPU_SET :: SCL_INTR [03:03] */ #define BCHP_BVNT_INTR2_CPU_SET_SCL_INTR_MASK 0x00000008 #define BCHP_BVNT_INTR2_CPU_SET_SCL_INTR_SHIFT 3 /* BVNT_INTR2 :: CPU_SET :: DNR_INTR [02:02] */ #define BCHP_BVNT_INTR2_CPU_SET_DNR_INTR_MASK 0x00000004 #define BCHP_BVNT_INTR2_CPU_SET_DNR_INTR_SHIFT 2 /* BVNT_INTR2 :: CPU_SET :: EOF_INTR [01:01] */ #define BCHP_BVNT_INTR2_CPU_SET_EOF_INTR_MASK 0x00000002 #define BCHP_BVNT_INTR2_CPU_SET_EOF_INTR_SHIFT 1 /* BVNT_INTR2 :: CPU_SET :: MFD_INTR [00:00] */ #define BCHP_BVNT_INTR2_CPU_SET_MFD_INTR_MASK 0x00000001 #define BCHP_BVNT_INTR2_CPU_SET_MFD_INTR_SHIFT 0 /*************************************************************************** *CPU_CLEAR - CPU interrupt Clear Register ***************************************************************************/ /* BVNT_INTR2 :: CPU_CLEAR :: reserved0 [31:09] */ #define BCHP_BVNT_INTR2_CPU_CLEAR_reserved0_MASK 0xfffffe00 #define BCHP_BVNT_INTR2_CPU_CLEAR_reserved0_SHIFT 9 /* BVNT_INTR2 :: CPU_CLEAR :: BOP_EOF_INTR [08:08] */ #define BCHP_BVNT_INTR2_CPU_CLEAR_BOP_EOF_INTR_MASK 0x00000100 #define BCHP_BVNT_INTR2_CPU_CLEAR_BOP_EOF_INTR_SHIFT 8 /* BVNT_INTR2 :: CPU_CLEAR :: BVN_EOF_INTR [07:07] */ #define BCHP_BVNT_INTR2_CPU_CLEAR_BVN_EOF_INTR_MASK 0x00000080 #define BCHP_BVNT_INTR2_CPU_CLEAR_BVN_EOF_INTR_SHIFT 7 /* BVNT_INTR2 :: CPU_CLEAR :: METADMA_INTR [06:06] */ #define BCHP_BVNT_INTR2_CPU_CLEAR_METADMA_INTR_MASK 0x00000040 #define BCHP_BVNT_INTR2_CPU_CLEAR_METADMA_INTR_SHIFT 6 /* BVNT_INTR2 :: CPU_CLEAR :: RXDMA3_INTR [05:05] */ #define BCHP_BVNT_INTR2_CPU_CLEAR_RXDMA3_INTR_MASK 0x00000020 #define BCHP_BVNT_INTR2_CPU_CLEAR_RXDMA3_INTR_SHIFT 5 /* BVNT_INTR2 :: CPU_CLEAR :: TXDMA_INTR [04:04] */ #define BCHP_BVNT_INTR2_CPU_CLEAR_TXDMA_INTR_MASK 0x00000010 #define BCHP_BVNT_INTR2_CPU_CLEAR_TXDMA_INTR_SHIFT 4 /* BVNT_INTR2 :: CPU_CLEAR :: SCL_INTR [03:03] */ #define BCHP_BVNT_INTR2_CPU_CLEAR_SCL_INTR_MASK 0x00000008 #define BCHP_BVNT_INTR2_CPU_CLEAR_SCL_INTR_SHIFT 3 /* BVNT_INTR2 :: CPU_CLEAR :: DNR_INTR [02:02] */ #define BCHP_BVNT_INTR2_CPU_CLEAR_DNR_INTR_MASK 0x00000004 #define BCHP_BVNT_INTR2_CPU_CLEAR_DNR_INTR_SHIFT 2 /* BVNT_INTR2 :: CPU_CLEAR :: EOF_INTR [01:01] */ #define BCHP_BVNT_INTR2_CPU_CLEAR_EOF_INTR_MASK 0x00000002 #define BCHP_BVNT_INTR2_CPU_CLEAR_EOF_INTR_SHIFT 1 /* BVNT_INTR2 :: CPU_CLEAR :: MFD_INTR [00:00] */ #define BCHP_BVNT_INTR2_CPU_CLEAR_MFD_INTR_MASK 0x00000001 #define BCHP_BVNT_INTR2_CPU_CLEAR_MFD_INTR_SHIFT 0 /*************************************************************************** *CPU_MASK_STATUS - CPU interrupt Mask Status Register ***************************************************************************/ /* BVNT_INTR2 :: CPU_MASK_STATUS :: reserved0 [31:09] */ #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_reserved0_MASK 0xfffffe00 #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_reserved0_SHIFT 9 /* BVNT_INTR2 :: CPU_MASK_STATUS :: BOP_EOF_INTR [08:08] */ #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_BOP_EOF_INTR_MASK 0x00000100 #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_BOP_EOF_INTR_SHIFT 8 /* BVNT_INTR2 :: CPU_MASK_STATUS :: BVN_EOF_INTR [07:07] */ #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_BVN_EOF_INTR_MASK 0x00000080 #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_BVN_EOF_INTR_SHIFT 7 /* BVNT_INTR2 :: CPU_MASK_STATUS :: METADMA_INTR [06:06] */ #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_METADMA_INTR_MASK 0x00000040 #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_METADMA_INTR_SHIFT 6 /* BVNT_INTR2 :: CPU_MASK_STATUS :: RXDMA3_INTR [05:05] */ #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_RXDMA3_INTR_MASK 0x00000020 #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_RXDMA3_INTR_SHIFT 5 /* BVNT_INTR2 :: CPU_MASK_STATUS :: TXDMA_INTR [04:04] */ #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_TXDMA_INTR_MASK 0x00000010 #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_TXDMA_INTR_SHIFT 4 /* BVNT_INTR2 :: CPU_MASK_STATUS :: SCL_INTR [03:03] */ #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_SCL_INTR_MASK 0x00000008 #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_SCL_INTR_SHIFT 3 /* BVNT_INTR2 :: CPU_MASK_STATUS :: DNR_INTR [02:02] */ #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_DNR_INTR_MASK 0x00000004 #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_DNR_INTR_SHIFT 2 /* BVNT_INTR2 :: CPU_MASK_STATUS :: EOF_INTR [01:01] */ #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_EOF_INTR_MASK 0x00000002 #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_EOF_INTR_SHIFT 1 /* BVNT_INTR2 :: CPU_MASK_STATUS :: MFD_INTR [00:00] */ #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_MFD_INTR_MASK 0x00000001 #define BCHP_BVNT_INTR2_CPU_MASK_STATUS_MFD_INTR_SHIFT 0 /*************************************************************************** *CPU_MASK_SET - CPU interrupt Mask Set Register ***************************************************************************/ /* BVNT_INTR2 :: CPU_MASK_SET :: reserved0 [31:09] */ #define BCHP_BVNT_INTR2_CPU_MASK_SET_reserved0_MASK 0xfffffe00 #define BCHP_BVNT_INTR2_CPU_MASK_SET_reserved0_SHIFT 9 /* BVNT_INTR2 :: CPU_MASK_SET :: BOP_EOF_INTR [08:08] */ #define BCHP_BVNT_INTR2_CPU_MASK_SET_BOP_EOF_INTR_MASK 0x00000100 #define BCHP_BVNT_INTR2_CPU_MASK_SET_BOP_EOF_INTR_SHIFT 8 /* BVNT_INTR2 :: CPU_MASK_SET :: BVN_EOF_INTR [07:07] */ #define BCHP_BVNT_INTR2_CPU_MASK_SET_BVN_EOF_INTR_MASK 0x00000080 #define BCHP_BVNT_INTR2_CPU_MASK_SET_BVN_EOF_INTR_SHIFT 7 /* BVNT_INTR2 :: CPU_MASK_SET :: METADMA_INTR [06:06] */ #define BCHP_BVNT_INTR2_CPU_MASK_SET_METADMA_INTR_MASK 0x00000040 #define BCHP_BVNT_INTR2_CPU_MASK_SET_METADMA_INTR_SHIFT 6 /* BVNT_INTR2 :: CPU_MASK_SET :: RXDMA3_INTR [05:05] */ #define BCHP_BVNT_INTR2_CPU_MASK_SET_RXDMA3_INTR_MASK 0x00000020 #define BCHP_BVNT_INTR2_CPU_MASK_SET_RXDMA3_INTR_SHIFT 5 /* BVNT_INTR2 :: CPU_MASK_SET :: TXDMA_INTR [04:04] */ #define BCHP_BVNT_INTR2_CPU_MASK_SET_TXDMA_INTR_MASK 0x00000010 #define BCHP_BVNT_INTR2_CPU_MASK_SET_TXDMA_INTR_SHIFT 4 /* BVNT_INTR2 :: CPU_MASK_SET :: SCL_INTR [03:03] */ #define BCHP_BVNT_INTR2_CPU_MASK_SET_SCL_INTR_MASK 0x00000008 #define BCHP_BVNT_INTR2_CPU_MASK_SET_SCL_INTR_SHIFT 3 /* BVNT_INTR2 :: CPU_MASK_SET :: DNR_INTR [02:02] */ #define BCHP_BVNT_INTR2_CPU_MASK_SET_DNR_INTR_MASK 0x00000004 #define BCHP_BVNT_INTR2_CPU_MASK_SET_DNR_INTR_SHIFT 2 /* BVNT_INTR2 :: CPU_MASK_SET :: EOF_INTR [01:01] */ #define BCHP_BVNT_INTR2_CPU_MASK_SET_EOF_INTR_MASK 0x00000002 #define BCHP_BVNT_INTR2_CPU_MASK_SET_EOF_INTR_SHIFT 1 /* BVNT_INTR2 :: CPU_MASK_SET :: MFD_INTR [00:00] */ #define BCHP_BVNT_INTR2_CPU_MASK_SET_MFD_INTR_MASK 0x00000001 #define BCHP_BVNT_INTR2_CPU_MASK_SET_MFD_INTR_SHIFT 0 /*************************************************************************** *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register ***************************************************************************/ /* BVNT_INTR2 :: CPU_MASK_CLEAR :: reserved0 [31:09] */ #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_reserved0_MASK 0xfffffe00 #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_reserved0_SHIFT 9 /* BVNT_INTR2 :: CPU_MASK_CLEAR :: BOP_EOF_INTR [08:08] */ #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_BOP_EOF_INTR_MASK 0x00000100 #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_BOP_EOF_INTR_SHIFT 8 /* BVNT_INTR2 :: CPU_MASK_CLEAR :: BVN_EOF_INTR [07:07] */ #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_BVN_EOF_INTR_MASK 0x00000080 #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_BVN_EOF_INTR_SHIFT 7 /* BVNT_INTR2 :: CPU_MASK_CLEAR :: METADMA_INTR [06:06] */ #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_METADMA_INTR_MASK 0x00000040 #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_METADMA_INTR_SHIFT 6 /* BVNT_INTR2 :: CPU_MASK_CLEAR :: RXDMA3_INTR [05:05] */ #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_RXDMA3_INTR_MASK 0x00000020 #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_RXDMA3_INTR_SHIFT 5 /* BVNT_INTR2 :: CPU_MASK_CLEAR :: TXDMA_INTR [04:04] */ #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_TXDMA_INTR_MASK 0x00000010 #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_TXDMA_INTR_SHIFT 4 /* BVNT_INTR2 :: CPU_MASK_CLEAR :: SCL_INTR [03:03] */ #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_SCL_INTR_MASK 0x00000008 #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_SCL_INTR_SHIFT 3 /* BVNT_INTR2 :: CPU_MASK_CLEAR :: DNR_INTR [02:02] */ #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_DNR_INTR_MASK 0x00000004 #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_DNR_INTR_SHIFT 2 /* BVNT_INTR2 :: CPU_MASK_CLEAR :: EOF_INTR [01:01] */ #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_EOF_INTR_MASK 0x00000002 #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_EOF_INTR_SHIFT 1 /* BVNT_INTR2 :: CPU_MASK_CLEAR :: MFD_INTR [00:00] */ #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_MFD_INTR_MASK 0x00000001 #define BCHP_BVNT_INTR2_CPU_MASK_CLEAR_MFD_INTR_SHIFT 0 /*************************************************************************** *PCI_STATUS - PCI interrupt Status Register ***************************************************************************/ /* BVNT_INTR2 :: PCI_STATUS :: reserved0 [31:09] */ #define BCHP_BVNT_INTR2_PCI_STATUS_reserved0_MASK 0xfffffe00 #define BCHP_BVNT_INTR2_PCI_STATUS_reserved0_SHIFT 9 /* BVNT_INTR2 :: PCI_STATUS :: BOP_EOF_INTR [08:08] */ #define BCHP_BVNT_INTR2_PCI_STATUS_BOP_EOF_INTR_MASK 0x00000100 #define BCHP_BVNT_INTR2_PCI_STATUS_BOP_EOF_INTR_SHIFT 8 /* BVNT_INTR2 :: PCI_STATUS :: BVN_EOF_INTR [07:07] */ #define BCHP_BVNT_INTR2_PCI_STATUS_BVN_EOF_INTR_MASK 0x00000080 #define BCHP_BVNT_INTR2_PCI_STATUS_BVN_EOF_INTR_SHIFT 7 /* BVNT_INTR2 :: PCI_STATUS :: METADMA_INTR [06:06] */ #define BCHP_BVNT_INTR2_PCI_STATUS_METADMA_INTR_MASK 0x00000040 #define BCHP_BVNT_INTR2_PCI_STATUS_METADMA_INTR_SHIFT 6 /* BVNT_INTR2 :: PCI_STATUS :: RXDMA3_INTR [05:05] */ #define BCHP_BVNT_INTR2_PCI_STATUS_RXDMA3_INTR_MASK 0x00000020 #define BCHP_BVNT_INTR2_PCI_STATUS_RXDMA3_INTR_SHIFT 5 /* BVNT_INTR2 :: PCI_STATUS :: TXDMA_INTR [04:04] */ #define BCHP_BVNT_INTR2_PCI_STATUS_TXDMA_INTR_MASK 0x00000010 #define BCHP_BVNT_INTR2_PCI_STATUS_TXDMA_INTR_SHIFT 4 /* BVNT_INTR2 :: PCI_STATUS :: SCL_INTR [03:03] */ #define BCHP_BVNT_INTR2_PCI_STATUS_SCL_INTR_MASK 0x00000008 #define BCHP_BVNT_INTR2_PCI_STATUS_SCL_INTR_SHIFT 3 /* BVNT_INTR2 :: PCI_STATUS :: DNR_INTR [02:02] */ #define BCHP_BVNT_INTR2_PCI_STATUS_DNR_INTR_MASK 0x00000004 #define BCHP_BVNT_INTR2_PCI_STATUS_DNR_INTR_SHIFT 2 /* BVNT_INTR2 :: PCI_STATUS :: EOF_INTR [01:01] */ #define BCHP_BVNT_INTR2_PCI_STATUS_EOF_INTR_MASK 0x00000002 #define BCHP_BVNT_INTR2_PCI_STATUS_EOF_INTR_SHIFT 1 /* BVNT_INTR2 :: PCI_STATUS :: MFD_INTR [00:00] */ #define BCHP_BVNT_INTR2_PCI_STATUS_MFD_INTR_MASK 0x00000001 #define BCHP_BVNT_INTR2_PCI_STATUS_MFD_INTR_SHIFT 0 /*************************************************************************** *PCI_SET - PCI interrupt Set Register ***************************************************************************/ /* BVNT_INTR2 :: PCI_SET :: reserved0 [31:09] */ #define BCHP_BVNT_INTR2_PCI_SET_reserved0_MASK 0xfffffe00 #define BCHP_BVNT_INTR2_PCI_SET_reserved0_SHIFT 9 /* BVNT_INTR2 :: PCI_SET :: BOP_EOF_INTR [08:08] */ #define BCHP_BVNT_INTR2_PCI_SET_BOP_EOF_INTR_MASK 0x00000100 #define BCHP_BVNT_INTR2_PCI_SET_BOP_EOF_INTR_SHIFT 8 /* BVNT_INTR2 :: PCI_SET :: BVN_EOF_INTR [07:07] */ #define BCHP_BVNT_INTR2_PCI_SET_BVN_EOF_INTR_MASK 0x00000080 #define BCHP_BVNT_INTR2_PCI_SET_BVN_EOF_INTR_SHIFT 7 /* BVNT_INTR2 :: PCI_SET :: METADMA_INTR [06:06] */ #define BCHP_BVNT_INTR2_PCI_SET_METADMA_INTR_MASK 0x00000040 #define BCHP_BVNT_INTR2_PCI_SET_METADMA_INTR_SHIFT 6 /* BVNT_INTR2 :: PCI_SET :: RXDMA3_INTR [05:05] */ #define BCHP_BVNT_INTR2_PCI_SET_RXDMA3_INTR_MASK 0x00000020 #define BCHP_BVNT_INTR2_PCI_SET_RXDMA3_INTR_SHIFT 5 /* BVNT_INTR2 :: PCI_SET :: TXDMA_INTR [04:04] */ #define BCHP_BVNT_INTR2_PCI_SET_TXDMA_INTR_MASK 0x00000010 #define BCHP_BVNT_INTR2_PCI_SET_TXDMA_INTR_SHIFT 4 /* BVNT_INTR2 :: PCI_SET :: SCL_INTR [03:03] */ #define BCHP_BVNT_INTR2_PCI_SET_SCL_INTR_MASK 0x00000008 #define BCHP_BVNT_INTR2_PCI_SET_SCL_INTR_SHIFT 3 /* BVNT_INTR2 :: PCI_SET :: DNR_INTR [02:02] */ #define BCHP_BVNT_INTR2_PCI_SET_DNR_INTR_MASK 0x00000004 #define BCHP_BVNT_INTR2_PCI_SET_DNR_INTR_SHIFT 2 /* BVNT_INTR2 :: PCI_SET :: EOF_INTR [01:01] */ #define BCHP_BVNT_INTR2_PCI_SET_EOF_INTR_MASK 0x00000002 #define BCHP_BVNT_INTR2_PCI_SET_EOF_INTR_SHIFT 1 /* BVNT_INTR2 :: PCI_SET :: MFD_INTR [00:00] */ #define BCHP_BVNT_INTR2_PCI_SET_MFD_INTR_MASK 0x00000001 #define BCHP_BVNT_INTR2_PCI_SET_MFD_INTR_SHIFT 0 /*************************************************************************** *PCI_CLEAR - PCI interrupt Clear Register ***************************************************************************/ /* BVNT_INTR2 :: PCI_CLEAR :: reserved0 [31:09] */ #define BCHP_BVNT_INTR2_PCI_CLEAR_reserved0_MASK 0xfffffe00 #define BCHP_BVNT_INTR2_PCI_CLEAR_reserved0_SHIFT 9 /* BVNT_INTR2 :: PCI_CLEAR :: BOP_EOF_INTR [08:08] */ #define BCHP_BVNT_INTR2_PCI_CLEAR_BOP_EOF_INTR_MASK 0x00000100 #define BCHP_BVNT_INTR2_PCI_CLEAR_BOP_EOF_INTR_SHIFT 8 /* BVNT_INTR2 :: PCI_CLEAR :: BVN_EOF_INTR [07:07] */ #define BCHP_BVNT_INTR2_PCI_CLEAR_BVN_EOF_INTR_MASK 0x00000080 #define BCHP_BVNT_INTR2_PCI_CLEAR_BVN_EOF_INTR_SHIFT 7 /* BVNT_INTR2 :: PCI_CLEAR :: METADMA_INTR [06:06] */ #define BCHP_BVNT_INTR2_PCI_CLEAR_METADMA_INTR_MASK 0x00000040 #define BCHP_BVNT_INTR2_PCI_CLEAR_METADMA_INTR_SHIFT 6 /* BVNT_INTR2 :: PCI_CLEAR :: RXDMA3_INTR [05:05] */ #define BCHP_BVNT_INTR2_PCI_CLEAR_RXDMA3_INTR_MASK 0x00000020 #define BCHP_BVNT_INTR2_PCI_CLEAR_RXDMA3_INTR_SHIFT 5 /* BVNT_INTR2 :: PCI_CLEAR :: TXDMA_INTR [04:04] */ #define BCHP_BVNT_INTR2_PCI_CLEAR_TXDMA_INTR_MASK 0x00000010 #define BCHP_BVNT_INTR2_PCI_CLEAR_TXDMA_INTR_SHIFT 4 /* BVNT_INTR2 :: PCI_CLEAR :: SCL_INTR [03:03] */ #define BCHP_BVNT_INTR2_PCI_CLEAR_SCL_INTR_MASK 0x00000008 #define BCHP_BVNT_INTR2_PCI_CLEAR_SCL_INTR_SHIFT 3 /* BVNT_INTR2 :: PCI_CLEAR :: DNR_INTR [02:02] */ #define BCHP_BVNT_INTR2_PCI_CLEAR_DNR_INTR_MASK 0x00000004 #define BCHP_BVNT_INTR2_PCI_CLEAR_DNR_INTR_SHIFT 2 /* BVNT_INTR2 :: PCI_CLEAR :: EOF_INTR [01:01] */ #define BCHP_BVNT_INTR2_PCI_CLEAR_EOF_INTR_MASK 0x00000002 #define BCHP_BVNT_INTR2_PCI_CLEAR_EOF_INTR_SHIFT 1 /* BVNT_INTR2 :: PCI_CLEAR :: MFD_INTR [00:00] */ #define BCHP_BVNT_INTR2_PCI_CLEAR_MFD_INTR_MASK 0x00000001 #define BCHP_BVNT_INTR2_PCI_CLEAR_MFD_INTR_SHIFT 0 /*************************************************************************** *PCI_MASK_STATUS - PCI interrupt Mask Status Register ***************************************************************************/ /* BVNT_INTR2 :: PCI_MASK_STATUS :: reserved0 [31:09] */ #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_reserved0_MASK 0xfffffe00 #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_reserved0_SHIFT 9 /* BVNT_INTR2 :: PCI_MASK_STATUS :: BOP_EOF_INTR [08:08] */ #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_BOP_EOF_INTR_MASK 0x00000100 #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_BOP_EOF_INTR_SHIFT 8 /* BVNT_INTR2 :: PCI_MASK_STATUS :: BVN_EOF_INTR [07:07] */ #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_BVN_EOF_INTR_MASK 0x00000080 #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_BVN_EOF_INTR_SHIFT 7 /* BVNT_INTR2 :: PCI_MASK_STATUS :: METADMA_INTR [06:06] */ #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_METADMA_INTR_MASK 0x00000040 #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_METADMA_INTR_SHIFT 6 /* BVNT_INTR2 :: PCI_MASK_STATUS :: RXDMA3_INTR [05:05] */ #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_RXDMA3_INTR_MASK 0x00000020 #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_RXDMA3_INTR_SHIFT 5 /* BVNT_INTR2 :: PCI_MASK_STATUS :: TXDMA_INTR [04:04] */ #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_TXDMA_INTR_MASK 0x00000010 #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_TXDMA_INTR_SHIFT 4 /* BVNT_INTR2 :: PCI_MASK_STATUS :: SCL_INTR [03:03] */ #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_SCL_INTR_MASK 0x00000008 #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_SCL_INTR_SHIFT 3 /* BVNT_INTR2 :: PCI_MASK_STATUS :: DNR_INTR [02:02] */ #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_DNR_INTR_MASK 0x00000004 #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_DNR_INTR_SHIFT 2 /* BVNT_INTR2 :: PCI_MASK_STATUS :: EOF_INTR [01:01] */ #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_EOF_INTR_MASK 0x00000002 #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_EOF_INTR_SHIFT 1 /* BVNT_INTR2 :: PCI_MASK_STATUS :: MFD_INTR [00:00] */ #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_MFD_INTR_MASK 0x00000001 #define BCHP_BVNT_INTR2_PCI_MASK_STATUS_MFD_INTR_SHIFT 0 /*************************************************************************** *PCI_MASK_SET - PCI interrupt Mask Set Register ***************************************************************************/ /* BVNT_INTR2 :: PCI_MASK_SET :: reserved0 [31:09] */ #define BCHP_BVNT_INTR2_PCI_MASK_SET_reserved0_MASK 0xfffffe00 #define BCHP_BVNT_INTR2_PCI_MASK_SET_reserved0_SHIFT 9 /* BVNT_INTR2 :: PCI_MASK_SET :: BOP_EOF_INTR [08:08] */ #define BCHP_BVNT_INTR2_PCI_MASK_SET_BOP_EOF_INTR_MASK 0x00000100 #define BCHP_BVNT_INTR2_PCI_MASK_SET_BOP_EOF_INTR_SHIFT 8 /* BVNT_INTR2 :: PCI_MASK_SET :: BVN_EOF_INTR [07:07] */ #define BCHP_BVNT_INTR2_PCI_MASK_SET_BVN_EOF_INTR_MASK 0x00000080 #define BCHP_BVNT_INTR2_PCI_MASK_SET_BVN_EOF_INTR_SHIFT 7 /* BVNT_INTR2 :: PCI_MASK_SET :: METADMA_INTR [06:06] */ #define BCHP_BVNT_INTR2_PCI_MASK_SET_METADMA_INTR_MASK 0x00000040 #define BCHP_BVNT_INTR2_PCI_MASK_SET_METADMA_INTR_SHIFT 6 /* BVNT_INTR2 :: PCI_MASK_SET :: RXDMA3_INTR [05:05] */ #define BCHP_BVNT_INTR2_PCI_MASK_SET_RXDMA3_INTR_MASK 0x00000020 #define BCHP_BVNT_INTR2_PCI_MASK_SET_RXDMA3_INTR_SHIFT 5 /* BVNT_INTR2 :: PCI_MASK_SET :: TXDMA_INTR [04:04] */ #define BCHP_BVNT_INTR2_PCI_MASK_SET_TXDMA_INTR_MASK 0x00000010 #define BCHP_BVNT_INTR2_PCI_MASK_SET_TXDMA_INTR_SHIFT 4 /* BVNT_INTR2 :: PCI_MASK_SET :: SCL_INTR [03:03] */ #define BCHP_BVNT_INTR2_PCI_MASK_SET_SCL_INTR_MASK 0x00000008 #define BCHP_BVNT_INTR2_PCI_MASK_SET_SCL_INTR_SHIFT 3 /* BVNT_INTR2 :: PCI_MASK_SET :: DNR_INTR [02:02] */ #define BCHP_BVNT_INTR2_PCI_MASK_SET_DNR_INTR_MASK 0x00000004 #define BCHP_BVNT_INTR2_PCI_MASK_SET_DNR_INTR_SHIFT 2 /* BVNT_INTR2 :: PCI_MASK_SET :: EOF_INTR [01:01] */ #define BCHP_BVNT_INTR2_PCI_MASK_SET_EOF_INTR_MASK 0x00000002 #define BCHP_BVNT_INTR2_PCI_MASK_SET_EOF_INTR_SHIFT 1 /* BVNT_INTR2 :: PCI_MASK_SET :: MFD_INTR [00:00] */ #define BCHP_BVNT_INTR2_PCI_MASK_SET_MFD_INTR_MASK 0x00000001 #define BCHP_BVNT_INTR2_PCI_MASK_SET_MFD_INTR_SHIFT 0 /*************************************************************************** *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register ***************************************************************************/ /* BVNT_INTR2 :: PCI_MASK_CLEAR :: reserved0 [31:09] */ #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_reserved0_MASK 0xfffffe00 #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_reserved0_SHIFT 9 /* BVNT_INTR2 :: PCI_MASK_CLEAR :: BOP_EOF_INTR [08:08] */ #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_BOP_EOF_INTR_MASK 0x00000100 #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_BOP_EOF_INTR_SHIFT 8 /* BVNT_INTR2 :: PCI_MASK_CLEAR :: BVN_EOF_INTR [07:07] */ #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_BVN_EOF_INTR_MASK 0x00000080 #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_BVN_EOF_INTR_SHIFT 7 /* BVNT_INTR2 :: PCI_MASK_CLEAR :: METADMA_INTR [06:06] */ #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_METADMA_INTR_MASK 0x00000040 #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_METADMA_INTR_SHIFT 6 /* BVNT_INTR2 :: PCI_MASK_CLEAR :: RXDMA3_INTR [05:05] */ #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_RXDMA3_INTR_MASK 0x00000020 #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_RXDMA3_INTR_SHIFT 5 /* BVNT_INTR2 :: PCI_MASK_CLEAR :: TXDMA_INTR [04:04] */ #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_TXDMA_INTR_MASK 0x00000010 #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_TXDMA_INTR_SHIFT 4 /* BVNT_INTR2 :: PCI_MASK_CLEAR :: SCL_INTR [03:03] */ #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_SCL_INTR_MASK 0x00000008 #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_SCL_INTR_SHIFT 3 /* BVNT_INTR2 :: PCI_MASK_CLEAR :: DNR_INTR [02:02] */ #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_DNR_INTR_MASK 0x00000004 #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_DNR_INTR_SHIFT 2 /* BVNT_INTR2 :: PCI_MASK_CLEAR :: EOF_INTR [01:01] */ #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_EOF_INTR_MASK 0x00000002 #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_EOF_INTR_SHIFT 1 /* BVNT_INTR2 :: PCI_MASK_CLEAR :: MFD_INTR [00:00] */ #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_MFD_INTR_MASK 0x00000001 #define BCHP_BVNT_INTR2_PCI_MASK_CLEAR_MFD_INTR_SHIFT 0 #endif /* #ifndef BCHP_BVNT_INTR2_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000014600000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc2.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc2.0000644000175000017500000003017211610313111030634 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_misc2.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:11p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:37 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc2.h $ * * Hydra_Software_Devel/1 7/17/09 8:11p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_MISC2_H__ #define BCHP_MISC2_H__ /*************************************************************************** *MISC2 - Registers for Meta DMA, Direct DRAM Access, Global Controls ***************************************************************************/ #define BCHP_MISC2_GLOBAL_CTRL 0x00502100 /* Global Control Register */ #define BCHP_MISC2_INTERNAL_STATUS 0x00502104 /* Internal Status Register */ #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL 0x00502108 /* Internal Debug Mux Control */ #define BCHP_MISC2_DEBUG_FIFO_LENGTH 0x0050210c /* Debug FIFO Length */ #define BCHP_MISC2_WRITE_BLOCKOUT_COUNT 0x00502110 /* Write Blockout Count */ #define BCHP_MISC2_META_DATA_BASE_ADDR 0x00502114 /* Meta Data Base DRAM Address */ #define BCHP_MISC2_META_DATA_LENGTH 0x00502118 /* Meta Data Length */ #define BCHP_MISC2_DIRECT_WINDOW_STATUS 0x0050211c /* Direct DRAM Access Window Status */ #define BCHP_MISC2_DIRECT_WINDOW_CONTROL 0x00502120 /* Direct DRAM Access Window Control */ /*************************************************************************** *GLOBAL_CTRL - Global Control Register ***************************************************************************/ /* MISC2 :: GLOBAL_CTRL :: reserved0 [31:07] */ #define BCHP_MISC2_GLOBAL_CTRL_reserved0_MASK 0xffffff80 #define BCHP_MISC2_GLOBAL_CTRL_reserved0_SHIFT 7 /* MISC2 :: GLOBAL_CTRL :: BURST_64_BYTES [06:06] */ #define BCHP_MISC2_GLOBAL_CTRL_BURST_64_BYTES_MASK 0x00000040 #define BCHP_MISC2_GLOBAL_CTRL_BURST_64_BYTES_SHIFT 6 /* MISC2 :: GLOBAL_CTRL :: BOP_DRAIN [05:05] */ #define BCHP_MISC2_GLOBAL_CTRL_BOP_DRAIN_MASK 0x00000020 #define BCHP_MISC2_GLOBAL_CTRL_BOP_DRAIN_SHIFT 5 /* MISC2 :: GLOBAL_CTRL :: META_DMA_ENABLE [04:04] */ #define BCHP_MISC2_GLOBAL_CTRL_META_DMA_ENABLE_MASK 0x00000010 #define BCHP_MISC2_GLOBAL_CTRL_META_DMA_ENABLE_SHIFT 4 /* MISC2 :: GLOBAL_CTRL :: BVN_CHECKSUM_10BITS [03:03] */ #define BCHP_MISC2_GLOBAL_CTRL_BVN_CHECKSUM_10BITS_MASK 0x00000008 #define BCHP_MISC2_GLOBAL_CTRL_BVN_CHECKSUM_10BITS_SHIFT 3 /* MISC2 :: GLOBAL_CTRL :: BVN_10B_TO_8B [02:02] */ #define BCHP_MISC2_GLOBAL_CTRL_BVN_10B_TO_8B_MASK 0x00000004 #define BCHP_MISC2_GLOBAL_CTRL_BVN_10B_TO_8B_SHIFT 2 /* MISC2 :: GLOBAL_CTRL :: BVN_YUY2_MODE [01:01] */ #define BCHP_MISC2_GLOBAL_CTRL_BVN_YUY2_MODE_MASK 0x00000002 #define BCHP_MISC2_GLOBAL_CTRL_BVN_YUY2_MODE_SHIFT 1 /* MISC2 :: GLOBAL_CTRL :: BVN_420_MODE [00:00] */ #define BCHP_MISC2_GLOBAL_CTRL_BVN_420_MODE_MASK 0x00000001 #define BCHP_MISC2_GLOBAL_CTRL_BVN_420_MODE_SHIFT 0 /*************************************************************************** *INTERNAL_STATUS - Internal Status Register ***************************************************************************/ /* MISC2 :: INTERNAL_STATUS :: META_DATA_ACTIVE [31:31] */ #define BCHP_MISC2_INTERNAL_STATUS_META_DATA_ACTIVE_MASK 0x80000000 #define BCHP_MISC2_INTERNAL_STATUS_META_DATA_ACTIVE_SHIFT 31 /* MISC2 :: INTERNAL_STATUS :: reserved0 [30:10] */ #define BCHP_MISC2_INTERNAL_STATUS_reserved0_MASK 0x7ffffc00 #define BCHP_MISC2_INTERNAL_STATUS_reserved0_SHIFT 10 /* MISC2 :: INTERNAL_STATUS :: BVN_BYTE_COUNT_FIFO_FULL [09:09] */ #define BCHP_MISC2_INTERNAL_STATUS_BVN_BYTE_COUNT_FIFO_FULL_MASK 0x00000200 #define BCHP_MISC2_INTERNAL_STATUS_BVN_BYTE_COUNT_FIFO_FULL_SHIFT 9 /* MISC2 :: INTERNAL_STATUS :: BVN_DATA_FIFO_FULL [08:08] */ #define BCHP_MISC2_INTERNAL_STATUS_BVN_DATA_FIFO_FULL_MASK 0x00000100 #define BCHP_MISC2_INTERNAL_STATUS_BVN_DATA_FIFO_FULL_SHIFT 8 /* MISC2 :: INTERNAL_STATUS :: reserved1 [07:06] */ #define BCHP_MISC2_INTERNAL_STATUS_reserved1_MASK 0x000000c0 #define BCHP_MISC2_INTERNAL_STATUS_reserved1_SHIFT 6 /* MISC2 :: INTERNAL_STATUS :: BVN_BYTE_COUNT_FIFO_EMPTY [05:05] */ #define BCHP_MISC2_INTERNAL_STATUS_BVN_BYTE_COUNT_FIFO_EMPTY_MASK 0x00000020 #define BCHP_MISC2_INTERNAL_STATUS_BVN_BYTE_COUNT_FIFO_EMPTY_SHIFT 5 /* MISC2 :: INTERNAL_STATUS :: BVN_DATA_FIFO_EMPTY [04:04] */ #define BCHP_MISC2_INTERNAL_STATUS_BVN_DATA_FIFO_EMPTY_MASK 0x00000010 #define BCHP_MISC2_INTERNAL_STATUS_BVN_DATA_FIFO_EMPTY_SHIFT 4 /* MISC2 :: INTERNAL_STATUS :: reserved2 [03:00] */ #define BCHP_MISC2_INTERNAL_STATUS_reserved2_MASK 0x0000000f #define BCHP_MISC2_INTERNAL_STATUS_reserved2_SHIFT 0 /*************************************************************************** *INTERNAL_STATUS_MUX_CTRL - Internal Debug Mux Control ***************************************************************************/ /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: reserved0 [31:16] */ #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_MASK 0xffff0000 #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_reserved0_SHIFT 16 /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: CLK_OUT_ALT_SRC [15:15] */ #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_MASK 0x00008000 #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_CLK_OUT_ALT_SRC_SHIFT 15 /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_CLK_SEL [14:12] */ #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_MASK 0x00007000 #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CLK_SEL_SHIFT 12 /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: reserved1 [11:09] */ #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_MASK 0x00000e00 #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_reserved1_SHIFT 9 /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_TOP_CORE_SEL [08:08] */ #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_MASK 0x00000100 #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_TOP_CORE_SEL_SHIFT 8 /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_CORE_BLK_SEL [07:04] */ #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_MASK 0x000000f0 #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_CORE_BLK_SEL_SHIFT 4 /* MISC2 :: INTERNAL_STATUS_MUX_CTRL :: DEBUG_VECTOR_SEL [03:00] */ #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_MASK 0x0000000f #define BCHP_MISC2_INTERNAL_STATUS_MUX_CTRL_DEBUG_VECTOR_SEL_SHIFT 0 /*************************************************************************** *DEBUG_FIFO_LENGTH - Debug FIFO Length ***************************************************************************/ /* MISC2 :: DEBUG_FIFO_LENGTH :: reserved0 [31:21] */ #define BCHP_MISC2_DEBUG_FIFO_LENGTH_reserved0_MASK 0xffe00000 #define BCHP_MISC2_DEBUG_FIFO_LENGTH_reserved0_SHIFT 21 /* MISC2 :: DEBUG_FIFO_LENGTH :: FIFO_LENGTH [20:00] */ #define BCHP_MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_MASK 0x001fffff #define BCHP_MISC2_DEBUG_FIFO_LENGTH_FIFO_LENGTH_SHIFT 0 /*************************************************************************** *WRITE_BLOCKOUT_COUNT - Write Blockout Count ***************************************************************************/ /* MISC2 :: WRITE_BLOCKOUT_COUNT :: reserved0 [31:16] */ #define BCHP_MISC2_WRITE_BLOCKOUT_COUNT_reserved0_MASK 0xffff0000 #define BCHP_MISC2_WRITE_BLOCKOUT_COUNT_reserved0_SHIFT 16 /* MISC2 :: WRITE_BLOCKOUT_COUNT :: BLOCKOUT_COUNT [15:00] */ #define BCHP_MISC2_WRITE_BLOCKOUT_COUNT_BLOCKOUT_COUNT_MASK 0x0000ffff #define BCHP_MISC2_WRITE_BLOCKOUT_COUNT_BLOCKOUT_COUNT_SHIFT 0 /*************************************************************************** *META_DATA_BASE_ADDR - Meta Data Base DRAM Address ***************************************************************************/ /* MISC2 :: META_DATA_BASE_ADDR :: META_DATA_BASE_ADDR [31:00] */ #define BCHP_MISC2_META_DATA_BASE_ADDR_META_DATA_BASE_ADDR_MASK 0xffffffff #define BCHP_MISC2_META_DATA_BASE_ADDR_META_DATA_BASE_ADDR_SHIFT 0 /*************************************************************************** *META_DATA_LENGTH - Meta Data Length ***************************************************************************/ /* MISC2 :: META_DATA_LENGTH :: reserved0 [31:24] */ #define BCHP_MISC2_META_DATA_LENGTH_reserved0_MASK 0xff000000 #define BCHP_MISC2_META_DATA_LENGTH_reserved0_SHIFT 24 /* MISC2 :: META_DATA_LENGTH :: META_DATA_LENGTH [23:00] */ #define BCHP_MISC2_META_DATA_LENGTH_META_DATA_LENGTH_MASK 0x00ffffff #define BCHP_MISC2_META_DATA_LENGTH_META_DATA_LENGTH_SHIFT 0 /*************************************************************************** *DIRECT_WINDOW_STATUS - Direct DRAM Access Window Status ***************************************************************************/ /* MISC2 :: DIRECT_WINDOW_STATUS :: reserved0 [31:01] */ #define BCHP_MISC2_DIRECT_WINDOW_STATUS_reserved0_MASK 0xfffffffe #define BCHP_MISC2_DIRECT_WINDOW_STATUS_reserved0_SHIFT 1 /* MISC2 :: DIRECT_WINDOW_STATUS :: DIRECT_BUSY [00:00] */ #define BCHP_MISC2_DIRECT_WINDOW_STATUS_DIRECT_BUSY_MASK 0x00000001 #define BCHP_MISC2_DIRECT_WINDOW_STATUS_DIRECT_BUSY_SHIFT 0 /*************************************************************************** *DIRECT_WINDOW_CONTROL - Direct DRAM Access Window Control ***************************************************************************/ /* MISC2 :: DIRECT_WINDOW_CONTROL :: DIRECT_WINDOW_BASE_ADDR [31:16] */ #define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK 0xffff0000 #define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_SHIFT 16 /* MISC2 :: DIRECT_WINDOW_CONTROL :: reserved0 [15:02] */ #define BCHP_MISC2_DIRECT_WINDOW_CONTROL_reserved0_MASK 0x0000fffc #define BCHP_MISC2_DIRECT_WINDOW_CONTROL_reserved0_SHIFT 2 /* MISC2 :: DIRECT_WINDOW_CONTROL :: DIRECT_WINDOW_POST_WRITES [01:01] */ #define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_POST_WRITES_MASK 0x00000002 #define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_POST_WRITES_SHIFT 1 /* MISC2 :: DIRECT_WINDOW_CONTROL :: DIRECT_WINDOW_ENABLE [00:00] */ #define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK 0x00000001 #define BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_SHIFT 0 #endif /* #ifndef BCHP_MISC2_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015600000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_main_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000003451411610313111030770 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_main_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:04p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:33 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_main_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:04p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_MAIN_0_H__ #define BCHP_DECODE_MAIN_0_H__ /*************************************************************************** *DECODE_MAIN_0 ***************************************************************************/ #define BCHP_DECODE_MAIN_0_REG_MAINCTL 0x00800100 /* Decoder Control */ #define BCHP_DECODE_MAIN_0_REG_FRAMESIZE 0x00800104 /* Size of the picture being decoded */ #define BCHP_DECODE_MAIN_0_REG_DEC_VERSION 0x00800108 /* Version of the decoder core */ #define BCHP_DECODE_MAIN_0_REG_STATUS 0x00800110 /* Provides back-end decoder processing status */ #define BCHP_DECODE_MAIN_0_REG_PMONCTL 0x00800120 /* Performance Monitoring */ #define BCHP_DECODE_MAIN_0_REG_PMONCNT0 0x00800124 /* REG_PMONCNT0 */ #define BCHP_DECODE_MAIN_0_REG_PMONCNT1 0x00800128 /* REG_PMONCNT1 */ #define BCHP_DECODE_MAIN_0_REG_PMON_MBCTL 0x0080012c /* REG_PMON_MBCTL */ #define BCHP_DECODE_MAIN_0_DBLK_BUFF_CONTROL 0x00800130 /* DBLK_BUFF_CONTROL */ #define BCHP_DECODE_MAIN_0_REG_MAIN_END 0x008001fc /* REG_MAIN_END */ /*************************************************************************** *REG_MAINCTL - Decoder Control ***************************************************************************/ /* DECODE_MAIN_0 :: REG_MAINCTL :: USE_2_OFF [31:31] */ #define BCHP_DECODE_MAIN_0_REG_MAINCTL_USE_2_OFF_MASK 0x80000000 #define BCHP_DECODE_MAIN_0_REG_MAINCTL_USE_2_OFF_SHIFT 31 /* DECODE_MAIN_0 :: REG_MAINCTL :: reserved0 [30:29] */ #define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved0_MASK 0x60000000 #define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved0_SHIFT 29 /* DECODE_MAIN_0 :: REG_MAINCTL :: QPC_OFFSET2 [28:24] */ #define BCHP_DECODE_MAIN_0_REG_MAINCTL_QPC_OFFSET2_MASK 0x1f000000 #define BCHP_DECODE_MAIN_0_REG_MAINCTL_QPC_OFFSET2_SHIFT 24 /* DECODE_MAIN_0 :: REG_MAINCTL :: reserved1 [23:21] */ #define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved1_MASK 0x00e00000 #define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved1_SHIFT 21 /* DECODE_MAIN_0 :: REG_MAINCTL :: QpC_Offset [20:16] */ #define BCHP_DECODE_MAIN_0_REG_MAINCTL_QpC_Offset_MASK 0x001f0000 #define BCHP_DECODE_MAIN_0_REG_MAINCTL_QpC_Offset_SHIFT 16 /* DECODE_MAIN_0 :: REG_MAINCTL :: reserved2 [15:13] */ #define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved2_MASK 0x0000e000 #define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved2_SHIFT 13 /* DECODE_MAIN_0 :: REG_MAINCTL :: use_alt_mocomp [12:12] */ #define BCHP_DECODE_MAIN_0_REG_MAINCTL_use_alt_mocomp_MASK 0x00001000 #define BCHP_DECODE_MAIN_0_REG_MAINCTL_use_alt_mocomp_SHIFT 12 /* DECODE_MAIN_0 :: REG_MAINCTL :: use_alt_xform [11:11] */ #define BCHP_DECODE_MAIN_0_REG_MAINCTL_use_alt_xform_MASK 0x00000800 #define BCHP_DECODE_MAIN_0_REG_MAINCTL_use_alt_xform_SHIFT 11 /* DECODE_MAIN_0 :: REG_MAINCTL :: block_ppbuf_avail [10:10] */ #define BCHP_DECODE_MAIN_0_REG_MAINCTL_block_ppbuf_avail_MASK 0x00000400 #define BCHP_DECODE_MAIN_0_REG_MAINCTL_block_ppbuf_avail_SHIFT 10 /* DECODE_MAIN_0 :: REG_MAINCTL :: Standard [09:07] */ #define BCHP_DECODE_MAIN_0_REG_MAINCTL_Standard_MASK 0x00000380 #define BCHP_DECODE_MAIN_0_REG_MAINCTL_Standard_SHIFT 7 /* DECODE_MAIN_0 :: REG_MAINCTL :: Profile [06:04] */ #define BCHP_DECODE_MAIN_0_REG_MAINCTL_Profile_MASK 0x00000070 #define BCHP_DECODE_MAIN_0_REG_MAINCTL_Profile_SHIFT 4 /* DECODE_MAIN_0 :: REG_MAINCTL :: reserved3 [03:01] */ #define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved3_MASK 0x0000000e #define BCHP_DECODE_MAIN_0_REG_MAINCTL_reserved3_SHIFT 1 /* DECODE_MAIN_0 :: REG_MAINCTL :: Rst [00:00] */ #define BCHP_DECODE_MAIN_0_REG_MAINCTL_Rst_MASK 0x00000001 #define BCHP_DECODE_MAIN_0_REG_MAINCTL_Rst_SHIFT 0 /*************************************************************************** *REG_FRAMESIZE - Size of the picture being decoded ***************************************************************************/ /* DECODE_MAIN_0 :: REG_FRAMESIZE :: reserved0 [31:28] */ #define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_reserved0_MASK 0xf0000000 #define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_reserved0_SHIFT 28 /* DECODE_MAIN_0 :: REG_FRAMESIZE :: Lines [27:16] */ #define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_Lines_MASK 0x0fff0000 #define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_Lines_SHIFT 16 /* DECODE_MAIN_0 :: REG_FRAMESIZE :: reserved1 [15:12] */ #define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_reserved1_MASK 0x0000f000 #define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_reserved1_SHIFT 12 /* DECODE_MAIN_0 :: REG_FRAMESIZE :: Pixels [11:00] */ #define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_Pixels_MASK 0x00000fff #define BCHP_DECODE_MAIN_0_REG_FRAMESIZE_Pixels_SHIFT 0 /*************************************************************************** *REG_DEC_VERSION - Version of the decoder core ***************************************************************************/ /* DECODE_MAIN_0 :: REG_DEC_VERSION :: Major [31:16] */ #define BCHP_DECODE_MAIN_0_REG_DEC_VERSION_Major_MASK 0xffff0000 #define BCHP_DECODE_MAIN_0_REG_DEC_VERSION_Major_SHIFT 16 /* DECODE_MAIN_0 :: REG_DEC_VERSION :: Minor [15:08] */ #define BCHP_DECODE_MAIN_0_REG_DEC_VERSION_Minor_MASK 0x0000ff00 #define BCHP_DECODE_MAIN_0_REG_DEC_VERSION_Minor_SHIFT 8 /* DECODE_MAIN_0 :: REG_DEC_VERSION :: FixID [07:00] */ #define BCHP_DECODE_MAIN_0_REG_DEC_VERSION_FixID_MASK 0x000000ff #define BCHP_DECODE_MAIN_0_REG_DEC_VERSION_FixID_SHIFT 0 /*************************************************************************** *REG_STATUS - Provides back-end decoder processing status ***************************************************************************/ /* DECODE_MAIN_0 :: REG_STATUS :: Ixfm [31:30] */ #define BCHP_DECODE_MAIN_0_REG_STATUS_Ixfm_MASK 0xc0000000 #define BCHP_DECODE_MAIN_0_REG_STATUS_Ixfm_SHIFT 30 /* DECODE_MAIN_0 :: REG_STATUS :: Spre [29:28] */ #define BCHP_DECODE_MAIN_0_REG_STATUS_Spre_MASK 0x30000000 #define BCHP_DECODE_MAIN_0_REG_STATUS_Spre_SHIFT 28 /* DECODE_MAIN_0 :: REG_STATUS :: Mcom [27:26] */ #define BCHP_DECODE_MAIN_0_REG_STATUS_Mcom_MASK 0x0c000000 #define BCHP_DECODE_MAIN_0_REG_STATUS_Mcom_SHIFT 26 /* DECODE_MAIN_0 :: REG_STATUS :: reserved0 [25:22] */ #define BCHP_DECODE_MAIN_0_REG_STATUS_reserved0_MASK 0x03c00000 #define BCHP_DECODE_MAIN_0_REG_STATUS_reserved0_SHIFT 22 /* DECODE_MAIN_0 :: REG_STATUS :: InpBuf_Overflow [21:16] */ #define BCHP_DECODE_MAIN_0_REG_STATUS_InpBuf_Overflow_MASK 0x003f0000 #define BCHP_DECODE_MAIN_0_REG_STATUS_InpBuf_Overflow_SHIFT 16 /* DECODE_MAIN_0 :: REG_STATUS :: mocomp_data_avail [15:15] */ #define BCHP_DECODE_MAIN_0_REG_STATUS_mocomp_data_avail_MASK 0x00008000 #define BCHP_DECODE_MAIN_0_REG_STATUS_mocomp_data_avail_SHIFT 15 /* DECODE_MAIN_0 :: REG_STATUS :: xform_data_avail [14:14] */ #define BCHP_DECODE_MAIN_0_REG_STATUS_xform_data_avail_MASK 0x00004000 #define BCHP_DECODE_MAIN_0_REG_STATUS_xform_data_avail_SHIFT 14 /* DECODE_MAIN_0 :: REG_STATUS :: Output [13:12] */ #define BCHP_DECODE_MAIN_0_REG_STATUS_Output_MASK 0x00003000 #define BCHP_DECODE_MAIN_0_REG_STATUS_Output_SHIFT 12 /* DECODE_MAIN_0 :: REG_STATUS :: Dblk [11:10] */ #define BCHP_DECODE_MAIN_0_REG_STATUS_Dblk_MASK 0x00000c00 #define BCHP_DECODE_MAIN_0_REG_STATUS_Dblk_SHIFT 10 /* DECODE_MAIN_0 :: REG_STATUS :: Recon [09:08] */ #define BCHP_DECODE_MAIN_0_REG_STATUS_Recon_MASK 0x00000300 #define BCHP_DECODE_MAIN_0_REG_STATUS_Recon_SHIFT 8 /* DECODE_MAIN_0 :: REG_STATUS :: reserved1 [07:00] */ #define BCHP_DECODE_MAIN_0_REG_STATUS_reserved1_MASK 0x000000ff #define BCHP_DECODE_MAIN_0_REG_STATUS_reserved1_SHIFT 0 /*************************************************************************** *REG_PMONCTL - Performance Monitoring ***************************************************************************/ /* DECODE_MAIN_0 :: REG_PMONCTL :: reserved0 [31:12] */ #define BCHP_DECODE_MAIN_0_REG_PMONCTL_reserved0_MASK 0xfffff000 #define BCHP_DECODE_MAIN_0_REG_PMONCTL_reserved0_SHIFT 12 /* DECODE_MAIN_0 :: REG_PMONCTL :: CNT1_SEL [11:08] */ #define BCHP_DECODE_MAIN_0_REG_PMONCTL_CNT1_SEL_MASK 0x00000f00 #define BCHP_DECODE_MAIN_0_REG_PMONCTL_CNT1_SEL_SHIFT 8 /* DECODE_MAIN_0 :: REG_PMONCTL :: reserved1 [07:04] */ #define BCHP_DECODE_MAIN_0_REG_PMONCTL_reserved1_MASK 0x000000f0 #define BCHP_DECODE_MAIN_0_REG_PMONCTL_reserved1_SHIFT 4 /* DECODE_MAIN_0 :: REG_PMONCTL :: CNT0_SEL [03:00] */ #define BCHP_DECODE_MAIN_0_REG_PMONCTL_CNT0_SEL_MASK 0x0000000f #define BCHP_DECODE_MAIN_0_REG_PMONCTL_CNT0_SEL_SHIFT 0 /*************************************************************************** *REG_PMONCNT0 - REG_PMONCNT0 ***************************************************************************/ /* DECODE_MAIN_0 :: REG_PMONCNT0 :: DATA [31:16] */ #define BCHP_DECODE_MAIN_0_REG_PMONCNT0_DATA_MASK 0xffff0000 #define BCHP_DECODE_MAIN_0_REG_PMONCNT0_DATA_SHIFT 16 /* DECODE_MAIN_0 :: REG_PMONCNT0 :: reserved0 [15:12] */ #define BCHP_DECODE_MAIN_0_REG_PMONCNT0_reserved0_MASK 0x0000f000 #define BCHP_DECODE_MAIN_0_REG_PMONCNT0_reserved0_SHIFT 12 /* DECODE_MAIN_0 :: REG_PMONCNT0 :: COUNT [11:00] */ #define BCHP_DECODE_MAIN_0_REG_PMONCNT0_COUNT_MASK 0x00000fff #define BCHP_DECODE_MAIN_0_REG_PMONCNT0_COUNT_SHIFT 0 /*************************************************************************** *REG_PMONCNT1 - REG_PMONCNT1 ***************************************************************************/ /* DECODE_MAIN_0 :: REG_PMONCNT1 :: DATA [31:16] */ #define BCHP_DECODE_MAIN_0_REG_PMONCNT1_DATA_MASK 0xffff0000 #define BCHP_DECODE_MAIN_0_REG_PMONCNT1_DATA_SHIFT 16 /* DECODE_MAIN_0 :: REG_PMONCNT1 :: reserved0 [15:12] */ #define BCHP_DECODE_MAIN_0_REG_PMONCNT1_reserved0_MASK 0x0000f000 #define BCHP_DECODE_MAIN_0_REG_PMONCNT1_reserved0_SHIFT 12 /* DECODE_MAIN_0 :: REG_PMONCNT1 :: COUNT [11:00] */ #define BCHP_DECODE_MAIN_0_REG_PMONCNT1_COUNT_MASK 0x00000fff #define BCHP_DECODE_MAIN_0_REG_PMONCNT1_COUNT_SHIFT 0 /*************************************************************************** *REG_PMON_MBCTL - REG_PMON_MBCTL ***************************************************************************/ /* DECODE_MAIN_0 :: REG_PMON_MBCTL :: reserved0 [31:02] */ #define BCHP_DECODE_MAIN_0_REG_PMON_MBCTL_reserved0_MASK 0xfffffffc #define BCHP_DECODE_MAIN_0_REG_PMON_MBCTL_reserved0_SHIFT 2 /* DECODE_MAIN_0 :: REG_PMON_MBCTL :: SW_Pmon [01:01] */ #define BCHP_DECODE_MAIN_0_REG_PMON_MBCTL_SW_Pmon_MASK 0x00000002 #define BCHP_DECODE_MAIN_0_REG_PMON_MBCTL_SW_Pmon_SHIFT 1 /* DECODE_MAIN_0 :: REG_PMON_MBCTL :: MBCtlEna [00:00] */ #define BCHP_DECODE_MAIN_0_REG_PMON_MBCTL_MBCtlEna_MASK 0x00000001 #define BCHP_DECODE_MAIN_0_REG_PMON_MBCTL_MBCtlEna_SHIFT 0 /*************************************************************************** *DBLK_BUFF_CONTROL - DBLK_BUFF_CONTROL ***************************************************************************/ /* DECODE_MAIN_0 :: DBLK_BUFF_CONTROL :: reserved0 [31:01] */ #define BCHP_DECODE_MAIN_0_DBLK_BUFF_CONTROL_reserved0_MASK 0xfffffffe #define BCHP_DECODE_MAIN_0_DBLK_BUFF_CONTROL_reserved0_SHIFT 1 /* DECODE_MAIN_0 :: DBLK_BUFF_CONTROL :: Enable [00:00] */ #define BCHP_DECODE_MAIN_0_DBLK_BUFF_CONTROL_Enable_MASK 0x00000001 #define BCHP_DECODE_MAIN_0_DBLK_BUFF_CONTROL_Enable_SHIFT 0 /*************************************************************************** *REG_MAIN_END - REG_MAIN_END ***************************************************************************/ /* DECODE_MAIN_0 :: REG_MAIN_END :: reserved0 [31:00] */ #define BCHP_DECODE_MAIN_0_REG_MAIN_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_MAIN_0_REG_MAIN_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_MAIN_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015100000000000011562 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_dll.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_d0000644000175000017500000011523111610313111030764 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pcie_dll.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:13p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:21 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pcie_dll.h $ * * Hydra_Software_Devel/1 7/17/09 8:13p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PCIE_DLL_H__ #define BCHP_PCIE_DLL_H__ /*************************************************************************** *PCIE_DLL - PCIE DLL related registers ***************************************************************************/ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL 0x00500500 /* DATA_LINK_CONTROL Register */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS 0x00500504 /* DATA_LINK_STATUS Register */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION 0x00500508 /* DATA_LINK_ATTENTION Register */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK 0x0050050c /* DATA_LINK_ATTENTION_MASK Register */ #define BCHP_PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00500510 /* NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ #define BCHP_PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00500514 /* ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ #define BCHP_PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG 0x00500518 /* PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register */ #define BCHP_PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG 0x0050051c /* RECEIVE_SEQUENCE_NUMBER_DEBUG Register */ #define BCHP_PCIE_DLL_DATA_LINK_REPLAY 0x00500520 /* DATA_LINK_REPLAY Register */ #define BCHP_PCIE_DLL_DATA_LINK_ACK_TIMEOUT 0x00500524 /* DATA_LINK_ACK_TIMEOUT Register */ #define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD 0x00500528 /* POWER_MANAGEMENT_THRESHOLD Register */ #define BCHP_PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG 0x0050052c /* RETRY_BUFFER_WRITE_POINTER_DEBUG Register */ #define BCHP_PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG 0x00500530 /* RETRY_BUFFER_READ_POINTER_DEBUG Register */ #define BCHP_PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG 0x00500534 /* RETRY_BUFFER_PURGED_POINTER_DEBUG Register */ #define BCHP_PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT 0x00500538 /* RETRY_BUFFER_READ_WRITE_DEBUG_PORT Register */ #define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD 0x0050053c /* ERROR_COUNT_THRESHOLD Register */ #define BCHP_PCIE_DLL_TL_ERROR_COUNTER 0x00500540 /* TL_ERROR_COUNTER Register */ #define BCHP_PCIE_DLL_DLLP_ERROR_COUNTER 0x00500544 /* DLLP_ERROR_COUNTER Register */ #define BCHP_PCIE_DLL_NAK_RECEIVED_COUNTER 0x00500548 /* NAK_RECEIVED_COUNTER Register */ #define BCHP_PCIE_DLL_DATA_LINK_TEST 0x0050054c /* DATA_LINK_TEST Register */ #define BCHP_PCIE_DLL_PACKET_BIST 0x00500550 /* PACKET_BIST Register */ #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL 0x00500554 /* LINK_PCIE_1_1_CONTROL Register */ /*************************************************************************** *DATA_LINK_CONTROL - DATA_LINK_CONTROL Register ***************************************************************************/ /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_0 [31:31] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_MASK 0x80000000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_0_SHIFT 31 /* PCIE_DLL :: DATA_LINK_CONTROL :: CQ28102_FIX_ENABLE [30:30] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ28102_FIX_ENABLE_MASK 0x40000000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ28102_FIX_ENABLE_SHIFT 30 /* PCIE_DLL :: DATA_LINK_CONTROL :: CQ28001_FIX_ENABLE [29:29] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_MASK 0x20000000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ28001_FIX_ENABLE_SHIFT 29 /* PCIE_DLL :: DATA_LINK_CONTROL :: CQ27820_FIX_ENABLE [28:28] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_MASK 0x10000000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ27820_FIX_ENABLE_SHIFT 28 /* PCIE_DLL :: DATA_LINK_CONTROL :: ASPM_L1_ENABLE [27:27] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_MASK 0x08000000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_ASPM_L1_ENABLE_SHIFT 27 /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_1 [26:25] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_MASK 0x06000000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_1_SHIFT 25 /* PCIE_DLL :: DATA_LINK_CONTROL :: CQ11211 [24:24] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ11211_MASK 0x01000000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CQ11211_SHIFT 24 /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_2 [23:23] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_MASK 0x00800000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_2_SHIFT 23 /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_3 [22:22] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_MASK 0x00400000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_3_SHIFT 22 /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_4 [21:21] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_MASK 0x00200000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_4_SHIFT 21 /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_5 [20:20] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_MASK 0x00100000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_5_SHIFT 20 /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_6 [19:19] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_MASK 0x00080000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_6_SHIFT 19 /* PCIE_DLL :: DATA_LINK_CONTROL :: PLL_REFSEL_SWITCH_CONTROL_CQ11011 [18:18] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_MASK 0x00040000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_PLL_REFSEL_SWITCH_CONTROL_CQ11011_SHIFT 18 /* PCIE_DLL :: DATA_LINK_CONTROL :: RESERVED_7 [17:17] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_MASK 0x00020000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_RESERVED_7_SHIFT 17 /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_MANAGEMENT_CONTROL [16:16] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_MASK 0x00010000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_SHIFT 16 /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_TRANSMITTER [15:15] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_MASK 0x00008000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_TRANSMITTER_SHIFT 15 /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_PLL [14:14] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_MASK 0x00004000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_PLL_SHIFT 14 /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_DOWN_SERDES_RECEIVER [13:13] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_MASK 0x00002000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_DOWN_SERDES_RECEIVER_SHIFT 13 /* PCIE_DLL :: DATA_LINK_CONTROL :: ENABLE_BEACON [12:12] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_MASK 0x00001000 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_ENABLE_BEACON_SHIFT 12 /* PCIE_DLL :: DATA_LINK_CONTROL :: AUTOMATIC_TIMER_THRESHOLD_ENABLE [11:11] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_MASK 0x00000800 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_AUTOMATIC_TIMER_THRESHOLD_ENABLE_SHIFT 11 /* PCIE_DLL :: DATA_LINK_CONTROL :: ENABLE_DLLP_TIMEOUT_MECHANISM [10:10] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_MASK 0x00000400 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_ENABLE_DLLP_TIMEOUT_MECHANISM_SHIFT 10 /* PCIE_DLL :: DATA_LINK_CONTROL :: CHECK_RECEIVE_FLOW_CONTROL_CREDITS [09:09] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_MASK 0x00000200 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_CHECK_RECEIVE_FLOW_CONTROL_CREDITS_SHIFT 9 /* PCIE_DLL :: DATA_LINK_CONTROL :: LINK_ENABLE [08:08] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_MASK 0x00000100 #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_LINK_ENABLE_SHIFT 8 /* PCIE_DLL :: DATA_LINK_CONTROL :: POWER_MANAGEMENT_CONTROL_2 [07:00] */ #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_MASK 0x000000ff #define BCHP_PCIE_DLL_DATA_LINK_CONTROL_POWER_MANAGEMENT_CONTROL_2_SHIFT 0 /*************************************************************************** *DATA_LINK_STATUS - DATA_LINK_STATUS Register ***************************************************************************/ /* PCIE_DLL :: DATA_LINK_STATUS :: RESERVED_0 [31:26] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_MASK 0xfc000000 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_RESERVED_0_SHIFT 26 /* PCIE_DLL :: DATA_LINK_STATUS :: PHY_LINK_STATE [25:23] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_MASK 0x03800000 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_PHY_LINK_STATE_SHIFT 23 /* PCIE_DLL :: DATA_LINK_STATUS :: POWER_MANAGEMENT_STATE [22:19] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_MASK 0x00780000 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_STATE_SHIFT 19 /* PCIE_DLL :: DATA_LINK_STATUS :: POWER_MANAGEMENT_SUB_STATE [18:17] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_MASK 0x00060000 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_POWER_MANAGEMENT_SUB_STATE_SHIFT 17 /* PCIE_DLL :: DATA_LINK_STATUS :: DATA_LINK_UP [16:16] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_MASK 0x00010000 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_UP_SHIFT 16 /* PCIE_DLL :: DATA_LINK_STATUS :: RESERVED_1 [15:11] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_MASK 0x0000f800 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_RESERVED_1_SHIFT 11 /* PCIE_DLL :: DATA_LINK_STATUS :: PME_TURN_OFF_STATUS_IN_D0 [10:10] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_MASK 0x00000400 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_PME_TURN_OFF_STATUS_IN_D0_SHIFT 10 /* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_UPDATE_TIMEOUT [09:09] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_MASK 0x00000200 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_UPDATE_TIMEOUT_SHIFT 9 /* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_RECEIVE_OVERFLOW [08:08] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_MASK 0x00000100 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_RECEIVE_OVERFLOW_SHIFT 8 /* PCIE_DLL :: DATA_LINK_STATUS :: FLOW_CONTROL_PROTOCOL_ERROR [07:07] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_MASK 0x00000080 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_FLOW_CONTROL_PROTOCOL_ERROR_SHIFT 7 /* PCIE_DLL :: DATA_LINK_STATUS :: DATA_LINK_PROTOCOL_ERROR [06:06] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_MASK 0x00000040 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_DATA_LINK_PROTOCOL_ERROR_SHIFT 6 /* PCIE_DLL :: DATA_LINK_STATUS :: REPLAY_ROLLOVER [05:05] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_MASK 0x00000020 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_REPLAY_ROLLOVER_SHIFT 5 /* PCIE_DLL :: DATA_LINK_STATUS :: REPLAY_TIMEOUT [04:04] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_MASK 0x00000010 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_REPLAY_TIMEOUT_SHIFT 4 /* PCIE_DLL :: DATA_LINK_STATUS :: NAK_RECEIVED [03:03] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_MASK 0x00000008 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_NAK_RECEIVED_SHIFT 3 /* PCIE_DLL :: DATA_LINK_STATUS :: DLLP_ERROR [02:02] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_MASK 0x00000004 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_DLLP_ERROR_SHIFT 2 /* PCIE_DLL :: DATA_LINK_STATUS :: BAD_TLP_SEQUENCE_NUMBER [01:01] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_MASK 0x00000002 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_BAD_TLP_SEQUENCE_NUMBER_SHIFT 1 /* PCIE_DLL :: DATA_LINK_STATUS :: TLP_ERROR [00:00] */ #define BCHP_PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_MASK 0x00000001 #define BCHP_PCIE_DLL_DATA_LINK_STATUS_TLP_ERROR_SHIFT 0 /*************************************************************************** *DATA_LINK_ATTENTION - DATA_LINK_ATTENTION Register ***************************************************************************/ /* PCIE_DLL :: DATA_LINK_ATTENTION :: RESERVED_0 [31:06] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_MASK 0xffffffc0 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_RESERVED_0_SHIFT 6 /* PCIE_DLL :: DATA_LINK_ATTENTION :: DATA_LINK_LAYER_PACKET_TEST_INDICATOR [05:05] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_MASK 0x00000020 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_PACKET_TEST_INDICATOR_SHIFT 5 /* PCIE_DLL :: DATA_LINK_ATTENTION :: DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR [04:04] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_MASK 0x00000010 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_DATA_LINK_LAYER_ERROR_ATTENTION_INDICATOR_SHIFT 4 /* PCIE_DLL :: DATA_LINK_ATTENTION :: NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR [03:03] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_MASK 0x00000008 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_NAK_RECEIVED_COUNTER_ATTENTION_INDICATOR_SHIFT 3 /* PCIE_DLL :: DATA_LINK_ATTENTION :: DLLP_ERROR_COUNTER_ATTENTION_INDICATOR [02:02] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_MASK 0x00000004 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_DLLP_ERROR_COUNTER_ATTENTION_INDICATOR_SHIFT 2 /* PCIE_DLL :: DATA_LINK_ATTENTION :: TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR [01:01] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_MASK 0x00000002 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_INDICATOR_SHIFT 1 /* PCIE_DLL :: DATA_LINK_ATTENTION :: TLP_ERROR_COUNTER_ATTENTION_INDICATOR [00:00] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_MASK 0x00000001 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_TLP_ERROR_COUNTER_ATTENTION_INDICATOR_SHIFT 0 /*************************************************************************** *DATA_LINK_ATTENTION_MASK - DATA_LINK_ATTENTION_MASK Register ***************************************************************************/ /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: RESERVED_0 [31:08] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_MASK 0xffffff00 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_RESERVED_0_SHIFT 8 /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: UNUSED_0 [07:06] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_MASK 0x000000c0 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_UNUSED_0_SHIFT 6 /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK [05:05] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_MASK 0x00000020 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_PACKET_TEST_ATTENTION_MASK_SHIFT 5 /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DATA_LINK_LAYER_ERROR_ATTENTION_MASK [04:04] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_MASK 0x00000010 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_DATA_LINK_LAYER_ERROR_ATTENTION_MASK_SHIFT 4 /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: NAK_RECEIVED_COUNTER_ATTENTION_MASK [03:03] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_MASK 0x00000008 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_NAK_RECEIVED_COUNTER_ATTENTION_MASK_SHIFT 3 /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: DLLP_ERROR_COUNTER_ATTENTION_MASK [02:02] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_MASK 0x00000004 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_DLLP_ERROR_COUNTER_ATTENTION_MASK_SHIFT 2 /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK [01:01] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_MASK 0x00000002 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_BAD_SEQUENCE_COUNTER_ATTENTION_MASK_SHIFT 1 /* PCIE_DLL :: DATA_LINK_ATTENTION_MASK :: TLP_ERROR_COUNTER_ATTENTION_MASK [00:00] */ #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_MASK 0x00000001 #define BCHP_PCIE_DLL_DATA_LINK_ATTENTION_MASK_TLP_ERROR_COUNTER_ATTENTION_MASK_SHIFT 0 /*************************************************************************** *NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG - NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register ***************************************************************************/ /* PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ #define BCHP_PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 #define BCHP_PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 /* PCIE_DLL :: NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: NEXT_TRANSMIT_SEQUENCE_NUMBER [11:00] */ #define BCHP_PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff #define BCHP_PCIE_DLL_NEXT_TRANSMIT_SEQUENCE_NUMBER_DEBUG_NEXT_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 /*************************************************************************** *ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG - ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register ***************************************************************************/ /* PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ #define BCHP_PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 #define BCHP_PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 /* PCIE_DLL :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: ACK_ED_TRANSMIT_SEQUENCE_NUMBER [11:00] */ #define BCHP_PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff #define BCHP_PCIE_DLL_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_ACK_ED_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 /*************************************************************************** *PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG - PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG Register ***************************************************************************/ /* PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ #define BCHP_PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 #define BCHP_PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 /* PCIE_DLL :: PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG :: PURGED_TRANSMIT_SEQUENCE_NUMBER [11:00] */ #define BCHP_PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_MASK 0x00000fff #define BCHP_PCIE_DLL_PURGED_TRANSMIT_SEQUENCE_NUMBER_DEBUG_PURGED_TRANSMIT_SEQUENCE_NUMBER_SHIFT 0 /*************************************************************************** *RECEIVE_SEQUENCE_NUMBER_DEBUG - RECEIVE_SEQUENCE_NUMBER_DEBUG Register ***************************************************************************/ /* PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG :: RESERVED_0 [31:12] */ #define BCHP_PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_MASK 0xfffff000 #define BCHP_PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RESERVED_0_SHIFT 12 /* PCIE_DLL :: RECEIVE_SEQUENCE_NUMBER_DEBUG :: RECEIVE_SEQUENCE_NUMBER [11:00] */ #define BCHP_PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_MASK 0x00000fff #define BCHP_PCIE_DLL_RECEIVE_SEQUENCE_NUMBER_DEBUG_RECEIVE_SEQUENCE_NUMBER_SHIFT 0 /*************************************************************************** *DATA_LINK_REPLAY - DATA_LINK_REPLAY Register ***************************************************************************/ /* PCIE_DLL :: DATA_LINK_REPLAY :: RESERVED_0 [31:23] */ #define BCHP_PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_MASK 0xff800000 #define BCHP_PCIE_DLL_DATA_LINK_REPLAY_RESERVED_0_SHIFT 23 /* PCIE_DLL :: DATA_LINK_REPLAY :: REPLAY_TIMEOUT_VALUE [22:10] */ #define BCHP_PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_MASK 0x007ffc00 #define BCHP_PCIE_DLL_DATA_LINK_REPLAY_REPLAY_TIMEOUT_VALUE_SHIFT 10 /* PCIE_DLL :: DATA_LINK_REPLAY :: REPLAY_BUFFER_SIZE [09:00] */ #define BCHP_PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_MASK 0x000003ff #define BCHP_PCIE_DLL_DATA_LINK_REPLAY_REPLAY_BUFFER_SIZE_SHIFT 0 /*************************************************************************** *DATA_LINK_ACK_TIMEOUT - DATA_LINK_ACK_TIMEOUT Register ***************************************************************************/ /* PCIE_DLL :: DATA_LINK_ACK_TIMEOUT :: RESERVED_0 [31:11] */ #define BCHP_PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_MASK 0xfffff800 #define BCHP_PCIE_DLL_DATA_LINK_ACK_TIMEOUT_RESERVED_0_SHIFT 11 /* PCIE_DLL :: DATA_LINK_ACK_TIMEOUT :: ACK_LATENCY_TIMEOUT_VALUE [10:00] */ #define BCHP_PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_MASK 0x000007ff #define BCHP_PCIE_DLL_DATA_LINK_ACK_TIMEOUT_ACK_LATENCY_TIMEOUT_VALUE_SHIFT 0 /*************************************************************************** *POWER_MANAGEMENT_THRESHOLD - POWER_MANAGEMENT_THRESHOLD Register ***************************************************************************/ /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: RESERVED_0 [31:24] */ #define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_MASK 0xff000000 #define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_RESERVED_0_SHIFT 24 /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L0_STAY_TIME [23:20] */ #define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_MASK 0x00f00000 #define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0_STAY_TIME_SHIFT 20 /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L1_STAY_TIME [19:16] */ #define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_MASK 0x000f0000 #define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_STAY_TIME_SHIFT 16 /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L1_THRESHOLD [15:08] */ #define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_MASK 0x0000ff00 #define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L1_THRESHOLD_SHIFT 8 /* PCIE_DLL :: POWER_MANAGEMENT_THRESHOLD :: L0S_THRESHOLD [07:00] */ #define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_MASK 0x000000ff #define BCHP_PCIE_DLL_POWER_MANAGEMENT_THRESHOLD_L0S_THRESHOLD_SHIFT 0 /*************************************************************************** *RETRY_BUFFER_WRITE_POINTER_DEBUG - RETRY_BUFFER_WRITE_POINTER_DEBUG Register ***************************************************************************/ /* PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG :: RESERVED_0 [31:11] */ #define BCHP_PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 #define BCHP_PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RESERVED_0_SHIFT 11 /* PCIE_DLL :: RETRY_BUFFER_WRITE_POINTER_DEBUG :: RETRY_BUFFER_WRITE_POINTER [10:00] */ #define BCHP_PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_MASK 0x000007ff #define BCHP_PCIE_DLL_RETRY_BUFFER_WRITE_POINTER_DEBUG_RETRY_BUFFER_WRITE_POINTER_SHIFT 0 /*************************************************************************** *RETRY_BUFFER_READ_POINTER_DEBUG - RETRY_BUFFER_READ_POINTER_DEBUG Register ***************************************************************************/ /* PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG :: RESERVED_0 [31:11] */ #define BCHP_PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 #define BCHP_PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RESERVED_0_SHIFT 11 /* PCIE_DLL :: RETRY_BUFFER_READ_POINTER_DEBUG :: RETRY_BUFFER_READ_POINTER [10:00] */ #define BCHP_PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_MASK 0x000007ff #define BCHP_PCIE_DLL_RETRY_BUFFER_READ_POINTER_DEBUG_RETRY_BUFFER_READ_POINTER_SHIFT 0 /*************************************************************************** *RETRY_BUFFER_PURGED_POINTER_DEBUG - RETRY_BUFFER_PURGED_POINTER_DEBUG Register ***************************************************************************/ /* PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG :: RESERVED_0 [31:11] */ #define BCHP_PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_MASK 0xfffff800 #define BCHP_PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RESERVED_0_SHIFT 11 /* PCIE_DLL :: RETRY_BUFFER_PURGED_POINTER_DEBUG :: RETRY_BUFFER_PURGED_POINTER [10:00] */ #define BCHP_PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_MASK 0x000007ff #define BCHP_PCIE_DLL_RETRY_BUFFER_PURGED_POINTER_DEBUG_RETRY_BUFFER_PURGED_POINTER_SHIFT 0 /*************************************************************************** *RETRY_BUFFER_READ_WRITE_DEBUG_PORT - RETRY_BUFFER_READ_WRITE_DEBUG_PORT Register ***************************************************************************/ /* PCIE_DLL :: RETRY_BUFFER_READ_WRITE_DEBUG_PORT :: RETRY_BUFFER_DATA [31:00] */ #define BCHP_PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_MASK 0xffffffff #define BCHP_PCIE_DLL_RETRY_BUFFER_READ_WRITE_DEBUG_PORT_RETRY_BUFFER_DATA_SHIFT 0 /*************************************************************************** *ERROR_COUNT_THRESHOLD - ERROR_COUNT_THRESHOLD Register ***************************************************************************/ /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: RESERVED_0 [31:15] */ #define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_MASK 0xffff8000 #define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_RESERVED_0_SHIFT 15 /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD [14:12] */ #define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_MASK 0x00007000 #define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_BAD_SEQUENCE_NUMBER_COUNT_THRESHOLD_SHIFT 12 /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: NAK_RECEIVED_COUNT_THRESHOLD [11:08] */ #define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_MASK 0x00000f00 #define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_NAK_RECEIVED_COUNT_THRESHOLD_SHIFT 8 /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: DLLP_ERROR_COUNT_THRESHOLD [07:04] */ #define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_MASK 0x000000f0 #define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_DLLP_ERROR_COUNT_THRESHOLD_SHIFT 4 /* PCIE_DLL :: ERROR_COUNT_THRESHOLD :: TLP_ERROR_COUNT_THRESHOLD [03:00] */ #define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_MASK 0x0000000f #define BCHP_PCIE_DLL_ERROR_COUNT_THRESHOLD_TLP_ERROR_COUNT_THRESHOLD_SHIFT 0 /*************************************************************************** *TL_ERROR_COUNTER - TL_ERROR_COUNTER Register ***************************************************************************/ /* PCIE_DLL :: TL_ERROR_COUNTER :: RESERVED_0 [31:24] */ #define BCHP_PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_MASK 0xff000000 #define BCHP_PCIE_DLL_TL_ERROR_COUNTER_RESERVED_0_SHIFT 24 /* PCIE_DLL :: TL_ERROR_COUNTER :: TLP_BAD_SEQUENCE_NUMBER_COUNTER [23:16] */ #define BCHP_PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_MASK 0x00ff0000 #define BCHP_PCIE_DLL_TL_ERROR_COUNTER_TLP_BAD_SEQUENCE_NUMBER_COUNTER_SHIFT 16 /* PCIE_DLL :: TL_ERROR_COUNTER :: TLP_ERROR_COUNTER [15:00] */ #define BCHP_PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_MASK 0x0000ffff #define BCHP_PCIE_DLL_TL_ERROR_COUNTER_TLP_ERROR_COUNTER_SHIFT 0 /*************************************************************************** *DLLP_ERROR_COUNTER - DLLP_ERROR_COUNTER Register ***************************************************************************/ /* PCIE_DLL :: DLLP_ERROR_COUNTER :: RESERVED_0 [31:16] */ #define BCHP_PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_MASK 0xffff0000 #define BCHP_PCIE_DLL_DLLP_ERROR_COUNTER_RESERVED_0_SHIFT 16 /* PCIE_DLL :: DLLP_ERROR_COUNTER :: DLLP_ERROR_COUNTER [15:00] */ #define BCHP_PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_MASK 0x0000ffff #define BCHP_PCIE_DLL_DLLP_ERROR_COUNTER_DLLP_ERROR_COUNTER_SHIFT 0 /*************************************************************************** *NAK_RECEIVED_COUNTER - NAK_RECEIVED_COUNTER Register ***************************************************************************/ /* PCIE_DLL :: NAK_RECEIVED_COUNTER :: RESERVED_0 [31:16] */ #define BCHP_PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_MASK 0xffff0000 #define BCHP_PCIE_DLL_NAK_RECEIVED_COUNTER_RESERVED_0_SHIFT 16 /* PCIE_DLL :: NAK_RECEIVED_COUNTER :: NAK_RECEIVED_COUNTER [15:00] */ #define BCHP_PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_MASK 0x0000ffff #define BCHP_PCIE_DLL_NAK_RECEIVED_COUNTER_NAK_RECEIVED_COUNTER_SHIFT 0 /*************************************************************************** *DATA_LINK_TEST - DATA_LINK_TEST Register ***************************************************************************/ /* PCIE_DLL :: DATA_LINK_TEST :: RESERVED_0 [31:16] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_RESERVED_0_MASK 0xffff0000 #define BCHP_PCIE_DLL_DATA_LINK_TEST_RESERVED_0_SHIFT 16 /* PCIE_DLL :: DATA_LINK_TEST :: STORE_RECEIVE_TLPS [15:15] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_MASK 0x00008000 #define BCHP_PCIE_DLL_DATA_LINK_TEST_STORE_RECEIVE_TLPS_SHIFT 15 /* PCIE_DLL :: DATA_LINK_TEST :: DISABLE_TLPS [14:14] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_MASK 0x00004000 #define BCHP_PCIE_DLL_DATA_LINK_TEST_DISABLE_TLPS_SHIFT 14 /* PCIE_DLL :: DATA_LINK_TEST :: DISABLE_DLLPS [13:13] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_MASK 0x00002000 #define BCHP_PCIE_DLL_DATA_LINK_TEST_DISABLE_DLLPS_SHIFT 13 /* PCIE_DLL :: DATA_LINK_TEST :: FORCE_PHY_LINK_UP [12:12] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_MASK 0x00001000 #define BCHP_PCIE_DLL_DATA_LINK_TEST_FORCE_PHY_LINK_UP_SHIFT 12 /* PCIE_DLL :: DATA_LINK_TEST :: BYPASS_FLOW_CONTROL [11:11] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_MASK 0x00000800 #define BCHP_PCIE_DLL_DATA_LINK_TEST_BYPASS_FLOW_CONTROL_SHIFT 11 /* PCIE_DLL :: DATA_LINK_TEST :: ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE [10:10] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_MASK 0x00000400 #define BCHP_PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_CORE_CLOCK_MARGIN_TEST_MODE_SHIFT 10 /* PCIE_DLL :: DATA_LINK_TEST :: ENABLE_RAM_OVERSTRESS_TEST_MODE [09:09] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_MASK 0x00000200 #define BCHP_PCIE_DLL_DATA_LINK_TEST_ENABLE_RAM_OVERSTRESS_TEST_MODE_SHIFT 9 /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_SLOW_CLOCK [08:08] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_MASK 0x00000100 #define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_SLOW_CLOCK_SHIFT 8 /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_COMPLETION_TIMER [07:07] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_MASK 0x00000080 #define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_COMPLETION_TIMER_SHIFT 7 /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_REPLAY_TIMER [06:06] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_MASK 0x00000040 #define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_REPLAY_TIMER_SHIFT 6 /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_ACK_LATENCY_TIMER [05:05] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_MASK 0x00000020 #define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_ACK_LATENCY_TIMER_SHIFT 5 /* PCIE_DLL :: DATA_LINK_TEST :: SPEED_UP_PME_SERVICE_TIMER [04:04] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_MASK 0x00000010 #define BCHP_PCIE_DLL_DATA_LINK_TEST_SPEED_UP_PME_SERVICE_TIMER_SHIFT 4 /* PCIE_DLL :: DATA_LINK_TEST :: FORCE_PURGE [03:03] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_MASK 0x00000008 #define BCHP_PCIE_DLL_DATA_LINK_TEST_FORCE_PURGE_SHIFT 3 /* PCIE_DLL :: DATA_LINK_TEST :: FORCE_RETRY [02:02] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_MASK 0x00000004 #define BCHP_PCIE_DLL_DATA_LINK_TEST_FORCE_RETRY_SHIFT 2 /* PCIE_DLL :: DATA_LINK_TEST :: INVERT_CRC [01:01] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_MASK 0x00000002 #define BCHP_PCIE_DLL_DATA_LINK_TEST_INVERT_CRC_SHIFT 1 /* PCIE_DLL :: DATA_LINK_TEST :: SEND_BAD_CRC_BIT [00:00] */ #define BCHP_PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_MASK 0x00000001 #define BCHP_PCIE_DLL_DATA_LINK_TEST_SEND_BAD_CRC_BIT_SHIFT 0 /*************************************************************************** *PACKET_BIST - PACKET_BIST Register ***************************************************************************/ /* PCIE_DLL :: PACKET_BIST :: RESERVED_0 [31:24] */ #define BCHP_PCIE_DLL_PACKET_BIST_RESERVED_0_MASK 0xff000000 #define BCHP_PCIE_DLL_PACKET_BIST_RESERVED_0_SHIFT 24 /* PCIE_DLL :: PACKET_BIST :: PACKET_CHECKER_LOCKED [23:23] */ #define BCHP_PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_MASK 0x00800000 #define BCHP_PCIE_DLL_PACKET_BIST_PACKET_CHECKER_LOCKED_SHIFT 23 /* PCIE_DLL :: PACKET_BIST :: RECEIVE_MISMATCH [22:22] */ #define BCHP_PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_MASK 0x00400000 #define BCHP_PCIE_DLL_PACKET_BIST_RECEIVE_MISMATCH_SHIFT 22 /* PCIE_DLL :: PACKET_BIST :: ENABLE_RANDOM_TLP_LENGTH [21:21] */ #define BCHP_PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_MASK 0x00200000 #define BCHP_PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_TLP_LENGTH_SHIFT 21 /* PCIE_DLL :: PACKET_BIST :: TLP_LENGTH [20:10] */ #define BCHP_PCIE_DLL_PACKET_BIST_TLP_LENGTH_MASK 0x001ffc00 #define BCHP_PCIE_DLL_PACKET_BIST_TLP_LENGTH_SHIFT 10 /* PCIE_DLL :: PACKET_BIST :: ENABLE_RANDOM_IPG_LENGTH [09:09] */ #define BCHP_PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_MASK 0x00000200 #define BCHP_PCIE_DLL_PACKET_BIST_ENABLE_RANDOM_IPG_LENGTH_SHIFT 9 /* PCIE_DLL :: PACKET_BIST :: IPG_LENGTH [08:02] */ #define BCHP_PCIE_DLL_PACKET_BIST_IPG_LENGTH_MASK 0x000001fc #define BCHP_PCIE_DLL_PACKET_BIST_IPG_LENGTH_SHIFT 2 /* PCIE_DLL :: PACKET_BIST :: TRANSMIT_START [01:01] */ #define BCHP_PCIE_DLL_PACKET_BIST_TRANSMIT_START_MASK 0x00000002 #define BCHP_PCIE_DLL_PACKET_BIST_TRANSMIT_START_SHIFT 1 /* PCIE_DLL :: PACKET_BIST :: ENABLE_PACKET_GENERATOR_TEST_MODE [00:00] */ #define BCHP_PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_MASK 0x00000001 #define BCHP_PCIE_DLL_PACKET_BIST_ENABLE_PACKET_GENERATOR_TEST_MODE_SHIFT 0 /*************************************************************************** *LINK_PCIE_1_1_CONTROL - LINK_PCIE_1_1_CONTROL Register ***************************************************************************/ /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: RTBF_CT_2_0 [31:29] */ #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_MASK 0xe0000000 #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_CT_2_0_SHIFT 29 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: RTBF_SAM_1_0 [28:27] */ #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_MASK 0x18000000 #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_RTBF_SAM_1_0_SHIFT 27 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: UNUSED_0 [26:10] */ #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_MASK 0x07fffc00 #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_UNUSED_0_SHIFT 10 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: SELOCALXTAL [09:09] */ #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_MASK 0x00000200 #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_SELOCALXTAL_SHIFT 9 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L2_PLL_POWERDOWN_DISABLE [08:08] */ #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_MASK 0x00000100 #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_PLL_POWERDOWN_DISABLE_SHIFT 8 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_PLL_POWERDOWN_DISABLE [07:07] */ #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_MASK 0x00000080 #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_POWERDOWN_DISABLE_SHIFT 7 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L2_D3PM_CLKREQ_DISABLE [06:06] */ #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_MASK 0x00000040 #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L2_D3PM_CLKREQ_DISABLE_SHIFT 6 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_D3PM_CLKREQ_DISABLE [05:05] */ #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_MASK 0x00000020 #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_D3PM_CLKREQ_DISABLE_SHIFT 5 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_ASPM_CLKREQ_DISABLE [04:04] */ #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_MASK 0x00000010 #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_ASPM_CLKREQ_DISABLE_SHIFT 4 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: L1_PLL_PD_W_O_CLKREQ [03:03] */ #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_MASK 0x00000008 #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_L1_PLL_PD_W_O_CLKREQ_SHIFT 3 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DASPM10USTIMER [02:02] */ #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_MASK 0x00000004 #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_DASPM10USTIMER_SHIFT 2 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DFFU_EL1 [01:01] */ #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_MASK 0x00000002 #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFFU_EL1_SHIFT 1 /* PCIE_DLL :: LINK_PCIE_1_1_CONTROL :: DFLOWCTLUPDATE1_1 [00:00] */ #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_MASK 0x00000001 #define BCHP_PCIE_DLL_LINK_PCIE_1_1_CONTROL_DFLOWCTLUPDATE1_1_SHIFT 0 #endif /* #ifndef BCHP_PCIE_DLL_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016300000000000011565 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_trace_regs.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_ar0000644000175000017500000015516111610313111031023 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_arb_trace_regs.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:15p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:42 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_trace_regs.h $ * * Hydra_Software_Devel/1 7/17/09 8:15p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_ARB_TRACE_REGS_H__ #define BCHP_PRI_ARB_TRACE_REGS_H__ /*************************************************************************** *PRI_ARB_TRACE_REGS - PRIMARY_ARB tracelog registers ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_VERSION 0x0040c600 /* Tracelog Version */ #define BCHP_PRI_ARB_TRACE_REGS_MBIST_TM 0x0040c604 /* MBIST Test Mode */ #define BCHP_PRI_ARB_TRACE_REGS_BUFF_ADDR 0x0040c608 /* Beginning of buffer DRAM address in the TraceLog */ #define BCHP_PRI_ARB_TRACE_REGS_BUFF_SIZE 0x0040c60c /* Size of the buffer in DRAM */ #define BCHP_PRI_ARB_TRACE_REGS_BUFF_WR_PTR 0x0040c610 /* Initial location of the write pointer in DRAM */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MODE 0x0040c614 /* Trigger configuration */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_N_EVENTS 0x0040c618 /* N transactions */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD 0x0040c61c /* Trigger command register */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_LOWER 0x0040c620 /* Lower 32 bits of Trigger Time Interval */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_UPPER 0x0040c624 /* Upper 16 bits of Trigger Time Interval */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS 0x0040c628 /* Transaction Status Register */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_UPPER 0x0040c62c /* Upper 16 bits of elapsed time */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_LOWER 0x0040c630 /* Lower 32 bits of elapsed time */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_WR_PTR 0x0040c634 /* Buffer Write Pointer Position at the Time of Trigger */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_COUNT_BEFORE_TRIGGER 0x0040c638 /* Trigger Count Before Trigger */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_COUNT_AFTER_TRIGGER 0x0040c63c /* Trigger Count After Trigger */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_EVENT_COUNTER 0x0040c640 /* Trigger Event Counter */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_NUMBER 0x0040c644 /* Number of transactions captured */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_UPPER 0x0040c648 /* Upper 16 bits of timestamp at the time of Trigger */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_LOWER 0x0040c64c /* Lower 32 bits of timestamp at the time of Trigger */ /*************************************************************************** *VERSION - Tracelog Version ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: VERSION :: MAJOR_REVISION_NUMBER [31:16] */ #define BCHP_PRI_ARB_TRACE_REGS_VERSION_MAJOR_REVISION_NUMBER_MASK 0xffff0000 #define BCHP_PRI_ARB_TRACE_REGS_VERSION_MAJOR_REVISION_NUMBER_SHIFT 16 /* PRI_ARB_TRACE_REGS :: VERSION :: MINOR_REVISION_NUMBER [15:08] */ #define BCHP_PRI_ARB_TRACE_REGS_VERSION_MINOR_REVISION_NUMBER_MASK 0x0000ff00 #define BCHP_PRI_ARB_TRACE_REGS_VERSION_MINOR_REVISION_NUMBER_SHIFT 8 /* PRI_ARB_TRACE_REGS :: VERSION :: METAL_REVISION_ID [07:00] */ #define BCHP_PRI_ARB_TRACE_REGS_VERSION_METAL_REVISION_ID_MASK 0x000000ff #define BCHP_PRI_ARB_TRACE_REGS_VERSION_METAL_REVISION_ID_SHIFT 0 /*************************************************************************** *MBIST_TM - MBIST Test Mode ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: MBIST_TM :: reserved0 [31:02] */ #define BCHP_PRI_ARB_TRACE_REGS_MBIST_TM_reserved0_MASK 0xfffffffc #define BCHP_PRI_ARB_TRACE_REGS_MBIST_TM_reserved0_SHIFT 2 /* PRI_ARB_TRACE_REGS :: MBIST_TM :: MBIST_TESTMODE [01:00] */ #define BCHP_PRI_ARB_TRACE_REGS_MBIST_TM_MBIST_TESTMODE_MASK 0x00000003 #define BCHP_PRI_ARB_TRACE_REGS_MBIST_TM_MBIST_TESTMODE_SHIFT 0 /*************************************************************************** *BUFF_ADDR - Beginning of buffer DRAM address in the TraceLog ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: BUFF_ADDR :: ADDR [31:08] */ #define BCHP_PRI_ARB_TRACE_REGS_BUFF_ADDR_ADDR_MASK 0xffffff00 #define BCHP_PRI_ARB_TRACE_REGS_BUFF_ADDR_ADDR_SHIFT 8 /* PRI_ARB_TRACE_REGS :: BUFF_ADDR :: reserved0 [07:00] */ #define BCHP_PRI_ARB_TRACE_REGS_BUFF_ADDR_reserved0_MASK 0x000000ff #define BCHP_PRI_ARB_TRACE_REGS_BUFF_ADDR_reserved0_SHIFT 0 /*************************************************************************** *BUFF_SIZE - Size of the buffer in DRAM ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: BUFF_SIZE :: SIZE [31:08] */ #define BCHP_PRI_ARB_TRACE_REGS_BUFF_SIZE_SIZE_MASK 0xffffff00 #define BCHP_PRI_ARB_TRACE_REGS_BUFF_SIZE_SIZE_SHIFT 8 /* PRI_ARB_TRACE_REGS :: BUFF_SIZE :: reserved0 [07:00] */ #define BCHP_PRI_ARB_TRACE_REGS_BUFF_SIZE_reserved0_MASK 0x000000ff #define BCHP_PRI_ARB_TRACE_REGS_BUFF_SIZE_reserved0_SHIFT 0 /*************************************************************************** *BUFF_WR_PTR - Initial location of the write pointer in DRAM ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: BUFF_WR_PTR :: ADDR [31:08] */ #define BCHP_PRI_ARB_TRACE_REGS_BUFF_WR_PTR_ADDR_MASK 0xffffff00 #define BCHP_PRI_ARB_TRACE_REGS_BUFF_WR_PTR_ADDR_SHIFT 8 /* PRI_ARB_TRACE_REGS :: BUFF_WR_PTR :: reserved0 [07:00] */ #define BCHP_PRI_ARB_TRACE_REGS_BUFF_WR_PTR_reserved0_MASK 0x000000ff #define BCHP_PRI_ARB_TRACE_REGS_BUFF_WR_PTR_reserved0_SHIFT 0 /*************************************************************************** *TRIG_MODE - Trigger configuration ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_MODE :: reserved0 [31:06] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MODE_reserved0_MASK 0xffffffc0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MODE_reserved0_SHIFT 6 /* PRI_ARB_TRACE_REGS :: TRIG_MODE :: EVENT_MODE [05:03] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MODE_EVENT_MODE_MASK 0x00000038 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MODE_EVENT_MODE_SHIFT 3 /* PRI_ARB_TRACE_REGS :: TRIG_MODE :: CAPTURE_MODE [02:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MODE_CAPTURE_MODE_MASK 0x00000007 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MODE_CAPTURE_MODE_SHIFT 0 /*************************************************************************** *TRIG_N_EVENTS - N transactions ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_N_EVENTS :: N_EVENTS [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_N_EVENTS_N_EVENTS_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_N_EVENTS_N_EVENTS_SHIFT 0 /*************************************************************************** *TRIG_CMD - Trigger command register ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_CMD :: reserved0 [31:05] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_reserved0_MASK 0xffffffe0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_reserved0_SHIFT 5 /* PRI_ARB_TRACE_REGS :: TRIG_CMD :: RESET [04:04] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_RESET_MASK 0x00000010 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_RESET_SHIFT 4 /* PRI_ARB_TRACE_REGS :: TRIG_CMD :: STOP [03:03] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_STOP_MASK 0x00000008 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_STOP_SHIFT 3 /* PRI_ARB_TRACE_REGS :: TRIG_CMD :: FLUSH [02:02] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_FLUSH_MASK 0x00000004 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_FLUSH_SHIFT 2 /* PRI_ARB_TRACE_REGS :: TRIG_CMD :: MANUAL_TRIGGER [01:01] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_MANUAL_TRIGGER_MASK 0x00000002 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_MANUAL_TRIGGER_SHIFT 1 /* PRI_ARB_TRACE_REGS :: TRIG_CMD :: START [00:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_START_MASK 0x00000001 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_CMD_START_SHIFT 0 /*************************************************************************** *TRIG_TIME_LOWER - Lower 32 bits of Trigger Time Interval ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_TIME_LOWER :: TRANSACTION_TIME_LOWER [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_LOWER_TRANSACTION_TIME_LOWER_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_LOWER_TRANSACTION_TIME_LOWER_SHIFT 0 /*************************************************************************** *TRIG_TIME_UPPER - Upper 16 bits of Trigger Time Interval ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_TIME_UPPER :: reserved0 [31:16] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_UPPER_reserved0_MASK 0xffff0000 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_UPPER_reserved0_SHIFT 16 /* PRI_ARB_TRACE_REGS :: TRIG_TIME_UPPER :: TRANSACTION_TIME_UPPER [15:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_UPPER_TRANSACTION_TIME_UPPER_MASK 0x0000ffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TIME_UPPER_TRANSACTION_TIME_UPPER_SHIFT 0 /*************************************************************************** *TRANSACTION_STATUS - Transaction Status Register ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRANSACTION_STATUS :: reserved0 [31:13] */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_reserved0_MASK 0xffffe000 #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_reserved0_SHIFT 13 /* PRI_ARB_TRACE_REGS :: TRANSACTION_STATUS :: RESET_ACTIVE [12:12] */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_RESET_ACTIVE_MASK 0x00001000 #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_RESET_ACTIVE_SHIFT 12 /* PRI_ARB_TRACE_REGS :: TRANSACTION_STATUS :: FIFO_EMPTY [11:11] */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_FIFO_EMPTY_MASK 0x00000800 #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_FIFO_EMPTY_SHIFT 11 /* PRI_ARB_TRACE_REGS :: TRANSACTION_STATUS :: TRIGGER_EVENT [10:10] */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_TRIGGER_EVENT_MASK 0x00000400 #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_TRIGGER_EVENT_SHIFT 10 /* PRI_ARB_TRACE_REGS :: TRANSACTION_STATUS :: LOST [09:09] */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_LOST_MASK 0x00000200 #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_LOST_SHIFT 9 /* PRI_ARB_TRACE_REGS :: TRANSACTION_STATUS :: ACTIVE [08:08] */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_ACTIVE_MASK 0x00000100 #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_ACTIVE_SHIFT 8 /* PRI_ARB_TRACE_REGS :: TRANSACTION_STATUS :: CONTINUITY_COUNT [07:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_CONTINUITY_COUNT_MASK 0x000000ff #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_STATUS_CONTINUITY_COUNT_SHIFT 0 /*************************************************************************** *TRANSACTION_TIME_UPPER - Upper 16 bits of elapsed time ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRANSACTION_TIME_UPPER :: reserved0 [31:16] */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_UPPER_reserved0_MASK 0xffff0000 #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_UPPER_reserved0_SHIFT 16 /* PRI_ARB_TRACE_REGS :: TRANSACTION_TIME_UPPER :: TRANSACTION_TIME_UPPER [15:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_UPPER_TRANSACTION_TIME_UPPER_MASK 0x0000ffff #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_UPPER_TRANSACTION_TIME_UPPER_SHIFT 0 /*************************************************************************** *TRANSACTION_TIME_LOWER - Lower 32 bits of elapsed time ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRANSACTION_TIME_LOWER :: TRANSACTION_TIME_LOWER [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_LOWER_TRANSACTION_TIME_LOWER_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_TIME_LOWER_TRANSACTION_TIME_LOWER_SHIFT 0 /*************************************************************************** *TRIG_WR_PTR - Buffer Write Pointer Position at the Time of Trigger ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_WR_PTR :: TRIGGER_WRITE_POINTER_ADDRESS [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_WR_PTR_TRIGGER_WRITE_POINTER_ADDRESS_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_WR_PTR_TRIGGER_WRITE_POINTER_ADDRESS_SHIFT 0 /*************************************************************************** *TRIG_COUNT_BEFORE_TRIGGER - Trigger Count Before Trigger ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_COUNT_BEFORE_TRIGGER :: EVENT_COUNT_BEFORE_TRIGGER [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_COUNT_BEFORE_TRIGGER_EVENT_COUNT_BEFORE_TRIGGER_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_COUNT_BEFORE_TRIGGER_EVENT_COUNT_BEFORE_TRIGGER_SHIFT 0 /*************************************************************************** *TRIG_COUNT_AFTER_TRIGGER - Trigger Count After Trigger ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_COUNT_AFTER_TRIGGER :: EVENT_COUNT_AFTER_TRIGGER [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_COUNT_AFTER_TRIGGER_EVENT_COUNT_AFTER_TRIGGER_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_COUNT_AFTER_TRIGGER_EVENT_COUNT_AFTER_TRIGGER_SHIFT 0 /*************************************************************************** *TRIG_EVENT_COUNTER - Trigger Event Counter ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_EVENT_COUNTER :: TRIGGER_EVENT_MATCH_COUNT [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_EVENT_COUNTER_TRIGGER_EVENT_MATCH_COUNT_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_EVENT_COUNTER_TRIGGER_EVENT_MATCH_COUNT_SHIFT 0 /*************************************************************************** *TRANSACTION_NUMBER - Number of transactions captured ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRANSACTION_NUMBER :: TRANS_NUMBER [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_NUMBER_TRANS_NUMBER_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRANSACTION_NUMBER_TRANS_NUMBER_SHIFT 0 /*************************************************************************** *TRIG_TRANS_TIME_UPPER - Upper 16 bits of timestamp at the time of Trigger ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_TRANS_TIME_UPPER :: reserved0 [31:16] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_UPPER_reserved0_MASK 0xffff0000 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_UPPER_reserved0_SHIFT 16 /* PRI_ARB_TRACE_REGS :: TRIG_TRANS_TIME_UPPER :: TRANSACTION_TIME_UPPER [15:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_UPPER_TRANSACTION_TIME_UPPER_MASK 0x0000ffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_UPPER_TRANSACTION_TIME_UPPER_SHIFT 0 /*************************************************************************** *TRIG_TRANS_TIME_LOWER - Lower 32 bits of timestamp at the time of Trigger ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_TRANS_TIME_LOWER :: TRANSACTION_TIME_LOWER [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_LOWER_TRANSACTION_TIME_LOWER_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_TRANS_TIME_LOWER_TRANSACTION_TIME_LOWER_SHIFT 0 /*************************************************************************** *DATA_MEM_FILT_MODE%i - Data Memory Filter Window Mode ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_ARRAY_BASE 0x0040c650 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *DATA_MEM_FILT_MODE%i - Data Memory Filter Window Mode ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: reserved0 [31:12] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_reserved0_MASK 0xfffff000 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_reserved0_SHIFT 12 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: FILTER_MEMORY_EN [11:11] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_FILTER_MEMORY_EN_MASK 0x00000800 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_FILTER_MEMORY_EN_SHIFT 11 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_MCACHE_MODE [10:10] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_MCACHE_MODE_MASK 0x00000400 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_MCACHE_MODE_SHIFT 10 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_READ_MODE [09:09] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_READ_MODE_MASK 0x00000200 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_READ_MODE_SHIFT 9 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_WRITE_MODE [08:08] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_WRITE_MODE_MASK 0x00000100 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_WRITE_MODE_SHIFT 8 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_PIXEL_MODE [07:07] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_PIXEL_MODE_MASK 0x00000080 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_PIXEL_MODE_SHIFT 7 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_LINEAR_MODE [06:06] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_LINEAR_MODE_MASK 0x00000040 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_LINEAR_MODE_SHIFT 6 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_DISPLAY_MODE [05:05] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_DISPLAY_MODE_MASK 0x00000020 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_DISPLAY_MODE_SHIFT 5 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_CACHE_MODE [04:04] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_CACHE_MODE_MASK 0x00000010 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_CACHE_MODE_SHIFT 4 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_FILTER_PIXEL_MODE [03:03] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_FILTER_PIXEL_MODE_MASK 0x00000008 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_FILTER_PIXEL_MODE_SHIFT 3 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_CLIENT_MASK_MODE [02:02] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_CLIENT_MASK_MODE_MASK 0x00000004 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_CLIENT_MASK_MODE_SHIFT 2 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_IN_OUT [01:01] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_IN_OUT_MASK 0x00000002 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_IN_OUT_SHIFT 1 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_MODEi :: MEMORY_ADDRESS_EN [00:00] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_ADDRESS_EN_MASK 0x00000001 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_MODEi_MEMORY_ADDRESS_EN_SHIFT 0 /*************************************************************************** *DATA_MEM_FILT_PIX_X1_Y1_COORD%i - X1,Y1 Coordinate ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_BASE 0x0040c660 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *DATA_MEM_FILT_PIX_X1_Y1_COORD%i - X1,Y1 Coordinate ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X1_Y1_COORDi :: reserved0 [31:27] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_reserved0_MASK 0xf8000000 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_reserved0_SHIFT 27 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X1_Y1_COORDi :: Y1_COORD [26:16] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_Y1_COORD_MASK 0x07ff0000 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_Y1_COORD_SHIFT 16 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X1_Y1_COORDi :: reserved1 [15:11] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_reserved1_MASK 0x0000f800 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_reserved1_SHIFT 11 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X1_Y1_COORDi :: X1_COORD [10:00] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_X1_COORD_MASK 0x000007ff #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X1_Y1_COORDi_X1_COORD_SHIFT 0 /*************************************************************************** *DATA_MEM_FILT_PIX_X2_Y2_COORD%i - X2,Y2 Coordinate ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_BASE 0x0040c670 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *DATA_MEM_FILT_PIX_X2_Y2_COORD%i - X2,Y2 Coordinate ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X2_Y2_COORDi :: reserved0 [31:27] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_reserved0_MASK 0xf8000000 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_reserved0_SHIFT 27 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X2_Y2_COORDi :: Y2_COORD [26:16] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_Y2_COORD_MASK 0x07ff0000 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_Y2_COORD_SHIFT 16 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X2_Y2_COORDi :: reserved1 [15:11] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_reserved1_MASK 0x0000f800 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_reserved1_SHIFT 11 /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_PIX_X2_Y2_COORDi :: X2_COORD [10:00] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_X2_COORD_MASK 0x000007ff #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_PIX_X2_Y2_COORDi_X2_COORD_SHIFT 0 /*************************************************************************** *DATA_MEM_FILT_CLIENT_MASK_64_95_%i - Data Memory Filter Window Client Mask for Clients 64-95 ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_BASE 0x0040c680 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *DATA_MEM_FILT_CLIENT_MASK_64_95_%i - Data Memory Filter Window Client Mask for Clients 64-95 ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_CLIENT_MASK_64_95_i :: MEMORY_CLIENT_MASK [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_64_95_i_MEMORY_CLIENT_MASK_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_64_95_i_MEMORY_CLIENT_MASK_SHIFT 0 /*************************************************************************** *DATA_MEM_FILT_CLIENT_MASK_32_63_%i - Data Memory Filter Window Client Mask for Clients 32-63 ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_BASE 0x0040c690 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *DATA_MEM_FILT_CLIENT_MASK_32_63_%i - Data Memory Filter Window Client Mask for Clients 32-63 ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_CLIENT_MASK_32_63_i :: MEMORY_CLIENT_MASK [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_32_63_i_MEMORY_CLIENT_MASK_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_32_63_i_MEMORY_CLIENT_MASK_SHIFT 0 /*************************************************************************** *DATA_MEM_FILT_CLIENT_MASK_31_0_%i - Data Memory Filter Window Client Mask for Clients 0-31 ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_BASE 0x0040c6a0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *DATA_MEM_FILT_CLIENT_MASK_31_0_%i - Data Memory Filter Window Client Mask for Clients 0-31 ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_CLIENT_MASK_31_0_i :: MEMORY_CLIENT_MASK [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_31_0_i_MEMORY_CLIENT_MASK_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_CLIENT_MASK_31_0_i_MEMORY_CLIENT_MASK_SHIFT 0 /*************************************************************************** *DATA_MEM_FILT_ADDR_UPPER%i - Data Memory Filter Window Client Mask Upper Bound Address ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_UPPERi_ARRAY_BASE 0x0040c6b0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_UPPERi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_UPPERi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_UPPERi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *DATA_MEM_FILT_ADDR_UPPER%i - Data Memory Filter Window Client Mask Upper Bound Address ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_ADDR_UPPERi :: UPPER_MEMORY_ADDR [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_UPPERi_UPPER_MEMORY_ADDR_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_UPPERi_UPPER_MEMORY_ADDR_SHIFT 0 /*************************************************************************** *DATA_MEM_FILT_ADDR_LOWER%i - Data Memory Filter Window Client Mask Lower Bound Address ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_LOWERi_ARRAY_BASE 0x0040c6c0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_LOWERi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_LOWERi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_LOWERi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *DATA_MEM_FILT_ADDR_LOWER%i - Data Memory Filter Window Client Mask Lower Bound Address ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: DATA_MEM_FILT_ADDR_LOWERi :: LOWER_MEMORY_ADDR [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_LOWERi_LOWER_MEMORY_ADDR_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_DATA_MEM_FILT_ADDR_LOWERi_LOWER_MEMORY_ADDR_SHIFT 0 /*************************************************************************** *DATA_IO_FILT_MODE%i - Data I/O Filter Mode ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_ARRAY_BASE 0x0040c6d0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *DATA_IO_FILT_MODE%i - Data I/O Filter Mode ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_MODEi :: reserved0 [31:06] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_reserved0_MASK 0xffffffc0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_reserved0_SHIFT 6 /* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_MODEi :: FILTER_IO_EN [05:05] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_FILTER_IO_EN_MASK 0x00000020 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_FILTER_IO_EN_SHIFT 5 /* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_MODEi :: GISB_READ_MODE [04:04] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_GISB_READ_MODE_MASK 0x00000010 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_GISB_READ_MODE_SHIFT 4 /* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_MODEi :: GISB_WRITE_MODE [03:03] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_GISB_WRITE_MODE_MASK 0x00000008 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_GISB_WRITE_MODE_SHIFT 3 /* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_MODEi :: DATA_MODE [02:02] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_DATA_MODE_MASK 0x00000004 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_DATA_MODE_SHIFT 2 /* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_MODEi :: IO_IN_OUT [01:01] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_IO_IN_OUT_MASK 0x00000002 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_IO_IN_OUT_SHIFT 1 /* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_MODEi :: IO_ADDRESS_EN [00:00] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_IO_ADDRESS_EN_MASK 0x00000001 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_MODEi_IO_ADDRESS_EN_SHIFT 0 /*************************************************************************** *DATA_IO_FILT_ADDR_UPPER%i - Data I/O Filter Window Client Mask Upper Bound Address ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_UPPERi_ARRAY_BASE 0x0040c6e0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_UPPERi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_UPPERi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_UPPERi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *DATA_IO_FILT_ADDR_UPPER%i - Data I/O Filter Window Client Mask Upper Bound Address ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_ADDR_UPPERi :: IO_ADDR_UPPER [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_UPPERi_IO_ADDR_UPPER_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_UPPERi_IO_ADDR_UPPER_SHIFT 0 /*************************************************************************** *DATA_IO_FILT_ADDR_LOWER%i - Data I/O Filter Window Client Mask Lower Bound Address ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_LOWERi_ARRAY_BASE 0x0040c6f0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_LOWERi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_LOWERi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_LOWERi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *DATA_IO_FILT_ADDR_LOWER%i - Data I/O Filter Window Client Mask Lower Bound Address ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_ADDR_LOWERi :: IO_ADDR_LOWER [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_LOWERi_IO_ADDR_LOWER_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_ADDR_LOWERi_IO_ADDR_LOWER_SHIFT 0 /*************************************************************************** *DATA_IO_FILT_DATA%i - Data I/O Filter Window Data ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATAi_ARRAY_BASE 0x0040c700 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATAi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATAi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATAi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *DATA_IO_FILT_DATA%i - Data I/O Filter Window Data ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_DATAi :: DATA [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATAi_DATA_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATAi_DATA_SHIFT 0 /*************************************************************************** *DATA_IO_FILT_DATA_MASK%i - Data I/O Filter Window Data Mask ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATA_MASKi_ARRAY_BASE 0x0040c710 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATA_MASKi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATA_MASKi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATA_MASKi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *DATA_IO_FILT_DATA_MASK%i - Data I/O Filter Window Data Mask ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: DATA_IO_FILT_DATA_MASKi :: MASK [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATA_MASKi_MASK_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_DATA_IO_FILT_DATA_MASKi_MASK_SHIFT 0 /*************************************************************************** *TRIG_MEM_FILT_MODE%i - Trigger Memory Filter Window Mode ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_ARRAY_BASE 0x0040c720 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TRIG_MEM_FILT_MODE%i - Trigger Memory Filter Window Mode ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: reserved0 [31:12] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_reserved0_MASK 0xfffff000 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_reserved0_SHIFT 12 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: FILTER_MEMORY_EN [11:11] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_FILTER_MEMORY_EN_MASK 0x00000800 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_FILTER_MEMORY_EN_SHIFT 11 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_MCACHE_MODE [10:10] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_MCACHE_MODE_MASK 0x00000400 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_MCACHE_MODE_SHIFT 10 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_READ_MODE [09:09] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_READ_MODE_MASK 0x00000200 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_READ_MODE_SHIFT 9 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_WRITE_MODE [08:08] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_WRITE_MODE_MASK 0x00000100 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_WRITE_MODE_SHIFT 8 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_PIXEL_MODE [07:07] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_PIXEL_MODE_MASK 0x00000080 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_PIXEL_MODE_SHIFT 7 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_LINEAR_MODE [06:06] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_LINEAR_MODE_MASK 0x00000040 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_LINEAR_MODE_SHIFT 6 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_DISPLAY_MODE [05:05] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_DISPLAY_MODE_MASK 0x00000020 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_DISPLAY_MODE_SHIFT 5 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_CACHE_MODE [04:04] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_CACHE_MODE_MASK 0x00000010 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_CACHE_MODE_SHIFT 4 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_FILTER_PIXEL_MODE [03:03] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_FILTER_PIXEL_MODE_MASK 0x00000008 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_FILTER_PIXEL_MODE_SHIFT 3 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_CLIENT_MASK_MODE [02:02] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_CLIENT_MASK_MODE_MASK 0x00000004 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_CLIENT_MASK_MODE_SHIFT 2 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_IN_OUT [01:01] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_IN_OUT_MASK 0x00000002 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_IN_OUT_SHIFT 1 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_MODEi :: MEMORY_ADDRESS_EN [00:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_ADDRESS_EN_MASK 0x00000001 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_MODEi_MEMORY_ADDRESS_EN_SHIFT 0 /*************************************************************************** *TRIG_MEM_FILT_PIX_X1_Y1_COORD%i - X1,Y1 Coordinate ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_BASE 0x0040c730 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TRIG_MEM_FILT_PIX_X1_Y1_COORD%i - X1,Y1 Coordinate ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X1_Y1_COORDi :: reserved0 [31:27] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_reserved0_MASK 0xf8000000 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_reserved0_SHIFT 27 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X1_Y1_COORDi :: Y1_COORD [26:16] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_Y1_COORD_MASK 0x07ff0000 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_Y1_COORD_SHIFT 16 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X1_Y1_COORDi :: reserved1 [15:11] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_reserved1_MASK 0x0000f800 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_reserved1_SHIFT 11 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X1_Y1_COORDi :: X1_COORD [10:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_X1_COORD_MASK 0x000007ff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X1_Y1_COORDi_X1_COORD_SHIFT 0 /*************************************************************************** *TRIG_MEM_FILT_PIX_X2_Y2_COORD%i - X2,Y2 Coordinate ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_BASE 0x0040c740 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TRIG_MEM_FILT_PIX_X2_Y2_COORD%i - X2,Y2 Coordinate ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X2_Y2_COORDi :: reserved0 [31:27] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_reserved0_MASK 0xf8000000 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_reserved0_SHIFT 27 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X2_Y2_COORDi :: Y2_COORD [26:16] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_Y2_COORD_MASK 0x07ff0000 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_Y2_COORD_SHIFT 16 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X2_Y2_COORDi :: reserved1 [15:11] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_reserved1_MASK 0x0000f800 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_reserved1_SHIFT 11 /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_PIX_X2_Y2_COORDi :: X2_COORD [10:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_X2_COORD_MASK 0x000007ff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_PIX_X2_Y2_COORDi_X2_COORD_SHIFT 0 /*************************************************************************** *TRIG_MEM_FILT_CLIENT_MASK_64_95_%i - Trigger Memory Filter Window Client Mask for Clients 64-95 ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_BASE 0x0040c750 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_64_95_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TRIG_MEM_FILT_CLIENT_MASK_64_95_%i - Trigger Memory Filter Window Client Mask for Clients 64-95 ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_CLIENT_MASK_64_95_i :: MEMORY_CLIENT_MASK [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_64_95_i_MEMORY_CLIENT_MASK_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_64_95_i_MEMORY_CLIENT_MASK_SHIFT 0 /*************************************************************************** *TRIG_MEM_FILT_CLIENT_MASK_32_63_%i - Trigger Memory Filter Window Client Mask for Clients 32-63 ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_BASE 0x0040c760 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_32_63_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TRIG_MEM_FILT_CLIENT_MASK_32_63_%i - Trigger Memory Filter Window Client Mask for Clients 32-63 ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_CLIENT_MASK_32_63_i :: MEMORY_CLIENT_MASK [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_32_63_i_MEMORY_CLIENT_MASK_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_32_63_i_MEMORY_CLIENT_MASK_SHIFT 0 /*************************************************************************** *TRIG_MEM_FILT_CLIENT_MASK_31_0_%i - Trigger Memory Filter Window Client Mask for Clients 0-31 ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_BASE 0x0040c770 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_31_0_i_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TRIG_MEM_FILT_CLIENT_MASK_31_0_%i - Trigger Memory Filter Window Client Mask for Clients 0-31 ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_CLIENT_MASK_31_0_i :: MEMORY_CLIENT_MASK [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_31_0_i_MEMORY_CLIENT_MASK_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_CLIENT_MASK_31_0_i_MEMORY_CLIENT_MASK_SHIFT 0 /*************************************************************************** *TRIG_MEM_FILT_ADDR_UPPER%i - Trigger Memory Filter Window Client Mask Upper Bound Address ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_UPPERi_ARRAY_BASE 0x0040c780 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_UPPERi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_UPPERi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_UPPERi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TRIG_MEM_FILT_ADDR_UPPER%i - Trigger Memory Filter Window Client Mask Upper Bound Address ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_ADDR_UPPERi :: UPPER_MEMORY_ADDR [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_UPPERi_UPPER_MEMORY_ADDR_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_UPPERi_UPPER_MEMORY_ADDR_SHIFT 0 /*************************************************************************** *TRIG_MEM_FILT_ADDR_LOWER%i - Trigger Memory Filter Window Client Mask Lower Bound Address ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_LOWERi_ARRAY_BASE 0x0040c790 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_LOWERi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_LOWERi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_LOWERi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TRIG_MEM_FILT_ADDR_LOWER%i - Trigger Memory Filter Window Client Mask Lower Bound Address ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_MEM_FILT_ADDR_LOWERi :: LOWER_MEMORY_ADDR [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_LOWERi_LOWER_MEMORY_ADDR_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_MEM_FILT_ADDR_LOWERi_LOWER_MEMORY_ADDR_SHIFT 0 /*************************************************************************** *TRIG_IO_FILT_MODE%i - Trigger I/O Filter Mode ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_ARRAY_BASE 0x0040c7a0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TRIG_IO_FILT_MODE%i - Trigger I/O Filter Mode ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_MODEi :: reserved0 [31:06] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_reserved0_MASK 0xffffffc0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_reserved0_SHIFT 6 /* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_MODEi :: FILTER_IO_EN [05:05] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_FILTER_IO_EN_MASK 0x00000020 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_FILTER_IO_EN_SHIFT 5 /* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_MODEi :: GISB_READ_MODE [04:04] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_GISB_READ_MODE_MASK 0x00000010 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_GISB_READ_MODE_SHIFT 4 /* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_MODEi :: GISB_WRITE_MODE [03:03] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_GISB_WRITE_MODE_MASK 0x00000008 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_GISB_WRITE_MODE_SHIFT 3 /* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_MODEi :: DATA_MODE [02:02] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_DATA_MODE_MASK 0x00000004 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_DATA_MODE_SHIFT 2 /* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_MODEi :: IO_IN_OUT [01:01] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_IO_IN_OUT_MASK 0x00000002 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_IO_IN_OUT_SHIFT 1 /* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_MODEi :: IO_ADDRESS_EN [00:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_IO_ADDRESS_EN_MASK 0x00000001 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_MODEi_IO_ADDRESS_EN_SHIFT 0 /*************************************************************************** *TRIG_IO_FILT_ADDR_UPPER%i - Trigger I/O Filter Window Client Mask Upper Bound Address ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_UPPERi_ARRAY_BASE 0x0040c7b0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_UPPERi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_UPPERi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_UPPERi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TRIG_IO_FILT_ADDR_UPPER%i - Trigger I/O Filter Window Client Mask Upper Bound Address ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_ADDR_UPPERi :: IO_ADDR_UPPER [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_UPPERi_IO_ADDR_UPPER_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_UPPERi_IO_ADDR_UPPER_SHIFT 0 /*************************************************************************** *TRIG_IO_FILT_ADDR_LOWER%i - Trigger I/O Filter Window Client Mask Lower Bound Address ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_LOWERi_ARRAY_BASE 0x0040c7c0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_LOWERi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_LOWERi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_LOWERi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TRIG_IO_FILT_ADDR_LOWER%i - Trigger I/O Filter Window Client Mask Lower Bound Address ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_ADDR_LOWERi :: IO_ADDR_LOWER [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_LOWERi_IO_ADDR_LOWER_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_ADDR_LOWERi_IO_ADDR_LOWER_SHIFT 0 /*************************************************************************** *TRIG_IO_FILT_DATA%i - Trigger I/O Filter Window Data ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATAi_ARRAY_BASE 0x0040c7d0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATAi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATAi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATAi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TRIG_IO_FILT_DATA%i - Trigger I/O Filter Window Data ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_DATAi :: DATA [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATAi_DATA_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATAi_DATA_SHIFT 0 /*************************************************************************** *TRIG_IO_FILT_DATA_MASK%i - Trigger I/O Filter Window Data Mask ***************************************************************************/ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATA_MASKi_ARRAY_BASE 0x0040c7e0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATA_MASKi_ARRAY_START 0 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATA_MASKi_ARRAY_END 3 #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATA_MASKi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *TRIG_IO_FILT_DATA_MASK%i - Trigger I/O Filter Window Data Mask ***************************************************************************/ /* PRI_ARB_TRACE_REGS :: TRIG_IO_FILT_DATA_MASKi :: MASK [31:00] */ #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATA_MASKi_MASK_MASK 0xffffffff #define BCHP_PRI_ARB_TRACE_REGS_TRIG_IO_FILT_DATA_MASKi_MASK_SHIFT 0 #endif /* #ifndef BCHP_PRI_ARB_TRACE_REGS_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016200000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_1.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rt0000644000175000017500000000664611610313111031051 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_rts_l2_regs_1.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:17p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:23 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_rts_l2_regs_1.h $ * * Hydra_Software_Devel/1 7/17/09 8:17p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_RTS_L2_REGS_1_H__ #define BCHP_PRI_RTS_L2_REGS_1_H__ /*************************************************************************** *PRI_RTS_L2_REGS_1 - PRIMARY_ARB_CLIENTS L2 (Mips) rts interrupt controller 1 registers ***************************************************************************/ #define BCHP_PRI_RTS_L2_REGS_1_CPU_STATUS 0x0040c4c0 /* CPU interrupt Status Register */ #define BCHP_PRI_RTS_L2_REGS_1_CPU_SET 0x0040c4c4 /* CPU interrupt Set Register */ #define BCHP_PRI_RTS_L2_REGS_1_CPU_CLEAR 0x0040c4c8 /* CPU interrupt Clear Register */ #define BCHP_PRI_RTS_L2_REGS_1_CPU_MASK_STATUS 0x0040c4cc /* CPU interrupt Mask Status Register */ #define BCHP_PRI_RTS_L2_REGS_1_CPU_MASK_SET 0x0040c4d0 /* CPU interrupt Mask Set Register */ #define BCHP_PRI_RTS_L2_REGS_1_CPU_MASK_CLEAR 0x0040c4d4 /* CPU interrupt Mask Clear Register */ #define BCHP_PRI_RTS_L2_REGS_1_PCI_STATUS 0x0040c4d8 /* PCI interrupt Status Register */ #define BCHP_PRI_RTS_L2_REGS_1_PCI_SET 0x0040c4dc /* PCI interrupt Set Register */ #define BCHP_PRI_RTS_L2_REGS_1_PCI_CLEAR 0x0040c4e0 /* PCI interrupt Clear Register */ #define BCHP_PRI_RTS_L2_REGS_1_PCI_MASK_STATUS 0x0040c4e4 /* PCI interrupt Mask Status Register */ #define BCHP_PRI_RTS_L2_REGS_1_PCI_MASK_SET 0x0040c4e8 /* PCI interrupt Mask Set Register */ #define BCHP_PRI_RTS_L2_REGS_1_PCI_MASK_CLEAR 0x0040c4ec /* PCI interrupt Mask Clear Register */ #endif /* #ifndef BCHP_PRI_RTS_L2_REGS_1_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016600000000000011570 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_1.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_0000644000175000017500000010546311610313111030624 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_ddr23_phy_byte_lane_1.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:59p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:17 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_1.h $ * * Hydra_Software_Devel/1 7/17/09 7:59p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DDR23_PHY_BYTE_LANE_1_H__ #define BCHP_DDR23_PHY_BYTE_LANE_1_H__ /*************************************************************************** *DDR23_PHY_BYTE_LANE_1 - DDR23 DDR23 byte lane #1 control registers ***************************************************************************/ #define BCHP_DDR23_PHY_BYTE_LANE_1_REVISION 0x01801100 /* Byte lane revision register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE 0x01801104 /* Byte lane VDL calibration control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS 0x01801108 /* Byte lane VDL calibration status register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0 0x01801110 /* Read DQSP VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1 0x01801114 /* Read DQSN VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2 0x01801118 /* Read Enable VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3 0x0180111c /* Write data and mask VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4 0x01801120 /* Read DQSP VDL dynamic override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5 0x01801124 /* Read DQSN VDL dynamic override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6 0x01801128 /* Read Enable VDL dynamic override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7 0x0180112c /* Write data and mask VDL dynamic override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL 0x01801130 /* Byte Lane read channel control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_STATUS 0x01801134 /* Read fifo status register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_CLEAR 0x01801138 /* Read fifo status clear register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL 0x0180113c /* Idle mode SSTL pad control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL 0x01801140 /* SSTL pad drive characteristics control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE 0x01801144 /* Clock pad disable register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE 0x01801148 /* Write cycle preamble control register */ #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL 0x0180114c /* Clock Regulator control register */ /*************************************************************************** *REVISION - Byte lane revision register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: REVISION :: reserved0 [31:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_REVISION_reserved0_MASK 0xffff0000 #define BCHP_DDR23_PHY_BYTE_LANE_1_REVISION_reserved0_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: REVISION :: MAJOR [15:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_DDR23_PHY_BYTE_LANE_1_REVISION_MAJOR_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: REVISION :: MINOR [07:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_REVISION_MINOR_MASK 0x000000ff #define BCHP_DDR23_PHY_BYTE_LANE_1_REVISION_MINOR_SHIFT 0 /*************************************************************************** *VDL_CALIBRATE - Byte lane VDL calibration control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: reserved0 [31:05] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_reserved0_MASK 0xffffffe0 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_reserved0_SHIFT 5 /* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_clocks [04:04] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_clocks_MASK 0x00000010 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_clocks_SHIFT 4 /* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_test [03:03] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_test_MASK 0x00000008 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_test_SHIFT 3 /* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_always [02:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_always_MASK 0x00000004 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_always_SHIFT 2 /* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_once [01:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_once_MASK 0x00000002 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_once_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_fast [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_fast_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE_calib_fast_SHIFT 0 /*************************************************************************** *VDL_STATUS - Byte lane VDL calibration status register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: reserved0 [31:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_reserved0_MASK 0xffffc000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_reserved0_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: calib_total [13:04] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_calib_total_MASK 0x00003ff0 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_calib_total_SHIFT 4 /* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: reserved1 [03:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_reserved1_MASK 0x0000000c #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_reserved1_SHIFT 2 /* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: calib_lock [01:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_calib_lock_MASK 0x00000002 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_calib_lock_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: calib_idle [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_calib_idle_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS_calib_idle_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_0 - Read DQSP VDL static override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0_ovr_step_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_1 - Read DQSN VDL static override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1_ovr_step_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_2 - Read Enable VDL static override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2_ovr_step_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_3 - Write data and mask VDL static override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3_ovr_step_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_4 - Read DQSP VDL dynamic override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_4_ovr_step_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_5 - Read DQSN VDL dynamic override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_5_ovr_step_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_6 - Read Enable VDL dynamic override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_6_ovr_step_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_7 - Write data and mask VDL dynamic override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_7_ovr_step_SHIFT 0 /*************************************************************************** *READ_CONTROL - Byte Lane read channel control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: reserved0 [31:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_reserved0_MASK 0xfffffc00 #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_reserved0_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_data_dly [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_rd_data_dly_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_rd_data_dly_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: reserved1 [07:04] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_reserved1_MASK 0x000000f0 #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_reserved1_SHIFT 4 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: dq_odt_enable [03:03] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_dq_odt_enable_MASK 0x00000008 #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_dq_odt_enable_SHIFT 3 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: dq_odt_adj [02:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_dq_odt_adj_MASK 0x00000004 #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_dq_odt_adj_SHIFT 2 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_enb_odt_enable [01:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_rd_enb_odt_enable_MASK 0x00000002 #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_rd_enb_odt_enable_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_enb_odt_adj [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_rd_enb_odt_adj_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_rd_enb_odt_adj_SHIFT 0 /*************************************************************************** *READ_FIFO_STATUS - Read fifo status register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: reserved0 [31:04] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_STATUS_reserved0_MASK 0xfffffff0 #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_STATUS_reserved0_SHIFT 4 /* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: status [03:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_STATUS_status_MASK 0x0000000f #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_STATUS_status_SHIFT 0 /*************************************************************************** *READ_FIFO_CLEAR - Read fifo status clear register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_reserved0_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR :: clear [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_clear_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_1_READ_FIFO_CLEAR_clear_SHIFT 0 /*************************************************************************** *IDLE_PAD_CONTROL - Idle mode SSTL pad control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: idle [31:31] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_MASK 0x80000000 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_SHIFT 31 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_reserved0_SHIFT 20 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_rxenb [19:19] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_rxenb_MASK 0x00080000 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_rxenb_SHIFT 19 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_iddq [18:18] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_iddq_MASK 0x00040000 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_iddq_SHIFT 18 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_reb [17:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_reb_MASK 0x00020000 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_reb_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_oeb [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_oeb_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_oeb_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_rxenb [15:15] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00008000 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 15 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_iddq [14:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00004000 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_iddq_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_reb [13:13] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_reb_MASK 0x00002000 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_reb_SHIFT 13 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_oeb [12:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_oeb_MASK 0x00001000 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_oeb_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_rxenb [11:11] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00000800 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 11 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_iddq [10:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00000400 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_reb [09:09] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00000200 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 9 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_oeb [08:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00000100 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_rxenb [07:07] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000080 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 7 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_iddq [06:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000040 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_reb [05:05] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000020 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_reb_SHIFT 5 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_oeb [04:04] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000010 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 4 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_rxenb [03:03] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_rxenb_MASK 0x00000008 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_rxenb_SHIFT 3 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_iddq [02:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_iddq_MASK 0x00000004 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_iddq_SHIFT 2 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_reb [01:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_reb_MASK 0x00000002 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_reb_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_oeb [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_oeb_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_oeb_SHIFT 0 /*************************************************************************** *DRIVE_PAD_CTL - SSTL pad drive characteristics control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: reserved0 [31:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_reserved0_MASK 0xffffffc0 #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_reserved0_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: rt60b_ddr_read_enb [05:05] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_rt60b_ddr_read_enb_MASK 0x00000020 #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_rt60b_ddr_read_enb_SHIFT 5 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: rt60b [04:04] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_rt60b_MASK 0x00000010 #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_rt60b_SHIFT 4 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_sel_sstl18_MASK 0x00000008 #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_sel_sstl18_SHIFT 3 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_seltxdrv_ci_MASK 0x00000004 #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_seltxdrv_ci_SHIFT 2 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: selrxdrv [01:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_selrxdrv_MASK 0x00000002 #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_selrxdrv_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: slew [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_slew_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_slew_SHIFT 0 /*************************************************************************** *CLOCK_PAD_DISABLE - Clock pad disable register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: CLOCK_PAD_DISABLE :: reserved0 [31:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffffe #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE_reserved0_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: CLOCK_PAD_DISABLE :: clk_pad_dis [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE_clk_pad_dis_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE_clk_pad_dis_SHIFT 0 /*************************************************************************** *WR_PREAMBLE_MODE - Write cycle preamble control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: reserved0 [31:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffe #define BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_reserved0_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: mode [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_mode_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE_mode_SHIFT 0 /*************************************************************************** *CLOCK_REG_CONTROL - Clock Regulator control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: reserved0 [31:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_reserved0_MASK 0xfffffffc #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_reserved0_SHIFT 2 /* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: half_power [01:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_half_power_MASK 0x00000002 #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_half_power_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_SHIFT 0 #endif /* #ifndef BCHP_DDR23_PHY_BYTE_LANE_1_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000014700000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_gr.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_gr0000644000175000017500000001143211610313111031042 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_xpt_gr.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:23p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:11 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_gr.h $ * * Hydra_Software_Devel/1 7/17/09 8:23p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_XPT_GR_H__ #define BCHP_XPT_GR_H__ /*************************************************************************** *XPT_GR - XPT GR_BRIDGE Control Registers ***************************************************************************/ #define BCHP_XPT_GR_REVISION 0x00230000 /* GR Bridge Revision */ #define BCHP_XPT_GR_CTRL 0x00230004 /* GR Bridge Control Register */ #define BCHP_XPT_GR_SW_RESET_0 0x00230008 /* GR Bridge Software Reset 0 Register */ #define BCHP_XPT_GR_SW_RESET_1 0x0023000c /* GR Bridge Software Reset 1 Register */ /*************************************************************************** *REVISION - GR Bridge Revision ***************************************************************************/ /* XPT_GR :: REVISION :: reserved0 [31:16] */ #define BCHP_XPT_GR_REVISION_reserved0_MASK 0xffff0000 #define BCHP_XPT_GR_REVISION_reserved0_SHIFT 16 /* XPT_GR :: REVISION :: MAJOR [15:08] */ #define BCHP_XPT_GR_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_XPT_GR_REVISION_MAJOR_SHIFT 8 /* XPT_GR :: REVISION :: MINOR [07:00] */ #define BCHP_XPT_GR_REVISION_MINOR_MASK 0x000000ff #define BCHP_XPT_GR_REVISION_MINOR_SHIFT 0 /*************************************************************************** *CTRL - GR Bridge Control Register ***************************************************************************/ /* XPT_GR :: CTRL :: reserved0 [31:01] */ #define BCHP_XPT_GR_CTRL_reserved0_MASK 0xfffffffe #define BCHP_XPT_GR_CTRL_reserved0_SHIFT 1 /* XPT_GR :: CTRL :: gisb_error_intr [00:00] */ #define BCHP_XPT_GR_CTRL_gisb_error_intr_MASK 0x00000001 #define BCHP_XPT_GR_CTRL_gisb_error_intr_SHIFT 0 #define BCHP_XPT_GR_CTRL_gisb_error_intr_INTR_DISABLE 0 #define BCHP_XPT_GR_CTRL_gisb_error_intr_INTR_ENABLE 1 /*************************************************************************** *SW_RESET_0 - GR Bridge Software Reset 0 Register ***************************************************************************/ /* XPT_GR :: SW_RESET_0 :: reserved0 [31:00] */ #define BCHP_XPT_GR_SW_RESET_0_reserved0_MASK 0xffffffff #define BCHP_XPT_GR_SW_RESET_0_reserved0_SHIFT 0 /*************************************************************************** *SW_RESET_1 - GR Bridge Software Reset 1 Register ***************************************************************************/ /* XPT_GR :: SW_RESET_1 :: reserved0 [31:00] */ #define BCHP_XPT_GR_SW_RESET_1_reserved0_MASK 0xffffffff #define BCHP_XPT_GR_SW_RESET_1_reserved0_SHIFT 0 #endif /* #ifndef BCHP_XPT_GR_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016300000000000011565 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_2.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_cr0000644000175000017500000002037311610313111031021 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_crit_l2_regs_2.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:16p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:09 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_crit_l2_regs_2.h $ * * Hydra_Software_Devel/1 7/17/09 8:16p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_CRIT_L2_REGS_2_H__ #define BCHP_PRI_CRIT_L2_REGS_2_H__ /*************************************************************************** *PRI_CRIT_L2_REGS_2 - PRIMARY_ARB_CLIENTS L2 (Mips) critical interrupt controller 2 registers ***************************************************************************/ #define BCHP_PRI_CRIT_L2_REGS_2_CPU_STATUS 0x0040c440 /* CPU interrupt Status Register */ #define BCHP_PRI_CRIT_L2_REGS_2_CPU_SET 0x0040c444 /* CPU interrupt Set Register */ #define BCHP_PRI_CRIT_L2_REGS_2_CPU_CLEAR 0x0040c448 /* CPU interrupt Clear Register */ #define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_STATUS 0x0040c44c /* CPU interrupt Mask Status Register */ #define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_SET 0x0040c450 /* CPU interrupt Mask Set Register */ #define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_CLEAR 0x0040c454 /* CPU interrupt Mask Clear Register */ #define BCHP_PRI_CRIT_L2_REGS_2_PCI_STATUS 0x0040c458 /* PCI interrupt Status Register */ #define BCHP_PRI_CRIT_L2_REGS_2_PCI_SET 0x0040c45c /* PCI interrupt Set Register */ #define BCHP_PRI_CRIT_L2_REGS_2_PCI_CLEAR 0x0040c460 /* PCI interrupt Clear Register */ #define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_STATUS 0x0040c464 /* PCI interrupt Mask Status Register */ #define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_SET 0x0040c468 /* PCI interrupt Mask Set Register */ #define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_CLEAR 0x0040c46c /* PCI interrupt Mask Clear Register */ /*************************************************************************** *CPU_STATUS - CPU interrupt Status Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_2 :: CPU_STATUS :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_2_CPU_STATUS_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_2_CPU_STATUS_reserved0_SHIFT 0 /*************************************************************************** *CPU_SET - CPU interrupt Set Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_2 :: CPU_SET :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_2_CPU_SET_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_2_CPU_SET_reserved0_SHIFT 0 /*************************************************************************** *CPU_CLEAR - CPU interrupt Clear Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_2 :: CPU_CLEAR :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_2_CPU_CLEAR_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_2_CPU_CLEAR_reserved0_SHIFT 0 /*************************************************************************** *CPU_MASK_STATUS - CPU interrupt Mask Status Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_2 :: CPU_MASK_STATUS :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_STATUS_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_STATUS_reserved0_SHIFT 0 /*************************************************************************** *CPU_MASK_SET - CPU interrupt Mask Set Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_2 :: CPU_MASK_SET :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_SET_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_SET_reserved0_SHIFT 0 /*************************************************************************** *CPU_MASK_CLEAR - CPU interrupt Mask Clear Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_2 :: CPU_MASK_CLEAR :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_CLEAR_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_2_CPU_MASK_CLEAR_reserved0_SHIFT 0 /*************************************************************************** *PCI_STATUS - PCI interrupt Status Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_2 :: PCI_STATUS :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_2_PCI_STATUS_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_2_PCI_STATUS_reserved0_SHIFT 0 /*************************************************************************** *PCI_SET - PCI interrupt Set Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_2 :: PCI_SET :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_2_PCI_SET_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_2_PCI_SET_reserved0_SHIFT 0 /*************************************************************************** *PCI_CLEAR - PCI interrupt Clear Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_2 :: PCI_CLEAR :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_2_PCI_CLEAR_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_2_PCI_CLEAR_reserved0_SHIFT 0 /*************************************************************************** *PCI_MASK_STATUS - PCI interrupt Mask Status Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_2 :: PCI_MASK_STATUS :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_STATUS_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_STATUS_reserved0_SHIFT 0 /*************************************************************************** *PCI_MASK_SET - PCI interrupt Mask Set Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_2 :: PCI_MASK_SET :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_SET_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_SET_reserved0_SHIFT 0 /*************************************************************************** *PCI_MASK_CLEAR - PCI interrupt Mask Clear Register ***************************************************************************/ /* PRI_CRIT_L2_REGS_2 :: PCI_MASK_CLEAR :: reserved0 [31:00] */ #define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_CLEAR_reserved0_MASK 0xffffffff #define BCHP_PRI_CRIT_L2_REGS_2_PCI_MASK_CLEAR_reserved0_SHIFT 0 #endif /* #ifndef BCHP_PRI_CRIT_L2_REGS_2_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015000000000000011561 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rgr.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rg0000644000175000017500000001433411610313111031040 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_sun_rgr.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:20p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:14 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_sun_rgr.h $ * * Hydra_Software_Devel/1 7/17/09 8:20p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_SUN_RGR_H__ #define BCHP_SUN_RGR_H__ /*************************************************************************** *SUN_RGR - Registers for the Sundry block's RGR bridge ***************************************************************************/ #define BCHP_SUN_RGR_REVISION 0x00400800 /* RGR Bridge Revision */ #define BCHP_SUN_RGR_CTRL 0x00400804 /* RGR Bridge Control Register */ #define BCHP_SUN_RGR_RBUS_TIMER 0x00400808 /* RGR Bridge RBUS Timer Register */ #define BCHP_SUN_RGR_SW_RESET_0 0x0040080c /* RGR Bridge Software Reset 0 Register */ #define BCHP_SUN_RGR_SW_RESET_1 0x00400810 /* RGR Bridge Software Reset 1 Register */ /*************************************************************************** *REVISION - RGR Bridge Revision ***************************************************************************/ /* SUN_RGR :: REVISION :: reserved0 [31:16] */ #define BCHP_SUN_RGR_REVISION_reserved0_MASK 0xffff0000 #define BCHP_SUN_RGR_REVISION_reserved0_SHIFT 16 /* SUN_RGR :: REVISION :: MAJOR [15:08] */ #define BCHP_SUN_RGR_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_SUN_RGR_REVISION_MAJOR_SHIFT 8 /* SUN_RGR :: REVISION :: MINOR [07:00] */ #define BCHP_SUN_RGR_REVISION_MINOR_MASK 0x000000ff #define BCHP_SUN_RGR_REVISION_MINOR_SHIFT 0 /*************************************************************************** *CTRL - RGR Bridge Control Register ***************************************************************************/ /* SUN_RGR :: CTRL :: reserved0 [31:02] */ #define BCHP_SUN_RGR_CTRL_reserved0_MASK 0xfffffffc #define BCHP_SUN_RGR_CTRL_reserved0_SHIFT 2 /* SUN_RGR :: CTRL :: rbus_error_intr [01:01] */ #define BCHP_SUN_RGR_CTRL_rbus_error_intr_MASK 0x00000002 #define BCHP_SUN_RGR_CTRL_rbus_error_intr_SHIFT 1 #define BCHP_SUN_RGR_CTRL_rbus_error_intr_INTR_DISABLE 0 #define BCHP_SUN_RGR_CTRL_rbus_error_intr_INTR_ENABLE 1 /* SUN_RGR :: CTRL :: gisb_error_intr [00:00] */ #define BCHP_SUN_RGR_CTRL_gisb_error_intr_MASK 0x00000001 #define BCHP_SUN_RGR_CTRL_gisb_error_intr_SHIFT 0 #define BCHP_SUN_RGR_CTRL_gisb_error_intr_INTR_DISABLE 0 #define BCHP_SUN_RGR_CTRL_gisb_error_intr_INTR_ENABLE 1 /*************************************************************************** *RBUS_TIMER - RGR Bridge RBUS Timer Register ***************************************************************************/ /* SUN_RGR :: RBUS_TIMER :: reserved0 [31:16] */ #define BCHP_SUN_RGR_RBUS_TIMER_reserved0_MASK 0xffff0000 #define BCHP_SUN_RGR_RBUS_TIMER_reserved0_SHIFT 16 /* SUN_RGR :: RBUS_TIMER :: timer_value [15:00] */ #define BCHP_SUN_RGR_RBUS_TIMER_timer_value_MASK 0x0000ffff #define BCHP_SUN_RGR_RBUS_TIMER_timer_value_SHIFT 0 /*************************************************************************** *SW_RESET_0 - RGR Bridge Software Reset 0 Register ***************************************************************************/ /* SUN_RGR :: SW_RESET_0 :: reserved0 [31:01] */ #define BCHP_SUN_RGR_SW_RESET_0_reserved0_MASK 0xfffffffe #define BCHP_SUN_RGR_SW_RESET_0_reserved0_SHIFT 1 /* SUN_RGR :: SW_RESET_0 :: ccb_arbiter_sw_reset [00:00] */ #define BCHP_SUN_RGR_SW_RESET_0_ccb_arbiter_sw_reset_MASK 0x00000001 #define BCHP_SUN_RGR_SW_RESET_0_ccb_arbiter_sw_reset_SHIFT 0 /*************************************************************************** *SW_RESET_1 - RGR Bridge Software Reset 1 Register ***************************************************************************/ /* SUN_RGR :: SW_RESET_1 :: reserved0 [31:01] */ #define BCHP_SUN_RGR_SW_RESET_1_reserved0_MASK 0xfffffffe #define BCHP_SUN_RGR_SW_RESET_1_reserved0_SHIFT 1 /* SUN_RGR :: SW_RESET_1 :: unused_sw_reset [00:00] */ #define BCHP_SUN_RGR_SW_RESET_1_unused_sw_reset_MASK 0x00000001 #define BCHP_SUN_RGR_SW_RESET_1_unused_sw_reset_SHIFT 0 #endif /* #ifndef BCHP_SUN_RGR_H__ */ /* End of File */ crystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_irq1.h0000644000175000017500000000452111610313111030642 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_irq1.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:10p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:34 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_irq1.h $ * * Hydra_Software_Devel/1 7/17/09 8:10p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_IRQ1_H__ #define BCHP_IRQ1_H__ /*************************************************************************** *IRQ1 - Level 2 PCI Interrupt Enable/Status ***************************************************************************/ #define BCHP_IRQ1_IRQEN 0x00406788 /* Interrupt Enable */ #define BCHP_IRQ1_IRQSTAT 0x0040678c /* Interrupt Status */ #endif /* #ifndef BCHP_IRQ1_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016200000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuimem2_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000455711610313111030774 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_cpuimem2_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:01p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:51 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuimem2_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:01p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_CPUIMEM2_0_H__ #define BCHP_DECODE_CPUIMEM2_0_H__ /*************************************************************************** *DECODE_CPUIMEM2_0 ***************************************************************************/ #define BCHP_DECODE_CPUIMEM2_0_CPUIMEM_REG 0x00856000 /* CPUIMEM_REG */ #define BCHP_DECODE_CPUIMEM2_0_CPUIMEM_END 0x00857ffc /* CPUIMEM_END */ #endif /* #ifndef BCHP_DECODE_CPUIMEM2_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015700000000000011570 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_int_id0000644000175000017500000000630311610313111031006 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_int_id_xpt_pb0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:08p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:40 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility unknown * RDB Parser 3.0 * generate_int_id.pl 1.0 * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_int_id_xpt_pb0.h $ * * Hydra_Software_Devel/1 7/17/09 8:08p albertl * PR56880: Initial revision. * ***************************************************************************/ #include "bchp.h" #include "bchp_xpt_pb0.h" #ifndef BCHP_INT_ID_XPT_PB0_H__ #define BCHP_INT_ID_XPT_PB0_H__ #define BCHP_INT_ID_XPT_PB0_DONE_INT BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_DONE_INT_SHIFT) #define BCHP_INT_ID_XPT_PB0_PARSER_CONTINUITY_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_PARSER_CONTINUITY_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB0_PARSER_LENGTH_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_PARSER_LENGTH_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB0_PARSER_SEC_CC_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_PARSER_SEC_CC_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB0_PARSER_TRANSPORT_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_PARSER_TRANSPORT_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB0_PB_COPYRIGHT_CHANGE BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_PB_COPYRIGHT_CHANGE_SHIFT) #define BCHP_INT_ID_XPT_PB0_SE_OUT_OF_SYNC_INT BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_SE_OUT_OF_SYNC_INT_SHIFT) #define BCHP_INT_ID_XPT_PB0_TS_PARITY_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_TS_PARITY_ERROR_SHIFT) #define BCHP_INT_ID_XPT_PB0_TS_RANGE_ERROR BCHP_INT_ID_CREATE(BCHP_XPT_PB0_INTR, BCHP_XPT_PB0_INTR_TS_RANGE_ERROR_SHIFT) #endif /* #ifndef BCHP_INT_ID_XPT_PB0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016500000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_block_avg_regs_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_avd_bl0000644000175000017500000002501511610313111030770 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_avd_block_avg_regs_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:56p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:49 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_avd_block_avg_regs_0.h $ * * Hydra_Software_Devel/1 7/17/09 7:56p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_AVD_BLOCK_AVG_REGS_0_H__ #define BCHP_AVD_BLOCK_AVG_REGS_0_H__ /*************************************************************************** *AVD_BLOCK_AVG_REGS_0 - FGT Block Avg Registers 0 ***************************************************************************/ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_8x8_AVG_BASE_ADDR 0x00861000 /* REG_8x8_AVG_BASE_ADDR */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_4x8_SUM_BASE_ADDR 0x00861004 /* REG_4x8_SUM_BASE_ADDR */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL 0x00861008 /* REG_AVG_CTL */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_IMAGE_PARAM 0x0086100c /* REG_IMAGE_PARAM */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_ERR 0x00861010 /* REG_AVG_ERR */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_DONE 0x00861014 /* REG_AVG_DONE */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_RESET 0x00861018 /* REG_AVG_RESET */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP 0x0086101c /* REG_VC1_RRMAP */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_BLOCK_AVG_END 0x0086103c /* REG_BLOCK_AVG_END */ /*************************************************************************** *REG_8x8_AVG_BASE_ADDR - REG_8x8_AVG_BASE_ADDR ***************************************************************************/ /* AVD_BLOCK_AVG_REGS_0 :: REG_8x8_AVG_BASE_ADDR :: Value [31:00] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_8x8_AVG_BASE_ADDR_Value_MASK 0xffffffff #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_8x8_AVG_BASE_ADDR_Value_SHIFT 0 /*************************************************************************** *REG_4x8_SUM_BASE_ADDR - REG_4x8_SUM_BASE_ADDR ***************************************************************************/ /* AVD_BLOCK_AVG_REGS_0 :: REG_4x8_SUM_BASE_ADDR :: Value [31:00] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_4x8_SUM_BASE_ADDR_Value_MASK 0xffffffff #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_4x8_SUM_BASE_ADDR_Value_SHIFT 0 /*************************************************************************** *REG_AVG_CTL - REG_AVG_CTL ***************************************************************************/ /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: reserved0 [31:09] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_reserved0_MASK 0xfffffe00 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_reserved0_SHIFT 9 /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: Enable_stall [08:08] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Enable_stall_MASK 0x00000100 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Enable_stall_SHIFT 8 /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: Debug [07:07] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Debug_MASK 0x00000080 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Debug_SHIFT 7 /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: Enable [06:06] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Enable_MASK 0x00000040 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Enable_SHIFT 6 /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: Monochrome [05:05] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Monochrome_MASK 0x00000020 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Monochrome_SHIFT 5 /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: VC1_Interlace [04:04] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_VC1_Interlace_MASK 0x00000010 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_VC1_Interlace_SHIFT 4 /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: MBAFF [03:03] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_MBAFF_MASK 0x00000008 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_MBAFF_SHIFT 3 /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: Frame [02:02] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Frame_MASK 0x00000004 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Frame_SHIFT 2 /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_CTL :: Standard [01:00] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Standard_MASK 0x00000003 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_CTL_Standard_SHIFT 0 /*************************************************************************** *REG_IMAGE_PARAM - REG_IMAGE_PARAM ***************************************************************************/ /* AVD_BLOCK_AVG_REGS_0 :: REG_IMAGE_PARAM :: Image_Width [31:16] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_IMAGE_PARAM_Image_Width_MASK 0xffff0000 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_IMAGE_PARAM_Image_Width_SHIFT 16 /* AVD_BLOCK_AVG_REGS_0 :: REG_IMAGE_PARAM :: Image_Height [15:00] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_IMAGE_PARAM_Image_Height_MASK 0x0000ffff #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_IMAGE_PARAM_Image_Height_SHIFT 0 /*************************************************************************** *REG_AVG_ERR - REG_AVG_ERR ***************************************************************************/ /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_ERR :: reserved0 [31:01] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_ERR_reserved0_MASK 0xfffffffe #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_ERR_reserved0_SHIFT 1 /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_ERR :: Overflow_error [00:00] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_ERR_Overflow_error_MASK 0x00000001 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_ERR_Overflow_error_SHIFT 0 /*************************************************************************** *REG_AVG_DONE - REG_AVG_DONE ***************************************************************************/ /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_DONE :: reserved0 [31:01] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_DONE_reserved0_MASK 0xfffffffe #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_DONE_reserved0_SHIFT 1 /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_DONE :: Average_done [00:00] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_DONE_Average_done_MASK 0x00000001 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_DONE_Average_done_SHIFT 0 /*************************************************************************** *REG_AVG_RESET - REG_AVG_RESET ***************************************************************************/ /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_RESET :: reserved0 [31:01] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_RESET_reserved0_MASK 0xfffffffe #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_RESET_reserved0_SHIFT 1 /* AVD_BLOCK_AVG_REGS_0 :: REG_AVG_RESET :: Reset [00:00] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_RESET_Reset_MASK 0x00000001 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_AVG_RESET_Reset_SHIFT 0 /*************************************************************************** *REG_VC1_RRMAP - REG_VC1_RRMAP ***************************************************************************/ /* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: VC1_main [31:31] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_VC1_main_MASK 0x80000000 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_VC1_main_SHIFT 31 /* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: reserved0 [30:16] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_reserved0_MASK 0x7fff0000 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_reserved0_SHIFT 16 /* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: Luma_range_en [15:15] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Luma_range_en_MASK 0x00008000 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Luma_range_en_SHIFT 15 /* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: reserved1 [14:11] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_reserved1_MASK 0x00007800 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_reserved1_SHIFT 11 /* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: Luma_range [10:08] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Luma_range_MASK 0x00000700 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Luma_range_SHIFT 8 /* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: Chroma_range_en [07:07] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Chroma_range_en_MASK 0x00000080 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Chroma_range_en_SHIFT 7 /* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: reserved2 [06:03] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_reserved2_MASK 0x00000078 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_reserved2_SHIFT 3 /* AVD_BLOCK_AVG_REGS_0 :: REG_VC1_RRMAP :: Chroma_range [02:00] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Chroma_range_MASK 0x00000007 #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_VC1_RRMAP_Chroma_range_SHIFT 0 /*************************************************************************** *REG_BLOCK_AVG_END - REG_BLOCK_AVG_END ***************************************************************************/ /* AVD_BLOCK_AVG_REGS_0 :: REG_BLOCK_AVG_END :: reserved0 [31:00] */ #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_BLOCK_AVG_END_reserved0_MASK 0xffffffff #define BCHP_AVD_BLOCK_AVG_REGS_0_REG_BLOCK_AVG_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_AVD_BLOCK_AVG_REGS_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015000000000000011561 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb1.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb0000644000175000017500000001037211610313111031035 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_xpt_pb1.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:24p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:51 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb1.h $ * * Hydra_Software_Devel/1 7/17/09 8:24p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_XPT_PB1_H__ #define BCHP_XPT_PB1_H__ /*************************************************************************** *XPT_PB1 - Playback 1 Control Registers ***************************************************************************/ #define BCHP_XPT_PB1_CTRL1 0x0020b080 /* Playback Control 1 Register */ #define BCHP_XPT_PB1_CTRL2 0x0020b084 /* Playback Control 2 Register */ #define BCHP_XPT_PB1_CTRL3 0x0020b088 /* Playback Control 3 Register */ #define BCHP_XPT_PB1_CTRL4 0x0020b08c /* Playback Control 4 Register */ #define BCHP_XPT_PB1_FIRST_DESC_ADDR 0x0020b090 /* Playback First Descriptor Address Register */ #define BCHP_XPT_PB1_CURR_DESC_ADDR 0x0020b094 /* Playback Current Descriptor Address Register */ #define BCHP_XPT_PB1_CURR_BUFF_ADDR 0x0020b098 /* Playback Current Buffer Address Register */ #define BCHP_XPT_PB1_BLOCKOUT 0x0020b09c /* Data Transport Playback Block Out Control */ #define BCHP_XPT_PB1_PKTZ_CONTEXT0 0x0020b0a0 /* Data Transport Playback Packetize Mode Context 0 Control */ #define BCHP_XPT_PB1_PKTZ_CONTEXT1 0x0020b0a4 /* Data Transport Playback Packetize Mode Context 1 Control */ #define BCHP_XPT_PB1_PKTZ_CONTEXT2 0x0020b0a8 /* Data Transport Playback Packetize Mode Context 2 Control */ #define BCHP_XPT_PB1_PKTZ_CONTEXT3 0x0020b0ac /* Data Transport Playback Packetize Mode Context 3 Control */ #define BCHP_XPT_PB1_TS_ERR_BOUND 0x0020b0b0 /* Data Transport Playback Timestamp Error Bound Register */ #define BCHP_XPT_PB1_PARSER_CTRL1 0x0020b0b4 /* Data Transport Playback Parser Control Register */ #define BCHP_XPT_PB1_PARSER_CTRL2 0x0020b0b8 /* Data Transport Playback Parser Control Register 2 */ #define BCHP_XPT_PB1_PARSER_TIMESTAMP 0x0020b0bc /* Data Transport Playback Parser Local Timestamp */ #define BCHP_XPT_PB1_INTR 0x0020b0c0 /* Playback Processing Error and Status Interrupt Register */ #define BCHP_XPT_PB1_INTR_EN 0x0020b0c4 /* Playback Processing Error and Status Interrupt Enable Register */ #define BCHP_XPT_PB1_INTR_TAGS 0x0020b0c8 /* Playback Interrupt Tag Register */ #endif /* #ifndef BCHP_XPT_PB1_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016400000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_sint_oloop_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000002631711610313111030772 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_sint_oloop_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:05p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:11 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_sint_oloop_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:05p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_SINT_OLOOP_0_H__ #define BCHP_DECODE_SINT_OLOOP_0_H__ /*************************************************************************** *DECODE_SINT_OLOOP_0 ***************************************************************************/ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_ADDR 0x0080cc00 /* DEC_SINT_DMA_ADDR */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_LEN 0x0080cc04 /* DEC_SINT_DMA_LEN */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_BASE 0x0080cc08 /* DEC_SINT_DMA_BASE */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_END 0x0080cc0c /* DEC_SINT_DMA_END */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_POS 0x0080cc10 /* DEC_SINT_STRM_POS */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT 0x0080cc14 /* DEC_SINT_STRM_STAT */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA 0x0080cc18 /* DEC_SINT_IENA */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_BITS 0x0080cc1c /* DEC_SINT_STRM_BITS */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB 0x0080cc20 /* DEC_SINT_GET_SYMB */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_OLOOP_END 0x0080ccfc /* DEC_OLOOP_END */ /*************************************************************************** *DEC_SINT_DMA_ADDR - DEC_SINT_DMA_ADDR ***************************************************************************/ /* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_ADDR :: Addr [31:02] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_ADDR_Addr_MASK 0xfffffffc #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_ADDR_Addr_SHIFT 2 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_ADDR :: reserved0 [01:00] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_ADDR_reserved0_MASK 0x00000003 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_ADDR_reserved0_SHIFT 0 /*************************************************************************** *DEC_SINT_DMA_LEN - DEC_SINT_DMA_LEN ***************************************************************************/ /* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_LEN :: Length [31:05] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_LEN_Length_MASK 0xffffffe0 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_LEN_Length_SHIFT 5 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_LEN :: reserved0 [04:00] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_LEN_reserved0_MASK 0x0000001f #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_LEN_reserved0_SHIFT 0 /*************************************************************************** *DEC_SINT_DMA_BASE - DEC_SINT_DMA_BASE ***************************************************************************/ /* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_BASE :: Base [31:08] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_BASE_Base_MASK 0xffffff00 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_BASE_Base_SHIFT 8 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_BASE :: reserved0 [07:01] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_BASE_reserved0_MASK 0x000000fe #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_BASE_reserved0_SHIFT 1 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_BASE :: Endian [00:00] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_BASE_Endian_MASK 0x00000001 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_BASE_Endian_SHIFT 0 /*************************************************************************** *DEC_SINT_DMA_END - DEC_SINT_DMA_END ***************************************************************************/ /* DECODE_SINT_OLOOP_0 :: DEC_SINT_DMA_END :: End [31:00] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_END_End_MASK 0xffffffff #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_DMA_END_End_SHIFT 0 /*************************************************************************** *DEC_SINT_STRM_POS - DEC_SINT_STRM_POS ***************************************************************************/ /* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_POS :: Bit_pos [31:00] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_POS_Bit_pos_MASK 0xffffffff #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_POS_Bit_pos_SHIFT 0 /*************************************************************************** *DEC_SINT_STRM_STAT - DEC_SINT_STRM_STAT ***************************************************************************/ /* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: reserved0 [31:19] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved0_MASK 0xfff80000 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved0_SHIFT 19 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: FlushInput [18:18] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_FlushInput_MASK 0x00040000 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_FlushInput_SHIFT 18 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: reserved1 [17:17] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved1_MASK 0x00020000 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved1_SHIFT 17 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: Rst [16:16] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Rst_MASK 0x00010000 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Rst_SHIFT 16 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: reserved2 [15:10] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved2_MASK 0x0000fc00 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved2_SHIFT 10 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: Derr [09:09] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Derr_MASK 0x00000200 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Derr_SHIFT 9 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: Serr [08:08] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Serr_MASK 0x00000100 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Serr_SHIFT 8 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: reserved3 [07:04] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved3_MASK 0x000000f0 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved3_SHIFT 4 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: Dact [03:03] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Dact_MASK 0x00000008 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Dact_SHIFT 3 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: reserved4 [02:01] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved4_MASK 0x00000006 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_reserved4_SHIFT 1 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_STAT :: Sval [00:00] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Sval_MASK 0x00000001 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_STAT_Sval_SHIFT 0 /*************************************************************************** *DEC_SINT_IENA - DEC_SINT_IENA ***************************************************************************/ /* DECODE_SINT_OLOOP_0 :: DEC_SINT_IENA :: reserved0 [31:10] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_reserved0_MASK 0xfffffc00 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_reserved0_SHIFT 10 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_IENA :: Derr [09:09] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_Derr_MASK 0x00000200 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_Derr_SHIFT 9 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_IENA :: Serr [08:08] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_Serr_MASK 0x00000100 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_Serr_SHIFT 8 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_IENA :: reserved1 [07:00] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_reserved1_MASK 0x000000ff #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_IENA_reserved1_SHIFT 0 /*************************************************************************** *DEC_SINT_STRM_BITS - DEC_SINT_STRM_BITS ***************************************************************************/ /* DECODE_SINT_OLOOP_0 :: DEC_SINT_STRM_BITS :: Stream_Bits [31:00] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_BITS_Stream_Bits_MASK 0xffffffff #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_STRM_BITS_Stream_Bits_SHIFT 0 /*************************************************************************** *DEC_SINT_GET_SYMB - DEC_SINT_GET_SYMB ***************************************************************************/ /* DECODE_SINT_OLOOP_0 :: DEC_SINT_GET_SYMB :: reserved0 [31:16] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_reserved0_MASK 0xffff0000 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_reserved0_SHIFT 16 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_GET_SYMB :: Type [15:12] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_Type_MASK 0x0000f000 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_Type_SHIFT 12 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_GET_SYMB :: SubType [11:08] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_SubType_MASK 0x00000f00 #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_SubType_SHIFT 8 /* DECODE_SINT_OLOOP_0 :: DEC_SINT_GET_SYMB :: N [07:00] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_N_MASK 0x000000ff #define BCHP_DECODE_SINT_OLOOP_0_DEC_SINT_GET_SYMB_N_SHIFT 0 /*************************************************************************** *DEC_OLOOP_END - DEC_OLOOP_END ***************************************************************************/ /* DECODE_SINT_OLOOP_0 :: DEC_OLOOP_END :: reserved0 [31:00] */ #define BCHP_DECODE_SINT_OLOOP_0_DEC_OLOOP_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_SINT_OLOOP_0_DEC_OLOOP_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_SINT_OLOOP_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015000000000000011561 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb2.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb0000644000175000017500000001037211610313111031035 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_xpt_pb2.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:24p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:32 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_xpt_pb2.h $ * * Hydra_Software_Devel/1 7/17/09 8:24p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_XPT_PB2_H__ #define BCHP_XPT_PB2_H__ /*************************************************************************** *XPT_PB2 - Playback 2 Control Registers ***************************************************************************/ #define BCHP_XPT_PB2_CTRL1 0x0020b100 /* Playback Control 1 Register */ #define BCHP_XPT_PB2_CTRL2 0x0020b104 /* Playback Control 2 Register */ #define BCHP_XPT_PB2_CTRL3 0x0020b108 /* Playback Control 3 Register */ #define BCHP_XPT_PB2_CTRL4 0x0020b10c /* Playback Control 4 Register */ #define BCHP_XPT_PB2_FIRST_DESC_ADDR 0x0020b110 /* Playback First Descriptor Address Register */ #define BCHP_XPT_PB2_CURR_DESC_ADDR 0x0020b114 /* Playback Current Descriptor Address Register */ #define BCHP_XPT_PB2_CURR_BUFF_ADDR 0x0020b118 /* Playback Current Buffer Address Register */ #define BCHP_XPT_PB2_BLOCKOUT 0x0020b11c /* Data Transport Playback Block Out Control */ #define BCHP_XPT_PB2_PKTZ_CONTEXT0 0x0020b120 /* Data Transport Playback Packetize Mode Context 0 Control */ #define BCHP_XPT_PB2_PKTZ_CONTEXT1 0x0020b124 /* Data Transport Playback Packetize Mode Context 1 Control */ #define BCHP_XPT_PB2_PKTZ_CONTEXT2 0x0020b128 /* Data Transport Playback Packetize Mode Context 2 Control */ #define BCHP_XPT_PB2_PKTZ_CONTEXT3 0x0020b12c /* Data Transport Playback Packetize Mode Context 3 Control */ #define BCHP_XPT_PB2_TS_ERR_BOUND 0x0020b130 /* Data Transport Playback Timestamp Error Bound Register */ #define BCHP_XPT_PB2_PARSER_CTRL1 0x0020b134 /* Data Transport Playback Parser Control Register */ #define BCHP_XPT_PB2_PARSER_CTRL2 0x0020b138 /* Data Transport Playback Parser Control Register 2 */ #define BCHP_XPT_PB2_PARSER_TIMESTAMP 0x0020b13c /* Data Transport Playback Parser Local Timestamp */ #define BCHP_XPT_PB2_INTR 0x0020b140 /* Playback Processing Error and Status Interrupt Register */ #define BCHP_XPT_PB2_INTR_EN 0x0020b144 /* Playback Processing Error and Status Interrupt Enable Register */ #define BCHP_XPT_PB2_INTR_TAGS 0x0020b148 /* Playback Interrupt Tag Register */ #endif /* #ifndef BCHP_XPT_PB2_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016100000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuaux2_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000454711610313111030773 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_cpuaux2_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:59p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:35 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpuaux2_0.h $ * * Hydra_Software_Devel/1 7/17/09 7:59p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_CPUAUX2_0_H__ #define BCHP_DECODE_CPUAUX2_0_H__ /*************************************************************************** *DECODE_CPUAUX2_0 ***************************************************************************/ #define BCHP_DECODE_CPUAUX2_0_CPUAUX_REG 0x00855000 /* CPUAUX_REG */ #define BCHP_DECODE_CPUAUX2_0_CPUAUX_END 0x00855ffc /* CPUAUX_END */ #endif /* #ifndef BCHP_DECODE_CPUAUX2_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016100000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_msa_regs.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_pri_ar0000644000175000017500000001565411610313111031025 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_pri_arb_msa_regs.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:15p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:49 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_pri_arb_msa_regs.h $ * * Hydra_Software_Devel/1 7/17/09 8:15p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_PRI_ARB_MSA_REGS_H__ #define BCHP_PRI_ARB_MSA_REGS_H__ /*************************************************************************** *PRI_ARB_MSA_REGS - PRIMARY_ARB memory soft access client registers ***************************************************************************/ #define BCHP_PRI_ARB_MSA_REGS_STATUS 0x0040c800 /* Memory Controller MSA Status Register */ #define BCHP_PRI_ARB_MSA_REGS_CMD_TYPE 0x0040c804 /* Memory Controller SCB Command Type Register */ #define BCHP_PRI_ARB_MSA_REGS_CMD_ADDR 0x0040c808 /* Memory Controller SCB Address Register */ /*************************************************************************** *STATUS - Memory Controller MSA Status Register ***************************************************************************/ /* PRI_ARB_MSA_REGS :: STATUS :: reserved0 [31:04] */ #define BCHP_PRI_ARB_MSA_REGS_STATUS_reserved0_MASK 0xfffffff0 #define BCHP_PRI_ARB_MSA_REGS_STATUS_reserved0_SHIFT 4 /* PRI_ARB_MSA_REGS :: STATUS :: FIFO_FULL [03:03] */ #define BCHP_PRI_ARB_MSA_REGS_STATUS_FIFO_FULL_MASK 0x00000008 #define BCHP_PRI_ARB_MSA_REGS_STATUS_FIFO_FULL_SHIFT 3 /* PRI_ARB_MSA_REGS :: STATUS :: FIFO_EMPTY [02:02] */ #define BCHP_PRI_ARB_MSA_REGS_STATUS_FIFO_EMPTY_MASK 0x00000004 #define BCHP_PRI_ARB_MSA_REGS_STATUS_FIFO_EMPTY_SHIFT 2 /* PRI_ARB_MSA_REGS :: STATUS :: T_LOCK [01:01] */ #define BCHP_PRI_ARB_MSA_REGS_STATUS_T_LOCK_MASK 0x00000002 #define BCHP_PRI_ARB_MSA_REGS_STATUS_T_LOCK_SHIFT 1 /* PRI_ARB_MSA_REGS :: STATUS :: BUSY [00:00] */ #define BCHP_PRI_ARB_MSA_REGS_STATUS_BUSY_MASK 0x00000001 #define BCHP_PRI_ARB_MSA_REGS_STATUS_BUSY_SHIFT 0 /*************************************************************************** *CMD_TYPE - Memory Controller SCB Command Type Register ***************************************************************************/ /* PRI_ARB_MSA_REGS :: CMD_TYPE :: reserved0 [31:09] */ #define BCHP_PRI_ARB_MSA_REGS_CMD_TYPE_reserved0_MASK 0xfffffe00 #define BCHP_PRI_ARB_MSA_REGS_CMD_TYPE_reserved0_SHIFT 9 /* PRI_ARB_MSA_REGS :: CMD_TYPE :: REQ_TYPE [08:00] */ #define BCHP_PRI_ARB_MSA_REGS_CMD_TYPE_REQ_TYPE_MASK 0x000001ff #define BCHP_PRI_ARB_MSA_REGS_CMD_TYPE_REQ_TYPE_SHIFT 0 /*************************************************************************** *CMD_ADDR - Memory Controller SCB Address Register ***************************************************************************/ /* PRI_ARB_MSA_REGS :: CMD_ADDR :: reserved_for_eco0 [31:29] */ #define BCHP_PRI_ARB_MSA_REGS_CMD_ADDR_reserved_for_eco0_MASK 0xe0000000 #define BCHP_PRI_ARB_MSA_REGS_CMD_ADDR_reserved_for_eco0_SHIFT 29 /* PRI_ARB_MSA_REGS :: CMD_ADDR :: ADDR [28:00] */ #define BCHP_PRI_ARB_MSA_REGS_CMD_ADDR_ADDR_MASK 0x1fffffff #define BCHP_PRI_ARB_MSA_REGS_CMD_ADDR_ADDR_SHIFT 0 /*************************************************************************** *MSA_DATA%i - Memory Controller MSA Data Register ***************************************************************************/ #define BCHP_PRI_ARB_MSA_REGS_MSA_DATAi_ARRAY_BASE 0x0040c810 #define BCHP_PRI_ARB_MSA_REGS_MSA_DATAi_ARRAY_START 0 #define BCHP_PRI_ARB_MSA_REGS_MSA_DATAi_ARRAY_END 63 #define BCHP_PRI_ARB_MSA_REGS_MSA_DATAi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *MSA_DATA%i - Memory Controller MSA Data Register ***************************************************************************/ /* PRI_ARB_MSA_REGS :: MSA_DATAi :: Data [31:00] */ #define BCHP_PRI_ARB_MSA_REGS_MSA_DATAi_Data_MASK 0xffffffff #define BCHP_PRI_ARB_MSA_REGS_MSA_DATAi_Data_SHIFT 0 /*************************************************************************** *MSA_MASK%i - Memory Controller MSA Mask Data Register ***************************************************************************/ #define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_ARRAY_BASE 0x0040c910 #define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_ARRAY_START 0 #define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_ARRAY_END 63 #define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_ARRAY_ELEMENT_SIZE 32 /*************************************************************************** *MSA_MASK%i - Memory Controller MSA Mask Data Register ***************************************************************************/ /* PRI_ARB_MSA_REGS :: MSA_MASKi :: reserved0 [31:04] */ #define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_reserved0_MASK 0xfffffff0 #define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_reserved0_SHIFT 4 /* PRI_ARB_MSA_REGS :: MSA_MASKi :: Mask [03:00] */ #define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_Mask_MASK 0x0000000f #define BCHP_PRI_ARB_MSA_REGS_MSA_MASKi_Mask_SHIFT 0 #endif /* #ifndef BCHP_PRI_ARB_MSA_REGS_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016200000000000011564 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dqnt_8x8_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000527411610313111030771 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_dqnt_8x8_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:03p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:35 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_dqnt_8x8_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:03p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_DQNT_8X8_0_H__ #define BCHP_DECODE_DQNT_8X8_0_H__ /*************************************************************************** *DECODE_DQNT_8X8_0 ***************************************************************************/ #define BCHP_DECODE_DQNT_8X8_0_REG_DQNT_8X8_END 0x0080057c /* REG_DQNT_8X8_END */ /*************************************************************************** *REG_DQNT_8X8_END - REG_DQNT_8X8_END ***************************************************************************/ /* DECODE_DQNT_8X8_0 :: REG_DQNT_8X8_END :: reserved0 [31:00] */ #define BCHP_DECODE_DQNT_8X8_0_REG_DQNT_8X8_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_DQNT_8X8_0_REG_DQNT_8X8_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_DQNT_8X8_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015600000000000011567 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_xfrm_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000002707011610313111030767 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_xfrm_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:06p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:16 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_xfrm_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:06p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_XFRM_0_H__ #define BCHP_DECODE_XFRM_0_H__ /*************************************************************************** *DECODE_XFRM_0 ***************************************************************************/ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL 0x00800700 /* Inverse Transform Control */ #define BCHP_DECODE_XFRM_0_REG_IXFM_COEF 0x00800704 /* Inverse Transform Coefficients */ #define BCHP_DECODE_XFRM_0_REG_IXFM_OUT 0x00800708 /* Residual buffer IDs */ #define BCHP_DECODE_XFRM_0_REG_IXFM_PCM 0x0080070c /* PCM Pixel data */ #define BCHP_DECODE_XFRM_0_REG_IXFM_264_COEF_NORUN 0x00800710 /* REG_IXFM_264_COEF_NORUN */ #define BCHP_DECODE_XFRM_0_REG_IXFM_BLK_SIZE 0x00800714 /* REG_IXFM_BLK_SIZE */ #define BCHP_DECODE_XFRM_0_REG_IXFM_SLICE 0x00800718 /* Slice ID */ #define BCHP_DECODE_XFRM_0_REG_IXFM_END 0x0080071c /* REG_IXFM_END */ /*************************************************************************** *REG_IXFM_CTL - Inverse Transform Control ***************************************************************************/ /* DECODE_XFRM_0 :: REG_IXFM_CTL :: Xfm [31:30] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Xfm_MASK 0xc0000000 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Xfm_SHIFT 30 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: Scan [29:29] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Scan_MASK 0x20000000 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Scan_SHIFT 29 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: USE_QS_TAB [28:28] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_USE_QS_TAB_MASK 0x10000000 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_USE_QS_TAB_SHIFT 28 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: CoefOrder_8x8 [27:27] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_CoefOrder_8x8_MASK 0x08000000 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_CoefOrder_8x8_SHIFT 27 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: Fld [26:26] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Fld_MASK 0x04000000 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Fld_SHIFT 26 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: Odd_ [25:25] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Odd__MASK 0x02000000 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Odd__SHIFT 25 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: Type [24:24] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Type_MASK 0x01000000 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_Type_SHIFT 24 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: reserved0 [23:23] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_reserved0_MASK 0x00800000 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_reserved0_SHIFT 23 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: QpY [22:16] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_QpY_MASK 0x007f0000 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_QpY_SHIFT 16 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: reserved1 [15:13] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_reserved1_MASK 0x0000e000 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_reserved1_SHIFT 13 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: OVERLAPTXM_BIT_SHIFT [12:12] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_OVERLAPTXM_BIT_SHIFT_MASK 0x00001000 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_OVERLAPTXM_BIT_SHIFT_SHIFT 12 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: NonUniform [11:11] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_NonUniform_MASK 0x00000800 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_NonUniform_SHIFT 11 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: ACPred [10:10] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_ACPred_MASK 0x00000400 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_ACPred_SHIFT 10 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: HalfQP [09:09] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_HalfQP_MASK 0x00000200 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_HalfQP_SHIFT 9 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: TopAvail [08:08] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_TopAvail_MASK 0x00000100 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_TopAvail_SHIFT 8 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: reserved2 [07:05] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_reserved2_MASK 0x000000e0 #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_reserved2_SHIFT 5 /* DECODE_XFRM_0 :: REG_IXFM_CTL :: CBP [04:00] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_CBP_MASK 0x0000001f #define BCHP_DECODE_XFRM_0_REG_IXFM_CTL_CBP_SHIFT 0 /*************************************************************************** *REG_IXFM_COEF - Inverse Transform Coefficients ***************************************************************************/ /* DECODE_XFRM_0 :: REG_IXFM_COEF :: Run0 [31:28] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Run0_MASK 0xf0000000 #define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Run0_SHIFT 28 /* DECODE_XFRM_0 :: REG_IXFM_COEF :: Coef0 [27:16] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Coef0_MASK 0x0fff0000 #define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Coef0_SHIFT 16 /* DECODE_XFRM_0 :: REG_IXFM_COEF :: Run1 [15:12] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Run1_MASK 0x0000f000 #define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Run1_SHIFT 12 /* DECODE_XFRM_0 :: REG_IXFM_COEF :: Coef1 [11:00] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Coef1_MASK 0x00000fff #define BCHP_DECODE_XFRM_0_REG_IXFM_COEF_Coef1_SHIFT 0 /*************************************************************************** *REG_IXFM_OUT - Residual buffer IDs ***************************************************************************/ /* DECODE_XFRM_0 :: REG_IXFM_OUT :: reserved0 [31:16] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_OUT_reserved0_MASK 0xffff0000 #define BCHP_DECODE_XFRM_0_REG_IXFM_OUT_reserved0_SHIFT 16 /* DECODE_XFRM_0 :: REG_IXFM_OUT :: Pict1 [15:08] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_OUT_Pict1_MASK 0x0000ff00 #define BCHP_DECODE_XFRM_0_REG_IXFM_OUT_Pict1_SHIFT 8 /* DECODE_XFRM_0 :: REG_IXFM_OUT :: Pict0 [07:00] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_OUT_Pict0_MASK 0x000000ff #define BCHP_DECODE_XFRM_0_REG_IXFM_OUT_Pict0_SHIFT 0 /*************************************************************************** *REG_IXFM_PCM - PCM Pixel data ***************************************************************************/ /* DECODE_XFRM_0 :: REG_IXFM_PCM :: Pixel0 [31:24] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel0_MASK 0xff000000 #define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel0_SHIFT 24 /* DECODE_XFRM_0 :: REG_IXFM_PCM :: Pixel1 [23:16] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel1_MASK 0x00ff0000 #define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel1_SHIFT 16 /* DECODE_XFRM_0 :: REG_IXFM_PCM :: Pixel2 [15:08] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel2_MASK 0x0000ff00 #define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel2_SHIFT 8 /* DECODE_XFRM_0 :: REG_IXFM_PCM :: Pixel3 [07:00] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel3_MASK 0x000000ff #define BCHP_DECODE_XFRM_0_REG_IXFM_PCM_Pixel3_SHIFT 0 /*************************************************************************** *REG_IXFM_264_COEF_NORUN - REG_IXFM_264_COEF_NORUN ***************************************************************************/ /* DECODE_XFRM_0 :: REG_IXFM_264_COEF_NORUN :: coef1 [31:16] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_264_COEF_NORUN_coef1_MASK 0xffff0000 #define BCHP_DECODE_XFRM_0_REG_IXFM_264_COEF_NORUN_coef1_SHIFT 16 /* DECODE_XFRM_0 :: REG_IXFM_264_COEF_NORUN :: coef0 [15:00] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_264_COEF_NORUN_coef0_MASK 0x0000ffff #define BCHP_DECODE_XFRM_0_REG_IXFM_264_COEF_NORUN_coef0_SHIFT 0 /*************************************************************************** *REG_IXFM_BLK_SIZE - REG_IXFM_BLK_SIZE ***************************************************************************/ /* DECODE_XFRM_0 :: REG_IXFM_BLK_SIZE :: reserved0 [31:03] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_BLK_SIZE_reserved0_MASK 0xfffffff8 #define BCHP_DECODE_XFRM_0_REG_IXFM_BLK_SIZE_reserved0_SHIFT 3 /* DECODE_XFRM_0 :: REG_IXFM_BLK_SIZE :: Intra [02:02] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_BLK_SIZE_Intra_MASK 0x00000004 #define BCHP_DECODE_XFRM_0_REG_IXFM_BLK_SIZE_Intra_SHIFT 2 /* DECODE_XFRM_0 :: REG_IXFM_BLK_SIZE :: SIZE [01:00] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_BLK_SIZE_SIZE_MASK 0x00000003 #define BCHP_DECODE_XFRM_0_REG_IXFM_BLK_SIZE_SIZE_SHIFT 0 /*************************************************************************** *REG_IXFM_SLICE - Slice ID ***************************************************************************/ /* DECODE_XFRM_0 :: REG_IXFM_SLICE :: reserved0 [31:07] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_SLICE_reserved0_MASK 0xffffff80 #define BCHP_DECODE_XFRM_0_REG_IXFM_SLICE_reserved0_SHIFT 7 /* DECODE_XFRM_0 :: REG_IXFM_SLICE :: Slice_ID [06:00] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_SLICE_Slice_ID_MASK 0x0000007f #define BCHP_DECODE_XFRM_0_REG_IXFM_SLICE_Slice_ID_SHIFT 0 /*************************************************************************** *REG_IXFM_END - REG_IXFM_END ***************************************************************************/ /* DECODE_XFRM_0 :: REG_IXFM_END :: reserved0 [31:00] */ #define BCHP_DECODE_XFRM_0_REG_IXFM_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_XFRM_0_REG_IXFM_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_XFRM_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000014600000000000011566 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc3.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_misc3.0000644000175000017500000002501311610313111030633 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_misc3.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:11p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:19 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_misc3.h $ * * Hydra_Software_Devel/1 7/17/09 8:11p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_MISC3_H__ #define BCHP_MISC3_H__ /*************************************************************************** *MISC3 - Registers for Reset, Options, DMA Checksums ***************************************************************************/ #define BCHP_MISC3_RESET_CTRL 0x00502200 /* Reset Control Register */ #define BCHP_MISC3_RX_CHECKSUM 0x0050220c /* Pixel Receive Checksum */ #define BCHP_MISC3_TX_CHECKSUM 0x00502210 /* Transmit Checksum */ #define BCHP_MISC3_ECO_CTRL_CORE 0x00502214 /* ECO Core Reset Control Register */ #define BCHP_MISC3_OPTIONS_CTRL 0x00502218 /* PCIe Options Control Register */ #define BCHP_MISC3_SW_ARB_CTRL 0x00502220 /* Software Arbitration Register */ #define BCHP_MISC3_HIF_RX_CHECKSUM 0x00502224 /* HIF Receive Checksum */ #define BCHP_MISC3_META_CHECKSUM 0x00502228 /* Meta Data Checksum */ #define BCHP_MISC3_MEMORY_CTRL 0x0050222c /* Memory Control Register */ /*************************************************************************** *RESET_CTRL - Reset Control Register ***************************************************************************/ /* MISC3 :: RESET_CTRL :: reserved0 [31:09] */ #define BCHP_MISC3_RESET_CTRL_reserved0_MASK 0xfffffe00 #define BCHP_MISC3_RESET_CTRL_reserved0_SHIFT 9 /* MISC3 :: RESET_CTRL :: PLL_RESET [08:08] */ #define BCHP_MISC3_RESET_CTRL_PLL_RESET_MASK 0x00000100 #define BCHP_MISC3_RESET_CTRL_PLL_RESET_SHIFT 8 /* MISC3 :: RESET_CTRL :: reserved1 [07:03] */ #define BCHP_MISC3_RESET_CTRL_reserved1_MASK 0x000000f8 #define BCHP_MISC3_RESET_CTRL_reserved1_SHIFT 3 /* MISC3 :: RESET_CTRL :: LOW_POWER [02:02] */ #define BCHP_MISC3_RESET_CTRL_LOW_POWER_MASK 0x00000004 #define BCHP_MISC3_RESET_CTRL_LOW_POWER_SHIFT 2 /* MISC3 :: RESET_CTRL :: POR_RESET [01:01] */ #define BCHP_MISC3_RESET_CTRL_POR_RESET_MASK 0x00000002 #define BCHP_MISC3_RESET_CTRL_POR_RESET_SHIFT 1 /* MISC3 :: RESET_CTRL :: CORE_RESET [00:00] */ #define BCHP_MISC3_RESET_CTRL_CORE_RESET_MASK 0x00000001 #define BCHP_MISC3_RESET_CTRL_CORE_RESET_SHIFT 0 /*************************************************************************** *RX_CHECKSUM - Pixel Receive Checksum ***************************************************************************/ /* MISC3 :: RX_CHECKSUM :: RX_CHECKSUM [31:00] */ #define BCHP_MISC3_RX_CHECKSUM_RX_CHECKSUM_MASK 0xffffffff #define BCHP_MISC3_RX_CHECKSUM_RX_CHECKSUM_SHIFT 0 /*************************************************************************** *TX_CHECKSUM - Transmit Checksum ***************************************************************************/ /* MISC3 :: TX_CHECKSUM :: TX_CHECKSUM [31:00] */ #define BCHP_MISC3_TX_CHECKSUM_TX_CHECKSUM_MASK 0xffffffff #define BCHP_MISC3_TX_CHECKSUM_TX_CHECKSUM_SHIFT 0 /*************************************************************************** *ECO_CTRL_CORE - ECO Core Reset Control Register ***************************************************************************/ /* MISC3 :: ECO_CTRL_CORE :: reserved0 [31:16] */ #define BCHP_MISC3_ECO_CTRL_CORE_reserved0_MASK 0xffff0000 #define BCHP_MISC3_ECO_CTRL_CORE_reserved0_SHIFT 16 /* MISC3 :: ECO_CTRL_CORE :: ECO_CORE_RST_N [15:00] */ #define BCHP_MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_MASK 0x0000ffff #define BCHP_MISC3_ECO_CTRL_CORE_ECO_CORE_RST_N_SHIFT 0 /*************************************************************************** *OPTIONS_CTRL - PCIe Options Control Register ***************************************************************************/ /* MISC3 :: OPTIONS_CTRL :: reserved0 [31:05] */ #define BCHP_MISC3_OPTIONS_CTRL_reserved0_MASK 0xffffffe0 #define BCHP_MISC3_OPTIONS_CTRL_reserved0_SHIFT 5 /* MISC3 :: OPTIONS_CTRL :: CQ39842_FIX_DISABLE [04:04] */ #define BCHP_MISC3_OPTIONS_CTRL_CQ39842_FIX_DISABLE_MASK 0x00000010 #define BCHP_MISC3_OPTIONS_CTRL_CQ39842_FIX_DISABLE_SHIFT 4 /* MISC3 :: OPTIONS_CTRL :: CQ35254_DISABLE [03:03] */ #define BCHP_MISC3_OPTIONS_CTRL_CQ35254_DISABLE_MASK 0x00000008 #define BCHP_MISC3_OPTIONS_CTRL_CQ35254_DISABLE_SHIFT 3 /* MISC3 :: OPTIONS_CTRL :: CQ31984_ENABLE_OPT2 [02:02] */ #define BCHP_MISC3_OPTIONS_CTRL_CQ31984_ENABLE_OPT2_MASK 0x00000004 #define BCHP_MISC3_OPTIONS_CTRL_CQ31984_ENABLE_OPT2_SHIFT 2 /* MISC3 :: OPTIONS_CTRL :: CQ31984_ENABLE_OPT1 [01:01] */ #define BCHP_MISC3_OPTIONS_CTRL_CQ31984_ENABLE_OPT1_MASK 0x00000002 #define BCHP_MISC3_OPTIONS_CTRL_CQ31984_ENABLE_OPT1_SHIFT 1 /* MISC3 :: OPTIONS_CTRL :: CQ30674_DISABLE [00:00] */ #define BCHP_MISC3_OPTIONS_CTRL_CQ30674_DISABLE_MASK 0x00000001 #define BCHP_MISC3_OPTIONS_CTRL_CQ30674_DISABLE_SHIFT 0 /*************************************************************************** *SW_ARB_CTRL - Software Arbitration Register ***************************************************************************/ /* MISC3 :: SW_ARB_CTRL :: reserved0 [31:08] */ #define BCHP_MISC3_SW_ARB_CTRL_reserved0_MASK 0xffffff00 #define BCHP_MISC3_SW_ARB_CTRL_reserved0_SHIFT 8 /* MISC3 :: SW_ARB_CTRL :: req1 [07:07] */ #define BCHP_MISC3_SW_ARB_CTRL_req1_MASK 0x00000080 #define BCHP_MISC3_SW_ARB_CTRL_req1_SHIFT 7 /* MISC3 :: SW_ARB_CTRL :: arb_won1 [06:06] */ #define BCHP_MISC3_SW_ARB_CTRL_arb_won1_MASK 0x00000040 #define BCHP_MISC3_SW_ARB_CTRL_arb_won1_SHIFT 6 /* MISC3 :: SW_ARB_CTRL :: reserved1 [05:04] */ #define BCHP_MISC3_SW_ARB_CTRL_reserved1_MASK 0x00000030 #define BCHP_MISC3_SW_ARB_CTRL_reserved1_SHIFT 4 /* MISC3 :: SW_ARB_CTRL :: req0 [03:03] */ #define BCHP_MISC3_SW_ARB_CTRL_req0_MASK 0x00000008 #define BCHP_MISC3_SW_ARB_CTRL_req0_SHIFT 3 /* MISC3 :: SW_ARB_CTRL :: arb_won0 [02:02] */ #define BCHP_MISC3_SW_ARB_CTRL_arb_won0_MASK 0x00000004 #define BCHP_MISC3_SW_ARB_CTRL_arb_won0_SHIFT 2 /* MISC3 :: SW_ARB_CTRL :: req_clr0 [01:01] */ #define BCHP_MISC3_SW_ARB_CTRL_req_clr0_MASK 0x00000002 #define BCHP_MISC3_SW_ARB_CTRL_req_clr0_SHIFT 1 /* MISC3 :: SW_ARB_CTRL :: req_set0 [00:00] */ #define BCHP_MISC3_SW_ARB_CTRL_req_set0_MASK 0x00000001 #define BCHP_MISC3_SW_ARB_CTRL_req_set0_SHIFT 0 /*************************************************************************** *HIF_RX_CHECKSUM - HIF Receive Checksum ***************************************************************************/ /* MISC3 :: HIF_RX_CHECKSUM :: HIF_RX_CHECKSUM [31:00] */ #define BCHP_MISC3_HIF_RX_CHECKSUM_HIF_RX_CHECKSUM_MASK 0xffffffff #define BCHP_MISC3_HIF_RX_CHECKSUM_HIF_RX_CHECKSUM_SHIFT 0 /*************************************************************************** *META_CHECKSUM - Meta Data Checksum ***************************************************************************/ /* MISC3 :: META_CHECKSUM :: META_CHECKSUM [31:00] */ #define BCHP_MISC3_META_CHECKSUM_META_CHECKSUM_MASK 0xffffffff #define BCHP_MISC3_META_CHECKSUM_META_CHECKSUM_SHIFT 0 /*************************************************************************** *MEMORY_CTRL - Memory Control Register ***************************************************************************/ /* MISC3 :: MEMORY_CTRL :: reserved0 [31:06] */ #define BCHP_MISC3_MEMORY_CTRL_reserved0_MASK 0xffffffc0 #define BCHP_MISC3_MEMORY_CTRL_reserved0_SHIFT 6 /* MISC3 :: MEMORY_CTRL :: TM_DLL_RETRY [05:04] */ #define BCHP_MISC3_MEMORY_CTRL_TM_DLL_RETRY_MASK 0x00000030 #define BCHP_MISC3_MEMORY_CTRL_TM_DLL_RETRY_SHIFT 4 /* MISC3 :: MEMORY_CTRL :: TM_TXDMA_BUFFER [03:02] */ #define BCHP_MISC3_MEMORY_CTRL_TM_TXDMA_BUFFER_MASK 0x0000000c #define BCHP_MISC3_MEMORY_CTRL_TM_TXDMA_BUFFER_SHIFT 2 /* MISC3 :: MEMORY_CTRL :: TM_BC_FIFO [01:00] */ #define BCHP_MISC3_MEMORY_CTRL_TM_BC_FIFO_MASK 0x00000003 #define BCHP_MISC3_MEMORY_CTRL_TM_BC_FIFO_SHIFT 0 #endif /* #ifndef BCHP_MISC3_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016100000000000011563 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpucore_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000000616011610313111030764 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_cpucore_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:00p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:26 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_cpucore_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:00p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_CPUCORE_0_H__ #define BCHP_DECODE_CPUCORE_0_H__ /*************************************************************************** *DECODE_CPUCORE_0 ***************************************************************************/ #define BCHP_DECODE_CPUCORE_0_CPUCORE_REG 0x00844000 /* CPUCORE_REG */ #define BCHP_DECODE_CPUCORE_0_CPUCORE_END 0x00844ffc /* CPUCORE_END */ /*************************************************************************** *CPUCORE_REG - CPUCORE_REG ***************************************************************************/ /* DECODE_CPUCORE_0 :: CPUCORE_REG :: Addr [31:00] */ #define BCHP_DECODE_CPUCORE_0_CPUCORE_REG_Addr_MASK 0xffffffff #define BCHP_DECODE_CPUCORE_0_CPUCORE_REG_Addr_SHIFT 0 /*************************************************************************** *CPUCORE_END - CPUCORE_END ***************************************************************************/ /* DECODE_CPUCORE_0 :: CPUCORE_END :: reserved0 [31:00] */ #define BCHP_DECODE_CPUCORE_0_CPUCORE_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_CPUCORE_0_CPUCORE_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_CPUCORE_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000016600000000000011570 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_0000644000175000017500000010546411610313111030625 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_ddr23_phy_byte_lane_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 7:59p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:43:18 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_ddr23_phy_byte_lane_0.h $ * * Hydra_Software_Devel/1 7/17/09 7:59p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DDR23_PHY_BYTE_LANE_0_H__ #define BCHP_DDR23_PHY_BYTE_LANE_0_H__ /*************************************************************************** *DDR23_PHY_BYTE_LANE_0 - DDR23 DDR23 byte lane #0 control registers ***************************************************************************/ #define BCHP_DDR23_PHY_BYTE_LANE_0_REVISION 0x01801200 /* Byte lane revision register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE 0x01801204 /* Byte lane VDL calibration control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS 0x01801208 /* Byte lane VDL calibration status register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0 0x01801210 /* Read DQSP VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1 0x01801214 /* Read DQSN VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2 0x01801218 /* Read Enable VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3 0x0180121c /* Write data and mask VDL static override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4 0x01801220 /* Read DQSP VDL dynamic override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5 0x01801224 /* Read DQSN VDL dynamic override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6 0x01801228 /* Read Enable VDL dynamic override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7 0x0180122c /* Write data and mask VDL dynamic override control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL 0x01801230 /* Byte Lane read channel control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_STATUS 0x01801234 /* Read fifo status register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_CLEAR 0x01801238 /* Read fifo status clear register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL 0x0180123c /* Idle mode SSTL pad control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL 0x01801240 /* SSTL pad drive characteristics control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE 0x01801244 /* Clock pad disable register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE 0x01801248 /* Write cycle preamble control register */ #define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL 0x0180124c /* Clock Regulator control register */ /*************************************************************************** *REVISION - Byte lane revision register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: REVISION :: reserved0 [31:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_REVISION_reserved0_MASK 0xffff0000 #define BCHP_DDR23_PHY_BYTE_LANE_0_REVISION_reserved0_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: REVISION :: MAJOR [15:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_DDR23_PHY_BYTE_LANE_0_REVISION_MAJOR_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: REVISION :: MINOR [07:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_REVISION_MINOR_MASK 0x000000ff #define BCHP_DDR23_PHY_BYTE_LANE_0_REVISION_MINOR_SHIFT 0 /*************************************************************************** *VDL_CALIBRATE - Byte lane VDL calibration control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: reserved0 [31:05] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_reserved0_MASK 0xffffffe0 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_reserved0_SHIFT 5 /* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_clocks [04:04] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_clocks_MASK 0x00000010 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_clocks_SHIFT 4 /* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_test [03:03] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_test_MASK 0x00000008 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_test_SHIFT 3 /* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_always [02:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_always_MASK 0x00000004 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_always_SHIFT 2 /* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_once [01:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_once_MASK 0x00000002 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_once_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: VDL_CALIBRATE :: calib_fast [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_fast_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE_calib_fast_SHIFT 0 /*************************************************************************** *VDL_STATUS - Byte lane VDL calibration status register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: reserved0 [31:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_reserved0_MASK 0xffffc000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_reserved0_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: calib_total [13:04] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_calib_total_MASK 0x00003ff0 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_calib_total_SHIFT 4 /* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: reserved1 [03:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_reserved1_MASK 0x0000000c #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_reserved1_SHIFT 2 /* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: calib_lock [01:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_calib_lock_MASK 0x00000002 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_calib_lock_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: VDL_STATUS :: calib_idle [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_calib_idle_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS_calib_idle_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_0 - Read DQSP VDL static override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_0 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0_ovr_step_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_1 - Read DQSN VDL static override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_1 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1_ovr_step_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_2 - Read Enable VDL static override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_2 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2_ovr_step_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_3 - Write data and mask VDL static override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_3 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3_ovr_step_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_4 - Read DQSP VDL dynamic override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_4 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_4_ovr_step_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_5 - Read DQSN VDL dynamic override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_5 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_5_ovr_step_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_6 - Read Enable VDL dynamic override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_6 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_6_ovr_step_SHIFT 0 /*************************************************************************** *VDL_OVERRIDE_7 - Write data and mask VDL dynamic override control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved0 [31:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved0_MASK 0xfffe0000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved0_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_en [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_en_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_en_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved1 [15:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved1_MASK 0x0000c000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved1_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_fine_fall [13:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_fine_fall_MASK 0x00003000 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_fine_fall_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved2 [11:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved2_MASK 0x00000c00 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved2_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_fine_rise [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_fine_rise_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_fine_rise_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: reserved3 [07:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved3_MASK 0x000000c0 #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_reserved3_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: VDL_OVERRIDE_7 :: ovr_step [05:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_step_MASK 0x0000003f #define BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_7_ovr_step_SHIFT 0 /*************************************************************************** *READ_CONTROL - Byte Lane read channel control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: reserved0 [31:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_reserved0_MASK 0xfffffc00 #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_reserved0_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_data_dly [09:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK 0x00000300 #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: reserved1 [07:04] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_reserved1_MASK 0x000000f0 #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_reserved1_SHIFT 4 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: dq_odt_enable [03:03] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_MASK 0x00000008 #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_SHIFT 3 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: dq_odt_adj [02:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_MASK 0x00000004 #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_SHIFT 2 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_enb_odt_enable [01:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_MASK 0x00000002 #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: READ_CONTROL :: rd_enb_odt_adj [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_SHIFT 0 /*************************************************************************** *READ_FIFO_STATUS - Read fifo status register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: reserved0 [31:04] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_STATUS_reserved0_MASK 0xfffffff0 #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_STATUS_reserved0_SHIFT 4 /* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_STATUS :: status [03:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_STATUS_status_MASK 0x0000000f #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_STATUS_status_SHIFT 0 /*************************************************************************** *READ_FIFO_CLEAR - Read fifo status clear register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR :: reserved0 [31:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_reserved0_MASK 0xfffffffe #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_reserved0_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: READ_FIFO_CLEAR :: clear [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_clear_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_0_READ_FIFO_CLEAR_clear_SHIFT 0 /*************************************************************************** *IDLE_PAD_CONTROL - Idle mode SSTL pad control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: idle [31:31] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_MASK 0x80000000 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_SHIFT 31 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: reserved0 [30:20] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_reserved0_MASK 0x7ff00000 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_reserved0_SHIFT 20 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_rxenb [19:19] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_rxenb_MASK 0x00080000 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_rxenb_SHIFT 19 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_iddq [18:18] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_iddq_MASK 0x00040000 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_iddq_SHIFT 18 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_reb [17:17] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_reb_MASK 0x00020000 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_reb_SHIFT 17 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dm_oeb [16:16] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_oeb_MASK 0x00010000 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_oeb_SHIFT 16 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_rxenb [15:15] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_rxenb_MASK 0x00008000 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_rxenb_SHIFT 15 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_iddq [14:14] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_iddq_MASK 0x00004000 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_iddq_SHIFT 14 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_reb [13:13] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_reb_MASK 0x00002000 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_reb_SHIFT 13 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dq_oeb [12:12] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_oeb_MASK 0x00001000 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_oeb_SHIFT 12 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_rxenb [11:11] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_rxenb_MASK 0x00000800 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_rxenb_SHIFT 11 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_iddq [10:10] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK 0x00000400 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_SHIFT 10 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_reb [09:09] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_reb_MASK 0x00000200 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_reb_SHIFT 9 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: read_enb_oeb [08:08] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_oeb_MASK 0x00000100 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_oeb_SHIFT 8 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_rxenb [07:07] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_rxenb_MASK 0x00000080 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_rxenb_SHIFT 7 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_iddq [06:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_MASK 0x00000040 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_reb [05:05] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_reb_MASK 0x00000020 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_reb_SHIFT 5 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: dqs_oeb [04:04] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_oeb_MASK 0x00000010 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_oeb_SHIFT 4 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_rxenb [03:03] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_rxenb_MASK 0x00000008 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_rxenb_SHIFT 3 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_iddq [02:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_iddq_MASK 0x00000004 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_iddq_SHIFT 2 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_reb [01:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_reb_MASK 0x00000002 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_reb_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: IDLE_PAD_CONTROL :: clk_oeb [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_oeb_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_oeb_SHIFT 0 /*************************************************************************** *DRIVE_PAD_CTL - SSTL pad drive characteristics control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: reserved0 [31:06] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_reserved0_MASK 0xffffffc0 #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_reserved0_SHIFT 6 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: rt60b_ddr_read_enb [05:05] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_ddr_read_enb_MASK 0x00000020 #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_ddr_read_enb_SHIFT 5 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: rt60b [04:04] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_MASK 0x00000010 #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_rt60b_SHIFT 4 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: sel_sstl18 [03:03] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_sel_sstl18_MASK 0x00000008 #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_sel_sstl18_SHIFT 3 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: seltxdrv_ci [02:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_seltxdrv_ci_MASK 0x00000004 #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_seltxdrv_ci_SHIFT 2 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: selrxdrv [01:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_selrxdrv_MASK 0x00000002 #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_selrxdrv_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: DRIVE_PAD_CTL :: slew [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_slew_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_slew_SHIFT 0 /*************************************************************************** *CLOCK_PAD_DISABLE - Clock pad disable register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: CLOCK_PAD_DISABLE :: reserved0 [31:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE_reserved0_MASK 0xfffffffe #define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE_reserved0_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: CLOCK_PAD_DISABLE :: clk_pad_dis [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE_clk_pad_dis_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_PAD_DISABLE_clk_pad_dis_SHIFT 0 /*************************************************************************** *WR_PREAMBLE_MODE - Write cycle preamble control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: reserved0 [31:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_reserved0_MASK 0xfffffffe #define BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_reserved0_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: WR_PREAMBLE_MODE :: mode [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_mode_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE_mode_SHIFT 0 /*************************************************************************** *CLOCK_REG_CONTROL - Clock Regulator control register ***************************************************************************/ /* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: reserved0 [31:02] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_reserved0_MASK 0xfffffffc #define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_reserved0_SHIFT 2 /* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: half_power [01:01] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_half_power_MASK 0x00000002 #define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_half_power_SHIFT 1 /* DDR23_PHY_BYTE_LANE_1 :: CLOCK_REG_CONTROL :: pwrdn [00:00] */ #define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_MASK 0x00000001 #define BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_SHIFT 0 #endif /* #ifndef BCHP_DDR23_PHY_BYTE_LANE_0_H__ */ /* End of File */ ././@LongLink0000000000000000000000000000015400000000000011565 Lustar rootrootcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode_mb_0.hcrystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_decode0000644000175000017500000002122111610313111030757 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_decode_mb_0.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:04p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:33 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_decode_mb_0.h $ * * Hydra_Software_Devel/1 7/17/09 8:04p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DECODE_MB_0_H__ #define BCHP_DECODE_MB_0_H__ /*************************************************************************** *DECODE_MB_0 ***************************************************************************/ #define BCHP_DECODE_MB_0_REG_MB_CTL 0x00800740 /* Decode Macroblock Control */ #define BCHP_DECODE_MB_0_REG_MB_END 0x0080075c /* REG_MB_END */ /*************************************************************************** *REG_MB_CTL - Decode Macroblock Control ***************************************************************************/ /* union - case WRITE [31:00] */ /* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: reserved0 [31:28] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_reserved0_MASK 0xf0000000 #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_reserved0_SHIFT 28 /* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: FCM [27:26] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_FCM_MASK 0x0c000000 #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_FCM_SHIFT 26 /* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: Type [25:24] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Type_MASK 0x03000000 #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Type_SHIFT 24 /* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: reserved1 [23:20] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_reserved1_MASK 0x00f00000 #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_reserved1_SHIFT 20 /* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: Intra_MB [19:19] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Intra_MB_MASK 0x00080000 #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Intra_MB_SHIFT 19 /* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: Mbaff [18:18] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Mbaff_MASK 0x00040000 #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Mbaff_SHIFT 18 /* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: Top [17:17] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Top_MASK 0x00020000 #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Top_SHIFT 17 /* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: Fld [16:16] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Fld_MASK 0x00010000 #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Fld_SHIFT 16 /* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: reserved2 [15:15] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_reserved2_MASK 0x00008000 #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_reserved2_SHIFT 15 /* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: YdestMB [14:08] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_YdestMB_MASK 0x00007f00 #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_YdestMB_SHIFT 8 /* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: Rv [07:07] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Rv_MASK 0x00000080 #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_Rv_SHIFT 7 /* DECODE_MB_0 :: REG_MB_CTL :: WRITE :: XdestMB [06:00] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_XdestMB_MASK 0x0000007f #define BCHP_DECODE_MB_0_REG_MB_CTL_WRITE_XdestMB_SHIFT 0 /* union - case READ [31:00] */ /* DECODE_MB_0 :: REG_MB_CTL :: READ :: reserved0 [31:15] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_reserved0_MASK 0xffff8000 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_reserved0_SHIFT 15 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: QRdyA [14:14] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QRdyA_MASK 0x00004000 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QRdyA_SHIFT 14 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: QEmptyA [13:13] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QEmptyA_MASK 0x00002000 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QEmptyA_SHIFT 13 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: QMBendA [12:12] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QMBendA_MASK 0x00001000 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QMBendA_SHIFT 12 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: QRdyB [11:11] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QRdyB_MASK 0x00000800 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QRdyB_SHIFT 11 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: QEmptyB [10:10] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QEmptyB_MASK 0x00000400 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QEmptyB_SHIFT 10 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: QMBendB [09:09] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QMBendB_MASK 0x00000200 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QMBendB_SHIFT 9 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: IntraRdy [08:08] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IntraRdy_MASK 0x00000100 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IntraRdy_SHIFT 8 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: IntraEmpty [07:07] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IntraEmpty_MASK 0x00000080 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IntraEmpty_SHIFT 7 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: IntraMBend [06:06] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IntraMBend_MASK 0x00000040 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IntraMBend_SHIFT 6 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: IXformRdy [05:05] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IXformRdy_MASK 0x00000020 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IXformRdy_SHIFT 5 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: IXformEmpty [04:04] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IXformEmpty_MASK 0x00000010 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IXformEmpty_SHIFT 4 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: IXformMBend [03:03] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IXformMBend_MASK 0x00000008 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IXformMBend_SHIFT 3 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: QRdy [02:02] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QRdy_MASK 0x00000004 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_QRdy_SHIFT 2 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: XRdy [01:01] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_XRdy_MASK 0x00000002 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_XRdy_SHIFT 1 /* DECODE_MB_0 :: REG_MB_CTL :: READ :: IRdy [00:00] */ #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IRdy_MASK 0x00000001 #define BCHP_DECODE_MB_0_REG_MB_CTL_READ_IRdy_SHIFT 0 /*************************************************************************** *REG_MB_END - REG_MB_END ***************************************************************************/ /* DECODE_MB_0 :: REG_MB_END :: reserved0 [31:00] */ #define BCHP_DECODE_MB_0_REG_MB_END_reserved0_MASK 0xffffffff #define BCHP_DECODE_MB_0_REG_MB_END_reserved0_SHIFT 0 #endif /* #ifndef BCHP_DECODE_MB_0_H__ */ /* End of File */ crystalhd-0.0~git20110715.fdd2f19/include/flea/70015/magnum/basemodules/chp/70015/rdb/a0/bchp_dnr.h0000644000175000017500000007754111610313111030565 0ustar andresandres/*************************************************************************** * Copyright (c) 1999-2009, Broadcom Corporation * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . ********************************************************************** * * $brcm_Workfile: bchp_dnr.h $ * $brcm_Revision: Hydra_Software_Devel/1 $ * $brcm_Date: 7/17/09 8:07p $ * * Module Description: * DO NOT EDIT THIS FILE DIRECTLY * * This module was generated magically with RDB from a source description * file. You must edit the source file for changes to be made to this file. * * * Date: Generated on Fri Jul 17 19:42:06 2009 * MD5 Checksum 2914699efc3fb3edefca5cb4f4f38b34 * * Compiled with: RDB Utility combo_header.pl * RDB Parser 3.0 * unknown unknown * Perl Interpreter 5.008008 * Operating System linux * * Revision History: * * $brcm_Log: /magnum/basemodules/chp/70015/rdb/a0/bchp_dnr.h $ * * Hydra_Software_Devel/1 7/17/09 8:07p albertl * PR56880: Initial revision. * ***************************************************************************/ #ifndef BCHP_DNR_H__ #define BCHP_DNR_H__ /*************************************************************************** *DNR - Digital Noise Reduction Registers ***************************************************************************/ #define BCHP_DNR_REVISION 0x00540400 /* Digital Noise Reduction (DNR) Revision ID */ #define BCHP_DNR_DNR_TOP_CTRL 0x00540404 /* DNR Top Level Control */ #define BCHP_DNR_LINE_STORE_CONFIG 0x00540408 /* Line Store Configuration */ #define BCHP_DNR_SRC_PIC_SIZE 0x0054040c /* Source Picture Size */ #define BCHP_DNR_SRC_SCAN_SETTING 0x00540410 /* Source Scan Setting */ #define BCHP_DNR_BNR_CTRL 0x00540414 /* Block Noise Reduction Control */ #define BCHP_DNR_VBNR_CONFIG 0x00540418 /* Vertical Block Noise Reduction Configuration */ #define BCHP_DNR_HBNR_CONFIG 0x0054041c /* Horizontal Block Noise Reduction Configuration */ #define BCHP_DNR_MNR_CTRL 0x00540420 /* Mosquito Noise Reduction Control */ #define BCHP_DNR_MNR_CONFIG 0x00540424 /* Mosquito Noise Reduction Configuration */ #define BCHP_DNR_EXT_FILT_CTRL 0x00540428 /* Extreme Filter Control */ #define BCHP_DNR_EXT_FILT_CONFIG 0x0054042c /* Extreme Filter Configuration */ #define BCHP_DNR_FILT_EFFECT_STATUS 0x00540430 /* DNR Filters Effect Status */ #define BCHP_DNR_BVB_IN_STATUS 0x00540434 /* DNR BVB Input Status */ #define BCHP_DNR_BVB_IN_STATUS_CLEAR 0x00540438 /* DNR BVB Input Status Clear */ #define BCHP_DNR_SCRATCH_REGISTER 0x0054043c /* DNR Scratch Register */ #define BCHP_DNR_DNR_DEMO_SETTING 0x00540440 /* DNR Demo Setting */ #define BCHP_DNR_DCR_CTRL 0x00540480 /* Digital Contour Removal Control */ #define BCHP_DNR_DCR_FILT_LIMIT 0x00540484 /* DCR Filtering Limits */ #define BCHP_DNR_DCR_FILT_CONFIG 0x00540488 /* DCR Filtering Configuration */ #define BCHP_DNR_DCR_DITH_ORDER_PATTERN 0x00540490 /* DCR Ordered Dither Pattern Control */ #define BCHP_DNR_DCR_DITH_ORDER_VALUE 0x00540494 /* DCR Ordered Dither Value */ #define BCHP_DNR_DCR_DITH_RANDOM_PATTERN 0x00540498 /* DCR Random Dither Pattern Control */ #define BCHP_DNR_DCR_DITH_RANDOM_VALUE 0x0054049c /* DCR Random Dither Values */ #define BCHP_DNR_DCR_DITH_OUT_CTRL 0x005404a0 /* DCR Dither Output Control */ /*************************************************************************** *REVISION - Digital Noise Reduction (DNR) Revision ID ***************************************************************************/ /* DNR :: REVISION :: reserved0 [31:16] */ #define BCHP_DNR_REVISION_reserved0_MASK 0xffff0000 #define BCHP_DNR_REVISION_reserved0_SHIFT 16 /* DNR :: REVISION :: MAJOR [15:08] */ #define BCHP_DNR_REVISION_MAJOR_MASK 0x0000ff00 #define BCHP_DNR_REVISION_MAJOR_SHIFT 8 /* DNR :: REVISION :: MINOR [07:00] */ #define BCHP_DNR_REVISION_MINOR_MASK 0x000000ff #define BCHP_DNR_REVISION_MINOR_SHIFT 0 /*************************************************************************** *DNR_TOP_CTRL - DNR Top Level Control ***************************************************************************/ /* DNR :: DNR_TOP_CTRL :: reserved0 [31:02] */ #define BCHP_DNR_DNR_TOP_CTRL_reserved0_MASK 0xfffffffc #define BCHP_DNR_DNR_TOP_CTRL_reserved0_SHIFT 2 /* DNR :: DNR_TOP_CTRL :: DNR_DEMO_ENABLE [01:01] */ #define BCHP_DNR_DNR_TOP_CTRL_DNR_DEMO_ENABLE_MASK 0x00000002 #define BCHP_DNR_DNR_TOP_CTRL_DNR_DEMO_ENABLE_SHIFT 1 /* DNR :: DNR_TOP_CTRL :: DNR_ENABLE [00:00] */ #define BCHP_DNR_DNR_TOP_CTRL_DNR_ENABLE_MASK 0x00000001 #define BCHP_DNR_DNR_TOP_CTRL_DNR_ENABLE_SHIFT 0 #define BCHP_DNR_DNR_TOP_CTRL_DNR_ENABLE_DISABLE 0 #define BCHP_DNR_DNR_TOP_CTRL_DNR_ENABLE_ENABLE 1 /*************************************************************************** *LINE_STORE_CONFIG - Line Store Configuration ***************************************************************************/ /* DNR :: LINE_STORE_CONFIG :: reserved0 [31:17] */ #define BCHP_DNR_LINE_STORE_CONFIG_reserved0_MASK 0xfffe0000 #define BCHP_DNR_LINE_STORE_CONFIG_reserved0_SHIFT 17 /* DNR :: LINE_STORE_CONFIG :: LS_MODE [16:16] */ #define BCHP_DNR_LINE_STORE_CONFIG_LS_MODE_MASK 0x00010000 #define BCHP_DNR_LINE_STORE_CONFIG_LS_MODE_SHIFT 16 #define BCHP_DNR_LINE_STORE_CONFIG_LS_MODE_SD 0 #define BCHP_DNR_LINE_STORE_CONFIG_LS_MODE_HD 1 /* DNR :: LINE_STORE_CONFIG :: reserved1 [15:00] */ #define BCHP_DNR_LINE_STORE_CONFIG_reserved1_MASK 0x0000ffff #define BCHP_DNR_LINE_STORE_CONFIG_reserved1_SHIFT 0 /*************************************************************************** *SRC_PIC_SIZE - Source Picture Size ***************************************************************************/ /* DNR :: SRC_PIC_SIZE :: reserved0 [31:27] */ #define BCHP_DNR_SRC_PIC_SIZE_reserved0_MASK 0xf8000000 #define BCHP_DNR_SRC_PIC_SIZE_reserved0_SHIFT 27 /* DNR :: SRC_PIC_SIZE :: HSIZE [26:16] */ #define BCHP_DNR_SRC_PIC_SIZE_HSIZE_MASK 0x07ff0000 #define BCHP_DNR_SRC_PIC_SIZE_HSIZE_SHIFT 16 /* DNR :: SRC_PIC_SIZE :: reserved1 [15:11] */ #define BCHP_DNR_SRC_PIC_SIZE_reserved1_MASK 0x0000f800 #define BCHP_DNR_SRC_PIC_SIZE_reserved1_SHIFT 11 /* DNR :: SRC_PIC_SIZE :: VSIZE [10:00] */ #define BCHP_DNR_SRC_PIC_SIZE_VSIZE_MASK 0x000007ff #define BCHP_DNR_SRC_PIC_SIZE_VSIZE_SHIFT 0 /*************************************************************************** *SRC_SCAN_SETTING - Source Scan Setting ***************************************************************************/ /* DNR :: SRC_SCAN_SETTING :: reserved0 [31:19] */ #define BCHP_DNR_SRC_SCAN_SETTING_reserved0_MASK 0xfff80000 #define BCHP_DNR_SRC_SCAN_SETTING_reserved0_SHIFT 19 /* DNR :: SRC_SCAN_SETTING :: H_OFFSET [18:16] */ #define BCHP_DNR_SRC_SCAN_SETTING_H_OFFSET_MASK 0x00070000 #define BCHP_DNR_SRC_SCAN_SETTING_H_OFFSET_SHIFT 16 /* DNR :: SRC_SCAN_SETTING :: reserved1 [15:11] */ #define BCHP_DNR_SRC_SCAN_SETTING_reserved1_MASK 0x0000f800 #define BCHP_DNR_SRC_SCAN_SETTING_reserved1_SHIFT 11 /* DNR :: SRC_SCAN_SETTING :: V_OFFSET [10:08] */ #define BCHP_DNR_SRC_SCAN_SETTING_V_OFFSET_MASK 0x00000700 #define BCHP_DNR_SRC_SCAN_SETTING_V_OFFSET_SHIFT 8 /* DNR :: SRC_SCAN_SETTING :: reserved2 [07:02] */ #define BCHP_DNR_SRC_SCAN_SETTING_reserved2_MASK 0x000000fc #define BCHP_DNR_SRC_SCAN_SETTING_reserved2_SHIFT 2 /* DNR :: SRC_SCAN_SETTING :: SRC_FORMAT [01:01] */ #define BCHP_DNR_SRC_SCAN_SETTING_SRC_FORMAT_MASK 0x00000002 #define BCHP_DNR_SRC_SCAN_SETTING_SRC_FORMAT_SHIFT 1 #define BCHP_DNR_SRC_SCAN_SETTING_SRC_FORMAT_FIELD 0 #define BCHP_DNR_SRC_SCAN_SETTING_SRC_FORMAT_FRAME 1 /* DNR :: SRC_SCAN_SETTING :: SRC_FIELD_ID [00:00] */ #define BCHP_DNR_SRC_SCAN_SETTING_SRC_FIELD_ID_MASK 0x00000001 #define BCHP_DNR_SRC_SCAN_SETTING_SRC_FIELD_ID_SHIFT 0 #define BCHP_DNR_SRC_SCAN_SETTING_SRC_FIELD_ID_TOP 0 #define BCHP_DNR_SRC_SCAN_SETTING_SRC_FIELD_ID_BOTTOM 1 /*************************************************************************** *BNR_CTRL - Block Noise Reduction Control ***************************************************************************/ /* DNR :: BNR_CTRL :: reserved0 [31:02] */ #define BCHP_DNR_BNR_CTRL_reserved0_MASK 0xfffffffc #define BCHP_DNR_BNR_CTRL_reserved0_SHIFT 2 /* DNR :: BNR_CTRL :: HBNR_ENABLE [01:01] */ #define BCHP_DNR_BNR_CTRL_HBNR_ENABLE_MASK 0x00000002 #define BCHP_DNR_BNR_CTRL_HBNR_ENABLE_SHIFT 1 #define BCHP_DNR_BNR_CTRL_HBNR_ENABLE_DISABLE 0 #define BCHP_DNR_BNR_CTRL_HBNR_ENABLE_ENABLE 1 /* DNR :: BNR_CTRL :: VBNR_ENABLE [00:00] */ #define BCHP_DNR_BNR_CTRL_VBNR_ENABLE_MASK 0x00000001 #define BCHP_DNR_BNR_CTRL_VBNR_ENABLE_SHIFT 0 #define BCHP_DNR_BNR_CTRL_VBNR_ENABLE_DISABLE 0 #define BCHP_DNR_BNR_CTRL_VBNR_ENABLE_ENABLE 1 /*************************************************************************** *VBNR_CONFIG - Vertical Block Noise Reduction Configuration ***************************************************************************/ /* DNR :: VBNR_CONFIG :: reserved0 [31:30] */ #define BCHP_DNR_VBNR_CONFIG_reserved0_MASK 0xc0000000 #define BCHP_DNR_VBNR_CONFIG_reserved0_SHIFT 30 /* DNR :: VBNR_CONFIG :: VBNR_LR_LIMIT [29:24] */ #define BCHP_DNR_VBNR_CONFIG_VBNR_LR_LIMIT_MASK 0x3f000000 #define BCHP_DNR_VBNR_CONFIG_VBNR_LR_LIMIT_SHIFT 24 /* DNR :: VBNR_CONFIG :: reserved1 [23:20] */ #define BCHP_DNR_VBNR_CONFIG_reserved1_MASK 0x00f00000 #define BCHP_DNR_VBNR_CONFIG_reserved1_SHIFT 20 /* DNR :: VBNR_CONFIG :: VBNR_REL [19:16] */ #define BCHP_DNR_VBNR_CONFIG_VBNR_REL_MASK 0x000f0000 #define BCHP_DNR_VBNR_CONFIG_VBNR_REL_SHIFT 16 /* DNR :: VBNR_CONFIG :: reserved2 [15:09] */ #define BCHP_DNR_VBNR_CONFIG_reserved2_MASK 0x0000fe00 #define BCHP_DNR_VBNR_CONFIG_reserved2_SHIFT 9 /* DNR :: VBNR_CONFIG :: VBNR_LIMIT [08:00] */ #define BCHP_DNR_VBNR_CONFIG_VBNR_LIMIT_MASK 0x000001ff #define BCHP_DNR_VBNR_CONFIG_VBNR_LIMIT_SHIFT 0 /*************************************************************************** *HBNR_CONFIG - Horizontal Block Noise Reduction Configuration ***************************************************************************/ /* DNR :: HBNR_CONFIG :: HBNR_SMALL_GRID [31:31] */ #define BCHP_DNR_HBNR_CONFIG_HBNR_SMALL_GRID_MASK 0x80000000 #define BCHP_DNR_HBNR_CONFIG_HBNR_SMALL_GRID_SHIFT 31 /* DNR :: HBNR_CONFIG :: reserved0 [30:20] */ #define BCHP_DNR_HBNR_CONFIG_reserved0_MASK 0x7ff00000 #define BCHP_DNR_HBNR_CONFIG_reserved0_SHIFT 20 /* DNR :: HBNR_CONFIG :: HBNR_REL [19:16] */ #define BCHP_DNR_HBNR_CONFIG_HBNR_REL_MASK 0x000f0000 #define BCHP_DNR_HBNR_CONFIG_HBNR_REL_SHIFT 16 /* DNR :: HBNR_CONFIG :: reserved1 [15:09] */ #define BCHP_DNR_HBNR_CONFIG_reserved1_MASK 0x0000fe00 #define BCHP_DNR_HBNR_CONFIG_reserved1_SHIFT 9 /* DNR :: HBNR_CONFIG :: HBNR_LIMIT [08:00] */ #define BCHP_DNR_HBNR_CONFIG_HBNR_LIMIT_MASK 0x000001ff #define BCHP_DNR_HBNR_CONFIG_HBNR_LIMIT_SHIFT 0 /*************************************************************************** *MNR_CTRL - Mosquito Noise Reduction Control ***************************************************************************/ /* DNR :: MNR_CTRL :: reserved0 [31:01] */ #define BCHP_DNR_MNR_CTRL_reserved0_MASK 0xfffffffe #define BCHP_DNR_MNR_CTRL_reserved0_SHIFT 1 /* DNR :: MNR_CTRL :: MNR_ENABLE [00:00] */ #define BCHP_DNR_MNR_CTRL_MNR_ENABLE_MASK 0x00000001 #define BCHP_DNR_MNR_CTRL_MNR_ENABLE_SHIFT 0 #define BCHP_DNR_MNR_CTRL_MNR_ENABLE_DISABLE 0 #define BCHP_DNR_MNR_CTRL_MNR_ENABLE_ENABLE 1 /*************************************************************************** *MNR_CONFIG - Mosquito Noise Reduction Configuration ***************************************************************************/ /* DNR :: MNR_CONFIG :: MNR_SPOT [31:31] */ #define BCHP_DNR_MNR_CONFIG_MNR_SPOT_MASK 0x80000000 #define BCHP_DNR_MNR_CONFIG_MNR_SPOT_SHIFT 31 /* DNR :: MNR_CONFIG :: reserved0 [30:27] */ #define BCHP_DNR_MNR_CONFIG_reserved0_MASK 0x78000000 #define BCHP_DNR_MNR_CONFIG_reserved0_SHIFT 27 /* DNR :: MNR_CONFIG :: MNR_MERGE [26:24] */ #define BCHP_DNR_MNR_CONFIG_MNR_MERGE_MASK 0x07000000 #define BCHP_DNR_MNR_CONFIG_MNR_MERGE_SHIFT 24 /* DNR :: MNR_CONFIG :: reserved1 [23:23] */ #define BCHP_DNR_MNR_CONFIG_reserved1_MASK 0x00800000 #define BCHP_DNR_MNR_CONFIG_reserved1_SHIFT 23 /* DNR :: MNR_CONFIG :: MNR_REL [22:16] */ #define BCHP_DNR_MNR_CONFIG_MNR_REL_MASK 0x007f0000 #define BCHP_DNR_MNR_CONFIG_MNR_REL_SHIFT 16 /* DNR :: MNR_CONFIG :: MNR_BLOCK_BOUND [15:15] */ #define BCHP_DNR_MNR_CONFIG_MNR_BLOCK_BOUND_MASK 0x00008000 #define BCHP_DNR_MNR_CONFIG_MNR_BLOCK_BOUND_SHIFT 15 /* DNR :: MNR_CONFIG :: reserved2 [14:09] */ #define BCHP_DNR_MNR_CONFIG_reserved2_MASK 0x00007e00 #define BCHP_DNR_MNR_CONFIG_reserved2_SHIFT 9 /* DNR :: MNR_CONFIG :: MNR_LIMIT [08:00] */ #define BCHP_DNR_MNR_CONFIG_MNR_LIMIT_MASK 0x000001ff #define BCHP_DNR_MNR_CONFIG_MNR_LIMIT_SHIFT 0 /*************************************************************************** *EXT_FILT_CTRL - Extreme Filter Control ***************************************************************************/ /* DNR :: EXT_FILT_CTRL :: reserved0 [31:01] */ #define BCHP_DNR_EXT_FILT_CTRL_reserved0_MASK 0xfffffffe #define BCHP_DNR_EXT_FILT_CTRL_reserved0_SHIFT 1 /* DNR :: EXT_FILT_CTRL :: ENABLE [00:00] */ #define BCHP_DNR_EXT_FILT_CTRL_ENABLE_MASK 0x00000001 #define BCHP_DNR_EXT_FILT_CTRL_ENABLE_SHIFT 0 #define BCHP_DNR_EXT_FILT_CTRL_ENABLE_DISABLE 0 #define BCHP_DNR_EXT_FILT_CTRL_ENABLE_ENABLE 1 /*************************************************************************** *EXT_FILT_CONFIG - Extreme Filter Configuration ***************************************************************************/ /* DNR :: EXT_FILT_CONFIG :: reserved0 [31:01] */ #define BCHP_DNR_EXT_FILT_CONFIG_reserved0_MASK 0xfffffffe #define BCHP_DNR_EXT_FILT_CONFIG_reserved0_SHIFT 1 /* DNR :: EXT_FILT_CONFIG :: CONFIG [00:00] */ #define BCHP_DNR_EXT_FILT_CONFIG_CONFIG_MASK 0x00000001 #define BCHP_DNR_EXT_FILT_CONFIG_CONFIG_SHIFT 0 /*************************************************************************** *FILT_EFFECT_STATUS - DNR Filters Effect Status ***************************************************************************/ /* DNR :: FILT_EFFECT_STATUS :: FILT_EFFECT [31:00] */ #define BCHP_DNR_FILT_EFFECT_STATUS_FILT_EFFECT_MASK 0xffffffff #define BCHP_DNR_FILT_EFFECT_STATUS_FILT_EFFECT_SHIFT 0 /*************************************************************************** *BVB_IN_STATUS - DNR BVB Input Status ***************************************************************************/ /* DNR :: BVB_IN_STATUS :: reserved0 [31:05] */ #define BCHP_DNR_BVB_IN_STATUS_reserved0_MASK 0xffffffe0 #define BCHP_DNR_BVB_IN_STATUS_reserved0_SHIFT 5 /* DNR :: BVB_IN_STATUS :: MISSING_SYNC [04:04] */ #define BCHP_DNR_BVB_IN_STATUS_MISSING_SYNC_MASK 0x00000010 #define BCHP_DNR_BVB_IN_STATUS_MISSING_SYNC_SHIFT 4 /* DNR :: BVB_IN_STATUS :: LONG_SOURCE [03:03] */ #define BCHP_DNR_BVB_IN_STATUS_LONG_SOURCE_MASK 0x00000008 #define BCHP_DNR_BVB_IN_STATUS_LONG_SOURCE_SHIFT 3 /* DNR :: BVB_IN_STATUS :: SHORT_SOURCE [02:02] */ #define BCHP_DNR_BVB_IN_STATUS_SHORT_SOURCE_MASK 0x00000004 #define BCHP_DNR_BVB_IN_STATUS_SHORT_SOURCE_SHIFT 2 /* DNR :: BVB_IN_STATUS :: LONG_LINE [01:01] */ #define BCHP_DNR_BVB_IN_STATUS_LONG_LINE_MASK 0x00000002 #define BCHP_DNR_BVB_IN_STATUS_LONG_LINE_SHIFT 1 /* DNR :: BVB_IN_STATUS :: SHORT_LINE [00:00] */ #define BCHP_DNR_BVB_IN_STATUS_SHORT_LINE_MASK 0x00000001 #define BCHP_DNR_BVB_IN_STATUS_SHORT_LINE_SHIFT 0 /*************************************************************************** *BVB_IN_STATUS_CLEAR - DNR BVB Input Status Clear ***************************************************************************/ /* DNR :: BVB_IN_STATUS_CLEAR :: reserved0 [31:05] */ #define BCHP_DNR_BVB_IN_STATUS_CLEAR_reserved0_MASK 0xffffffe0 #define BCHP_DNR_BVB_IN_STATUS_CLEAR_reserved0_SHIFT 5 /* DNR :: BVB_IN_STATUS_CLEAR :: MISSING_SYNC [04:04] */ #define BCHP_DNR_BVB_IN_STATUS_CLEAR_MISSING_SYNC_MASK 0x00000010 #define BCHP_DNR_BVB_IN_STATUS_CLEAR_MISSING_SYNC_SHIFT 4 /* DNR :: BVB_IN_STATUS_CLEAR :: LONG_SOURCE [03:03] */ #define BCHP_DNR_BVB_IN_STATUS_CLEAR_LONG_SOURCE_MASK 0x00000008 #define BCHP_DNR_BVB_IN_STATUS_CLEAR_LONG_SOURCE_SHIFT 3 /* DNR :: BVB_IN_STATUS_CLEAR :: SHORT_SOURCE [02:02] */ #define BCHP_DNR_BVB_IN_STATUS_CLEAR_SHORT_SOURCE_MASK 0x00000004 #define BCHP_DNR_BVB_IN_STATUS_CLEAR_SHORT_SOURCE_SHIFT 2 /* DNR :: BVB_IN_STATUS_CLEAR :: LONG_LINE [01:01] */ #define BCHP_DNR_BVB_IN_STATUS_CLEAR_LONG_LINE_MASK 0x00000002 #define BCHP_DNR_BVB_IN_STATUS_CLEAR_LONG_LINE_SHIFT 1 /* DNR :: BVB_IN_STATUS_CLEAR :: SHORT_LINE [00:00] */ #define BCHP_DNR_BVB_IN_STATUS_CLEAR_SHORT_LINE_MASK 0x00000001 #define BCHP_DNR_BVB_IN_STATUS_CLEAR_SHORT_LINE_SHIFT 0 /*************************************************************************** *SCRATCH_REGISTER - DNR Scratch Register ***************************************************************************/ /* DNR :: SCRATCH_REGISTER :: reserved0 [31:16] */ #define BCHP_DNR_SCRATCH_REGISTER_reserved0_MASK 0xffff0000 #define BCHP_DNR_SCRATCH_REGISTER_reserved0_SHIFT 16 /* DNR :: SCRATCH_REGISTER :: VALUE [15:00] */ #define BCHP_DNR_SCRATCH_REGISTER_VALUE_MASK 0x0000ffff #define BCHP_DNR_SCRATCH_REGISTER_VALUE_SHIFT 0 /*************************************************************************** *DNR_DEMO_SETTING - DNR Demo Setting ***************************************************************************/ /* DNR :: DNR_DEMO_SETTING :: reserved0 [31:17] */ #define BCHP_DNR_DNR_DEMO_SETTING_reserved0_MASK 0xfffe0000 #define BCHP_DNR_DNR_DEMO_SETTING_reserved0_SHIFT 17 /* DNR :: DNR_DEMO_SETTING :: DEMO_L_R [16:16] */ #define BCHP_DNR_DNR_DEMO_SETTING_DEMO_L_R_MASK 0x00010000 #define BCHP_DNR_DNR_DEMO_SETTING_DEMO_L_R_SHIFT 16 #define BCHP_DNR_DNR_DEMO_SETTING_DEMO_L_R_LEFT 1 #define BCHP_DNR_DNR_DEMO_SETTING_DEMO_L_R_RIGHT 0 /* DNR :: DNR_DEMO_SETTING :: reserved1 [15:11] */ #define BCHP_DNR_DNR_DEMO_SETTING_reserved1_MASK 0x0000f800 #define BCHP_DNR_DNR_DEMO_SETTING_reserved1_SHIFT 11 /* DNR :: DNR_DEMO_SETTING :: DEMO_BOUNDARY [10:00] */ #define BCHP_DNR_DNR_DEMO_SETTING_DEMO_BOUNDARY_MASK 0x000007ff #define BCHP_DNR_DNR_DEMO_SETTING_DEMO_BOUNDARY_SHIFT 0 /*************************************************************************** *DCR_CTRL - Digital Contour Removal Control ***************************************************************************/ /* DNR :: DCR_CTRL :: reserved0 [31:02] */ #define BCHP_DNR_DCR_CTRL_reserved0_MASK 0xfffffffc #define BCHP_DNR_DCR_CTRL_reserved0_SHIFT 2 /* DNR :: DCR_CTRL :: DITH_ENABLE [01:01] */ #define BCHP_DNR_DCR_CTRL_DITH_ENABLE_MASK 0x00000002 #define BCHP_DNR_DCR_CTRL_DITH_ENABLE_SHIFT 1 #define BCHP_DNR_DCR_CTRL_DITH_ENABLE_DISABLE 0 #define BCHP_DNR_DCR_CTRL_DITH_ENABLE_ENABLE 1 /* DNR :: DCR_CTRL :: FILT_ENABLE [00:00] */ #define BCHP_DNR_DCR_CTRL_FILT_ENABLE_MASK 0x00000001 #define BCHP_DNR_DCR_CTRL_FILT_ENABLE_SHIFT 0 #define BCHP_DNR_DCR_CTRL_FILT_ENABLE_DISABLE 0 #define BCHP_DNR_DCR_CTRL_FILT_ENABLE_ENABLE 1 /*************************************************************************** *DCR_FILT_LIMIT - DCR Filtering Limits ***************************************************************************/ /* DNR :: DCR_FILT_LIMIT :: reserved0 [31:28] */ #define BCHP_DNR_DCR_FILT_LIMIT_reserved0_MASK 0xf0000000 #define BCHP_DNR_DCR_FILT_LIMIT_reserved0_SHIFT 28 /* DNR :: DCR_FILT_LIMIT :: FILT_3_LIMIT [27:24] */ #define BCHP_DNR_DCR_FILT_LIMIT_FILT_3_LIMIT_MASK 0x0f000000 #define BCHP_DNR_DCR_FILT_LIMIT_FILT_3_LIMIT_SHIFT 24 /* DNR :: DCR_FILT_LIMIT :: reserved1 [23:20] */ #define BCHP_DNR_DCR_FILT_LIMIT_reserved1_MASK 0x00f00000 #define BCHP_DNR_DCR_FILT_LIMIT_reserved1_SHIFT 20 /* DNR :: DCR_FILT_LIMIT :: FILT_2_LIMIT [19:16] */ #define BCHP_DNR_DCR_FILT_LIMIT_FILT_2_LIMIT_MASK 0x000f0000 #define BCHP_DNR_DCR_FILT_LIMIT_FILT_2_LIMIT_SHIFT 16 /* DNR :: DCR_FILT_LIMIT :: reserved2 [15:12] */ #define BCHP_DNR_DCR_FILT_LIMIT_reserved2_MASK 0x0000f000 #define BCHP_DNR_DCR_FILT_LIMIT_reserved2_SHIFT 12 /* DNR :: DCR_FILT_LIMIT :: FILT_1_LIMIT [11:08] */ #define BCHP_DNR_DCR_FILT_LIMIT_FILT_1_LIMIT_MASK 0x00000f00 #define BCHP_DNR_DCR_FILT_LIMIT_FILT_1_LIMIT_SHIFT 8 /* DNR :: DCR_FILT_LIMIT :: reserved3 [07:04] */ #define BCHP_DNR_DCR_FILT_LIMIT_reserved3_MASK 0x000000f0 #define BCHP_DNR_DCR_FILT_LIMIT_reserved3_SHIFT 4 /* DNR :: DCR_FILT_LIMIT :: FILT_0_LIMIT [03:00] */ #define BCHP_DNR_DCR_FILT_LIMIT_FILT_0_LIMIT_MASK 0x0000000f #define BCHP_DNR_DCR_FILT_LIMIT_FILT_0_LIMIT_SHIFT 0 /*************************************************************************** *DCR_FILT_CONFIG - DCR Filtering Configuration ***************************************************************************/ /* DNR :: DCR_FILT_CONFIG :: reserved0 [31:11] */ #define BCHP_DNR_DCR_FILT_CONFIG_reserved0_MASK 0xfffff800 #define BCHP_DNR_DCR_FILT_CONFIG_reserved0_SHIFT 11 /* DNR :: DCR_FILT_CONFIG :: BRIGHT_2 [10:10] */ #define BCHP_DNR_DCR_FILT_CONFIG_BRIGHT_2_MASK 0x00000400 #define BCHP_DNR_DCR_FILT_CONFIG_BRIGHT_2_SHIFT 10 /* DNR :: DCR_FILT_CONFIG :: BRIGHT_1 [09:09] */ #define BCHP_DNR_DCR_FILT_CONFIG_BRIGHT_1_MASK 0x00000200 #define BCHP_DNR_DCR_FILT_CONFIG_BRIGHT_1_SHIFT 9 /* DNR :: DCR_FILT_CONFIG :: BRIGHT_0 [08:08] */ #define BCHP_DNR_DCR_FILT_CONFIG_BRIGHT_0_MASK 0x00000100 #define BCHP_DNR_DCR_FILT_CONFIG_BRIGHT_0_SHIFT 8 /* DNR :: DCR_FILT_CONFIG :: reserved1 [07:07] */ #define BCHP_DNR_DCR_FILT_CONFIG_reserved1_MASK 0x00000080 #define BCHP_DNR_DCR_FILT_CONFIG_reserved1_SHIFT 7 /* DNR :: DCR_FILT_CONFIG :: FILT_CLAMP [06:00] */ #define BCHP_DNR_DCR_FILT_CONFIG_FILT_CLAMP_MASK 0x0000007f #define BCHP_DNR_DCR_FILT_CONFIG_FILT_CLAMP_SHIFT 0 /*************************************************************************** *DCR_DITH_ORDER_PATTERN - DCR Ordered Dither Pattern Control ***************************************************************************/ /* DNR :: DCR_DITH_ORDER_PATTERN :: reserved0 [31:05] */ #define BCHP_DNR_DCR_DITH_ORDER_PATTERN_reserved0_MASK 0xffffffe0 #define BCHP_DNR_DCR_DITH_ORDER_PATTERN_reserved0_SHIFT 5 /* DNR :: DCR_DITH_ORDER_PATTERN :: ALTERNATE_Y [04:04] */ #define BCHP_DNR_DCR_DITH_ORDER_PATTERN_ALTERNATE_Y_MASK 0x00000010 #define BCHP_DNR_DCR_DITH_ORDER_PATTERN_ALTERNATE_Y_SHIFT 4 /* DNR :: DCR_DITH_ORDER_PATTERN :: ALTERNATE_X [03:03] */ #define BCHP_DNR_DCR_DITH_ORDER_PATTERN_ALTERNATE_X_MASK 0x00000008 #define BCHP_DNR_DCR_DITH_ORDER_PATTERN_ALTERNATE_X_SHIFT 3 /* DNR :: DCR_DITH_ORDER_PATTERN :: INVERT_Y [02:02] */ #define BCHP_DNR_DCR_DITH_ORDER_PATTERN_INVERT_Y_MASK 0x00000004 #define BCHP_DNR_DCR_DITH_ORDER_PATTERN_INVERT_Y_SHIFT 2 /* DNR :: DCR_DITH_ORDER_PATTERN :: INVERT_X [01:01] */ #define BCHP_DNR_DCR_DITH_ORDER_PATTERN_INVERT_X_MASK 0x00000002 #define BCHP_DNR_DCR_DITH_ORDER_PATTERN_INVERT_X_SHIFT 1 /* DNR :: DCR_DITH_ORDER_PATTERN :: AUTO_DITH [00:00] */ #define BCHP_DNR_DCR_DITH_ORDER_PATTERN_AUTO_DITH_MASK 0x00000001 #define BCHP_DNR_DCR_DITH_ORDER_PATTERN_AUTO_DITH_SHIFT 0 /*************************************************************************** *DCR_DITH_ORDER_VALUE - DCR Ordered Dither Value ***************************************************************************/ /* DNR :: DCR_DITH_ORDER_VALUE :: reserved0 [31:15] */ #define BCHP_DNR_DCR_DITH_ORDER_VALUE_reserved0_MASK 0xffff8000 #define BCHP_DNR_DCR_DITH_ORDER_VALUE_reserved0_SHIFT 15 /* DNR :: DCR_DITH_ORDER_VALUE :: ORDER_B [14:08] */ #define BCHP_DNR_DCR_DITH_ORDER_VALUE_ORDER_B_MASK 0x00007f00 #define BCHP_DNR_DCR_DITH_ORDER_VALUE_ORDER_B_SHIFT 8 /* DNR :: DCR_DITH_ORDER_VALUE :: reserved1 [07:07] */ #define BCHP_DNR_DCR_DITH_ORDER_VALUE_reserved1_MASK 0x00000080 #define BCHP_DNR_DCR_DITH_ORDER_VALUE_reserved1_SHIFT 7 /* DNR :: DCR_DITH_ORDER_VALUE :: ORDER_A [06:00] */ #define BCHP_DNR_DCR_DITH_ORDER_VALUE_ORDER_A_MASK 0x0000007f #define BCHP_DNR_DCR_DITH_ORDER_VALUE_ORDER_A_SHIFT 0 /*************************************************************************** *DCR_DITH_RANDOM_PATTERN - DCR Random Dither Pattern Control ***************************************************************************/ /* DNR :: DCR_DITH_RANDOM_PATTERN :: reserved0 [31:18] */ #define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_reserved0_MASK 0xfffc0000 #define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_reserved0_SHIFT 18 /* DNR :: DCR_DITH_RANDOM_PATTERN :: RNG_MODE [17:16] */ #define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_RNG_MODE_MASK 0x00030000 #define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_RNG_MODE_SHIFT 16 #define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_RNG_MODE_RUN 0 #define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_RNG_MODE_RNG_FIELD 1 #define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_RNG_MODE_RNG_FRAME 2 /* DNR :: DCR_DITH_RANDOM_PATTERN :: RNG_SEED [15:00] */ #define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_RNG_SEED_MASK 0x0000ffff #define BCHP_DNR_DCR_DITH_RANDOM_PATTERN_RNG_SEED_SHIFT 0 /*************************************************************************** *DCR_DITH_RANDOM_VALUE - DCR Random Dither Values ***************************************************************************/ /* DNR :: DCR_DITH_RANDOM_VALUE :: reserved0 [31:31] */ #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved0_MASK 0x80000000 #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved0_SHIFT 31 /* DNR :: DCR_DITH_RANDOM_VALUE :: RANDOM_D [30:24] */ #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_D_MASK 0x7f000000 #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_D_SHIFT 24 /* DNR :: DCR_DITH_RANDOM_VALUE :: reserved1 [23:23] */ #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved1_MASK 0x00800000 #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved1_SHIFT 23 /* DNR :: DCR_DITH_RANDOM_VALUE :: RANDOM_C [22:16] */ #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_C_MASK 0x007f0000 #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_C_SHIFT 16 /* DNR :: DCR_DITH_RANDOM_VALUE :: reserved2 [15:15] */ #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved2_MASK 0x00008000 #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved2_SHIFT 15 /* DNR :: DCR_DITH_RANDOM_VALUE :: RANDOM_B [14:08] */ #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_B_MASK 0x00007f00 #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_B_SHIFT 8 /* DNR :: DCR_DITH_RANDOM_VALUE :: reserved3 [07:07] */ #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved3_MASK 0x00000080 #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_reserved3_SHIFT 7 /* DNR :: DCR_DITH_RANDOM_VALUE :: RANDOM_A [06:00] */ #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_A_MASK 0x0000007f #define BCHP_DNR_DCR_DITH_RANDOM_VALUE_RANDOM_A_SHIFT 0 /*************************************************************************** *DCR_DITH_OUT_CTRL - DCR Dither Output Control ***************************************************************************/ /* DNR :: DCR_DITH_OUT_CTRL :: reserved0 [31:08] */ #define BCHP_DNR_DCR_DITH_OUT_CTRL_reserved0_MASK 0xffffff00 #define BCHP_DNR_DCR_DITH_OUT_CTRL_reserved0_SHIFT 8 /* DNR :: DCR_DITH_OUT_CTRL :: DITH_CLAMP [07:00] */ #define BCHP_DNR_DCR_DITH_OUT_CTRL_DITH_CLAMP_MASK 0x000000ff #define BCHP_DNR_DCR_DITH_OUT_CTRL_DITH_CLAMP_SHIFT 0 #endif /* #ifndef BCHP_DNR_H__ */ /* End of File */ crystalhd-0.0~git20110715.fdd2f19/include/libcrystalhd_version.h0000644000175000017500000000614211610313111023555 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_version.h * * Description: Version numbering for the driver use. * * AU * * HISTORY: * ******************************************************************** * This header is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This header is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this header. If not, see . *******************************************************************/ #ifndef _BC_DTS_VERSION_LNX_ #define _BC_DTS_VERSION_LNX_ // // The version format that we are adopting is // MajorVersion.MinorVersion.Revision // This will be the same for all the components. // // #define STRINGIFY_VERSION(MAJ,MIN,REV) STRINGIFIED_VERSION(MAJ,MIN,REV) #define STRINGIFIED_VERSION(MAJ,MIN,REV) #MAJ "." #MIN "." #REV #define STRINGIFY_VERSION_W(MAJ,MIN,REV) STRINGIFIED_VERSION_W(MAJ,MIN,REV) #define STRINGIFIED_VERSION_W(MAJ,MIN,REV) #MAJ "." #MIN "." #REV // // Product Version number is: // x.y.z.a // // x = Major release. 1 = Dozer, 2 = Dozer + Link // y = Minor release. Should increase +1 per "real" release. // z = Branch release. 0 for main branch. This is +1 per branch release. // a = Build number +1 per candidate release. Reset to 0 every "real" release. // // // Enabling Check-In rules enforcement 08092007 // #define INVALID_VERSION 0xFFFF /*========================== Common For All Components =================================*/ #define BRCM_MAJOR_VERSION 3 // Note: the driver doesn't currently use these defines, it has its own // version information (which should match) stored in bc_dts_glob_lnx.h #define DRIVER_MAJOR_VERSION BRCM_MAJOR_VERSION #define DRIVER_MINOR_VERSION 10 #define DRIVER_REVISION 0 #define RC_FILE_VERSION STRINGIFY_VERSION(DRIVER_MAJOR_VERSION,DRIVER_MINOR_VERSION,DRIVER_REVISION) ".0" /*======================= Device Interface Library ========================*/ #define DIL_MAJOR_VERSION BRCM_MAJOR_VERSION #define DIL_MINOR_VERSION 22 #define DIL_REVISION 0 #define DIL_RC_FILE_VERSION STRINGIFY_VERSION(DIL_MAJOR_VERSION,DIL_MINOR_VERSION,DIL_REVISION) /*========================== deconf utility ==============================*/ #define DECONF_MAJOR_VERSION BRCM_MAJOR_VERSION #define DECONF_MINOR_VERSION 9 #define DECONF_REVISION 18 #define DECONF_RC_FILE_VERSION STRINGIFY_VERSION(DIL_MAJOR_VERSION,DIL_MINOR_VERSION,DIL_REVISION) /*========================== Firmware ==============================*/ #define FW_MAJOR_VERSION BRCM_MAJOR_VERSION #define FW_MINOR_VERSION 60 #define FW_REVISION 39 #endif crystalhd-0.0~git20110715.fdd2f19/include/bc_dts_defs.h0000644000175000017500000004772011610313111021572 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: bc_dts_defs.h * * Description: Common definitions for all components. Only types * is allowed to be included from this file. * * AU * * HISTORY: * ******************************************************************** * This header is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This header is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this header. If not, see . *******************************************************************/ #ifndef _BC_DTS_DEFS_H_ #define _BC_DTS_DEFS_H_ /* BIT Mask */ #define BC_BIT(_x) (1 << (_x)) typedef enum _BC_STATUS { BC_STS_SUCCESS = 0, BC_STS_INV_ARG = 1, BC_STS_BUSY = 2, BC_STS_NOT_IMPL = 3, BC_STS_PGM_QUIT = 4, BC_STS_NO_ACCESS = 5, BC_STS_INSUFF_RES = 6, BC_STS_IO_ERROR = 7, BC_STS_NO_DATA = 8, BC_STS_VER_MISMATCH = 9, BC_STS_TIMEOUT = 10, BC_STS_FW_CMD_ERR = 11, BC_STS_DEC_NOT_OPEN = 12, BC_STS_ERR_USAGE = 13, BC_STS_IO_USER_ABORT = 14, BC_STS_IO_XFR_ERROR = 15, BC_STS_DEC_NOT_STARTED = 16, BC_STS_FWHEX_NOT_FOUND = 17, BC_STS_FMT_CHANGE = 18, BC_STS_HIF_ACCESS = 19, BC_STS_CMD_CANCELLED = 20, BC_STS_FW_AUTH_FAILED = 21, BC_STS_BOOTLOADER_FAILED = 22, BC_STS_CERT_VERIFY_ERROR = 23, BC_STS_DEC_EXIST_OPEN = 24, BC_STS_PENDING = 25, BC_STS_PWR_MGMT = 26, /* Must be the last one.*/ BC_STS_ERROR = -1 } BC_STATUS; typedef enum _BC_HW_STATE { BC_HW_RUNNING = 0, BC_HW_SUSPEND = 1, BC_HW_RESUME = 2 } BC_HW_STATE; /*------------------------------------------------------* * Registry Key Definitions * *------------------------------------------------------*/ #define BC_REG_KEY_MAIN_PATH "Software\\Broadcom\\MediaPC\\CrystalHD" #define BC_REG_KEY_FWPATH "FirmwareFilePath" #define BC_REG_KEY_SEC_OPT "DbgOptions" /* * Options: * * b[5] = Enable RSA KEY in EEPROM Support * b[6] = Enable Old PIB scheme. (0 = Use PIB with video scheme) * * b[12] = Enable send message to NotifyIcon * */ typedef enum _BC_SW_OPTIONS { BC_OPT_DOSER_OUT_ENCRYPT = BC_BIT(3), BC_OPT_LINK_OUT_ENCRYPT = BC_BIT(29), } BC_SW_OPTIONS; typedef struct _BC_REG_CONFIG{ uint32_t DbgOptions; } BC_REG_CONFIG; /*#if defined(__KERNEL__) || defined(__LINUX_USER__) */ #if defined(_WIN32) || defined(_WIN64) /* Align data structures */ #define ALIGN(x) __declspec(align(x)) #endif /* mode * b[0]..b[7] = _DtsDeviceOpenMode * b[8] = Load new FW * b[9] = Load file play back FW * b[10] = Disk format (0 for HD DVD and 1 for BLU ray) * b[11]-b[15] = default output resolution * b[16] = Skip TX CPB Buffer Check * b[17] = Adaptive Output Encrypt/Scramble Scheme * b[18]-b[31] = reserved for future use */ /* To allow multiple apps to open the device. */ enum _DtsDeviceOpenMode { DTS_PLAYBACK_MODE = 0, DTS_DIAG_MODE, DTS_MONITOR_MODE, DTS_HWINIT_MODE }; /* To enable the filter to selectively enable/disable fixes or erratas */ enum _DtsDeviceFixMode { DTS_LOAD_NEW_FW = BC_BIT(8), DTS_LOAD_FILE_PLAY_FW = BC_BIT(9), DTS_DISK_FMT_BD = BC_BIT(10), /* b[11]-b[15] : Default output resolution */ DTS_SKIP_TX_CHK_CPB = BC_BIT(16), DTS_ADAPTIVE_OUTPUT_PER = BC_BIT(17), DTS_INTELLIMAP = BC_BIT(18), /* b[19]-b[21] : select clock frequency */ DTS_PLAYBACK_DROP_RPT_MODE = BC_BIT(22), DTS_DIAG_TEST_MODE = BC_BIT(23), DTS_SINGLE_THREADED_MODE = BC_BIT(24), DTS_FILTER_MODE = BC_BIT(25), DTS_MFT_MODE = BC_BIT(26) }; #define DTS_DFLT_RESOLUTION(x) (x<<11) #define DTS_DFLT_CLOCK(x) (x<<19) /* F/W File Version corresponding to S/W Releases */ enum _FW_FILE_VER { /* S/W release: 02.04.02 F/W release 2.12.2.0 */ BC_FW_VER_020402 = ((12<<16) | (2<<8) | (0)) }; /*------------------------------------------------------* * Stream Types for DtsOpenDecoder() * *------------------------------------------------------*/ enum _DtsOpenDecStreamTypes { BC_STREAM_TYPE_ES = 0, BC_STREAM_TYPE_PES = 1, BC_STREAM_TYPE_TS = 2, BC_STREAM_TYPE_ES_TSTAMP = 6, }; /*------------------------------------------------------* * Video Algorithms for DtsSetVideoParams() * *------------------------------------------------------*/ enum _DtsSetVideoParamsAlgo { BC_VID_ALGO_H264 = 0, BC_VID_ALGO_MPEG2 = 1, BC_VID_ALGO_VC1 = 4, BC_VID_ALGO_DIVX = 6, BC_VID_ALGO_VC1MP = 7, }; /*------------------------------------------------------* * MPEG Extension to the PPB * *------------------------------------------------------*/ #define BC_MPEG_VALID_PANSCAN (1) typedef struct _BC_PIB_EXT_MPEG { uint32_t valid; /* Always valid, defaults to picture size if no * sequence display extension in the stream. */ uint32_t display_horizontal_size; uint32_t display_vertical_size; /* MPEG_VALID_PANSCAN * Offsets are a copy values from the MPEG stream. */ uint32_t offset_count; int32_t horizontal_offset[3]; int32_t vertical_offset[3]; } BC_PIB_EXT_MPEG; /*------------------------------------------------------* * H.264 Extension to the PPB * *------------------------------------------------------*/ /* Bit definitions for 'other.h264.valid' field */ #define H264_VALID_PANSCAN (1) #define H264_VALID_SPS_CROP (2) #define H264_VALID_VUI (4) typedef struct _BC_PIB_EXT_H264 { /* 'valid' specifies which fields (or sets of * fields) below are valid. If the corresponding * bit in 'valid' is NOT set then that field(s) * is (are) not initialized. */ uint32_t valid; /* H264_VALID_PANSCAN */ uint32_t pan_scan_count; int32_t pan_scan_left[3]; int32_t pan_scan_right[3]; int32_t pan_scan_top[3]; int32_t pan_scan_bottom[3]; /* H264_VALID_SPS_CROP */ int32_t sps_crop_left; int32_t sps_crop_right; int32_t sps_crop_top; int32_t sps_crop_bottom; /* H264_VALID_VUI */ uint32_t chroma_top; uint32_t chroma_bottom; } BC_PIB_EXT_H264; /*------------------------------------------------------* * VC1 Extension to the PPB * *------------------------------------------------------*/ #define VC1_VALID_PANSCAN (1) typedef struct _BC_PIB_EXT_VC1 { uint32_t valid; /* Always valid, defaults to picture size if no * sequence display extension in the stream. */ uint32_t display_horizontal_size; uint32_t display_vertical_size; /* VC1 pan scan windows */ uint32_t num_panscan_windows; int32_t ps_horiz_offset[4]; int32_t ps_vert_offset[4]; int32_t ps_width[4]; int32_t ps_height[4]; } BC_PIB_EXT_VC1; /*------------------------------------------------------* * Picture Information Block * *------------------------------------------------------*/ #if !defined(__KERNEL__) /* Values for 'pulldown' field. '0' means no pulldown information * was present for this picture. */ enum { vdecNoPulldownInfo = 0, vdecTop = 1, vdecBottom = 2, vdecTopBottom = 3, vdecBottomTop = 4, vdecTopBottomTop = 5, vdecBottomTopBottom = 6, vdecFrame_X2 = 7, vdecFrame_X3 = 8, vdecFrame_X1 = 9, vdecFrame_X4 = 10, }; /* Values for the 'frame_rate' field. */ enum { vdecFrameRateUnknown = 0, vdecFrameRate23_97, vdecFrameRate24, vdecFrameRate25, vdecFrameRate29_97, vdecFrameRate30, vdecFrameRate50, vdecFrameRate59_94, vdecFrameRate60, vdecFrameRate14_985, vdecFrameRate7_496, }; /* Values for the 'aspect_ratio' field. */ enum { vdecAspectRatioUnknown = 0, vdecAspectRatioSquare, vdecAspectRatio12_11, vdecAspectRatio10_11, vdecAspectRatio16_11, vdecAspectRatio40_33, vdecAspectRatio24_11, vdecAspectRatio20_11, vdecAspectRatio32_11, vdecAspectRatio80_33, vdecAspectRatio18_11, vdecAspectRatio15_11, vdecAspectRatio64_33, vdecAspectRatio160_99, vdecAspectRatio4_3, vdecAspectRatio16_9, vdecAspectRatio221_1, vdecAspectRatioOther = 255, }; /* Values for the 'colour_primaries' field. */ enum { vdecColourPrimariesUnknown = 0, vdecColourPrimariesBT709, vdecColourPrimariesUnspecified, vdecColourPrimariesReserved, vdecColourPrimariesBT470_2M = 4, vdecColourPrimariesBT470_2BG, vdecColourPrimariesSMPTE170M, vdecColourPrimariesSMPTE240M, vdecColourPrimariesGenericFilm, }; enum { vdecRESOLUTION_CUSTOM = 0x00000000, /* custom */ vdecRESOLUTION_480i = 0x00000001, /* 480i */ vdecRESOLUTION_1080i = 0x00000002, /* 1080i (1920x1080, 60i) */ vdecRESOLUTION_NTSC = 0x00000003, /* NTSC (720x483, 60i) */ vdecRESOLUTION_480p = 0x00000004, /* 480p (720x480, 60p) */ vdecRESOLUTION_720p = 0x00000005, /* 720p (1280x720, 60p) */ vdecRESOLUTION_PAL1 = 0x00000006, /* PAL_1 (720x576, 50i) */ vdecRESOLUTION_1080i25 = 0x00000007, /* 1080i25 (1920x1080, 50i) */ vdecRESOLUTION_720p50 = 0x00000008, /* 720p50 (1280x720, 50p) */ vdecRESOLUTION_576p = 0x00000009, /* 576p (720x576, 50p) */ vdecRESOLUTION_1080i29_97 = 0x0000000A, /* 1080i (1920x1080, 59.94i) */ vdecRESOLUTION_720p59_94 = 0x0000000B, /* 720p (1280x720, 59.94p) */ vdecRESOLUTION_SD_DVD = 0x0000000C, /* SD DVD (720x483, 60i) */ vdecRESOLUTION_480p656 = 0x0000000D, /* 480p (720x480, 60p), output bus width 8 bit, clock 74.25MHz */ vdecRESOLUTION_1080p23_976 = 0x0000000E, /* 1080p23_976 (1920x1080, 23.976p) */ vdecRESOLUTION_720p23_976 = 0x0000000F, /* 720p23_976 (1280x720p, 23.976p) */ vdecRESOLUTION_240p29_97 = 0x00000010, /* 240p (1440x240, 29.97p ) */ vdecRESOLUTION_240p30 = 0x00000011, /* 240p (1440x240, 30p) */ vdecRESOLUTION_288p25 = 0x00000012, /* 288p (1440x288p, 25p) */ vdecRESOLUTION_1080p29_97 = 0x00000013, /* 1080p29_97 (1920x1080, 29.97p) */ vdecRESOLUTION_1080p30 = 0x00000014, /* 1080p30 (1920x1080, 30p) */ vdecRESOLUTION_1080p24 = 0x00000015, /* 1080p24 (1920x1080, 24p) */ vdecRESOLUTION_1080p25 = 0x00000016, /* 1080p25 (1920x1080, 25p) */ vdecRESOLUTION_720p24 = 0x00000017, /* 720p24 (1280x720, 25p) */ vdecRESOLUTION_720p29_97 = 0x00000018, /* 720p29.97 (1280x720, 29.97p) */ vdecRESOLUTION_480p23_976 = 0x00000019, /* 480p23.976 (720*480, 23.976) */ vdecRESOLUTION_480p29_97 = 0x0000001A, /* 480p29.976 (720*480, 29.97p) */ vdecRESOLUTION_576p25 = 0x0000001B, /* 576p25 (720*576, 25p) */ /* For Zero Frame Rate */ vdecRESOLUTION_480p0 = 0x0000001C, /* 480p (720x480, 0p) */ vdecRESOLUTION_480i0 = 0x0000001D, /* 480i (720x480, 0i) */ vdecRESOLUTION_576p0 = 0x0000001E, /* 576p (720x576, 0p) */ vdecRESOLUTION_720p0 = 0x0000001F, /* 720p (1280x720, 0p) */ vdecRESOLUTION_1080p0 = 0x00000020, /* 1080p (1920x1080, 0p) */ vdecRESOLUTION_1080i0 = 0x00000021, /* 1080i (1920x1080, 0i) */ }; /* Bit definitions for 'flags' field */ #define VDEC_FLAG_EOS (0x0004) #define VDEC_FLAG_FRAME (0x0000) #define VDEC_FLAG_FIELDPAIR (0x0008) #define VDEC_FLAG_TOPFIELD (0x0010) #define VDEC_FLAG_BOTTOMFIELD (0x0018) #define VDEC_FLAG_PROGRESSIVE_SRC (0x0000) #define VDEC_FLAG_INTERLACED_SRC (0x0020) #define VDEC_FLAG_UNKNOWN_SRC (0x0040) #define VDEC_FLAG_BOTTOM_FIRST (0x0080) #define VDEC_FLAG_LAST_PICTURE (0x0100) #define VDEC_FLAG_PICTURE_META_DATA_PRESENT (0x40000) #endif /* __KERNEL__ */ typedef struct _BC_PIC_INFO_BLOCK { /* Common fields. */ uint64_t timeStamp; /* Timestamp */ uint32_t picture_number; /* Ordinal display number */ uint32_t width; /* pixels */ uint32_t height; /* pixels */ uint32_t chroma_format; /* 0x420, 0x422 or 0x444 */ uint32_t pulldown; uint32_t flags; uint32_t frame_rate; uint32_t aspect_ratio; uint32_t colour_primaries; uint32_t picture_meta_payload; uint32_t sess_num; uint32_t ycom; uint32_t custom_aspect_ratio_width_height; uint32_t n_drop; /* number of non-reference frames remaining to be dropped */ /* Protocol-specific extensions. */ union { BC_PIB_EXT_H264 h264; BC_PIB_EXT_MPEG mpeg; BC_PIB_EXT_VC1 vc1; } other; } BC_PIC_INFO_BLOCK, *PBC_PIC_INFO_BLOCK; /*------------------------------------------------------* * ProcOut Info * *------------------------------------------------------*/ /* Optional flags for ProcOut Interface.*/ enum _POUT_OPTIONAL_IN_FLAGS_{ /* Flags from App to Device */ BC_POUT_FLAGS_YV12 = 0x01, /* Copy Data in YV12 format */ BC_POUT_FLAGS_STRIDE = 0x02, /* Stride size is valid. */ BC_POUT_FLAGS_SIZE = 0x04, /* Take size information from Application */ BC_POUT_FLAGS_INTERLACED = 0x08, /* copy only half the bytes */ BC_POUT_FLAGS_INTERLEAVED = 0x10, /* interleaved frame */ BC_POUT_FLAGS_STRIDE_UV = 0x20, /* Stride size is valid (for UV buffers). */ BC_POUT_FLAGS_MODE = 0x40, /* Take output mode from Application, overrides YV12 flag if on */ /* Flags from Device to APP */ BC_POUT_FLAGS_FMT_CHANGE = 0x10000, /* Data is not VALID when this flag is set */ BC_POUT_FLAGS_PIB_VALID = 0x20000, /* PIB Information valid */ BC_POUT_FLAGS_ENCRYPTED = 0x40000, /* Data is encrypted. */ BC_POUT_FLAGS_FLD_BOT = 0x80000, /* Bottom Field data */ }; /*Decoder Capability */ enum DECODER_CAP_FLAGS { BC_DEC_FLAGS_H264 = 0x01, BC_DEC_FLAGS_MPEG2 = 0x02, BC_DEC_FLAGS_VC1 = 0x04, BC_DEC_FLAGS_M4P2 = 0x08, /*MPEG-4 Part 2: Divx, Xvid etc. */ }; #if defined(__KERNEL__) || defined(__LINUX_USER__) || defined(__LINUX__) typedef BC_STATUS(*dts_pout_callback)(void *shnd, uint32_t width, uint32_t height, uint32_t stride, void *pOut); #else typedef BC_STATUS(*dts_pout_callback)(void *shnd, uint32_t width, uint32_t height, uint32_t stride, struct _BC_DTS_PROC_OUT *pOut); #endif /* Line 21 Closed Caption */ /* User Data */ #define MAX_UD_SIZE 1792 /* 1920 - 128 */ typedef struct _BC_DTS_PROC_OUT { uint8_t *Ybuff; /* Caller Supplied buffer for Y data */ uint32_t YbuffSz; /* Caller Supplied Y buffer size */ uint32_t YBuffDoneSz; /* Transferred Y datasize */ uint8_t *UVbuff; /* Caller Supplied buffer for UV data */ uint32_t UVbuffSz; /* Caller Supplied UV buffer size */ uint32_t UVBuffDoneSz; /* Transferred UV data size */ uint32_t StrideSz; /* Caller supplied Stride Size */ uint32_t PoutFlags; /* Call IN Flags */ uint32_t discCnt; /* Picture discontinuity count */ BC_PIC_INFO_BLOCK PicInfo; /* Picture Information Block Data */ /* Line 21 Closed Caption */ /* User Data */ uint32_t UserDataSz; uint8_t UserData[MAX_UD_SIZE]; void *hnd; dts_pout_callback AppCallBack; uint8_t DropFrames; uint8_t b422Mode; /* Picture output Mode */ uint8_t bPibEnc; /* PIB encrypted */ uint8_t bRevertScramble; uint32_t StrideSzUV; /* Caller supplied Stride Size */ } BC_DTS_PROC_OUT; typedef struct _BC_DTS_STATUS { uint8_t ReadyListCount; /* Number of frames in ready list (reported by driver) */ uint8_t FreeListCount; /* Number of frame buffers free. (reported by driver) */ uint8_t PowerStateChange; /* Number of active state power transitions (reported by driver) */ uint8_t reserved_[1]; uint32_t FramesDropped; /* Number of frames dropped. (reported by DIL) */ uint32_t FramesCaptured; /* Number of frames captured. (reported by DIL) */ uint32_t FramesRepeated; /* Number of frames repeated. (reported by DIL) */ uint32_t InputCount; /* Times compressed video has been sent to the HW. * i.e. Successful DtsProcInput() calls (reported by DIL) */ uint64_t InputTotalSize; /* Amount of compressed video that has been sent to the HW. * (reported by DIL) */ uint32_t InputBusyCount; /* Times compressed video has attempted to be sent to the HW * but the input FIFO was full. (reported by DIL) */ uint32_t PIBMissCount; /* Amount of times a PIB is invalid. (reported by DIL) */ uint32_t cpbEmptySize; /* supported only for H.264, specifically changed for * SingleThreadedAppMode. Report size of CPB buffer available. * Reported by DIL */ uint64_t NextTimeStamp; /* TimeStamp of the next picture that will be returned * by a call to ProcOutput. Added for SingleThreadedAppMode. * Reported back from the driver */ uint8_t TxBufData; uint8_t reserved__[3]; uint32_t picNumFlags; /* Picture number and flags of the next picture to be delivered from the driver */ uint8_t reserved___[8]; } BC_DTS_STATUS; #define BC_SWAP32(_v) \ ((((_v) & 0xFF000000)>>24)| \ (((_v) & 0x00FF0000)>>8)| \ (((_v) & 0x0000FF00)<<8)| \ (((_v) & 0x000000FF)<<24)) #define WM_AGENT_TRAYICON_DECODER_OPEN 10001 #define WM_AGENT_TRAYICON_DECODER_CLOSE 10002 #define WM_AGENT_TRAYICON_DECODER_START 10003 #define WM_AGENT_TRAYICON_DECODER_STOP 10004 #define WM_AGENT_TRAYICON_DECODER_RUN 10005 #define WM_AGENT_TRAYICON_DECODER_PAUSE 10006 #define MAX_COLOR_SPACES 3 typedef enum _BC_OUTPUT_FORMAT { MODE420 = 0x0, MODE422_YUY2 = 0x1, MODE422_UYVY = 0x2, OUTPUT_MODE420 = 0x0, OUTPUT_MODE422_YUY2 = 0x1, OUTPUT_MODE422_UYVY = 0x2, OUTPUT_MODE420_NV12 = 0x0, OUTPUT_MODE_INVALID = 0xFF, } BC_OUTPUT_FORMAT; typedef struct _BC_COLOR_SPACES_ { BC_OUTPUT_FORMAT OutFmt[MAX_COLOR_SPACES]; uint16_t Count; } BC_COLOR_SPACES; typedef enum _BC_CAPS_FLAGS_ { PES_CONV_SUPPORT = 1, /*Support PES Conversion*/ MULTIPLE_DECODE_SUPPORT = 2 /*Support multiple stream decode*/ } BC_CAPS_FLAGS; typedef struct _BC_HW_CAPABILITY_ { BC_CAPS_FLAGS flags; BC_COLOR_SPACES ColorCaps; void* Reserved1; /* Expansion Of API */ /*Decoder Capability */ uint32_t DecCaps; /*DECODER_CAP_FLAGS */ } BC_HW_CAPS, *PBC_HW_CAPS; typedef struct _BC_SCALING_PARAMS_ { uint32_t sWidth; uint32_t sHeight; uint32_t DNR; uint32_t Reserved1; /*Expansion Of API*/ uint8_t *Reserved2; /*Expansion OF API*/ uint32_t Reserved3; /*Expansion Of API*/ uint8_t *Reserved4; /*Expansion Of API*/ } BC_SCALING_PARAMS, *PBC_SCALING_PARAMS; typedef enum _BC_MEDIA_SUBTYPE_ { BC_MSUBTYPE_INVALID = 0, BC_MSUBTYPE_MPEG1VIDEO, BC_MSUBTYPE_MPEG2VIDEO, BC_MSUBTYPE_H264, BC_MSUBTYPE_WVC1, BC_MSUBTYPE_WMV3, BC_MSUBTYPE_AVC1, BC_MSUBTYPE_WMVA, BC_MSUBTYPE_VC1, BC_MSUBTYPE_DIVX, BC_MSUBTYPE_DIVX311, BC_MSUBTYPE_OTHERS /*Types to facilitate PES conversion*/ } BC_MEDIA_SUBTYPE; typedef struct _BC_INPUT_FORMAT_ { int FGTEnable; /*Enable processing of FGT SEI*/ int MetaDataEnable; /*Enable retrieval of picture metadata to be sent to video pipeline.*/ int Progressive; /*Instruct decoder to always try to send back progressive frames. If input content is 1080p, the decoder will ignore pull-down flags and always give 1080p output. If 1080i content is processed, the decoder will return 1080i data. When this flag is not set, the decoder will use pull-down information in the input stream to decide the decoded data format.*/ uint32_t OptFlags; /*In this field bits 0:3 are used pass default frame rate, bits 4:5 are for operation mode (used to indicate Blu-ray mode to the decoder) and bit 6 is for the flag mpcOutPutMaxFRate which when set tells the FW to output at the max rate for the resolution and ignore the frame rate determined from the stream. Bit 7 is set to indicate that this is single threaded mode and the driver will be peeked to get timestamps ahead of time*/ BC_MEDIA_SUBTYPE mSubtype; /* Video Media Type*/ uint32_t width; uint32_t height; uint32_t startCodeSz; /*Start code size for H264 clips*/ uint8_t *pMetaData; /*Metadata buffer that is used to pass sequence header*/ uint32_t metaDataSz; /*Metadata size*/ uint8_t bEnableScaling; BC_SCALING_PARAMS ScalingParams; } BC_INPUT_FORMAT; typedef struct _BC_INFO_CRYSTAL_ { uint8_t device; union { struct { uint32_t dilRelease:8; uint32_t dilMajor:8; uint32_t dilMinor:16; }; uint32_t version; } dilVersion; union { struct { uint32_t drvRelease:4; uint32_t drvMajor:8; uint32_t drvMinor:12; uint32_t drvBuild:8; }; uint32_t version; } drvVersion; union { struct { uint32_t fwRelease:4; uint32_t fwMajor:8; uint32_t fwMinor:12; uint32_t fwBuild:8; }; uint32_t version; } fwVersion; uint32_t Reserved1; /* For future expansion */ uint32_t Reserved2; /* For future expansion */ } BC_INFO_CRYSTAL, *PBC_INFO_CRYSTAL; #endif /* _BC_DTS_DEFS_H_ */ crystalhd-0.0~git20110715.fdd2f19/include/7411d.h0000644000175000017500000021731411610313111020071 0ustar andresandres/*************************************************************************** * Copyright (c) 2004-2009, Broadcom Corporation. * * Name: 7411d.h * * Description: Decoder register, status and parameter definitions * * Revision History: * * $brcm_Log: /brickstone/sw/emb/stream/c011api.h $ * * sw_branch_7411_d0/sw_branch_7412_a0/sw_branch_7412_a0_apple/2 10/25/06 5:27p xshi * Code clean: removed sdramInputBuf0/1 in channelOpenRsp; obsoleted * sdramInputDmaBufferSize in startVideoCmd. * * sw_branch_7411_d0/sw_branch_7412_a0/sw_branch_7412_a0_apple/1 10/19/06 10:16a baginski * More Vista modifications * * sw_branch_7411_d0/sw_branch_7412_a0/7 9/26/06 1:54p baginski * Merge from sw_branch_7411_d0 via sw_branch_settop_firmware_7411d0 * * sw_branch_7411_d0/66 9/26/06 1:45p baginski * Merge from sw_branch_settop_firmware_7411d0 - * REL_CANDIDATE_C0_003_005_006_2006_09_26 * * sw_branch_7411_d0/65 9/18/06 11:50a baginski * Merge 7412 Vista Modifications * * sw_branch_7411_d0/sw_branch_7412_a0/6 8/24/06 11:38a baginski * Merge from FW_7411D_DVD_4_4_25 * * sw_branch_7411_d0/sw_branch_7412_a0/5 8/3/06 1:53p xshi * code optimization: * (1) add "dramInputEnabled" in channel context; * (2) move the struct "dmaXferCtrlInfo" from c011api.h to stream.h; * (3) swap the bit-field packing order of "dmaXferCtrlInfo"; * (4) always set "IncDst" bit if dstAddr of CIB is zero * * sw_branch_7411_d0/sw_branch_7412_a0/4 7/31/06 5:39p baginski * Broadcom ECG Mode - Phase 1,2 * - ts fake header support * - sequence number attachment for H.264 bitstreams * - chroma upsampling turned off * * sw_branch_7411_d0/sw_branch_7412_a0/3 7/27/06 2:32p xshi * Obsolete param "sdramInputDmaBufferSize" of channelOpen * * sw_branch_7411_d0/sw_branch_7412_a0/2 7/18/06 11:44a xshi * add support for sid interrupt. * * sw_branch_7411_d0/sw_branch_7412_a0/1 7/13/06 2:18p xshi * pci dma API: (1) data struct of Control Info; (2) CIQ; (3) cmd/rsp * change; and (4) dma handling on stream arc * * sw_branch_7411_d0/62 6/26/06 10:23a xshi * SID program space allocation and init. Note that the program space * starts at 0x302000 and has a length of about 1 Mbytes, whichn used to * be encoder's program space. In future if ENC is brought back we need * to re-tune the memory. * * sw_branch_7411_d0/61 6/23/06 2:04p xshi * SID memory allocation * * sw_branch_7411_d0/60 6/21/06 4:24p baginski * Set Clipping Command * * sw_branch_7411_d0/59 6/15/06 1:45p baginski * add picture done payload field to channel status block * * sw_branch_7411_d0/58 6/1/06 11:16a xshi * (1) Added new DramLogEnable in C011CmdInit; and return dramLogBase(s) * and dramLogSize(s) in C011RspInit * (2) Removed trickPlayBuf away from channelOpen/startVideo * * sw_branch_7411_d0/57 5/25/06 2:03p xshi * (1) async event renaming; (2) added cmd respond int to bit-map * * sw_branch_7411_d0/56 5/23/06 2:07p baginski * Merge settop c011api.h changes - to form a single shared c011api.h * * sw_branch_7411_d0/55 5/23/06 10:40a xshi * restore the para "reserved" of channelOperationMode * * sw_branch_7411_d0/54 5/23/06 10:31a xshi * (1) remove picReadyInt and picSetupInt of channelopen/startvideo * (2) cleanup the code correspondingly * ******************************************************************** * This header is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This header is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this header. If not, see . ***************************************************************************/ #ifndef __INC_C011API_H__ #define __INC_C011API_H__ #include "vdec_info.h" // maximum number of host commands and responses #define C011_MAX_HST_CMDS (16) #define C011_MAX_HST_RSPS (16) #define C011_MAX_HST_CMDQ_SIZE (64) // default success return code #define C011_RET_SUCCESS (0x0) // default failure return code #define C011_RET_FAILURE (0xFFFFFFFF) #define C011_RET_UNKNOWN (0x1) // Stream ARC base address #define STR_BASE (0x00000000) // Stream ARC <- Host (default) address #define STR_HOSTRCV (STR_BASE + 0x100) // Stream ARC -> Host address #define STR_HOSTSND (STR_BASE + 0x200) #define eCMD_C011_CMD_BASE (0x73763000) /* host commands */ typedef enum { eCMD_TS_GET_NEXT_PIC = 0x7376F100, // debug get next picture eCMD_TS_GET_LAST_PIC = 0x7376F102, // debug get last pic status eCMD_TS_READ_WRITE_MEM = 0x7376F104, // debug read write memory /* New API commands */ /* General commands */ eCMD_C011_INIT = eCMD_C011_CMD_BASE + 0x01, eCMD_C011_RESET = eCMD_C011_CMD_BASE + 0x02, eCMD_C011_SELF_TEST = eCMD_C011_CMD_BASE + 0x03, eCMD_C011_GET_VERSION = eCMD_C011_CMD_BASE + 0x04, eCMD_C011_GPIO = eCMD_C011_CMD_BASE + 0x05, eCMD_C011_DEBUG_SETUP = eCMD_C011_CMD_BASE + 0x06, /* Decoding commands */ eCMD_C011_DEC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x100, eCMD_C011_DEC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x101, eCMD_C011_DEC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x102, eCMD_C011_DEC_CHAN_STATUS = eCMD_C011_CMD_BASE + 0x103, eCMD_C011_DEC_CHAN_FLUSH = eCMD_C011_CMD_BASE + 0x104, eCMD_C011_DEC_CHAN_TRICK_PLAY = eCMD_C011_CMD_BASE + 0x105, eCMD_C011_DEC_CHAN_TS_PIDS = eCMD_C011_CMD_BASE + 0x106, eCMD_C011_DEC_CHAN_PS_STREAM_ID = eCMD_C011_CMD_BASE + 0x107, eCMD_C011_DEC_CHAN_INPUT_PARAMS = eCMD_C011_CMD_BASE + 0x108, eCMD_C011_DEC_CHAN_VIDEO_OUTPUT = eCMD_C011_CMD_BASE + 0x109, eCMD_C011_DEC_CHAN_OUTPUT_FORMAT = eCMD_C011_CMD_BASE + 0x10A, eCMD_C011_DEC_CHAN_SCALING_FILTERS = eCMD_C011_CMD_BASE + 0x10B, eCMD_C011_DEC_CHAN_OSD_MODE = eCMD_C011_CMD_BASE + 0x10D, eCMD_C011_DEC_CHAN_DROP = eCMD_C011_CMD_BASE + 0x10E, eCMD_C011_DEC_CHAN_RELEASE = eCMD_C011_CMD_BASE + 0x10F, eCMD_C011_DEC_CHAN_STREAM_SETTINGS = eCMD_C011_CMD_BASE + 0x110, eCMD_C011_DEC_CHAN_PAUSE_OUTPUT = eCMD_C011_CMD_BASE + 0x111, eCMD_C011_DEC_CHAN_CHANGE = eCMD_C011_CMD_BASE + 0x112, eCMD_C011_DEC_CHAN_SET_STC = eCMD_C011_CMD_BASE + 0x113, eCMD_C011_DEC_CHAN_SET_PTS = eCMD_C011_CMD_BASE + 0x114, eCMD_C011_DEC_CHAN_CC_MODE = eCMD_C011_CMD_BASE + 0x115, eCMD_C011_DEC_CREATE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x116, eCMD_C011_DEC_COPY_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x117, eCMD_C011_DEC_DELETE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x118, eCMD_C011_DEC_CHAN_SET_DECYPTION = eCMD_C011_CMD_BASE + 0x119, eCMD_C011_DEC_CHAN_START_VIDEO = eCMD_C011_CMD_BASE + 0x11A, eCMD_C011_DEC_CHAN_STOP_VIDEO = eCMD_C011_CMD_BASE + 0x11B, eCMD_C011_DEC_CHAN_PIC_CAPTURE = eCMD_C011_CMD_BASE + 0x11C, eCMD_C011_DEC_CHAN_PAUSE = eCMD_C011_CMD_BASE + 0x11D, eCMD_C011_DEC_CHAN_PAUSE_STATE = eCMD_C011_CMD_BASE + 0x11E, eCMD_C011_DEC_CHAN_SET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x11F, eCMD_C011_DEC_CHAN_GET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x120, eCMD_C011_DEC_CHAN_SET_FF_RATE = eCMD_C011_CMD_BASE + 0x121, eCMD_C011_DEC_CHAN_GET_FF_RATE = eCMD_C011_CMD_BASE + 0x122, eCMD_C011_DEC_CHAN_FRAME_ADVANCE = eCMD_C011_CMD_BASE + 0x123, eCMD_C011_DEC_CHAN_SET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x124, eCMD_C011_DEC_CHAN_GET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x125, eCMD_C011_DEC_CHAN_FILL_PIC_BUF = eCMD_C011_CMD_BASE + 0x126, eCMD_C011_DEC_CHAN_SET_CONTINUITY_CHECK = eCMD_C011_CMD_BASE + 0x127, eCMD_C011_DEC_CHAN_GET_CONTINUITY_CHECK = eCMD_C011_CMD_BASE + 0x128, eCMD_C011_DEC_CHAN_SET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x129, eCMD_C011_DEC_CHAN_GET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x12A, eCMD_C011_DEC_CHAN_REVERSE_FIELD_STATUS = eCMD_C011_CMD_BASE + 0x12B, eCMD_C011_DEC_CHAN_I_PICTURE_FOUND = eCMD_C011_CMD_BASE + 0x12C, eCMD_C011_DEC_CHAN_SET_PARAMETER = eCMD_C011_CMD_BASE + 0x12D, eCMD_C011_DEC_CHAN_SET_USER_DATA_MODE = eCMD_C011_CMD_BASE + 0x12E, eCMD_C011_DEC_CHAN_SET_PAUSE_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x12F, eCMD_C011_DEC_CHAN_SET_SLOW_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x130, eCMD_C011_DEC_CHAN_SET_FF_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x131, eCMD_C011_DEC_CHAN_SET_DISPLAY_TIMING_MODE = eCMD_C011_CMD_BASE + 0x132, eCMD_C011_DEC_CHAN_SET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x133, eCMD_C011_DEC_CHAN_GET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x134, eCMD_C011_DEC_CHAN_SET_REVERSE_FIELD = eCMD_C011_CMD_BASE + 0x135, eCMD_C011_DEC_CHAN_STREAM_OPEN = eCMD_C011_CMD_BASE + 0x136, eCMD_C011_DEC_CHAN_SET_PCR_PID = eCMD_C011_CMD_BASE + 0x137, eCMD_C011_DEC_CHAN_SET_VID_PID = eCMD_C011_CMD_BASE + 0x138, eCMD_C011_DEC_CHAN_SET_PAN_SCAN_MODE = eCMD_C011_CMD_BASE + 0x139, eCMD_C011_DEC_CHAN_START_DISPLAY_AT_PTS = eCMD_C011_CMD_BASE + 0x140, eCMD_C011_DEC_CHAN_STOP_DISPLAY_AT_PTS = eCMD_C011_CMD_BASE + 0x141, eCMD_C011_DEC_CHAN_SET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x142, eCMD_C011_DEC_CHAN_GET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x143, eCMD_C011_DEC_CHAN_SET_HOST_TRICK_MODE = eCMD_C011_CMD_BASE + 0x144, eCMD_C011_DEC_CHAN_SET_OPERATION_MODE = eCMD_C011_CMD_BASE + 0x145, eCMD_C011_DEC_CHAN_DISPLAY_PAUSE_UNTO_PTS = eCMD_C011_CMD_BASE + 0x146, eCMD_C011_DEC_CHAN_SET_PTS_STC_DIFF_THRESHOLD = eCMD_C011_CMD_BASE + 0x147, eCMD_C011_DEC_CHAN_SEND_COMPRESSED_BUF = eCMD_C011_CMD_BASE + 0x148, eCMD_C011_DEC_CHAN_SET_CLIPPING = eCMD_C011_CMD_BASE + 0x149, eCMD_C011_DEC_CHAN_SET_PARAMETERS_FOR_HARD_RESET_INTERRUPT_TO_HOST = eCMD_C011_CMD_BASE + 0x150, /* Decoder RevD commands */ eCMD_C011_DEC_CHAN_SET_CSC = eCMD_C011_CMD_BASE + 0x180, /* CSC:color space conversion */ eCMD_C011_DEC_CHAN_SET_RANGE_REMAP = eCMD_C011_CMD_BASE + 0x181, eCMD_C011_DEC_CHAN_SET_FGT = eCMD_C011_CMD_BASE + 0x182, eCMD_C011_DEC_CHAN_SET_LASTPICTURE_PADDING = eCMD_C011_CMD_BASE + 0x183, // not implemented yet in Rev D main /* Decoder 7412 commands */ eCMD_C011_DEC_CHAN_SET_CONTENT_KEY = eCMD_C011_CMD_BASE + 0x190, // 7412 only eCMD_C011_DEC_CHAN_SET_SESSION_KEY = eCMD_C011_CMD_BASE + 0x191, // 7412 only eCMD_C011_DEC_CHAN_FMT_CHANGE_ACK = eCMD_C011_CMD_BASE + 0x192, // 7412 only eCMD_C011_DEC_CHAN_CUSTOM_VIDOUT = eCMD_C011_CMD_BASE + 0x1FF, /* Encoding commands */ eCMD_C011_ENC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x200, eCMD_C011_ENC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x201, eCMD_C011_ENC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x202, eCMD_C011_ENC_CHAN_CONTROL = eCMD_C011_CMD_BASE + 0x203, eCMD_C011_ENC_CHAN_STATISTICS = eCMD_C011_CMD_BASE + 0x204, eNOTIFY_C011_ENC_CHAN_EVENT = eCMD_C011_CMD_BASE + 0x210, eCMD_C011_DEC_CHAN_SET_SINGLE_FIELD = eCMD_C011_CMD_BASE + 0x501, } eC011_TS_CMD; /* ARCs */ /* - eCMD_C011_INIT */ #define C011_STREAM_ARC (0x00000001) /* stream ARC */ #define C011_VDEC_ARC (0x00000002) /* video decoder ARC */ #define C011_SID_ARC (0x00000004) /* SID ARC */ /* Interrupt Status Register definition for HostControlled mode: * 16 bits available for general use, bit-31 dedicated for MailBox Interrupt! */ #define RESERVED_FOR_FUTURE_USE_0 (1<<0) /* BIT 0 */ #define PICTURE_INFO_AVAILABLE (1<<1) #define PICTURE_DONE_MARKER (1<<2) #define ASYNC_EVENTQ (1<<3) #define INPUT_DMA_DONE (1<<4) #define OUTPUT_DMA_DONE (1<<5) #define VIDEO_DATA_UNDERFLOW_IN0 (1<<6) #define CRC_DATA_AVAILABLE_IN0 (1<<7) #define SID_SERVICE (1<<8) #define USER_DATA_AVAILABLE_IN0 (1<<9) #define NEW_PCR_OFFSET (1<<10) /* New PCR Offset received */ #define RESERVED_FOR_FUTURE_USE_2 (1<<11) #define HOST_DMA_COMPLETE (1<<12) #define RAPTOR_SERVICE (1<<13) #define INITIAL_PTS (1<<14) /* STC Request Interrupt */ #define PTS_DISCONTINUITY (1<<15) /* PTS Error Interrupt */ #define COMMAND_RESPONSE (1<<31) /* Command Response Register Interrupt */ /* Asynchronous Events - enabled via ChannelOpen */ #define EVENT_PRESENTATION_START (0x00000001) #define EVENT_PRESENTATION_STOP (0x00000002) #define EVENT_ILLEGAL_STREAM (0x00000003) #define EVENT_UNDERFLOW (0x00000004) #define EVENT_VSYNC_ERROR (0x00000005) #define INPUT_DMA_BUFFER0_RELEASE (0x00000006) #define INPUT_DMA_BUFFER1_RELEASE (0x00000007) /* interrupt control */ /* - eCMD_C011_INIT */ typedef enum { eC011_INT_DISABLE = 0x00000000, eC011_INT_ENABLE = 0x00000001, eC011_INT_ENABLE_RAPTOR = 0x00000003, } eC011_INT_CONTROL; /*chdDiskformatBD*/ /* - eCMD_C011_INIT */ #define eC011_DSK_BLURAY (1<<10) #define eC011_RES_MASK 0x0000F800 /* test id */ /* - eCMD_C011_SELF_TEST */ typedef enum { eC011_TEST_SHORT_MEMORY = 0x00000001, eC011_TEST_LONG_MEMORY = 0x00000002, eC011_TEST_SHORT_REGISTER = 0x00000003, eC011_TEST_LONG_REGISTER = 0x00000004, eC011_TEST_DECODE_LOOPBACK = 0x00000005, eC011_TEST_ENCODE_LOOPBACK = 0x00000006, } eC011_TEST_ID; /* gpio control */ /* - eCMD_C011_GPIO */ typedef enum { eC011_GPIO_CONTROL_INTERNAL = 0x00000000, eC011_GPIO_CONTROL_HOST = 0x00000001, } eC011_GPIO_CONTROL; /* input port */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_IN_PORT0 = 0x00000000, // input port 0 eC011_IN_PORT1 = 0x00000001, // input port 1 eC011_IN_HOST_PORT0 = 0x00000010, // host port (OR this bit to specify which port is host mode) eC011_IN_HOST_PORT1 = 0x00000011, // host port (OR this bit to specify which port is host mode) eC011_IN_DRAM = 0x00000100, // SDRAM } eC011_INPUT_PORT; /* output port */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_OUT_PORT0 = 0x00000000, // output port 0 eC011_OUT_PORT1 = 0x00000001, // output port 1 eC011_OUT_BOTH = 0x00000002, // output port 0 and 1 eC011_OUT_HOST = 0x00000010, // host port (OR this bit to specify which port is host mode) } eC011_OUTPUT_PORT; /* stream types */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_STREAM_TYPE_ES = 0x00000000, // elementary stream eC011_STREAM_TYPE_PES = 0x00000001, // packetized elementary stream eC011_STREAM_TYPE_TS = 0x00000002, // transport stream eC011_STREAM_TYPE_TSD_ES = 0x00000003, // legacy 130-byte transport stream with ES eC011_STREAM_TYPE_TSD_PES = 0x00000004, // legacy 130-byte transport stream with PES eC011_STREAM_TYPE_CMS = 0x00000005, // compressed multistream eC011_STREAM_TYPE_ES_W_TSHDR = 0x00000006, // elementary stream with fixed TS headers eC011_STREAM_TYPE_ES_DBG = 0x80000000, // debug elementary stream eC011_STREAM_TYPE_PES_DBG = 0x80000001, // debug packetized elementary stream eC011_STREAM_TYPE_TS_DBG = 0x80000002, // debug transport stream eC011_STREAM_TYPE_TSD_ES_DBG = 0x80000003, // debug legacy 130-byte transport stream with ES eC011_STREAM_TYPE_TSD_PES_DBG = 0x80000004, // debug legacy 130-byte transport stream with PES eC011_STREAM_TYPE_CMS_DBG = 0x80000005, // debug compressed multistream eC011_STREAM_TYPE_ES_FIXED_TS_DBG = 0x80000006, // debug elementary stream with fixed TS headers } eC011_STREAM_TYPE; /* maximum picture size */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_MAX_PICSIZE_HD = 0x00000000, // 1920x1088 eC011_MAX_PICSIZE_SD = 0x00000001, // 720x576 } eC011_MAX_PICSIZE; /* output control mode */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_OUTCTRL_VIDEO_TIMING = 0x00000000, eC011_OUTCTRL_HOST_TIMING = 0x00000001, } eC011_OUTCTRL_MODE; /* live/playback */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_CHANNEL_PLAYBACK = 0x00000000, eC011_CHANNEL_LIVE_DECODE = 0x00000001, eC011_CHANNEL_TRANSPORT_STREAM_CAPTURE = 0x00000002, } eC011_CHANNEL_TYPE; /* video algorithm */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_VIDEO_ALG_H264 = 0x00000000, // H.264 eC011_VIDEO_ALG_MPEG2 = 0x00000001, // MPEG-2 eC011_VIDEO_ALG_H261 = 0x00000002, // H.261 eC011_VIDEO_ALG_H263 = 0x00000003, // H.263 eC011_VIDEO_ALG_VC1 = 0x00000004, // VC1 eC011_VIDEO_ALG_MPEG1 = 0x00000005, // MPEG-1 eC011_VIDEO_ALG_DIVX = 0x00000006, // divx #if 0 eC011_VIDEO_ALG_MPEG4 = 0x00000006, // MPEG-4 #endif } eC011_VIDEO_ALG; /* input source */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_VIDSRC_DEFAULT_PROGRESSIVE = 0x00000000, // derive from stream eC011_VIDSRC_DEFAULT_INTERLACED = 0x00000001, // derive from stream eC011_VIDSRC_FIXED_PROGRESSIVE = 0x00000002, // progressive frames eC011_VIDSRC_FIXED_INTERLACED = 0x00000003, // interlaced fields } eC011_VIDEO_SOURCE_MODE; /* pull-down mode */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_PULLDOWN_DEFAULT_32 = 0x00000000, // derive from PTS inside stream eC011_PULLDOWN_DEFAULT_22 = 0x00000001, // derive from PTS inside stream eC011_PULLDOWN_DEFAULT_ASAP = 0x00000002, // derive from PTS inside stream eC011_PULLDOWN_FIXED_32 = 0x00000003, // fixed 3-2 pulldown eC011_PULLDOWN_FIXED_22 = 0x00000004, // fixed 2-2 pulldown eC011_PULLDOWN_FIXED_ASAP = 0x00000005, // fixed as fast as possible } eC011_PULLDOWN_MODE; /* display order */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_DISPLAY_ORDER_DISPLAY = 0x00000000, // display in display order eC011_DISPLAY_ORDER_DECODE = 0x00000001, // display in decode order } eC011_DISPLAY_ORDER; /* picture information mode */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_PICTURE_INFO_OFF = 0x00000000, // no picture information eC011_PICTURE_INFO_ON = 0x00000001, // pass picture information to host } eC011_PICTURE_INFO_MODE; /* picture ready interrupt mode */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_PIC_INT_NONE = 0x00000000, // no picture ready interrupts eC011_PIC_INT_FIRST_PICTURE = 0x00000001, // interrupt on first picture only eC011_PIC_INT_ALL_PICTURES = 0x00000002, // interrupt on all pictures } eC011_PIC_INT_MODE; /* picture setup interrupt mode */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_DISP_INT_NONE = 0x00000000, // no picture setup/release interrupts eC011_DISP_INT_SETUP = 0x00000001, // interrupt on picture setup only eC011_DISP_INT_SETUP_RELEASE = 0x00000002, // interrupt on picture setup and release } eC011_DISP_INT_MODE; /* deblocking mode */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_DEBLOCKING_OFF = 0x00000000, // no deblocking eC011_DEBLOCKING_ON = 0x00000001, // deblocking on } eC011_DEBLOCKING_MODE; /* BRCM (HD-DVI) mode */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_BRCM_MODE_OFF = 0x00000000, // Non BRCM (non HD-DVI) mode eC011_BRCM_MODE_ON = 0x00000001, // BRCM (HD-DVI) mode eC011_BRCM_ECG_MODE_ON = 0x00000002, // BRCM (HD-DVI) ECG mode } eC011_BRCM_MODE; /* External VCXO control mode */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_EXTERNAL_VCXO_OFF = 0x00000000, // No external vcxo control eC011_EXTERNAL_VCXO_ON = 0x00000001, // External vcxo control } eC011_EXTERNAL_VCXO_MODE; /* Display timing mode */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_DISPLAY_TIMING_USE_PTS = 0x00000000, // Use PTS for display timing eC011_DISPLAY_TIMING_IGNORE_PTS = 0x00000001, // Ignore PTS and follow pulldown } eC011_DISPLAY_TIMING_MODE; /* User data collection mode */ /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_USER_DATA_MODE_OFF = 0x00000000, // User data disabled eC011_USER_DATA_MODE_ON = 0x00000001, // User data enabled } eC011_USER_DATA_MODE; /* - eCMD_C011_DEC_CHAN_OPEN */ typedef enum { eC011_PAN_SCAN_MODE_OFF = 0x00000000, // pan-scan disabled eC011_PAN_SCAN_MODE_ON = 0x00000001, // pan-scan enabled eC011_PAN_SCAN_MODE_HOR_ON = 0x00000002, //Horizontal pan-scan enabled, Vertical pan-scan disabled eC011_PAN_SCAN_MODE_HOR_OFF = 0x00000003, //Horizontal pan-scan disabled, Vertical pan-scan disabled eC011_PAN_SCAN_MODE_VER_ON = 0x00000004, //Horizontal pan-scan disabled, Vertical pan-scan enabled eC011_PAN_SCAN_MODE_VER_OFF = 0x00000005, //Horizontal pan-scan disabled, Vertical pan-scan disabled } eC011_PAN_SCAN_MODE; /* * PTS States * * PTS_VALID: PTS is coded in the picture * PTS_INTERPOLATED: PTS has been interpolated from an earlier picture which had a coded PTS * PTS_UNKNOWN: Startup condition when PTS is not yet received * PTS_HOST: Host has set the PTS to be used for the next pic via the SetPTS API command */ typedef enum PTS_STATE { PTS_VALID = 0, PTS_INTERPOLATED, PTS_UNKNOWN, PTS_HOST, } ePtsState; /* channel status structure */ /* - eCMD_C011_DEC_CHAN_OPEN response */ typedef struct { eC011_DISPLAY_TIMING_MODE displayTimingMode; // current display timing mode in effect int32_t videoDisplayOffset; // current video display offset in effect uint32_t currentPts; // current PTS value uint32_t interpolatedPts; // currentPts of type PTS_STATE uint32_t refCounter; uint32_t pcrOffset; uint32_t stcValue; uint32_t stcWritten; // 1 -> host updated STC, 0 -> stream ARC ack int32_t ptsStcOffset; // PTS - STC uint32_t pVdecStatusBlk; /* pointer to vdec status block */ /* Change from void * to make it 64-bit safe */ uint32_t lastPicture; // 1 -> decoder last picture indication uint32_t pictureTag; /* Picture Tag from VDEC */ uint32_t tsmLockTime; /* Time when the First Picture passed TSM */ uint32_t firstPicRcvdTime; /* Time when the First Picture was recieved */ uint32_t picture_done_payload;/* Payload associated with the picture done marker interrupt */ } sC011_CHAN_STATUS; /* picture information block (PIB) */ /* used in picInfomode, userdataMode */ struct C011_PIB { uint32_t bFormatChange; uint32_t resolution; uint32_t channelId; uint32_t ppbPtr; int32_t ptsStcOffset; uint32_t zeroPanscanValid; uint32_t dramOutBufAddr; uint32_t yComponent; PPB ppb; }; /* size of picture information block */ #define C011_PIB_SIZE (sizeof(C011_PIB)) /* picture release mode */ /* - eCMD_C011_DEC_CHAN_CLOSE */ typedef enum { eC011_PIC_REL_HOST = 0x00000000, // wait for host to release pics eC011_PIC_REL_INTERNAL = 0x00000001, // do not wait for host } eC011_PIC_REL_MODE; /* last picture display mode */ /* - eCMD_C011_DEC_CHAN_CLOSE */ typedef enum { eC011_LASTPIC_DISPLAY_ON = 0x00000000, // keep displaying last picture after channelClose eC011_LASTPIC_DISPLAY_OFF = 0x00000001, // blank output after channelClose } eC011_LASTPIC_DISPLAY; /* channel flush mode */ /* - eCMD_C011_DEC_CHAN_FLUSH */ typedef enum { eC011_FLUSH_INPUT_POINT = 0x00000000, // flush at current input point eC011_FLUSH_PROC_POINT = 0x00000001, // flush at current processing eC011_FLUSH_PROC_POINT_RESET_TS = 0x00000002, // flush at current processing, reset TS } eC011_FLUSH_MODE; /* direction */ /* - eCMD_C011_DEC_CHAN_TRICK_PLAY */ typedef enum { eCODEC_DIR_FORWARD = 0x00000000, // forward eCODEC_DIR_REVERSE = 0x00000001, // reverse } eC011_DIR; /* speed */ /* - eCMD_C011_DEC_CHAN_TRICK_PLAY */ typedef enum { eC011_SPEED_NORMAL = 0x00000000, // all pictures eC011_SPEED_FAST = 0x00000001, // reference pictures only eC011_SPEED_VERYFAST = 0x00000002, // I-picture only eC011_SPEED_SLOW = 0x00000003, // STC trickplay slow eC011_SPEED_PAUSE = 0x00000004, // STC trickplay pause eC011_SPEED_I_ONLY_HOST_MODE = 0x00000100, // I-picture only host mode eC011_SPEED_2x_SLOW = 0xFFFFFFFF, // all pics played 2x frame time eC011_SPEED_4x_SLOW = 0xFFFFFFFE, // all pics played 4x frame time eC011_SPEED_8x_SLOW = 0xFFFFFFFD, // all pics played 8x frame time eC011_SPEED_STEP = 0xFFFFFFFC, // STC trickplay step } eC011_SPEED; typedef enum { eC011_DROP_TYPE_DECODER = 0x00000000, eC011_DROP_TYPE_DISPLAY = 0x00000001, } eC011_DROP_TYPE; /* stream input sync mode */ /* - eCMD_C011_DEC_CHAN_INPUT_PARAMS */ typedef enum { eC011_SYNC_MODE_AUTOMATIC = 0x00000000, // automatic sync detection eC011_SYNC_MODE_SYNCPIN = 0x00000001, // sync pin mode } eC011_SYNC_MODE; /* unmarked discontinuity notification */ /* - eCMD_C011_DEC_CHAN_INPUT_PARAMS */ typedef enum { eC011_UNMARKED_DISCONTINUITY_OFF = 0x00000000, // disable unmarked discontinuity eC011_UNMARKED_DISCONTINUITY_ON = 0x00000001, // enable unmarked discontinuity } eC011_UNMARKED_DISCONTINUITY_MODE; /* unmarked discontinuity notification trigger threshold */ /* - eCMD_C011_DEC_CHAN_INPUT_PARAMS */ typedef enum { eC011_UNMARKED_DISCONTINUITY_THRESHOLD_1_PKT = 0x00000000, // trigger on one packet only eC011_UNMARKED_DISCONTINUITY_THRESHOLD_2_PKTS = 0x00000001, // trigger on 2 consecutive packets only } eC011_UNMARKED_DISCONTINUITY_THRESHOLD; /* display resolution */ /* - eCMD_C011_DEC_CHAN_VIDEO_OUTPUT */ typedef enum { eC011_RESOLUTION_CUSTOM = 0x00000000, // custom eC011_RESOLUTION_480i = 0x00000001, // 480i eC011_RESOLUTION_1080i = 0x00000002, // 1080i (1920x1080, 60i) eC011_RESOLUTION_NTSC = 0x00000003, // NTSC (720x483, 60i) eC011_RESOLUTION_480p = 0x00000004, // 480p (720x480, 60p) eC011_RESOLUTION_720p = 0x00000005, // 720p (1280x720, 60p) eC011_RESOLUTION_PAL1 = 0x00000006, // PAL_1 (720x576, 50i) eC011_RESOLUTION_1080i25 = 0x00000007, // 1080i25 (1920x1080, 50i) eC011_RESOLUTION_720p50 = 0x00000008, // 720p50 (1280x720, 50p) eC011_RESOLUTION_576p = 0x00000009, // 576p (720x576, 50p) eC011_RESOLUTION_1080i29_97 = 0x0000000A, // 1080i (1920x1080, 59.94i) eC011_RESOLUTION_720p59_94 = 0x0000000B, // 720p (1280x720, 59.94p) eC011_RESOLUTION_SD_DVD = 0x0000000C, // SD DVD (720x483, 60i) eC011_RESOLUTION_480p656 = 0x0000000D, // 480p (720x480, 60p), output bus width 8 bit, clock 74.25MHz. eC011_RESOLUTION_1080p23_976 = 0x0000000E, // 1080p23_976 (1920x1080, 23.976p) eC011_RESOLUTION_720p23_976 = 0x0000000F, // 720p23_976 (1280x720p, 23.976p) eC011_RESOLUTION_240p29_97 = 0x00000010, // 240p (1440x240, 29.97p ) eC011_RESOLUTION_240p30 = 0x00000011, // 240p (1440x240, 30p) eC011_RESOLUTION_288p25 = 0x00000012, // 288p (1440x288p, 25p) eC011_RESOLUTION_1080p29_97 = 0x00000013, // 1080p29_97 (1920x1080, 29.97p) eC011_RESOLUTION_1080p30 = 0x00000014, // 1080p30 (1920x1080, 30p) eC011_RESOLUTION_1080p24 = 0x00000015, // 1080p24 (1920x1080, 24p) eC011_RESOLUTION_1080p25 = 0x00000016, // 1080p25 (1920x1080, 25p) eC011_RESOLUTION_720p24 = 0x00000017, // 720p24 (1280x720, 25p) eC011_RESOLUTION_720p29_97 = 0x00000018, // 720p29_97 (1280x720, 29.97p) } eC011_RESOLUTION; /* output scanning mode */ /* - eCMD_C011_DEC_CHAN_VIDEO_OUTPUT */ typedef enum { eC011_SCAN_MODE_PROGRESSIVE = 0x00000000, // progressive frames eC011_SCAN_MODE_INTERLACED = 0x00000001, // interlaced fields } eC011_SCAN_MODE; /* display option */ /* - eCMD_C011_DEC_CHAN_VIDEO_OUTPUT */ typedef enum { eC011_DISPLAY_LETTERBOX = 0x00000000, // letter box eC011_DISPLAY_FULLSCREEN = 0x00000001, // full screen eC011_DISPLAY_PILLARBOX = 0x00000002, // pillar box } eC011_DISPLAY_OPTION; /* display formatting */ /* - eCMD_C011_DEC_CHAN_VIDEO_OUTPUT */ typedef enum { eC011_FORMATTING_AUTO = 0x00000000, // automatic eC011_FORMATTING_CUSTOM = 0x00000001, // custom eC011_FORMATTING_NONE = 0x00000002, // no formatting eC011_FORMATTING_PICTURE = 0x00000003, // picture level } eC011_FORMATTING; /* vsync mode */ /* - eCMD_C011_DEC_CHAN_VIDEO_OUTPUT */ typedef enum { eC011_VSYNC_MODE_NORMAL = 0x00000000, // internal video timing eC011_VSYNC_MODE_EXTERNAL = 0x00000001, // use external vsync_in signal eC011_VSYNC_MODE_BYPASS = 0x00000002, // 7411 updates STC from PCR in stream, but external vsync eC011_VSYNC_MODE_INTERNAL = 0x00000003, // User updates STC, but internal vsync } eC011_VSYNC_MODE; /* output clipping mode */ /* - eCMD_C011_DEC_CHAN_VIDEO_OUTPUT */ typedef enum { eC011_OUTPUT_CLIPPING_BT601 = 0x00000000, // Luma pixel is clipped to [16,235]. Chroma pixel is clipped to [16,240] eC011_OUTPUT_CLIPPING_BT1120 = 0x00000001, // The pixel is clipped to [1,254] eC011_OUTPUT_CLIPPING_NONE = 0x00000002, // No output clipping } eC011_OUTPUT_CLIPPING; /* display mode for pause/slow/fastforward*/ /* - eCMD_C011_DEC_CHAN_VIDEO_OUTPUT */ typedef enum { eC011_DISPLAY_MODE_AUTO = 0x00000000, eC011_DISPLAY_MODE_FRAME = 0x00000001, eC011_DISPLAY_MODE_TOP = 0x00000002, eC011_DISPLAY_MODE_BOTTOM = 0x00000003, } eC011_DISPLAY_MODE; /*order in timeline where the pauseUntoPts and displayUntoPts occur*/ typedef enum { eC011_PAUSE_UNTO_PTS_ONLY = 0x00000001, eC011_DISPLAY_UNTO_PTS_ONLY = 0x00000002, eC011_DISPLAY_UNTO_PTS_LESSER_THAN_PAUSE_UNTO_PTS = 0x00000003, eC011_DISPLAY_UNTO_PTS_GREATER_THAN_PAUSE_UNTO_PTS = 0x00000004, } eC011_DISPLAY_PAUSE_STATE; /* scaling on/off */ /* - eCMD_C011_DEC_CHAN_OUTPUT_FORMAT */ typedef enum { eC011_SCALING_OFF = 0x00000000, eC011_SCALING_ON = 0x00000001, } eC011_SCALING; /* edge control */ /* - eCMD_C011_DEC_CHAN_OUTPUT_FORMAT */ typedef enum { eC011_EDGE_CONTROL_NONE = 0x00000000, // no cropping or padding eC011_EDGE_CONTROL_CROP = 0x00000001, // cropping eC011_EDGE_CONTROL_PAD = 0x00000002, // padding } eC011_EDGE_CONTROL; /* deinterlacing on/off */ /* - eCMD_C011_DEC_CHAN_OUTPUT_FORMAT */ typedef enum { eC011_DEINTERLACING_OFF = 0x00000000, eC011_DEINTERLACING_ON = 0x00000001, } eC011_DEINTERLACING; /* scaling target */ /* - eCMD_C011_DEC_CHAN_SCALING_FILTERS */ typedef enum { eC011_HORIZONTAL = 0x00000000, eC011_VERTICAL_FRAME = 0x00000001, eC011_VERTICAL_FIELD_TOP = 0x00000002, eC011_VERTICAL_FIELD_BOTTOM = 0x00000003, } eC011_SCALING_TARGET; /* normalization */ /* - eCMD_C011_DEC_CHAN_SCALING_FILTERS */ typedef enum { eC011_NORMALIZATION_128 = 0x00000000, // divide by 128 eC011_NORMALIZATION_64 = 0x00000001, // divide by 64 } eC011_NORMALIZATION; /* pause type */ /* - eCMD_C011_DEC_CHAN_PAUSE_OUTPUT */ typedef enum { eC011_PAUSE_TYPE_RESUME = 0x00000000, // resume video output eC011_PAUSE_TYPE_CURRENT = 0x00000001, // pause video on current frame eC011_PAUSE_TYPE_BLACK = 0x00000002, // pause video with black screen eC011_PAUSE_TYPE_STEP = 0x00000003, // display next picture } eC011_PAUSE_TYPE; /* TSD audio payload type */ /* - eCMD_C011_DEC_CREATE_AUDIO_CONTEXT */ typedef enum { eC011_TSD_AUDIO_PAYLOAD_MPEG1 = 0x00000000, eC011_TSD_AUDIO_PAYLOAD_AC3 = 0x00000001, } eC011_TSD_AUDIO_PAYLOAD_TYPE; /* CDB extract bytes for PES */ /* - eCMD_C011_DEC_CREATE_AUDIO_CONTEXT */ typedef enum { eC011_PES_CDB_EXTRACT_0_BYTES = 0x00000000, eC011_PES_CDB_EXTRACT_1_BYTE = 0x00000001, eC011_PES_CDB_EXTRACT_4_BYTES = 0x00000002, eC011_PES_CDB_EXTRACT_7_BYTES = 0x00000003, } eC011_PES_CDB_EXTRACT_BYTES; /* audio payload info */ /* - eCMD_C011_DEC_CREATE_AUDIO_CONTEXT */ typedef union DecAudioPayloadInfo { eC011_TSD_AUDIO_PAYLOAD_TYPE payloadType; eC011_PES_CDB_EXTRACT_BYTES extractBytes; } uC011_AUDIO_PAYLOAD_INFO; /* descrambling mode */ /* - eCMD_C011_DEC_CHAN_SET_DECYPTION */ typedef enum { eC011_DESCRAMBLING_3DES = 0x00000000, eC011_DESCRAMBLING_DES = 0x00000001, } eC011_DESCRAMBLING_MODE; /* key exchange */ /* - eCMD_C011_DEC_CHAN_SET_DECYPTION */ typedef enum { eC011_KEY_EXCHANGE_EVEN_0 = 0x00000001, eC011_KEY_EXCHANGE_EVEN_1 = 0x00000002, eC011_KEY_EXCHANGE_EVEN_2 = 0x00000004, eC011_KEY_EXCHANGE_ODD_0 = 0x00000010, eC011_KEY_EXCHANGE_ODD_1 = 0x00000020, eC011_KEY_EXCHANGE_ODD_2 = 0x00000040, } eC011_KEY_EXCHANGE_MODE; /* cipher text stealing */ /* - eCMD_C011_DEC_CHAN_SET_DECYPTION */ typedef enum { eC011_CT_STEALING_MODE_OFF = 0x00000000, eC011_CT_STEALING_MODE_ON = 0x00000001, } eC011_CT_STEALING_MODE; /* pause mode */ /* - eCMD_C011_DEC_CHAN_PAUSE */ typedef enum { eC011_PAUSE_MODE_OFF = 0x00000000, eC011_PAUSE_MODE_ON = 0x00000001, } eC011_PAUSE_MODE; /* skip pic mode */ /* - eCMD_C011_DEC_CHAN_SET_SKIP_PIC_MODE */ typedef enum { eC011_SKIP_PIC_IPB_DECODE = 0x00000000, eC011_SKIP_PIC_IP_DECODE = 0x00000001, eC011_SKIP_PIC_I_DECODE = 0x00000002, } eC011_SKIP_PIC_MODE; /* enum for color space conversion */ typedef enum { eC011_DEC_CSC_CTLBYDEC = 0x00000000, eC011_DEC_CSC_ENABLE = 0x00000001, eC011_DEC_CSC_DISABLE = 0x00000002, } eC011_DEC_CSC_SETUP; /* enum for setting range remap */ typedef enum { eC011_DEC_RANGE_REMAP_VIDCTL = 0x00000000, eC011_DEC_RANGE_REMAP_ENABLE = 0x00000001, eC011_DEC_RANGE_REMAP_DISABLE = 0x00000002, } eC011_DEC_RANGE_REMAP_SETUP; typedef enum { eC011_DEC_OPERATION_MODE_GENERIC = 0x00000000, eC011_DEC_OPERATION_MODE_BLURAY = 0x00000001, eC011_DEC_OPERATION_MODE_HDDVD = 0x00000002, } eC011_DEC_OPERATION_MODE; typedef enum { eC011_DEC_RANGE_REMAP_ADVANCED = 0x00000000, eC011_DEC_RANGE_REMAP_MAIN = 0x00000001, } eC011_DEC_RANGE_REMAP_VC1PROFILE; /* encoder sequence paramaters */ /* - eCMD_C011_ENC_CHAN_OPEN */ /* - eCMD_C011_ENC_CHAN_CONTROL */ typedef struct { uint32_t seqParamId; // sequence parameter set ID uint32_t profile; // profile (E_ENC_PROFILE) uint32_t level; // level x 10 uint32_t constraintMap; // bitmap for constraint sets uint32_t frameNumMaxLog; // logorithm of frame number max uint32_t pocLsbMaxLog; // logorithm of POC LSB max uint32_t pocType; // POC type uint32_t refFrameMax; // number of reference frames uint32_t frameMBHeight; // frame height in MB uint32_t frameMBWidth; // frame width in MB uint32_t frameMBOnly; // frame MB only flag uint32_t adaptMB; // MBAFF flag uint32_t dir8x8Infer; // direct 8x8 inference flag } sC011_ENC_SEQ_PARAM; /* encoder picture parameters */ /* - eCMD_C011_ENC_CHAN_OPEN */ /* - eCMD_C011_ENC_CHAN_CONTROL */ typedef struct { uint32_t picParamId; // picture parameter set ID uint32_t seqParameterId; // sequence parameter set ID uint32_t refIdxMaxL0; // number of active reference indices uint32_t refIdxMaxL1; // number of active reference indices uint32_t entMode; // entropy mode (E_ENC_ENT_MODE) uint32_t initQP; // picture init QP uint32_t intraConst; // constrained intra prediction flag } sC011_ENC_PIC_PARAM; /* encoder coding parameters */ /* - eCMD_C011_ENC_CHAN_OPEN */ /* - eCMD_C011_ENC_CHAN_CONTROL */ typedef struct { uint32_t eventNfy; // event notify generation flag uint32_t intMode; // interlace coding mode (E_ENC_INT_MODE) uint32_t gopSize; // number of frames per GOP (I frame period) uint32_t gopStruct; // number of B-frames between references uint32_t rateCtrlMode; // rate control mode (E_ENC_RATE_CTRL_MODE) uint32_t frameRate; // frame rate uint32_t constQP; // constant QP uint32_t bitratePeriod; // VBR bitrate average period (in GOPs) uint32_t bitRateAvg; // VBR average bitrate uint32_t bitRateMax; // VBR max bitrate uint32_t bitRateMin; // VBR min bitrate } sC011_ENC_CODING_PARAM; /* encoder video-in parameters */ /* - eCMD_C011_ENC_CHAN_OPEN */ /* - eCMD_C011_ENC_CHAN_CONTROL */ typedef struct { uint32_t picInfoMode; // picture info mode (E_ENC_PIC_INFO_MODE) uint32_t picIdSrc; // picture ID source (E_ENC_PIC_ID_SRC) uint32_t picYUVFormat; // picture YUV format (E_ENC_PIC_YUV_FORMAT) uint32_t picIntFormat; // picture interlace format (E_ENC_PIC_INT_FORMAT) } sC011_ENC_VID_IN_PARAM; /* encoder code-out parameters */ /* - eCMD_C011_ENC_CHAN_OPEN */ /* - eCMD_C011_ENC_CHAN_CONTROL */ typedef struct { uint32_t portId; // port ID uint32_t codeFormat; // code format (E_ENC_CODE_FORMAT) uint32_t delimiter; // delimiter NAL flag uint32_t endOfSeq; // end of sequence NAL flag uint32_t endOfStream; // end of stream NAL flag uint32_t picParamPerPic; // picture parameter set per picture flag uint32_t seiMasks; // SEI message (1 << E_ENC_SEI_TYPE) } sC011_ENC_CODE_OUT_PARAM; /* encoder picture data */ /* - eCMD_C011_ENC_CHAN_CONTROL */ typedef struct { uint32_t picId; // picture ID uint32_t picStruct; // picture structure (E_ENC_PIC_STRUCT) uint32_t origBuffIdx; // original frame buffer index uint32_t reconBuffIdx; // reconstructed frame buffer index } sC011_ENC_PIC_DATA; /* encoder channel control parameter type */ /* - eCMD_C011_ENC_CHAN_CONTROL */ typedef enum { eC011_ENC_CTRL_SEQ_PARAM = 0x00000000, eC011_ENC_CTRL_PIC_PARAM = 0x00000001, eC011_ENC_CTRL_CODING_PARAM = 0x00000002, eC011_ENC_CTRL_PIC_DATA = 0x00000003, } eC011_ENC_CTRL_CODE; /* encoder channel control parameter */ /* - eCMD_C011_ENC_CHAN_CONTROL */ typedef union EncCtrlParam { sC011_ENC_SEQ_PARAM seqParams; sC011_ENC_PIC_PARAM picParams; sC011_ENC_CODING_PARAM codingParams; sC011_ENC_PIC_DATA picData; } uC011_ENC_CTRL_PARAM; /* * Data Structures for the API commands above */ #define DMA_CIQ_DEPTH 64 /* dsDmaCtrlInfo */ typedef struct { uint32_t dmaSrcAddr; /* word 0: src addr */ uint32_t dmaDstAddr; /* word 1: dst addr */ uint32_t dmaXferCtrol; /* word 2: * bit 31-30. reserved * bit 29. Stream number * bit 28-27. Interrupt * x0: no interrupt; * 01: interrupt when dma done wo err * 11: interrupt only if there is err * bit 26. Endidan. 0: big endian; 1: little endian * bit 25. dst inc. 0: addr doesn't change; 1: addr+=4 * bit 24. src inc. 0: addr doesn't change; 1: addr+=4 * bit 23-0. number of bytes to be transfered */ } dsDmaCtrlInfo; /* dsDmaCtrlInfoQueue */ typedef struct { uint32_t readIndex; uint32_t writeIndex; dsDmaCtrlInfo dmaCtrlInfo[DMA_CIQ_DEPTH]; } dsDmaCtrlInfoQueue; /* Init */ typedef struct { uint32_t command; uint32_t sequence; uint32_t memSizeMBytes; uint32_t inputClkFreq; uint32_t uartBaudRate; uint32_t initArcs; eC011_INT_CONTROL interrupt; uint32_t audioMemSize; eC011_BRCM_MODE brcmMode; uint32_t fgtEnable; /* 0 - disable FGT, 1 - enable FGT */ uint32_t DramLogEnable; /* 0 - disable DramLog, 1 - enable DramLog */ uint32_t sidMemorySize; /* in bytes */ uint32_t dmaDataXferEnable; /* 0:disable; 1:enable */ uint32_t rsaDecrypt; /* 0:disable; 1:enable */ uint32_t openMode; uint32_t rsvd1; uint32_t rsvd2; uint32_t rsvd3; } C011CmdInit; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t commandBuffer; uint32_t responseBuffer; uint32_t blockPool; uint32_t blockSize; /* in words */ uint32_t blockCount; uint32_t audioMemBase; uint32_t watchMemAddr; uint32_t streamDramLogBase; uint32_t streamDramLogSize; uint32_t vdecOuterDramLogBase; uint32_t vdecOuterDramLogSize; uint32_t vdecInnerDramLogBase; uint32_t vdecInnerDramLogSize; uint32_t sidMemoryBaseAddr; uint32_t inputDmaCiqAddr; uint32_t inputDmaCiqReleaseAddr; uint32_t outputDmaCiqAddr; uint32_t outputDmaCiqReleaseAddr; uint32_t dramX509CertAddr; uint32_t rsvdAddr; } C011RspInit; /* Reset */ typedef struct { uint32_t command; uint32_t sequence; } C011CmdReset; /* SelfTest */ typedef struct { uint32_t command; uint32_t sequence; eC011_TEST_ID testId; uint32_t mode; uint32_t height; uint32_t width; uint32_t rsvd[5]; } C011CmdSelfTest; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t errorCode; } C011RspSelfTest; /* GetVersion */ typedef struct { uint32_t command; uint32_t sequence; } C011CmdGetVersion; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t streamSwVersion; uint32_t decoderSwVersion; uint32_t chipHwVersion; uint32_t reserved1; uint32_t reserved2; uint32_t reserved3; uint32_t reserved4; uint32_t blockSizePIB; uint32_t blockSizeChannelStatus; uint32_t blockSizePPB; uint32_t blockSizePPBprotocolMpeg; uint32_t blockSizePPBprotocolH264; uint32_t blockSizePPBprotocolRsvd; } C011RspGetVersion; /* GPIO */ typedef struct { uint32_t command; uint32_t sequence; eC011_GPIO_CONTROL gpioControl; } C011CmdGPIO; /* DebugSetup */ typedef struct { uint32_t command; uint32_t sequence; uint32_t paramMask; uint32_t debugARCs; uint32_t debugARCmode; uint32_t outPort; uint32_t clock; uint32_t channelId; uint32_t enableRVCcapture; uint32_t playbackMode; uint32_t enableCRCinterrupt; uint32_t esStartDelay10us; } C011CmdDebugSetup; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t DQ; uint32_t DRQ; } C011RspDebugSetup; /* DecChannelOpen */ typedef struct { uint32_t command; uint32_t sequence; eC011_INPUT_PORT inPort; eC011_OUTPUT_PORT outVidPort; eC011_STREAM_TYPE streamType; eC011_MAX_PICSIZE maxPicSize; eC011_OUTCTRL_MODE outCtrlMode; eC011_CHANNEL_TYPE chanType; uint32_t reservedWord8; eC011_VIDEO_ALG videoAlg; eC011_VIDEO_SOURCE_MODE sourceMode; eC011_PULLDOWN_MODE pulldown; eC011_PICTURE_INFO_MODE picInfo; eC011_DISPLAY_ORDER displayOrder; uint32_t reservedWord14; uint32_t reservedWord15; uint32_t streamId; /* for multi-stream */ eC011_DEBLOCKING_MODE deblocking; eC011_EXTERNAL_VCXO_MODE vcxoControl; eC011_DISPLAY_TIMING_MODE displayTiming; int32_t videoDisplayOffset; eC011_USER_DATA_MODE userDataMode; uint32_t enableUserDataInterrupt; uint32_t ptsStcDiffThreshold; uint32_t stcPtsDiffThreshold; uint32_t enableFirstPtsInterrupt; uint32_t enableStcPtsThresholdInterrupt; uint32_t frameRateDefinition; uint32_t hostDmaInterruptEnable; uint32_t asynchEventNotifyEnable; uint32_t enablePtsStcChangeInterrupt; uint32_t enablePtsErrorInterrupt; uint32_t enableFgt; uint32_t enable23_297FrameRateOutput; uint32_t enableVideoDataUnderflowInterrupt; uint32_t reservedWord35; uint32_t pictureInfoInterruptEnable; } DecCmdChannelOpen; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t channelId; uint32_t picBuf; uint32_t picRelBuf; uint32_t picInfoDeliveryQ; uint32_t picInfoReleaseQ; uint32_t channelStatus; uint32_t userDataDeliveryQ; uint32_t userDataReleaseQ; uint32_t transportStreamCaptureAddr; uint32_t asyncEventQ; } DecRspChannelOpen; /* DecChannelClose */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_PIC_REL_MODE pictureRelease; eC011_LASTPIC_DISPLAY lastPicDisplay; } DecCmdChannelClose; /* DecChannelActivate */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t dbgMode; } DecCmdChannelActivate; //For Single Field typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t SingleField; } DecCmdChannelSingleField; /* DecChannelStatus */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } DecCmdChannelStatus; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t channelStatus; uint32_t cpbSize; /* CPB size */ uint32_t cpbFullness; /* CPB fullness */ uint32_t binSize; /* BIN buffer size */ uint32_t binFullness; /* BIN buffer fullness */ uint32_t bytesDecoded; /* Bytes decoded */ uint32_t nDelayed; /* pics with delayed delivery */ } DecRspChannelStatus; /* DecChannelFlush */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_FLUSH_MODE flushMode; } DecCmdChannelFlush; /* DecChannelTrickPlay */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_DIR direction; eC011_SPEED speed; } DecCmdChannelTrickPlay; /* DecChannelSetTSPIDs */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t pcrPid; uint32_t videoPid; uint32_t videoSubStreamId; } DecCmdChannelSetTSPIDs; /* DecChannelSetPcrPID */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t pcrPid; } DecCmdChannelSetPcrPID; /* DecChannelSetVideoPID */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t videoPid; uint32_t videoSubStreamId; } DecCmdChannelSetVideoPID; /* DecChannelSetPSStreamIDs */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t videoStreamId; uint32_t videoStreamIdExtEnable; uint32_t videoStreamIdExt; } DecCmdChannelSetPSStreamIDs; /* DecChannelSetInputParams */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_SYNC_MODE syncMode; eC011_UNMARKED_DISCONTINUITY_MODE discontinuityNotify; eC011_UNMARKED_DISCONTINUITY_THRESHOLD discontinuityPktThreshold; uint32_t discontinuityThreshold; uint32_t disableFlowControl; uint32_t disablePCROffset; } DecCmdChannelSetInputParams; /* DecChannelSetVideoOutput */ typedef struct { uint32_t command; uint32_t sequence; eC011_OUTPUT_PORT portId; eC011_RESOLUTION resolution; uint32_t width; uint32_t height; eC011_SCAN_MODE scanMode; uint32_t picRate; eC011_DISPLAY_OPTION option; eC011_FORMATTING formatMode; eC011_VSYNC_MODE vsyncMode; uint32_t numOsdBufs; uint32_t numCcDataBufs; uint32_t memOut; eC011_OUTPUT_CLIPPING outputClipping; uint32_t invertHddviSync; eC011_DISPLAY_MODE pauseMode; eC011_DISPLAY_MODE slowMode; eC011_DISPLAY_MODE ffMode; uint32_t vppPaddingValue; /* bits: 23-16 (Y), 15-8 (U), 7-0 (V) */ uint32_t extVideoClock; uint32_t hddviEnable; uint32_t numDramOutBufs; } DecCmdChannelSetVideoOutput; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t osdBuf1; uint32_t osdBuf2; uint32_t ccDataBuf1; uint32_t ccDataBuf2; uint32_t memOutBuf; } DecRspChannelSetVideoOutput; /* DecChannelSetCustomVidOut */ typedef struct { uint32_t command; uint32_t sequence; eC011_OUTPUT_PORT portId; uint32_t spl; uint32_t spal; uint32_t e2e; uint32_t lpf; uint32_t vlpf; uint32_t vbsf1; uint32_t vbff1; uint32_t vbsf2; uint32_t vbff2; uint32_t f1id; uint32_t f2id; uint32_t gdband; uint32_t vsdf0; uint32_t vsdf1; uint32_t hsyncst; uint32_t hsyncsz; uint32_t vsstf1; uint32_t vsszf1; uint32_t vsstf2; uint32_t vsszf2; uint32_t bkf1; uint32_t bkf2; uint32_t invertsync; uint32_t wordmode; uint32_t hdclock; } DecCmdChannelSetCustomVidOut; /* DecChannelSetOutputFormatting */ typedef struct { uint32_t command; uint32_t sequence; eC011_OUTPUT_PORT portId; eC011_SCALING horizontalScaling; eC011_SCALING verticalScaling; uint32_t horizontalPhases; uint32_t verticalPhases; eC011_EDGE_CONTROL horizontalEdgeControl; eC011_EDGE_CONTROL verticalEdgeControl; uint32_t leftSize; uint32_t rightSize; uint32_t topSize; uint32_t bottomSize; uint32_t horizontalSize; uint32_t verticalSize; int32_t horizontalOrigin; int32_t verticalOrigin; uint32_t horizontalCropSize; uint32_t verticalCropSize; uint32_t lumaTopFieldOffset; uint32_t lumaBottomFieldOffset; uint32_t chromaTopFieldOffset; uint32_t chromaBottomFieldOffset; eC011_SCAN_MODE inputScanMode; eC011_DEINTERLACING deinterlacing; uint32_t horizontalDecimation_N; uint32_t horizontalDecimation_M; uint32_t verticalDecimation_N; uint32_t verticalDecimation_M; uint32_t horizontalDecimationVector [4]; uint32_t verticalDecimationVector [4]; } DecCmdChannelSetOutputFormatting; /* DecCmdChannelSetPictureOutputFormatting */ typedef struct { uint32_t command; uint32_t sequence; eC011_OUTPUT_PORT portId; eC011_SCALING horizontalScaling; eC011_SCALING verticalScaling; uint32_t horizontalPhases; uint32_t verticalPhases; eC011_EDGE_CONTROL horizontalEdgeControl; eC011_EDGE_CONTROL verticalEdgeControl; uint32_t leftSize; uint32_t rightSize; /* 10 */ uint32_t topSize; uint32_t bottomSize; uint32_t horizontalSize; uint32_t verticalSize; int32_t horizontalOrigin; int32_t verticalOrigin; uint32_t horizontalCropSize; uint32_t verticalCropSize; uint32_t lumaTopFieldOffset; uint32_t lumaBottomFieldOffset; /* 20 */ uint32_t chromaTopFieldOffset; uint32_t chromaBottomFieldOffset; eC011_SCAN_MODE inputScanMode; eC011_DEINTERLACING deinterlacing; uint32_t horizontalDecimationFactor; /* bits: 0-7 N; 8-15 M */ uint32_t verticalDecimationFactor; /* bits: 0-7 Np; 8-15 Mp; 16-23 Ni; 24-31 Mi*/ uint32_t horizontalDecimationOutputSize; uint32_t verticalDecimationOutputSize; uint32_t horizontalScalingFactor; /* bits: 0-7 N; 8-15 M */ uint32_t verticalScalingFactorProgressive; /* bits: 0-7 Nt; 8-15 Mt; 16-23 Nb; 24-31 Mb*/ uint32_t verticalScalingFactorInterlace; /* bits: 0-7 Nt; 8-15 Mt; 16-23 Nb; 24-31 Mb*/ uint32_t Reserved[5]; } DecCmdChannelSetPictureOutputFormatting; /* DecChannelSetScalingFilters */ typedef struct { uint32_t command; uint32_t sequence; eC011_OUTPUT_PORT portId; eC011_SCALING_TARGET target; uint32_t pixelPos; uint32_t increment; int32_t lumaCoeff1; int32_t lumaCoeff2; int32_t lumaCoeff3; int32_t lumaCoeff4; int32_t lumaCoeff5; eC011_NORMALIZATION lumaNormalization; int32_t chromaCoeff1; int32_t chromaCoeff2; int32_t chromaCoeff3; eC011_NORMALIZATION chromaNormalization; } DecCmdChannelSetScalingFilters; /* DecChannelOsdMode */ typedef struct { uint32_t command; uint32_t sequence; eC011_OUTPUT_PORT portId; uint32_t osdBuffer; uint32_t fullRes; } DecCmdChannelOsdMode; /* DecChannelCcMode */ typedef struct { uint32_t command; uint32_t sequence; eC011_OUTPUT_PORT portId; uint32_t ccBuffer; } DecCmdChannelCcDataMode; /* DecChannelDrop */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t numPicDrop; eC011_DROP_TYPE dropType; } DecCmdChannelDrop; /* DecChannelRelease */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t picBuffer; } DecCmdChannelRelease; /* DecChannelStreamSettings */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t pcrDelay; } DecCmdChannelStreamSettings; /* DecChannelPauseVideoOutput */ typedef struct { uint32_t command; uint32_t sequence; eC011_OUTPUT_PORT portId; eC011_PAUSE_TYPE action; } DecCmdChannelPauseVideoOutput; /* DecChannelChange */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t pcrPid; uint32_t videoPid; uint32_t audio1Pid; uint32_t audio2Pid; uint32_t audio1StreamId; uint32_t audio2StreamId; } DecCmdChannelChange; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t channelId; uint32_t picBuf; uint32_t picRelBuf; } DecRspChannelChange; /* DecChannelSetSTC */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t stcValue0; uint32_t stcValue1; } DecCmdChannelSetSTC; /* DecChannelSetPTS */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t ptsValue0; uint32_t ptsValue1; } DecCmdChannelSetPTS; /* DecCreateAudioContext */ typedef struct { uint32_t command; uint32_t sequence; uint32_t contextId; uint32_t inPort; uint32_t streamId; uint32_t subStreamId; uC011_AUDIO_PAYLOAD_INFO payloadInfo; uint32_t cdbBaseAddress; uint32_t cdbEndAddress; uint32_t itbBaseAddress; uint32_t itbEndAddress; uint32_t streamIdExtension; } DecCmdCreateAudioContext; /* DecCopyAudioContext */ typedef struct { uint32_t command; uint32_t sequence; uint32_t cdbBaseAddress; uint32_t cdbEndAddress; uint32_t itbBaseAddress; uint32_t itbEndAddress; } DecCmdCopyAudioContext; /* DecDeleteAudioContext */ typedef struct { uint32_t command; uint32_t sequence; uint32_t contextId; } DecCmdDeleteAudioContext; /* DecSetDecryption */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_DESCRAMBLING_MODE descramMode; uint32_t evenKey0; uint32_t evenKey1; uint32_t evenKey2; uint32_t evenKey3; uint32_t oddKey0; uint32_t oddKey1; uint32_t oddKey2; uint32_t oddKey3; eC011_KEY_EXCHANGE_MODE keyExchangeMode; eC011_CT_STEALING_MODE cipherTextStealingMode; } DecCmdSetDecryption; /* DecChanPicCapture */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } DecCmdChanPicCapture; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t pibAddress; } DecRspChanPicCapture; /* DecChanPause */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_PAUSE_MODE enableState; } DecCmdChannelPause; /* DecChanPauseState */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } DecCmdChannelPauseState; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; eC011_PAUSE_MODE pauseState; } DecRspChannelPauseState; /* DecChanSetSlowMotionRate */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t rate; // 1 -> 1x (normal speed), 2 -> 2x slower, etc } DecCmdChannelSetSlowMotionRate; /* DecChanGetSlowMotionRate */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } DecCmdChannelGetSlowMotionRate; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t rate; // 1 -> 1x (normal speed), 2 -> 2x slower, etc } DecRspChannelGetSlowMotionRate; /* DecChanSetFFRate */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t rate; // 1 -> 1x (normal speed), 2 -> 2x faster, etc } DecCmdChannelSetFFRate; /* DecChanGetFFRate */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } DecCmdChannelGetFFRate; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t rate; // 1 -> 1x (normal speed), 2 -> 2x faster, etc } DecRspChannelGetFFRate; /* DecChanFrameAdvance */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } DecCmdChannelFrameAdvance; /* DecChanSetSkipPictureMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_SKIP_PIC_MODE skipMode; } DecCmdChannelSetSkipPictureMode; /* DecChanGetSkipPictureMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } DecCmdChannelGetSkipPictureMode; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; eC011_SKIP_PIC_MODE skipMode; } DecRspChannelGetSkipPictureMode; /* DecChanFillPictureBuffer */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t yuvValue; } DecCmdChannelFillPictureBuffer; /* DecChanSetContinuityCheck */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t enable; } DecCmdChannelSetContinuityCheck; /* DecChanGetContinuityCheck */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } DecCmdChannelGetContinuityCheck; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t enable; } DecRspChannelGetContinuityCheck; /* DecChanSetBRCMTrickMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t enable; uint32_t reverseField; } DecCmdChannelSetBRCMTrickMode; /* DecChanGetBRCMTrickMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } DecCmdChannelGetBRCMTrickMode; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t brcmTrickMode; } DecRspChannelGetBRCMTrickMode; /* DecChanReverseFieldStatus */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } DecCmdChannelReverseFieldStatus; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t reverseField; } DecRspChannelReverseFieldStatus; /* DecChanIPictureFound */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } DecCmdChannelIPictureFound; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t iPictureFound; } DecRspChannelIPictureFound; /* DecCmdChannelSetParameter */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; int32_t videoDisplayOffset; int32_t ptsStcPhaseThreshold; /* add more paras below ... */ } DecCmdChannelSetParameter; /* DecCmdChannelSetUserDataMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t enable; } DecCmdChannelSetUserDataMode; /* DecCmdChannelSetPauseDisplayMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_DISPLAY_MODE displayMode; } DecCmdChannelSetPauseDisplayMode; /* DecCmdChannelSetSlowDisplayMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_DISPLAY_MODE displayMode; } DecCmdChannelSetSlowDisplayMode; /* DecCmdChannelSetFastForwardDisplayMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_DISPLAY_MODE displayMode; } DecCmdChannelSetFastForwardDisplayMode; /* DecCmdChannelSetDisplayMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_DISPLAY_MODE displayMode; } DecCmdChannelSetDisplayMode; /* DecCmdChannelGetDisplayMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } DecCmdChannelGetDisplayMode; /* DecRspChannelGetDisplayMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t status; eC011_DISPLAY_MODE displayMode; } DecRspChannelGetDisplayMode; /* DecCmdChannelSetReverseField */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t enable; } DecCmdChannelSetReverseField; /* DecCmdChannelSetDisplayTimingMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_DISPLAY_TIMING_MODE displayTiming; } DecCmdChannelSetDisplayTimingMode; /* DecCmdChannelStreamOpen */ typedef struct { uint32_t command; uint32_t sequence; eC011_INPUT_PORT inPort; eC011_STREAM_TYPE streamType; } DecCmdChannelStreamOpen; /*DecCmdChannelChannelOpen*/ typedef struct { uint32_t command; uint32_t sequence; eC011_INPUT_PORT inPort; uint32_t outVidPort; eC011_STREAM_TYPE streamType; uint32_t maxPicSize; uint32_t outCtrlMode; uint32_t chanType; uint32_t reservedWord8; eC011_VIDEO_ALG videoAlg; uint32_t sourceMode; uint32_t pulldown; uint32_t picInfo; uint32_t displayOrder; uint32_t reservedWord14; uint32_t reservedWord15; uint32_t streamId; /* for multi-stream */ uint32_t deblocking; uint32_t vcxoControl; uint32_t displayTiming; uint32_t videoDisplayOffset; uint32_t userDataMode; uint32_t enableUserDataInterrupt; uint32_t ptsStcDiffThreshold; uint32_t stcPtsDiffThreshold; uint32_t enableFirstPtsInterrupt; uint32_t enableStcPtsThresholdInterrupt; uint32_t frameRateDefinition; uint32_t hostDmaInterruptEnable; uint32_t asynchEventNotifyEnable; uint32_t enablePtsStcChangeInterrupt; uint32_t enablePtsErrorInterrupt; uint32_t enableFgt; uint32_t enable23_297FrameRateOutput; uint32_t enableVideoDataUnderflowInterrupt; uint32_t reservedWord35; uint32_t pictureInfoInterruptEnable; } DecCmdChannelChannelOpen; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t ChannelID; uint32_t picBuf; uint32_t picRelBuf; uint32_t picInfoDeliveryQ; uint32_t picInfoReleaseQ; uint32_t channelStatus; uint32_t userDataDeliveryQ; uint32_t userDataReleaseQ; uint32_t transportStreamCaptureAddr; uint32_t asyncEventQ; } DecRspChannelChannelOpen; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t channelId; uint32_t channelStatus; } DecRspChannelStreamOpen; /* DecChannelStartVideo */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_OUTPUT_PORT outVidPort; eC011_MAX_PICSIZE maxPicSize; eC011_OUTCTRL_MODE outCtrlMode; eC011_CHANNEL_TYPE chanType; uint32_t defaultFrameRate;//reservedWord7; eC011_VIDEO_ALG videoAlg; eC011_VIDEO_SOURCE_MODE sourceMode; eC011_PULLDOWN_MODE pulldown; eC011_PICTURE_INFO_MODE picInfo; eC011_DISPLAY_ORDER displayOrder; uint32_t decOperationMode; //reservedWord13; uint32_t MaxFrameRateMode;//reservedWord14; uint32_t streamId; eC011_DEBLOCKING_MODE deblocking; eC011_EXTERNAL_VCXO_MODE vcxoControl; eC011_DISPLAY_TIMING_MODE displayTiming; int32_t videoDisplayOffset; eC011_USER_DATA_MODE userDataMode; uint32_t enableUserDataInterrupt; uint32_t ptsStcDiffThreshold; uint32_t stcPtsDiffThreshold; uint32_t enableFirstPtsInterrupt; uint32_t enableStcPtsThresholdInterrupt; uint32_t frameRateDefinition; uint32_t hostDmaInterruptEnable; uint32_t asynchEventNotifyEnable; uint32_t enablePtsStcChangeInterrupt; uint32_t enablePtsErrorInterrupt; uint32_t enableFgt; uint32_t enable23_297FrameRateOutput; uint32_t enableVideoDataUnderflowInterrupt; uint32_t reservedWord34; uint32_t pictureInfoInterruptEnable; } DecCmdChannelStartVideo; typedef struct { uint32_t command; uint32_t sequence; uint32_t status; uint32_t picBuf; uint32_t picRelBuf; uint32_t picInfoDeliveryQ; uint32_t picInfoReleaseQ; uint32_t channelStatus; uint32_t userDataDeliveryQ; uint32_t userDataReleaseQ; uint32_t transportStreamCaptureAddr; uint32_t asyncEventQ; } DecRspChannelStartVideo; /* DecChannelStopVideo */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_PIC_REL_MODE pictureRelease; eC011_LASTPIC_DISPLAY lastPicDisplay; } DecCmdChannelStopVideo; /* DecCmdChannelSetPanScanMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; eC011_PAN_SCAN_MODE ePanScanMode; } DecCmdChannelSetPanScanMode; /* DecChannelStartDisplayAtPTS */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t ptsValue0; uint32_t ptsValue1; } DecCmdChannelStartDisplayAtPTS; /* DecChannelStopDisplayAtPTS */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t ptsValue0; uint32_t ptsValue1; } DecCmdChannelStopDisplayAtPTS; /* DecChannelDisplayPauseUntoPTS */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t pausePtsValue0; uint32_t pausePtsValue1; uint32_t displayPtsValue0; uint32_t displayPtsValue1; int32_t pauseLoopAroundCounter; int32_t displayLoopAroundCounter; int32_t pauseUntoPtsValid; int32_t displayUntoPtsValid; } DecCmdChannelDisplayPauseUntoPTS; /* DecCmdChanSetPtsStcDiffThreshold */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t ptsStcDiffThreshold; } DecCmdChanSetPtsStcDiffThreshold; /* DecChanSetDisplayOrder */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t decodeOrder; // 0: displayOrder, 1: decodeOrder } DecCmdChannelSetDisplayOrder; /* DecChanGetDisplayOrder */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } DecCmdChannelGetDisplayOrder; typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t decodeOrder; // 0: displayOrder, 1: decodeOrder } DecRspChannelGetDisplayOrder; typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t CodeInBuffLowerThreshold; uint32_t CodeInBuffHigherThreshold; int32_t MaxNumVsyncsCodeInEmpty; int32_t MaxNumVsyncsCodeInFull; } DecCmdChanSetParametersForHardResetInterruptToHost; /* EncChannelOpen */ typedef struct { uint32_t command; uint32_t sequence; sC011_ENC_SEQ_PARAM seqParam; // sequence paramaters sC011_ENC_PIC_PARAM picParam; // picture parameters sC011_ENC_CODING_PARAM codingParam; // coding parameters sC011_ENC_VID_IN_PARAM vidInParam; // video-in parameters sC011_ENC_CODE_OUT_PARAM codeOutParam; // code-out parameters } EncCmdChannelOpen; /* EncChannelClose */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t condClose; uint32_t lastPicId; } EncCmdChannelClose; /* EncChannelActivate */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } EncCmdChannelActivate; /* EncChannelControl */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t condControl; uint32_t picId; eC011_ENC_CTRL_CODE controlCode; uC011_ENC_CTRL_PARAM controlParam; } EncCmdChannelControl; /* EncChannelStatistics */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; } EncCmdChannelStatistics; /* DecChannelColorSpaceConv */ typedef struct { uint32_t command; uint32_t sequence; eC011_OUTPUT_PORT portId; eC011_DEC_CSC_SETUP enable; uint32_t padInput; /* if the padded pixels need to be converted. 1: input; 0:output */ uint32_t lumaCoefY; uint32_t lumaCoefU; uint32_t lumaDCOffset; uint32_t lumaOffset; uint32_t lumaCoefChrV; uint32_t chrUCoefY; uint32_t chrUCoefU; uint32_t chrUDCOffset; uint32_t chrUOffset; uint32_t chrUCoefChrV; uint32_t chrVCoefY; uint32_t chrVCoefU; uint32_t chrVDCOffset; uint32_t chrVOffset; uint32_t chrVCoefChrV; } DecCmdChannelColorSpaceConv; typedef struct { uint32_t command; uint32_t sequence; eC011_OUTPUT_PORT portId; eC011_DEC_RANGE_REMAP_SETUP enable; eC011_DEC_RANGE_REMAP_VC1PROFILE vc1Profile; uint32_t lumaEnable; uint32_t lumaMultiplier; uint32_t chromaEnable; uint32_t chromaMultiplier; } DecCmdChannelSetRangeRemap; /* DecChanSetFgt */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t on; // 0: fgt off, 1: fgt on } DecCmdChannelSetFgt; /* DecChanSetLastPicturePadding */ typedef struct { uint32_t command; uint32_t sequence; eC011_OUTPUT_PORT portId; uint32_t paddingValue; // bits: 23-16 (Y), 15-8 (U), 7-0 (V) uint32_t padFullScreen; // 0: fgt off, 1: fgt on } DecCmdChannelSetLastPicturePadding; /* DecChanSetHostTrickMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t enable; /* 0:disable; 1:enable */ } DecCmdChannelSetHostTrickMode; /* DecChanSetOperationMode */ typedef struct { uint32_t command; uint32_t sequence; uint32_t reserved; eC011_DEC_OPERATION_MODE mode; } DecCmdChannelSetOperationMode; /* DecChanSendCompressedBuffer */ typedef struct { uint32_t command; uint32_t sequence; uint32_t dramInBufAddr; uint32_t dataSizeInBytes; } DecCmdSendCompressedBuffer; /* DecChanSetClipping */ typedef struct { uint32_t command; uint32_t sequence; eC011_OUTPUT_PORT portId; eC011_OUTPUT_CLIPPING outputClipping; } DecCmdSetClipping; /* DecSetContentKey */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t flags; uint32_t inputKey0; // bits 31:0 uint32_t inputKey1; // bits 33:63 uint32_t inputKey2; uint32_t inputKey3; uint32_t inputIv0; // bits 31:0 uint32_t inputIv1; uint32_t inputIv2; uint32_t inputIv3; uint32_t outputKey0; uint32_t outputKey1; uint32_t outputKey2; uint32_t outputKey3; uint32_t outputIv0; uint32_t outputIv1; uint32_t outputIv2; uint32_t outputIv3; uint32_t outputStripeStart; // 0 based stripe encrypt start number, don't use 0 uint32_t outputStripeNumber; // 0 based number of stripes to encrypt uint32_t outputStripeLines; // 0 = 256 lines, otherwise actual number of lines, start on second line uint32_t outputStripeLineStart; // 0 based start line number uint32_t outputMode; uint32_t outputyScramLen; uint32_t outputuvLen; uint32_t outputuvOffset; uint32_t outputyLen; uint32_t outputyOffset; union { // Adaptive Output Encryption Percentages struct { uint32_t outputClearPercent:8; // Clear Percentage uint32_t outputEncryptPercent:8; // Encrypt Percentage uint32_t outputScramPercent:8; // Scramble Percentage uint32_t output422Mode:8; // 422 Mode } u; uint32_t outputPercentage; } adapt; uint32_t outputReserved1; } DecCmdSetContentKey; /* DecSetSessionKey */ typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t flags; uint32_t sessionData[32]; // 128 bytes of cipher data. } DecCmdSetSessionKey; typedef struct { uint32_t command; uint32_t sequence; uint32_t channelId; uint32_t flags; uint32_t reserved[4]; } DecCmdFormatChangeAck; /* common response structure */ typedef struct { uint32_t command; uint32_t sequence; uint32_t status; } C011RspReset, C011RspGPIO, DecRspChannelClose, DecRspChannelActivate, DecRspChannelFlush, DecRspChannelTrickPlay, DecRspChannelSetTSPIDs, DecRspChannelSetPcrPID, DecRspChannelSetVideoPID, DecRspChannelSetPSStreamIDs, DecRspChannelSetInputParams, DecRspChannelSetOutputFormatting, DecRspChannelSetScalingFilters, DecRspChannelOsdMode, DecRspChannelCcDataMode, DecRspChannelDrop, DecRspChannelRelease, DecRspChannelStreamSettings, DecRspChannelPauseVideoOutput, DecRspChannelSetSTC, DecRspChannelSetPTS, DecRspChannelSetCustomVidOut, DecRspCreateAudioContext, DecRspDeleteAudioContext, DecRspCopyAudioContext, DecRspSetDecryption, DecRspChannelPause, DecRspChannelSetSlowMotionRate, DecRspChannelSetFFRate, DecRspChannelFrameAdvance, DecRspChannelSetSkipPictureMode, DecRspChannelFillPictureBuffer, DecRspChannelSetContinuityCheck, DecRspChannelSetBRCMTrickMode, DecRspChannelSetDisplayOrder, EncRspChannelOpen, EncRspChannelClose, EncRspChannelActivate, EncRspChannelControl, EncRspChannelStatistics, EncNotifyChannelEvent, DecRspChannelSetParameter, DecRspChannelSetUserDataMode, DecRspChannelSetPauseDisplayMode, DecRspChannelSetSlowDisplayMode, DecRspChannelSetFastForwardDisplayMode, DecRspChannelSetDisplayTimingMode, DecRspChannelSetDisplayMode, DecRspChannelSetReverseField, DecRspChannelStopVideo, DecRspChannelSetPanScanMode, DecRspChannelStartDisplayAtPTS, DecRspChannelStopDisplayAtPTS, DecRspChannelDisplayPauseUntoPTS, DecRspChannelColorSpaceConv, DecRspChannelSetRangeRemap, DecRspChannelSetFgt, DecRspChannelSetLastPicturePadding, DecRspChannelSetHostTrickMode, DecRspChannelSetOperationMode, DecRspChannelSetPtsStcDiffThreshold, DecRspSendCompressedBuffer, DecRspSetClipping, DecRspChannelSetParametersForHardResetInterruptToHost, DecRspSetContentKey, DecRspSetSessionKey, DecRspFormatChangeAck, DecRspChannelSingleField, DecRspChannelUnknownCmd; #endif // __INC_C011API_H__ crystalhd-0.0~git20110715.fdd2f19/include/bc_dts_glob_lnx.h0000644000175000017500000002331011610313111022442 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: bc_dts_glob_lnx.h * * Description: Wrapper to Windows dts_glob.h for Link-Linux usage. * The idea is to define additional Linux related defs * in this file to avoid changes to existing Windows * glob file. * * AU * * HISTORY: * ******************************************************************** * This header is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This header is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this header. If not, see . *******************************************************************/ #ifndef _BC_DTS_GLOB_LNX_H_ #define _BC_DTS_GLOB_LNX_H_ #if !defined(__KERNEL__) #include #include #include #include #include #include #include #include #include #include #include #include #include #include #define DRVIFLIB_INT_API #endif #include "bc_dts_defs.h" #include "bcm_70012_regs.h" /* Link Register defs */ #define CRYSTALHD_API_NAME "crystalhd" #define CRYSTALHD_API_DEV_NAME "/dev/crystalhd" enum _BC_PCI_DEV_IDS{ BC_PCI_DEVID_INVALID = 0, BC_PCI_DEVID_DOZER = 0x1610, BC_PCI_DEVID_TANK = 0x1620, BC_PCI_DEVID_LINK = 0x1612, BC_PCI_DEVID_LOCKE = 0x1613, BC_PCI_DEVID_DEMOBRD = 0x7411, BC_PCI_DEVID_MORPHEUS = 0x7412, BC_PCI_DEVID_FLEA = 0x1615, }; /* * These are SW stack tunable parameters shared * between the driver and the application. */ enum _BC_DTS_GLOBALS { BC_MAX_FW_CMD_BUFF_SZ = 0x40, /* FW passthrough cmd/rsp buffer size */ PCI_CFG_SIZE = 256, /* PCI config size buffer */ BC_IOCTL_DATA_POOL_SIZE = 8, /* BC_IOCTL_DATA Pool size */ BC_LINK_MAX_OPENS = 3, /* Maximum simultaneous opens*/ BC_LINK_MAX_SGLS = 1024, /* Maximum SG elements 4M/4K */ BC_TX_LIST_CNT = 2, /* Max Tx DMA Rings */ BC_RX_LIST_CNT = 16, /* Max Rx DMA Rings*/ BC_PROC_OUTPUT_TIMEOUT = 2000, /* Milliseconds */ BC_INFIFO_THRESHOLD = 0x10000, }; /* definitions for HW Pause */ /* NAREN FIXME temporarily disable HW PAUSE */ #define HW_PAUSE_THRESHOLD (BC_RX_LIST_CNT) #define HW_RESUME_THRESHOLD (BC_RX_LIST_CNT/2) typedef union _addr_64_ { struct { uint32_t low_part; uint32_t high_part; }; uint64_t full_addr; } addr_64; typedef struct _BC_CMD_REG_ACC { uint32_t Offset; uint32_t Value; } BC_CMD_REG_ACC; typedef struct _BC_CMD_DEV_MEM { uint32_t StartOff; uint32_t NumDwords; uint32_t Rsrd; } BC_CMD_DEV_MEM; /* FW Passthrough command structure */ enum _bc_fw_cmd_flags { BC_FW_CMD_FLAGS_NONE = 0, BC_FW_CMD_PIB_QS = 0x01, }; typedef struct _BC_FW_CMD { uint32_t cmd[BC_MAX_FW_CMD_BUFF_SZ]; uint32_t rsp[BC_MAX_FW_CMD_BUFF_SZ]; uint32_t flags; uint32_t add_data; } BC_FW_CMD, *PBC_FW_CMD; typedef struct _BC_HW_TYPE { uint16_t PciDevId; uint16_t PciVenId; uint8_t HwRev; uint8_t Align[3]; } BC_HW_TYPE; typedef struct _BC_PCI_CFG { uint32_t Size; uint32_t Offset; uint8_t pci_cfg_space[PCI_CFG_SIZE]; } BC_PCI_CFG; typedef struct _BC_VERSION_INFO_ { uint8_t DriverMajor; uint8_t DriverMinor; uint16_t DriverRevision; } BC_VERSION_INFO; typedef struct _BC_START_RX_CAP_ { uint32_t Rsrd; uint32_t StartDeliveryThsh; uint32_t PauseThsh; uint32_t ResumeThsh; } BC_START_RX_CAP; typedef struct _BC_FLUSH_RX_CAP_ { uint32_t Rsrd; uint32_t bDiscardOnly; } BC_FLUSH_RX_CAP; typedef struct _BC_DTS_STATS { uint8_t drvRLL; uint8_t drvFLL; uint8_t eosDetected; uint8_t pwr_state_change; /* 0 is Default (running/stopped), 1 is going to suspend, 2 is going to resume */ /* Stats from App */ uint32_t opFrameDropped; uint32_t opFrameCaptured; uint32_t ipSampleCnt; uint64_t ipTotalSize; uint32_t reptdFrames; uint32_t pauseCount; uint32_t pibMisses; uint32_t discCounter; /* Stats from Driver */ uint32_t TxFifoBsyCnt; uint32_t intCount; uint32_t DrvIgnIntrCnt; uint32_t DrvTotalFrmDropped; uint32_t DrvTotalHWErrs; uint32_t DrvTotalPIBFlushCnt; uint32_t DrvTotalFrmCaptured; uint32_t DrvPIBMisses; uint32_t DrvPauseTime; uint32_t DrvRepeatedFrms; /* * BIT-31 MEANS READ Next PIB Info. * Width will be in bit 0-16. */ uint64_t DrvNextMDataPLD; uint32_t DrvcpbEmptySize; float Temperature; uint32_t TempFromDriver; uint32_t picNumFlags; uint32_t res1[7]; } BC_DTS_STATS; typedef struct _BC_PROC_INPUT_ { uint8_t *pDmaBuff; uint32_t BuffSz; uint8_t Mapped; uint8_t Encrypted; uint8_t Rsrd[2]; uint32_t DramOffset; /* For debug use only */ } BC_PROC_INPUT, *PBC_PROC_INPUT; typedef struct _BC_DEC_YUV_BUFFS { uint32_t b422Mode; uint8_t *YuvBuff; uint32_t YuvBuffSz; uint32_t UVbuffOffset; uint32_t YBuffDoneSz; uint32_t UVBuffDoneSz; uint32_t RefCnt; } BC_DEC_YUV_BUFFS; enum _DECOUT_COMPLETION_FLAGS{ COMP_FLAG_NO_INFO = 0x00, COMP_FLAG_FMT_CHANGE = 0x01, COMP_FLAG_PIB_VALID = 0x02, COMP_FLAG_DATA_VALID = 0x04, COMP_FLAG_DATA_ENC = 0x08, COMP_FLAG_DATA_BOT = 0x10, }; typedef struct _BC_DEC_OUT_BUFF{ BC_DEC_YUV_BUFFS OutPutBuffs; #if !defined(__KERNEL__) C011_PIB PibInfo; #else struct C011_PIB PibInfo; #endif uint32_t Flags; uint32_t BadFrCnt; } BC_DEC_OUT_BUFF; typedef struct _BC_NOTIFY_MODE { uint32_t Mode; uint32_t Rsvr[3]; } BC_NOTIFY_MODE; typedef struct _BC_IOCTL_DATA { BC_STATUS RetSts; uint32_t IoctlDataSz; uint32_t Timeout; union { BC_CMD_REG_ACC regAcc; BC_CMD_DEV_MEM devMem; BC_FW_CMD fwCmd; BC_HW_TYPE hwType; BC_PCI_CFG pciCfg; BC_VERSION_INFO VerInfo; BC_PROC_INPUT ProcInput; BC_DEC_YUV_BUFFS RxBuffs; BC_DEC_OUT_BUFF DecOutData; BC_START_RX_CAP RxCap; BC_FLUSH_RX_CAP FlushRxCap; BC_DTS_STATS drvStat; BC_NOTIFY_MODE NotifyMode; } u; struct _BC_IOCTL_DATA *next; } BC_IOCTL_DATA; typedef enum _BC_DRV_CMD{ DRV_CMD_VERSION = 0, /* Get SW version */ DRV_CMD_GET_HWTYPE, /* Get HW version and type Dozer/Tank */ DRV_CMD_REG_RD, /* Read Device Register */ DRV_CMD_REG_WR, /* Write Device Register */ DRV_CMD_FPGA_RD, /* Read FPGA Register */ DRV_CMD_FPGA_WR, /* Wrtie FPGA Reister */ DRV_CMD_MEM_RD, /* Read Device Memory */ DRV_CMD_MEM_WR, /* Write Device Memory */ DRV_CMD_RD_PCI_CFG, /* Read PCI Config Space */ DRV_CMD_WR_PCI_CFG, /* Write the PCI Configuration Space*/ DRV_CMD_FW_DOWNLOAD, /* Download Firmware */ DRV_ISSUE_FW_CMD, /* Issue FW Cmd (pass through mode) */ DRV_CMD_PROC_INPUT, /* Process Input Sample */ DRV_CMD_ADD_RXBUFFS, /* Add Rx side buffers to driver pool */ DRV_CMD_FETCH_RXBUFF, /* Get Rx DMAed buffer */ DRV_CMD_START_RX_CAP, /* Start Rx Buffer Capture */ DRV_CMD_FLUSH_RX_CAP, /* Stop the capture for now...we will enhance this later*/ DRV_CMD_GET_DRV_STAT, /* Get Driver Internal Statistics */ DRV_CMD_RST_DRV_STAT, /* Reset Driver Internal Statistics */ DRV_CMD_NOTIFY_MODE, /* Notify the Mode to driver in which the application is Operating*/ DRV_CMD_RELEASE, /* Notify the driver to release user handle and application resources */ /* MUST be the last one.. */ DRV_CMD_END, /* End of the List.. */ } BC_DRV_CMD; #define BC_IOC_BASE 'b' #define BC_IOC_VOID _IOC_NONE #define BC_IOC_IOWR(nr, type) _IOWR(BC_IOC_BASE, nr, type) #define BC_IOCTL_MB BC_IOCTL_DATA #define BCM_IOC_GET_VERSION BC_IOC_IOWR(DRV_CMD_VERSION, BC_IOCTL_MB) #define BCM_IOC_GET_HWTYPE BC_IOC_IOWR(DRV_CMD_GET_HWTYPE, BC_IOCTL_MB) #define BCM_IOC_REG_RD BC_IOC_IOWR(DRV_CMD_REG_RD, BC_IOCTL_MB) #define BCM_IOC_REG_WR BC_IOC_IOWR(DRV_CMD_REG_WR, BC_IOCTL_MB) #define BCM_IOC_MEM_RD BC_IOC_IOWR(DRV_CMD_MEM_RD, BC_IOCTL_MB) #define BCM_IOC_MEM_WR BC_IOC_IOWR(DRV_CMD_MEM_WR, BC_IOCTL_MB) #define BCM_IOC_FPGA_RD BC_IOC_IOWR(DRV_CMD_FPGA_RD, BC_IOCTL_MB) #define BCM_IOC_FPGA_WR BC_IOC_IOWR(DRV_CMD_FPGA_WR, BC_IOCTL_MB) #define BCM_IOC_RD_PCI_CFG BC_IOC_IOWR(DRV_CMD_RD_PCI_CFG, BC_IOCTL_MB) #define BCM_IOC_WR_PCI_CFG BC_IOC_IOWR(DRV_CMD_WR_PCI_CFG, BC_IOCTL_MB) #define BCM_IOC_PROC_INPUT BC_IOC_IOWR(DRV_CMD_PROC_INPUT, BC_IOCTL_MB) #define BCM_IOC_ADD_RXBUFFS BC_IOC_IOWR(DRV_CMD_ADD_RXBUFFS, BC_IOCTL_MB) #define BCM_IOC_FETCH_RXBUFF BC_IOC_IOWR(DRV_CMD_FETCH_RXBUFF, BC_IOCTL_MB) #define BCM_IOC_FW_CMD BC_IOC_IOWR(DRV_ISSUE_FW_CMD, BC_IOCTL_MB) #define BCM_IOC_START_RX_CAP BC_IOC_IOWR(DRV_CMD_START_RX_CAP, BC_IOCTL_MB) #define BCM_IOC_FLUSH_RX_CAP BC_IOC_IOWR(DRV_CMD_FLUSH_RX_CAP, BC_IOCTL_MB) #define BCM_IOC_GET_DRV_STAT BC_IOC_IOWR(DRV_CMD_GET_DRV_STAT, BC_IOCTL_MB) #define BCM_IOC_RST_DRV_STAT BC_IOC_IOWR(DRV_CMD_RST_DRV_STAT, BC_IOCTL_MB) #define BCM_IOC_NOTIFY_MODE BC_IOC_IOWR(DRV_CMD_NOTIFY_MODE, BC_IOCTL_MB) #define BCM_IOC_FW_DOWNLOAD BC_IOC_IOWR(DRV_CMD_FW_DOWNLOAD, BC_IOCTL_MB) #define BCM_IOC_RELEASE BC_IOC_IOWR(DRV_CMD_RELEASE, BC_IOCTL_MB) #define BCM_IOC_END BC_IOC_VOID /* Wrapper for main IOCTL data */ typedef struct _crystalhd_ioctl_data { BC_IOCTL_DATA udata; /* IOCTL from App..*/ uint32_t u_id; /* Driver specific user ID */ uint32_t cmd; /* Cmd ID for driver's use. */ void *add_cdata; /* Additional command specific data..*/ uint32_t add_cdata_sz; /* Additional command specific data size */ struct _crystalhd_ioctl_data *next; /* List/Fifo management */ } crystalhd_ioctl_data; enum _crystalhd_kmod_ver{ crystalhd_kmod_major = 3, crystalhd_kmod_minor = 10, crystalhd_kmod_rev = 0, }; #endif crystalhd-0.0~git20110715.fdd2f19/filters/0000755000175000017500000000000011610313111017175 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/filters/gst/0000755000175000017500000000000011610313111017772 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/0000755000175000017500000000000011610313122022065 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/INSTALL0000644000175000017500000002245011610313111023117 0ustar andresandresInstallation Instructions ************************* Copyright (C) 1994, 1995, 1996, 1999, 2000, 2001, 2002, 2004, 2005, 2006, 2007 Free Software Foundation, Inc. This file is free documentation; the Free Software Foundation gives unlimited permission to copy, distribute and modify it. Basic Installation ================== Briefly, the shell commands `./configure; make; make install' should configure, build, and install this package. The following more-detailed instructions are generic; see the `README' file for instructions specific to this package. The `configure' shell script attempts to guess correct values for various system-dependent variables used during compilation. It uses those values to create a `Makefile' in each directory of the package. It may also create one or more `.h' files containing system-dependent definitions. Finally, it creates a shell script `config.status' that you can run in the future to recreate the current configuration, and a file `config.log' containing compiler output (useful mainly for debugging `configure'). It can also use an optional file (typically called `config.cache' and enabled with `--cache-file=config.cache' or simply `-C') that saves the results of its tests to speed up reconfiguring. Caching is disabled by default to prevent problems with accidental use of stale cache files. If you need to do unusual things to compile the package, please try to figure out how `configure' could check whether to do them, and mail diffs or instructions to the address given in the `README' so they can be considered for the next release. If you are using the cache, and at some point `config.cache' contains results you don't want to keep, you may remove or edit it. The file `configure.ac' (or `configure.in') is used to create `configure' by a program called `autoconf'. You need `configure.ac' if you want to change it or regenerate `configure' using a newer version of `autoconf'. The simplest way to compile this package is: 1. `cd' to the directory containing the package's source code and type `./configure' to configure the package for your system. Running `configure' might take a while. While running, it prints some messages telling which features it is checking for. 2. Type `make' to compile the package. 3. Optionally, type `make check' to run any self-tests that come with the package. 4. Type `make install' to install the programs and any data files and documentation. 5. You can remove the program binaries and object files from the source code directory by typing `make clean'. To also remove the files that `configure' created (so you can compile the package for a different kind of computer), type `make distclean'. There is also a `make maintainer-clean' target, but that is intended mainly for the package's developers. If you use it, you may have to get all sorts of other programs in order to regenerate files that came with the distribution. 6. Often, you can also type `make uninstall' to remove the installed files again. Compilers and Options ===================== Some systems require unusual options for compilation or linking that the `configure' script does not know about. Run `./configure --help' for details on some of the pertinent environment variables. You can give `configure' initial values for configuration parameters by setting variables in the command line or in the environment. Here is an example: ./configure CC=c99 CFLAGS=-g LIBS=-lposix *Note Defining Variables::, for more details. Compiling For Multiple Architectures ==================================== You can compile the package for more than one kind of computer at the same time, by placing the object files for each architecture in their own directory. To do this, you can use GNU `make'. `cd' to the directory where you want the object files and executables to go and run the `configure' script. `configure' automatically checks for the source code in the directory that `configure' is in and in `..'. With a non-GNU `make', it is safer to compile the package for one architecture at a time in the source code directory. After you have installed the package for one architecture, use `make distclean' before reconfiguring for another architecture. Installation Names ================== By default, `make install' installs the package's commands under `/usr/local/bin', include files under `/usr/local/include', etc. You can specify an installation prefix other than `/usr/local' by giving `configure' the option `--prefix=PREFIX'. You can specify separate installation prefixes for architecture-specific files and architecture-independent files. If you pass the option `--exec-prefix=PREFIX' to `configure', the package uses PREFIX as the prefix for installing programs and libraries. Documentation and other data files still use the regular prefix. In addition, if you use an unusual directory layout you can give options like `--bindir=DIR' to specify different values for particular kinds of files. Run `configure --help' for a list of the directories you can set and what kinds of files go in them. If the package supports it, you can cause programs to be installed with an extra prefix or suffix on their names by giving `configure' the option `--program-prefix=PREFIX' or `--program-suffix=SUFFIX'. Optional Features ================= Some packages pay attention to `--enable-FEATURE' options to `configure', where FEATURE indicates an optional part of the package. They may also pay attention to `--with-PACKAGE' options, where PACKAGE is something like `gnu-as' or `x' (for the X Window System). The `README' should mention any `--enable-' and `--with-' options that the package recognizes. For packages that use the X Window System, `configure' can usually find the X include and library files automatically, but if it doesn't, you can use the `configure' options `--x-includes=DIR' and `--x-libraries=DIR' to specify their locations. Specifying the System Type ========================== There may be some features `configure' cannot figure out automatically, but needs to determine by the type of machine the package will run on. Usually, assuming the package is built to be run on the _same_ architectures, `configure' can figure that out, but if it prints a message saying it cannot guess the machine type, give it the `--build=TYPE' option. TYPE can either be a short name for the system type, such as `sun4', or a canonical name which has the form: CPU-COMPANY-SYSTEM where SYSTEM can have one of these forms: OS KERNEL-OS See the file `config.sub' for the possible values of each field. If `config.sub' isn't included in this package, then this package doesn't need to know the machine type. If you are _building_ compiler tools for cross-compiling, you should use the option `--target=TYPE' to select the type of system they will produce code for. If you want to _use_ a cross compiler, that generates code for a platform different from the build platform, you should specify the "host" platform (i.e., that on which the generated programs will eventually be run) with `--host=TYPE'. Sharing Defaults ================ If you want to set default values for `configure' scripts to share, you can create a site shell script called `config.site' that gives default values for variables like `CC', `cache_file', and `prefix'. `configure' looks for `PREFIX/share/config.site' if it exists, then `PREFIX/etc/config.site' if it exists. Or, you can set the `CONFIG_SITE' environment variable to the location of the site script. A warning: not all `configure' scripts look for a site script. Defining Variables ================== Variables not defined in a site shell script can be set in the environment passed to `configure'. However, some packages may run configure again during the build, and the customized values of these variables may be lost. In order to avoid this problem, you should set them in the `configure' command line, using `VAR=value'. For example: ./configure CC=/usr/local2/bin/gcc causes the specified `gcc' to be used as the C compiler (unless it is overridden in the site shell script). Unfortunately, this technique does not work for `CONFIG_SHELL' due to an Autoconf bug. Until the bug is fixed you can use this workaround: CONFIG_SHELL=/bin/bash /bin/bash ./configure CONFIG_SHELL=/bin/bash `configure' Invocation ====================== `configure' recognizes the following options to control how it operates. `--help' `-h' Print a summary of the options to `configure', and exit. `--version' `-V' Print the version of Autoconf used to generate the `configure' script, and exit. `--cache-file=FILE' Enable the cache: use and save the results of the tests in FILE, traditionally `config.cache'. FILE defaults to `/dev/null' to disable caching. `--config-cache' `-C' Alias for `--cache-file=config.cache'. `--quiet' `--silent' `-q' Do not print messages saying which checks are being made. To suppress all normal output, redirect it to `/dev/null' (any error messages will still be shown). `--srcdir=DIR' Look for the package's source code in directory DIR. Usually `configure' can determine that directory automatically. `configure' also accepts some other, not widely useful, options. Run `configure --help' for more details. crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/AUTHORS0000644000175000017500000000152611610313111023137 0ustar andresandres/******************************************************************** * Copyright(c) 2008 Broadcom Corporation. * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/ltmain.sh0000755000175000017500000105051111610313115023715 0ustar andresandres # libtool (GNU libtool) 2.4 # Written by Gordon Matzigkeit , 1996 # Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, 2006, # 2007, 2008, 2009, 2010 Free Software Foundation, Inc. # This is free software; see the source for copying conditions. There is NO # warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. # GNU Libtool is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # As a special exception to the GNU General Public License, # if you distribute this file as part of a program or library that # is built using GNU Libtool, you may include this file under the # same distribution terms that you use for the rest of that program. # # GNU Libtool is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # General Public License for more details. # # You should have received a copy of the GNU General Public License # along with GNU Libtool; see the file COPYING. If not, a copy # can be downloaded from http://www.gnu.org/licenses/gpl.html, # or obtained by writing to the Free Software Foundation, Inc., # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. # Usage: $progname [OPTION]... [MODE-ARG]... # # Provide generalized library-building support services. # # --config show all configuration variables # --debug enable verbose shell tracing # -n, --dry-run display commands without modifying any files # --features display basic configuration information and exit # --mode=MODE use operation mode MODE # --preserve-dup-deps don't remove duplicate dependency libraries # --quiet, --silent don't print informational messages # --no-quiet, --no-silent # print informational messages (default) # --tag=TAG use configuration variables from tag TAG # -v, --verbose print more informational messages than default # --no-verbose don't print the extra informational messages # --version print version information # -h, --help, --help-all print short, long, or detailed help message # # MODE must be one of the following: # # clean remove files from the build directory # compile compile a source file into a libtool object # execute automatically set library path, then run a program # finish complete the installation of libtool libraries # install install libraries or executables # link create a library or an executable # uninstall remove libraries from an installed directory # # MODE-ARGS vary depending on the MODE. When passed as first option, # `--mode=MODE' may be abbreviated as `MODE' or a unique abbreviation of that. # Try `$progname --help --mode=MODE' for a more detailed description of MODE. # # When reporting a bug, please describe a test case to reproduce it and # include the following information: # # host-triplet: $host # shell: $SHELL # compiler: $LTCC # compiler flags: $LTCFLAGS # linker: $LD (gnu? $with_gnu_ld) # $progname: (GNU libtool) 2.4 Debian-2.4-2 # automake: $automake_version # autoconf: $autoconf_version # # Report bugs to . # GNU libtool home page: . # General help using GNU software: . PROGRAM=libtool PACKAGE=libtool VERSION="2.4 Debian-2.4-2" TIMESTAMP="" package_revision=1.3293 # Be Bourne compatible if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then emulate sh NULLCMD=: # Zsh 3.x and 4.x performs word splitting on ${1+"$@"}, which # is contrary to our usage. Disable this feature. alias -g '${1+"$@"}'='"$@"' setopt NO_GLOB_SUBST else case `(set -o) 2>/dev/null` in *posix*) set -o posix;; esac fi BIN_SH=xpg4; export BIN_SH # for Tru64 DUALCASE=1; export DUALCASE # for MKS sh # A function that is used when there is no print builtin or printf. func_fallback_echo () { eval 'cat <<_LTECHO_EOF $1 _LTECHO_EOF' } # NLS nuisances: We save the old values to restore during execute mode. lt_user_locale= lt_safe_locale= for lt_var in LANG LANGUAGE LC_ALL LC_CTYPE LC_COLLATE LC_MESSAGES do eval "if test \"\${$lt_var+set}\" = set; then save_$lt_var=\$$lt_var $lt_var=C export $lt_var lt_user_locale=\"$lt_var=\\\$save_\$lt_var; \$lt_user_locale\" lt_safe_locale=\"$lt_var=C; \$lt_safe_locale\" fi" done LC_ALL=C LANGUAGE=C export LANGUAGE LC_ALL $lt_unset CDPATH # Work around backward compatibility issue on IRIX 6.5. On IRIX 6.4+, sh # is ksh but when the shell is invoked as "sh" and the current value of # the _XPG environment variable is not equal to 1 (one), the special # positional parameter $0, within a function call, is the name of the # function. progpath="$0" : ${CP="cp -f"} test "${ECHO+set}" = set || ECHO=${as_echo-'printf %s\n'} : ${EGREP="/bin/grep -E"} : ${FGREP="/bin/grep -F"} : ${GREP="/bin/grep"} : ${LN_S="ln -s"} : ${MAKE="make"} : ${MKDIR="mkdir"} : ${MV="mv -f"} : ${RM="rm -f"} : ${SED="/bin/sed"} : ${SHELL="${CONFIG_SHELL-/bin/sh}"} : ${Xsed="$SED -e 1s/^X//"} # Global variables: EXIT_SUCCESS=0 EXIT_FAILURE=1 EXIT_MISMATCH=63 # $? = 63 is used to indicate version mismatch to missing. EXIT_SKIP=77 # $? = 77 is used to indicate a skipped test to automake. exit_status=$EXIT_SUCCESS # Make sure IFS has a sensible default lt_nl=' ' IFS=" $lt_nl" dirname="s,/[^/]*$,," basename="s,^.*/,," # func_dirname file append nondir_replacement # Compute the dirname of FILE. If nonempty, add APPEND to the result, # otherwise set result to NONDIR_REPLACEMENT. func_dirname () { func_dirname_result=`$ECHO "${1}" | $SED "$dirname"` if test "X$func_dirname_result" = "X${1}"; then func_dirname_result="${3}" else func_dirname_result="$func_dirname_result${2}" fi } # func_dirname may be replaced by extended shell implementation # func_basename file func_basename () { func_basename_result=`$ECHO "${1}" | $SED "$basename"` } # func_basename may be replaced by extended shell implementation # func_dirname_and_basename file append nondir_replacement # perform func_basename and func_dirname in a single function # call: # dirname: Compute the dirname of FILE. If nonempty, # add APPEND to the result, otherwise set result # to NONDIR_REPLACEMENT. # value returned in "$func_dirname_result" # basename: Compute filename of FILE. # value retuned in "$func_basename_result" # Implementation must be kept synchronized with func_dirname # and func_basename. For efficiency, we do not delegate to # those functions but instead duplicate the functionality here. func_dirname_and_basename () { # Extract subdirectory from the argument. func_dirname_result=`$ECHO "${1}" | $SED -e "$dirname"` if test "X$func_dirname_result" = "X${1}"; then func_dirname_result="${3}" else func_dirname_result="$func_dirname_result${2}" fi func_basename_result=`$ECHO "${1}" | $SED -e "$basename"` } # func_dirname_and_basename may be replaced by extended shell implementation # func_stripname prefix suffix name # strip PREFIX and SUFFIX off of NAME. # PREFIX and SUFFIX must not contain globbing or regex special # characters, hashes, percent signs, but SUFFIX may contain a leading # dot (in which case that matches only a dot). # func_strip_suffix prefix name func_stripname () { case ${2} in .*) func_stripname_result=`$ECHO "${3}" | $SED "s%^${1}%%; s%\\\\${2}\$%%"`;; *) func_stripname_result=`$ECHO "${3}" | $SED "s%^${1}%%; s%${2}\$%%"`;; esac } # func_stripname may be replaced by extended shell implementation # These SED scripts presuppose an absolute path with a trailing slash. pathcar='s,^/\([^/]*\).*$,\1,' pathcdr='s,^/[^/]*,,' removedotparts=':dotsl s@/\./@/@g t dotsl s,/\.$,/,' collapseslashes='s@/\{1,\}@/@g' finalslash='s,/*$,/,' # func_normal_abspath PATH # Remove doubled-up and trailing slashes, "." path components, # and cancel out any ".." path components in PATH after making # it an absolute path. # value returned in "$func_normal_abspath_result" func_normal_abspath () { # Start from root dir and reassemble the path. func_normal_abspath_result= func_normal_abspath_tpath=$1 func_normal_abspath_altnamespace= case $func_normal_abspath_tpath in "") # Empty path, that just means $cwd. func_stripname '' '/' "`pwd`" func_normal_abspath_result=$func_stripname_result return ;; # The next three entries are used to spot a run of precisely # two leading slashes without using negated character classes; # we take advantage of case's first-match behaviour. ///*) # Unusual form of absolute path, do nothing. ;; //*) # Not necessarily an ordinary path; POSIX reserves leading '//' # and for example Cygwin uses it to access remote file shares # over CIFS/SMB, so we conserve a leading double slash if found. func_normal_abspath_altnamespace=/ ;; /*) # Absolute path, do nothing. ;; *) # Relative path, prepend $cwd. func_normal_abspath_tpath=`pwd`/$func_normal_abspath_tpath ;; esac # Cancel out all the simple stuff to save iterations. We also want # the path to end with a slash for ease of parsing, so make sure # there is one (and only one) here. func_normal_abspath_tpath=`$ECHO "$func_normal_abspath_tpath" | $SED \ -e "$removedotparts" -e "$collapseslashes" -e "$finalslash"` while :; do # Processed it all yet? if test "$func_normal_abspath_tpath" = / ; then # If we ascended to the root using ".." the result may be empty now. if test -z "$func_normal_abspath_result" ; then func_normal_abspath_result=/ fi break fi func_normal_abspath_tcomponent=`$ECHO "$func_normal_abspath_tpath" | $SED \ -e "$pathcar"` func_normal_abspath_tpath=`$ECHO "$func_normal_abspath_tpath" | $SED \ -e "$pathcdr"` # Figure out what to do with it case $func_normal_abspath_tcomponent in "") # Trailing empty path component, ignore it. ;; ..) # Parent dir; strip last assembled component from result. func_dirname "$func_normal_abspath_result" func_normal_abspath_result=$func_dirname_result ;; *) # Actual path component, append it. func_normal_abspath_result=$func_normal_abspath_result/$func_normal_abspath_tcomponent ;; esac done # Restore leading double-slash if one was found on entry. func_normal_abspath_result=$func_normal_abspath_altnamespace$func_normal_abspath_result } # func_relative_path SRCDIR DSTDIR # generates a relative path from SRCDIR to DSTDIR, with a trailing # slash if non-empty, suitable for immediately appending a filename # without needing to append a separator. # value returned in "$func_relative_path_result" func_relative_path () { func_relative_path_result= func_normal_abspath "$1" func_relative_path_tlibdir=$func_normal_abspath_result func_normal_abspath "$2" func_relative_path_tbindir=$func_normal_abspath_result # Ascend the tree starting from libdir while :; do # check if we have found a prefix of bindir case $func_relative_path_tbindir in $func_relative_path_tlibdir) # found an exact match func_relative_path_tcancelled= break ;; $func_relative_path_tlibdir*) # found a matching prefix func_stripname "$func_relative_path_tlibdir" '' "$func_relative_path_tbindir" func_relative_path_tcancelled=$func_stripname_result if test -z "$func_relative_path_result"; then func_relative_path_result=. fi break ;; *) func_dirname $func_relative_path_tlibdir func_relative_path_tlibdir=${func_dirname_result} if test "x$func_relative_path_tlibdir" = x ; then # Have to descend all the way to the root! func_relative_path_result=../$func_relative_path_result func_relative_path_tcancelled=$func_relative_path_tbindir break fi func_relative_path_result=../$func_relative_path_result ;; esac done # Now calculate path; take care to avoid doubling-up slashes. func_stripname '' '/' "$func_relative_path_result" func_relative_path_result=$func_stripname_result func_stripname '/' '/' "$func_relative_path_tcancelled" if test "x$func_stripname_result" != x ; then func_relative_path_result=${func_relative_path_result}/${func_stripname_result} fi # Normalisation. If bindir is libdir, return empty string, # else relative path ending with a slash; either way, target # file name can be directly appended. if test ! -z "$func_relative_path_result"; then func_stripname './' '' "$func_relative_path_result/" func_relative_path_result=$func_stripname_result fi } # The name of this program: func_dirname_and_basename "$progpath" progname=$func_basename_result # Make sure we have an absolute path for reexecution: case $progpath in [\\/]*|[A-Za-z]:\\*) ;; *[\\/]*) progdir=$func_dirname_result progdir=`cd "$progdir" && pwd` progpath="$progdir/$progname" ;; *) save_IFS="$IFS" IFS=: for progdir in $PATH; do IFS="$save_IFS" test -x "$progdir/$progname" && break done IFS="$save_IFS" test -n "$progdir" || progdir=`pwd` progpath="$progdir/$progname" ;; esac # Sed substitution that helps us do robust quoting. It backslashifies # metacharacters that are still active within double-quoted strings. Xsed="${SED}"' -e 1s/^X//' sed_quote_subst='s/\([`"$\\]\)/\\\1/g' # Same as above, but do not quote variable references. double_quote_subst='s/\(["`\\]\)/\\\1/g' # Sed substitution that turns a string into a regex matching for the # string literally. sed_make_literal_regex='s,[].[^$\\*\/],\\&,g' # Sed substitution that converts a w32 file name or path # which contains forward slashes, into one that contains # (escaped) backslashes. A very naive implementation. lt_sed_naive_backslashify='s|\\\\*|\\|g;s|/|\\|g;s|\\|\\\\|g' # Re-`\' parameter expansions in output of double_quote_subst that were # `\'-ed in input to the same. If an odd number of `\' preceded a '$' # in input to double_quote_subst, that '$' was protected from expansion. # Since each input `\' is now two `\'s, look for any number of runs of # four `\'s followed by two `\'s and then a '$'. `\' that '$'. bs='\\' bs2='\\\\' bs4='\\\\\\\\' dollar='\$' sed_double_backslash="\ s/$bs4/&\\ /g s/^$bs2$dollar/$bs&/ s/\\([^$bs]\\)$bs2$dollar/\\1$bs2$bs$dollar/g s/\n//g" # Standard options: opt_dry_run=false opt_help=false opt_quiet=false opt_verbose=false opt_warning=: # func_echo arg... # Echo program name prefixed message, along with the current mode # name if it has been set yet. func_echo () { $ECHO "$progname: ${opt_mode+$opt_mode: }$*" } # func_verbose arg... # Echo program name prefixed message in verbose mode only. func_verbose () { $opt_verbose && func_echo ${1+"$@"} # A bug in bash halts the script if the last line of a function # fails when set -e is in force, so we need another command to # work around that: : } # func_echo_all arg... # Invoke $ECHO with all args, space-separated. func_echo_all () { $ECHO "$*" } # func_error arg... # Echo program name prefixed message to standard error. func_error () { $ECHO "$progname: ${opt_mode+$opt_mode: }"${1+"$@"} 1>&2 } # func_warning arg... # Echo program name prefixed warning message to standard error. func_warning () { $opt_warning && $ECHO "$progname: ${opt_mode+$opt_mode: }warning: "${1+"$@"} 1>&2 # bash bug again: : } # func_fatal_error arg... # Echo program name prefixed message to standard error, and exit. func_fatal_error () { func_error ${1+"$@"} exit $EXIT_FAILURE } # func_fatal_help arg... # Echo program name prefixed message to standard error, followed by # a help hint, and exit. func_fatal_help () { func_error ${1+"$@"} func_fatal_error "$help" } help="Try \`$progname --help' for more information." ## default # func_grep expression filename # Check whether EXPRESSION matches any line of FILENAME, without output. func_grep () { $GREP "$1" "$2" >/dev/null 2>&1 } # func_mkdir_p directory-path # Make sure the entire path to DIRECTORY-PATH is available. func_mkdir_p () { my_directory_path="$1" my_dir_list= if test -n "$my_directory_path" && test "$opt_dry_run" != ":"; then # Protect directory names starting with `-' case $my_directory_path in -*) my_directory_path="./$my_directory_path" ;; esac # While some portion of DIR does not yet exist... while test ! -d "$my_directory_path"; do # ...make a list in topmost first order. Use a colon delimited # list incase some portion of path contains whitespace. my_dir_list="$my_directory_path:$my_dir_list" # If the last portion added has no slash in it, the list is done case $my_directory_path in */*) ;; *) break ;; esac # ...otherwise throw away the child directory and loop my_directory_path=`$ECHO "$my_directory_path" | $SED -e "$dirname"` done my_dir_list=`$ECHO "$my_dir_list" | $SED 's,:*$,,'` save_mkdir_p_IFS="$IFS"; IFS=':' for my_dir in $my_dir_list; do IFS="$save_mkdir_p_IFS" # mkdir can fail with a `File exist' error if two processes # try to create one of the directories concurrently. Don't # stop in that case! $MKDIR "$my_dir" 2>/dev/null || : done IFS="$save_mkdir_p_IFS" # Bail out if we (or some other process) failed to create a directory. test -d "$my_directory_path" || \ func_fatal_error "Failed to create \`$1'" fi } # func_mktempdir [string] # Make a temporary directory that won't clash with other running # libtool processes, and avoids race conditions if possible. If # given, STRING is the basename for that directory. func_mktempdir () { my_template="${TMPDIR-/tmp}/${1-$progname}" if test "$opt_dry_run" = ":"; then # Return a directory name, but don't create it in dry-run mode my_tmpdir="${my_template}-$$" else # If mktemp works, use that first and foremost my_tmpdir=`mktemp -d "${my_template}-XXXXXXXX" 2>/dev/null` if test ! -d "$my_tmpdir"; then # Failing that, at least try and use $RANDOM to avoid a race my_tmpdir="${my_template}-${RANDOM-0}$$" save_mktempdir_umask=`umask` umask 0077 $MKDIR "$my_tmpdir" umask $save_mktempdir_umask fi # If we're not in dry-run mode, bomb out on failure test -d "$my_tmpdir" || \ func_fatal_error "cannot create temporary directory \`$my_tmpdir'" fi $ECHO "$my_tmpdir" } # func_quote_for_eval arg # Aesthetically quote ARG to be evaled later. # This function returns two values: FUNC_QUOTE_FOR_EVAL_RESULT # is double-quoted, suitable for a subsequent eval, whereas # FUNC_QUOTE_FOR_EVAL_UNQUOTED_RESULT has merely all characters # which are still active within double quotes backslashified. func_quote_for_eval () { case $1 in *[\\\`\"\$]*) func_quote_for_eval_unquoted_result=`$ECHO "$1" | $SED "$sed_quote_subst"` ;; *) func_quote_for_eval_unquoted_result="$1" ;; esac case $func_quote_for_eval_unquoted_result in # Double-quote args containing shell metacharacters to delay # word splitting, command substitution and and variable # expansion for a subsequent eval. # Many Bourne shells cannot handle close brackets correctly # in scan sets, so we specify it separately. *[\[\~\#\^\&\*\(\)\{\}\|\;\<\>\?\'\ \ ]*|*]*|"") func_quote_for_eval_result="\"$func_quote_for_eval_unquoted_result\"" ;; *) func_quote_for_eval_result="$func_quote_for_eval_unquoted_result" esac } # func_quote_for_expand arg # Aesthetically quote ARG to be evaled later; same as above, # but do not quote variable references. func_quote_for_expand () { case $1 in *[\\\`\"]*) my_arg=`$ECHO "$1" | $SED \ -e "$double_quote_subst" -e "$sed_double_backslash"` ;; *) my_arg="$1" ;; esac case $my_arg in # Double-quote args containing shell metacharacters to delay # word splitting and command substitution for a subsequent eval. # Many Bourne shells cannot handle close brackets correctly # in scan sets, so we specify it separately. *[\[\~\#\^\&\*\(\)\{\}\|\;\<\>\?\'\ \ ]*|*]*|"") my_arg="\"$my_arg\"" ;; esac func_quote_for_expand_result="$my_arg" } # func_show_eval cmd [fail_exp] # Unless opt_silent is true, then output CMD. Then, if opt_dryrun is # not true, evaluate CMD. If the evaluation of CMD fails, and FAIL_EXP # is given, then evaluate it. func_show_eval () { my_cmd="$1" my_fail_exp="${2-:}" ${opt_silent-false} || { func_quote_for_expand "$my_cmd" eval "func_echo $func_quote_for_expand_result" } if ${opt_dry_run-false}; then :; else eval "$my_cmd" my_status=$? if test "$my_status" -eq 0; then :; else eval "(exit $my_status); $my_fail_exp" fi fi } # func_show_eval_locale cmd [fail_exp] # Unless opt_silent is true, then output CMD. Then, if opt_dryrun is # not true, evaluate CMD. If the evaluation of CMD fails, and FAIL_EXP # is given, then evaluate it. Use the saved locale for evaluation. func_show_eval_locale () { my_cmd="$1" my_fail_exp="${2-:}" ${opt_silent-false} || { func_quote_for_expand "$my_cmd" eval "func_echo $func_quote_for_expand_result" } if ${opt_dry_run-false}; then :; else eval "$lt_user_locale $my_cmd" my_status=$? eval "$lt_safe_locale" if test "$my_status" -eq 0; then :; else eval "(exit $my_status); $my_fail_exp" fi fi } # func_tr_sh # Turn $1 into a string suitable for a shell variable name. # Result is stored in $func_tr_sh_result. All characters # not in the set a-zA-Z0-9_ are replaced with '_'. Further, # if $1 begins with a digit, a '_' is prepended as well. func_tr_sh () { case $1 in [0-9]* | *[!a-zA-Z0-9_]*) func_tr_sh_result=`$ECHO "$1" | $SED 's/^\([0-9]\)/_\1/; s/[^a-zA-Z0-9_]/_/g'` ;; * ) func_tr_sh_result=$1 ;; esac } # func_version # Echo version message to standard output and exit. func_version () { $opt_debug $SED -n '/(C)/!b go :more /\./!{ N s/\n# / / b more } :go /^# '$PROGRAM' (GNU /,/# warranty; / { s/^# // s/^# *$// s/\((C)\)[ 0-9,-]*\( [1-9][0-9]*\)/\1\2/ p }' < "$progpath" exit $? } # func_usage # Echo short help message to standard output and exit. func_usage () { $opt_debug $SED -n '/^# Usage:/,/^# *.*--help/ { s/^# // s/^# *$// s/\$progname/'$progname'/ p }' < "$progpath" echo $ECHO "run \`$progname --help | more' for full usage" exit $? } # func_help [NOEXIT] # Echo long help message to standard output and exit, # unless 'noexit' is passed as argument. func_help () { $opt_debug $SED -n '/^# Usage:/,/# Report bugs to/ { :print s/^# // s/^# *$// s*\$progname*'$progname'* s*\$host*'"$host"'* s*\$SHELL*'"$SHELL"'* s*\$LTCC*'"$LTCC"'* s*\$LTCFLAGS*'"$LTCFLAGS"'* s*\$LD*'"$LD"'* s/\$with_gnu_ld/'"$with_gnu_ld"'/ s/\$automake_version/'"`(automake --version) 2>/dev/null |$SED 1q`"'/ s/\$autoconf_version/'"`(autoconf --version) 2>/dev/null |$SED 1q`"'/ p d } /^# .* home page:/b print /^# General help using/b print ' < "$progpath" ret=$? if test -z "$1"; then exit $ret fi } # func_missing_arg argname # Echo program name prefixed message to standard error and set global # exit_cmd. func_missing_arg () { $opt_debug func_error "missing argument for $1." exit_cmd=exit } # func_split_short_opt shortopt # Set func_split_short_opt_name and func_split_short_opt_arg shell # variables after splitting SHORTOPT after the 2nd character. func_split_short_opt () { my_sed_short_opt='1s/^\(..\).*$/\1/;q' my_sed_short_rest='1s/^..\(.*\)$/\1/;q' func_split_short_opt_name=`$ECHO "$1" | $SED "$my_sed_short_opt"` func_split_short_opt_arg=`$ECHO "$1" | $SED "$my_sed_short_rest"` } # func_split_short_opt may be replaced by extended shell implementation # func_split_long_opt longopt # Set func_split_long_opt_name and func_split_long_opt_arg shell # variables after splitting LONGOPT at the `=' sign. func_split_long_opt () { my_sed_long_opt='1s/^\(--[^=]*\)=.*/\1/;q' my_sed_long_arg='1s/^--[^=]*=//' func_split_long_opt_name=`$ECHO "$1" | $SED "$my_sed_long_opt"` func_split_long_opt_arg=`$ECHO "$1" | $SED "$my_sed_long_arg"` } # func_split_long_opt may be replaced by extended shell implementation exit_cmd=: magic="%%%MAGIC variable%%%" magic_exe="%%%MAGIC EXE variable%%%" # Global variables. nonopt= preserve_args= lo2o="s/\\.lo\$/.${objext}/" o2lo="s/\\.${objext}\$/.lo/" extracted_archives= extracted_serial=0 # If this variable is set in any of the actions, the command in it # will be execed at the end. This prevents here-documents from being # left over by shells. exec_cmd= # func_append var value # Append VALUE to the end of shell variable VAR. func_append () { eval "${1}=\$${1}\${2}" } # func_append may be replaced by extended shell implementation # func_append_quoted var value # Quote VALUE and append to the end of shell variable VAR, separated # by a space. func_append_quoted () { func_quote_for_eval "${2}" eval "${1}=\$${1}\\ \$func_quote_for_eval_result" } # func_append_quoted may be replaced by extended shell implementation # func_arith arithmetic-term... func_arith () { func_arith_result=`expr "${@}"` } # func_arith may be replaced by extended shell implementation # func_len string # STRING may not start with a hyphen. func_len () { func_len_result=`expr "${1}" : ".*" 2>/dev/null || echo $max_cmd_len` } # func_len may be replaced by extended shell implementation # func_lo2o object func_lo2o () { func_lo2o_result=`$ECHO "${1}" | $SED "$lo2o"` } # func_lo2o may be replaced by extended shell implementation # func_xform libobj-or-source func_xform () { func_xform_result=`$ECHO "${1}" | $SED 's/\.[^.]*$/.lo/'` } # func_xform may be replaced by extended shell implementation # func_fatal_configuration arg... # Echo program name prefixed message to standard error, followed by # a configuration failure hint, and exit. func_fatal_configuration () { func_error ${1+"$@"} func_error "See the $PACKAGE documentation for more information." func_fatal_error "Fatal configuration error." } # func_config # Display the configuration for all the tags in this script. func_config () { re_begincf='^# ### BEGIN LIBTOOL' re_endcf='^# ### END LIBTOOL' # Default configuration. $SED "1,/$re_begincf CONFIG/d;/$re_endcf CONFIG/,\$d" < "$progpath" # Now print the configurations for the tags. for tagname in $taglist; do $SED -n "/$re_begincf TAG CONFIG: $tagname\$/,/$re_endcf TAG CONFIG: $tagname\$/p" < "$progpath" done exit $? } # func_features # Display the features supported by this script. func_features () { echo "host: $host" if test "$build_libtool_libs" = yes; then echo "enable shared libraries" else echo "disable shared libraries" fi if test "$build_old_libs" = yes; then echo "enable static libraries" else echo "disable static libraries" fi exit $? } # func_enable_tag tagname # Verify that TAGNAME is valid, and either flag an error and exit, or # enable the TAGNAME tag. We also add TAGNAME to the global $taglist # variable here. func_enable_tag () { # Global variable: tagname="$1" re_begincf="^# ### BEGIN LIBTOOL TAG CONFIG: $tagname\$" re_endcf="^# ### END LIBTOOL TAG CONFIG: $tagname\$" sed_extractcf="/$re_begincf/,/$re_endcf/p" # Validate tagname. case $tagname in *[!-_A-Za-z0-9,/]*) func_fatal_error "invalid tag name: $tagname" ;; esac # Don't test for the "default" C tag, as we know it's # there but not specially marked. case $tagname in CC) ;; *) if $GREP "$re_begincf" "$progpath" >/dev/null 2>&1; then taglist="$taglist $tagname" # Evaluate the configuration. Be careful to quote the path # and the sed script, to avoid splitting on whitespace, but # also don't use non-portable quotes within backquotes within # quotes we have to do it in 2 steps: extractedcf=`$SED -n -e "$sed_extractcf" < "$progpath"` eval "$extractedcf" else func_error "ignoring unknown tag $tagname" fi ;; esac } # func_check_version_match # Ensure that we are using m4 macros, and libtool script from the same # release of libtool. func_check_version_match () { if test "$package_revision" != "$macro_revision"; then if test "$VERSION" != "$macro_version"; then if test -z "$macro_version"; then cat >&2 <<_LT_EOF $progname: Version mismatch error. This is $PACKAGE $VERSION, but the $progname: definition of this LT_INIT comes from an older release. $progname: You should recreate aclocal.m4 with macros from $PACKAGE $VERSION $progname: and run autoconf again. _LT_EOF else cat >&2 <<_LT_EOF $progname: Version mismatch error. This is $PACKAGE $VERSION, but the $progname: definition of this LT_INIT comes from $PACKAGE $macro_version. $progname: You should recreate aclocal.m4 with macros from $PACKAGE $VERSION $progname: and run autoconf again. _LT_EOF fi else cat >&2 <<_LT_EOF $progname: Version mismatch error. This is $PACKAGE $VERSION, revision $package_revision, $progname: but the definition of this LT_INIT comes from revision $macro_revision. $progname: You should recreate aclocal.m4 with macros from revision $package_revision $progname: of $PACKAGE $VERSION and run autoconf again. _LT_EOF fi exit $EXIT_MISMATCH fi } # Shorthand for --mode=foo, only valid as the first argument case $1 in clean|clea|cle|cl) shift; set dummy --mode clean ${1+"$@"}; shift ;; compile|compil|compi|comp|com|co|c) shift; set dummy --mode compile ${1+"$@"}; shift ;; execute|execut|execu|exec|exe|ex|e) shift; set dummy --mode execute ${1+"$@"}; shift ;; finish|finis|fini|fin|fi|f) shift; set dummy --mode finish ${1+"$@"}; shift ;; install|instal|insta|inst|ins|in|i) shift; set dummy --mode install ${1+"$@"}; shift ;; link|lin|li|l) shift; set dummy --mode link ${1+"$@"}; shift ;; uninstall|uninstal|uninsta|uninst|unins|unin|uni|un|u) shift; set dummy --mode uninstall ${1+"$@"}; shift ;; esac # Option defaults: opt_debug=: opt_dry_run=false opt_config=false opt_preserve_dup_deps=false opt_features=false opt_finish=false opt_help=false opt_help_all=false opt_silent=: opt_verbose=: opt_silent=false opt_verbose=false # Parse options once, thoroughly. This comes as soon as possible in the # script to make things like `--version' happen as quickly as we can. { # this just eases exit handling while test $# -gt 0; do opt="$1" shift case $opt in --debug|-x) opt_debug='set -x' func_echo "enabling shell trace mode" $opt_debug ;; --dry-run|--dryrun|-n) opt_dry_run=: ;; --config) opt_config=: func_config ;; --dlopen|-dlopen) optarg="$1" opt_dlopen="${opt_dlopen+$opt_dlopen }$optarg" shift ;; --preserve-dup-deps) opt_preserve_dup_deps=: ;; --features) opt_features=: func_features ;; --finish) opt_finish=: set dummy --mode finish ${1+"$@"}; shift ;; --help) opt_help=: ;; --help-all) opt_help_all=: opt_help=': help-all' ;; --mode) test $# = 0 && func_missing_arg $opt && break optarg="$1" opt_mode="$optarg" case $optarg in # Valid mode arguments: clean|compile|execute|finish|install|link|relink|uninstall) ;; # Catch anything else as an error *) func_error "invalid argument for $opt" exit_cmd=exit break ;; esac shift ;; --no-silent|--no-quiet) opt_silent=false func_append preserve_args " $opt" ;; --no-verbose) opt_verbose=false func_append preserve_args " $opt" ;; --silent|--quiet) opt_silent=: func_append preserve_args " $opt" opt_verbose=false ;; --verbose|-v) opt_verbose=: func_append preserve_args " $opt" opt_silent=false ;; --tag) test $# = 0 && func_missing_arg $opt && break optarg="$1" opt_tag="$optarg" func_append preserve_args " $opt $optarg" func_enable_tag "$optarg" shift ;; -\?|-h) func_usage ;; --help) func_help ;; --version) func_version ;; # Separate optargs to long options: --*=*) func_split_long_opt "$opt" set dummy "$func_split_long_opt_name" "$func_split_long_opt_arg" ${1+"$@"} shift ;; # Separate non-argument short options: -\?*|-h*|-n*|-v*) func_split_short_opt "$opt" set dummy "$func_split_short_opt_name" "-$func_split_short_opt_arg" ${1+"$@"} shift ;; --) break ;; -*) func_fatal_help "unrecognized option \`$opt'" ;; *) set dummy "$opt" ${1+"$@"}; shift; break ;; esac done # Validate options: # save first non-option argument if test "$#" -gt 0; then nonopt="$opt" shift fi # preserve --debug test "$opt_debug" = : || func_append preserve_args " --debug" case $host in *cygwin* | *mingw* | *pw32* | *cegcc*) # don't eliminate duplications in $postdeps and $predeps opt_duplicate_compiler_generated_deps=: ;; *) opt_duplicate_compiler_generated_deps=$opt_preserve_dup_deps ;; esac $opt_help || { # Sanity checks first: func_check_version_match if test "$build_libtool_libs" != yes && test "$build_old_libs" != yes; then func_fatal_configuration "not configured to build any kind of library" fi # Darwin sucks eval std_shrext=\"$shrext_cmds\" # Only execute mode is allowed to have -dlopen flags. if test -n "$opt_dlopen" && test "$opt_mode" != execute; then func_error "unrecognized option \`-dlopen'" $ECHO "$help" 1>&2 exit $EXIT_FAILURE fi # Change the help message to a mode-specific one. generic_help="$help" help="Try \`$progname --help --mode=$opt_mode' for more information." } # Bail if the options were screwed $exit_cmd $EXIT_FAILURE } ## ----------- ## ## Main. ## ## ----------- ## # func_lalib_p file # True iff FILE is a libtool `.la' library or `.lo' object file. # This function is only a basic sanity check; it will hardly flush out # determined imposters. func_lalib_p () { test -f "$1" && $SED -e 4q "$1" 2>/dev/null \ | $GREP "^# Generated by .*$PACKAGE" > /dev/null 2>&1 } # func_lalib_unsafe_p file # True iff FILE is a libtool `.la' library or `.lo' object file. # This function implements the same check as func_lalib_p without # resorting to external programs. To this end, it redirects stdin and # closes it afterwards, without saving the original file descriptor. # As a safety measure, use it only where a negative result would be # fatal anyway. Works if `file' does not exist. func_lalib_unsafe_p () { lalib_p=no if test -f "$1" && test -r "$1" && exec 5<&0 <"$1"; then for lalib_p_l in 1 2 3 4 do read lalib_p_line case "$lalib_p_line" in \#\ Generated\ by\ *$PACKAGE* ) lalib_p=yes; break;; esac done exec 0<&5 5<&- fi test "$lalib_p" = yes } # func_ltwrapper_script_p file # True iff FILE is a libtool wrapper script # This function is only a basic sanity check; it will hardly flush out # determined imposters. func_ltwrapper_script_p () { func_lalib_p "$1" } # func_ltwrapper_executable_p file # True iff FILE is a libtool wrapper executable # This function is only a basic sanity check; it will hardly flush out # determined imposters. func_ltwrapper_executable_p () { func_ltwrapper_exec_suffix= case $1 in *.exe) ;; *) func_ltwrapper_exec_suffix=.exe ;; esac $GREP "$magic_exe" "$1$func_ltwrapper_exec_suffix" >/dev/null 2>&1 } # func_ltwrapper_scriptname file # Assumes file is an ltwrapper_executable # uses $file to determine the appropriate filename for a # temporary ltwrapper_script. func_ltwrapper_scriptname () { func_dirname_and_basename "$1" "" "." func_stripname '' '.exe' "$func_basename_result" func_ltwrapper_scriptname_result="$func_dirname_result/$objdir/${func_stripname_result}_ltshwrapper" } # func_ltwrapper_p file # True iff FILE is a libtool wrapper script or wrapper executable # This function is only a basic sanity check; it will hardly flush out # determined imposters. func_ltwrapper_p () { func_ltwrapper_script_p "$1" || func_ltwrapper_executable_p "$1" } # func_execute_cmds commands fail_cmd # Execute tilde-delimited COMMANDS. # If FAIL_CMD is given, eval that upon failure. # FAIL_CMD may read-access the current command in variable CMD! func_execute_cmds () { $opt_debug save_ifs=$IFS; IFS='~' for cmd in $1; do IFS=$save_ifs eval cmd=\"$cmd\" func_show_eval "$cmd" "${2-:}" done IFS=$save_ifs } # func_source file # Source FILE, adding directory component if necessary. # Note that it is not necessary on cygwin/mingw to append a dot to # FILE even if both FILE and FILE.exe exist: automatic-append-.exe # behavior happens only for exec(3), not for open(2)! Also, sourcing # `FILE.' does not work on cygwin managed mounts. func_source () { $opt_debug case $1 in */* | *\\*) . "$1" ;; *) . "./$1" ;; esac } # func_resolve_sysroot PATH # Replace a leading = in PATH with a sysroot. Store the result into # func_resolve_sysroot_result func_resolve_sysroot () { func_resolve_sysroot_result=$1 case $func_resolve_sysroot_result in =*) func_stripname '=' '' "$func_resolve_sysroot_result" func_resolve_sysroot_result=$lt_sysroot$func_stripname_result ;; esac } # func_replace_sysroot PATH # If PATH begins with the sysroot, replace it with = and # store the result into func_replace_sysroot_result. func_replace_sysroot () { case "$lt_sysroot:$1" in ?*:"$lt_sysroot"*) func_stripname "$lt_sysroot" '' "$1" func_replace_sysroot_result="=$func_stripname_result" ;; *) # Including no sysroot. func_replace_sysroot_result=$1 ;; esac } # func_infer_tag arg # Infer tagged configuration to use if any are available and # if one wasn't chosen via the "--tag" command line option. # Only attempt this if the compiler in the base compile # command doesn't match the default compiler. # arg is usually of the form 'gcc ...' func_infer_tag () { $opt_debug if test -n "$available_tags" && test -z "$tagname"; then CC_quoted= for arg in $CC; do func_append_quoted CC_quoted "$arg" done CC_expanded=`func_echo_all $CC` CC_quoted_expanded=`func_echo_all $CC_quoted` case $@ in # Blanks in the command may have been stripped by the calling shell, # but not from the CC environment variable when configure was run. " $CC "* | "$CC "* | " $CC_expanded "* | "$CC_expanded "* | \ " $CC_quoted"* | "$CC_quoted "* | " $CC_quoted_expanded "* | "$CC_quoted_expanded "*) ;; # Blanks at the start of $base_compile will cause this to fail # if we don't check for them as well. *) for z in $available_tags; do if $GREP "^# ### BEGIN LIBTOOL TAG CONFIG: $z$" < "$progpath" > /dev/null; then # Evaluate the configuration. eval "`${SED} -n -e '/^# ### BEGIN LIBTOOL TAG CONFIG: '$z'$/,/^# ### END LIBTOOL TAG CONFIG: '$z'$/p' < $progpath`" CC_quoted= for arg in $CC; do # Double-quote args containing other shell metacharacters. func_append_quoted CC_quoted "$arg" done CC_expanded=`func_echo_all $CC` CC_quoted_expanded=`func_echo_all $CC_quoted` case "$@ " in " $CC "* | "$CC "* | " $CC_expanded "* | "$CC_expanded "* | \ " $CC_quoted"* | "$CC_quoted "* | " $CC_quoted_expanded "* | "$CC_quoted_expanded "*) # The compiler in the base compile command matches # the one in the tagged configuration. # Assume this is the tagged configuration we want. tagname=$z break ;; esac fi done # If $tagname still isn't set, then no tagged configuration # was found and let the user know that the "--tag" command # line option must be used. if test -z "$tagname"; then func_echo "unable to infer tagged configuration" func_fatal_error "specify a tag with \`--tag'" # else # func_verbose "using $tagname tagged configuration" fi ;; esac fi } # func_write_libtool_object output_name pic_name nonpic_name # Create a libtool object file (analogous to a ".la" file), # but don't create it if we're doing a dry run. func_write_libtool_object () { write_libobj=${1} if test "$build_libtool_libs" = yes; then write_lobj=\'${2}\' else write_lobj=none fi if test "$build_old_libs" = yes; then write_oldobj=\'${3}\' else write_oldobj=none fi $opt_dry_run || { cat >${write_libobj}T </dev/null` if test "$?" -eq 0 && test -n "${func_convert_core_file_wine_to_w32_tmp}"; then func_convert_core_file_wine_to_w32_result=`$ECHO "$func_convert_core_file_wine_to_w32_tmp" | $SED -e "$lt_sed_naive_backslashify"` else func_convert_core_file_wine_to_w32_result= fi fi } # end: func_convert_core_file_wine_to_w32 # func_convert_core_path_wine_to_w32 ARG # Helper function used by path conversion functions when $build is *nix, and # $host is mingw, cygwin, or some other w32 environment. Relies on a correctly # configured wine environment available, with the winepath program in $build's # $PATH. Assumes ARG has no leading or trailing path separator characters. # # ARG is path to be converted from $build format to win32. # Result is available in $func_convert_core_path_wine_to_w32_result. # Unconvertible file (directory) names in ARG are skipped; if no directory names # are convertible, then the result may be empty. func_convert_core_path_wine_to_w32 () { $opt_debug # unfortunately, winepath doesn't convert paths, only file names func_convert_core_path_wine_to_w32_result="" if test -n "$1"; then oldIFS=$IFS IFS=: for func_convert_core_path_wine_to_w32_f in $1; do IFS=$oldIFS func_convert_core_file_wine_to_w32 "$func_convert_core_path_wine_to_w32_f" if test -n "$func_convert_core_file_wine_to_w32_result" ; then if test -z "$func_convert_core_path_wine_to_w32_result"; then func_convert_core_path_wine_to_w32_result="$func_convert_core_file_wine_to_w32_result" else func_append func_convert_core_path_wine_to_w32_result ";$func_convert_core_file_wine_to_w32_result" fi fi done IFS=$oldIFS fi } # end: func_convert_core_path_wine_to_w32 # func_cygpath ARGS... # Wrapper around calling the cygpath program via LT_CYGPATH. This is used when # when (1) $build is *nix and Cygwin is hosted via a wine environment; or (2) # $build is MSYS and $host is Cygwin, or (3) $build is Cygwin. In case (1) or # (2), returns the Cygwin file name or path in func_cygpath_result (input # file name or path is assumed to be in w32 format, as previously converted # from $build's *nix or MSYS format). In case (3), returns the w32 file name # or path in func_cygpath_result (input file name or path is assumed to be in # Cygwin format). Returns an empty string on error. # # ARGS are passed to cygpath, with the last one being the file name or path to # be converted. # # Specify the absolute *nix (or w32) name to cygpath in the LT_CYGPATH # environment variable; do not put it in $PATH. func_cygpath () { $opt_debug if test -n "$LT_CYGPATH" && test -f "$LT_CYGPATH"; then func_cygpath_result=`$LT_CYGPATH "$@" 2>/dev/null` if test "$?" -ne 0; then # on failure, ensure result is empty func_cygpath_result= fi else func_cygpath_result= func_error "LT_CYGPATH is empty or specifies non-existent file: \`$LT_CYGPATH'" fi } #end: func_cygpath # func_convert_core_msys_to_w32 ARG # Convert file name or path ARG from MSYS format to w32 format. Return # result in func_convert_core_msys_to_w32_result. func_convert_core_msys_to_w32 () { $opt_debug # awkward: cmd appends spaces to result func_convert_core_msys_to_w32_result=`( cmd //c echo "$1" ) 2>/dev/null | $SED -e 's/[ ]*$//' -e "$lt_sed_naive_backslashify"` } #end: func_convert_core_msys_to_w32 # func_convert_file_check ARG1 ARG2 # Verify that ARG1 (a file name in $build format) was converted to $host # format in ARG2. Otherwise, emit an error message, but continue (resetting # func_to_host_file_result to ARG1). func_convert_file_check () { $opt_debug if test -z "$2" && test -n "$1" ; then func_error "Could not determine host file name corresponding to" func_error " \`$1'" func_error "Continuing, but uninstalled executables may not work." # Fallback: func_to_host_file_result="$1" fi } # end func_convert_file_check # func_convert_path_check FROM_PATHSEP TO_PATHSEP FROM_PATH TO_PATH # Verify that FROM_PATH (a path in $build format) was converted to $host # format in TO_PATH. Otherwise, emit an error message, but continue, resetting # func_to_host_file_result to a simplistic fallback value (see below). func_convert_path_check () { $opt_debug if test -z "$4" && test -n "$3"; then func_error "Could not determine the host path corresponding to" func_error " \`$3'" func_error "Continuing, but uninstalled executables may not work." # Fallback. This is a deliberately simplistic "conversion" and # should not be "improved". See libtool.info. if test "x$1" != "x$2"; then lt_replace_pathsep_chars="s|$1|$2|g" func_to_host_path_result=`echo "$3" | $SED -e "$lt_replace_pathsep_chars"` else func_to_host_path_result="$3" fi fi } # end func_convert_path_check # func_convert_path_front_back_pathsep FRONTPAT BACKPAT REPL ORIG # Modifies func_to_host_path_result by prepending REPL if ORIG matches FRONTPAT # and appending REPL if ORIG matches BACKPAT. func_convert_path_front_back_pathsep () { $opt_debug case $4 in $1 ) func_to_host_path_result="$3$func_to_host_path_result" ;; esac case $4 in $2 ) func_append func_to_host_path_result "$3" ;; esac } # end func_convert_path_front_back_pathsep ################################################## # $build to $host FILE NAME CONVERSION FUNCTIONS # ################################################## # invoked via `$to_host_file_cmd ARG' # # In each case, ARG is the path to be converted from $build to $host format. # Result will be available in $func_to_host_file_result. # func_to_host_file ARG # Converts the file name ARG from $build format to $host format. Return result # in func_to_host_file_result. func_to_host_file () { $opt_debug $to_host_file_cmd "$1" } # end func_to_host_file # func_to_tool_file ARG LAZY # converts the file name ARG from $build format to toolchain format. Return # result in func_to_tool_file_result. If the conversion in use is listed # in (the comma separated) LAZY, no conversion takes place. func_to_tool_file () { $opt_debug case ,$2, in *,"$to_tool_file_cmd",*) func_to_tool_file_result=$1 ;; *) $to_tool_file_cmd "$1" func_to_tool_file_result=$func_to_host_file_result ;; esac } # end func_to_tool_file # func_convert_file_noop ARG # Copy ARG to func_to_host_file_result. func_convert_file_noop () { func_to_host_file_result="$1" } # end func_convert_file_noop # func_convert_file_msys_to_w32 ARG # Convert file name ARG from (mingw) MSYS to (mingw) w32 format; automatic # conversion to w32 is not available inside the cwrapper. Returns result in # func_to_host_file_result. func_convert_file_msys_to_w32 () { $opt_debug func_to_host_file_result="$1" if test -n "$1"; then func_convert_core_msys_to_w32 "$1" func_to_host_file_result="$func_convert_core_msys_to_w32_result" fi func_convert_file_check "$1" "$func_to_host_file_result" } # end func_convert_file_msys_to_w32 # func_convert_file_cygwin_to_w32 ARG # Convert file name ARG from Cygwin to w32 format. Returns result in # func_to_host_file_result. func_convert_file_cygwin_to_w32 () { $opt_debug func_to_host_file_result="$1" if test -n "$1"; then # because $build is cygwin, we call "the" cygpath in $PATH; no need to use # LT_CYGPATH in this case. func_to_host_file_result=`cygpath -m "$1"` fi func_convert_file_check "$1" "$func_to_host_file_result" } # end func_convert_file_cygwin_to_w32 # func_convert_file_nix_to_w32 ARG # Convert file name ARG from *nix to w32 format. Requires a wine environment # and a working winepath. Returns result in func_to_host_file_result. func_convert_file_nix_to_w32 () { $opt_debug func_to_host_file_result="$1" if test -n "$1"; then func_convert_core_file_wine_to_w32 "$1" func_to_host_file_result="$func_convert_core_file_wine_to_w32_result" fi func_convert_file_check "$1" "$func_to_host_file_result" } # end func_convert_file_nix_to_w32 # func_convert_file_msys_to_cygwin ARG # Convert file name ARG from MSYS to Cygwin format. Requires LT_CYGPATH set. # Returns result in func_to_host_file_result. func_convert_file_msys_to_cygwin () { $opt_debug func_to_host_file_result="$1" if test -n "$1"; then func_convert_core_msys_to_w32 "$1" func_cygpath -u "$func_convert_core_msys_to_w32_result" func_to_host_file_result="$func_cygpath_result" fi func_convert_file_check "$1" "$func_to_host_file_result" } # end func_convert_file_msys_to_cygwin # func_convert_file_nix_to_cygwin ARG # Convert file name ARG from *nix to Cygwin format. Requires Cygwin installed # in a wine environment, working winepath, and LT_CYGPATH set. Returns result # in func_to_host_file_result. func_convert_file_nix_to_cygwin () { $opt_debug func_to_host_file_result="$1" if test -n "$1"; then # convert from *nix to w32, then use cygpath to convert from w32 to cygwin. func_convert_core_file_wine_to_w32 "$1" func_cygpath -u "$func_convert_core_file_wine_to_w32_result" func_to_host_file_result="$func_cygpath_result" fi func_convert_file_check "$1" "$func_to_host_file_result" } # end func_convert_file_nix_to_cygwin ############################################# # $build to $host PATH CONVERSION FUNCTIONS # ############################################# # invoked via `$to_host_path_cmd ARG' # # In each case, ARG is the path to be converted from $build to $host format. # The result will be available in $func_to_host_path_result. # # Path separators are also converted from $build format to $host format. If # ARG begins or ends with a path separator character, it is preserved (but # converted to $host format) on output. # # All path conversion functions are named using the following convention: # file name conversion function : func_convert_file_X_to_Y () # path conversion function : func_convert_path_X_to_Y () # where, for any given $build/$host combination the 'X_to_Y' value is the # same. If conversion functions are added for new $build/$host combinations, # the two new functions must follow this pattern, or func_init_to_host_path_cmd # will break. # func_init_to_host_path_cmd # Ensures that function "pointer" variable $to_host_path_cmd is set to the # appropriate value, based on the value of $to_host_file_cmd. to_host_path_cmd= func_init_to_host_path_cmd () { $opt_debug if test -z "$to_host_path_cmd"; then func_stripname 'func_convert_file_' '' "$to_host_file_cmd" to_host_path_cmd="func_convert_path_${func_stripname_result}" fi } # func_to_host_path ARG # Converts the path ARG from $build format to $host format. Return result # in func_to_host_path_result. func_to_host_path () { $opt_debug func_init_to_host_path_cmd $to_host_path_cmd "$1" } # end func_to_host_path # func_convert_path_noop ARG # Copy ARG to func_to_host_path_result. func_convert_path_noop () { func_to_host_path_result="$1" } # end func_convert_path_noop # func_convert_path_msys_to_w32 ARG # Convert path ARG from (mingw) MSYS to (mingw) w32 format; automatic # conversion to w32 is not available inside the cwrapper. Returns result in # func_to_host_path_result. func_convert_path_msys_to_w32 () { $opt_debug func_to_host_path_result="$1" if test -n "$1"; then # Remove leading and trailing path separator characters from ARG. MSYS # behavior is inconsistent here; cygpath turns them into '.;' and ';.'; # and winepath ignores them completely. func_stripname : : "$1" func_to_host_path_tmp1=$func_stripname_result func_convert_core_msys_to_w32 "$func_to_host_path_tmp1" func_to_host_path_result="$func_convert_core_msys_to_w32_result" func_convert_path_check : ";" \ "$func_to_host_path_tmp1" "$func_to_host_path_result" func_convert_path_front_back_pathsep ":*" "*:" ";" "$1" fi } # end func_convert_path_msys_to_w32 # func_convert_path_cygwin_to_w32 ARG # Convert path ARG from Cygwin to w32 format. Returns result in # func_to_host_file_result. func_convert_path_cygwin_to_w32 () { $opt_debug func_to_host_path_result="$1" if test -n "$1"; then # See func_convert_path_msys_to_w32: func_stripname : : "$1" func_to_host_path_tmp1=$func_stripname_result func_to_host_path_result=`cygpath -m -p "$func_to_host_path_tmp1"` func_convert_path_check : ";" \ "$func_to_host_path_tmp1" "$func_to_host_path_result" func_convert_path_front_back_pathsep ":*" "*:" ";" "$1" fi } # end func_convert_path_cygwin_to_w32 # func_convert_path_nix_to_w32 ARG # Convert path ARG from *nix to w32 format. Requires a wine environment and # a working winepath. Returns result in func_to_host_file_result. func_convert_path_nix_to_w32 () { $opt_debug func_to_host_path_result="$1" if test -n "$1"; then # See func_convert_path_msys_to_w32: func_stripname : : "$1" func_to_host_path_tmp1=$func_stripname_result func_convert_core_path_wine_to_w32 "$func_to_host_path_tmp1" func_to_host_path_result="$func_convert_core_path_wine_to_w32_result" func_convert_path_check : ";" \ "$func_to_host_path_tmp1" "$func_to_host_path_result" func_convert_path_front_back_pathsep ":*" "*:" ";" "$1" fi } # end func_convert_path_nix_to_w32 # func_convert_path_msys_to_cygwin ARG # Convert path ARG from MSYS to Cygwin format. Requires LT_CYGPATH set. # Returns result in func_to_host_file_result. func_convert_path_msys_to_cygwin () { $opt_debug func_to_host_path_result="$1" if test -n "$1"; then # See func_convert_path_msys_to_w32: func_stripname : : "$1" func_to_host_path_tmp1=$func_stripname_result func_convert_core_msys_to_w32 "$func_to_host_path_tmp1" func_cygpath -u -p "$func_convert_core_msys_to_w32_result" func_to_host_path_result="$func_cygpath_result" func_convert_path_check : : \ "$func_to_host_path_tmp1" "$func_to_host_path_result" func_convert_path_front_back_pathsep ":*" "*:" : "$1" fi } # end func_convert_path_msys_to_cygwin # func_convert_path_nix_to_cygwin ARG # Convert path ARG from *nix to Cygwin format. Requires Cygwin installed in a # a wine environment, working winepath, and LT_CYGPATH set. Returns result in # func_to_host_file_result. func_convert_path_nix_to_cygwin () { $opt_debug func_to_host_path_result="$1" if test -n "$1"; then # Remove leading and trailing path separator characters from # ARG. msys behavior is inconsistent here, cygpath turns them # into '.;' and ';.', and winepath ignores them completely. func_stripname : : "$1" func_to_host_path_tmp1=$func_stripname_result func_convert_core_path_wine_to_w32 "$func_to_host_path_tmp1" func_cygpath -u -p "$func_convert_core_path_wine_to_w32_result" func_to_host_path_result="$func_cygpath_result" func_convert_path_check : : \ "$func_to_host_path_tmp1" "$func_to_host_path_result" func_convert_path_front_back_pathsep ":*" "*:" : "$1" fi } # end func_convert_path_nix_to_cygwin # func_mode_compile arg... func_mode_compile () { $opt_debug # Get the compilation command and the source file. base_compile= srcfile="$nonopt" # always keep a non-empty value in "srcfile" suppress_opt=yes suppress_output= arg_mode=normal libobj= later= pie_flag= for arg do case $arg_mode in arg ) # do not "continue". Instead, add this to base_compile lastarg="$arg" arg_mode=normal ;; target ) libobj="$arg" arg_mode=normal continue ;; normal ) # Accept any command-line options. case $arg in -o) test -n "$libobj" && \ func_fatal_error "you cannot specify \`-o' more than once" arg_mode=target continue ;; -pie | -fpie | -fPIE) func_append pie_flag " $arg" continue ;; -shared | -static | -prefer-pic | -prefer-non-pic) func_append later " $arg" continue ;; -no-suppress) suppress_opt=no continue ;; -Xcompiler) arg_mode=arg # the next one goes into the "base_compile" arg list continue # The current "srcfile" will either be retained or ;; # replaced later. I would guess that would be a bug. -Wc,*) func_stripname '-Wc,' '' "$arg" args=$func_stripname_result lastarg= save_ifs="$IFS"; IFS=',' for arg in $args; do IFS="$save_ifs" func_append_quoted lastarg "$arg" done IFS="$save_ifs" func_stripname ' ' '' "$lastarg" lastarg=$func_stripname_result # Add the arguments to base_compile. func_append base_compile " $lastarg" continue ;; *) # Accept the current argument as the source file. # The previous "srcfile" becomes the current argument. # lastarg="$srcfile" srcfile="$arg" ;; esac # case $arg ;; esac # case $arg_mode # Aesthetically quote the previous argument. func_append_quoted base_compile "$lastarg" done # for arg case $arg_mode in arg) func_fatal_error "you must specify an argument for -Xcompile" ;; target) func_fatal_error "you must specify a target with \`-o'" ;; *) # Get the name of the library object. test -z "$libobj" && { func_basename "$srcfile" libobj="$func_basename_result" } ;; esac # Recognize several different file suffixes. # If the user specifies -o file.o, it is replaced with file.lo case $libobj in *.[cCFSifmso] | \ *.ada | *.adb | *.ads | *.asm | \ *.c++ | *.cc | *.ii | *.class | *.cpp | *.cxx | \ *.[fF][09]? | *.for | *.java | *.obj | *.sx | *.cu | *.cup) func_xform "$libobj" libobj=$func_xform_result ;; esac case $libobj in *.lo) func_lo2o "$libobj"; obj=$func_lo2o_result ;; *) func_fatal_error "cannot determine name of library object from \`$libobj'" ;; esac func_infer_tag $base_compile for arg in $later; do case $arg in -shared) test "$build_libtool_libs" != yes && \ func_fatal_configuration "can not build a shared library" build_old_libs=no continue ;; -static) build_libtool_libs=no build_old_libs=yes continue ;; -prefer-pic) pic_mode=yes continue ;; -prefer-non-pic) pic_mode=no continue ;; esac done func_quote_for_eval "$libobj" test "X$libobj" != "X$func_quote_for_eval_result" \ && $ECHO "X$libobj" | $GREP '[]~#^*{};<>?"'"'"' &()|`$[]' \ && func_warning "libobj name \`$libobj' may not contain shell special characters." func_dirname_and_basename "$obj" "/" "" objname="$func_basename_result" xdir="$func_dirname_result" lobj=${xdir}$objdir/$objname test -z "$base_compile" && \ func_fatal_help "you must specify a compilation command" # Delete any leftover library objects. if test "$build_old_libs" = yes; then removelist="$obj $lobj $libobj ${libobj}T" else removelist="$lobj $libobj ${libobj}T" fi # On Cygwin there's no "real" PIC flag so we must build both object types case $host_os in cygwin* | mingw* | pw32* | os2* | cegcc*) pic_mode=default ;; esac if test "$pic_mode" = no && test "$deplibs_check_method" != pass_all; then # non-PIC code in shared libraries is not supported pic_mode=default fi # Calculate the filename of the output object if compiler does # not support -o with -c if test "$compiler_c_o" = no; then output_obj=`$ECHO "$srcfile" | $SED 's%^.*/%%; s%\.[^.]*$%%'`.${objext} lockfile="$output_obj.lock" else output_obj= need_locks=no lockfile= fi # Lock this critical section if it is needed # We use this script file to make the link, it avoids creating a new file if test "$need_locks" = yes; then until $opt_dry_run || ln "$progpath" "$lockfile" 2>/dev/null; do func_echo "Waiting for $lockfile to be removed" sleep 2 done elif test "$need_locks" = warn; then if test -f "$lockfile"; then $ECHO "\ *** ERROR, $lockfile exists and contains: `cat $lockfile 2>/dev/null` This indicates that another process is trying to use the same temporary object file, and libtool could not work around it because your compiler does not support \`-c' and \`-o' together. If you repeat this compilation, it may succeed, by chance, but you had better avoid parallel builds (make -j) in this platform, or get a better compiler." $opt_dry_run || $RM $removelist exit $EXIT_FAILURE fi func_append removelist " $output_obj" $ECHO "$srcfile" > "$lockfile" fi $opt_dry_run || $RM $removelist func_append removelist " $lockfile" trap '$opt_dry_run || $RM $removelist; exit $EXIT_FAILURE' 1 2 15 func_to_tool_file "$srcfile" func_convert_file_msys_to_w32 srcfile=$func_to_tool_file_result func_quote_for_eval "$srcfile" qsrcfile=$func_quote_for_eval_result # Only build a PIC object if we are building libtool libraries. if test "$build_libtool_libs" = yes; then # Without this assignment, base_compile gets emptied. fbsd_hideous_sh_bug=$base_compile if test "$pic_mode" != no; then command="$base_compile $qsrcfile $pic_flag" else # Don't build PIC code command="$base_compile $qsrcfile" fi func_mkdir_p "$xdir$objdir" if test -z "$output_obj"; then # Place PIC objects in $objdir func_append command " -o $lobj" fi func_show_eval_locale "$command" \ 'test -n "$output_obj" && $RM $removelist; exit $EXIT_FAILURE' if test "$need_locks" = warn && test "X`cat $lockfile 2>/dev/null`" != "X$srcfile"; then $ECHO "\ *** ERROR, $lockfile contains: `cat $lockfile 2>/dev/null` but it should contain: $srcfile This indicates that another process is trying to use the same temporary object file, and libtool could not work around it because your compiler does not support \`-c' and \`-o' together. If you repeat this compilation, it may succeed, by chance, but you had better avoid parallel builds (make -j) in this platform, or get a better compiler." $opt_dry_run || $RM $removelist exit $EXIT_FAILURE fi # Just move the object if needed, then go on to compile the next one if test -n "$output_obj" && test "X$output_obj" != "X$lobj"; then func_show_eval '$MV "$output_obj" "$lobj"' \ 'error=$?; $opt_dry_run || $RM $removelist; exit $error' fi # Allow error messages only from the first compilation. if test "$suppress_opt" = yes; then suppress_output=' >/dev/null 2>&1' fi fi # Only build a position-dependent object if we build old libraries. if test "$build_old_libs" = yes; then if test "$pic_mode" != yes; then # Don't build PIC code command="$base_compile $qsrcfile$pie_flag" else command="$base_compile $qsrcfile $pic_flag" fi if test "$compiler_c_o" = yes; then func_append command " -o $obj" fi # Suppress compiler output if we already did a PIC compilation. func_append command "$suppress_output" func_show_eval_locale "$command" \ '$opt_dry_run || $RM $removelist; exit $EXIT_FAILURE' if test "$need_locks" = warn && test "X`cat $lockfile 2>/dev/null`" != "X$srcfile"; then $ECHO "\ *** ERROR, $lockfile contains: `cat $lockfile 2>/dev/null` but it should contain: $srcfile This indicates that another process is trying to use the same temporary object file, and libtool could not work around it because your compiler does not support \`-c' and \`-o' together. If you repeat this compilation, it may succeed, by chance, but you had better avoid parallel builds (make -j) in this platform, or get a better compiler." $opt_dry_run || $RM $removelist exit $EXIT_FAILURE fi # Just move the object if needed if test -n "$output_obj" && test "X$output_obj" != "X$obj"; then func_show_eval '$MV "$output_obj" "$obj"' \ 'error=$?; $opt_dry_run || $RM $removelist; exit $error' fi fi $opt_dry_run || { func_write_libtool_object "$libobj" "$objdir/$objname" "$objname" # Unlock the critical section if it was locked if test "$need_locks" != no; then removelist=$lockfile $RM "$lockfile" fi } exit $EXIT_SUCCESS } $opt_help || { test "$opt_mode" = compile && func_mode_compile ${1+"$@"} } func_mode_help () { # We need to display help for each of the modes. case $opt_mode in "") # Generic help is extracted from the usage comments # at the start of this file. func_help ;; clean) $ECHO \ "Usage: $progname [OPTION]... --mode=clean RM [RM-OPTION]... FILE... Remove files from the build directory. RM is the name of the program to use to delete files associated with each FILE (typically \`/bin/rm'). RM-OPTIONS are options (such as \`-f') to be passed to RM. If FILE is a libtool library, object or program, all the files associated with it are deleted. Otherwise, only FILE itself is deleted using RM." ;; compile) $ECHO \ "Usage: $progname [OPTION]... --mode=compile COMPILE-COMMAND... SOURCEFILE Compile a source file into a libtool library object. This mode accepts the following additional options: -o OUTPUT-FILE set the output file name to OUTPUT-FILE -no-suppress do not suppress compiler output for multiple passes -prefer-pic try to build PIC objects only -prefer-non-pic try to build non-PIC objects only -shared do not build a \`.o' file suitable for static linking -static only build a \`.o' file suitable for static linking -Wc,FLAG pass FLAG directly to the compiler COMPILE-COMMAND is a command to be used in creating a \`standard' object file from the given SOURCEFILE. The output file name is determined by removing the directory component from SOURCEFILE, then substituting the C source code suffix \`.c' with the library object suffix, \`.lo'." ;; execute) $ECHO \ "Usage: $progname [OPTION]... --mode=execute COMMAND [ARGS]... Automatically set library path, then run a program. This mode accepts the following additional options: -dlopen FILE add the directory containing FILE to the library path This mode sets the library path environment variable according to \`-dlopen' flags. If any of the ARGS are libtool executable wrappers, then they are translated into their corresponding uninstalled binary, and any of their required library directories are added to the library path. Then, COMMAND is executed, with ARGS as arguments." ;; finish) $ECHO \ "Usage: $progname [OPTION]... --mode=finish [LIBDIR]... Complete the installation of libtool libraries. Each LIBDIR is a directory that contains libtool libraries. The commands that this mode executes may require superuser privileges. Use the \`--dry-run' option if you just want to see what would be executed." ;; install) $ECHO \ "Usage: $progname [OPTION]... --mode=install INSTALL-COMMAND... Install executables or libraries. INSTALL-COMMAND is the installation command. The first component should be either the \`install' or \`cp' program. The following components of INSTALL-COMMAND are treated specially: -inst-prefix-dir PREFIX-DIR Use PREFIX-DIR as a staging area for installation The rest of the components are interpreted as arguments to that command (only BSD-compatible install options are recognized)." ;; link) $ECHO \ "Usage: $progname [OPTION]... --mode=link LINK-COMMAND... Link object files or libraries together to form another library, or to create an executable program. LINK-COMMAND is a command using the C compiler that you would use to create a program from several object files. The following components of LINK-COMMAND are treated specially: -all-static do not do any dynamic linking at all -avoid-version do not add a version suffix if possible -bindir BINDIR specify path to binaries directory (for systems where libraries must be found in the PATH setting at runtime) -dlopen FILE \`-dlpreopen' FILE if it cannot be dlopened at runtime -dlpreopen FILE link in FILE and add its symbols to lt_preloaded_symbols -export-dynamic allow symbols from OUTPUT-FILE to be resolved with dlsym(3) -export-symbols SYMFILE try to export only the symbols listed in SYMFILE -export-symbols-regex REGEX try to export only the symbols matching REGEX -LLIBDIR search LIBDIR for required installed libraries -lNAME OUTPUT-FILE requires the installed library libNAME -module build a library that can dlopened -no-fast-install disable the fast-install mode -no-install link a not-installable executable -no-undefined declare that a library does not refer to external symbols -o OUTPUT-FILE create OUTPUT-FILE from the specified objects -objectlist FILE Use a list of object files found in FILE to specify objects -precious-files-regex REGEX don't remove output files matching REGEX -release RELEASE specify package release information -rpath LIBDIR the created library will eventually be installed in LIBDIR -R[ ]LIBDIR add LIBDIR to the runtime path of programs and libraries -shared only do dynamic linking of libtool libraries -shrext SUFFIX override the standard shared library file extension -static do not do any dynamic linking of uninstalled libtool libraries -static-libtool-libs do not do any dynamic linking of libtool libraries -version-info CURRENT[:REVISION[:AGE]] specify library version info [each variable defaults to 0] -weak LIBNAME declare that the target provides the LIBNAME interface -Wc,FLAG -Xcompiler FLAG pass linker-specific FLAG directly to the compiler -Wl,FLAG -Xlinker FLAG pass linker-specific FLAG directly to the linker -XCClinker FLAG pass link-specific FLAG to the compiler driver (CC) All other options (arguments beginning with \`-') are ignored. Every other argument is treated as a filename. Files ending in \`.la' are treated as uninstalled libtool libraries, other files are standard or library object files. If the OUTPUT-FILE ends in \`.la', then a libtool library is created, only library objects (\`.lo' files) may be specified, and \`-rpath' is required, except when creating a convenience library. If OUTPUT-FILE ends in \`.a' or \`.lib', then a standard library is created using \`ar' and \`ranlib', or on Windows using \`lib'. If OUTPUT-FILE ends in \`.lo' or \`.${objext}', then a reloadable object file is created, otherwise an executable program is created." ;; uninstall) $ECHO \ "Usage: $progname [OPTION]... --mode=uninstall RM [RM-OPTION]... FILE... Remove libraries from an installation directory. RM is the name of the program to use to delete files associated with each FILE (typically \`/bin/rm'). RM-OPTIONS are options (such as \`-f') to be passed to RM. If FILE is a libtool library, all the files associated with it are deleted. Otherwise, only FILE itself is deleted using RM." ;; *) func_fatal_help "invalid operation mode \`$opt_mode'" ;; esac echo $ECHO "Try \`$progname --help' for more information about other modes." } # Now that we've collected a possible --mode arg, show help if necessary if $opt_help; then if test "$opt_help" = :; then func_mode_help else { func_help noexit for opt_mode in compile link execute install finish uninstall clean; do func_mode_help done } | sed -n '1p; 2,$s/^Usage:/ or: /p' { func_help noexit for opt_mode in compile link execute install finish uninstall clean; do echo func_mode_help done } | sed '1d /^When reporting/,/^Report/{ H d } $x /information about other modes/d /more detailed .*MODE/d s/^Usage:.*--mode=\([^ ]*\) .*/Description of \1 mode:/' fi exit $? fi # func_mode_execute arg... func_mode_execute () { $opt_debug # The first argument is the command name. cmd="$nonopt" test -z "$cmd" && \ func_fatal_help "you must specify a COMMAND" # Handle -dlopen flags immediately. for file in $opt_dlopen; do test -f "$file" \ || func_fatal_help "\`$file' is not a file" dir= case $file in *.la) func_resolve_sysroot "$file" file=$func_resolve_sysroot_result # Check to see that this really is a libtool archive. func_lalib_unsafe_p "$file" \ || func_fatal_help "\`$lib' is not a valid libtool archive" # Read the libtool library. dlname= library_names= func_source "$file" # Skip this library if it cannot be dlopened. if test -z "$dlname"; then # Warn if it was a shared library. test -n "$library_names" && \ func_warning "\`$file' was not linked with \`-export-dynamic'" continue fi func_dirname "$file" "" "." dir="$func_dirname_result" if test -f "$dir/$objdir/$dlname"; then func_append dir "/$objdir" else if test ! -f "$dir/$dlname"; then func_fatal_error "cannot find \`$dlname' in \`$dir' or \`$dir/$objdir'" fi fi ;; *.lo) # Just add the directory containing the .lo file. func_dirname "$file" "" "." dir="$func_dirname_result" ;; *) func_warning "\`-dlopen' is ignored for non-libtool libraries and objects" continue ;; esac # Get the absolute pathname. absdir=`cd "$dir" && pwd` test -n "$absdir" && dir="$absdir" # Now add the directory to shlibpath_var. if eval "test -z \"\$$shlibpath_var\""; then eval "$shlibpath_var=\"\$dir\"" else eval "$shlibpath_var=\"\$dir:\$$shlibpath_var\"" fi done # This variable tells wrapper scripts just to set shlibpath_var # rather than running their programs. libtool_execute_magic="$magic" # Check if any of the arguments is a wrapper script. args= for file do case $file in -* | *.la | *.lo ) ;; *) # Do a test to see if this is really a libtool program. if func_ltwrapper_script_p "$file"; then func_source "$file" # Transform arg to wrapped name. file="$progdir/$program" elif func_ltwrapper_executable_p "$file"; then func_ltwrapper_scriptname "$file" func_source "$func_ltwrapper_scriptname_result" # Transform arg to wrapped name. file="$progdir/$program" fi ;; esac # Quote arguments (to preserve shell metacharacters). func_append_quoted args "$file" done if test "X$opt_dry_run" = Xfalse; then if test -n "$shlibpath_var"; then # Export the shlibpath_var. eval "export $shlibpath_var" fi # Restore saved environment variables for lt_var in LANG LANGUAGE LC_ALL LC_CTYPE LC_COLLATE LC_MESSAGES do eval "if test \"\${save_$lt_var+set}\" = set; then $lt_var=\$save_$lt_var; export $lt_var else $lt_unset $lt_var fi" done # Now prepare to actually exec the command. exec_cmd="\$cmd$args" else # Display what would be done. if test -n "$shlibpath_var"; then eval "\$ECHO \"\$shlibpath_var=\$$shlibpath_var\"" echo "export $shlibpath_var" fi $ECHO "$cmd$args" exit $EXIT_SUCCESS fi } test "$opt_mode" = execute && func_mode_execute ${1+"$@"} # func_mode_finish arg... func_mode_finish () { $opt_debug libs= libdirs= admincmds= for opt in "$nonopt" ${1+"$@"} do if test -d "$opt"; then func_append libdirs " $opt" elif test -f "$opt"; then if func_lalib_unsafe_p "$opt"; then func_append libs " $opt" else func_warning "\`$opt' is not a valid libtool archive" fi else func_fatal_error "invalid argument \`$opt'" fi done if test -n "$libs"; then if test -n "$lt_sysroot"; then sysroot_regex=`$ECHO "$lt_sysroot" | $SED "$sed_make_literal_regex"` sysroot_cmd="s/\([ ']\)$sysroot_regex/\1/g;" else sysroot_cmd= fi # Remove sysroot references if $opt_dry_run; then for lib in $libs; do echo "removing references to $lt_sysroot and \`=' prefixes from $lib" done else tmpdir=`func_mktempdir` for lib in $libs; do sed -e "${sysroot_cmd} s/\([ ']-[LR]\)=/\1/g; s/\([ ']\)=/\1/g" $lib \ > $tmpdir/tmp-la mv -f $tmpdir/tmp-la $lib done ${RM}r "$tmpdir" fi fi if test -n "$finish_cmds$finish_eval" && test -n "$libdirs"; then for libdir in $libdirs; do if test -n "$finish_cmds"; then # Do each command in the finish commands. func_execute_cmds "$finish_cmds" 'admincmds="$admincmds '"$cmd"'"' fi if test -n "$finish_eval"; then # Do the single finish_eval. eval cmds=\"$finish_eval\" $opt_dry_run || eval "$cmds" || func_append admincmds " $cmds" fi done fi # Exit here if they wanted silent mode. $opt_silent && exit $EXIT_SUCCESS if test -n "$finish_cmds$finish_eval" && test -n "$libdirs"; then echo "----------------------------------------------------------------------" echo "Libraries have been installed in:" for libdir in $libdirs; do $ECHO " $libdir" done echo echo "If you ever happen to want to link against installed libraries" echo "in a given directory, LIBDIR, you must either use libtool, and" echo "specify the full pathname of the library, or use the \`-LLIBDIR'" echo "flag during linking and do at least one of the following:" if test -n "$shlibpath_var"; then echo " - add LIBDIR to the \`$shlibpath_var' environment variable" echo " during execution" fi if test -n "$runpath_var"; then echo " - add LIBDIR to the \`$runpath_var' environment variable" echo " during linking" fi if test -n "$hardcode_libdir_flag_spec"; then libdir=LIBDIR eval flag=\"$hardcode_libdir_flag_spec\" $ECHO " - use the \`$flag' linker flag" fi if test -n "$admincmds"; then $ECHO " - have your system administrator run these commands:$admincmds" fi if test -f /etc/ld.so.conf; then echo " - have your system administrator add LIBDIR to \`/etc/ld.so.conf'" fi echo echo "See any operating system documentation about shared libraries for" case $host in solaris2.[6789]|solaris2.1[0-9]) echo "more information, such as the ld(1), crle(1) and ld.so(8) manual" echo "pages." ;; *) echo "more information, such as the ld(1) and ld.so(8) manual pages." ;; esac echo "----------------------------------------------------------------------" fi exit $EXIT_SUCCESS } test "$opt_mode" = finish && func_mode_finish ${1+"$@"} # func_mode_install arg... func_mode_install () { $opt_debug # There may be an optional sh(1) argument at the beginning of # install_prog (especially on Windows NT). if test "$nonopt" = "$SHELL" || test "$nonopt" = /bin/sh || # Allow the use of GNU shtool's install command. case $nonopt in *shtool*) :;; *) false;; esac; then # Aesthetically quote it. func_quote_for_eval "$nonopt" install_prog="$func_quote_for_eval_result " arg=$1 shift else install_prog= arg=$nonopt fi # The real first argument should be the name of the installation program. # Aesthetically quote it. func_quote_for_eval "$arg" func_append install_prog "$func_quote_for_eval_result" install_shared_prog=$install_prog case " $install_prog " in *[\\\ /]cp\ *) install_cp=: ;; *) install_cp=false ;; esac # We need to accept at least all the BSD install flags. dest= files= opts= prev= install_type= isdir=no stripme= no_mode=: for arg do arg2= if test -n "$dest"; then func_append files " $dest" dest=$arg continue fi case $arg in -d) isdir=yes ;; -f) if $install_cp; then :; else prev=$arg fi ;; -g | -m | -o) prev=$arg ;; -s) stripme=" -s" continue ;; -*) ;; *) # If the previous option needed an argument, then skip it. if test -n "$prev"; then if test "x$prev" = x-m && test -n "$install_override_mode"; then arg2=$install_override_mode no_mode=false fi prev= else dest=$arg continue fi ;; esac # Aesthetically quote the argument. func_quote_for_eval "$arg" func_append install_prog " $func_quote_for_eval_result" if test -n "$arg2"; then func_quote_for_eval "$arg2" fi func_append install_shared_prog " $func_quote_for_eval_result" done test -z "$install_prog" && \ func_fatal_help "you must specify an install program" test -n "$prev" && \ func_fatal_help "the \`$prev' option requires an argument" if test -n "$install_override_mode" && $no_mode; then if $install_cp; then :; else func_quote_for_eval "$install_override_mode" func_append install_shared_prog " -m $func_quote_for_eval_result" fi fi if test -z "$files"; then if test -z "$dest"; then func_fatal_help "no file or destination specified" else func_fatal_help "you must specify a destination" fi fi # Strip any trailing slash from the destination. func_stripname '' '/' "$dest" dest=$func_stripname_result # Check to see that the destination is a directory. test -d "$dest" && isdir=yes if test "$isdir" = yes; then destdir="$dest" destname= else func_dirname_and_basename "$dest" "" "." destdir="$func_dirname_result" destname="$func_basename_result" # Not a directory, so check to see that there is only one file specified. set dummy $files; shift test "$#" -gt 1 && \ func_fatal_help "\`$dest' is not a directory" fi case $destdir in [\\/]* | [A-Za-z]:[\\/]*) ;; *) for file in $files; do case $file in *.lo) ;; *) func_fatal_help "\`$destdir' must be an absolute directory name" ;; esac done ;; esac # This variable tells wrapper scripts just to set variables rather # than running their programs. libtool_install_magic="$magic" staticlibs= future_libdirs= current_libdirs= for file in $files; do # Do each installation. case $file in *.$libext) # Do the static libraries later. func_append staticlibs " $file" ;; *.la) func_resolve_sysroot "$file" file=$func_resolve_sysroot_result # Check to see that this really is a libtool archive. func_lalib_unsafe_p "$file" \ || func_fatal_help "\`$file' is not a valid libtool archive" library_names= old_library= relink_command= func_source "$file" # Add the libdir to current_libdirs if it is the destination. if test "X$destdir" = "X$libdir"; then case "$current_libdirs " in *" $libdir "*) ;; *) func_append current_libdirs " $libdir" ;; esac else # Note the libdir as a future libdir. case "$future_libdirs " in *" $libdir "*) ;; *) func_append future_libdirs " $libdir" ;; esac fi func_dirname "$file" "/" "" dir="$func_dirname_result" func_append dir "$objdir" if test -n "$relink_command"; then # Determine the prefix the user has applied to our future dir. inst_prefix_dir=`$ECHO "$destdir" | $SED -e "s%$libdir\$%%"` # Don't allow the user to place us outside of our expected # location b/c this prevents finding dependent libraries that # are installed to the same prefix. # At present, this check doesn't affect windows .dll's that # are installed into $libdir/../bin (currently, that works fine) # but it's something to keep an eye on. test "$inst_prefix_dir" = "$destdir" && \ func_fatal_error "error: cannot install \`$file' to a directory not ending in $libdir" if test -n "$inst_prefix_dir"; then # Stick the inst_prefix_dir data into the link command. relink_command=`$ECHO "$relink_command" | $SED "s%@inst_prefix_dir@%-inst-prefix-dir $inst_prefix_dir%"` else relink_command=`$ECHO "$relink_command" | $SED "s%@inst_prefix_dir@%%"` fi func_warning "relinking \`$file'" func_show_eval "$relink_command" \ 'func_fatal_error "error: relink \`$file'\'' with the above command before installing it"' fi # See the names of the shared library. set dummy $library_names; shift if test -n "$1"; then realname="$1" shift srcname="$realname" test -n "$relink_command" && srcname="$realname"T # Install the shared library and build the symlinks. func_show_eval "$install_shared_prog $dir/$srcname $destdir/$realname" \ 'exit $?' tstripme="$stripme" case $host_os in cygwin* | mingw* | pw32* | cegcc*) case $realname in *.dll.a) tstripme="" ;; esac ;; esac if test -n "$tstripme" && test -n "$striplib"; then func_show_eval "$striplib $destdir/$realname" 'exit $?' fi if test "$#" -gt 0; then # Delete the old symlinks, and create new ones. # Try `ln -sf' first, because the `ln' binary might depend on # the symlink we replace! Solaris /bin/ln does not understand -f, # so we also need to try rm && ln -s. for linkname do test "$linkname" != "$realname" \ && func_show_eval "(cd $destdir && { $LN_S -f $realname $linkname || { $RM $linkname && $LN_S $realname $linkname; }; })" done fi # Do each command in the postinstall commands. lib="$destdir/$realname" func_execute_cmds "$postinstall_cmds" 'exit $?' fi # Install the pseudo-library for information purposes. func_basename "$file" name="$func_basename_result" instname="$dir/$name"i func_show_eval "$install_prog $instname $destdir/$name" 'exit $?' # Maybe install the static library, too. test -n "$old_library" && func_append staticlibs " $dir/$old_library" ;; *.lo) # Install (i.e. copy) a libtool object. # Figure out destination file name, if it wasn't already specified. if test -n "$destname"; then destfile="$destdir/$destname" else func_basename "$file" destfile="$func_basename_result" destfile="$destdir/$destfile" fi # Deduce the name of the destination old-style object file. case $destfile in *.lo) func_lo2o "$destfile" staticdest=$func_lo2o_result ;; *.$objext) staticdest="$destfile" destfile= ;; *) func_fatal_help "cannot copy a libtool object to \`$destfile'" ;; esac # Install the libtool object if requested. test -n "$destfile" && \ func_show_eval "$install_prog $file $destfile" 'exit $?' # Install the old object if enabled. if test "$build_old_libs" = yes; then # Deduce the name of the old-style object file. func_lo2o "$file" staticobj=$func_lo2o_result func_show_eval "$install_prog \$staticobj \$staticdest" 'exit $?' fi exit $EXIT_SUCCESS ;; *) # Figure out destination file name, if it wasn't already specified. if test -n "$destname"; then destfile="$destdir/$destname" else func_basename "$file" destfile="$func_basename_result" destfile="$destdir/$destfile" fi # If the file is missing, and there is a .exe on the end, strip it # because it is most likely a libtool script we actually want to # install stripped_ext="" case $file in *.exe) if test ! -f "$file"; then func_stripname '' '.exe' "$file" file=$func_stripname_result stripped_ext=".exe" fi ;; esac # Do a test to see if this is really a libtool program. case $host in *cygwin* | *mingw*) if func_ltwrapper_executable_p "$file"; then func_ltwrapper_scriptname "$file" wrapper=$func_ltwrapper_scriptname_result else func_stripname '' '.exe' "$file" wrapper=$func_stripname_result fi ;; *) wrapper=$file ;; esac if func_ltwrapper_script_p "$wrapper"; then notinst_deplibs= relink_command= func_source "$wrapper" # Check the variables that should have been set. test -z "$generated_by_libtool_version" && \ func_fatal_error "invalid libtool wrapper script \`$wrapper'" finalize=yes for lib in $notinst_deplibs; do # Check to see that each library is installed. libdir= if test -f "$lib"; then func_source "$lib" fi libfile="$libdir/"`$ECHO "$lib" | $SED 's%^.*/%%g'` ### testsuite: skip nested quoting test if test -n "$libdir" && test ! -f "$libfile"; then func_warning "\`$lib' has not been installed in \`$libdir'" finalize=no fi done relink_command= func_source "$wrapper" outputname= if test "$fast_install" = no && test -n "$relink_command"; then $opt_dry_run || { if test "$finalize" = yes; then tmpdir=`func_mktempdir` func_basename "$file$stripped_ext" file="$func_basename_result" outputname="$tmpdir/$file" # Replace the output file specification. relink_command=`$ECHO "$relink_command" | $SED 's%@OUTPUT@%'"$outputname"'%g'` $opt_silent || { func_quote_for_expand "$relink_command" eval "func_echo $func_quote_for_expand_result" } if eval "$relink_command"; then : else func_error "error: relink \`$file' with the above command before installing it" $opt_dry_run || ${RM}r "$tmpdir" continue fi file="$outputname" else func_warning "cannot relink \`$file'" fi } else # Install the binary that we compiled earlier. file=`$ECHO "$file$stripped_ext" | $SED "s%\([^/]*\)$%$objdir/\1%"` fi fi # remove .exe since cygwin /usr/bin/install will append another # one anyway case $install_prog,$host in */usr/bin/install*,*cygwin*) case $file:$destfile in *.exe:*.exe) # this is ok ;; *.exe:*) destfile=$destfile.exe ;; *:*.exe) func_stripname '' '.exe' "$destfile" destfile=$func_stripname_result ;; esac ;; esac func_show_eval "$install_prog\$stripme \$file \$destfile" 'exit $?' $opt_dry_run || if test -n "$outputname"; then ${RM}r "$tmpdir" fi ;; esac done for file in $staticlibs; do func_basename "$file" name="$func_basename_result" # Set up the ranlib parameters. oldlib="$destdir/$name" func_show_eval "$install_prog \$file \$oldlib" 'exit $?' if test -n "$stripme" && test -n "$old_striplib"; then func_show_eval "$old_striplib $oldlib" 'exit $?' fi # Do each command in the postinstall commands. func_execute_cmds "$old_postinstall_cmds" 'exit $?' done test -n "$future_libdirs" && \ func_warning "remember to run \`$progname --finish$future_libdirs'" if test -n "$current_libdirs"; then # Maybe just do a dry run. $opt_dry_run && current_libdirs=" -n$current_libdirs" exec_cmd='$SHELL $progpath $preserve_args --finish$current_libdirs' else exit $EXIT_SUCCESS fi } test "$opt_mode" = install && func_mode_install ${1+"$@"} # func_generate_dlsyms outputname originator pic_p # Extract symbols from dlprefiles and create ${outputname}S.o with # a dlpreopen symbol table. func_generate_dlsyms () { $opt_debug my_outputname="$1" my_originator="$2" my_pic_p="${3-no}" my_prefix=`$ECHO "$my_originator" | sed 's%[^a-zA-Z0-9]%_%g'` my_dlsyms= if test -n "$dlfiles$dlprefiles" || test "$dlself" != no; then if test -n "$NM" && test -n "$global_symbol_pipe"; then my_dlsyms="${my_outputname}S.c" else func_error "not configured to extract global symbols from dlpreopened files" fi fi if test -n "$my_dlsyms"; then case $my_dlsyms in "") ;; *.c) # Discover the nlist of each of the dlfiles. nlist="$output_objdir/${my_outputname}.nm" func_show_eval "$RM $nlist ${nlist}S ${nlist}T" # Parse the name list into a source file. func_verbose "creating $output_objdir/$my_dlsyms" $opt_dry_run || $ECHO > "$output_objdir/$my_dlsyms" "\ /* $my_dlsyms - symbol resolution table for \`$my_outputname' dlsym emulation. */ /* Generated by $PROGRAM (GNU $PACKAGE$TIMESTAMP) $VERSION */ #ifdef __cplusplus extern \"C\" { #endif #if defined(__GNUC__) && (((__GNUC__ == 4) && (__GNUC_MINOR__ >= 4)) || (__GNUC__ > 4)) #pragma GCC diagnostic ignored \"-Wstrict-prototypes\" #endif /* Keep this code in sync between libtool.m4, ltmain, lt_system.h, and tests. */ #if defined(_WIN32) || defined(__CYGWIN__) || defined(_WIN32_WCE) /* DATA imports from DLLs on WIN32 con't be const, because runtime relocations are performed -- see ld's documentation on pseudo-relocs. */ # define LT_DLSYM_CONST #elif defined(__osf__) /* This system does not cope well with relocations in const data. */ # define LT_DLSYM_CONST #else # define LT_DLSYM_CONST const #endif /* External symbol declarations for the compiler. */\ " if test "$dlself" = yes; then func_verbose "generating symbol list for \`$output'" $opt_dry_run || echo ': @PROGRAM@ ' > "$nlist" # Add our own program objects to the symbol list. progfiles=`$ECHO "$objs$old_deplibs" | $SP2NL | $SED "$lo2o" | $NL2SP` for progfile in $progfiles; do func_to_tool_file "$progfile" func_convert_file_msys_to_w32 func_verbose "extracting global C symbols from \`$func_to_tool_file_result'" $opt_dry_run || eval "$NM $func_to_tool_file_result | $global_symbol_pipe >> '$nlist'" done if test -n "$exclude_expsyms"; then $opt_dry_run || { eval '$EGREP -v " ($exclude_expsyms)$" "$nlist" > "$nlist"T' eval '$MV "$nlist"T "$nlist"' } fi if test -n "$export_symbols_regex"; then $opt_dry_run || { eval '$EGREP -e "$export_symbols_regex" "$nlist" > "$nlist"T' eval '$MV "$nlist"T "$nlist"' } fi # Prepare the list of exported symbols if test -z "$export_symbols"; then export_symbols="$output_objdir/$outputname.exp" $opt_dry_run || { $RM $export_symbols eval "${SED} -n -e '/^: @PROGRAM@ $/d' -e 's/^.* \(.*\)$/\1/p' "'< "$nlist" > "$export_symbols"' case $host in *cygwin* | *mingw* | *cegcc* ) eval "echo EXPORTS "'> "$output_objdir/$outputname.def"' eval 'cat "$export_symbols" >> "$output_objdir/$outputname.def"' ;; esac } else $opt_dry_run || { eval "${SED} -e 's/\([].[*^$]\)/\\\\\1/g' -e 's/^/ /' -e 's/$/$/'"' < "$export_symbols" > "$output_objdir/$outputname.exp"' eval '$GREP -f "$output_objdir/$outputname.exp" < "$nlist" > "$nlist"T' eval '$MV "$nlist"T "$nlist"' case $host in *cygwin* | *mingw* | *cegcc* ) eval "echo EXPORTS "'> "$output_objdir/$outputname.def"' eval 'cat "$nlist" >> "$output_objdir/$outputname.def"' ;; esac } fi fi for dlprefile in $dlprefiles; do func_verbose "extracting global C symbols from \`$dlprefile'" func_basename "$dlprefile" name="$func_basename_result" case $host in *cygwin* | *mingw* | *cegcc* ) # if an import library, we need to obtain dlname if func_win32_import_lib_p "$dlprefile"; then func_tr_sh "$dlprefile" eval "curr_lafile=\$libfile_$func_tr_sh_result" dlprefile_dlbasename="" if test -n "$curr_lafile" && func_lalib_p "$curr_lafile"; then # Use subshell, to avoid clobbering current variable values dlprefile_dlname=`source "$curr_lafile" && echo "$dlname"` if test -n "$dlprefile_dlname" ; then func_basename "$dlprefile_dlname" dlprefile_dlbasename="$func_basename_result" else # no lafile. user explicitly requested -dlpreopen . $sharedlib_from_linklib_cmd "$dlprefile" dlprefile_dlbasename=$sharedlib_from_linklib_result fi fi $opt_dry_run || { if test -n "$dlprefile_dlbasename" ; then eval '$ECHO ": $dlprefile_dlbasename" >> "$nlist"' else func_warning "Could not compute DLL name from $name" eval '$ECHO ": $name " >> "$nlist"' fi func_to_tool_file "$dlprefile" func_convert_file_msys_to_w32 eval "$NM \"$func_to_tool_file_result\" 2>/dev/null | $global_symbol_pipe | $SED -e '/I __imp/d' -e 's/I __nm_/D /;s/_nm__//' >> '$nlist'" } else # not an import lib $opt_dry_run || { eval '$ECHO ": $name " >> "$nlist"' func_to_tool_file "$dlprefile" func_convert_file_msys_to_w32 eval "$NM \"$func_to_tool_file_result\" 2>/dev/null | $global_symbol_pipe >> '$nlist'" } fi ;; *) $opt_dry_run || { eval '$ECHO ": $name " >> "$nlist"' func_to_tool_file "$dlprefile" func_convert_file_msys_to_w32 eval "$NM \"$func_to_tool_file_result\" 2>/dev/null | $global_symbol_pipe >> '$nlist'" } ;; esac done $opt_dry_run || { # Make sure we have at least an empty file. test -f "$nlist" || : > "$nlist" if test -n "$exclude_expsyms"; then $EGREP -v " ($exclude_expsyms)$" "$nlist" > "$nlist"T $MV "$nlist"T "$nlist" fi # Try sorting and uniquifying the output. if $GREP -v "^: " < "$nlist" | if sort -k 3 /dev/null 2>&1; then sort -k 3 else sort +2 fi | uniq > "$nlist"S; then : else $GREP -v "^: " < "$nlist" > "$nlist"S fi if test -f "$nlist"S; then eval "$global_symbol_to_cdecl"' < "$nlist"S >> "$output_objdir/$my_dlsyms"' else echo '/* NONE */' >> "$output_objdir/$my_dlsyms" fi echo >> "$output_objdir/$my_dlsyms" "\ /* The mapping between symbol names and symbols. */ typedef struct { const char *name; void *address; } lt_dlsymlist; extern LT_DLSYM_CONST lt_dlsymlist lt_${my_prefix}_LTX_preloaded_symbols[]; LT_DLSYM_CONST lt_dlsymlist lt_${my_prefix}_LTX_preloaded_symbols[] = {\ { \"$my_originator\", (void *) 0 }," case $need_lib_prefix in no) eval "$global_symbol_to_c_name_address" < "$nlist" >> "$output_objdir/$my_dlsyms" ;; *) eval "$global_symbol_to_c_name_address_lib_prefix" < "$nlist" >> "$output_objdir/$my_dlsyms" ;; esac echo >> "$output_objdir/$my_dlsyms" "\ {0, (void *) 0} }; /* This works around a problem in FreeBSD linker */ #ifdef FREEBSD_WORKAROUND static const void *lt_preloaded_setup() { return lt_${my_prefix}_LTX_preloaded_symbols; } #endif #ifdef __cplusplus } #endif\ " } # !$opt_dry_run pic_flag_for_symtable= case "$compile_command " in *" -static "*) ;; *) case $host in # compiling the symbol table file with pic_flag works around # a FreeBSD bug that causes programs to crash when -lm is # linked before any other PIC object. But we must not use # pic_flag when linking with -static. The problem exists in # FreeBSD 2.2.6 and is fixed in FreeBSD 3.1. *-*-freebsd2*|*-*-freebsd3.0*|*-*-freebsdelf3.0*) pic_flag_for_symtable=" $pic_flag -DFREEBSD_WORKAROUND" ;; *-*-hpux*) pic_flag_for_symtable=" $pic_flag" ;; *) if test "X$my_pic_p" != Xno; then pic_flag_for_symtable=" $pic_flag" fi ;; esac ;; esac symtab_cflags= for arg in $LTCFLAGS; do case $arg in -pie | -fpie | -fPIE) ;; *) func_append symtab_cflags " $arg" ;; esac done # Now compile the dynamic symbol file. func_show_eval '(cd $output_objdir && $LTCC$symtab_cflags -c$no_builtin_flag$pic_flag_for_symtable "$my_dlsyms")' 'exit $?' # Clean up the generated files. func_show_eval '$RM "$output_objdir/$my_dlsyms" "$nlist" "${nlist}S" "${nlist}T"' # Transform the symbol file into the correct name. symfileobj="$output_objdir/${my_outputname}S.$objext" case $host in *cygwin* | *mingw* | *cegcc* ) if test -f "$output_objdir/$my_outputname.def"; then compile_command=`$ECHO "$compile_command" | $SED "s%@SYMFILE@%$output_objdir/$my_outputname.def $symfileobj%"` finalize_command=`$ECHO "$finalize_command" | $SED "s%@SYMFILE@%$output_objdir/$my_outputname.def $symfileobj%"` else compile_command=`$ECHO "$compile_command" | $SED "s%@SYMFILE@%$symfileobj%"` finalize_command=`$ECHO "$finalize_command" | $SED "s%@SYMFILE@%$symfileobj%"` fi ;; *) compile_command=`$ECHO "$compile_command" | $SED "s%@SYMFILE@%$symfileobj%"` finalize_command=`$ECHO "$finalize_command" | $SED "s%@SYMFILE@%$symfileobj%"` ;; esac ;; *) func_fatal_error "unknown suffix for \`$my_dlsyms'" ;; esac else # We keep going just in case the user didn't refer to # lt_preloaded_symbols. The linker will fail if global_symbol_pipe # really was required. # Nullify the symbol file. compile_command=`$ECHO "$compile_command" | $SED "s% @SYMFILE@%%"` finalize_command=`$ECHO "$finalize_command" | $SED "s% @SYMFILE@%%"` fi } # func_win32_libid arg # return the library type of file 'arg' # # Need a lot of goo to handle *both* DLLs and import libs # Has to be a shell function in order to 'eat' the argument # that is supplied when $file_magic_command is called. # Despite the name, also deal with 64 bit binaries. func_win32_libid () { $opt_debug win32_libid_type="unknown" win32_fileres=`file -L $1 2>/dev/null` case $win32_fileres in *ar\ archive\ import\ library*) # definitely import win32_libid_type="x86 archive import" ;; *ar\ archive*) # could be an import, or static # Keep the egrep pattern in sync with the one in _LT_CHECK_MAGIC_METHOD. if eval $OBJDUMP -f $1 | $SED -e '10q' 2>/dev/null | $EGREP 'file format (pei*-i386(.*architecture: i386)?|pe-arm-wince|pe-x86-64)' >/dev/null; then func_to_tool_file "$1" func_convert_file_msys_to_w32 win32_nmres=`eval $NM -f posix -A \"$func_to_tool_file_result\" | $SED -n -e ' 1,100{ / I /{ s,.*,import, p q } }'` case $win32_nmres in import*) win32_libid_type="x86 archive import";; *) win32_libid_type="x86 archive static";; esac fi ;; *DLL*) win32_libid_type="x86 DLL" ;; *executable*) # but shell scripts are "executable" too... case $win32_fileres in *MS\ Windows\ PE\ Intel*) win32_libid_type="x86 DLL" ;; esac ;; esac $ECHO "$win32_libid_type" } # func_cygming_dll_for_implib ARG # # Platform-specific function to extract the # name of the DLL associated with the specified # import library ARG. # Invoked by eval'ing the libtool variable # $sharedlib_from_linklib_cmd # Result is available in the variable # $sharedlib_from_linklib_result func_cygming_dll_for_implib () { $opt_debug sharedlib_from_linklib_result=`$DLLTOOL --identify-strict --identify "$1"` } # func_cygming_dll_for_implib_fallback_core SECTION_NAME LIBNAMEs # # The is the core of a fallback implementation of a # platform-specific function to extract the name of the # DLL associated with the specified import library LIBNAME. # # SECTION_NAME is either .idata$6 or .idata$7, depending # on the platform and compiler that created the implib. # # Echos the name of the DLL associated with the # specified import library. func_cygming_dll_for_implib_fallback_core () { $opt_debug match_literal=`$ECHO "$1" | $SED "$sed_make_literal_regex"` $OBJDUMP -s --section "$1" "$2" 2>/dev/null | $SED '/^Contents of section '"$match_literal"':/{ # Place marker at beginning of archive member dllname section s/.*/====MARK====/ p d } # These lines can sometimes be longer than 43 characters, but # are always uninteresting /:[ ]*file format pe[i]\{,1\}-/d /^In archive [^:]*:/d # Ensure marker is printed /^====MARK====/p # Remove all lines with less than 43 characters /^.\{43\}/!d # From remaining lines, remove first 43 characters s/^.\{43\}//' | $SED -n ' # Join marker and all lines until next marker into a single line /^====MARK====/ b para H $ b para b :para x s/\n//g # Remove the marker s/^====MARK====// # Remove trailing dots and whitespace s/[\. \t]*$// # Print /./p' | # we now have a list, one entry per line, of the stringified # contents of the appropriate section of all members of the # archive which possess that section. Heuristic: eliminate # all those which have a first or second character that is # a '.' (that is, objdump's representation of an unprintable # character.) This should work for all archives with less than # 0x302f exports -- but will fail for DLLs whose name actually # begins with a literal '.' or a single character followed by # a '.'. # # Of those that remain, print the first one. $SED -e '/^\./d;/^.\./d;q' } # func_cygming_gnu_implib_p ARG # This predicate returns with zero status (TRUE) if # ARG is a GNU/binutils-style import library. Returns # with nonzero status (FALSE) otherwise. func_cygming_gnu_implib_p () { $opt_debug func_to_tool_file "$1" func_convert_file_msys_to_w32 func_cygming_gnu_implib_tmp=`$NM "$func_to_tool_file_result" | eval "$global_symbol_pipe" | $EGREP ' (_head_[A-Za-z0-9_]+_[ad]l*|[A-Za-z0-9_]+_[ad]l*_iname)$'` test -n "$func_cygming_gnu_implib_tmp" } # func_cygming_ms_implib_p ARG # This predicate returns with zero status (TRUE) if # ARG is an MS-style import library. Returns # with nonzero status (FALSE) otherwise. func_cygming_ms_implib_p () { $opt_debug func_to_tool_file "$1" func_convert_file_msys_to_w32 func_cygming_ms_implib_tmp=`$NM "$func_to_tool_file_result" | eval "$global_symbol_pipe" | $GREP '_NULL_IMPORT_DESCRIPTOR'` test -n "$func_cygming_ms_implib_tmp" } # func_cygming_dll_for_implib_fallback ARG # Platform-specific function to extract the # name of the DLL associated with the specified # import library ARG. # # This fallback implementation is for use when $DLLTOOL # does not support the --identify-strict option. # Invoked by eval'ing the libtool variable # $sharedlib_from_linklib_cmd # Result is available in the variable # $sharedlib_from_linklib_result func_cygming_dll_for_implib_fallback () { $opt_debug if func_cygming_gnu_implib_p "$1" ; then # binutils import library sharedlib_from_linklib_result=`func_cygming_dll_for_implib_fallback_core '.idata$7' "$1"` elif func_cygming_ms_implib_p "$1" ; then # ms-generated import library sharedlib_from_linklib_result=`func_cygming_dll_for_implib_fallback_core '.idata$6' "$1"` else # unknown sharedlib_from_linklib_result="" fi } # func_extract_an_archive dir oldlib func_extract_an_archive () { $opt_debug f_ex_an_ar_dir="$1"; shift f_ex_an_ar_oldlib="$1" if test "$lock_old_archive_extraction" = yes; then lockfile=$f_ex_an_ar_oldlib.lock until $opt_dry_run || ln "$progpath" "$lockfile" 2>/dev/null; do func_echo "Waiting for $lockfile to be removed" sleep 2 done fi func_show_eval "(cd \$f_ex_an_ar_dir && $AR x \"\$f_ex_an_ar_oldlib\")" \ 'stat=$?; rm -f "$lockfile"; exit $stat' if test "$lock_old_archive_extraction" = yes; then $opt_dry_run || rm -f "$lockfile" fi if ($AR t "$f_ex_an_ar_oldlib" | sort | sort -uc >/dev/null 2>&1); then : else func_fatal_error "object name conflicts in archive: $f_ex_an_ar_dir/$f_ex_an_ar_oldlib" fi } # func_extract_archives gentop oldlib ... func_extract_archives () { $opt_debug my_gentop="$1"; shift my_oldlibs=${1+"$@"} my_oldobjs="" my_xlib="" my_xabs="" my_xdir="" for my_xlib in $my_oldlibs; do # Extract the objects. case $my_xlib in [\\/]* | [A-Za-z]:[\\/]*) my_xabs="$my_xlib" ;; *) my_xabs=`pwd`"/$my_xlib" ;; esac func_basename "$my_xlib" my_xlib="$func_basename_result" my_xlib_u=$my_xlib while :; do case " $extracted_archives " in *" $my_xlib_u "*) func_arith $extracted_serial + 1 extracted_serial=$func_arith_result my_xlib_u=lt$extracted_serial-$my_xlib ;; *) break ;; esac done extracted_archives="$extracted_archives $my_xlib_u" my_xdir="$my_gentop/$my_xlib_u" func_mkdir_p "$my_xdir" case $host in *-darwin*) func_verbose "Extracting $my_xabs" # Do not bother doing anything if just a dry run $opt_dry_run || { darwin_orig_dir=`pwd` cd $my_xdir || exit $? darwin_archive=$my_xabs darwin_curdir=`pwd` darwin_base_archive=`basename "$darwin_archive"` darwin_arches=`$LIPO -info "$darwin_archive" 2>/dev/null | $GREP Architectures 2>/dev/null || true` if test -n "$darwin_arches"; then darwin_arches=`$ECHO "$darwin_arches" | $SED -e 's/.*are://'` darwin_arch= func_verbose "$darwin_base_archive has multiple architectures $darwin_arches" for darwin_arch in $darwin_arches ; do func_mkdir_p "unfat-$$/${darwin_base_archive}-${darwin_arch}" $LIPO -thin $darwin_arch -output "unfat-$$/${darwin_base_archive}-${darwin_arch}/${darwin_base_archive}" "${darwin_archive}" cd "unfat-$$/${darwin_base_archive}-${darwin_arch}" func_extract_an_archive "`pwd`" "${darwin_base_archive}" cd "$darwin_curdir" $RM "unfat-$$/${darwin_base_archive}-${darwin_arch}/${darwin_base_archive}" done # $darwin_arches ## Okay now we've a bunch of thin objects, gotta fatten them up :) darwin_filelist=`find unfat-$$ -type f -name \*.o -print -o -name \*.lo -print | $SED -e "$basename" | sort -u` darwin_file= darwin_files= for darwin_file in $darwin_filelist; do darwin_files=`find unfat-$$ -name $darwin_file -print | sort | $NL2SP` $LIPO -create -output "$darwin_file" $darwin_files done # $darwin_filelist $RM -rf unfat-$$ cd "$darwin_orig_dir" else cd $darwin_orig_dir func_extract_an_archive "$my_xdir" "$my_xabs" fi # $darwin_arches } # !$opt_dry_run ;; *) func_extract_an_archive "$my_xdir" "$my_xabs" ;; esac my_oldobjs="$my_oldobjs "`find $my_xdir -name \*.$objext -print -o -name \*.lo -print | sort | $NL2SP` done func_extract_archives_result="$my_oldobjs" } # func_emit_wrapper [arg=no] # # Emit a libtool wrapper script on stdout. # Don't directly open a file because we may want to # incorporate the script contents within a cygwin/mingw # wrapper executable. Must ONLY be called from within # func_mode_link because it depends on a number of variables # set therein. # # ARG is the value that the WRAPPER_SCRIPT_BELONGS_IN_OBJDIR # variable will take. If 'yes', then the emitted script # will assume that the directory in which it is stored is # the $objdir directory. This is a cygwin/mingw-specific # behavior. func_emit_wrapper () { func_emit_wrapper_arg1=${1-no} $ECHO "\ #! $SHELL # $output - temporary wrapper script for $objdir/$outputname # Generated by $PROGRAM (GNU $PACKAGE$TIMESTAMP) $VERSION # # The $output program cannot be directly executed until all the libtool # libraries that it depends on are installed. # # This wrapper script should never be moved out of the build directory. # If it is, it will not operate correctly. # Sed substitution that helps us do robust quoting. It backslashifies # metacharacters that are still active within double-quoted strings. sed_quote_subst='$sed_quote_subst' # Be Bourne compatible if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then emulate sh NULLCMD=: # Zsh 3.x and 4.x performs word splitting on \${1+\"\$@\"}, which # is contrary to our usage. Disable this feature. alias -g '\${1+\"\$@\"}'='\"\$@\"' setopt NO_GLOB_SUBST else case \`(set -o) 2>/dev/null\` in *posix*) set -o posix;; esac fi BIN_SH=xpg4; export BIN_SH # for Tru64 DUALCASE=1; export DUALCASE # for MKS sh # The HP-UX ksh and POSIX shell print the target directory to stdout # if CDPATH is set. (unset CDPATH) >/dev/null 2>&1 && unset CDPATH relink_command=\"$relink_command\" # This environment variable determines our operation mode. if test \"\$libtool_install_magic\" = \"$magic\"; then # install mode needs the following variables: generated_by_libtool_version='$macro_version' notinst_deplibs='$notinst_deplibs' else # When we are sourced in execute mode, \$file and \$ECHO are already set. if test \"\$libtool_execute_magic\" != \"$magic\"; then file=\"\$0\"" qECHO=`$ECHO "$ECHO" | $SED "$sed_quote_subst"` $ECHO "\ # A function that is used when there is no print builtin or printf. func_fallback_echo () { eval 'cat <<_LTECHO_EOF \$1 _LTECHO_EOF' } ECHO=\"$qECHO\" fi # Very basic option parsing. These options are (a) specific to # the libtool wrapper, (b) are identical between the wrapper # /script/ and the wrapper /executable/ which is used only on # windows platforms, and (c) all begin with the string "--lt-" # (application programs are unlikely to have options which match # this pattern). # # There are only two supported options: --lt-debug and # --lt-dump-script. There is, deliberately, no --lt-help. # # The first argument to this parsing function should be the # script's $0 value, followed by "$@". lt_option_debug= func_parse_lt_options () { lt_script_arg0=\$0 shift for lt_opt do case \"\$lt_opt\" in --lt-debug) lt_option_debug=1 ;; --lt-dump-script) lt_dump_D=\`\$ECHO \"X\$lt_script_arg0\" | $SED -e 's/^X//' -e 's%/[^/]*$%%'\` test \"X\$lt_dump_D\" = \"X\$lt_script_arg0\" && lt_dump_D=. lt_dump_F=\`\$ECHO \"X\$lt_script_arg0\" | $SED -e 's/^X//' -e 's%^.*/%%'\` cat \"\$lt_dump_D/\$lt_dump_F\" exit 0 ;; --lt-*) \$ECHO \"Unrecognized --lt- option: '\$lt_opt'\" 1>&2 exit 1 ;; esac done # Print the debug banner immediately: if test -n \"\$lt_option_debug\"; then echo \"${outputname}:${output}:\${LINENO}: libtool wrapper (GNU $PACKAGE$TIMESTAMP) $VERSION\" 1>&2 fi } # Used when --lt-debug. Prints its arguments to stdout # (redirection is the responsibility of the caller) func_lt_dump_args () { lt_dump_args_N=1; for lt_arg do \$ECHO \"${outputname}:${output}:\${LINENO}: newargv[\$lt_dump_args_N]: \$lt_arg\" lt_dump_args_N=\`expr \$lt_dump_args_N + 1\` done } # Core function for launching the target application func_exec_program_core () { " case $host in # Backslashes separate directories on plain windows *-*-mingw | *-*-os2* | *-cegcc*) $ECHO "\ if test -n \"\$lt_option_debug\"; then \$ECHO \"${outputname}:${output}:\${LINENO}: newargv[0]: \$progdir\\\\\$program\" 1>&2 func_lt_dump_args \${1+\"\$@\"} 1>&2 fi exec \"\$progdir\\\\\$program\" \${1+\"\$@\"} " ;; *) $ECHO "\ if test -n \"\$lt_option_debug\"; then \$ECHO \"${outputname}:${output}:\${LINENO}: newargv[0]: \$progdir/\$program\" 1>&2 func_lt_dump_args \${1+\"\$@\"} 1>&2 fi exec \"\$progdir/\$program\" \${1+\"\$@\"} " ;; esac $ECHO "\ \$ECHO \"\$0: cannot exec \$program \$*\" 1>&2 exit 1 } # A function to encapsulate launching the target application # Strips options in the --lt-* namespace from \$@ and # launches target application with the remaining arguments. func_exec_program () { for lt_wr_arg do case \$lt_wr_arg in --lt-*) ;; *) set x \"\$@\" \"\$lt_wr_arg\"; shift;; esac shift done func_exec_program_core \${1+\"\$@\"} } # Parse options func_parse_lt_options \"\$0\" \${1+\"\$@\"} # Find the directory that this script lives in. thisdir=\`\$ECHO \"\$file\" | $SED 's%/[^/]*$%%'\` test \"x\$thisdir\" = \"x\$file\" && thisdir=. # Follow symbolic links until we get to the real thisdir. file=\`ls -ld \"\$file\" | $SED -n 's/.*-> //p'\` while test -n \"\$file\"; do destdir=\`\$ECHO \"\$file\" | $SED 's%/[^/]*\$%%'\` # If there was a directory component, then change thisdir. if test \"x\$destdir\" != \"x\$file\"; then case \"\$destdir\" in [\\\\/]* | [A-Za-z]:[\\\\/]*) thisdir=\"\$destdir\" ;; *) thisdir=\"\$thisdir/\$destdir\" ;; esac fi file=\`\$ECHO \"\$file\" | $SED 's%^.*/%%'\` file=\`ls -ld \"\$thisdir/\$file\" | $SED -n 's/.*-> //p'\` done # Usually 'no', except on cygwin/mingw when embedded into # the cwrapper. WRAPPER_SCRIPT_BELONGS_IN_OBJDIR=$func_emit_wrapper_arg1 if test \"\$WRAPPER_SCRIPT_BELONGS_IN_OBJDIR\" = \"yes\"; then # special case for '.' if test \"\$thisdir\" = \".\"; then thisdir=\`pwd\` fi # remove .libs from thisdir case \"\$thisdir\" in *[\\\\/]$objdir ) thisdir=\`\$ECHO \"\$thisdir\" | $SED 's%[\\\\/][^\\\\/]*$%%'\` ;; $objdir ) thisdir=. ;; esac fi # Try to get the absolute directory name. absdir=\`cd \"\$thisdir\" && pwd\` test -n \"\$absdir\" && thisdir=\"\$absdir\" " if test "$fast_install" = yes; then $ECHO "\ program=lt-'$outputname'$exeext progdir=\"\$thisdir/$objdir\" if test ! -f \"\$progdir/\$program\" || { file=\`ls -1dt \"\$progdir/\$program\" \"\$progdir/../\$program\" 2>/dev/null | ${SED} 1q\`; \\ test \"X\$file\" != \"X\$progdir/\$program\"; }; then file=\"\$\$-\$program\" if test ! -d \"\$progdir\"; then $MKDIR \"\$progdir\" else $RM \"\$progdir/\$file\" fi" $ECHO "\ # relink executable if necessary if test -n \"\$relink_command\"; then if relink_command_output=\`eval \$relink_command 2>&1\`; then : else $ECHO \"\$relink_command_output\" >&2 $RM \"\$progdir/\$file\" exit 1 fi fi $MV \"\$progdir/\$file\" \"\$progdir/\$program\" 2>/dev/null || { $RM \"\$progdir/\$program\"; $MV \"\$progdir/\$file\" \"\$progdir/\$program\"; } $RM \"\$progdir/\$file\" fi" else $ECHO "\ program='$outputname' progdir=\"\$thisdir/$objdir\" " fi $ECHO "\ if test -f \"\$progdir/\$program\"; then" # fixup the dll searchpath if we need to. # # Fix the DLL searchpath if we need to. Do this before prepending # to shlibpath, because on Windows, both are PATH and uninstalled # libraries must come first. if test -n "$dllsearchpath"; then $ECHO "\ # Add the dll search path components to the executable PATH PATH=$dllsearchpath:\$PATH " fi # Export our shlibpath_var if we have one. if test "$shlibpath_overrides_runpath" = yes && test -n "$shlibpath_var" && test -n "$temp_rpath"; then $ECHO "\ # Add our own library path to $shlibpath_var $shlibpath_var=\"$temp_rpath\$$shlibpath_var\" # Some systems cannot cope with colon-terminated $shlibpath_var # The second colon is a workaround for a bug in BeOS R4 sed $shlibpath_var=\`\$ECHO \"\$$shlibpath_var\" | $SED 's/::*\$//'\` export $shlibpath_var " fi $ECHO "\ if test \"\$libtool_execute_magic\" != \"$magic\"; then # Run the actual program with our arguments. func_exec_program \${1+\"\$@\"} fi else # The program doesn't exist. \$ECHO \"\$0: error: \\\`\$progdir/\$program' does not exist\" 1>&2 \$ECHO \"This script is just a wrapper for \$program.\" 1>&2 \$ECHO \"See the $PACKAGE documentation for more information.\" 1>&2 exit 1 fi fi\ " } # func_emit_cwrapperexe_src # emit the source code for a wrapper executable on stdout # Must ONLY be called from within func_mode_link because # it depends on a number of variable set therein. func_emit_cwrapperexe_src () { cat < #include #ifdef _MSC_VER # include # include # include #else # include # include # ifdef __CYGWIN__ # include # endif #endif #include #include #include #include #include #include #include #include /* declarations of non-ANSI functions */ #if defined(__MINGW32__) # ifdef __STRICT_ANSI__ int _putenv (const char *); # endif #elif defined(__CYGWIN__) # ifdef __STRICT_ANSI__ char *realpath (const char *, char *); int putenv (char *); int setenv (const char *, const char *, int); # endif /* #elif defined (other platforms) ... */ #endif /* portability defines, excluding path handling macros */ #if defined(_MSC_VER) # define setmode _setmode # define stat _stat # define chmod _chmod # define getcwd _getcwd # define putenv _putenv # define S_IXUSR _S_IEXEC # ifndef _INTPTR_T_DEFINED # define _INTPTR_T_DEFINED # define intptr_t int # endif #elif defined(__MINGW32__) # define setmode _setmode # define stat _stat # define chmod _chmod # define getcwd _getcwd # define putenv _putenv #elif defined(__CYGWIN__) # define HAVE_SETENV # define FOPEN_WB "wb" /* #elif defined (other platforms) ... */ #endif #if defined(PATH_MAX) # define LT_PATHMAX PATH_MAX #elif defined(MAXPATHLEN) # define LT_PATHMAX MAXPATHLEN #else # define LT_PATHMAX 1024 #endif #ifndef S_IXOTH # define S_IXOTH 0 #endif #ifndef S_IXGRP # define S_IXGRP 0 #endif /* path handling portability macros */ #ifndef DIR_SEPARATOR # define DIR_SEPARATOR '/' # define PATH_SEPARATOR ':' #endif #if defined (_WIN32) || defined (__MSDOS__) || defined (__DJGPP__) || \ defined (__OS2__) # define HAVE_DOS_BASED_FILE_SYSTEM # define FOPEN_WB "wb" # ifndef DIR_SEPARATOR_2 # define DIR_SEPARATOR_2 '\\' # endif # ifndef PATH_SEPARATOR_2 # define PATH_SEPARATOR_2 ';' # endif #endif #ifndef DIR_SEPARATOR_2 # define IS_DIR_SEPARATOR(ch) ((ch) == DIR_SEPARATOR) #else /* DIR_SEPARATOR_2 */ # define IS_DIR_SEPARATOR(ch) \ (((ch) == DIR_SEPARATOR) || ((ch) == DIR_SEPARATOR_2)) #endif /* DIR_SEPARATOR_2 */ #ifndef PATH_SEPARATOR_2 # define IS_PATH_SEPARATOR(ch) ((ch) == PATH_SEPARATOR) #else /* PATH_SEPARATOR_2 */ # define IS_PATH_SEPARATOR(ch) ((ch) == PATH_SEPARATOR_2) #endif /* PATH_SEPARATOR_2 */ #ifndef FOPEN_WB # define FOPEN_WB "w" #endif #ifndef _O_BINARY # define _O_BINARY 0 #endif #define XMALLOC(type, num) ((type *) xmalloc ((num) * sizeof(type))) #define XFREE(stale) do { \ if (stale) { free ((void *) stale); stale = 0; } \ } while (0) #if defined(LT_DEBUGWRAPPER) static int lt_debug = 1; #else static int lt_debug = 0; #endif const char *program_name = "libtool-wrapper"; /* in case xstrdup fails */ void *xmalloc (size_t num); char *xstrdup (const char *string); const char *base_name (const char *name); char *find_executable (const char *wrapper); char *chase_symlinks (const char *pathspec); int make_executable (const char *path); int check_executable (const char *path); char *strendzap (char *str, const char *pat); void lt_debugprintf (const char *file, int line, const char *fmt, ...); void lt_fatal (const char *file, int line, const char *message, ...); static const char *nonnull (const char *s); static const char *nonempty (const char *s); void lt_setenv (const char *name, const char *value); char *lt_extend_str (const char *orig_value, const char *add, int to_end); void lt_update_exe_path (const char *name, const char *value); void lt_update_lib_path (const char *name, const char *value); char **prepare_spawn (char **argv); void lt_dump_script (FILE *f); EOF cat <= 0) && (st.st_mode & (S_IXUSR | S_IXGRP | S_IXOTH))) return 1; else return 0; } int make_executable (const char *path) { int rval = 0; struct stat st; lt_debugprintf (__FILE__, __LINE__, "(make_executable): %s\n", nonempty (path)); if ((!path) || (!*path)) return 0; if (stat (path, &st) >= 0) { rval = chmod (path, st.st_mode | S_IXOTH | S_IXGRP | S_IXUSR); } return rval; } /* Searches for the full path of the wrapper. Returns newly allocated full path name if found, NULL otherwise Does not chase symlinks, even on platforms that support them. */ char * find_executable (const char *wrapper) { int has_slash = 0; const char *p; const char *p_next; /* static buffer for getcwd */ char tmp[LT_PATHMAX + 1]; int tmp_len; char *concat_name; lt_debugprintf (__FILE__, __LINE__, "(find_executable): %s\n", nonempty (wrapper)); if ((wrapper == NULL) || (*wrapper == '\0')) return NULL; /* Absolute path? */ #if defined (HAVE_DOS_BASED_FILE_SYSTEM) if (isalpha ((unsigned char) wrapper[0]) && wrapper[1] == ':') { concat_name = xstrdup (wrapper); if (check_executable (concat_name)) return concat_name; XFREE (concat_name); } else { #endif if (IS_DIR_SEPARATOR (wrapper[0])) { concat_name = xstrdup (wrapper); if (check_executable (concat_name)) return concat_name; XFREE (concat_name); } #if defined (HAVE_DOS_BASED_FILE_SYSTEM) } #endif for (p = wrapper; *p; p++) if (*p == '/') { has_slash = 1; break; } if (!has_slash) { /* no slashes; search PATH */ const char *path = getenv ("PATH"); if (path != NULL) { for (p = path; *p; p = p_next) { const char *q; size_t p_len; for (q = p; *q; q++) if (IS_PATH_SEPARATOR (*q)) break; p_len = q - p; p_next = (*q == '\0' ? q : q + 1); if (p_len == 0) { /* empty path: current directory */ if (getcwd (tmp, LT_PATHMAX) == NULL) lt_fatal (__FILE__, __LINE__, "getcwd failed: %s", nonnull (strerror (errno))); tmp_len = strlen (tmp); concat_name = XMALLOC (char, tmp_len + 1 + strlen (wrapper) + 1); memcpy (concat_name, tmp, tmp_len); concat_name[tmp_len] = '/'; strcpy (concat_name + tmp_len + 1, wrapper); } else { concat_name = XMALLOC (char, p_len + 1 + strlen (wrapper) + 1); memcpy (concat_name, p, p_len); concat_name[p_len] = '/'; strcpy (concat_name + p_len + 1, wrapper); } if (check_executable (concat_name)) return concat_name; XFREE (concat_name); } } /* not found in PATH; assume curdir */ } /* Relative path | not found in path: prepend cwd */ if (getcwd (tmp, LT_PATHMAX) == NULL) lt_fatal (__FILE__, __LINE__, "getcwd failed: %s", nonnull (strerror (errno))); tmp_len = strlen (tmp); concat_name = XMALLOC (char, tmp_len + 1 + strlen (wrapper) + 1); memcpy (concat_name, tmp, tmp_len); concat_name[tmp_len] = '/'; strcpy (concat_name + tmp_len + 1, wrapper); if (check_executable (concat_name)) return concat_name; XFREE (concat_name); return NULL; } char * chase_symlinks (const char *pathspec) { #ifndef S_ISLNK return xstrdup (pathspec); #else char buf[LT_PATHMAX]; struct stat s; char *tmp_pathspec = xstrdup (pathspec); char *p; int has_symlinks = 0; while (strlen (tmp_pathspec) && !has_symlinks) { lt_debugprintf (__FILE__, __LINE__, "checking path component for symlinks: %s\n", tmp_pathspec); if (lstat (tmp_pathspec, &s) == 0) { if (S_ISLNK (s.st_mode) != 0) { has_symlinks = 1; break; } /* search backwards for last DIR_SEPARATOR */ p = tmp_pathspec + strlen (tmp_pathspec) - 1; while ((p > tmp_pathspec) && (!IS_DIR_SEPARATOR (*p))) p--; if ((p == tmp_pathspec) && (!IS_DIR_SEPARATOR (*p))) { /* no more DIR_SEPARATORS left */ break; } *p = '\0'; } else { lt_fatal (__FILE__, __LINE__, "error accessing file \"%s\": %s", tmp_pathspec, nonnull (strerror (errno))); } } XFREE (tmp_pathspec); if (!has_symlinks) { return xstrdup (pathspec); } tmp_pathspec = realpath (pathspec, buf); if (tmp_pathspec == 0) { lt_fatal (__FILE__, __LINE__, "could not follow symlinks for %s", pathspec); } return xstrdup (tmp_pathspec); #endif } char * strendzap (char *str, const char *pat) { size_t len, patlen; assert (str != NULL); assert (pat != NULL); len = strlen (str); patlen = strlen (pat); if (patlen <= len) { str += len - patlen; if (strcmp (str, pat) == 0) *str = '\0'; } return str; } void lt_debugprintf (const char *file, int line, const char *fmt, ...) { va_list args; if (lt_debug) { (void) fprintf (stderr, "%s:%s:%d: ", program_name, file, line); va_start (args, fmt); (void) vfprintf (stderr, fmt, args); va_end (args); } } static void lt_error_core (int exit_status, const char *file, int line, const char *mode, const char *message, va_list ap) { fprintf (stderr, "%s:%s:%d: %s: ", program_name, file, line, mode); vfprintf (stderr, message, ap); fprintf (stderr, ".\n"); if (exit_status >= 0) exit (exit_status); } void lt_fatal (const char *file, int line, const char *message, ...) { va_list ap; va_start (ap, message); lt_error_core (EXIT_FAILURE, file, line, "FATAL", message, ap); va_end (ap); } static const char * nonnull (const char *s) { return s ? s : "(null)"; } static const char * nonempty (const char *s) { return (s && !*s) ? "(empty)" : nonnull (s); } void lt_setenv (const char *name, const char *value) { lt_debugprintf (__FILE__, __LINE__, "(lt_setenv) setting '%s' to '%s'\n", nonnull (name), nonnull (value)); { #ifdef HAVE_SETENV /* always make a copy, for consistency with !HAVE_SETENV */ char *str = xstrdup (value); setenv (name, str, 1); #else int len = strlen (name) + 1 + strlen (value) + 1; char *str = XMALLOC (char, len); sprintf (str, "%s=%s", name, value); if (putenv (str) != EXIT_SUCCESS) { XFREE (str); } #endif } } char * lt_extend_str (const char *orig_value, const char *add, int to_end) { char *new_value; if (orig_value && *orig_value) { int orig_value_len = strlen (orig_value); int add_len = strlen (add); new_value = XMALLOC (char, add_len + orig_value_len + 1); if (to_end) { strcpy (new_value, orig_value); strcpy (new_value + orig_value_len, add); } else { strcpy (new_value, add); strcpy (new_value + add_len, orig_value); } } else { new_value = xstrdup (add); } return new_value; } void lt_update_exe_path (const char *name, const char *value) { lt_debugprintf (__FILE__, __LINE__, "(lt_update_exe_path) modifying '%s' by prepending '%s'\n", nonnull (name), nonnull (value)); if (name && *name && value && *value) { char *new_value = lt_extend_str (getenv (name), value, 0); /* some systems can't cope with a ':'-terminated path #' */ int len = strlen (new_value); while (((len = strlen (new_value)) > 0) && IS_PATH_SEPARATOR (new_value[len-1])) { new_value[len-1] = '\0'; } lt_setenv (name, new_value); XFREE (new_value); } } void lt_update_lib_path (const char *name, const char *value) { lt_debugprintf (__FILE__, __LINE__, "(lt_update_lib_path) modifying '%s' by prepending '%s'\n", nonnull (name), nonnull (value)); if (name && *name && value && *value) { char *new_value = lt_extend_str (getenv (name), value, 0); lt_setenv (name, new_value); XFREE (new_value); } } EOF case $host_os in mingw*) cat <<"EOF" /* Prepares an argument vector before calling spawn(). Note that spawn() does not by itself call the command interpreter (getenv ("COMSPEC") != NULL ? getenv ("COMSPEC") : ({ OSVERSIONINFO v; v.dwOSVersionInfoSize = sizeof(OSVERSIONINFO); GetVersionEx(&v); v.dwPlatformId == VER_PLATFORM_WIN32_NT; }) ? "cmd.exe" : "command.com"). Instead it simply concatenates the arguments, separated by ' ', and calls CreateProcess(). We must quote the arguments since Win32 CreateProcess() interprets characters like ' ', '\t', '\\', '"' (but not '<' and '>') in a special way: - Space and tab are interpreted as delimiters. They are not treated as delimiters if they are surrounded by double quotes: "...". - Unescaped double quotes are removed from the input. Their only effect is that within double quotes, space and tab are treated like normal characters. - Backslashes not followed by double quotes are not special. - But 2*n+1 backslashes followed by a double quote become n backslashes followed by a double quote (n >= 0): \" -> " \\\" -> \" \\\\\" -> \\" */ #define SHELL_SPECIAL_CHARS "\"\\ \001\002\003\004\005\006\007\010\011\012\013\014\015\016\017\020\021\022\023\024\025\026\027\030\031\032\033\034\035\036\037" #define SHELL_SPACE_CHARS " \001\002\003\004\005\006\007\010\011\012\013\014\015\016\017\020\021\022\023\024\025\026\027\030\031\032\033\034\035\036\037" char ** prepare_spawn (char **argv) { size_t argc; char **new_argv; size_t i; /* Count number of arguments. */ for (argc = 0; argv[argc] != NULL; argc++) ; /* Allocate new argument vector. */ new_argv = XMALLOC (char *, argc + 1); /* Put quoted arguments into the new argument vector. */ for (i = 0; i < argc; i++) { const char *string = argv[i]; if (string[0] == '\0') new_argv[i] = xstrdup ("\"\""); else if (strpbrk (string, SHELL_SPECIAL_CHARS) != NULL) { int quote_around = (strpbrk (string, SHELL_SPACE_CHARS) != NULL); size_t length; unsigned int backslashes; const char *s; char *quoted_string; char *p; length = 0; backslashes = 0; if (quote_around) length++; for (s = string; *s != '\0'; s++) { char c = *s; if (c == '"') length += backslashes + 1; length++; if (c == '\\') backslashes++; else backslashes = 0; } if (quote_around) length += backslashes + 1; quoted_string = XMALLOC (char, length + 1); p = quoted_string; backslashes = 0; if (quote_around) *p++ = '"'; for (s = string; *s != '\0'; s++) { char c = *s; if (c == '"') { unsigned int j; for (j = backslashes + 1; j > 0; j--) *p++ = '\\'; } *p++ = c; if (c == '\\') backslashes++; else backslashes = 0; } if (quote_around) { unsigned int j; for (j = backslashes; j > 0; j--) *p++ = '\\'; *p++ = '"'; } *p = '\0'; new_argv[i] = quoted_string; } else new_argv[i] = (char *) string; } new_argv[argc] = NULL; return new_argv; } EOF ;; esac cat <<"EOF" void lt_dump_script (FILE* f) { EOF func_emit_wrapper yes | $SED -e 's/\([\\"]\)/\\\1/g' \ -e 's/^/ fputs ("/' -e 's/$/\\n", f);/' cat <<"EOF" } EOF } # end: func_emit_cwrapperexe_src # func_win32_import_lib_p ARG # True if ARG is an import lib, as indicated by $file_magic_cmd func_win32_import_lib_p () { $opt_debug case `eval $file_magic_cmd \"\$1\" 2>/dev/null | $SED -e 10q` in *import*) : ;; *) false ;; esac } # func_mode_link arg... func_mode_link () { $opt_debug case $host in *-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-os2* | *-cegcc*) # It is impossible to link a dll without this setting, and # we shouldn't force the makefile maintainer to figure out # which system we are compiling for in order to pass an extra # flag for every libtool invocation. # allow_undefined=no # FIXME: Unfortunately, there are problems with the above when trying # to make a dll which has undefined symbols, in which case not # even a static library is built. For now, we need to specify # -no-undefined on the libtool link line when we can be certain # that all symbols are satisfied, otherwise we get a static library. allow_undefined=yes ;; *) allow_undefined=yes ;; esac libtool_args=$nonopt base_compile="$nonopt $@" compile_command=$nonopt finalize_command=$nonopt compile_rpath= finalize_rpath= compile_shlibpath= finalize_shlibpath= convenience= old_convenience= deplibs= old_deplibs= compiler_flags= linker_flags= dllsearchpath= lib_search_path=`pwd` inst_prefix_dir= new_inherited_linker_flags= avoid_version=no bindir= dlfiles= dlprefiles= dlself=no export_dynamic=no export_symbols= export_symbols_regex= generated= libobjs= ltlibs= module=no no_install=no objs= non_pic_objects= precious_files_regex= prefer_static_libs=no preload=no prev= prevarg= release= rpath= xrpath= perm_rpath= temp_rpath= thread_safe=no vinfo= vinfo_number=no weak_libs= single_module="${wl}-single_module" func_infer_tag $base_compile # We need to know -static, to get the right output filenames. for arg do case $arg in -shared) test "$build_libtool_libs" != yes && \ func_fatal_configuration "can not build a shared library" build_old_libs=no break ;; -all-static | -static | -static-libtool-libs) case $arg in -all-static) if test "$build_libtool_libs" = yes && test -z "$link_static_flag"; then func_warning "complete static linking is impossible in this configuration" fi if test -n "$link_static_flag"; then dlopen_self=$dlopen_self_static fi prefer_static_libs=yes ;; -static) if test -z "$pic_flag" && test -n "$link_static_flag"; then dlopen_self=$dlopen_self_static fi prefer_static_libs=built ;; -static-libtool-libs) if test -z "$pic_flag" && test -n "$link_static_flag"; then dlopen_self=$dlopen_self_static fi prefer_static_libs=yes ;; esac build_libtool_libs=no build_old_libs=yes break ;; esac done # See if our shared archives depend on static archives. test -n "$old_archive_from_new_cmds" && build_old_libs=yes # Go through the arguments, transforming them on the way. while test "$#" -gt 0; do arg="$1" shift func_quote_for_eval "$arg" qarg=$func_quote_for_eval_unquoted_result func_append libtool_args " $func_quote_for_eval_result" # If the previous option needs an argument, assign it. if test -n "$prev"; then case $prev in output) func_append compile_command " @OUTPUT@" func_append finalize_command " @OUTPUT@" ;; esac case $prev in bindir) bindir="$arg" prev= continue ;; dlfiles|dlprefiles) if test "$preload" = no; then # Add the symbol object into the linking commands. func_append compile_command " @SYMFILE@" func_append finalize_command " @SYMFILE@" preload=yes fi case $arg in *.la | *.lo) ;; # We handle these cases below. force) if test "$dlself" = no; then dlself=needless export_dynamic=yes fi prev= continue ;; self) if test "$prev" = dlprefiles; then dlself=yes elif test "$prev" = dlfiles && test "$dlopen_self" != yes; then dlself=yes else dlself=needless export_dynamic=yes fi prev= continue ;; *) if test "$prev" = dlfiles; then func_append dlfiles " $arg" else func_append dlprefiles " $arg" fi prev= continue ;; esac ;; expsyms) export_symbols="$arg" test -f "$arg" \ || func_fatal_error "symbol file \`$arg' does not exist" prev= continue ;; expsyms_regex) export_symbols_regex="$arg" prev= continue ;; framework) case $host in *-*-darwin*) case "$deplibs " in *" $qarg.ltframework "*) ;; *) func_append deplibs " $qarg.ltframework" # this is fixed later ;; esac ;; esac prev= continue ;; inst_prefix) inst_prefix_dir="$arg" prev= continue ;; objectlist) if test -f "$arg"; then save_arg=$arg moreargs= for fil in `cat "$save_arg"` do # func_append moreargs " $fil" arg=$fil # A libtool-controlled object. # Check to see that this really is a libtool object. if func_lalib_unsafe_p "$arg"; then pic_object= non_pic_object= # Read the .lo file func_source "$arg" if test -z "$pic_object" || test -z "$non_pic_object" || test "$pic_object" = none && test "$non_pic_object" = none; then func_fatal_error "cannot find name of object for \`$arg'" fi # Extract subdirectory from the argument. func_dirname "$arg" "/" "" xdir="$func_dirname_result" if test "$pic_object" != none; then # Prepend the subdirectory the object is found in. pic_object="$xdir$pic_object" if test "$prev" = dlfiles; then if test "$build_libtool_libs" = yes && test "$dlopen_support" = yes; then func_append dlfiles " $pic_object" prev= continue else # If libtool objects are unsupported, then we need to preload. prev=dlprefiles fi fi # CHECK ME: I think I busted this. -Ossama if test "$prev" = dlprefiles; then # Preload the old-style object. func_append dlprefiles " $pic_object" prev= fi # A PIC object. func_append libobjs " $pic_object" arg="$pic_object" fi # Non-PIC object. if test "$non_pic_object" != none; then # Prepend the subdirectory the object is found in. non_pic_object="$xdir$non_pic_object" # A standard non-PIC object func_append non_pic_objects " $non_pic_object" if test -z "$pic_object" || test "$pic_object" = none ; then arg="$non_pic_object" fi else # If the PIC object exists, use it instead. # $xdir was prepended to $pic_object above. non_pic_object="$pic_object" func_append non_pic_objects " $non_pic_object" fi else # Only an error if not doing a dry-run. if $opt_dry_run; then # Extract subdirectory from the argument. func_dirname "$arg" "/" "" xdir="$func_dirname_result" func_lo2o "$arg" pic_object=$xdir$objdir/$func_lo2o_result non_pic_object=$xdir$func_lo2o_result func_append libobjs " $pic_object" func_append non_pic_objects " $non_pic_object" else func_fatal_error "\`$arg' is not a valid libtool object" fi fi done else func_fatal_error "link input file \`$arg' does not exist" fi arg=$save_arg prev= continue ;; precious_regex) precious_files_regex="$arg" prev= continue ;; release) release="-$arg" prev= continue ;; rpath | xrpath) # We need an absolute path. case $arg in [\\/]* | [A-Za-z]:[\\/]*) ;; *) func_fatal_error "only absolute run-paths are allowed" ;; esac if test "$prev" = rpath; then case "$rpath " in *" $arg "*) ;; *) func_append rpath " $arg" ;; esac else case "$xrpath " in *" $arg "*) ;; *) func_append xrpath " $arg" ;; esac fi prev= continue ;; shrext) shrext_cmds="$arg" prev= continue ;; weak) func_append weak_libs " $arg" prev= continue ;; xcclinker) func_append linker_flags " $qarg" func_append compiler_flags " $qarg" prev= func_append compile_command " $qarg" func_append finalize_command " $qarg" continue ;; xcompiler) func_append compiler_flags " $qarg" prev= func_append compile_command " $qarg" func_append finalize_command " $qarg" continue ;; xlinker) func_append linker_flags " $qarg" func_append compiler_flags " $wl$qarg" prev= func_append compile_command " $wl$qarg" func_append finalize_command " $wl$qarg" continue ;; *) eval "$prev=\"\$arg\"" prev= continue ;; esac fi # test -n "$prev" prevarg="$arg" case $arg in -all-static) if test -n "$link_static_flag"; then # See comment for -static flag below, for more details. func_append compile_command " $link_static_flag" func_append finalize_command " $link_static_flag" fi continue ;; -allow-undefined) # FIXME: remove this flag sometime in the future. func_fatal_error "\`-allow-undefined' must not be used because it is the default" ;; -avoid-version) avoid_version=yes continue ;; -bindir) prev=bindir continue ;; -dlopen) prev=dlfiles continue ;; -dlpreopen) prev=dlprefiles continue ;; -export-dynamic) export_dynamic=yes continue ;; -export-symbols | -export-symbols-regex) if test -n "$export_symbols" || test -n "$export_symbols_regex"; then func_fatal_error "more than one -exported-symbols argument is not allowed" fi if test "X$arg" = "X-export-symbols"; then prev=expsyms else prev=expsyms_regex fi continue ;; -framework) prev=framework continue ;; -inst-prefix-dir) prev=inst_prefix continue ;; # The native IRIX linker understands -LANG:*, -LIST:* and -LNO:* # so, if we see these flags be careful not to treat them like -L -L[A-Z][A-Z]*:*) case $with_gcc/$host in no/*-*-irix* | /*-*-irix*) func_append compile_command " $arg" func_append finalize_command " $arg" ;; esac continue ;; -L*) func_stripname "-L" '' "$arg" if test -z "$func_stripname_result"; then if test "$#" -gt 0; then func_fatal_error "require no space between \`-L' and \`$1'" else func_fatal_error "need path for \`-L' option" fi fi func_resolve_sysroot "$func_stripname_result" dir=$func_resolve_sysroot_result # We need an absolute path. case $dir in [\\/]* | [A-Za-z]:[\\/]*) ;; *) absdir=`cd "$dir" && pwd` test -z "$absdir" && \ func_fatal_error "cannot determine absolute directory name of \`$dir'" dir="$absdir" ;; esac case "$deplibs " in *" -L$dir "* | *" $arg "*) # Will only happen for absolute or sysroot arguments ;; *) # Preserve sysroot, but never include relative directories case $dir in [\\/]* | [A-Za-z]:[\\/]* | =*) func_append deplibs " $arg" ;; *) func_append deplibs " -L$dir" ;; esac func_append lib_search_path " $dir" ;; esac case $host in *-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-os2* | *-cegcc*) testbindir=`$ECHO "$dir" | $SED 's*/lib$*/bin*'` case :$dllsearchpath: in *":$dir:"*) ;; ::) dllsearchpath=$dir;; *) func_append dllsearchpath ":$dir";; esac case :$dllsearchpath: in *":$testbindir:"*) ;; ::) dllsearchpath=$testbindir;; *) func_append dllsearchpath ":$testbindir";; esac ;; esac continue ;; -l*) if test "X$arg" = "X-lc" || test "X$arg" = "X-lm"; then case $host in *-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-beos* | *-cegcc* | *-*-haiku*) # These systems don't actually have a C or math library (as such) continue ;; *-*-os2*) # These systems don't actually have a C library (as such) test "X$arg" = "X-lc" && continue ;; *-*-openbsd* | *-*-freebsd* | *-*-dragonfly*) # Do not include libc due to us having libc/libc_r. test "X$arg" = "X-lc" && continue ;; *-*-rhapsody* | *-*-darwin1.[012]) # Rhapsody C and math libraries are in the System framework func_append deplibs " System.ltframework" continue ;; *-*-sco3.2v5* | *-*-sco5v6*) # Causes problems with __ctype test "X$arg" = "X-lc" && continue ;; *-*-sysv4.2uw2* | *-*-sysv5* | *-*-unixware* | *-*-OpenUNIX*) # Compiler inserts libc in the correct place for threads to work test "X$arg" = "X-lc" && continue ;; esac elif test "X$arg" = "X-lc_r"; then case $host in *-*-openbsd* | *-*-freebsd* | *-*-dragonfly*) # Do not include libc_r directly, use -pthread flag. continue ;; esac fi func_append deplibs " $arg" continue ;; -module) module=yes continue ;; # Tru64 UNIX uses -model [arg] to determine the layout of C++ # classes, name mangling, and exception handling. # Darwin uses the -arch flag to determine output architecture. -model|-arch|-isysroot|--sysroot) func_append compiler_flags " $arg" func_append compile_command " $arg" func_append finalize_command " $arg" prev=xcompiler continue ;; -mt|-mthreads|-kthread|-Kthread|-pthread|-pthreads|--thread-safe|-threads) func_append compiler_flags " $arg" func_append compile_command " $arg" func_append finalize_command " $arg" case "$new_inherited_linker_flags " in *" $arg "*) ;; * ) func_append new_inherited_linker_flags " $arg" ;; esac continue ;; -multi_module) single_module="${wl}-multi_module" continue ;; -no-fast-install) fast_install=no continue ;; -no-install) case $host in *-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-os2* | *-*-darwin* | *-cegcc*) # The PATH hackery in wrapper scripts is required on Windows # and Darwin in order for the loader to find any dlls it needs. func_warning "\`-no-install' is ignored for $host" func_warning "assuming \`-no-fast-install' instead" fast_install=no ;; *) no_install=yes ;; esac continue ;; -no-undefined) allow_undefined=no continue ;; -objectlist) prev=objectlist continue ;; -o) prev=output ;; -precious-files-regex) prev=precious_regex continue ;; -release) prev=release continue ;; -rpath) prev=rpath continue ;; -R) prev=xrpath continue ;; -R*) func_stripname '-R' '' "$arg" dir=$func_stripname_result # We need an absolute path. case $dir in [\\/]* | [A-Za-z]:[\\/]*) ;; =*) func_stripname '=' '' "$dir" dir=$lt_sysroot$func_stripname_result ;; *) func_fatal_error "only absolute run-paths are allowed" ;; esac case "$xrpath " in *" $dir "*) ;; *) func_append xrpath " $dir" ;; esac continue ;; -shared) # The effects of -shared are defined in a previous loop. continue ;; -shrext) prev=shrext continue ;; -static | -static-libtool-libs) # The effects of -static are defined in a previous loop. # We used to do the same as -all-static on platforms that # didn't have a PIC flag, but the assumption that the effects # would be equivalent was wrong. It would break on at least # Digital Unix and AIX. continue ;; -thread-safe) thread_safe=yes continue ;; -version-info) prev=vinfo continue ;; -version-number) prev=vinfo vinfo_number=yes continue ;; -weak) prev=weak continue ;; -Wc,*) func_stripname '-Wc,' '' "$arg" args=$func_stripname_result arg= save_ifs="$IFS"; IFS=',' for flag in $args; do IFS="$save_ifs" func_quote_for_eval "$flag" func_append arg " $func_quote_for_eval_result" func_append compiler_flags " $func_quote_for_eval_result" done IFS="$save_ifs" func_stripname ' ' '' "$arg" arg=$func_stripname_result ;; -Wl,*) func_stripname '-Wl,' '' "$arg" args=$func_stripname_result arg= save_ifs="$IFS"; IFS=',' for flag in $args; do IFS="$save_ifs" func_quote_for_eval "$flag" func_append arg " $wl$func_quote_for_eval_result" func_append compiler_flags " $wl$func_quote_for_eval_result" func_append linker_flags " $func_quote_for_eval_result" done IFS="$save_ifs" func_stripname ' ' '' "$arg" arg=$func_stripname_result ;; -Xcompiler) prev=xcompiler continue ;; -Xlinker) prev=xlinker continue ;; -XCClinker) prev=xcclinker continue ;; # -msg_* for osf cc -msg_*) func_quote_for_eval "$arg" arg="$func_quote_for_eval_result" ;; # Flags to be passed through unchanged, with rationale: # -64, -mips[0-9] enable 64-bit mode for the SGI compiler # -r[0-9][0-9]* specify processor for the SGI compiler # -xarch=*, -xtarget=* enable 64-bit mode for the Sun compiler # +DA*, +DD* enable 64-bit mode for the HP compiler # -q* compiler args for the IBM compiler # -m*, -t[45]*, -txscale* architecture-specific flags for GCC # -F/path path to uninstalled frameworks, gcc on darwin # -p, -pg, --coverage, -fprofile-* profiling flags for GCC # @file GCC response files # -tp=* Portland pgcc target processor selection # --sysroot=* for sysroot support # -O*, -flto*, -fwhopr*, -fuse-linker-plugin GCC link-time optimization -64|-mips[0-9]|-r[0-9][0-9]*|-xarch=*|-xtarget=*|+DA*|+DD*|-q*|-m*| \ -t[45]*|-txscale*|-p|-pg|--coverage|-fprofile-*|-F*|@*|-tp=*|--sysroot=*| \ -O*|-flto*|-fwhopr*|-fuse-linker-plugin) func_quote_for_eval "$arg" arg="$func_quote_for_eval_result" func_append compile_command " $arg" func_append finalize_command " $arg" func_append compiler_flags " $arg" continue ;; # Some other compiler flag. -* | +*) func_quote_for_eval "$arg" arg="$func_quote_for_eval_result" ;; *.$objext) # A standard object. func_append objs " $arg" ;; *.lo) # A libtool-controlled object. # Check to see that this really is a libtool object. if func_lalib_unsafe_p "$arg"; then pic_object= non_pic_object= # Read the .lo file func_source "$arg" if test -z "$pic_object" || test -z "$non_pic_object" || test "$pic_object" = none && test "$non_pic_object" = none; then func_fatal_error "cannot find name of object for \`$arg'" fi # Extract subdirectory from the argument. func_dirname "$arg" "/" "" xdir="$func_dirname_result" if test "$pic_object" != none; then # Prepend the subdirectory the object is found in. pic_object="$xdir$pic_object" if test "$prev" = dlfiles; then if test "$build_libtool_libs" = yes && test "$dlopen_support" = yes; then func_append dlfiles " $pic_object" prev= continue else # If libtool objects are unsupported, then we need to preload. prev=dlprefiles fi fi # CHECK ME: I think I busted this. -Ossama if test "$prev" = dlprefiles; then # Preload the old-style object. func_append dlprefiles " $pic_object" prev= fi # A PIC object. func_append libobjs " $pic_object" arg="$pic_object" fi # Non-PIC object. if test "$non_pic_object" != none; then # Prepend the subdirectory the object is found in. non_pic_object="$xdir$non_pic_object" # A standard non-PIC object func_append non_pic_objects " $non_pic_object" if test -z "$pic_object" || test "$pic_object" = none ; then arg="$non_pic_object" fi else # If the PIC object exists, use it instead. # $xdir was prepended to $pic_object above. non_pic_object="$pic_object" func_append non_pic_objects " $non_pic_object" fi else # Only an error if not doing a dry-run. if $opt_dry_run; then # Extract subdirectory from the argument. func_dirname "$arg" "/" "" xdir="$func_dirname_result" func_lo2o "$arg" pic_object=$xdir$objdir/$func_lo2o_result non_pic_object=$xdir$func_lo2o_result func_append libobjs " $pic_object" func_append non_pic_objects " $non_pic_object" else func_fatal_error "\`$arg' is not a valid libtool object" fi fi ;; *.$libext) # An archive. func_append deplibs " $arg" func_append old_deplibs " $arg" continue ;; *.la) # A libtool-controlled library. func_resolve_sysroot "$arg" if test "$prev" = dlfiles; then # This library was specified with -dlopen. func_append dlfiles " $func_resolve_sysroot_result" prev= elif test "$prev" = dlprefiles; then # The library was specified with -dlpreopen. func_append dlprefiles " $func_resolve_sysroot_result" prev= else func_append deplibs " $func_resolve_sysroot_result" fi continue ;; # Some other compiler argument. *) # Unknown arguments in both finalize_command and compile_command need # to be aesthetically quoted because they are evaled later. func_quote_for_eval "$arg" arg="$func_quote_for_eval_result" ;; esac # arg # Now actually substitute the argument into the commands. if test -n "$arg"; then func_append compile_command " $arg" func_append finalize_command " $arg" fi done # argument parsing loop test -n "$prev" && \ func_fatal_help "the \`$prevarg' option requires an argument" if test "$export_dynamic" = yes && test -n "$export_dynamic_flag_spec"; then eval arg=\"$export_dynamic_flag_spec\" func_append compile_command " $arg" func_append finalize_command " $arg" fi oldlibs= # calculate the name of the file, without its directory func_basename "$output" outputname="$func_basename_result" libobjs_save="$libobjs" if test -n "$shlibpath_var"; then # get the directories listed in $shlibpath_var eval shlib_search_path=\`\$ECHO \"\${$shlibpath_var}\" \| \$SED \'s/:/ /g\'\` else shlib_search_path= fi eval sys_lib_search_path=\"$sys_lib_search_path_spec\" eval sys_lib_dlsearch_path=\"$sys_lib_dlsearch_path_spec\" func_dirname "$output" "/" "" output_objdir="$func_dirname_result$objdir" func_to_tool_file "$output_objdir/" tool_output_objdir=$func_to_tool_file_result # Create the object directory. func_mkdir_p "$output_objdir" # Determine the type of output case $output in "") func_fatal_help "you must specify an output file" ;; *.$libext) linkmode=oldlib ;; *.lo | *.$objext) linkmode=obj ;; *.la) linkmode=lib ;; *) linkmode=prog ;; # Anything else should be a program. esac specialdeplibs= libs= # Find all interdependent deplibs by searching for libraries # that are linked more than once (e.g. -la -lb -la) for deplib in $deplibs; do if $opt_preserve_dup_deps ; then case "$libs " in *" $deplib "*) func_append specialdeplibs " $deplib" ;; esac fi func_append libs " $deplib" done if test "$linkmode" = lib; then libs="$predeps $libs $compiler_lib_search_path $postdeps" # Compute libraries that are listed more than once in $predeps # $postdeps and mark them as special (i.e., whose duplicates are # not to be eliminated). pre_post_deps= if $opt_duplicate_compiler_generated_deps; then for pre_post_dep in $predeps $postdeps; do case "$pre_post_deps " in *" $pre_post_dep "*) func_append specialdeplibs " $pre_post_deps" ;; esac func_append pre_post_deps " $pre_post_dep" done fi pre_post_deps= fi deplibs= newdependency_libs= newlib_search_path= need_relink=no # whether we're linking any uninstalled libtool libraries notinst_deplibs= # not-installed libtool libraries notinst_path= # paths that contain not-installed libtool libraries case $linkmode in lib) passes="conv dlpreopen link" for file in $dlfiles $dlprefiles; do case $file in *.la) ;; *) func_fatal_help "libraries can \`-dlopen' only libtool libraries: $file" ;; esac done ;; prog) compile_deplibs= finalize_deplibs= alldeplibs=no newdlfiles= newdlprefiles= passes="conv scan dlopen dlpreopen link" ;; *) passes="conv" ;; esac for pass in $passes; do # The preopen pass in lib mode reverses $deplibs; put it back here # so that -L comes before libs that need it for instance... if test "$linkmode,$pass" = "lib,link"; then ## FIXME: Find the place where the list is rebuilt in the wrong ## order, and fix it there properly tmp_deplibs= for deplib in $deplibs; do tmp_deplibs="$deplib $tmp_deplibs" done deplibs="$tmp_deplibs" fi if test "$linkmode,$pass" = "lib,link" || test "$linkmode,$pass" = "prog,scan"; then libs="$deplibs" deplibs= fi if test "$linkmode" = prog; then case $pass in dlopen) libs="$dlfiles" ;; dlpreopen) libs="$dlprefiles" ;; link) libs="$deplibs %DEPLIBS%" test "X$link_all_deplibs" != Xno && libs="$libs $dependency_libs" ;; esac fi if test "$linkmode,$pass" = "lib,dlpreopen"; then # Collect and forward deplibs of preopened libtool libs for lib in $dlprefiles; do # Ignore non-libtool-libs dependency_libs= func_resolve_sysroot "$lib" case $lib in *.la) func_source "$func_resolve_sysroot_result" ;; esac # Collect preopened libtool deplibs, except any this library # has declared as weak libs for deplib in $dependency_libs; do func_basename "$deplib" deplib_base=$func_basename_result case " $weak_libs " in *" $deplib_base "*) ;; *) func_append deplibs " $deplib" ;; esac done done libs="$dlprefiles" fi if test "$pass" = dlopen; then # Collect dlpreopened libraries save_deplibs="$deplibs" deplibs= fi for deplib in $libs; do lib= found=no case $deplib in -mt|-mthreads|-kthread|-Kthread|-pthread|-pthreads|--thread-safe|-threads) if test "$linkmode,$pass" = "prog,link"; then compile_deplibs="$deplib $compile_deplibs" finalize_deplibs="$deplib $finalize_deplibs" else func_append compiler_flags " $deplib" if test "$linkmode" = lib ; then case "$new_inherited_linker_flags " in *" $deplib "*) ;; * ) func_append new_inherited_linker_flags " $deplib" ;; esac fi fi continue ;; -l*) if test "$linkmode" != lib && test "$linkmode" != prog; then func_warning "\`-l' is ignored for archives/objects" continue fi func_stripname '-l' '' "$deplib" name=$func_stripname_result if test "$linkmode" = lib; then searchdirs="$newlib_search_path $lib_search_path $compiler_lib_search_dirs $sys_lib_search_path $shlib_search_path" else searchdirs="$newlib_search_path $lib_search_path $sys_lib_search_path $shlib_search_path" fi for searchdir in $searchdirs; do for search_ext in .la $std_shrext .so .a; do # Search the libtool library lib="$searchdir/lib${name}${search_ext}" if test -f "$lib"; then if test "$search_ext" = ".la"; then found=yes else found=no fi break 2 fi done done if test "$found" != yes; then # deplib doesn't seem to be a libtool library if test "$linkmode,$pass" = "prog,link"; then compile_deplibs="$deplib $compile_deplibs" finalize_deplibs="$deplib $finalize_deplibs" else deplibs="$deplib $deplibs" test "$linkmode" = lib && newdependency_libs="$deplib $newdependency_libs" fi continue else # deplib is a libtool library # If $allow_libtool_libs_with_static_runtimes && $deplib is a stdlib, # We need to do some special things here, and not later. if test "X$allow_libtool_libs_with_static_runtimes" = "Xyes" ; then case " $predeps $postdeps " in *" $deplib "*) if func_lalib_p "$lib"; then library_names= old_library= func_source "$lib" for l in $old_library $library_names; do ll="$l" done if test "X$ll" = "X$old_library" ; then # only static version available found=no func_dirname "$lib" "" "." ladir="$func_dirname_result" lib=$ladir/$old_library if test "$linkmode,$pass" = "prog,link"; then compile_deplibs="$deplib $compile_deplibs" finalize_deplibs="$deplib $finalize_deplibs" else deplibs="$deplib $deplibs" test "$linkmode" = lib && newdependency_libs="$deplib $newdependency_libs" fi continue fi fi ;; *) ;; esac fi fi ;; # -l *.ltframework) if test "$linkmode,$pass" = "prog,link"; then compile_deplibs="$deplib $compile_deplibs" finalize_deplibs="$deplib $finalize_deplibs" else deplibs="$deplib $deplibs" if test "$linkmode" = lib ; then case "$new_inherited_linker_flags " in *" $deplib "*) ;; * ) func_append new_inherited_linker_flags " $deplib" ;; esac fi fi continue ;; -L*) case $linkmode in lib) deplibs="$deplib $deplibs" test "$pass" = conv && continue newdependency_libs="$deplib $newdependency_libs" func_stripname '-L' '' "$deplib" func_resolve_sysroot "$func_stripname_result" func_append newlib_search_path " $func_resolve_sysroot_result" ;; prog) if test "$pass" = conv; then deplibs="$deplib $deplibs" continue fi if test "$pass" = scan; then deplibs="$deplib $deplibs" else compile_deplibs="$deplib $compile_deplibs" finalize_deplibs="$deplib $finalize_deplibs" fi func_stripname '-L' '' "$deplib" func_resolve_sysroot "$func_stripname_result" func_append newlib_search_path " $func_resolve_sysroot_result" ;; *) func_warning "\`-L' is ignored for archives/objects" ;; esac # linkmode continue ;; # -L -R*) if test "$pass" = link; then func_stripname '-R' '' "$deplib" func_resolve_sysroot "$func_stripname_result" dir=$func_resolve_sysroot_result # Make sure the xrpath contains only unique directories. case "$xrpath " in *" $dir "*) ;; *) func_append xrpath " $dir" ;; esac fi deplibs="$deplib $deplibs" continue ;; *.la) func_resolve_sysroot "$deplib" lib=$func_resolve_sysroot_result ;; *.$libext) if test "$pass" = conv; then deplibs="$deplib $deplibs" continue fi case $linkmode in lib) # Linking convenience modules into shared libraries is allowed, # but linking other static libraries is non-portable. case " $dlpreconveniencelibs " in *" $deplib "*) ;; *) valid_a_lib=no case $deplibs_check_method in match_pattern*) set dummy $deplibs_check_method; shift match_pattern_regex=`expr "$deplibs_check_method" : "$1 \(.*\)"` if eval "\$ECHO \"$deplib\"" 2>/dev/null | $SED 10q \ | $EGREP "$match_pattern_regex" > /dev/null; then valid_a_lib=yes fi ;; pass_all) valid_a_lib=yes ;; esac if test "$valid_a_lib" != yes; then echo $ECHO "*** Warning: Trying to link with static lib archive $deplib." echo "*** I have the capability to make that library automatically link in when" echo "*** you link to this library. But I can only do this if you have a" echo "*** shared version of the library, which you do not appear to have" echo "*** because the file extensions .$libext of this argument makes me believe" echo "*** that it is just a static archive that I should not use here." else echo $ECHO "*** Warning: Linking the shared library $output against the" $ECHO "*** static library $deplib is not portable!" deplibs="$deplib $deplibs" fi ;; esac continue ;; prog) if test "$pass" != link; then deplibs="$deplib $deplibs" else compile_deplibs="$deplib $compile_deplibs" finalize_deplibs="$deplib $finalize_deplibs" fi continue ;; esac # linkmode ;; # *.$libext *.lo | *.$objext) if test "$pass" = conv; then deplibs="$deplib $deplibs" elif test "$linkmode" = prog; then if test "$pass" = dlpreopen || test "$dlopen_support" != yes || test "$build_libtool_libs" = no; then # If there is no dlopen support or we're linking statically, # we need to preload. func_append newdlprefiles " $deplib" compile_deplibs="$deplib $compile_deplibs" finalize_deplibs="$deplib $finalize_deplibs" else func_append newdlfiles " $deplib" fi fi continue ;; %DEPLIBS%) alldeplibs=yes continue ;; esac # case $deplib if test "$found" = yes || test -f "$lib"; then : else func_fatal_error "cannot find the library \`$lib' or unhandled argument \`$deplib'" fi # Check to see that this really is a libtool archive. func_lalib_unsafe_p "$lib" \ || func_fatal_error "\`$lib' is not a valid libtool archive" func_dirname "$lib" "" "." ladir="$func_dirname_result" dlname= dlopen= dlpreopen= libdir= library_names= old_library= inherited_linker_flags= # If the library was installed with an old release of libtool, # it will not redefine variables installed, or shouldnotlink installed=yes shouldnotlink=no avoidtemprpath= # Read the .la file func_source "$lib" # Convert "-framework foo" to "foo.ltframework" if test -n "$inherited_linker_flags"; then tmp_inherited_linker_flags=`$ECHO "$inherited_linker_flags" | $SED 's/-framework \([^ $]*\)/\1.ltframework/g'` for tmp_inherited_linker_flag in $tmp_inherited_linker_flags; do case " $new_inherited_linker_flags " in *" $tmp_inherited_linker_flag "*) ;; *) func_append new_inherited_linker_flags " $tmp_inherited_linker_flag";; esac done fi dependency_libs=`$ECHO " $dependency_libs" | $SED 's% \([^ $]*\).ltframework% -framework \1%g'` if test "$linkmode,$pass" = "lib,link" || test "$linkmode,$pass" = "prog,scan" || { test "$linkmode" != prog && test "$linkmode" != lib; }; then test -n "$dlopen" && func_append dlfiles " $dlopen" test -n "$dlpreopen" && func_append dlprefiles " $dlpreopen" fi if test "$pass" = conv; then # Only check for convenience libraries deplibs="$lib $deplibs" if test -z "$libdir"; then if test -z "$old_library"; then func_fatal_error "cannot find name of link library for \`$lib'" fi # It is a libtool convenience library, so add in its objects. func_append convenience " $ladir/$objdir/$old_library" func_append old_convenience " $ladir/$objdir/$old_library" tmp_libs= for deplib in $dependency_libs; do deplibs="$deplib $deplibs" if $opt_preserve_dup_deps ; then case "$tmp_libs " in *" $deplib "*) func_append specialdeplibs " $deplib" ;; esac fi func_append tmp_libs " $deplib" done elif test "$linkmode" != prog && test "$linkmode" != lib; then func_fatal_error "\`$lib' is not a convenience library" fi continue fi # $pass = conv # Get the name of the library we link against. linklib= if test -n "$old_library" && { test "$prefer_static_libs" = yes || test "$prefer_static_libs,$installed" = "built,no"; }; then linklib=$old_library else for l in $old_library $library_names; do linklib="$l" done fi if test -z "$linklib"; then func_fatal_error "cannot find name of link library for \`$lib'" fi # This library was specified with -dlopen. if test "$pass" = dlopen; then if test -z "$libdir"; then func_fatal_error "cannot -dlopen a convenience library: \`$lib'" fi if test -z "$dlname" || test "$dlopen_support" != yes || test "$build_libtool_libs" = no; then # If there is no dlname, no dlopen support or we're linking # statically, we need to preload. We also need to preload any # dependent libraries so libltdl's deplib preloader doesn't # bomb out in the load deplibs phase. func_append dlprefiles " $lib $dependency_libs" else func_append newdlfiles " $lib" fi continue fi # $pass = dlopen # We need an absolute path. case $ladir in [\\/]* | [A-Za-z]:[\\/]*) abs_ladir="$ladir" ;; *) abs_ladir=`cd "$ladir" && pwd` if test -z "$abs_ladir"; then func_warning "cannot determine absolute directory name of \`$ladir'" func_warning "passing it literally to the linker, although it might fail" abs_ladir="$ladir" fi ;; esac func_basename "$lib" laname="$func_basename_result" # Find the relevant object directory and library name. if test "X$installed" = Xyes; then if test ! -f "$lt_sysroot$libdir/$linklib" && test -f "$abs_ladir/$linklib"; then func_warning "library \`$lib' was moved." dir="$ladir" absdir="$abs_ladir" libdir="$abs_ladir" else dir="$lt_sysroot$libdir" absdir="$lt_sysroot$libdir" fi test "X$hardcode_automatic" = Xyes && avoidtemprpath=yes else if test ! -f "$ladir/$objdir/$linklib" && test -f "$abs_ladir/$linklib"; then dir="$ladir" absdir="$abs_ladir" # Remove this search path later func_append notinst_path " $abs_ladir" else dir="$ladir/$objdir" absdir="$abs_ladir/$objdir" # Remove this search path later func_append notinst_path " $abs_ladir" fi fi # $installed = yes func_stripname 'lib' '.la' "$laname" name=$func_stripname_result # This library was specified with -dlpreopen. if test "$pass" = dlpreopen; then if test -z "$libdir" && test "$linkmode" = prog; then func_fatal_error "only libraries may -dlpreopen a convenience library: \`$lib'" fi case "$host" in # special handling for platforms with PE-DLLs. *cygwin* | *mingw* | *cegcc* ) # Linker will automatically link against shared library if both # static and shared are present. Therefore, ensure we extract # symbols from the import library if a shared library is present # (otherwise, the dlopen module name will be incorrect). We do # this by putting the import library name into $newdlprefiles. # We recover the dlopen module name by 'saving' the la file # name in a special purpose variable, and (later) extracting the # dlname from the la file. if test -n "$dlname"; then func_tr_sh "$dir/$linklib" eval "libfile_$func_tr_sh_result=\$abs_ladir/\$laname" func_append newdlprefiles " $dir/$linklib" else func_append newdlprefiles " $dir/$old_library" # Keep a list of preopened convenience libraries to check # that they are being used correctly in the link pass. test -z "$libdir" && \ func_append dlpreconveniencelibs " $dir/$old_library" fi ;; * ) # Prefer using a static library (so that no silly _DYNAMIC symbols # are required to link). if test -n "$old_library"; then func_append newdlprefiles " $dir/$old_library" # Keep a list of preopened convenience libraries to check # that they are being used correctly in the link pass. test -z "$libdir" && \ func_append dlpreconveniencelibs " $dir/$old_library" # Otherwise, use the dlname, so that lt_dlopen finds it. elif test -n "$dlname"; then func_append newdlprefiles " $dir/$dlname" else func_append newdlprefiles " $dir/$linklib" fi ;; esac fi # $pass = dlpreopen if test -z "$libdir"; then # Link the convenience library if test "$linkmode" = lib; then deplibs="$dir/$old_library $deplibs" elif test "$linkmode,$pass" = "prog,link"; then compile_deplibs="$dir/$old_library $compile_deplibs" finalize_deplibs="$dir/$old_library $finalize_deplibs" else deplibs="$lib $deplibs" # used for prog,scan pass fi continue fi if test "$linkmode" = prog && test "$pass" != link; then func_append newlib_search_path " $ladir" deplibs="$lib $deplibs" linkalldeplibs=no if test "$link_all_deplibs" != no || test -z "$library_names" || test "$build_libtool_libs" = no; then linkalldeplibs=yes fi tmp_libs= for deplib in $dependency_libs; do case $deplib in -L*) func_stripname '-L' '' "$deplib" func_resolve_sysroot "$func_stripname_result" func_append newlib_search_path " $func_resolve_sysroot_result" ;; esac # Need to link against all dependency_libs? if test "$linkalldeplibs" = yes; then deplibs="$deplib $deplibs" else # Need to hardcode shared library paths # or/and link against static libraries newdependency_libs="$deplib $newdependency_libs" fi if $opt_preserve_dup_deps ; then case "$tmp_libs " in *" $deplib "*) func_append specialdeplibs " $deplib" ;; esac fi func_append tmp_libs " $deplib" done # for deplib continue fi # $linkmode = prog... if test "$linkmode,$pass" = "prog,link"; then if test -n "$library_names" && { { test "$prefer_static_libs" = no || test "$prefer_static_libs,$installed" = "built,yes"; } || test -z "$old_library"; }; then # We need to hardcode the library path if test -n "$shlibpath_var" && test -z "$avoidtemprpath" ; then # Make sure the rpath contains only unique directories. case "$temp_rpath:" in *"$absdir:"*) ;; *) func_append temp_rpath "$absdir:" ;; esac fi # Hardcode the library path. # Skip directories that are in the system default run-time # search path. case " $sys_lib_dlsearch_path " in *" $absdir "*) ;; *) case "$compile_rpath " in *" $absdir "*) ;; *) func_append compile_rpath " $absdir" ;; esac ;; esac case " $sys_lib_dlsearch_path " in *" $libdir "*) ;; *) case "$finalize_rpath " in *" $libdir "*) ;; *) func_append finalize_rpath " $libdir" ;; esac ;; esac fi # $linkmode,$pass = prog,link... if test "$alldeplibs" = yes && { test "$deplibs_check_method" = pass_all || { test "$build_libtool_libs" = yes && test -n "$library_names"; }; }; then # We only need to search for static libraries continue fi fi link_static=no # Whether the deplib will be linked statically use_static_libs=$prefer_static_libs if test "$use_static_libs" = built && test "$installed" = yes; then use_static_libs=no fi if test -n "$library_names" && { test "$use_static_libs" = no || test -z "$old_library"; }; then case $host in *cygwin* | *mingw* | *cegcc*) # No point in relinking DLLs because paths are not encoded func_append notinst_deplibs " $lib" need_relink=no ;; *) if test "$installed" = no; then func_append notinst_deplibs " $lib" need_relink=yes fi ;; esac # This is a shared library # Warn about portability, can't link against -module's on some # systems (darwin). Don't bleat about dlopened modules though! dlopenmodule="" for dlpremoduletest in $dlprefiles; do if test "X$dlpremoduletest" = "X$lib"; then dlopenmodule="$dlpremoduletest" break fi done if test -z "$dlopenmodule" && test "$shouldnotlink" = yes && test "$pass" = link; then echo if test "$linkmode" = prog; then $ECHO "*** Warning: Linking the executable $output against the loadable module" else $ECHO "*** Warning: Linking the shared library $output against the loadable module" fi $ECHO "*** $linklib is not portable!" fi if test "$linkmode" = lib && test "$hardcode_into_libs" = yes; then # Hardcode the library path. # Skip directories that are in the system default run-time # search path. case " $sys_lib_dlsearch_path " in *" $absdir "*) ;; *) case "$compile_rpath " in *" $absdir "*) ;; *) func_append compile_rpath " $absdir" ;; esac ;; esac case " $sys_lib_dlsearch_path " in *" $libdir "*) ;; *) case "$finalize_rpath " in *" $libdir "*) ;; *) func_append finalize_rpath " $libdir" ;; esac ;; esac fi if test -n "$old_archive_from_expsyms_cmds"; then # figure out the soname set dummy $library_names shift realname="$1" shift libname=`eval "\\$ECHO \"$libname_spec\""` # use dlname if we got it. it's perfectly good, no? if test -n "$dlname"; then soname="$dlname" elif test -n "$soname_spec"; then # bleh windows case $host in *cygwin* | mingw* | *cegcc*) func_arith $current - $age major=$func_arith_result versuffix="-$major" ;; esac eval soname=\"$soname_spec\" else soname="$realname" fi # Make a new name for the extract_expsyms_cmds to use soroot="$soname" func_basename "$soroot" soname="$func_basename_result" func_stripname 'lib' '.dll' "$soname" newlib=libimp-$func_stripname_result.a # If the library has no export list, then create one now if test -f "$output_objdir/$soname-def"; then : else func_verbose "extracting exported symbol list from \`$soname'" func_execute_cmds "$extract_expsyms_cmds" 'exit $?' fi # Create $newlib if test -f "$output_objdir/$newlib"; then :; else func_verbose "generating import library for \`$soname'" func_execute_cmds "$old_archive_from_expsyms_cmds" 'exit $?' fi # make sure the library variables are pointing to the new library dir=$output_objdir linklib=$newlib fi # test -n "$old_archive_from_expsyms_cmds" if test "$linkmode" = prog || test "$opt_mode" != relink; then add_shlibpath= add_dir= add= lib_linked=yes case $hardcode_action in immediate | unsupported) if test "$hardcode_direct" = no; then add="$dir/$linklib" case $host in *-*-sco3.2v5.0.[024]*) add_dir="-L$dir" ;; *-*-sysv4*uw2*) add_dir="-L$dir" ;; *-*-sysv5OpenUNIX* | *-*-sysv5UnixWare7.[01].[10]* | \ *-*-unixware7*) add_dir="-L$dir" ;; *-*-darwin* ) # if the lib is a (non-dlopened) module then we can not # link against it, someone is ignoring the earlier warnings if /usr/bin/file -L $add 2> /dev/null | $GREP ": [^:]* bundle" >/dev/null ; then if test "X$dlopenmodule" != "X$lib"; then $ECHO "*** Warning: lib $linklib is a module, not a shared library" if test -z "$old_library" ; then echo echo "*** And there doesn't seem to be a static archive available" echo "*** The link will probably fail, sorry" else add="$dir/$old_library" fi elif test -n "$old_library"; then add="$dir/$old_library" fi fi esac elif test "$hardcode_minus_L" = no; then case $host in *-*-sunos*) add_shlibpath="$dir" ;; esac add_dir="-L$dir" add="-l$name" elif test "$hardcode_shlibpath_var" = no; then add_shlibpath="$dir" add="-l$name" else lib_linked=no fi ;; relink) if test "$hardcode_direct" = yes && test "$hardcode_direct_absolute" = no; then add="$dir/$linklib" elif test "$hardcode_minus_L" = yes; then add_dir="-L$dir" # Try looking first in the location we're being installed to. if test -n "$inst_prefix_dir"; then case $libdir in [\\/]*) func_append add_dir " -L$inst_prefix_dir$libdir" ;; esac fi add="-l$name" elif test "$hardcode_shlibpath_var" = yes; then add_shlibpath="$dir" add="-l$name" else lib_linked=no fi ;; *) lib_linked=no ;; esac if test "$lib_linked" != yes; then func_fatal_configuration "unsupported hardcode properties" fi if test -n "$add_shlibpath"; then case :$compile_shlibpath: in *":$add_shlibpath:"*) ;; *) func_append compile_shlibpath "$add_shlibpath:" ;; esac fi if test "$linkmode" = prog; then test -n "$add_dir" && compile_deplibs="$add_dir $compile_deplibs" test -n "$add" && compile_deplibs="$add $compile_deplibs" else test -n "$add_dir" && deplibs="$add_dir $deplibs" test -n "$add" && deplibs="$add $deplibs" if test "$hardcode_direct" != yes && test "$hardcode_minus_L" != yes && test "$hardcode_shlibpath_var" = yes; then case :$finalize_shlibpath: in *":$libdir:"*) ;; *) func_append finalize_shlibpath "$libdir:" ;; esac fi fi fi if test "$linkmode" = prog || test "$opt_mode" = relink; then add_shlibpath= add_dir= add= # Finalize command for both is simple: just hardcode it. if test "$hardcode_direct" = yes && test "$hardcode_direct_absolute" = no; then add="$libdir/$linklib" elif test "$hardcode_minus_L" = yes; then add_dir="-L$libdir" add="-l$name" elif test "$hardcode_shlibpath_var" = yes; then case :$finalize_shlibpath: in *":$libdir:"*) ;; *) func_append finalize_shlibpath "$libdir:" ;; esac add="-l$name" elif test "$hardcode_automatic" = yes; then if test -n "$inst_prefix_dir" && test -f "$inst_prefix_dir$libdir/$linklib" ; then add="$inst_prefix_dir$libdir/$linklib" else add="$libdir/$linklib" fi else # We cannot seem to hardcode it, guess we'll fake it. add_dir="-L$libdir" # Try looking first in the location we're being installed to. if test -n "$inst_prefix_dir"; then case $libdir in [\\/]*) func_append add_dir " -L$inst_prefix_dir$libdir" ;; esac fi add="-l$name" fi if test "$linkmode" = prog; then test -n "$add_dir" && finalize_deplibs="$add_dir $finalize_deplibs" test -n "$add" && finalize_deplibs="$add $finalize_deplibs" else test -n "$add_dir" && deplibs="$add_dir $deplibs" test -n "$add" && deplibs="$add $deplibs" fi fi elif test "$linkmode" = prog; then # Here we assume that one of hardcode_direct or hardcode_minus_L # is not unsupported. This is valid on all known static and # shared platforms. if test "$hardcode_direct" != unsupported; then test -n "$old_library" && linklib="$old_library" compile_deplibs="$dir/$linklib $compile_deplibs" finalize_deplibs="$dir/$linklib $finalize_deplibs" else compile_deplibs="-l$name -L$dir $compile_deplibs" finalize_deplibs="-l$name -L$dir $finalize_deplibs" fi elif test "$build_libtool_libs" = yes; then # Not a shared library if test "$deplibs_check_method" != pass_all; then # We're trying link a shared library against a static one # but the system doesn't support it. # Just print a warning and add the library to dependency_libs so # that the program can be linked against the static library. echo $ECHO "*** Warning: This system can not link to static lib archive $lib." echo "*** I have the capability to make that library automatically link in when" echo "*** you link to this library. But I can only do this if you have a" echo "*** shared version of the library, which you do not appear to have." if test "$module" = yes; then echo "*** But as you try to build a module library, libtool will still create " echo "*** a static module, that should work as long as the dlopening application" echo "*** is linked with the -dlopen flag to resolve symbols at runtime." if test -z "$global_symbol_pipe"; then echo echo "*** However, this would only work if libtool was able to extract symbol" echo "*** lists from a program, using \`nm' or equivalent, but libtool could" echo "*** not find such a program. So, this module is probably useless." echo "*** \`nm' from GNU binutils and a full rebuild may help." fi if test "$build_old_libs" = no; then build_libtool_libs=module build_old_libs=yes else build_libtool_libs=no fi fi else deplibs="$dir/$old_library $deplibs" link_static=yes fi fi # link shared/static library? if test "$linkmode" = lib; then if test -n "$dependency_libs" && { test "$hardcode_into_libs" != yes || test "$build_old_libs" = yes || test "$link_static" = yes; }; then # Extract -R from dependency_libs temp_deplibs= for libdir in $dependency_libs; do case $libdir in -R*) func_stripname '-R' '' "$libdir" temp_xrpath=$func_stripname_result case " $xrpath " in *" $temp_xrpath "*) ;; *) func_append xrpath " $temp_xrpath";; esac;; *) func_append temp_deplibs " $libdir";; esac done dependency_libs="$temp_deplibs" fi func_append newlib_search_path " $absdir" # Link against this library test "$link_static" = no && newdependency_libs="$abs_ladir/$laname $newdependency_libs" # ... and its dependency_libs tmp_libs= for deplib in $dependency_libs; do newdependency_libs="$deplib $newdependency_libs" case $deplib in -L*) func_stripname '-L' '' "$deplib" func_resolve_sysroot "$func_stripname_result";; *) func_resolve_sysroot "$deplib" ;; esac if $opt_preserve_dup_deps ; then case "$tmp_libs " in *" $func_resolve_sysroot_result "*) func_append specialdeplibs " $func_resolve_sysroot_result" ;; esac fi func_append tmp_libs " $func_resolve_sysroot_result" done if test "$link_all_deplibs" != no; then # Add the search paths of all dependency libraries for deplib in $dependency_libs; do path= case $deplib in -L*) path="$deplib" ;; *.la) func_resolve_sysroot "$deplib" deplib=$func_resolve_sysroot_result func_dirname "$deplib" "" "." dir=$func_dirname_result # We need an absolute path. case $dir in [\\/]* | [A-Za-z]:[\\/]*) absdir="$dir" ;; *) absdir=`cd "$dir" && pwd` if test -z "$absdir"; then func_warning "cannot determine absolute directory name of \`$dir'" absdir="$dir" fi ;; esac if $GREP "^installed=no" $deplib > /dev/null; then case $host in *-*-darwin*) depdepl= eval deplibrary_names=`${SED} -n -e 's/^library_names=\(.*\)$/\1/p' $deplib` if test -n "$deplibrary_names" ; then for tmp in $deplibrary_names ; do depdepl=$tmp done if test -f "$absdir/$objdir/$depdepl" ; then depdepl="$absdir/$objdir/$depdepl" darwin_install_name=`${OTOOL} -L $depdepl | awk '{if (NR == 2) {print $1;exit}}'` if test -z "$darwin_install_name"; then darwin_install_name=`${OTOOL64} -L $depdepl | awk '{if (NR == 2) {print $1;exit}}'` fi func_append compiler_flags " ${wl}-dylib_file ${wl}${darwin_install_name}:${depdepl}" func_append linker_flags " -dylib_file ${darwin_install_name}:${depdepl}" path= fi fi ;; *) path="-L$absdir/$objdir" ;; esac else eval libdir=`${SED} -n -e 's/^libdir=\(.*\)$/\1/p' $deplib` test -z "$libdir" && \ func_fatal_error "\`$deplib' is not a valid libtool archive" test "$absdir" != "$libdir" && \ func_warning "\`$deplib' seems to be moved" path="-L$absdir" fi ;; esac case " $deplibs " in *" $path "*) ;; *) deplibs="$path $deplibs" ;; esac done fi # link_all_deplibs != no fi # linkmode = lib done # for deplib in $libs if test "$pass" = link; then if test "$linkmode" = "prog"; then compile_deplibs="$new_inherited_linker_flags $compile_deplibs" finalize_deplibs="$new_inherited_linker_flags $finalize_deplibs" else compiler_flags="$compiler_flags "`$ECHO " $new_inherited_linker_flags" | $SED 's% \([^ $]*\).ltframework% -framework \1%g'` fi fi dependency_libs="$newdependency_libs" if test "$pass" = dlpreopen; then # Link the dlpreopened libraries before other libraries for deplib in $save_deplibs; do deplibs="$deplib $deplibs" done fi if test "$pass" != dlopen; then if test "$pass" != conv; then # Make sure lib_search_path contains only unique directories. lib_search_path= for dir in $newlib_search_path; do case "$lib_search_path " in *" $dir "*) ;; *) func_append lib_search_path " $dir" ;; esac done newlib_search_path= fi if test "$linkmode,$pass" != "prog,link"; then vars="deplibs" else vars="compile_deplibs finalize_deplibs" fi for var in $vars dependency_libs; do # Add libraries to $var in reverse order eval tmp_libs=\"\$$var\" new_libs= for deplib in $tmp_libs; do # FIXME: Pedantically, this is the right thing to do, so # that some nasty dependency loop isn't accidentally # broken: #new_libs="$deplib $new_libs" # Pragmatically, this seems to cause very few problems in # practice: case $deplib in -L*) new_libs="$deplib $new_libs" ;; -R*) ;; *) # And here is the reason: when a library appears more # than once as an explicit dependence of a library, or # is implicitly linked in more than once by the # compiler, it is considered special, and multiple # occurrences thereof are not removed. Compare this # with having the same library being listed as a # dependency of multiple other libraries: in this case, # we know (pedantically, we assume) the library does not # need to be listed more than once, so we keep only the # last copy. This is not always right, but it is rare # enough that we require users that really mean to play # such unportable linking tricks to link the library # using -Wl,-lname, so that libtool does not consider it # for duplicate removal. case " $specialdeplibs " in *" $deplib "*) new_libs="$deplib $new_libs" ;; *) case " $new_libs " in *" $deplib "*) ;; *) new_libs="$deplib $new_libs" ;; esac ;; esac ;; esac done tmp_libs= for deplib in $new_libs; do case $deplib in -L*) case " $tmp_libs " in *" $deplib "*) ;; *) func_append tmp_libs " $deplib" ;; esac ;; *) func_append tmp_libs " $deplib" ;; esac done eval $var=\"$tmp_libs\" done # for var fi # Last step: remove runtime libs from dependency_libs # (they stay in deplibs) tmp_libs= for i in $dependency_libs ; do case " $predeps $postdeps $compiler_lib_search_path " in *" $i "*) i="" ;; esac if test -n "$i" ; then func_append tmp_libs " $i" fi done dependency_libs=$tmp_libs done # for pass if test "$linkmode" = prog; then dlfiles="$newdlfiles" fi if test "$linkmode" = prog || test "$linkmode" = lib; then dlprefiles="$newdlprefiles" fi case $linkmode in oldlib) if test -n "$dlfiles$dlprefiles" || test "$dlself" != no; then func_warning "\`-dlopen' is ignored for archives" fi case " $deplibs" in *\ -l* | *\ -L*) func_warning "\`-l' and \`-L' are ignored for archives" ;; esac test -n "$rpath" && \ func_warning "\`-rpath' is ignored for archives" test -n "$xrpath" && \ func_warning "\`-R' is ignored for archives" test -n "$vinfo" && \ func_warning "\`-version-info/-version-number' is ignored for archives" test -n "$release" && \ func_warning "\`-release' is ignored for archives" test -n "$export_symbols$export_symbols_regex" && \ func_warning "\`-export-symbols' is ignored for archives" # Now set the variables for building old libraries. build_libtool_libs=no oldlibs="$output" func_append objs "$old_deplibs" ;; lib) # Make sure we only generate libraries of the form `libNAME.la'. case $outputname in lib*) func_stripname 'lib' '.la' "$outputname" name=$func_stripname_result eval shared_ext=\"$shrext_cmds\" eval libname=\"$libname_spec\" ;; *) test "$module" = no && \ func_fatal_help "libtool library \`$output' must begin with \`lib'" if test "$need_lib_prefix" != no; then # Add the "lib" prefix for modules if required func_stripname '' '.la' "$outputname" name=$func_stripname_result eval shared_ext=\"$shrext_cmds\" eval libname=\"$libname_spec\" else func_stripname '' '.la' "$outputname" libname=$func_stripname_result fi ;; esac if test -n "$objs"; then if test "$deplibs_check_method" != pass_all; then func_fatal_error "cannot build libtool library \`$output' from non-libtool objects on this host:$objs" else echo $ECHO "*** Warning: Linking the shared library $output against the non-libtool" $ECHO "*** objects $objs is not portable!" func_append libobjs " $objs" fi fi test "$dlself" != no && \ func_warning "\`-dlopen self' is ignored for libtool libraries" set dummy $rpath shift test "$#" -gt 1 && \ func_warning "ignoring multiple \`-rpath's for a libtool library" install_libdir="$1" oldlibs= if test -z "$rpath"; then if test "$build_libtool_libs" = yes; then # Building a libtool convenience library. # Some compilers have problems with a `.al' extension so # convenience libraries should have the same extension an # archive normally would. oldlibs="$output_objdir/$libname.$libext $oldlibs" build_libtool_libs=convenience build_old_libs=yes fi test -n "$vinfo" && \ func_warning "\`-version-info/-version-number' is ignored for convenience libraries" test -n "$release" && \ func_warning "\`-release' is ignored for convenience libraries" else # Parse the version information argument. save_ifs="$IFS"; IFS=':' set dummy $vinfo 0 0 0 shift IFS="$save_ifs" test -n "$7" && \ func_fatal_help "too many parameters to \`-version-info'" # convert absolute version numbers to libtool ages # this retains compatibility with .la files and attempts # to make the code below a bit more comprehensible case $vinfo_number in yes) number_major="$1" number_minor="$2" number_revision="$3" # # There are really only two kinds -- those that # use the current revision as the major version # and those that subtract age and use age as # a minor version. But, then there is irix # which has an extra 1 added just for fun # case $version_type in darwin|linux|osf|windows|none) func_arith $number_major + $number_minor current=$func_arith_result age="$number_minor" revision="$number_revision" ;; freebsd-aout|freebsd-elf|qnx|sunos) current="$number_major" revision="$number_minor" age="0" ;; irix|nonstopux) func_arith $number_major + $number_minor current=$func_arith_result age="$number_minor" revision="$number_minor" lt_irix_increment=no ;; *) func_fatal_configuration "$modename: unknown library version type \`$version_type'" ;; esac ;; no) current="$1" revision="$2" age="$3" ;; esac # Check that each of the things are valid numbers. case $current in 0|[1-9]|[1-9][0-9]|[1-9][0-9][0-9]|[1-9][0-9][0-9][0-9]|[1-9][0-9][0-9][0-9][0-9]) ;; *) func_error "CURRENT \`$current' must be a nonnegative integer" func_fatal_error "\`$vinfo' is not valid version information" ;; esac case $revision in 0|[1-9]|[1-9][0-9]|[1-9][0-9][0-9]|[1-9][0-9][0-9][0-9]|[1-9][0-9][0-9][0-9][0-9]) ;; *) func_error "REVISION \`$revision' must be a nonnegative integer" func_fatal_error "\`$vinfo' is not valid version information" ;; esac case $age in 0|[1-9]|[1-9][0-9]|[1-9][0-9][0-9]|[1-9][0-9][0-9][0-9]|[1-9][0-9][0-9][0-9][0-9]) ;; *) func_error "AGE \`$age' must be a nonnegative integer" func_fatal_error "\`$vinfo' is not valid version information" ;; esac if test "$age" -gt "$current"; then func_error "AGE \`$age' is greater than the current interface number \`$current'" func_fatal_error "\`$vinfo' is not valid version information" fi # Calculate the version variables. major= versuffix= verstring= case $version_type in none) ;; darwin) # Like Linux, but with the current version available in # verstring for coding it into the library header func_arith $current - $age major=.$func_arith_result versuffix="$major.$age.$revision" # Darwin ld doesn't like 0 for these options... func_arith $current + 1 minor_current=$func_arith_result xlcverstring="${wl}-compatibility_version ${wl}$minor_current ${wl}-current_version ${wl}$minor_current.$revision" verstring="-compatibility_version $minor_current -current_version $minor_current.$revision" ;; freebsd-aout) major=".$current" versuffix=".$current.$revision"; ;; freebsd-elf) major=".$current" versuffix=".$current" ;; irix | nonstopux) if test "X$lt_irix_increment" = "Xno"; then func_arith $current - $age else func_arith $current - $age + 1 fi major=$func_arith_result case $version_type in nonstopux) verstring_prefix=nonstopux ;; *) verstring_prefix=sgi ;; esac verstring="$verstring_prefix$major.$revision" # Add in all the interfaces that we are compatible with. loop=$revision while test "$loop" -ne 0; do func_arith $revision - $loop iface=$func_arith_result func_arith $loop - 1 loop=$func_arith_result verstring="$verstring_prefix$major.$iface:$verstring" done # Before this point, $major must not contain `.'. major=.$major versuffix="$major.$revision" ;; linux) func_arith $current - $age major=.$func_arith_result versuffix="$major.$age.$revision" ;; osf) func_arith $current - $age major=.$func_arith_result versuffix=".$current.$age.$revision" verstring="$current.$age.$revision" # Add in all the interfaces that we are compatible with. loop=$age while test "$loop" -ne 0; do func_arith $current - $loop iface=$func_arith_result func_arith $loop - 1 loop=$func_arith_result verstring="$verstring:${iface}.0" done # Make executables depend on our current version. func_append verstring ":${current}.0" ;; qnx) major=".$current" versuffix=".$current" ;; sunos) major=".$current" versuffix=".$current.$revision" ;; windows) # Use '-' rather than '.', since we only want one # extension on DOS 8.3 filesystems. func_arith $current - $age major=$func_arith_result versuffix="-$major" ;; *) func_fatal_configuration "unknown library version type \`$version_type'" ;; esac # Clear the version info if we defaulted, and they specified a release. if test -z "$vinfo" && test -n "$release"; then major= case $version_type in darwin) # we can't check for "0.0" in archive_cmds due to quoting # problems, so we reset it completely verstring= ;; *) verstring="0.0" ;; esac if test "$need_version" = no; then versuffix= else versuffix=".0.0" fi fi # Remove version info from name if versioning should be avoided if test "$avoid_version" = yes && test "$need_version" = no; then major= versuffix= verstring="" fi # Check to see if the archive will have undefined symbols. if test "$allow_undefined" = yes; then if test "$allow_undefined_flag" = unsupported; then func_warning "undefined symbols not allowed in $host shared libraries" build_libtool_libs=no build_old_libs=yes fi else # Don't allow undefined symbols. allow_undefined_flag="$no_undefined_flag" fi fi func_generate_dlsyms "$libname" "$libname" "yes" func_append libobjs " $symfileobj" test "X$libobjs" = "X " && libobjs= if test "$opt_mode" != relink; then # Remove our outputs, but don't remove object files since they # may have been created when compiling PIC objects. removelist= tempremovelist=`$ECHO "$output_objdir/*"` for p in $tempremovelist; do case $p in *.$objext | *.gcno) ;; $output_objdir/$outputname | $output_objdir/$libname.* | $output_objdir/${libname}${release}.*) if test "X$precious_files_regex" != "X"; then if $ECHO "$p" | $EGREP -e "$precious_files_regex" >/dev/null 2>&1 then continue fi fi func_append removelist " $p" ;; *) ;; esac done test -n "$removelist" && \ func_show_eval "${RM}r \$removelist" fi # Now set the variables for building old libraries. if test "$build_old_libs" = yes && test "$build_libtool_libs" != convenience ; then func_append oldlibs " $output_objdir/$libname.$libext" # Transform .lo files to .o files. oldobjs="$objs "`$ECHO "$libobjs" | $SP2NL | $SED "/\.${libext}$/d; $lo2o" | $NL2SP` fi # Eliminate all temporary directories. #for path in $notinst_path; do # lib_search_path=`$ECHO "$lib_search_path " | $SED "s% $path % %g"` # deplibs=`$ECHO "$deplibs " | $SED "s% -L$path % %g"` # dependency_libs=`$ECHO "$dependency_libs " | $SED "s% -L$path % %g"` #done if test -n "$xrpath"; then # If the user specified any rpath flags, then add them. temp_xrpath= for libdir in $xrpath; do func_replace_sysroot "$libdir" func_append temp_xrpath " -R$func_replace_sysroot_result" case "$finalize_rpath " in *" $libdir "*) ;; *) func_append finalize_rpath " $libdir" ;; esac done if test "$hardcode_into_libs" != yes || test "$build_old_libs" = yes; then dependency_libs="$temp_xrpath $dependency_libs" fi fi # Make sure dlfiles contains only unique files that won't be dlpreopened old_dlfiles="$dlfiles" dlfiles= for lib in $old_dlfiles; do case " $dlprefiles $dlfiles " in *" $lib "*) ;; *) func_append dlfiles " $lib" ;; esac done # Make sure dlprefiles contains only unique files old_dlprefiles="$dlprefiles" dlprefiles= for lib in $old_dlprefiles; do case "$dlprefiles " in *" $lib "*) ;; *) func_append dlprefiles " $lib" ;; esac done if test "$build_libtool_libs" = yes; then if test -n "$rpath"; then case $host in *-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-os2* | *-*-beos* | *-cegcc* | *-*-haiku*) # these systems don't actually have a c library (as such)! ;; *-*-rhapsody* | *-*-darwin1.[012]) # Rhapsody C library is in the System framework func_append deplibs " System.ltframework" ;; *-*-netbsd*) # Don't link with libc until the a.out ld.so is fixed. ;; *-*-openbsd* | *-*-freebsd* | *-*-dragonfly*) # Do not include libc due to us having libc/libc_r. ;; *-*-sco3.2v5* | *-*-sco5v6*) # Causes problems with __ctype ;; *-*-sysv4.2uw2* | *-*-sysv5* | *-*-unixware* | *-*-OpenUNIX*) # Compiler inserts libc in the correct place for threads to work ;; *) # Add libc to deplibs on all other systems if necessary. if test "$build_libtool_need_lc" = "yes"; then func_append deplibs " -lc" fi ;; esac fi # Transform deplibs into only deplibs that can be linked in shared. name_save=$name libname_save=$libname release_save=$release versuffix_save=$versuffix major_save=$major # I'm not sure if I'm treating the release correctly. I think # release should show up in the -l (ie -lgmp5) so we don't want to # add it in twice. Is that correct? release="" versuffix="" major="" newdeplibs= droppeddeps=no case $deplibs_check_method in pass_all) # Don't check for shared/static. Everything works. # This might be a little naive. We might want to check # whether the library exists or not. But this is on # osf3 & osf4 and I'm not really sure... Just # implementing what was already the behavior. newdeplibs=$deplibs ;; test_compile) # This code stresses the "libraries are programs" paradigm to its # limits. Maybe even breaks it. We compile a program, linking it # against the deplibs as a proxy for the library. Then we can check # whether they linked in statically or dynamically with ldd. $opt_dry_run || $RM conftest.c cat > conftest.c </dev/null` $nocaseglob else potential_libs=`ls $i/$libnameglob[.-]* 2>/dev/null` fi for potent_lib in $potential_libs; do # Follow soft links. if ls -lLd "$potent_lib" 2>/dev/null | $GREP " -> " >/dev/null; then continue fi # The statement above tries to avoid entering an # endless loop below, in case of cyclic links. # We might still enter an endless loop, since a link # loop can be closed while we follow links, # but so what? potlib="$potent_lib" while test -h "$potlib" 2>/dev/null; do potliblink=`ls -ld $potlib | ${SED} 's/.* -> //'` case $potliblink in [\\/]* | [A-Za-z]:[\\/]*) potlib="$potliblink";; *) potlib=`$ECHO "$potlib" | $SED 's,[^/]*$,,'`"$potliblink";; esac done if eval $file_magic_cmd \"\$potlib\" 2>/dev/null | $SED -e 10q | $EGREP "$file_magic_regex" > /dev/null; then func_append newdeplibs " $a_deplib" a_deplib="" break 2 fi done done fi if test -n "$a_deplib" ; then droppeddeps=yes echo $ECHO "*** Warning: linker path does not have real file for library $a_deplib." echo "*** I have the capability to make that library automatically link in when" echo "*** you link to this library. But I can only do this if you have a" echo "*** shared version of the library, which you do not appear to have" echo "*** because I did check the linker path looking for a file starting" if test -z "$potlib" ; then $ECHO "*** with $libname but no candidates were found. (...for file magic test)" else $ECHO "*** with $libname and none of the candidates passed a file format test" $ECHO "*** using a file magic. Last file checked: $potlib" fi fi ;; *) # Add a -L argument. func_append newdeplibs " $a_deplib" ;; esac done # Gone through all deplibs. ;; match_pattern*) set dummy $deplibs_check_method; shift match_pattern_regex=`expr "$deplibs_check_method" : "$1 \(.*\)"` for a_deplib in $deplibs; do case $a_deplib in -l*) func_stripname -l '' "$a_deplib" name=$func_stripname_result if test "X$allow_libtool_libs_with_static_runtimes" = "Xyes" ; then case " $predeps $postdeps " in *" $a_deplib "*) func_append newdeplibs " $a_deplib" a_deplib="" ;; esac fi if test -n "$a_deplib" ; then libname=`eval "\\$ECHO \"$libname_spec\""` for i in $lib_search_path $sys_lib_search_path $shlib_search_path; do potential_libs=`ls $i/$libname[.-]* 2>/dev/null` for potent_lib in $potential_libs; do potlib="$potent_lib" # see symlink-check above in file_magic test if eval "\$ECHO \"$potent_lib\"" 2>/dev/null | $SED 10q | \ $EGREP "$match_pattern_regex" > /dev/null; then func_append newdeplibs " $a_deplib" a_deplib="" break 2 fi done done fi if test -n "$a_deplib" ; then droppeddeps=yes echo $ECHO "*** Warning: linker path does not have real file for library $a_deplib." echo "*** I have the capability to make that library automatically link in when" echo "*** you link to this library. But I can only do this if you have a" echo "*** shared version of the library, which you do not appear to have" echo "*** because I did check the linker path looking for a file starting" if test -z "$potlib" ; then $ECHO "*** with $libname but no candidates were found. (...for regex pattern test)" else $ECHO "*** with $libname and none of the candidates passed a file format test" $ECHO "*** using a regex pattern. Last file checked: $potlib" fi fi ;; *) # Add a -L argument. func_append newdeplibs " $a_deplib" ;; esac done # Gone through all deplibs. ;; none | unknown | *) newdeplibs="" tmp_deplibs=`$ECHO " $deplibs" | $SED 's/ -lc$//; s/ -[LR][^ ]*//g'` if test "X$allow_libtool_libs_with_static_runtimes" = "Xyes" ; then for i in $predeps $postdeps ; do # can't use Xsed below, because $i might contain '/' tmp_deplibs=`$ECHO " $tmp_deplibs" | $SED "s,$i,,"` done fi case $tmp_deplibs in *[!\ \ ]*) echo if test "X$deplibs_check_method" = "Xnone"; then echo "*** Warning: inter-library dependencies are not supported in this platform." else echo "*** Warning: inter-library dependencies are not known to be supported." fi echo "*** All declared inter-library dependencies are being dropped." droppeddeps=yes ;; esac ;; esac versuffix=$versuffix_save major=$major_save release=$release_save libname=$libname_save name=$name_save case $host in *-*-rhapsody* | *-*-darwin1.[012]) # On Rhapsody replace the C library with the System framework newdeplibs=`$ECHO " $newdeplibs" | $SED 's/ -lc / System.ltframework /'` ;; esac if test "$droppeddeps" = yes; then if test "$module" = yes; then echo echo "*** Warning: libtool could not satisfy all declared inter-library" $ECHO "*** dependencies of module $libname. Therefore, libtool will create" echo "*** a static module, that should work as long as the dlopening" echo "*** application is linked with the -dlopen flag." if test -z "$global_symbol_pipe"; then echo echo "*** However, this would only work if libtool was able to extract symbol" echo "*** lists from a program, using \`nm' or equivalent, but libtool could" echo "*** not find such a program. So, this module is probably useless." echo "*** \`nm' from GNU binutils and a full rebuild may help." fi if test "$build_old_libs" = no; then oldlibs="$output_objdir/$libname.$libext" build_libtool_libs=module build_old_libs=yes else build_libtool_libs=no fi else echo "*** The inter-library dependencies that have been dropped here will be" echo "*** automatically added whenever a program is linked with this library" echo "*** or is declared to -dlopen it." if test "$allow_undefined" = no; then echo echo "*** Since this library must not contain undefined symbols," echo "*** because either the platform does not support them or" echo "*** it was explicitly requested with -no-undefined," echo "*** libtool will only create a static version of it." if test "$build_old_libs" = no; then oldlibs="$output_objdir/$libname.$libext" build_libtool_libs=module build_old_libs=yes else build_libtool_libs=no fi fi fi fi # Done checking deplibs! deplibs=$newdeplibs fi # Time to change all our "foo.ltframework" stuff back to "-framework foo" case $host in *-*-darwin*) newdeplibs=`$ECHO " $newdeplibs" | $SED 's% \([^ $]*\).ltframework% -framework \1%g'` new_inherited_linker_flags=`$ECHO " $new_inherited_linker_flags" | $SED 's% \([^ $]*\).ltframework% -framework \1%g'` deplibs=`$ECHO " $deplibs" | $SED 's% \([^ $]*\).ltframework% -framework \1%g'` ;; esac # move library search paths that coincide with paths to not yet # installed libraries to the beginning of the library search list new_libs= for path in $notinst_path; do case " $new_libs " in *" -L$path/$objdir "*) ;; *) case " $deplibs " in *" -L$path/$objdir "*) func_append new_libs " -L$path/$objdir" ;; esac ;; esac done for deplib in $deplibs; do case $deplib in -L*) case " $new_libs " in *" $deplib "*) ;; *) func_append new_libs " $deplib" ;; esac ;; *) func_append new_libs " $deplib" ;; esac done deplibs="$new_libs" # All the library-specific variables (install_libdir is set above). library_names= old_library= dlname= # Test again, we may have decided not to build it any more if test "$build_libtool_libs" = yes; then if test "$hardcode_into_libs" = yes; then # Hardcode the library paths hardcode_libdirs= dep_rpath= rpath="$finalize_rpath" test "$opt_mode" != relink && rpath="$compile_rpath$rpath" for libdir in $rpath; do if test -n "$hardcode_libdir_flag_spec"; then if test -n "$hardcode_libdir_separator"; then func_replace_sysroot "$libdir" libdir=$func_replace_sysroot_result if test -z "$hardcode_libdirs"; then hardcode_libdirs="$libdir" else # Just accumulate the unique libdirs. case $hardcode_libdir_separator$hardcode_libdirs$hardcode_libdir_separator in *"$hardcode_libdir_separator$libdir$hardcode_libdir_separator"*) ;; *) func_append hardcode_libdirs "$hardcode_libdir_separator$libdir" ;; esac fi else eval flag=\"$hardcode_libdir_flag_spec\" func_append dep_rpath " $flag" fi elif test -n "$runpath_var"; then case "$perm_rpath " in *" $libdir "*) ;; *) func_apped perm_rpath " $libdir" ;; esac fi done # Substitute the hardcoded libdirs into the rpath. if test -n "$hardcode_libdir_separator" && test -n "$hardcode_libdirs"; then libdir="$hardcode_libdirs" if test -n "$hardcode_libdir_flag_spec_ld"; then eval dep_rpath=\"$hardcode_libdir_flag_spec_ld\" else eval dep_rpath=\"$hardcode_libdir_flag_spec\" fi fi if test -n "$runpath_var" && test -n "$perm_rpath"; then # We should set the runpath_var. rpath= for dir in $perm_rpath; do func_append rpath "$dir:" done eval "$runpath_var='$rpath\$$runpath_var'; export $runpath_var" fi test -n "$dep_rpath" && deplibs="$dep_rpath $deplibs" fi shlibpath="$finalize_shlibpath" test "$opt_mode" != relink && shlibpath="$compile_shlibpath$shlibpath" if test -n "$shlibpath"; then eval "$shlibpath_var='$shlibpath\$$shlibpath_var'; export $shlibpath_var" fi # Get the real and link names of the library. eval shared_ext=\"$shrext_cmds\" eval library_names=\"$library_names_spec\" set dummy $library_names shift realname="$1" shift if test -n "$soname_spec"; then eval soname=\"$soname_spec\" else soname="$realname" fi if test -z "$dlname"; then dlname=$soname fi lib="$output_objdir/$realname" linknames= for link do func_append linknames " $link" done # Use standard objects if they are pic test -z "$pic_flag" && libobjs=`$ECHO "$libobjs" | $SP2NL | $SED "$lo2o" | $NL2SP` test "X$libobjs" = "X " && libobjs= delfiles= if test -n "$export_symbols" && test -n "$include_expsyms"; then $opt_dry_run || cp "$export_symbols" "$output_objdir/$libname.uexp" export_symbols="$output_objdir/$libname.uexp" func_append delfiles " $export_symbols" fi orig_export_symbols= case $host_os in cygwin* | mingw* | cegcc*) if test -n "$export_symbols" && test -z "$export_symbols_regex"; then # exporting using user supplied symfile if test "x`$SED 1q $export_symbols`" != xEXPORTS; then # and it's NOT already a .def file. Must figure out # which of the given symbols are data symbols and tag # them as such. So, trigger use of export_symbols_cmds. # export_symbols gets reassigned inside the "prepare # the list of exported symbols" if statement, so the # include_expsyms logic still works. orig_export_symbols="$export_symbols" export_symbols= always_export_symbols=yes fi fi ;; esac # Prepare the list of exported symbols if test -z "$export_symbols"; then if test "$always_export_symbols" = yes || test -n "$export_symbols_regex"; then func_verbose "generating symbol list for \`$libname.la'" export_symbols="$output_objdir/$libname.exp" $opt_dry_run || $RM $export_symbols cmds=$export_symbols_cmds save_ifs="$IFS"; IFS='~' for cmd1 in $cmds; do IFS="$save_ifs" # Take the normal branch if the nm_file_list_spec branch # doesn't work or if tool conversion is not needed. case $nm_file_list_spec~$to_tool_file_cmd in *~func_convert_file_noop | *~func_convert_file_msys_to_w32 | ~*) try_normal_branch=yes eval cmd=\"$cmd1\" func_len " $cmd" len=$func_len_result ;; *) try_normal_branch=no ;; esac if test "$try_normal_branch" = yes \ && { test "$len" -lt "$max_cmd_len" \ || test "$max_cmd_len" -le -1; } then func_show_eval "$cmd" 'exit $?' skipped_export=false elif test -n "$nm_file_list_spec"; then func_basename "$output" output_la=$func_basename_result save_libobjs=$libobjs save_output=$output output=${output_objdir}/${output_la}.nm func_to_tool_file "$output" libobjs=$nm_file_list_spec$func_to_tool_file_result func_append delfiles " $output" func_verbose "creating $NM input file list: $output" for obj in $save_libobjs; do func_to_tool_file "$obj" $ECHO "$func_to_tool_file_result" done > "$output" eval cmd=\"$cmd1\" func_show_eval "$cmd" 'exit $?' output=$save_output libobjs=$save_libobjs skipped_export=false else # The command line is too long to execute in one step. func_verbose "using reloadable object file for export list..." skipped_export=: # Break out early, otherwise skipped_export may be # set to false by a later but shorter cmd. break fi done IFS="$save_ifs" if test -n "$export_symbols_regex" && test "X$skipped_export" != "X:"; then func_show_eval '$EGREP -e "$export_symbols_regex" "$export_symbols" > "${export_symbols}T"' func_show_eval '$MV "${export_symbols}T" "$export_symbols"' fi fi fi if test -n "$export_symbols" && test -n "$include_expsyms"; then tmp_export_symbols="$export_symbols" test -n "$orig_export_symbols" && tmp_export_symbols="$orig_export_symbols" $opt_dry_run || eval '$ECHO "$include_expsyms" | $SP2NL >> "$tmp_export_symbols"' fi if test "X$skipped_export" != "X:" && test -n "$orig_export_symbols"; then # The given exports_symbols file has to be filtered, so filter it. func_verbose "filter symbol list for \`$libname.la' to tag DATA exports" # FIXME: $output_objdir/$libname.filter potentially contains lots of # 's' commands which not all seds can handle. GNU sed should be fine # though. Also, the filter scales superlinearly with the number of # global variables. join(1) would be nice here, but unfortunately # isn't a blessed tool. $opt_dry_run || $SED -e '/[ ,]DATA/!d;s,\(.*\)\([ \,].*\),s|^\1$|\1\2|,' < $export_symbols > $output_objdir/$libname.filter func_append delfiles " $export_symbols $output_objdir/$libname.filter" export_symbols=$output_objdir/$libname.def $opt_dry_run || $SED -f $output_objdir/$libname.filter < $orig_export_symbols > $export_symbols fi tmp_deplibs= for test_deplib in $deplibs; do case " $convenience " in *" $test_deplib "*) ;; *) func_append tmp_deplibs " $test_deplib" ;; esac done deplibs="$tmp_deplibs" if test -n "$convenience"; then if test -n "$whole_archive_flag_spec" && test "$compiler_needs_object" = yes && test -z "$libobjs"; then # extract the archives, so we have objects to list. # TODO: could optimize this to just extract one archive. whole_archive_flag_spec= fi if test -n "$whole_archive_flag_spec"; then save_libobjs=$libobjs eval libobjs=\"\$libobjs $whole_archive_flag_spec\" test "X$libobjs" = "X " && libobjs= else gentop="$output_objdir/${outputname}x" func_append generated " $gentop" func_extract_archives $gentop $convenience func_append libobjs " $func_extract_archives_result" test "X$libobjs" = "X " && libobjs= fi fi if test "$thread_safe" = yes && test -n "$thread_safe_flag_spec"; then eval flag=\"$thread_safe_flag_spec\" func_append linker_flags " $flag" fi # Make a backup of the uninstalled library when relinking if test "$opt_mode" = relink; then $opt_dry_run || eval '(cd $output_objdir && $RM ${realname}U && $MV $realname ${realname}U)' || exit $? fi # Do each of the archive commands. if test "$module" = yes && test -n "$module_cmds" ; then if test -n "$export_symbols" && test -n "$module_expsym_cmds"; then eval test_cmds=\"$module_expsym_cmds\" cmds=$module_expsym_cmds else eval test_cmds=\"$module_cmds\" cmds=$module_cmds fi else if test -n "$export_symbols" && test -n "$archive_expsym_cmds"; then eval test_cmds=\"$archive_expsym_cmds\" cmds=$archive_expsym_cmds else eval test_cmds=\"$archive_cmds\" cmds=$archive_cmds fi fi if test "X$skipped_export" != "X:" && func_len " $test_cmds" && len=$func_len_result && test "$len" -lt "$max_cmd_len" || test "$max_cmd_len" -le -1; then : else # The command line is too long to link in one step, link piecewise # or, if using GNU ld and skipped_export is not :, use a linker # script. # Save the value of $output and $libobjs because we want to # use them later. If we have whole_archive_flag_spec, we # want to use save_libobjs as it was before # whole_archive_flag_spec was expanded, because we can't # assume the linker understands whole_archive_flag_spec. # This may have to be revisited, in case too many # convenience libraries get linked in and end up exceeding # the spec. if test -z "$convenience" || test -z "$whole_archive_flag_spec"; then save_libobjs=$libobjs fi save_output=$output func_basename "$output" output_la=$func_basename_result # Clear the reloadable object creation command queue and # initialize k to one. test_cmds= concat_cmds= objlist= last_robj= k=1 if test -n "$save_libobjs" && test "X$skipped_export" != "X:" && test "$with_gnu_ld" = yes; then output=${output_objdir}/${output_la}.lnkscript func_verbose "creating GNU ld script: $output" echo 'INPUT (' > $output for obj in $save_libobjs do func_to_tool_file "$obj" $ECHO "$func_to_tool_file_result" >> $output done echo ')' >> $output func_append delfiles " $output" func_to_tool_file "$output" output=$func_to_tool_file_result elif test -n "$save_libobjs" && test "X$skipped_export" != "X:" && test "X$file_list_spec" != X; then output=${output_objdir}/${output_la}.lnk func_verbose "creating linker input file list: $output" : > $output set x $save_libobjs shift firstobj= if test "$compiler_needs_object" = yes; then firstobj="$1 " shift fi for obj do func_to_tool_file "$obj" $ECHO "$func_to_tool_file_result" >> $output done func_append delfiles " $output" func_to_tool_file "$output" output=$firstobj\"$file_list_spec$func_to_tool_file_result\" else if test -n "$save_libobjs"; then func_verbose "creating reloadable object files..." output=$output_objdir/$output_la-${k}.$objext eval test_cmds=\"$reload_cmds\" func_len " $test_cmds" len0=$func_len_result len=$len0 # Loop over the list of objects to be linked. for obj in $save_libobjs do func_len " $obj" func_arith $len + $func_len_result len=$func_arith_result if test "X$objlist" = X || test "$len" -lt "$max_cmd_len"; then func_append objlist " $obj" else # The command $test_cmds is almost too long, add a # command to the queue. if test "$k" -eq 1 ; then # The first file doesn't have a previous command to add. reload_objs=$objlist eval concat_cmds=\"$reload_cmds\" else # All subsequent reloadable object files will link in # the last one created. reload_objs="$objlist $last_robj" eval concat_cmds=\"\$concat_cmds~$reload_cmds~\$RM $last_robj\" fi last_robj=$output_objdir/$output_la-${k}.$objext func_arith $k + 1 k=$func_arith_result output=$output_objdir/$output_la-${k}.$objext objlist=" $obj" func_len " $last_robj" func_arith $len0 + $func_len_result len=$func_arith_result fi done # Handle the remaining objects by creating one last # reloadable object file. All subsequent reloadable object # files will link in the last one created. test -z "$concat_cmds" || concat_cmds=$concat_cmds~ reload_objs="$objlist $last_robj" eval concat_cmds=\"\${concat_cmds}$reload_cmds\" if test -n "$last_robj"; then eval concat_cmds=\"\${concat_cmds}~\$RM $last_robj\" fi func_append delfiles " $output" else output= fi if ${skipped_export-false}; then func_verbose "generating symbol list for \`$libname.la'" export_symbols="$output_objdir/$libname.exp" $opt_dry_run || $RM $export_symbols libobjs=$output # Append the command to create the export file. test -z "$concat_cmds" || concat_cmds=$concat_cmds~ eval concat_cmds=\"\$concat_cmds$export_symbols_cmds\" if test -n "$last_robj"; then eval concat_cmds=\"\$concat_cmds~\$RM $last_robj\" fi fi test -n "$save_libobjs" && func_verbose "creating a temporary reloadable object file: $output" # Loop through the commands generated above and execute them. save_ifs="$IFS"; IFS='~' for cmd in $concat_cmds; do IFS="$save_ifs" $opt_silent || { func_quote_for_expand "$cmd" eval "func_echo $func_quote_for_expand_result" } $opt_dry_run || eval "$cmd" || { lt_exit=$? # Restore the uninstalled library and exit if test "$opt_mode" = relink; then ( cd "$output_objdir" && \ $RM "${realname}T" && \ $MV "${realname}U" "$realname" ) fi exit $lt_exit } done IFS="$save_ifs" if test -n "$export_symbols_regex" && ${skipped_export-false}; then func_show_eval '$EGREP -e "$export_symbols_regex" "$export_symbols" > "${export_symbols}T"' func_show_eval '$MV "${export_symbols}T" "$export_symbols"' fi fi if ${skipped_export-false}; then if test -n "$export_symbols" && test -n "$include_expsyms"; then tmp_export_symbols="$export_symbols" test -n "$orig_export_symbols" && tmp_export_symbols="$orig_export_symbols" $opt_dry_run || eval '$ECHO "$include_expsyms" | $SP2NL >> "$tmp_export_symbols"' fi if test -n "$orig_export_symbols"; then # The given exports_symbols file has to be filtered, so filter it. func_verbose "filter symbol list for \`$libname.la' to tag DATA exports" # FIXME: $output_objdir/$libname.filter potentially contains lots of # 's' commands which not all seds can handle. GNU sed should be fine # though. Also, the filter scales superlinearly with the number of # global variables. join(1) would be nice here, but unfortunately # isn't a blessed tool. $opt_dry_run || $SED -e '/[ ,]DATA/!d;s,\(.*\)\([ \,].*\),s|^\1$|\1\2|,' < $export_symbols > $output_objdir/$libname.filter func_append delfiles " $export_symbols $output_objdir/$libname.filter" export_symbols=$output_objdir/$libname.def $opt_dry_run || $SED -f $output_objdir/$libname.filter < $orig_export_symbols > $export_symbols fi fi libobjs=$output # Restore the value of output. output=$save_output if test -n "$convenience" && test -n "$whole_archive_flag_spec"; then eval libobjs=\"\$libobjs $whole_archive_flag_spec\" test "X$libobjs" = "X " && libobjs= fi # Expand the library linking commands again to reset the # value of $libobjs for piecewise linking. # Do each of the archive commands. if test "$module" = yes && test -n "$module_cmds" ; then if test -n "$export_symbols" && test -n "$module_expsym_cmds"; then cmds=$module_expsym_cmds else cmds=$module_cmds fi else if test -n "$export_symbols" && test -n "$archive_expsym_cmds"; then cmds=$archive_expsym_cmds else cmds=$archive_cmds fi fi fi if test -n "$delfiles"; then # Append the command to remove temporary files to $cmds. eval cmds=\"\$cmds~\$RM $delfiles\" fi # Add any objects from preloaded convenience libraries if test -n "$dlprefiles"; then gentop="$output_objdir/${outputname}x" func_append generated " $gentop" func_extract_archives $gentop $dlprefiles func_append libobjs " $func_extract_archives_result" test "X$libobjs" = "X " && libobjs= fi save_ifs="$IFS"; IFS='~' for cmd in $cmds; do IFS="$save_ifs" eval cmd=\"$cmd\" $opt_silent || { func_quote_for_expand "$cmd" eval "func_echo $func_quote_for_expand_result" } $opt_dry_run || eval "$cmd" || { lt_exit=$? # Restore the uninstalled library and exit if test "$opt_mode" = relink; then ( cd "$output_objdir" && \ $RM "${realname}T" && \ $MV "${realname}U" "$realname" ) fi exit $lt_exit } done IFS="$save_ifs" # Restore the uninstalled library and exit if test "$opt_mode" = relink; then $opt_dry_run || eval '(cd $output_objdir && $RM ${realname}T && $MV $realname ${realname}T && $MV ${realname}U $realname)' || exit $? if test -n "$convenience"; then if test -z "$whole_archive_flag_spec"; then func_show_eval '${RM}r "$gentop"' fi fi exit $EXIT_SUCCESS fi # Create links to the real library. for linkname in $linknames; do if test "$realname" != "$linkname"; then func_show_eval '(cd "$output_objdir" && $RM "$linkname" && $LN_S "$realname" "$linkname")' 'exit $?' fi done # If -module or -export-dynamic was specified, set the dlname. if test "$module" = yes || test "$export_dynamic" = yes; then # On all known operating systems, these are identical. dlname="$soname" fi fi ;; obj) if test -n "$dlfiles$dlprefiles" || test "$dlself" != no; then func_warning "\`-dlopen' is ignored for objects" fi case " $deplibs" in *\ -l* | *\ -L*) func_warning "\`-l' and \`-L' are ignored for objects" ;; esac test -n "$rpath" && \ func_warning "\`-rpath' is ignored for objects" test -n "$xrpath" && \ func_warning "\`-R' is ignored for objects" test -n "$vinfo" && \ func_warning "\`-version-info' is ignored for objects" test -n "$release" && \ func_warning "\`-release' is ignored for objects" case $output in *.lo) test -n "$objs$old_deplibs" && \ func_fatal_error "cannot build library object \`$output' from non-libtool objects" libobj=$output func_lo2o "$libobj" obj=$func_lo2o_result ;; *) libobj= obj="$output" ;; esac # Delete the old objects. $opt_dry_run || $RM $obj $libobj # Objects from convenience libraries. This assumes # single-version convenience libraries. Whenever we create # different ones for PIC/non-PIC, this we'll have to duplicate # the extraction. reload_conv_objs= gentop= # reload_cmds runs $LD directly, so let us get rid of # -Wl from whole_archive_flag_spec and hope we can get by with # turning comma into space.. wl= if test -n "$convenience"; then if test -n "$whole_archive_flag_spec"; then eval tmp_whole_archive_flags=\"$whole_archive_flag_spec\" reload_conv_objs=$reload_objs\ `$ECHO "$tmp_whole_archive_flags" | $SED 's|,| |g'` else gentop="$output_objdir/${obj}x" func_append generated " $gentop" func_extract_archives $gentop $convenience reload_conv_objs="$reload_objs $func_extract_archives_result" fi fi # If we're not building shared, we need to use non_pic_objs test "$build_libtool_libs" != yes && libobjs="$non_pic_objects" # Create the old-style object. reload_objs="$objs$old_deplibs "`$ECHO "$libobjs" | $SP2NL | $SED "/\.${libext}$/d; /\.lib$/d; $lo2o" | $NL2SP`" $reload_conv_objs" ### testsuite: skip nested quoting test output="$obj" func_execute_cmds "$reload_cmds" 'exit $?' # Exit if we aren't doing a library object file. if test -z "$libobj"; then if test -n "$gentop"; then func_show_eval '${RM}r "$gentop"' fi exit $EXIT_SUCCESS fi if test "$build_libtool_libs" != yes; then if test -n "$gentop"; then func_show_eval '${RM}r "$gentop"' fi # Create an invalid libtool object if no PIC, so that we don't # accidentally link it into a program. # $show "echo timestamp > $libobj" # $opt_dry_run || eval "echo timestamp > $libobj" || exit $? exit $EXIT_SUCCESS fi if test -n "$pic_flag" || test "$pic_mode" != default; then # Only do commands if we really have different PIC objects. reload_objs="$libobjs $reload_conv_objs" output="$libobj" func_execute_cmds "$reload_cmds" 'exit $?' fi if test -n "$gentop"; then func_show_eval '${RM}r "$gentop"' fi exit $EXIT_SUCCESS ;; prog) case $host in *cygwin*) func_stripname '' '.exe' "$output" output=$func_stripname_result.exe;; esac test -n "$vinfo" && \ func_warning "\`-version-info' is ignored for programs" test -n "$release" && \ func_warning "\`-release' is ignored for programs" test "$preload" = yes \ && test "$dlopen_support" = unknown \ && test "$dlopen_self" = unknown \ && test "$dlopen_self_static" = unknown && \ func_warning "\`LT_INIT([dlopen])' not used. Assuming no dlopen support." case $host in *-*-rhapsody* | *-*-darwin1.[012]) # On Rhapsody replace the C library is the System framework compile_deplibs=`$ECHO " $compile_deplibs" | $SED 's/ -lc / System.ltframework /'` finalize_deplibs=`$ECHO " $finalize_deplibs" | $SED 's/ -lc / System.ltframework /'` ;; esac case $host in *-*-darwin*) # Don't allow lazy linking, it breaks C++ global constructors # But is supposedly fixed on 10.4 or later (yay!). if test "$tagname" = CXX ; then case ${MACOSX_DEPLOYMENT_TARGET-10.0} in 10.[0123]) func_append compile_command " ${wl}-bind_at_load" func_append finalize_command " ${wl}-bind_at_load" ;; esac fi # Time to change all our "foo.ltframework" stuff back to "-framework foo" compile_deplibs=`$ECHO " $compile_deplibs" | $SED 's% \([^ $]*\).ltframework% -framework \1%g'` finalize_deplibs=`$ECHO " $finalize_deplibs" | $SED 's% \([^ $]*\).ltframework% -framework \1%g'` ;; esac # move library search paths that coincide with paths to not yet # installed libraries to the beginning of the library search list new_libs= for path in $notinst_path; do case " $new_libs " in *" -L$path/$objdir "*) ;; *) case " $compile_deplibs " in *" -L$path/$objdir "*) func_append new_libs " -L$path/$objdir" ;; esac ;; esac done for deplib in $compile_deplibs; do case $deplib in -L*) case " $new_libs " in *" $deplib "*) ;; *) func_append new_libs " $deplib" ;; esac ;; *) func_append new_libs " $deplib" ;; esac done compile_deplibs="$new_libs" func_append compile_command " $compile_deplibs" func_append finalize_command " $finalize_deplibs" if test -n "$rpath$xrpath"; then # If the user specified any rpath flags, then add them. for libdir in $rpath $xrpath; do # This is the magic to use -rpath. case "$finalize_rpath " in *" $libdir "*) ;; *) func_append finalize_rpath " $libdir" ;; esac done fi # Now hardcode the library paths rpath= hardcode_libdirs= for libdir in $compile_rpath $finalize_rpath; do if test -n "$hardcode_libdir_flag_spec"; then if test -n "$hardcode_libdir_separator"; then if test -z "$hardcode_libdirs"; then hardcode_libdirs="$libdir" else # Just accumulate the unique libdirs. case $hardcode_libdir_separator$hardcode_libdirs$hardcode_libdir_separator in *"$hardcode_libdir_separator$libdir$hardcode_libdir_separator"*) ;; *) func_append hardcode_libdirs "$hardcode_libdir_separator$libdir" ;; esac fi else eval flag=\"$hardcode_libdir_flag_spec\" func_append rpath " $flag" fi elif test -n "$runpath_var"; then case "$perm_rpath " in *" $libdir "*) ;; *) func_append perm_rpath " $libdir" ;; esac fi case $host in *-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-os2* | *-cegcc*) testbindir=`${ECHO} "$libdir" | ${SED} -e 's*/lib$*/bin*'` case :$dllsearchpath: in *":$libdir:"*) ;; ::) dllsearchpath=$libdir;; *) func_append dllsearchpath ":$libdir";; esac case :$dllsearchpath: in *":$testbindir:"*) ;; ::) dllsearchpath=$testbindir;; *) func_append dllsearchpath ":$testbindir";; esac ;; esac done # Substitute the hardcoded libdirs into the rpath. if test -n "$hardcode_libdir_separator" && test -n "$hardcode_libdirs"; then libdir="$hardcode_libdirs" eval rpath=\" $hardcode_libdir_flag_spec\" fi compile_rpath="$rpath" rpath= hardcode_libdirs= for libdir in $finalize_rpath; do if test -n "$hardcode_libdir_flag_spec"; then if test -n "$hardcode_libdir_separator"; then if test -z "$hardcode_libdirs"; then hardcode_libdirs="$libdir" else # Just accumulate the unique libdirs. case $hardcode_libdir_separator$hardcode_libdirs$hardcode_libdir_separator in *"$hardcode_libdir_separator$libdir$hardcode_libdir_separator"*) ;; *) func_append hardcode_libdirs "$hardcode_libdir_separator$libdir" ;; esac fi else eval flag=\"$hardcode_libdir_flag_spec\" func_append rpath " $flag" fi elif test -n "$runpath_var"; then case "$finalize_perm_rpath " in *" $libdir "*) ;; *) func_append finalize_perm_rpath " $libdir" ;; esac fi done # Substitute the hardcoded libdirs into the rpath. if test -n "$hardcode_libdir_separator" && test -n "$hardcode_libdirs"; then libdir="$hardcode_libdirs" eval rpath=\" $hardcode_libdir_flag_spec\" fi finalize_rpath="$rpath" if test -n "$libobjs" && test "$build_old_libs" = yes; then # Transform all the library objects into standard objects. compile_command=`$ECHO "$compile_command" | $SP2NL | $SED "$lo2o" | $NL2SP` finalize_command=`$ECHO "$finalize_command" | $SP2NL | $SED "$lo2o" | $NL2SP` fi func_generate_dlsyms "$outputname" "@PROGRAM@" "no" # template prelinking step if test -n "$prelink_cmds"; then func_execute_cmds "$prelink_cmds" 'exit $?' fi wrappers_required=yes case $host in *cegcc* | *mingw32ce*) # Disable wrappers for cegcc and mingw32ce hosts, we are cross compiling anyway. wrappers_required=no ;; *cygwin* | *mingw* ) if test "$build_libtool_libs" != yes; then wrappers_required=no fi ;; *) if test "$need_relink" = no || test "$build_libtool_libs" != yes; then wrappers_required=no fi ;; esac if test "$wrappers_required" = no; then # Replace the output file specification. compile_command=`$ECHO "$compile_command" | $SED 's%@OUTPUT@%'"$output"'%g'` link_command="$compile_command$compile_rpath" # We have no uninstalled library dependencies, so finalize right now. exit_status=0 func_show_eval "$link_command" 'exit_status=$?' if test -n "$postlink_cmds"; then func_to_tool_file "$output" postlink_cmds=`func_echo_all "$postlink_cmds" | $SED -e 's%@OUTPUT@%'"$output"'%g' -e 's%@TOOL_OUTPUT@%'"$func_to_tool_file_result"'%g'` func_execute_cmds "$postlink_cmds" 'exit $?' fi # Delete the generated files. if test -f "$output_objdir/${outputname}S.${objext}"; then func_show_eval '$RM "$output_objdir/${outputname}S.${objext}"' fi exit $exit_status fi if test -n "$compile_shlibpath$finalize_shlibpath"; then compile_command="$shlibpath_var=\"$compile_shlibpath$finalize_shlibpath\$$shlibpath_var\" $compile_command" fi if test -n "$finalize_shlibpath"; then finalize_command="$shlibpath_var=\"$finalize_shlibpath\$$shlibpath_var\" $finalize_command" fi compile_var= finalize_var= if test -n "$runpath_var"; then if test -n "$perm_rpath"; then # We should set the runpath_var. rpath= for dir in $perm_rpath; do func_append rpath "$dir:" done compile_var="$runpath_var=\"$rpath\$$runpath_var\" " fi if test -n "$finalize_perm_rpath"; then # We should set the runpath_var. rpath= for dir in $finalize_perm_rpath; do func_append rpath "$dir:" done finalize_var="$runpath_var=\"$rpath\$$runpath_var\" " fi fi if test "$no_install" = yes; then # We don't need to create a wrapper script. link_command="$compile_var$compile_command$compile_rpath" # Replace the output file specification. link_command=`$ECHO "$link_command" | $SED 's%@OUTPUT@%'"$output"'%g'` # Delete the old output file. $opt_dry_run || $RM $output # Link the executable and exit func_show_eval "$link_command" 'exit $?' if test -n "$postlink_cmds"; then func_to_tool_file "$output" postlink_cmds=`func_echo_all "$postlink_cmds" | $SED -e 's%@OUTPUT@%'"$output"'%g' -e 's%@TOOL_OUTPUT@%'"$func_to_tool_file_result"'%g'` func_execute_cmds "$postlink_cmds" 'exit $?' fi exit $EXIT_SUCCESS fi if test "$hardcode_action" = relink; then # Fast installation is not supported link_command="$compile_var$compile_command$compile_rpath" relink_command="$finalize_var$finalize_command$finalize_rpath" func_warning "this platform does not like uninstalled shared libraries" func_warning "\`$output' will be relinked during installation" else if test "$fast_install" != no; then link_command="$finalize_var$compile_command$finalize_rpath" if test "$fast_install" = yes; then relink_command=`$ECHO "$compile_var$compile_command$compile_rpath" | $SED 's%@OUTPUT@%\$progdir/\$file%g'` else # fast_install is set to needless relink_command= fi else link_command="$compile_var$compile_command$compile_rpath" relink_command="$finalize_var$finalize_command$finalize_rpath" fi fi # Replace the output file specification. link_command=`$ECHO "$link_command" | $SED 's%@OUTPUT@%'"$output_objdir/$outputname"'%g'` # Delete the old output files. $opt_dry_run || $RM $output $output_objdir/$outputname $output_objdir/lt-$outputname func_show_eval "$link_command" 'exit $?' if test -n "$postlink_cmds"; then func_to_tool_file "$output_objdir/$outputname" postlink_cmds=`func_echo_all "$postlink_cmds" | $SED -e 's%@OUTPUT@%'"$output_objdir/$outputname"'%g' -e 's%@TOOL_OUTPUT@%'"$func_to_tool_file_result"'%g'` func_execute_cmds "$postlink_cmds" 'exit $?' fi # Now create the wrapper script. func_verbose "creating $output" # Quote the relink command for shipping. if test -n "$relink_command"; then # Preserve any variables that may affect compiler behavior for var in $variables_saved_for_relink; do if eval test -z \"\${$var+set}\"; then relink_command="{ test -z \"\${$var+set}\" || $lt_unset $var || { $var=; export $var; }; }; $relink_command" elif eval var_value=\$$var; test -z "$var_value"; then relink_command="$var=; export $var; $relink_command" else func_quote_for_eval "$var_value" relink_command="$var=$func_quote_for_eval_result; export $var; $relink_command" fi done relink_command="(cd `pwd`; $relink_command)" relink_command=`$ECHO "$relink_command" | $SED "$sed_quote_subst"` fi # Only actually do things if not in dry run mode. $opt_dry_run || { # win32 will think the script is a binary if it has # a .exe suffix, so we strip it off here. case $output in *.exe) func_stripname '' '.exe' "$output" output=$func_stripname_result ;; esac # test for cygwin because mv fails w/o .exe extensions case $host in *cygwin*) exeext=.exe func_stripname '' '.exe' "$outputname" outputname=$func_stripname_result ;; *) exeext= ;; esac case $host in *cygwin* | *mingw* ) func_dirname_and_basename "$output" "" "." output_name=$func_basename_result output_path=$func_dirname_result cwrappersource="$output_path/$objdir/lt-$output_name.c" cwrapper="$output_path/$output_name.exe" $RM $cwrappersource $cwrapper trap "$RM $cwrappersource $cwrapper; exit $EXIT_FAILURE" 1 2 15 func_emit_cwrapperexe_src > $cwrappersource # The wrapper executable is built using the $host compiler, # because it contains $host paths and files. If cross- # compiling, it, like the target executable, must be # executed on the $host or under an emulation environment. $opt_dry_run || { $LTCC $LTCFLAGS -o $cwrapper $cwrappersource $STRIP $cwrapper } # Now, create the wrapper script for func_source use: func_ltwrapper_scriptname $cwrapper $RM $func_ltwrapper_scriptname_result trap "$RM $func_ltwrapper_scriptname_result; exit $EXIT_FAILURE" 1 2 15 $opt_dry_run || { # note: this script will not be executed, so do not chmod. if test "x$build" = "x$host" ; then $cwrapper --lt-dump-script > $func_ltwrapper_scriptname_result else func_emit_wrapper no > $func_ltwrapper_scriptname_result fi } ;; * ) $RM $output trap "$RM $output; exit $EXIT_FAILURE" 1 2 15 func_emit_wrapper no > $output chmod +x $output ;; esac } exit $EXIT_SUCCESS ;; esac # See if we need to build an old-fashioned archive. for oldlib in $oldlibs; do if test "$build_libtool_libs" = convenience; then oldobjs="$libobjs_save $symfileobj" addlibs="$convenience" build_libtool_libs=no else if test "$build_libtool_libs" = module; then oldobjs="$libobjs_save" build_libtool_libs=no else oldobjs="$old_deplibs $non_pic_objects" if test "$preload" = yes && test -f "$symfileobj"; then func_append oldobjs " $symfileobj" fi fi addlibs="$old_convenience" fi if test -n "$addlibs"; then gentop="$output_objdir/${outputname}x" func_append generated " $gentop" func_extract_archives $gentop $addlibs func_append oldobjs " $func_extract_archives_result" fi # Do each command in the archive commands. if test -n "$old_archive_from_new_cmds" && test "$build_libtool_libs" = yes; then cmds=$old_archive_from_new_cmds else # Add any objects from preloaded convenience libraries if test -n "$dlprefiles"; then gentop="$output_objdir/${outputname}x" func_append generated " $gentop" func_extract_archives $gentop $dlprefiles func_append oldobjs " $func_extract_archives_result" fi # POSIX demands no paths to be encoded in archives. We have # to avoid creating archives with duplicate basenames if we # might have to extract them afterwards, e.g., when creating a # static archive out of a convenience library, or when linking # the entirety of a libtool archive into another (currently # not supported by libtool). if (for obj in $oldobjs do func_basename "$obj" $ECHO "$func_basename_result" done | sort | sort -uc >/dev/null 2>&1); then : else echo "copying selected object files to avoid basename conflicts..." gentop="$output_objdir/${outputname}x" func_append generated " $gentop" func_mkdir_p "$gentop" save_oldobjs=$oldobjs oldobjs= counter=1 for obj in $save_oldobjs do func_basename "$obj" objbase="$func_basename_result" case " $oldobjs " in " ") oldobjs=$obj ;; *[\ /]"$objbase "*) while :; do # Make sure we don't pick an alternate name that also # overlaps. newobj=lt$counter-$objbase func_arith $counter + 1 counter=$func_arith_result case " $oldobjs " in *[\ /]"$newobj "*) ;; *) if test ! -f "$gentop/$newobj"; then break; fi ;; esac done func_show_eval "ln $obj $gentop/$newobj || cp $obj $gentop/$newobj" func_append oldobjs " $gentop/$newobj" ;; *) func_append oldobjs " $obj" ;; esac done fi eval cmds=\"$old_archive_cmds\" func_len " $cmds" len=$func_len_result if test "$len" -lt "$max_cmd_len" || test "$max_cmd_len" -le -1; then cmds=$old_archive_cmds elif test -n "$archiver_list_spec"; then func_verbose "using command file archive linking..." for obj in $oldobjs do func_to_tool_file "$obj" $ECHO "$func_to_tool_file_result" done > $output_objdir/$libname.libcmd func_to_tool_file "$output_objdir/$libname.libcmd" oldobjs=" $archiver_list_spec$func_to_tool_file_result" cmds=$old_archive_cmds else # the command line is too long to link in one step, link in parts func_verbose "using piecewise archive linking..." save_RANLIB=$RANLIB RANLIB=: objlist= concat_cmds= save_oldobjs=$oldobjs oldobjs= # Is there a better way of finding the last object in the list? for obj in $save_oldobjs do last_oldobj=$obj done eval test_cmds=\"$old_archive_cmds\" func_len " $test_cmds" len0=$func_len_result len=$len0 for obj in $save_oldobjs do func_len " $obj" func_arith $len + $func_len_result len=$func_arith_result func_append objlist " $obj" if test "$len" -lt "$max_cmd_len"; then : else # the above command should be used before it gets too long oldobjs=$objlist if test "$obj" = "$last_oldobj" ; then RANLIB=$save_RANLIB fi test -z "$concat_cmds" || concat_cmds=$concat_cmds~ eval concat_cmds=\"\${concat_cmds}$old_archive_cmds\" objlist= len=$len0 fi done RANLIB=$save_RANLIB oldobjs=$objlist if test "X$oldobjs" = "X" ; then eval cmds=\"\$concat_cmds\" else eval cmds=\"\$concat_cmds~\$old_archive_cmds\" fi fi fi func_execute_cmds "$cmds" 'exit $?' done test -n "$generated" && \ func_show_eval "${RM}r$generated" # Now create the libtool archive. case $output in *.la) old_library= test "$build_old_libs" = yes && old_library="$libname.$libext" func_verbose "creating $output" # Preserve any variables that may affect compiler behavior for var in $variables_saved_for_relink; do if eval test -z \"\${$var+set}\"; then relink_command="{ test -z \"\${$var+set}\" || $lt_unset $var || { $var=; export $var; }; }; $relink_command" elif eval var_value=\$$var; test -z "$var_value"; then relink_command="$var=; export $var; $relink_command" else func_quote_for_eval "$var_value" relink_command="$var=$func_quote_for_eval_result; export $var; $relink_command" fi done # Quote the link command for shipping. relink_command="(cd `pwd`; $SHELL $progpath $preserve_args --mode=relink $libtool_args @inst_prefix_dir@)" relink_command=`$ECHO "$relink_command" | $SED "$sed_quote_subst"` if test "$hardcode_automatic" = yes ; then relink_command= fi # Only create the output if not a dry run. $opt_dry_run || { for installed in no yes; do if test "$installed" = yes; then if test -z "$install_libdir"; then break fi output="$output_objdir/$outputname"i # Replace all uninstalled libtool libraries with the installed ones newdependency_libs= for deplib in $dependency_libs; do case $deplib in *.la) func_basename "$deplib" name="$func_basename_result" eval libdir=`${SED} -n -e 's/^libdir=\(.*\)$/\1/p' $deplib` test -z "$libdir" && \ func_fatal_error "\`$deplib' is not a valid libtool archive" func_append newdependency_libs " ${lt_sysroot:+=}$libdir/$name" ;; -L*) func_stripname -L '' "$deplib" func_replace_sysroot "$func_stripname_result" func_append newdependency_libs " -L$func_replace_sysroot_result" ;; -R*) func_stripname -R '' "$deplib" func_replace_sysroot "$func_stripname_result" func_append newdependency_libs " -R$func_replace_sysroot_result" ;; *) func_append newdependency_libs " $deplib" ;; esac done dependency_libs="$newdependency_libs" newdlfiles= for lib in $dlfiles; do case $lib in *.la) func_basename "$lib" name="$func_basename_result" eval libdir=`${SED} -n -e 's/^libdir=\(.*\)$/\1/p' $lib` test -z "$libdir" && \ func_fatal_error "\`$lib' is not a valid libtool archive" func_append newdlfiles " ${lt_sysroot:+=}$libdir/$name" ;; *) func_append newdlfiles " $lib" ;; esac done dlfiles="$newdlfiles" newdlprefiles= for lib in $dlprefiles; do case $lib in *.la) # Only pass preopened files to the pseudo-archive (for # eventual linking with the app. that links it) if we # didn't already link the preopened objects directly into # the library: func_basename "$lib" name="$func_basename_result" eval libdir=`${SED} -n -e 's/^libdir=\(.*\)$/\1/p' $lib` test -z "$libdir" && \ func_fatal_error "\`$lib' is not a valid libtool archive" func_append newdlprefiles " ${lt_sysroot:+=}$libdir/$name" ;; esac done dlprefiles="$newdlprefiles" else newdlfiles= for lib in $dlfiles; do case $lib in [\\/]* | [A-Za-z]:[\\/]*) abs="$lib" ;; *) abs=`pwd`"/$lib" ;; esac func_append newdlfiles " $abs" done dlfiles="$newdlfiles" newdlprefiles= for lib in $dlprefiles; do case $lib in [\\/]* | [A-Za-z]:[\\/]*) abs="$lib" ;; *) abs=`pwd`"/$lib" ;; esac func_append newdlprefiles " $abs" done dlprefiles="$newdlprefiles" fi $RM $output # place dlname in correct position for cygwin # In fact, it would be nice if we could use this code for all target # systems that can't hard-code library paths into their executables # and that have no shared library path variable independent of PATH, # but it turns out we can't easily determine that from inspecting # libtool variables, so we have to hard-code the OSs to which it # applies here; at the moment, that means platforms that use the PE # object format with DLL files. See the long comment at the top of # tests/bindir.at for full details. tdlname=$dlname case $host,$output,$installed,$module,$dlname in *cygwin*,*lai,yes,no,*.dll | *mingw*,*lai,yes,no,*.dll | *cegcc*,*lai,yes,no,*.dll) # If a -bindir argument was supplied, place the dll there. if test "x$bindir" != x ; then func_relative_path "$install_libdir" "$bindir" tdlname=$func_relative_path_result$dlname else # Otherwise fall back on heuristic. tdlname=../bin/$dlname fi ;; esac $ECHO > $output "\ # $outputname - a libtool library file # Generated by $PROGRAM (GNU $PACKAGE$TIMESTAMP) $VERSION # # Please DO NOT delete this file! # It is necessary for linking the library. # The name that we can dlopen(3). dlname='$tdlname' # Names of this library. library_names='$library_names' # The name of the static archive. old_library='$old_library' # Linker flags that can not go in dependency_libs. inherited_linker_flags='$new_inherited_linker_flags' # Libraries that this one depends upon. dependency_libs='$dependency_libs' # Names of additional weak libraries provided by this library weak_library_names='$weak_libs' # Version information for $libname. current=$current age=$age revision=$revision # Is this an already installed library? installed=$installed # Should we warn about portability when linking against -modules? shouldnotlink=$module # Files to dlopen/dlpreopen dlopen='$dlfiles' dlpreopen='$dlprefiles' # Directory that this library needs to be installed in: libdir='$install_libdir'" if test "$installed" = no && test "$need_relink" = yes; then $ECHO >> $output "\ relink_command=\"$relink_command\"" fi done } # Do a symbolic link so that the libtool archive can be found in # LD_LIBRARY_PATH before the program is installed. func_show_eval '( cd "$output_objdir" && $RM "$outputname" && $LN_S "../$outputname" "$outputname" )' 'exit $?' ;; esac exit $EXIT_SUCCESS } { test "$opt_mode" = link || test "$opt_mode" = relink; } && func_mode_link ${1+"$@"} # func_mode_uninstall arg... func_mode_uninstall () { $opt_debug RM="$nonopt" files= rmforce= exit_status=0 # This variable tells wrapper scripts just to set variables rather # than running their programs. libtool_install_magic="$magic" for arg do case $arg in -f) func_append RM " $arg"; rmforce=yes ;; -*) func_append RM " $arg" ;; *) func_append files " $arg" ;; esac done test -z "$RM" && \ func_fatal_help "you must specify an RM program" rmdirs= for file in $files; do func_dirname "$file" "" "." dir="$func_dirname_result" if test "X$dir" = X.; then odir="$objdir" else odir="$dir/$objdir" fi func_basename "$file" name="$func_basename_result" test "$opt_mode" = uninstall && odir="$dir" # Remember odir for removal later, being careful to avoid duplicates if test "$opt_mode" = clean; then case " $rmdirs " in *" $odir "*) ;; *) func_append rmdirs " $odir" ;; esac fi # Don't error if the file doesn't exist and rm -f was used. if { test -L "$file"; } >/dev/null 2>&1 || { test -h "$file"; } >/dev/null 2>&1 || test -f "$file"; then : elif test -d "$file"; then exit_status=1 continue elif test "$rmforce" = yes; then continue fi rmfiles="$file" case $name in *.la) # Possibly a libtool archive, so verify it. if func_lalib_p "$file"; then func_source $dir/$name # Delete the libtool libraries and symlinks. for n in $library_names; do func_append rmfiles " $odir/$n" done test -n "$old_library" && func_append rmfiles " $odir/$old_library" case "$opt_mode" in clean) case " $library_names " in *" $dlname "*) ;; *) test -n "$dlname" && func_append rmfiles " $odir/$dlname" ;; esac test -n "$libdir" && func_append rmfiles " $odir/$name $odir/${name}i" ;; uninstall) if test -n "$library_names"; then # Do each command in the postuninstall commands. func_execute_cmds "$postuninstall_cmds" 'test "$rmforce" = yes || exit_status=1' fi if test -n "$old_library"; then # Do each command in the old_postuninstall commands. func_execute_cmds "$old_postuninstall_cmds" 'test "$rmforce" = yes || exit_status=1' fi # FIXME: should reinstall the best remaining shared library. ;; esac fi ;; *.lo) # Possibly a libtool object, so verify it. if func_lalib_p "$file"; then # Read the .lo file func_source $dir/$name # Add PIC object to the list of files to remove. if test -n "$pic_object" && test "$pic_object" != none; then func_append rmfiles " $dir/$pic_object" fi # Add non-PIC object to the list of files to remove. if test -n "$non_pic_object" && test "$non_pic_object" != none; then func_append rmfiles " $dir/$non_pic_object" fi fi ;; *) if test "$opt_mode" = clean ; then noexename=$name case $file in *.exe) func_stripname '' '.exe' "$file" file=$func_stripname_result func_stripname '' '.exe' "$name" noexename=$func_stripname_result # $file with .exe has already been added to rmfiles, # add $file without .exe func_append rmfiles " $file" ;; esac # Do a test to see if this is a libtool program. if func_ltwrapper_p "$file"; then if func_ltwrapper_executable_p "$file"; then func_ltwrapper_scriptname "$file" relink_command= func_source $func_ltwrapper_scriptname_result func_append rmfiles " $func_ltwrapper_scriptname_result" else relink_command= func_source $dir/$noexename fi # note $name still contains .exe if it was in $file originally # as does the version of $file that was added into $rmfiles func_append rmfiles " $odir/$name $odir/${name}S.${objext}" if test "$fast_install" = yes && test -n "$relink_command"; then func_append rmfiles " $odir/lt-$name" fi if test "X$noexename" != "X$name" ; then func_append rmfiles " $odir/lt-${noexename}.c" fi fi fi ;; esac func_show_eval "$RM $rmfiles" 'exit_status=1' done # Try to remove the ${objdir}s in the directories where we deleted files for dir in $rmdirs; do if test -d "$dir"; then func_show_eval "rmdir $dir >/dev/null 2>&1" fi done exit $exit_status } { test "$opt_mode" = uninstall || test "$opt_mode" = clean; } && func_mode_uninstall ${1+"$@"} test -z "$opt_mode" && { help="$generic_help" func_fatal_help "you must specify a MODE" } test -z "$exec_cmd" && \ func_fatal_help "invalid operation mode \`$opt_mode'" if test -n "$exec_cmd"; then eval exec "$exec_cmd" exit $EXIT_FAILURE fi exit $exit_status # The TAGs below are defined such that we never get into a situation # in which we disable both kinds of libraries. Given conflicting # choices, we go for a static library, that is the most portable, # since we can't tell whether shared libraries were disabled because # the user asked for that or because the platform doesn't support # them. This is particularly important on AIX, because we don't # support having both static and shared libraries enabled at the same # time on that platform, so we default to a shared-only configuration. # If a disable-shared tag is given, we'll fallback to a static-only # configuration. But we'll never go from static-only to shared-only. # ### BEGIN LIBTOOL TAG CONFIG: disable-shared build_libtool_libs=no build_old_libs=yes # ### END LIBTOOL TAG CONFIG: disable-shared # ### BEGIN LIBTOOL TAG CONFIG: disable-static build_old_libs=`case $build_libtool_libs in yes) echo no;; *) echo yes;; esac` # ### END LIBTOOL TAG CONFIG: disable-static # Local Variables: # mode:shell-script # sh-indentation:2 # End: # vi:sw=2 crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/config.sub0000644000175000017500000010115311610313111024044 0ustar andresandres#! /bin/sh # Configuration validation subroutine script. # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, # 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 # Free Software Foundation, Inc. timestamp='2008-01-16' # This file is (in principle) common to ALL GNU software. # The presence of a machine in this file suggests that SOME GNU software # can handle that machine. It does not imply ALL GNU software can. # # This file is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA # 02110-1301, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Please send patches to . Submit a context # diff and a properly formatted ChangeLog entry. # # Configuration subroutine to validate and canonicalize a configuration type. # Supply the specified configuration type as an argument. # If it is invalid, we print an error message on stderr and exit with code 1. # Otherwise, we print the canonical config type on stdout and succeed. # This file is supposed to be the same for all GNU packages # and recognize all the CPU types, system types and aliases # that are meaningful with *any* GNU software. # Each package is responsible for reporting which valid configurations # it does not support. The user should be able to distinguish # a failure to support a valid configuration from a meaningless # configuration. # The goal of this file is to map all the various variations of a given # machine specification into a single specification in the form: # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM # or in some cases, the newer four-part form: # CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM # It is wrong to echo any other type of specification. me=`echo "$0" | sed -e 's,.*/,,'` usage="\ Usage: $0 [OPTION] CPU-MFR-OPSYS $0 [OPTION] ALIAS Canonicalize a configuration name. Operation modes: -h, --help print this help, then exit -t, --time-stamp print date of last modification, then exit -v, --version print version number, then exit Report bugs and patches to ." version="\ GNU config.sub ($timestamp) Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." help=" Try \`$me --help' for more information." # Parse command line while test $# -gt 0 ; do case $1 in --time-stamp | --time* | -t ) echo "$timestamp" ; exit ;; --version | -v ) echo "$version" ; exit ;; --help | --h* | -h ) echo "$usage"; exit ;; -- ) # Stop option processing shift; break ;; - ) # Use stdin as input. break ;; -* ) echo "$me: invalid option $1$help" exit 1 ;; *local*) # First pass through any local machine types. echo $1 exit ;; * ) break ;; esac done case $# in 0) echo "$me: missing argument$help" >&2 exit 1;; 1) ;; *) echo "$me: too many arguments$help" >&2 exit 1;; esac # Separate what the user gave into CPU-COMPANY and OS or KERNEL-OS (if any). # Here we must recognize all the valid KERNEL-OS combinations. maybe_os=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\2/'` case $maybe_os in nto-qnx* | linux-gnu* | linux-dietlibc | linux-newlib* | linux-uclibc* | \ uclinux-uclibc* | uclinux-gnu* | kfreebsd*-gnu* | knetbsd*-gnu* | netbsd*-gnu* | \ storm-chaos* | os2-emx* | rtmk-nova*) os=-$maybe_os basic_machine=`echo $1 | sed 's/^\(.*\)-\([^-]*-[^-]*\)$/\1/'` ;; *) basic_machine=`echo $1 | sed 's/-[^-]*$//'` if [ $basic_machine != $1 ] then os=`echo $1 | sed 's/.*-/-/'` else os=; fi ;; esac ### Let's recognize common machines as not being operating systems so ### that things like config.sub decstation-3100 work. We also ### recognize some manufacturers as not being operating systems, so we ### can provide default operating systems below. case $os in -sun*os*) # Prevent following clause from handling this invalid input. ;; -dec* | -mips* | -sequent* | -encore* | -pc532* | -sgi* | -sony* | \ -att* | -7300* | -3300* | -delta* | -motorola* | -sun[234]* | \ -unicom* | -ibm* | -next | -hp | -isi* | -apollo | -altos* | \ -convergent* | -ncr* | -news | -32* | -3600* | -3100* | -hitachi* |\ -c[123]* | -convex* | -sun | -crds | -omron* | -dg | -ultra | -tti* | \ -harris | -dolphin | -highlevel | -gould | -cbm | -ns | -masscomp | \ -apple | -axis | -knuth | -cray) os= basic_machine=$1 ;; -sim | -cisco | -oki | -wec | -winbond) os= basic_machine=$1 ;; -scout) ;; -wrs) os=-vxworks basic_machine=$1 ;; -chorusos*) os=-chorusos basic_machine=$1 ;; -chorusrdb) os=-chorusrdb basic_machine=$1 ;; -hiux*) os=-hiuxwe2 ;; -sco6) os=-sco5v6 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco5) os=-sco3.2v5 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco4) os=-sco3.2v4 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco3.2.[4-9]*) os=`echo $os | sed -e 's/sco3.2./sco3.2v/'` basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco3.2v[4-9]*) # Don't forget version if it is 3.2v4 or newer. basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco5v6*) # Don't forget version if it is 3.2v4 or newer. basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -sco*) os=-sco3.2v2 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -udk*) basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -isc) os=-isc2.2 basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -clix*) basic_machine=clipper-intergraph ;; -isc*) basic_machine=`echo $1 | sed -e 's/86-.*/86-pc/'` ;; -lynx*) os=-lynxos ;; -ptx*) basic_machine=`echo $1 | sed -e 's/86-.*/86-sequent/'` ;; -windowsnt*) os=`echo $os | sed -e 's/windowsnt/winnt/'` ;; -psos*) os=-psos ;; -mint | -mint[0-9]*) basic_machine=m68k-atari os=-mint ;; esac # Decode aliases for certain CPU-COMPANY combinations. case $basic_machine in # Recognize the basic CPU types without company name. # Some are omitted here because they have special meanings below. 1750a | 580 \ | a29k \ | alpha | alphaev[4-8] | alphaev56 | alphaev6[78] | alphapca5[67] \ | alpha64 | alpha64ev[4-8] | alpha64ev56 | alpha64ev6[78] | alpha64pca5[67] \ | am33_2.0 \ | arc | arm | arm[bl]e | arme[lb] | armv[2345] | armv[345][lb] | avr | avr32 \ | bfin \ | c4x | clipper \ | d10v | d30v | dlx | dsp16xx \ | fido | fr30 | frv \ | h8300 | h8500 | hppa | hppa1.[01] | hppa2.0 | hppa2.0[nw] | hppa64 \ | i370 | i860 | i960 | ia64 \ | ip2k | iq2000 \ | m32c | m32r | m32rle | m68000 | m68k | m88k \ | maxq | mb | microblaze | mcore | mep \ | mips | mipsbe | mipseb | mipsel | mipsle \ | mips16 \ | mips64 | mips64el \ | mips64vr | mips64vrel \ | mips64orion | mips64orionel \ | mips64vr4100 | mips64vr4100el \ | mips64vr4300 | mips64vr4300el \ | mips64vr5000 | mips64vr5000el \ | mips64vr5900 | mips64vr5900el \ | mipsisa32 | mipsisa32el \ | mipsisa32r2 | mipsisa32r2el \ | mipsisa64 | mipsisa64el \ | mipsisa64r2 | mipsisa64r2el \ | mipsisa64sb1 | mipsisa64sb1el \ | mipsisa64sr71k | mipsisa64sr71kel \ | mipstx39 | mipstx39el \ | mn10200 | mn10300 \ | mt \ | msp430 \ | nios | nios2 \ | ns16k | ns32k \ | or32 \ | pdp10 | pdp11 | pj | pjl \ | powerpc | powerpc64 | powerpc64le | powerpcle | ppcbe \ | pyramid \ | score \ | sh | sh[1234] | sh[24]a | sh[23]e | sh[34]eb | sheb | shbe | shle | sh[1234]le | sh3ele \ | sh64 | sh64le \ | sparc | sparc64 | sparc64b | sparc64v | sparc86x | sparclet | sparclite \ | sparcv8 | sparcv9 | sparcv9b | sparcv9v \ | spu | strongarm \ | tahoe | thumb | tic4x | tic80 | tron \ | v850 | v850e \ | we32k \ | x86 | xc16x | xscale | xscalee[bl] | xstormy16 | xtensa \ | z8k) basic_machine=$basic_machine-unknown ;; m6811 | m68hc11 | m6812 | m68hc12) # Motorola 68HC11/12. basic_machine=$basic_machine-unknown os=-none ;; m88110 | m680[12346]0 | m683?2 | m68360 | m5200 | v70 | w65 | z8k) ;; ms1) basic_machine=mt-unknown ;; # We use `pc' rather than `unknown' # because (1) that's what they normally are, and # (2) the word "unknown" tends to confuse beginning users. i*86 | x86_64) basic_machine=$basic_machine-pc ;; # Object if more than one company name word. *-*-*) echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 exit 1 ;; # Recognize the basic CPU types with company name. 580-* \ | a29k-* \ | alpha-* | alphaev[4-8]-* | alphaev56-* | alphaev6[78]-* \ | alpha64-* | alpha64ev[4-8]-* | alpha64ev56-* | alpha64ev6[78]-* \ | alphapca5[67]-* | alpha64pca5[67]-* | arc-* \ | arm-* | armbe-* | armle-* | armeb-* | armv*-* \ | avr-* | avr32-* \ | bfin-* | bs2000-* \ | c[123]* | c30-* | [cjt]90-* | c4x-* | c54x-* | c55x-* | c6x-* \ | clipper-* | craynv-* | cydra-* \ | d10v-* | d30v-* | dlx-* \ | elxsi-* \ | f30[01]-* | f700-* | fido-* | fr30-* | frv-* | fx80-* \ | h8300-* | h8500-* \ | hppa-* | hppa1.[01]-* | hppa2.0-* | hppa2.0[nw]-* | hppa64-* \ | i*86-* | i860-* | i960-* | ia64-* \ | ip2k-* | iq2000-* \ | m32c-* | m32r-* | m32rle-* \ | m68000-* | m680[012346]0-* | m68360-* | m683?2-* | m68k-* \ | m88110-* | m88k-* | maxq-* | mcore-* \ | mips-* | mipsbe-* | mipseb-* | mipsel-* | mipsle-* \ | mips16-* \ | mips64-* | mips64el-* \ | mips64vr-* | mips64vrel-* \ | mips64orion-* | mips64orionel-* \ | mips64vr4100-* | mips64vr4100el-* \ | mips64vr4300-* | mips64vr4300el-* \ | mips64vr5000-* | mips64vr5000el-* \ | mips64vr5900-* | mips64vr5900el-* \ | mipsisa32-* | mipsisa32el-* \ | mipsisa32r2-* | mipsisa32r2el-* \ | mipsisa64-* | mipsisa64el-* \ | mipsisa64r2-* | mipsisa64r2el-* \ | mipsisa64sb1-* | mipsisa64sb1el-* \ | mipsisa64sr71k-* | mipsisa64sr71kel-* \ | mipstx39-* | mipstx39el-* \ | mmix-* \ | mt-* \ | msp430-* \ | nios-* | nios2-* \ | none-* | np1-* | ns16k-* | ns32k-* \ | orion-* \ | pdp10-* | pdp11-* | pj-* | pjl-* | pn-* | power-* \ | powerpc-* | powerpc64-* | powerpc64le-* | powerpcle-* | ppcbe-* \ | pyramid-* \ | romp-* | rs6000-* \ | sh-* | sh[1234]-* | sh[24]a-* | sh[23]e-* | sh[34]eb-* | sheb-* | shbe-* \ | shle-* | sh[1234]le-* | sh3ele-* | sh64-* | sh64le-* \ | sparc-* | sparc64-* | sparc64b-* | sparc64v-* | sparc86x-* | sparclet-* \ | sparclite-* \ | sparcv8-* | sparcv9-* | sparcv9b-* | sparcv9v-* | strongarm-* | sv1-* | sx?-* \ | tahoe-* | thumb-* \ | tic30-* | tic4x-* | tic54x-* | tic55x-* | tic6x-* | tic80-* \ | tron-* \ | v850-* | v850e-* | vax-* \ | we32k-* \ | x86-* | x86_64-* | xc16x-* | xps100-* | xscale-* | xscalee[bl]-* \ | xstormy16-* | xtensa*-* \ | ymp-* \ | z8k-*) ;; # Recognize the basic CPU types without company name, with glob match. xtensa*) basic_machine=$basic_machine-unknown ;; # Recognize the various machine names and aliases which stand # for a CPU type and a company and sometimes even an OS. 386bsd) basic_machine=i386-unknown os=-bsd ;; 3b1 | 7300 | 7300-att | att-7300 | pc7300 | safari | unixpc) basic_machine=m68000-att ;; 3b*) basic_machine=we32k-att ;; a29khif) basic_machine=a29k-amd os=-udi ;; abacus) basic_machine=abacus-unknown ;; adobe68k) basic_machine=m68010-adobe os=-scout ;; alliant | fx80) basic_machine=fx80-alliant ;; altos | altos3068) basic_machine=m68k-altos ;; am29k) basic_machine=a29k-none os=-bsd ;; amd64) basic_machine=x86_64-pc ;; amd64-*) basic_machine=x86_64-`echo $basic_machine | sed 's/^[^-]*-//'` ;; amdahl) basic_machine=580-amdahl os=-sysv ;; amiga | amiga-*) basic_machine=m68k-unknown ;; amigaos | amigados) basic_machine=m68k-unknown os=-amigaos ;; amigaunix | amix) basic_machine=m68k-unknown os=-sysv4 ;; apollo68) basic_machine=m68k-apollo os=-sysv ;; apollo68bsd) basic_machine=m68k-apollo os=-bsd ;; aux) basic_machine=m68k-apple os=-aux ;; balance) basic_machine=ns32k-sequent os=-dynix ;; blackfin) basic_machine=bfin-unknown os=-linux ;; blackfin-*) basic_machine=bfin-`echo $basic_machine | sed 's/^[^-]*-//'` os=-linux ;; c90) basic_machine=c90-cray os=-unicos ;; convex-c1) basic_machine=c1-convex os=-bsd ;; convex-c2) basic_machine=c2-convex os=-bsd ;; convex-c32) basic_machine=c32-convex os=-bsd ;; convex-c34) basic_machine=c34-convex os=-bsd ;; convex-c38) basic_machine=c38-convex os=-bsd ;; cray | j90) basic_machine=j90-cray os=-unicos ;; craynv) basic_machine=craynv-cray os=-unicosmp ;; cr16) basic_machine=cr16-unknown os=-elf ;; crds | unos) basic_machine=m68k-crds ;; crisv32 | crisv32-* | etraxfs*) basic_machine=crisv32-axis ;; cris | cris-* | etrax*) basic_machine=cris-axis ;; crx) basic_machine=crx-unknown os=-elf ;; da30 | da30-*) basic_machine=m68k-da30 ;; decstation | decstation-3100 | pmax | pmax-* | pmin | dec3100 | decstatn) basic_machine=mips-dec ;; decsystem10* | dec10*) basic_machine=pdp10-dec os=-tops10 ;; decsystem20* | dec20*) basic_machine=pdp10-dec os=-tops20 ;; delta | 3300 | motorola-3300 | motorola-delta \ | 3300-motorola | delta-motorola) basic_machine=m68k-motorola ;; delta88) basic_machine=m88k-motorola os=-sysv3 ;; djgpp) basic_machine=i586-pc os=-msdosdjgpp ;; dpx20 | dpx20-*) basic_machine=rs6000-bull os=-bosx ;; dpx2* | dpx2*-bull) basic_machine=m68k-bull os=-sysv3 ;; ebmon29k) basic_machine=a29k-amd os=-ebmon ;; elxsi) basic_machine=elxsi-elxsi os=-bsd ;; encore | umax | mmax) basic_machine=ns32k-encore ;; es1800 | OSE68k | ose68k | ose | OSE) basic_machine=m68k-ericsson os=-ose ;; fx2800) basic_machine=i860-alliant ;; genix) basic_machine=ns32k-ns ;; gmicro) basic_machine=tron-gmicro os=-sysv ;; go32) basic_machine=i386-pc os=-go32 ;; h3050r* | hiux*) basic_machine=hppa1.1-hitachi os=-hiuxwe2 ;; h8300hms) basic_machine=h8300-hitachi os=-hms ;; h8300xray) basic_machine=h8300-hitachi os=-xray ;; h8500hms) basic_machine=h8500-hitachi os=-hms ;; harris) basic_machine=m88k-harris os=-sysv3 ;; hp300-*) basic_machine=m68k-hp ;; hp300bsd) basic_machine=m68k-hp os=-bsd ;; hp300hpux) basic_machine=m68k-hp os=-hpux ;; hp3k9[0-9][0-9] | hp9[0-9][0-9]) basic_machine=hppa1.0-hp ;; hp9k2[0-9][0-9] | hp9k31[0-9]) basic_machine=m68000-hp ;; hp9k3[2-9][0-9]) basic_machine=m68k-hp ;; hp9k6[0-9][0-9] | hp6[0-9][0-9]) basic_machine=hppa1.0-hp ;; hp9k7[0-79][0-9] | hp7[0-79][0-9]) basic_machine=hppa1.1-hp ;; hp9k78[0-9] | hp78[0-9]) # FIXME: really hppa2.0-hp basic_machine=hppa1.1-hp ;; hp9k8[67]1 | hp8[67]1 | hp9k80[24] | hp80[24] | hp9k8[78]9 | hp8[78]9 | hp9k893 | hp893) # FIXME: really hppa2.0-hp basic_machine=hppa1.1-hp ;; hp9k8[0-9][13679] | hp8[0-9][13679]) basic_machine=hppa1.1-hp ;; hp9k8[0-9][0-9] | hp8[0-9][0-9]) basic_machine=hppa1.0-hp ;; hppa-next) os=-nextstep3 ;; hppaosf) basic_machine=hppa1.1-hp os=-osf ;; hppro) basic_machine=hppa1.1-hp os=-proelf ;; i370-ibm* | ibm*) basic_machine=i370-ibm ;; # I'm not sure what "Sysv32" means. Should this be sysv3.2? i*86v32) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv32 ;; i*86v4*) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv4 ;; i*86v) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-sysv ;; i*86sol2) basic_machine=`echo $1 | sed -e 's/86.*/86-pc/'` os=-solaris2 ;; i386mach) basic_machine=i386-mach os=-mach ;; i386-vsta | vsta) basic_machine=i386-unknown os=-vsta ;; iris | iris4d) basic_machine=mips-sgi case $os in -irix*) ;; *) os=-irix4 ;; esac ;; isi68 | isi) basic_machine=m68k-isi os=-sysv ;; m68knommu) basic_machine=m68k-unknown os=-linux ;; m68knommu-*) basic_machine=m68k-`echo $basic_machine | sed 's/^[^-]*-//'` os=-linux ;; m88k-omron*) basic_machine=m88k-omron ;; magnum | m3230) basic_machine=mips-mips os=-sysv ;; merlin) basic_machine=ns32k-utek os=-sysv ;; mingw32) basic_machine=i386-pc os=-mingw32 ;; mingw32ce) basic_machine=arm-unknown os=-mingw32ce ;; miniframe) basic_machine=m68000-convergent ;; *mint | -mint[0-9]* | *MiNT | *MiNT[0-9]*) basic_machine=m68k-atari os=-mint ;; mips3*-*) basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'` ;; mips3*) basic_machine=`echo $basic_machine | sed -e 's/mips3/mips64/'`-unknown ;; monitor) basic_machine=m68k-rom68k os=-coff ;; morphos) basic_machine=powerpc-unknown os=-morphos ;; msdos) basic_machine=i386-pc os=-msdos ;; ms1-*) basic_machine=`echo $basic_machine | sed -e 's/ms1-/mt-/'` ;; mvs) basic_machine=i370-ibm os=-mvs ;; ncr3000) basic_machine=i486-ncr os=-sysv4 ;; netbsd386) basic_machine=i386-unknown os=-netbsd ;; netwinder) basic_machine=armv4l-rebel os=-linux ;; news | news700 | news800 | news900) basic_machine=m68k-sony os=-newsos ;; news1000) basic_machine=m68030-sony os=-newsos ;; news-3600 | risc-news) basic_machine=mips-sony os=-newsos ;; necv70) basic_machine=v70-nec os=-sysv ;; next | m*-next ) basic_machine=m68k-next case $os in -nextstep* ) ;; -ns2*) os=-nextstep2 ;; *) os=-nextstep3 ;; esac ;; nh3000) basic_machine=m68k-harris os=-cxux ;; nh[45]000) basic_machine=m88k-harris os=-cxux ;; nindy960) basic_machine=i960-intel os=-nindy ;; mon960) basic_machine=i960-intel os=-mon960 ;; nonstopux) basic_machine=mips-compaq os=-nonstopux ;; np1) basic_machine=np1-gould ;; nsr-tandem) basic_machine=nsr-tandem ;; op50n-* | op60c-*) basic_machine=hppa1.1-oki os=-proelf ;; openrisc | openrisc-*) basic_machine=or32-unknown ;; os400) basic_machine=powerpc-ibm os=-os400 ;; OSE68000 | ose68000) basic_machine=m68000-ericsson os=-ose ;; os68k) basic_machine=m68k-none os=-os68k ;; pa-hitachi) basic_machine=hppa1.1-hitachi os=-hiuxwe2 ;; paragon) basic_machine=i860-intel os=-osf ;; parisc) basic_machine=hppa-unknown os=-linux ;; parisc-*) basic_machine=hppa-`echo $basic_machine | sed 's/^[^-]*-//'` os=-linux ;; pbd) basic_machine=sparc-tti ;; pbb) basic_machine=m68k-tti ;; pc532 | pc532-*) basic_machine=ns32k-pc532 ;; pc98) basic_machine=i386-pc ;; pc98-*) basic_machine=i386-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentium | p5 | k5 | k6 | nexgen | viac3) basic_machine=i586-pc ;; pentiumpro | p6 | 6x86 | athlon | athlon_*) basic_machine=i686-pc ;; pentiumii | pentium2 | pentiumiii | pentium3) basic_machine=i686-pc ;; pentium4) basic_machine=i786-pc ;; pentium-* | p5-* | k5-* | k6-* | nexgen-* | viac3-*) basic_machine=i586-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentiumpro-* | p6-* | 6x86-* | athlon-*) basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentiumii-* | pentium2-* | pentiumiii-* | pentium3-*) basic_machine=i686-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pentium4-*) basic_machine=i786-`echo $basic_machine | sed 's/^[^-]*-//'` ;; pn) basic_machine=pn-gould ;; power) basic_machine=power-ibm ;; ppc) basic_machine=powerpc-unknown ;; ppc-*) basic_machine=powerpc-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppcle | powerpclittle | ppc-le | powerpc-little) basic_machine=powerpcle-unknown ;; ppcle-* | powerpclittle-*) basic_machine=powerpcle-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppc64) basic_machine=powerpc64-unknown ;; ppc64-*) basic_machine=powerpc64-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ppc64le | powerpc64little | ppc64-le | powerpc64-little) basic_machine=powerpc64le-unknown ;; ppc64le-* | powerpc64little-*) basic_machine=powerpc64le-`echo $basic_machine | sed 's/^[^-]*-//'` ;; ps2) basic_machine=i386-ibm ;; pw32) basic_machine=i586-unknown os=-pw32 ;; rdos) basic_machine=i386-pc os=-rdos ;; rom68k) basic_machine=m68k-rom68k os=-coff ;; rm[46]00) basic_machine=mips-siemens ;; rtpc | rtpc-*) basic_machine=romp-ibm ;; s390 | s390-*) basic_machine=s390-ibm ;; s390x | s390x-*) basic_machine=s390x-ibm ;; sa29200) basic_machine=a29k-amd os=-udi ;; sb1) basic_machine=mipsisa64sb1-unknown ;; sb1el) basic_machine=mipsisa64sb1el-unknown ;; sde) basic_machine=mipsisa32-sde os=-elf ;; sei) basic_machine=mips-sei os=-seiux ;; sequent) basic_machine=i386-sequent ;; sh) basic_machine=sh-hitachi os=-hms ;; sh5el) basic_machine=sh5le-unknown ;; sh64) basic_machine=sh64-unknown ;; sparclite-wrs | simso-wrs) basic_machine=sparclite-wrs os=-vxworks ;; sps7) basic_machine=m68k-bull os=-sysv2 ;; spur) basic_machine=spur-unknown ;; st2000) basic_machine=m68k-tandem ;; stratus) basic_machine=i860-stratus os=-sysv4 ;; sun2) basic_machine=m68000-sun ;; sun2os3) basic_machine=m68000-sun os=-sunos3 ;; sun2os4) basic_machine=m68000-sun os=-sunos4 ;; sun3os3) basic_machine=m68k-sun os=-sunos3 ;; sun3os4) basic_machine=m68k-sun os=-sunos4 ;; sun4os3) basic_machine=sparc-sun os=-sunos3 ;; sun4os4) basic_machine=sparc-sun os=-sunos4 ;; sun4sol2) basic_machine=sparc-sun os=-solaris2 ;; sun3 | sun3-*) basic_machine=m68k-sun ;; sun4) basic_machine=sparc-sun ;; sun386 | sun386i | roadrunner) basic_machine=i386-sun ;; sv1) basic_machine=sv1-cray os=-unicos ;; symmetry) basic_machine=i386-sequent os=-dynix ;; t3e) basic_machine=alphaev5-cray os=-unicos ;; t90) basic_machine=t90-cray os=-unicos ;; tic54x | c54x*) basic_machine=tic54x-unknown os=-coff ;; tic55x | c55x*) basic_machine=tic55x-unknown os=-coff ;; tic6x | c6x*) basic_machine=tic6x-unknown os=-coff ;; tile*) basic_machine=tile-unknown os=-linux-gnu ;; tx39) basic_machine=mipstx39-unknown ;; tx39el) basic_machine=mipstx39el-unknown ;; toad1) basic_machine=pdp10-xkl os=-tops20 ;; tower | tower-32) basic_machine=m68k-ncr ;; tpf) basic_machine=s390x-ibm os=-tpf ;; udi29k) basic_machine=a29k-amd os=-udi ;; ultra3) basic_machine=a29k-nyu os=-sym1 ;; v810 | necv810) basic_machine=v810-nec os=-none ;; vaxv) basic_machine=vax-dec os=-sysv ;; vms) basic_machine=vax-dec os=-vms ;; vpp*|vx|vx-*) basic_machine=f301-fujitsu ;; vxworks960) basic_machine=i960-wrs os=-vxworks ;; vxworks68) basic_machine=m68k-wrs os=-vxworks ;; vxworks29k) basic_machine=a29k-wrs os=-vxworks ;; w65*) basic_machine=w65-wdc os=-none ;; w89k-*) basic_machine=hppa1.1-winbond os=-proelf ;; xbox) basic_machine=i686-pc os=-mingw32 ;; xps | xps100) basic_machine=xps100-honeywell ;; ymp) basic_machine=ymp-cray os=-unicos ;; z8k-*-coff) basic_machine=z8k-unknown os=-sim ;; none) basic_machine=none-none os=-none ;; # Here we handle the default manufacturer of certain CPU types. It is in # some cases the only manufacturer, in others, it is the most popular. w89k) basic_machine=hppa1.1-winbond ;; op50n) basic_machine=hppa1.1-oki ;; op60c) basic_machine=hppa1.1-oki ;; romp) basic_machine=romp-ibm ;; mmix) basic_machine=mmix-knuth ;; rs6000) basic_machine=rs6000-ibm ;; vax) basic_machine=vax-dec ;; pdp10) # there are many clones, so DEC is not a safe bet basic_machine=pdp10-unknown ;; pdp11) basic_machine=pdp11-dec ;; we32k) basic_machine=we32k-att ;; sh[1234] | sh[24]a | sh[34]eb | sh[1234]le | sh[23]ele) basic_machine=sh-unknown ;; sparc | sparcv8 | sparcv9 | sparcv9b | sparcv9v) basic_machine=sparc-sun ;; cydra) basic_machine=cydra-cydrome ;; orion) basic_machine=orion-highlevel ;; orion105) basic_machine=clipper-highlevel ;; mac | mpw | mac-mpw) basic_machine=m68k-apple ;; pmac | pmac-mpw) basic_machine=powerpc-apple ;; *-unknown) # Make sure to match an already-canonicalized machine name. ;; *) echo Invalid configuration \`$1\': machine \`$basic_machine\' not recognized 1>&2 exit 1 ;; esac # Here we canonicalize certain aliases for manufacturers. case $basic_machine in *-digital*) basic_machine=`echo $basic_machine | sed 's/digital.*/dec/'` ;; *-commodore*) basic_machine=`echo $basic_machine | sed 's/commodore.*/cbm/'` ;; *) ;; esac # Decode manufacturer-specific aliases for certain operating systems. if [ x"$os" != x"" ] then case $os in # First match some system type aliases # that might get confused with valid system types. # -solaris* is a basic system type, with this one exception. -solaris1 | -solaris1.*) os=`echo $os | sed -e 's|solaris1|sunos4|'` ;; -solaris) os=-solaris2 ;; -svr4*) os=-sysv4 ;; -unixware*) os=-sysv4.2uw ;; -gnu/linux*) os=`echo $os | sed -e 's|gnu/linux|linux-gnu|'` ;; # First accept the basic system types. # The portable systems comes first. # Each alternative MUST END IN A *, to match a version number. # -sysv* is not here because it comes later, after sysvr4. -gnu* | -bsd* | -mach* | -minix* | -genix* | -ultrix* | -irix* \ | -*vms* | -sco* | -esix* | -isc* | -aix* | -sunos | -sunos[34]*\ | -hpux* | -unos* | -osf* | -luna* | -dgux* | -solaris* | -sym* \ | -amigaos* | -amigados* | -msdos* | -newsos* | -unicos* | -aof* \ | -aos* \ | -nindy* | -vxsim* | -vxworks* | -ebmon* | -hms* | -mvs* \ | -clix* | -riscos* | -uniplus* | -iris* | -rtu* | -xenix* \ | -hiux* | -386bsd* | -knetbsd* | -mirbsd* | -netbsd* \ | -openbsd* | -solidbsd* \ | -ekkobsd* | -kfreebsd* | -freebsd* | -riscix* | -lynxos* \ | -bosx* | -nextstep* | -cxux* | -aout* | -elf* | -oabi* \ | -ptx* | -coff* | -ecoff* | -winnt* | -domain* | -vsta* \ | -udi* | -eabi* | -lites* | -ieee* | -go32* | -aux* \ | -chorusos* | -chorusrdb* \ | -cygwin* | -pe* | -psos* | -moss* | -proelf* | -rtems* \ | -mingw32* | -linux-gnu* | -linux-newlib* | -linux-uclibc* \ | -uxpv* | -beos* | -mpeix* | -udk* \ | -interix* | -uwin* | -mks* | -rhapsody* | -darwin* | -opened* \ | -openstep* | -oskit* | -conix* | -pw32* | -nonstopux* \ | -storm-chaos* | -tops10* | -tenex* | -tops20* | -its* \ | -os2* | -vos* | -palmos* | -uclinux* | -nucleus* \ | -morphos* | -superux* | -rtmk* | -rtmk-nova* | -windiss* \ | -powermax* | -dnix* | -nx6 | -nx7 | -sei* | -dragonfly* \ | -skyos* | -haiku* | -rdos* | -toppers* | -drops*) # Remember, each alternative MUST END IN *, to match a version number. ;; -qnx*) case $basic_machine in x86-* | i*86-*) ;; *) os=-nto$os ;; esac ;; -nto-qnx*) ;; -nto*) os=`echo $os | sed -e 's|nto|nto-qnx|'` ;; -sim | -es1800* | -hms* | -xray | -os68k* | -none* | -v88r* \ | -windows* | -osx | -abug | -netware* | -os9* | -beos* | -haiku* \ | -macos* | -mpw* | -magic* | -mmixware* | -mon960* | -lnews*) ;; -mac*) os=`echo $os | sed -e 's|mac|macos|'` ;; -linux-dietlibc) os=-linux-dietlibc ;; -linux*) os=`echo $os | sed -e 's|linux|linux-gnu|'` ;; -sunos5*) os=`echo $os | sed -e 's|sunos5|solaris2|'` ;; -sunos6*) os=`echo $os | sed -e 's|sunos6|solaris3|'` ;; -opened*) os=-openedition ;; -os400*) os=-os400 ;; -wince*) os=-wince ;; -osfrose*) os=-osfrose ;; -osf*) os=-osf ;; -utek*) os=-bsd ;; -dynix*) os=-bsd ;; -acis*) os=-aos ;; -atheos*) os=-atheos ;; -syllable*) os=-syllable ;; -386bsd) os=-bsd ;; -ctix* | -uts*) os=-sysv ;; -nova*) os=-rtmk-nova ;; -ns2 ) os=-nextstep2 ;; -nsk*) os=-nsk ;; # Preserve the version number of sinix5. -sinix5.*) os=`echo $os | sed -e 's|sinix|sysv|'` ;; -sinix*) os=-sysv4 ;; -tpf*) os=-tpf ;; -triton*) os=-sysv3 ;; -oss*) os=-sysv3 ;; -svr4) os=-sysv4 ;; -svr3) os=-sysv3 ;; -sysvr4) os=-sysv4 ;; # This must come after -sysvr4. -sysv*) ;; -ose*) os=-ose ;; -es1800*) os=-ose ;; -xenix) os=-xenix ;; -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) os=-mint ;; -aros*) os=-aros ;; -kaos*) os=-kaos ;; -zvmoe) os=-zvmoe ;; -none) ;; *) # Get rid of the `-' at the beginning of $os. os=`echo $os | sed 's/[^-]*-//'` echo Invalid configuration \`$1\': system \`$os\' not recognized 1>&2 exit 1 ;; esac else # Here we handle the default operating systems that come with various machines. # The value should be what the vendor currently ships out the door with their # machine or put another way, the most popular os provided with the machine. # Note that if you're going to try to match "-MANUFACTURER" here (say, # "-sun"), then you have to tell the case statement up towards the top # that MANUFACTURER isn't an operating system. Otherwise, code above # will signal an error saying that MANUFACTURER isn't an operating # system, and we'll never get to this point. case $basic_machine in score-*) os=-elf ;; spu-*) os=-elf ;; *-acorn) os=-riscix1.2 ;; arm*-rebel) os=-linux ;; arm*-semi) os=-aout ;; c4x-* | tic4x-*) os=-coff ;; # This must come before the *-dec entry. pdp10-*) os=-tops20 ;; pdp11-*) os=-none ;; *-dec | vax-*) os=-ultrix4.2 ;; m68*-apollo) os=-domain ;; i386-sun) os=-sunos4.0.2 ;; m68000-sun) os=-sunos3 # This also exists in the configure program, but was not the # default. # os=-sunos4 ;; m68*-cisco) os=-aout ;; mep-*) os=-elf ;; mips*-cisco) os=-elf ;; mips*-*) os=-elf ;; or32-*) os=-coff ;; *-tti) # must be before sparc entry or we get the wrong os. os=-sysv3 ;; sparc-* | *-sun) os=-sunos4.1.1 ;; *-be) os=-beos ;; *-haiku) os=-haiku ;; *-ibm) os=-aix ;; *-knuth) os=-mmixware ;; *-wec) os=-proelf ;; *-winbond) os=-proelf ;; *-oki) os=-proelf ;; *-hp) os=-hpux ;; *-hitachi) os=-hiux ;; i860-* | *-att | *-ncr | *-altos | *-motorola | *-convergent) os=-sysv ;; *-cbm) os=-amigaos ;; *-dg) os=-dgux ;; *-dolphin) os=-sysv3 ;; m68k-ccur) os=-rtu ;; m88k-omron*) os=-luna ;; *-next ) os=-nextstep ;; *-sequent) os=-ptx ;; *-crds) os=-unos ;; *-ns) os=-genix ;; i370-*) os=-mvs ;; *-next) os=-nextstep3 ;; *-gould) os=-sysv ;; *-highlevel) os=-bsd ;; *-encore) os=-bsd ;; *-sgi) os=-irix ;; *-siemens) os=-sysv4 ;; *-masscomp) os=-rtu ;; f30[01]-fujitsu | f700-fujitsu) os=-uxpv ;; *-rom68k) os=-coff ;; *-*bug) os=-coff ;; *-apple) os=-macos ;; *-atari*) os=-mint ;; *) os=-none ;; esac fi # Here we handle the case where we know the os, and the CPU type, but not the # manufacturer. We pick the logical manufacturer. vendor=unknown case $basic_machine in *-unknown) case $os in -riscix*) vendor=acorn ;; -sunos*) vendor=sun ;; -aix*) vendor=ibm ;; -beos*) vendor=be ;; -hpux*) vendor=hp ;; -mpeix*) vendor=hp ;; -hiux*) vendor=hitachi ;; -unos*) vendor=crds ;; -dgux*) vendor=dg ;; -luna*) vendor=omron ;; -genix*) vendor=ns ;; -mvs* | -opened*) vendor=ibm ;; -os400*) vendor=ibm ;; -ptx*) vendor=sequent ;; -tpf*) vendor=ibm ;; -vxsim* | -vxworks* | -windiss*) vendor=wrs ;; -aux*) vendor=apple ;; -hms*) vendor=hitachi ;; -mpw* | -macos*) vendor=apple ;; -*mint | -mint[0-9]* | -*MiNT | -MiNT[0-9]*) vendor=atari ;; -vos*) vendor=stratus ;; esac basic_machine=`echo $basic_machine | sed "s/unknown/$vendor/"` ;; esac echo $basic_machine$os exit # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "timestamp='" # time-stamp-format: "%:y-%02m-%02d" # time-stamp-end: "'" # End: crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/src/0000755000175000017500000000000011610313122022654 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/src/gstbcmdec.h0000644000175000017500000002131511610313111024760 0ustar andresandres /******************************************************************** * Copyright(c) 2008 Broadcom Corporation. * * Name: gstbcmdec.h * * Description: Broadcom 70012 Decoder plugin header * * AU * * HISTORY: * ******************************************************************* * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #ifndef __GST_BCMDEC_H__ #define __GST_BCMDEC_H__ #define GST_BCMDEC_RANK 0xffff #define CLOCK_BASE 9LL #define CLOC_FREQ_CLOC_BASE * 10000 #define GST_BUF_LIST_POOL_SZ 100; #define GST_RENDERER_BUF_POOL_SZ 20 #define MPEGTIME_TO_GSTTIME(time) ((time) * (GST_MSECOND/10)) / CLOCK_BASE) #define GSTIME_TO_MPEGTIME(time) (((time) * CLOCK_BASE) / (GST_MSECOND)/10)) const gint64 UNITS = 1000000000; #define BRCM_START_CODE_SIZE 4 //VC1 prefix 000001 #define VC1_FRM_SUFFIX 0x0D #define VC1_SEQ_SUFFIX 0x0F //VC1 SM Profile prefix 000001 #define VC1_SM_FRM_SUFFIX 0xE0 //Check WMV SP/MP PES Payload for PTS Info //#define VC1_SM_MAGIC_WORD 0x5A5A5A5A //#define VC1_SM_PTS_INFO_START_CODE 0xBD //MPEG2 prefix 000001 #define MPEG2_FRM_SUFFIX 0x00 #define MPEG2_SEQ_SUFFIX 0xB3 #define PAUSE_THRESHOLD 16 #define RESUME_THRESHOLD 8 #define SPS_PPS_SIZE 1000 #define BCM_GST_SHMEM_KEY 0xDEADBEEF #define THUMBNAIL_FRAMES 60 typedef enum { H264=0, MPEG2, VC1 }VIDFOMATS; typedef enum { NV12 = 0, YUY2, UYVY, YV12 }CLRSPACE; typedef struct { guint width; guint height; guint8 clr_space; gdouble framerate; guint8 aspectratio_x; guint8 aspectratio_y; guint32 y_size; guint32 uv_size; guint8 stride; }OUTPARAMS; typedef struct { guint8* sps_pps_buf; guint32 pps_size; gboolean inside_buffer; guint32 consumed_offset; guint32 strtcode_offset; guint32 nal_sz; guint8 nal_size_bytes; } CODEC_PARAMS; typedef struct _GSTBUF_LIST{ GstBuffer* gstbuf; struct _GSTBUF_LIST *next; }GSTBUF_LIST; #define MAX_ADV_PROF_SEQ_HDR_SZ 50 typedef enum { UNKNOWN = 0, THUMBNAIL = 1, PLAYBACK = 2, }CURDECODE; typedef struct { guint rendered_frames; gboolean waiting; CURDECODE cur_decode; sem_t inst_ctrl_event; }GLB_INST_STS; G_BEGIN_DECLS #define GST_TYPE_BCMDEC \ (gst_bcmdec_get_type()) #define GST_BCMDEC(obj) \ (G_TYPE_CHECK_INSTANCE_CAST((obj),GST_TYPE_BCMDEC,GstBcmDec)) #define GST_BCMDEC_CLASS(klass) \ (G_TYPE_CHECK_CLASS_CAST((klass),GST_TYPE_BCMDEC,GstBcmDecClass)) #define GST_IS_BCMDEC(obj) \ (G_TYPE_CHECK_INSTANCE_TYPE((obj),GST_TYPE_BCMDEC)) #define GST_IS_BCMDEC_CLASS(klass) \ (G_TYPE_CHECK_CLASS_TYPE((klass),GST_TYPE_BCMDEC)) typedef struct _GstBcmDec GstBcmDec; typedef struct _GstBcmDecClass GstBcmDecClass; struct _GstBcmDec { GstElement element; GstPad *sinkpad, *srcpad; gboolean silent; void* hdevice; gboolean dec_ready; gboolean streaming; gboolean feos; GMutex *mPlayLock; BC_MEDIA_SUBTYPE input_format; OUTPARAMS output_params; pthread_t recv_thread; sem_t play_event; sem_t quit_event; BcmDecIF decif; Parse parse; BC_PIC_INFO_BLOCK pic_info; gboolean format_reset; gboolean interlace; GstClockTime base_time; FILE *fhnd ; gboolean play_pending; GstEvent* ev_eos; GSTBUF_LIST* gst_buf_que_hd; GSTBUF_LIST* gst_buf_que_tl; pthread_mutex_t gst_buf_que_lock; guint gst_que_cnt; pthread_t push_thread; gboolean last_picture_set; sem_t buf_event; guint gst_buf_que_sz; GSTBUF_LIST* gst_mem_buf_que_hd; gdouble input_framerate; guint32 prev_pic; gboolean paused; gboolean insert_start_code; CODEC_PARAMS codec_params ; gboolean sec_field; guint8 input_par_x; guint8 input_par_y; gboolean flushing; sem_t push_stop_event; sem_t push_start_event; sem_t recv_stop_event; guint ses_nbr; gboolean insert_pps; gboolean ses_change; gboolean push_exit; pthread_mutex_t fn_lock; gboolean suspend_mode; GstClock* gst_clock; guint32 rpt_pic_cnt; gboolean enable_spes; guint8* dest_buf; guint32 spes_frame_cnt; GstClockTime spes_frm_time; gboolean catchup_on; GstClockTime last_spes_time; GstClockTime last_output_spes_time; GstClockTime frame_time; GstClockTime base_clock_time; GstClockTime prev_clock_time; GstClockTime cur_stream_time; guint8 proc_in_flags; gint frame_width; /*The value from Demux used for WMV9 or VC-1 SP/MP */ gint frame_height; /*The value from Demux used for WMV9 or VC-1 SP/MP */ GSTBUF_LIST* gst_padbuf_que_hd; GSTBUF_LIST* gst_padbuf_que_tl; pthread_mutex_t gst_padbuf_que_lock; guint gst_padbuf_que_cnt; pthread_t get_rbuf_thread; sem_t rbuf_start_event; sem_t rbuf_stop_event; sem_t rbuf_ins_event; guint gst_padbuf_que_sz; GSTBUF_LIST* gst_mem_padbuf_que_hd; gboolean rbuf_thread_running; }; struct _GstBcmDecClass { GstElementClass parent_class; }; GType gst_bcmdec_get_type (void); static void gst_bcmdec_base_init (gpointer gclass); static void gst_bcmdec_class_init(GstBcmDecClass * klass); static void gst_bcmdec_init(GstBcmDec * bcmdec, GstBcmDecClass * gclass); static void gst_bcmdec_finalize(GObject * object); static GstFlowReturn gst_bcmdec_chain(GstPad * pad, GstBuffer * buffer); static GstStateChangeReturn gst_bcmdec_change_state(GstElement * element, GstStateChange transition); static gboolean gst_bcmdec_sink_set_caps(GstPad * pad, GstCaps * caps); static GstCaps *gst_bcmdec_getcaps (GstPad * pad); static gboolean gst_bcmdec_src_event(GstPad * pad, GstEvent * event); static gboolean gst_bcmdec_sink_event(GstPad * pad, GstEvent * event); static void gst_bcmdec_set_property (GObject * object, guint prop_id, const GValue * value, GParamSpec * pspec); static void gst_bcmdec_get_property (GObject * object, guint prop_id, GValue * value, GParamSpec * pspec); static gboolean bcmdec_negotiate_format (GstBcmDec * bcmdec); static void bcmdec_reset(GstBcmDec * bcmdec); static gboolean bcmdec_get_buffer(GstBcmDec * bcmdec, GstBuffer ** obuf); static void* bcmdec_process_output(void * ctx); static void bcmdec_init_procout(GstBcmDec * filter,BC_DTS_PROC_OUT* pout, guint8* buf); static void bcmdec_set_framerate(GstBcmDec * filter,guint32 resolution); static gboolean bcmdec_format_change(GstBcmDec * filter,BC_PIC_INFO_BLOCK* pic_info); static BC_STATUS gst_bcmdec_cleanup(GstBcmDec *filter); static gboolean bcmdec_start_recv_thread(GstBcmDec * bcmdec); static GstClockTime bcmdec_get_time_stamp(GstBcmDec* filter, guint32 pic_no,GstClockTime spes_time); static gboolean bcmdec_process_play(GstBcmDec *filter); static gboolean bcmdec_alloc_mem_buf_que_pool(GstBcmDec *filter); static gboolean bcmdec_release_mem_buf_que_pool(GstBcmDec *filter); static void bcmdec_put_que_mem_buf(GstBcmDec *filter,GSTBUF_LIST *gst_queue_element); static GSTBUF_LIST* bcmdec_get_que_mem_buf(GstBcmDec *filter); static void bcmdec_ins_buf(GstBcmDec *filter,GSTBUF_LIST *gst_queue_element); static GSTBUF_LIST* bcmdec_rem_buf(GstBcmDec *filter); static void* bcmdec_process_push(void* ctx); static gboolean bcmdec_start_push_thread(GstBcmDec * bcmdec); //static BC_STATUS //bcmdec_insert_startcode(GstBcmDec* filter,GstBuffer* gstbuf, guint8* dest_buf,guint32* sz); static BC_STATUS bcmdec_insert_sps_pps(GstBcmDec* filter,GstBuffer* gstbuf); static void bcmdec_set_aspect_ratio(GstBcmDec *filter,BC_PIC_INFO_BLOCK* pic_info); static void bcmdec_process_flush_start(GstBcmDec* filter); static void bcmdec_process_flush_stop(GstBcmDec* filter); static gboolean bcmdec_mul_inst_cor(GstBcmDec* filter); static BC_STATUS bcmdec_create_shmem(GstBcmDec* filter,int *shmem_id); static BC_STATUS bcmdec_get_shmem(GstBcmDec* filter,int shmid,gboolean newsh); static BC_STATUS bcmdec_del_shmem(GstBcmDec* filter); static gboolean bcmdec_start_get_rbuf_thread(GstBcmDec * bcmdec); // static gboolean // bcmdec_alloc_mem_padbuf_que_pool(GstBcmDec *filter); // // static gboolean // bcmdec_release_mem_padbuf_que_pool(GstBcmDec *filter); // static void // bcmdec_put_que_mem_padbuf(GstBcmDec *filter,GSTBUF_LIST *gst_queue_element); // // static GSTBUF_LIST* // bcmdec_get_que_mem_padbuf(GstBcmDec *filter); static void bcmdec_ins_padbuf(GstBcmDec *filter,GSTBUF_LIST *gst_queue_element); static GSTBUF_LIST* bcmdec_rem_padbuf(GstBcmDec *filter); G_END_DECLS #endif /* __GST_BCMDEC_H__ */ crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/src/decif.h0000644000175000017500000000421311610313111024075 0ustar andresandres/******************************************************************** * Copyright(c) 2008 Broadcom Corporation. * * Name: decif.h * * Description: Devic Interface API. * * AU * * HISTORY: * ******************************************************************* * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #ifndef __BCMDECIF_H__ #define __BCMDECIF_H__ #include "bc_dts_defs.h" #include "libcrystalhd_if.h" #define PROC_TIMEOUT 3000 #define ALIGN_BUF_SIZE (512*1024) struct _DecIf { HANDLE hdev; }; typedef struct _DecIf BcmDecIF; BC_STATUS decif_getcaps(BcmDecIF *decif, BC_HW_CAPS *hwCaps); BC_STATUS decif_open(BcmDecIF * decif); BC_STATUS decif_close(BcmDecIF * decif); BC_STATUS decif_prepare_play(BcmDecIF* decif); BC_STATUS decif_start_play(BcmDecIF * decif); BC_STATUS decif_pause(BcmDecIF * decif,gboolean pause); BC_STATUS decif_stop(BcmDecIF * decif); BC_STATUS decif_flush_dec(BcmDecIF * decif,gint8 flush_type); BC_STATUS decif_flush_rxbuf(BcmDecIF * decif,gboolean discard_only); BC_STATUS decif_send_buffer(BcmDecIF * decif,guint8* buffer,guint32 size,GstClockTime time_stamp,guint8 flags); BC_STATUS decif_setcolorspace(BcmDecIF * decif, BC_OUTPUT_FORMAT mode); BC_STATUS decif_get_drv_status(BcmDecIF * decif, gboolean* suspended, guint32 *rll, guint32 *picNumFlags); BC_STATUS decif_get_eos(BcmDecIF *decif, gboolean *bEOS); BC_STATUS decif_decode_catchup(BcmDecIF * decif, gboolean catchup); BC_STATUS decif_setinputformat(BcmDecIF *decif, BC_INPUT_FORMAT bcInputFormat); #endif crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/src/gstbcmdec.c0000644000175000017500000023112711610313111024757 0ustar andresandres/******************************************************************** * Copyright(c) 2008 Broadcom Corporation. * * Name: gstbcmdec.c * * Description: Broadcom 70012 decoder plugin * * AU * * HISTORY: * ******************************************************************* * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #ifdef HAVE_CONFIG_H #include #endif #include #include "decif.h" #include "parse.h" #include "gstbcmdec.h" GST_DEBUG_CATEGORY_STATIC (gst_bcmdec_debug); #define GST_CAT_DEFAULT gst_bcmdec_debug //#define YV12__ //#define FILE_DUMP__ 1 static GstFlowReturn bcmdec_send_buff_detect_error(GstBcmDec *bcmdec, GstBuffer *buf, guint8* pbuffer, guint32 size, guint32 offset, GstClockTime tCurrent, guint8 flags) { BC_STATUS sts = BC_STS_SUCCESS; GST_DEBUG_OBJECT(bcmdec, "Attempting to Send Buffer"); sts = decif_send_buffer(&bcmdec->decif, pbuffer, size, tCurrent, flags); if (sts != BC_STS_SUCCESS) { GST_ERROR_OBJECT(bcmdec, "proc input failed sts = %d", sts); GST_ERROR_OBJECT(bcmdec, "Chain: timeStamp = %llu size = %d data = %p", GST_BUFFER_TIMESTAMP(buf), GST_BUFFER_SIZE(buf), GST_BUFFER_DATA (buf)); return GST_FLOW_ERROR; } return GST_FLOW_OK; } /* bcmdec signals and args */ enum { /* FILL ME */ LAST_SIGNAL }; enum { PROP_0, PROP_SILENT }; GLB_INST_STS *g_inst_sts = NULL; /* * the capabilities of the inputs and outputs. * * describe the real formats here. */ GstStaticPadTemplate sink_factory_bcm70015 = GST_STATIC_PAD_TEMPLATE("sink", GST_PAD_SINK, GST_PAD_ALWAYS, GST_STATIC_CAPS("video/mpeg, " "mpegversion = (int) {2, 4}," "systemstream =(boolean) false; " "video/x-h264;" "video/x-vc1;" "video/x-wmv, " "wmvversion = (int) {3};" "video/x-msmpeg, " "msmpegversion = (int) {43};" "video/x-divx, " "divxversion = (int) {3, 4, 5};" "video/x-xvid;")); GstStaticPadTemplate sink_factory_bcm70012 = GST_STATIC_PAD_TEMPLATE("sink", GST_PAD_SINK, GST_PAD_ALWAYS, GST_STATIC_CAPS("video/mpeg, " "mpegversion = (int) {2}," "systemstream =(boolean) false; " "video/x-h264;" "video/x-vc1;" "video/x-wmv, " "wmvversion = (int) {3};")); #ifdef YV12__ static GstStaticPadTemplate src_factory = GST_STATIC_PAD_TEMPLATE("src", GST_PAD_SRC, GST_PAD_ALWAYS, GST_STATIC_CAPS("video/x-raw-yuv, " "format = (fourcc) { YV12 }, " "width = (int) [ 1, MAX ], " "height = (int) [ 1, MAX ], " "framerate = (fraction) [ 0/1, 2147483647/1 ]")); #define BUF_MULT (12 / 8) #define BUF_MODE MODE420 #else static GstStaticPadTemplate src_factory = GST_STATIC_PAD_TEMPLATE("src", GST_PAD_SRC, GST_PAD_ALWAYS, GST_STATIC_CAPS("video/x-raw-yuv, " "format = (fourcc) { YUY2 } , " "framerate = (fraction) [0,MAX], " "width = (int) [1,MAX], " "height = (int) [1,MAX]; " "video/x-raw-yuv, " "format = (fourcc) { UYVY } , " "framerate = (fraction) [0,MAX], " "width = (int) [1,MAX], " "height = (int) [1,MAX]; ")); #define BUF_MULT (16 / 8) #define BUF_MODE MODE422_YUY2 #endif GST_BOILERPLATE(GstBcmDec, gst_bcmdec, GstElement, GST_TYPE_ELEMENT); /* GObject vmethod implementations */ static void gst_bcmdec_base_init(gpointer gclass) { static GstElementDetails element_details; BC_HW_CAPS hwCaps; GST_DEBUG_OBJECT(gclass, "gst_bcmdec_base_init"); element_details.klass = (gchar *)"Codec/Decoder/Video"; element_details.longname = (gchar *)"Generic Video Decoder"; element_details.description = (gchar *)"Decodes various Video Formats using CrystalHD Decoders"; element_details.author = (gchar *)"Broadcom Corp."; GstElementClass *element_class = GST_ELEMENT_CLASS(gclass); hwCaps.DecCaps = 0; decif_getcaps(NULL, &hwCaps); gst_element_class_add_pad_template(element_class, gst_static_pad_template_get (&src_factory)); if(hwCaps.DecCaps & BC_DEC_FLAGS_M4P2) { GST_DEBUG_OBJECT(gclass, "Found M4P2 support"); gst_element_class_add_pad_template(element_class, gst_static_pad_template_get (&sink_factory_bcm70015)); } else gst_element_class_add_pad_template(element_class, gst_static_pad_template_get (&sink_factory_bcm70012)); gst_element_class_set_details(element_class, &element_details); } /* initialize the bcmdec's class */ static void gst_bcmdec_class_init(GstBcmDecClass *klass) { GObjectClass *gobject_class; GstElementClass *gstelement_class; gobject_class = (GObjectClass *)klass; gstelement_class = (GstElementClass *)klass; GST_DEBUG_OBJECT(klass, "gst_bcmdec_class_init"); gstelement_class->change_state = gst_bcmdec_change_state; gobject_class->set_property = gst_bcmdec_set_property; gobject_class->get_property = gst_bcmdec_get_property; gobject_class->finalize = gst_bcmdec_finalize; g_object_class_install_property(gobject_class, PROP_SILENT, g_param_spec_boolean("silent", "Silent", "Produce verbose output ?", FALSE, (GParamFlags)G_PARAM_READWRITE)); } /* * initialize the new element * instantiate pads and add them to element * set pad calback functions * initialize instance structure */ static void gst_bcmdec_init(GstBcmDec *bcmdec, GstBcmDecClass *gclass) { pid_t pid; BC_STATUS sts = BC_STS_SUCCESS; int shmid = 0; BC_HW_CAPS hwCaps; GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_init"); bcmdec_reset(bcmdec); hwCaps.DecCaps = 0; sts = decif_getcaps(&bcmdec->decif, &hwCaps); if(hwCaps.DecCaps & BC_DEC_FLAGS_M4P2) { bcmdec->sinkpad = gst_pad_new_from_static_template(&sink_factory_bcm70015, "sink"); } else bcmdec->sinkpad = gst_pad_new_from_static_template(&sink_factory_bcm70012, "sink"); gst_pad_set_event_function(bcmdec->sinkpad, GST_DEBUG_FUNCPTR(gst_bcmdec_sink_event)); gst_pad_set_setcaps_function(bcmdec->sinkpad, GST_DEBUG_FUNCPTR(gst_bcmdec_sink_set_caps)); gst_pad_set_getcaps_function(bcmdec->sinkpad, GST_DEBUG_FUNCPTR(gst_bcmdec_getcaps)); gst_pad_set_chain_function(bcmdec->sinkpad, GST_DEBUG_FUNCPTR(gst_bcmdec_chain)); bcmdec->srcpad = gst_pad_new_from_static_template (&src_factory, "src"); gst_pad_set_getcaps_function(bcmdec->srcpad, GST_DEBUG_FUNCPTR(gst_bcmdec_getcaps)); gst_pad_set_event_function(bcmdec->srcpad, GST_DEBUG_FUNCPTR(gst_bcmdec_src_event)); gst_pad_use_fixed_caps(bcmdec->srcpad); bcmdec_negotiate_format(bcmdec); gst_element_add_pad(GST_ELEMENT(bcmdec), bcmdec->sinkpad); gst_element_add_pad(GST_ELEMENT(bcmdec), bcmdec->srcpad); bcmdec->silent = FALSE; pid = getpid(); GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_init _-- PID = %x",pid); sts = bcmdec_create_shmem(bcmdec, &shmid); GST_DEBUG_OBJECT(bcmdec, "bcmdec_create_shmem _-- Sts = %x",sts); } /* plugin close function*/ static void gst_bcmdec_finalize(GObject *object) { GstBcmDec *bcmdec = GST_BCMDEC(object); bcmdec_del_shmem(bcmdec); /*gst_bcmdec_cleanup(bcmdec);*/ GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_finalize"); G_OBJECT_CLASS(parent_class)->finalize(object); } static void gst_bcmdec_set_property(GObject *object, guint prop_id, const GValue *value, GParamSpec *pspec) { GstBcmDec *bcmdec = GST_BCMDEC(object); switch (prop_id) { case PROP_SILENT: bcmdec->silent = g_value_get_boolean (value); GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_set_property PROP_SILENT"); break; default: G_OBJECT_WARN_INVALID_PROPERTY_ID(object, prop_id, pspec); break; } if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_set_property"); } static void gst_bcmdec_get_property(GObject *object, guint prop_id, GValue *value, GParamSpec *pspec) { GstBcmDec *bcmdec = GST_BCMDEC(object); switch (prop_id) { case PROP_SILENT: g_value_set_boolean (value, bcmdec->silent); GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_get_property PROP_SILENT"); break; default: G_OBJECT_WARN_INVALID_PROPERTY_ID (object, prop_id, pspec); break; } if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_get_property"); } /* GstElement vmethod implementations */ static gboolean gst_bcmdec_sink_event(GstPad* pad, GstEvent* event) { GstBcmDec *bcmdec; BC_STATUS sts = BC_STS_SUCCESS; bcmdec = GST_BCMDEC(gst_pad_get_parent(pad)); gboolean result = TRUE; switch (GST_EVENT_TYPE(event)) { case GST_EVENT_NEWSEGMENT: GstFormat newsegment_format; gint64 newsegment_start; gst_event_parse_new_segment(event, NULL, NULL, &newsegment_format, &newsegment_start, NULL, NULL); bcmdec->base_clock_time = newsegment_start; bcmdec->cur_stream_time = 0; if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "new segment"); bcmdec->codec_params.inside_buffer = TRUE; bcmdec->codec_params.consumed_offset = 0; bcmdec->codec_params.strtcode_offset = 0; bcmdec->codec_params.nal_sz = 0; bcmdec->insert_pps = TRUE; bcmdec->base_time = 0; bcmdec->spes_frame_cnt = 0; bcmdec->catchup_on = FALSE; bcmdec->last_output_spes_time = 0; bcmdec->last_spes_time = 0; result = gst_pad_push_event(bcmdec->srcpad, event); break; case GST_EVENT_FLUSH_START: GST_DEBUG_OBJECT(bcmdec, "Flush Start"); #if 0 pthread_mutex_lock(&bcmdec->fn_lock); if (!g_inst_sts->waiting) /*in case of playback process waiting*/ bcmdec_process_flush_start(bcmdec); pthread_mutex_unlock(&bcmdec->fn_lock); #endif bcmdec_process_flush_start(bcmdec); result = gst_pad_push_event(bcmdec->srcpad, event); break; case GST_EVENT_FLUSH_STOP: if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "Flush Stop"); //if (!g_inst_sts->waiting) // bcmdec_process_flush_stop(bcmdec); bcmdec_process_flush_stop(bcmdec); result = gst_pad_push_event(bcmdec->srcpad, event); break; case GST_EVENT_EOS: if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "EOS on sink pad"); sts = decif_flush_dec(&bcmdec->decif, 0); GST_DEBUG_OBJECT(bcmdec, "dec_flush ret = %d", sts); bcmdec->ev_eos = event; gst_event_ref(bcmdec->ev_eos); break; default: result = gst_pad_push_event(bcmdec->srcpad, event); GST_DEBUG_OBJECT(bcmdec, "unhandled event on sink pad"); break; } gst_object_unref(bcmdec); if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_sink_event %u", GST_EVENT_TYPE(event)); return result; } static GstCaps *gst_bcmdec_getcaps (GstPad * pad) { return gst_caps_copy (gst_pad_get_pad_template_caps (pad)); } /* this function handles the link with other elements */ static gboolean gst_bcmdec_sink_set_caps(GstPad *pad, GstCaps *caps) { GstBcmDec *bcmdec; bcmdec = GST_BCMDEC(gst_pad_get_parent(pad)); GstStructure *structure; GstCaps *intersection; const gchar *mime; guint num = 0; guint den = 0; const GValue *g_value; int version = 0; GstBuffer *buffer; guint8 *data; guint size; guint index; GST_DEBUG_OBJECT (pad, "setcaps called"); intersection = gst_caps_intersect(gst_pad_get_pad_template_caps(pad), caps); GST_DEBUG_OBJECT(bcmdec, "Intersection return %", GST_PTR_FORMAT, intersection); if (gst_caps_is_empty(intersection)) { GST_ERROR_OBJECT(bcmdec, "setscaps:caps empty"); gst_object_unref(bcmdec); return FALSE; } gst_caps_unref(intersection); structure = gst_caps_get_structure(caps, 0); mime = gst_structure_get_name(structure); if (!strcmp("video/x-h264", mime)) { bcmdec->input_format = BC_MSUBTYPE_AVC1; // GStreamer uses the bit-stream format so have to add start codes // We might override this later down below if the codec_data indicates otherwise // So don't print codec type yet GST_DEBUG_OBJECT(bcmdec, "InFmt H.264"); } else if (!strcmp("video/mpeg", mime)) { gst_structure_get_int(structure, "mpegversion", &version); if (version == 2) { bcmdec->input_format = BC_MSUBTYPE_MPEG2VIDEO; GST_DEBUG_OBJECT(bcmdec, "InFmt MPEG2"); } else if (version == 4) { bcmdec->input_format = BC_MSUBTYPE_DIVX; GST_DEBUG_OBJECT(bcmdec, "InFmt MPEG4"); } else { gst_object_unref(bcmdec); return FALSE; } } else if (!strcmp("video/x-vc1", mime)) { bcmdec->input_format = BC_MSUBTYPE_VC1; GST_DEBUG_OBJECT(bcmdec, "InFmt VC1"); } else if (!strcmp("video/x-divx", mime)) { gst_structure_get_int(structure, "divxversion", &version); if(version == 3) { bcmdec->input_format = BC_MSUBTYPE_DIVX311; GST_DEBUG_OBJECT(bcmdec, "InFmt DIVX3"); } else { bcmdec->input_format = BC_MSUBTYPE_DIVX; GST_DEBUG_OBJECT(bcmdec, "InFmt DIVX%d", version); } } else if (!strcmp("video/x-xvid", mime)) { bcmdec->input_format = BC_MSUBTYPE_DIVX; GST_DEBUG_OBJECT(bcmdec, "InFmt XVID"); } else if (!strcmp("video/x-msmpeg", mime)) { bcmdec->input_format = BC_MSUBTYPE_DIVX311; GST_DEBUG_OBJECT(bcmdec, "InFmt MPMPEGv43"); } else if (!strcmp("video/x-wmv", mime)) { gst_structure_get_int(structure, "wmvversion", &version); if(version == 3) { bcmdec->input_format = BC_MSUBTYPE_WMV3; GST_DEBUG_OBJECT(bcmdec, "InFmt WMV9"); } else { gst_object_unref(bcmdec); return FALSE; } } else { GST_DEBUG_OBJECT(bcmdec, "unknown mime %s", mime); gst_object_unref(bcmdec); return FALSE; } g_value = gst_structure_get_value(structure, "framerate"); if (g_value != NULL) { num = gst_value_get_fraction_numerator(g_value); den = gst_value_get_fraction_denominator(g_value); bcmdec->input_framerate = (double)num / den; GST_LOG_OBJECT(bcmdec, "demux frame rate = %f ", bcmdec->input_framerate); } else { GST_DEBUG_OBJECT(bcmdec, "no demux framerate_value"); } g_value = gst_structure_get_value(structure, "pixel-aspect-ratio"); if (g_value) { bcmdec->input_par_x = gst_value_get_fraction_numerator(g_value); bcmdec->input_par_y = gst_value_get_fraction_denominator(g_value); GST_DEBUG_OBJECT(bcmdec, "sink caps have pixel-aspect-ratio of %d:%d", bcmdec->input_par_x, bcmdec->input_par_y); if (bcmdec->input_par_x > 5 * bcmdec->input_par_y) { bcmdec->input_par_x = 1; bcmdec->input_par_y = 1; GST_DEBUG_OBJECT(bcmdec, "demux par reset"); } } else { GST_DEBUG_OBJECT (bcmdec, "no par from demux"); } gst_structure_get_int(structure, "width", &bcmdec->frame_width); gst_structure_get_int(structure, "height", &bcmdec->frame_height); // Check Codec Data for various codecs // Determine if this is bitstream video (AVC1 or no start codes) or Byte stream video (H264) // Determine if this is VC-1 AP or SP/MP for VC-1 if ((g_value = gst_structure_get_value (structure, "codec_data"))) { if (G_VALUE_TYPE(g_value) == GST_TYPE_BUFFER) { if (!strcmp("video/x-h264", mime)) { GST_DEBUG_OBJECT (bcmdec, "Don't have start codes'"); bcmdec->input_format = BC_MSUBTYPE_AVC1; GST_DEBUG_OBJECT(bcmdec, "InFmt H.264 (AVC1)"); buffer = gst_value_get_buffer(g_value); data = GST_BUFFER_DATA(buffer); size = GST_BUFFER_SIZE(buffer); GST_DEBUG_OBJECT(bcmdec, "codec_data size = %d", size); /* parse the avcC data */ if (size < 7) { GST_ERROR_OBJECT(bcmdec, "avcC size %u < 7", size); goto avcc_error; } /* parse the version, this must be 1 */ if (data[0] != 1) goto wrong_version; if (bcmdec->codec_params.sps_pps_buf == NULL) bcmdec->codec_params.sps_pps_buf = (guint8 *)malloc(size * 2); if (bcmdec_insert_sps_pps(bcmdec, buffer) != BC_STS_SUCCESS) { bcmdec->codec_params.pps_size = 0; } } else if (!strcmp("video/x-wmv", mime)) { buffer = gst_value_get_buffer(g_value); data = GST_BUFFER_DATA(buffer); size = GST_BUFFER_SIZE(buffer); GST_DEBUG_OBJECT(bcmdec, "codec_data size = %d", size); if (size == 4) { // Simple or Main Profile bcmdec->input_format = BC_MSUBTYPE_WMV3; GST_DEBUG_OBJECT(bcmdec, "InFmt VC-1 (SP/MP)"); if (bcmdec->codec_params.sps_pps_buf == NULL) bcmdec->codec_params.sps_pps_buf = (guint8 *)malloc(4); memcpy(bcmdec->codec_params.sps_pps_buf, data, 4); bcmdec->codec_params.pps_size = 4; } else { bcmdec->input_format = BC_MSUBTYPE_VC1; GST_DEBUG_OBJECT(bcmdec, "InFmt VC-1 (AP)"); for (index = 0; index < size; index++) { data += index; if (((size - index) >= 4) && (*data == 0x00) && (*(data + 1) == 0x00) && (*(data + 2) == 0x01) && (*(data + 3) == 0x0f)) { GST_DEBUG_OBJECT(bcmdec, "VC1 Sequence Header Found for Adv Profile"); if ((size - index + 1) > MAX_ADV_PROF_SEQ_HDR_SZ) bcmdec->codec_params.pps_size = MAX_ADV_PROF_SEQ_HDR_SZ; else bcmdec->codec_params.pps_size = size - index + 1; memcpy(bcmdec->codec_params.sps_pps_buf, data, bcmdec->codec_params.pps_size); break; } } } } } } else { if (!strcmp("video/x-h264", mime)) { GST_DEBUG_OBJECT (bcmdec, "Have start codes'"); bcmdec->input_format = BC_MSUBTYPE_H264; GST_DEBUG_OBJECT(bcmdec, "InFmt H.264 (H264)");; bcmdec->codec_params.nal_size_bytes = 4; // 4 sync bytes used } else { // No Codec data. So try with FourCC for VC1/WMV9 if (!strcmp("video/x-wmv", mime)) { guint32 fourcc; if (gst_structure_get_fourcc (structure, "format", &fourcc)) { if ((fourcc == GST_MAKE_FOURCC ('W', 'V', 'C', '1')) || (fourcc == GST_MAKE_FOURCC ('W', 'M', 'V', 'A'))) { bcmdec->input_format = BC_MSUBTYPE_VC1; GST_DEBUG_OBJECT(bcmdec, "InFmt VC-1 (AP)"); } else { GST_DEBUG_OBJECT(bcmdec, "no codec_data. Don't know how to handle"); gst_object_unref(bcmdec); return FALSE; } } } else if(bcmdec->input_format == BC_MSUBTYPE_MPEG2VIDEO) { // For MPEG-2 don't need any additional codec_data is most cases GST_DEBUG_OBJECT(bcmdec, "no codec_data for MPEG-2. Trying to decode anyway"); } else if(bcmdec->input_format == BC_MSUBTYPE_DIVX){ // For DIVX don't need any additional codec_data is most cases GST_DEBUG_OBJECT(bcmdec, "no codec_data for MPEG-4. Trying to decode anyway"); } else { GST_DEBUG_OBJECT(bcmdec, "no codec_data. Don't know how to handle"); gst_object_unref(bcmdec); return FALSE; } } } if (bcmdec->play_pending) { bcmdec->play_pending = FALSE; bcmdec_process_play(bcmdec); } gst_object_unref(bcmdec); return TRUE; /* ERRORS */ avcc_error: { gst_object_unref(bcmdec); return FALSE; } wrong_version: { GST_ERROR_OBJECT(bcmdec, "wrong avcC version"); gst_object_unref(bcmdec); return FALSE; } } void bcmdec_msleep(gint msec) { gint cnt = msec; while (cnt) { usleep(1000); cnt--; } } /* * chain function * this function does the actual processing */ static GstFlowReturn gst_bcmdec_chain(GstPad *pad, GstBuffer *buf) { GstBcmDec *bcmdec; // BC_STATUS sts = BC_STS_SUCCESS; guint32 offset = 0; GstClockTime tCurrent = 0; guint8 *pbuffer; guint32 size = 0; // guint32 vc1_buff_sz = 0; #ifdef FILE_DUMP__ guint32 bytes_written =0; #endif bcmdec = GST_BCMDEC (GST_OBJECT_PARENT (pad)); #ifdef FILE_DUMP__ if (bcmdec->fhnd == NULL) bcmdec->fhnd = fopen("dump2.264", "a+"); #endif if (bcmdec->flushing) { GST_DEBUG_OBJECT(bcmdec, "input while flushing"); gst_buffer_unref(buf); return GST_FLOW_OK; } if (GST_CLOCK_TIME_NONE != GST_BUFFER_TIMESTAMP(buf)) { if (bcmdec->base_time == 0) { bcmdec->base_time = GST_BUFFER_TIMESTAMP(buf); GST_DEBUG_OBJECT(bcmdec, "base time is set to %llu", bcmdec->base_time / 1000000); } tCurrent = GST_BUFFER_TIMESTAMP(buf); } if (bcmdec->play_pending) { bcmdec->play_pending = FALSE; bcmdec_process_play(bcmdec); } else if (!bcmdec->streaming) { GST_DEBUG_OBJECT(bcmdec, "input while streaming is false"); gst_buffer_unref(buf); return GST_FLOW_WRONG_STATE; } pbuffer = GST_BUFFER_DATA (buf); size = GST_BUFFER_SIZE(buf); if (GST_FLOW_OK != bcmdec_send_buff_detect_error(bcmdec, buf, pbuffer, size, offset, tCurrent, bcmdec->proc_in_flags)) { gst_buffer_unref(buf); return GST_FLOW_ERROR; } #ifdef FILE_DUMP__ bytes_written = fwrite(GST_BUFFER_DATA(buf), sizeof(unsigned char), GST_BUFFER_SIZE(buf), bcmdec->fhnd); #endif gst_buffer_unref(buf); return GST_FLOW_OK; } static gboolean gst_bcmdec_src_event(GstPad *pad, GstEvent *event) { gboolean result; GstBcmDec *bcmdec; bcmdec = GST_BCMDEC(GST_OBJECT_PARENT(pad)); result = gst_pad_push_event(bcmdec->sinkpad, event); return result; } static gboolean bcmdec_negotiate_format(GstBcmDec *bcmdec) { GstCaps *caps; gboolean result; guint num = (guint)(bcmdec->output_params.framerate * 1000); guint den = 1000; GstStructure *s1; const GValue *framerate_value; GstVideoFormat vidFmt; #ifdef YV12__ vidFmt = GST_VIDEO_FORMAT_YV12; #else vidFmt = GST_VIDEO_FORMAT_YUY2; #endif GST_DEBUG_OBJECT(bcmdec, "framerate = %f", bcmdec->output_params.framerate); if(bcmdec->interlace) { caps = gst_video_format_new_caps_interlaced(vidFmt, bcmdec->output_params.width, bcmdec->output_params.height, num, den, bcmdec->output_params.aspectratio_x, bcmdec->output_params.aspectratio_y, TRUE); } else { caps = gst_video_format_new_caps(vidFmt, bcmdec->output_params.width, bcmdec->output_params.height, num, den, bcmdec->output_params.aspectratio_x, bcmdec->output_params.aspectratio_y); } result = gst_pad_set_caps(bcmdec->srcpad, caps); GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_negotiate_format %d", result); if (bcmdec->output_params.clr_space == MODE422_YUY2) { bcmdec->output_params.y_size = bcmdec->output_params.width * bcmdec->output_params.height * BUF_MULT; if (bcmdec->interlace) { GST_DEBUG_OBJECT(bcmdec, "bcmdec_negotiate_format Interlaced"); bcmdec->output_params.y_size /= 2; } bcmdec->output_params.uv_size = 0; GST_DEBUG_OBJECT(bcmdec, "YUY2 set on caps"); } else if (bcmdec->output_params.clr_space == MODE420) { bcmdec->output_params.y_size = bcmdec->output_params.width * bcmdec->output_params.height; bcmdec->output_params.uv_size = bcmdec->output_params.width * bcmdec->output_params.height / 2; #ifdef YV12__ if (bcmdec->interlace) { GST_DEBUG_OBJECT(bcmdec, "bcmdec_negotiate_format Interlaced"); bcmdec->output_params.y_size = bcmdec->output_params.width * bcmdec->output_params.height / 2; bcmdec->output_params.uv_size = bcmdec->output_params.y_size / 2; } #endif GST_DEBUG_OBJECT(bcmdec, "420 set on caps"); } s1 = gst_caps_get_structure(caps, 0); framerate_value = gst_structure_get_value(s1, "framerate"); if (framerate_value != NULL) { num = gst_value_get_fraction_numerator(framerate_value); den = gst_value_get_fraction_denominator(framerate_value); GST_DEBUG_OBJECT(bcmdec, "framerate = %f rate_num %d rate_den %d", bcmdec->output_params.framerate, num, den); } else { GST_DEBUG_OBJECT(bcmdec, "failed to get framerate_value"); } framerate_value = gst_structure_get_value (s1, "pixel-aspect-ratio"); if (framerate_value) { num = gst_value_get_fraction_numerator(framerate_value); den = gst_value_get_fraction_denominator(framerate_value); GST_DEBUG_OBJECT(bcmdec, "pixel-aspect-ratio_x = %d y %d ", num, den); } else { GST_DEBUG_OBJECT(bcmdec, "failed to get par"); } gst_caps_unref(caps); return result; } static gboolean bcmdec_process_play(GstBcmDec *bcmdec) { BC_STATUS sts = BC_STS_SUCCESS; BC_INPUT_FORMAT bcInputFormat; GST_DEBUG_OBJECT(bcmdec, "Starting Process Play"); bcInputFormat.OptFlags = 0; // NAREN - FIXME - Should we enable BD mode and max frame rate mode for LINK? bcInputFormat.FGTEnable = FALSE; bcInputFormat.MetaDataEnable = FALSE; bcInputFormat.Progressive = !(bcmdec->interlace); bcInputFormat.mSubtype= bcmdec->input_format; //Use Demux Image Size for VC-1 Simple/Main and for DIVX311 if(bcInputFormat.mSubtype == BC_MSUBTYPE_WMV3 || bcInputFormat.mSubtype == BC_MSUBTYPE_DIVX311) { //VC-1 Simple/Main bcInputFormat.width = bcmdec->frame_width; bcInputFormat.height = bcmdec->frame_height; } else { bcInputFormat.width = bcmdec->output_params.width; bcInputFormat.height = bcmdec->output_params.height; } bcInputFormat.startCodeSz = bcmdec->codec_params.nal_size_bytes; bcInputFormat.pMetaData = bcmdec->codec_params.sps_pps_buf; bcInputFormat.metaDataSz = bcmdec->codec_params.pps_size; bcInputFormat.OptFlags = 0x80000000 | vdecFrameRate23_97; // ENABLE the Following lines if HW Scaling is desired bcInputFormat.bEnableScaling = false; // bcInputFormat.ScalingParams.sWidth = 800; sts = decif_setinputformat(&bcmdec->decif, bcInputFormat); if (sts == BC_STS_SUCCESS) { GST_DEBUG_OBJECT(bcmdec, "set input format success"); } else { GST_ERROR_OBJECT(bcmdec, "set input format failed"); bcmdec->streaming = FALSE; return FALSE; } sts = decif_prepare_play(&bcmdec->decif); if (sts == BC_STS_SUCCESS) { GST_DEBUG_OBJECT(bcmdec, "prepare play success"); } else { GST_ERROR_OBJECT(bcmdec, "prepare play failed"); bcmdec->streaming = FALSE; return FALSE; } GST_DEBUG_OBJECT(bcmdec, "Setting color space %d", BUF_MODE); decif_setcolorspace(&bcmdec->decif, BUF_MODE); sts = decif_start_play(&bcmdec->decif); if (sts == BC_STS_SUCCESS) { GST_DEBUG_OBJECT(bcmdec, "start play success"); bcmdec->streaming = TRUE; } else { GST_ERROR_OBJECT(bcmdec, "start play failed"); bcmdec->streaming = FALSE; return FALSE; } if (sem_post(&bcmdec->play_event) == -1) GST_ERROR_OBJECT(bcmdec, "sem_post failed"); if (sem_post(&bcmdec->push_start_event) == -1) GST_ERROR_OBJECT(bcmdec, "push_start post failed"); return TRUE; } static GstStateChangeReturn gst_bcmdec_change_state(GstElement *element, GstStateChange transition) { GstStateChangeReturn result = GST_STATE_CHANGE_SUCCESS; GstBcmDec *bcmdec = GST_BCMDEC(element); BC_STATUS sts = BC_STS_SUCCESS; int ret = 0; switch (transition) { case GST_STATE_CHANGE_NULL_TO_READY: GST_DEBUG_OBJECT(bcmdec, "State change from NULL_TO_READY"); if (bcmdec_mul_inst_cor(bcmdec)) { sts = decif_open(&bcmdec->decif); if (sts == BC_STS_SUCCESS) { GST_DEBUG_OBJECT(bcmdec, "dev open success"); parse_init(&bcmdec->parse); } else { GST_ERROR_OBJECT(bcmdec, "dev open failed %d",sts); GST_ERROR_OBJECT(bcmdec, "dev open failed...ret GST_STATE_CHANGE_FAILURE"); return GST_STATE_CHANGE_FAILURE; } } else { GST_ERROR_OBJECT(bcmdec, "dev open failed...ret GST_STATE_CHANGE_FAILURE"); return GST_STATE_CHANGE_FAILURE; } break; case GST_STATE_CHANGE_READY_TO_PAUSED: if (!bcmdec_start_recv_thread(bcmdec)) { GST_ERROR_OBJECT(bcmdec, "GST_STATE_CHANGE_NULL_TO_READY -failed"); return GST_STATE_CHANGE_FAILURE; } if (!bcmdec_start_push_thread(bcmdec)) { GST_ERROR_OBJECT(bcmdec, "GST_STATE_CHANGE_READY_TO_THREAD -failed"); return GST_STATE_CHANGE_FAILURE; } if (!bcmdec_start_get_rbuf_thread(bcmdec)) { GST_ERROR_OBJECT(bcmdec, "GST_STATE_CHANGE_THREAD_TO_RBUF -failed"); return GST_STATE_CHANGE_FAILURE; } bcmdec->play_pending = TRUE; GST_DEBUG_OBJECT(bcmdec, "GST_STATE_CHANGE_READY_TO_PAUSED"); break; case GST_STATE_CHANGE_PAUSED_TO_PLAYING: GST_DEBUG_OBJECT(bcmdec, "GST_STATE_CHANGE_PAUSED_TO_PLAYING"); bcmdec->gst_clock = gst_element_get_clock(element); if (bcmdec->gst_clock) { #if 0 GstClockTime clock_time, base_clock_time; printf("clock available %p\n",bcmdec->gst_clock); base_clock_time = gst_element_get_base_time(element); printf("base clock time %lld\n",base_clock_time); clock_time = gst_clock_get_time(bcmdec->gst_clock); printf(" clock time %lld\n",clock_time); #endif } break; case GST_STATE_CHANGE_PAUSED_TO_READY: GST_DEBUG_OBJECT(bcmdec, "GST_STATE_CHANGE_PAUSED_TO_READY"); bcmdec->streaming = FALSE; GST_DEBUG_OBJECT(bcmdec, "Flushing\n"); sts = decif_flush_dec(&bcmdec->decif, 2); if (sts != BC_STS_SUCCESS) GST_ERROR_OBJECT(bcmdec, "Dec flush failed %d",sts); if (!bcmdec->play_pending) { GST_DEBUG_OBJECT(bcmdec, "Stopping\n"); sts = decif_stop(&bcmdec->decif); if (sts == BC_STS_SUCCESS) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "stop play success"); g_inst_sts->cur_decode = UNKNOWN; g_inst_sts->rendered_frames = 0; GST_DEBUG_OBJECT(bcmdec, "cur_dec set to UNKNOWN"); } else { GST_ERROR_OBJECT(bcmdec, "stop play failed %d", sts); } } GST_DEBUG_OBJECT(bcmdec, "Stopping threads\n"); if (bcmdec->get_rbuf_thread) { GST_DEBUG_OBJECT(bcmdec, "rbuf stop event"); if (sem_post(&bcmdec->rbuf_stop_event) == -1) GST_ERROR_OBJECT(bcmdec, "sem_post failed"); GST_DEBUG_OBJECT(bcmdec, "waiting for get_rbuf_thread exit"); ret = pthread_join(bcmdec->get_rbuf_thread, NULL); GST_DEBUG_OBJECT(bcmdec, "get_rbuf_thread exit - %d errno = %d", ret, errno); bcmdec->get_rbuf_thread = 0; } if (bcmdec->recv_thread) { GST_DEBUG_OBJECT(bcmdec, "quit event"); if (sem_post(&bcmdec->quit_event) == -1) GST_ERROR_OBJECT(bcmdec, "sem_post failed"); GST_DEBUG_OBJECT(bcmdec, "waiting for rec_thread exit"); ret = pthread_join(bcmdec->recv_thread, NULL); GST_DEBUG_OBJECT(bcmdec, "thread exit - %d errno = %d", ret, errno); bcmdec->recv_thread = 0; } if (bcmdec->push_thread) { GST_DEBUG_OBJECT(bcmdec, "waiting for push_thread exit"); ret = pthread_join(bcmdec->push_thread, NULL); GST_DEBUG_OBJECT(bcmdec, "push_thread exit - %d errno = %d", ret, errno); bcmdec->push_thread = 0; } break; case GST_STATE_CHANGE_PLAYING_TO_PAUSED: GST_DEBUG_OBJECT(bcmdec, "GST_STATE_CHANGE_PLAYING_TO_PAUSED"); break; default: GST_DEBUG_OBJECT(bcmdec, "default %d", transition); break; } result = GST_ELEMENT_CLASS(parent_class)->change_state(element, transition); if (result == GST_STATE_CHANGE_FAILURE) { GST_ERROR_OBJECT(bcmdec, "parent class state change failed"); return result; } if(transition == GST_STATE_CHANGE_READY_TO_NULL) { GST_DEBUG_OBJECT(bcmdec, "GST_STATE_CHANGE_READY_TO_NULL"); sts = gst_bcmdec_cleanup(bcmdec); if (sts == BC_STS_SUCCESS) GST_DEBUG_OBJECT(bcmdec, "dev close success"); else GST_ERROR_OBJECT(bcmdec, "dev close failed %d", sts); } return result; } GstClockTime gst_get_current_timex (void) { GTimeVal tv; g_get_current_time(&tv); return GST_TIMEVAL_TO_TIME(tv); } clock_t bcm_get_tick_count() { tms tm; return times(&tm); } static gboolean bcmdec_get_buffer(GstBcmDec *bcmdec, GstBuffer **obuf) { GstFlowReturn ret; GST_DEBUG_OBJECT(bcmdec, "gst_pad_alloc_buffer_and_set_caps "); ret = gst_pad_alloc_buffer_and_set_caps(bcmdec->srcpad, GST_BUFFER_OFFSET_NONE, bcmdec->output_params.width * bcmdec->output_params.height * BUF_MULT, GST_PAD_CAPS (bcmdec->srcpad), obuf); if (ret != GST_FLOW_OK) { GST_ERROR_OBJECT(bcmdec, "gst_pad_alloc_buffer_and_set_caps failed %d ",ret); return FALSE; } if (((uintptr_t)GST_BUFFER_DATA(*obuf)) % 4) GST_DEBUG_OBJECT(bcmdec, "buf is not aligned"); return TRUE; } static void bcmdec_init_procout(GstBcmDec *bcmdec,BC_DTS_PROC_OUT* pout, guint8* buf) { // GSTREAMER only supports Interleaved mode for Interlaced content //if (bcmdec->format_reset) { memset(pout,0,sizeof(BC_DTS_PROC_OUT)); pout->PicInfo.width = bcmdec->output_params.width ; pout->PicInfo.height = bcmdec->output_params.height; pout->YbuffSz = bcmdec->output_params.y_size / 4; pout->UVbuffSz = bcmdec->output_params.uv_size / 4; pout->PoutFlags = BC_POUT_FLAGS_SIZE ; #ifdef YV12__ pout->PoutFlags |= BC_POUT_FLAGS_YV12; #endif if (bcmdec->interlace) pout->PoutFlags |= BC_POUT_FLAGS_INTERLACED; if ((bcmdec->output_params.stride) || (bcmdec->interlace)) { pout->PoutFlags |= BC_POUT_FLAGS_STRIDE ; if (bcmdec->interlace) pout->StrideSz = bcmdec->output_params.width + 2 * bcmdec->output_params.stride; else pout->StrideSz = bcmdec->output_params.stride; } // bcmdec->format_reset = FALSE; } pout->PoutFlags = pout->PoutFlags & 0xff; pout->Ybuff = (uint8_t*)buf; if (pout->UVbuffSz) { if (bcmdec->interlace) { pout->UVbuff = buf + bcmdec->output_params.y_size * 2; if (bcmdec->sec_field) { pout->Ybuff += bcmdec->output_params.width; pout->UVbuff += bcmdec->output_params.width / 2; } } else { pout->UVbuff = buf + bcmdec->output_params.y_size; } } else { pout->UVbuff = NULL; if (bcmdec->interlace) { if (bcmdec->sec_field) pout->Ybuff += bcmdec->output_params.width * 2; } } return; } static void bcmdec_set_framerate(GstBcmDec * bcmdec,guint32 nFrameRate) { gdouble framerate; // bcmdec->interlace = FALSE; framerate = (gdouble)nFrameRate / 1000; if((framerate) && (bcmdec->output_params.framerate != framerate)) { bcmdec->output_params.framerate = framerate; bcmdec->frame_time = (GstClockTime)(UNITS / bcmdec->output_params.framerate); //if (bcmdec->interlace) // bcmdec->output_params.framerate /= 2; GST_DEBUG_OBJECT(bcmdec, "framerate = %x", framerate); } } static void bcmdec_set_aspect_ratio(GstBcmDec *bcmdec, BC_PIC_INFO_BLOCK *pic_info) { switch (pic_info->aspect_ratio) { case vdecAspectRatioSquare: bcmdec->output_params.aspectratio_x = 1; bcmdec->output_params.aspectratio_y = 1; break; case vdecAspectRatio12_11: bcmdec->output_params.aspectratio_x = 12; bcmdec->output_params.aspectratio_y = 11; break; case vdecAspectRatio10_11: bcmdec->output_params.aspectratio_x = 10; bcmdec->output_params.aspectratio_y = 11; break; case vdecAspectRatio16_11: bcmdec->output_params.aspectratio_x = 16; bcmdec->output_params.aspectratio_y = 11; break; case vdecAspectRatio40_33: bcmdec->output_params.aspectratio_x = 40; bcmdec->output_params.aspectratio_y = 33; break; case vdecAspectRatio24_11: bcmdec->output_params.aspectratio_x = 24; bcmdec->output_params.aspectratio_y = 11; break; case vdecAspectRatio20_11: bcmdec->output_params.aspectratio_x = 20; bcmdec->output_params.aspectratio_y = 11; break; case vdecAspectRatio32_11: bcmdec->output_params.aspectratio_x = 32; bcmdec->output_params.aspectratio_y = 11; break; case vdecAspectRatio80_33: bcmdec->output_params.aspectratio_x = 80; bcmdec->output_params.aspectratio_y = 33; break; case vdecAspectRatio18_11: bcmdec->output_params.aspectratio_x = 18; bcmdec->output_params.aspectratio_y = 11; break; case vdecAspectRatio15_11: bcmdec->output_params.aspectratio_x = 15; bcmdec->output_params.aspectratio_y = 11; break; case vdecAspectRatio64_33: bcmdec->output_params.aspectratio_x = 64; bcmdec->output_params.aspectratio_y = 33; break; case vdecAspectRatio160_99: bcmdec->output_params.aspectratio_x = 160; bcmdec->output_params.aspectratio_y = 99; break; case vdecAspectRatio4_3: bcmdec->output_params.aspectratio_x = 4; bcmdec->output_params.aspectratio_y = 3; break; case vdecAspectRatio16_9: bcmdec->output_params.aspectratio_x = 16; bcmdec->output_params.aspectratio_y = 9; break; case vdecAspectRatio221_1: bcmdec->output_params.aspectratio_x = 221; bcmdec->output_params.aspectratio_y = 1; break; case vdecAspectRatioOther: bcmdec->output_params.aspectratio_x = pic_info->custom_aspect_ratio_width_height & 0x0000ffff; bcmdec->output_params.aspectratio_y = pic_info->custom_aspect_ratio_width_height >> 16; break; case vdecAspectRatioUnknown: default: bcmdec->output_params.aspectratio_x = 0; bcmdec->output_params.aspectratio_y = 0; break; } // Use Demux Aspect ratio first before falling back to HW ratio if(bcmdec->input_par_x != 0) { bcmdec->output_params.aspectratio_x = bcmdec->input_par_x; bcmdec->output_params.aspectratio_y = bcmdec->input_par_y; } else if (bcmdec->output_params.aspectratio_x == 0) { bcmdec->output_params.aspectratio_x = 1; bcmdec->output_params.aspectratio_y = 1; } GST_DEBUG_OBJECT(bcmdec, "dec_par x = %d", bcmdec->output_params.aspectratio_x); GST_DEBUG_OBJECT(bcmdec, "dec_par y = %d", bcmdec->output_params.aspectratio_y); } static gboolean bcmdec_format_change(GstBcmDec *bcmdec, BC_PIC_INFO_BLOCK *pic_info) { GST_DEBUG_OBJECT(bcmdec, "Got format Change to %dx%d", pic_info->width, pic_info->height); gboolean result = FALSE; if (pic_info->height == 1088) pic_info->height = 1080; bcmdec->output_params.width = pic_info->width; bcmdec->output_params.height = pic_info->height; bcmdec_set_aspect_ratio(bcmdec,pic_info); // Interlaced if((pic_info->flags & VDEC_FLAG_INTERLACED_SRC) == VDEC_FLAG_INTERLACED_SRC) bcmdec->interlace = true; else bcmdec->interlace = false; if( (bcmdec->input_format == BC_MSUBTYPE_AVC1) || (bcmdec->input_format == BC_MSUBTYPE_H264)) { if (!bcmdec->interlace && (pic_info->pulldown == vdecFrame_X1) && (pic_info->flags & VDEC_FLAG_FIELDPAIR) && (pic_info->flags & VDEC_FLAG_INTERLACED_SRC)) bcmdec->interlace = true; } result = bcmdec_negotiate_format(bcmdec); if (!bcmdec->silent) { if (result) GST_DEBUG_OBJECT(bcmdec, "negotiate_format success"); else GST_ERROR_OBJECT(bcmdec, "negotiate_format failed"); } //bcmdec->format_reset = TRUE; return result; } static int bcmdec_wait_for_event(GstBcmDec *bcmdec) { int ret = 0, i = 0; sem_t *event_list[] = { &bcmdec->play_event, &bcmdec->quit_event }; GST_DEBUG_OBJECT(bcmdec, "Waiting for event\n"); while (1) { for (i = 0; i < 2; i++) { ret = sem_trywait(event_list[i]); if (ret == 0) { GST_DEBUG_OBJECT(bcmdec, "event wait over in Rx thread ret = %d",i); return i; } else if (errno == EINTR) { break; } if (bcmdec->streaming) break; } usleep(10); } } static void bcmdec_flush_gstbuf_queue(GstBcmDec *bcmdec) { GSTBUF_LIST *gst_queue_element; int sval; do { gst_queue_element = bcmdec_rem_buf(bcmdec); if (gst_queue_element) { if (gst_queue_element->gstbuf) { gst_buffer_unref (gst_queue_element->gstbuf); bcmdec_put_que_mem_buf(bcmdec,gst_queue_element); } } else { GST_DEBUG_OBJECT(bcmdec, "no gst_queue_element"); } } while (gst_queue_element && gst_queue_element->gstbuf); // Re-initialize the buf_event semaphone since we have just flushed the entire queued sem_destroy(&bcmdec->buf_event); sem_init(&bcmdec->buf_event, 0, 0); sem_getvalue(&bcmdec->buf_event, &sval); GST_DEBUG_OBJECT(bcmdec, "sem value after flush is %d", sval); } static void * bcmdec_process_push(void *ctx) { GstBcmDec *bcmdec = (GstBcmDec *)ctx; GSTBUF_LIST *gst_queue_element = NULL; gboolean result = FALSE, done = FALSE; struct timespec ts; gint ret; ts.tv_sec = time(NULL); ts.tv_nsec = 30 * 1000000; if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "process push starting "); while (1) { if (!bcmdec->recv_thread && !bcmdec->streaming) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "process push exiting.."); break; } ret = sem_timedwait(&bcmdec->push_start_event, &ts); if (ret < 0) { if (errno == ETIMEDOUT) continue; else if (errno == EINTR) break; } else { GST_DEBUG_OBJECT(bcmdec, "push_start wait over"); done = FALSE; } ts.tv_sec = time(NULL) + 1; ts.tv_nsec = 0; while (bcmdec->streaming && !done) { ret = sem_timedwait(&bcmdec->buf_event, &ts); if (ret < 0) { switch (errno) { case ETIMEDOUT: if (bcmdec->streaming) { continue; } else { done = TRUE; GST_DEBUG_OBJECT(bcmdec, "TOB "); break; } case EINTR: GST_DEBUG_OBJECT(bcmdec, "Sig interrupt "); done = TRUE; break; default: GST_ERROR_OBJECT(bcmdec, "sem wait failed %d ", errno); done = TRUE; break; } } if (ret == 0) { GST_DEBUG_OBJECT(bcmdec, "Starting to PUSH "); gst_queue_element = bcmdec_rem_buf(bcmdec); if (gst_queue_element) { if (gst_queue_element->gstbuf) { GST_DEBUG_OBJECT(bcmdec, "Trying to PUSH "); result = gst_pad_push(bcmdec->srcpad, gst_queue_element->gstbuf); if (result != GST_FLOW_OK) { GST_DEBUG_OBJECT(bcmdec, "exiting, failed to push sts = %d", result); gst_buffer_unref(gst_queue_element->gstbuf); done = TRUE; } else { GST_DEBUG_OBJECT(bcmdec, "PUSHED, Qcnt:%d, Rcnt:%d", bcmdec->gst_que_cnt, bcmdec->gst_padbuf_que_cnt); if ((g_inst_sts->rendered_frames++ > THUMBNAIL_FRAMES) && (g_inst_sts->cur_decode != PLAYBACK)) { g_inst_sts->cur_decode = PLAYBACK; GST_DEBUG_OBJECT(bcmdec, "cur_dec set to PLAYBACK"); } } } else { /*exit */ /* NULL value of gstbuf indicates EOS */ gst_pad_push_event(bcmdec->srcpad, bcmdec->ev_eos); gst_event_unref(bcmdec->ev_eos); done = TRUE; bcmdec->streaming = FALSE; GST_DEBUG_OBJECT(bcmdec, "eos sent, cnt:%d", bcmdec->gst_que_cnt); } bcmdec_put_que_mem_buf(bcmdec, gst_queue_element); } else GST_DEBUG_OBJECT(bcmdec, "NO BUFFER FOUND"); } if (bcmdec->flushing && bcmdec->push_exit) { GST_DEBUG_OBJECT(bcmdec, "push -flush exit"); break; } } if (bcmdec->flushing) { GST_DEBUG_OBJECT(bcmdec, "flushing gstbuf queue"); bcmdec_flush_gstbuf_queue(bcmdec); if (sem_post(&bcmdec->push_stop_event) == -1) GST_ERROR_OBJECT(bcmdec, "push_stop sem_post failed"); g_inst_sts->rendered_frames = 0; } } bcmdec_flush_gstbuf_queue(bcmdec); GST_DEBUG_OBJECT(bcmdec, "process push exiting.. "); pthread_exit((void*)&result); } static void * bcmdec_process_output(void *ctx) { BC_DTS_PROC_OUT pout; BC_STATUS sts = BC_STS_SUCCESS; GstBcmDec *bcmdec = (GstBcmDec *)ctx; GstBuffer *gstbuf = NULL; gboolean rx_flush = FALSE, bEOS = FALSE; const guint first_picture = 3; guint32 pic_number = 0; GstClockTime clock_time = 0; gboolean first_frame_after_seek = FALSE; GstClockTime cur_stream_time_diff = 0; int wait_cnt = 0; guint32 nextPicNumFlags = 0; gboolean is_paused = FALSE; GSTBUF_LIST *gst_queue_element = NULL; if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "Rx thread started"); while (1) { if (1 == bcmdec_wait_for_event(bcmdec)) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "quit event set, exit"); break; } GST_DEBUG_OBJECT(bcmdec, "wait over streaming = %d", bcmdec->streaming); while (bcmdec->streaming && !bcmdec->last_picture_set) { GST_DEBUG_OBJECT(bcmdec, "Getting Status"); // NAREN FIXME - This is HARDCODED right now till we get HW PAUSE and RESUME working from the driver uint32_t rll; gboolean tmp; decif_get_drv_status(&(bcmdec->decif), &tmp, &rll, &nextPicNumFlags); if(rll >= 12 && !is_paused) { GST_DEBUG_OBJECT(bcmdec, "HW PAUSE with RLL %u", rll); decif_pause(&(bcmdec->decif), TRUE); is_paused = TRUE; } else if (rll < 12 && is_paused) { GST_DEBUG_OBJECT(bcmdec, "HW RESUME with RLL %u", rll); decif_pause(&(bcmdec->decif), false); is_paused = FALSE; } if(rll == 0) { GST_DEBUG_OBJECT(bcmdec, "No Picture Found"); usleep(5 * 1000); // Check if there was an EOS signalled decif_get_eos(&bcmdec->decif, &bEOS); if(!bEOS) continue; } guint8* data_ptr; if (gstbuf == NULL) { if (!bcmdec->rbuf_thread_running) { if (!bcmdec_get_buffer(bcmdec, &gstbuf)) { usleep(30 * 1000); continue; } GST_DEBUG_OBJECT(bcmdec, "got default buffer, going to proc output"); } else { if (gst_queue_element) { if (gst_queue_element->gstbuf) gst_buffer_unref(gst_queue_element->gstbuf); bcmdec_put_que_mem_buf(bcmdec, gst_queue_element); gst_queue_element = NULL; } gst_queue_element = bcmdec_rem_padbuf(bcmdec); if (!gst_queue_element) { GST_DEBUG_OBJECT(bcmdec, "rbuf queue empty"); usleep(10 * 1000); continue; } gstbuf = gst_queue_element->gstbuf; if (!gstbuf) { bcmdec_put_que_mem_buf(bcmdec, gst_queue_element); gst_queue_element = NULL; usleep(10 * 1000); continue; } GST_DEBUG_OBJECT(bcmdec, "got rbuf, going to proc output"); } } else GST_DEBUG_OBJECT(bcmdec, "re-using rbuf, going to proc output"); data_ptr = GST_BUFFER_DATA(gstbuf); bcmdec_init_procout(bcmdec, &pout, data_ptr); rx_flush = TRUE; pout.PicInfo.picture_number = 0; // For interlaced content, if I am holding a buffer but the next buffer is not from the same picture // i.e. the second field, then assume that this is a case of one field per picture and deliver this field // Don't deliver the one with picture number of 0 if(bcmdec->sec_field) { if(((nextPicNumFlags & 0x0FFFFFFF) - first_picture) != pic_number) { if(pic_number == 0) gst_buffer_unref(gstbuf); else if (gst_queue_element) { GST_BUFFER_FLAG_SET(gstbuf, GST_VIDEO_BUFFER_ONEFIELD); gst_queue_element->gstbuf = gstbuf; bcmdec_ins_buf(bcmdec, gst_queue_element); bcmdec->prev_pic = pic_number; gst_queue_element = NULL; } else { GST_DEBUG_OBJECT(bcmdec, "SOMETHING BAD HAPPENED\n"); gst_buffer_unref(gstbuf); } gstbuf = NULL; bcmdec->sec_field = FALSE;; continue; } } if (bEOS) { if (gstbuf) { gst_buffer_unref(gstbuf); gstbuf = NULL; } if (gst_queue_element) { gst_queue_element->gstbuf = NULL; bcmdec_ins_buf(bcmdec, gst_queue_element); gst_queue_element = NULL; } else { GST_DEBUG_OBJECT(bcmdec, "queue element failed"); } GST_DEBUG_OBJECT(bcmdec, "last picture set "); bcmdec->last_picture_set = TRUE; continue; } sts = DtsProcOutput(bcmdec->decif.hdev, PROC_TIMEOUT, &pout); GST_DEBUG_OBJECT(bcmdec, "procoutput status %d", sts); switch (sts) { case BC_STS_FMT_CHANGE: if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "procout ret FMT"); if ((pout.PoutFlags & BC_POUT_FLAGS_PIB_VALID) && (pout.PoutFlags & BC_POUT_FLAGS_FMT_CHANGE)) { if (bcmdec_format_change(bcmdec, &pout.PicInfo)) { GST_DEBUG_OBJECT(bcmdec, "format change success"); //bcmdec->frame_time = (GstClockTime)(UNITS / bcmdec->output_params.framerate); bcmdec->last_spes_time = 0; bcmdec->prev_clock_time = 0; cur_stream_time_diff = 0; first_frame_after_seek = TRUE; } else { GST_DEBUG_OBJECT(bcmdec, "format change failed"); } } gst_buffer_unref(gstbuf); gstbuf = NULL; bcmdec->sec_field = FALSE; if (sem_post(&bcmdec->rbuf_start_event) == -1) GST_ERROR_OBJECT(bcmdec, "rbuf sem_post failed"); //should modify to wait event wait_cnt = 0; while (!bcmdec->rbuf_thread_running && (wait_cnt < 5000)) { usleep(1000); wait_cnt++; } GST_DEBUG_OBJECT(bcmdec, "format change wait for rbuf thread start wait_cnt:%d", wait_cnt); break; case BC_STS_SUCCESS: if (!(pout.PoutFlags & BC_POUT_FLAGS_PIB_VALID)) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "procout ret PIB miss %d", pout.PicInfo.picture_number - 3); continue; } bcmdec_set_framerate(bcmdec, pout.PicInfo.frame_rate); pic_number = pout.PicInfo.picture_number - first_picture; if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "pic_number from HW is %u", pout.PicInfo.picture_number); if (bcmdec->flushing) { GST_DEBUG_OBJECT(bcmdec, "flushing discard, pic = %d", pic_number); continue; } if (bcmdec->prev_pic + 1 < pic_number) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "LOST PICTURE pic_no = %d, prev = %d", pic_number, bcmdec->prev_pic); } /* if ((bcmdec->prev_pic == pic_number) && (bcmdec->ses_nbr == pout.PicInfo.sess_num) && !bcmdec->interlace) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "rp"); if (!(pout.PicInfo.flags & VDEC_FLAG_LAST_PICTURE)) continue; }*/ if (!bcmdec->interlace || bcmdec->sec_field) { GST_DEBUG_OBJECT(bcmdec, "Progressive or Second Field"); GST_BUFFER_OFFSET(gstbuf) = 0; GST_BUFFER_TIMESTAMP(gstbuf) = bcmdec_get_time_stamp(bcmdec, pic_number, pout.PicInfo.timeStamp); GST_BUFFER_DURATION(gstbuf) = bcmdec->frame_time; if (bcmdec->gst_clock) { clock_time = gst_clock_get_time(bcmdec->gst_clock); if (first_frame_after_seek) { bcmdec->prev_clock_time = clock_time; first_frame_after_seek = FALSE; cur_stream_time_diff = 0; } if (bcmdec->prev_clock_time > clock_time) bcmdec->prev_clock_time = 0; cur_stream_time_diff += clock_time - bcmdec->prev_clock_time; bcmdec->cur_stream_time = cur_stream_time_diff + bcmdec->base_clock_time; bcmdec->prev_clock_time = clock_time; if ((bcmdec->last_spes_time < bcmdec->cur_stream_time) && (!bcmdec->catchup_on) && (pout.PicInfo.timeStamp)) { bcmdec->catchup_on = TRUE; decif_decode_catchup(&bcmdec->decif, TRUE); } else if (bcmdec->catchup_on) { decif_decode_catchup(&bcmdec->decif, FALSE); bcmdec->catchup_on = FALSE; } } } GST_BUFFER_SIZE(gstbuf) = bcmdec->output_params.width * bcmdec->output_params.height * BUF_MULT; if (!bcmdec->interlace || bcmdec->sec_field) { if (gst_queue_element) { // If interlaced, set the GST_VIDEO_BUFFER_TFF flags if(bcmdec->sec_field) GST_BUFFER_FLAG_SET(gstbuf, GST_VIDEO_BUFFER_TFF); gst_queue_element->gstbuf = gstbuf; bcmdec_ins_buf(bcmdec, gst_queue_element); bcmdec->prev_pic = pic_number; } else { GST_ERROR_OBJECT(bcmdec, "This CANNOT HAPPEN");//pending error recovery } gstbuf = NULL; bcmdec->sec_field = FALSE; gst_queue_element = NULL; } else { GST_DEBUG_OBJECT(bcmdec, "Wait for second field"); bcmdec->sec_field = TRUE; } break; case BC_STS_TIMEOUT: GST_DEBUG_OBJECT(bcmdec, "procout timeout QCnt:%d, RCnt:%d, Paused:%d", bcmdec->gst_que_cnt, bcmdec->gst_padbuf_que_cnt, bcmdec->paused); break; case BC_STS_IO_XFR_ERROR: GST_DEBUG_OBJECT(bcmdec, "procout xfer error"); break; case BC_STS_IO_USER_ABORT: case BC_STS_IO_ERROR: bcmdec->streaming = FALSE; GST_DEBUG_OBJECT(bcmdec, "ABORT sts = %d", sts); if (gstbuf) { gst_buffer_unref(gstbuf); gstbuf = NULL; } break; case BC_STS_NO_DATA: GST_DEBUG_OBJECT(bcmdec, "procout no data"); // Check for EOS decif_get_eos(&bcmdec->decif, &bEOS); if (bEOS) { if (gstbuf) { gst_buffer_unref(gstbuf); gstbuf = NULL; } if (gst_queue_element) { gst_queue_element->gstbuf = NULL; bcmdec_ins_buf(bcmdec, gst_queue_element); gst_queue_element = NULL; } else { GST_DEBUG_OBJECT(bcmdec, "queue element failed"); } GST_DEBUG_OBJECT(bcmdec, "last picture set "); bcmdec->last_picture_set = TRUE; } break; default: GST_DEBUG_OBJECT(bcmdec, "unhandled status from Procout sts %d",sts); if (gstbuf) { gst_buffer_unref(gstbuf); gstbuf = NULL; } break; } } if (gstbuf) { gst_buffer_unref(gstbuf); gstbuf = NULL; } if (gst_queue_element) { bcmdec_put_que_mem_buf(bcmdec, gst_queue_element); gst_queue_element = NULL; } if (rx_flush) { if (!bcmdec->flushing) { // GST_DEBUG_OBJECT(bcmdec, "DtsFlushRxCapture called"); // sts = decif_flush_rxbuf(&bcmdec->decif, FALSE); // if (sts != BC_STS_SUCCESS) // GST_DEBUG_OBJECT(bcmdec, "DtsFlushRxCapture failed"); } rx_flush = FALSE; if (bcmdec->flushing) { if (sem_post(&bcmdec->recv_stop_event) == -1) GST_ERROR_OBJECT(bcmdec, "recv_stop sem_post failed"); } GST_DEBUG_OBJECT(bcmdec, "DtsFlushRxCapture Done"); } } GST_DEBUG_OBJECT(bcmdec, "Rx thread exiting .."); pthread_exit((void*)&sts); } static gboolean bcmdec_start_push_thread(GstBcmDec *bcmdec) { gboolean result = TRUE; pthread_attr_t thread_attr; gint ret = 0; pthread_attr_init(&thread_attr); pthread_attr_setdetachstate(&thread_attr, PTHREAD_CREATE_JOINABLE); pthread_create(&bcmdec->push_thread, &thread_attr, bcmdec_process_push, bcmdec); pthread_attr_destroy(&thread_attr); if (!bcmdec->push_thread) { GST_ERROR_OBJECT(bcmdec, "Failed to create PushThread"); result = FALSE; } else { GST_DEBUG_OBJECT(bcmdec, "Success to create PushThread"); } ret = sem_init(&bcmdec->buf_event, 0, 0); if (ret != 0) { GST_ERROR_OBJECT(bcmdec, "play event init failed"); result = FALSE; } ret = sem_init(&bcmdec->push_start_event, 0, 0); if (ret != 0) { GST_ERROR_OBJECT(bcmdec, "play event init failed"); result = FALSE; } ret = sem_init(&bcmdec->push_stop_event, 0, 0); if (ret != 0) { GST_ERROR_OBJECT(bcmdec, "push_stop event init failed"); result = FALSE; } return result; } static gboolean bcmdec_start_recv_thread(GstBcmDec *bcmdec) { gboolean result = TRUE; gint ret = 0; pthread_attr_t thread_attr; if (!bcmdec_alloc_mem_buf_que_pool(bcmdec)) GST_ERROR_OBJECT(bcmdec, "pool alloc failed/n"); ret = sem_init(&bcmdec->play_event, 0, 0); if (ret != 0) { GST_ERROR_OBJECT(bcmdec, "play event init failed"); result = FALSE; } ret = sem_init(&bcmdec->quit_event, 0, 0); if (ret != 0) { GST_ERROR_OBJECT(bcmdec, "play event init failed"); result = FALSE; } ret = sem_init(&bcmdec->recv_stop_event, 0, 0); if (ret != 0) { GST_ERROR_OBJECT(bcmdec, "recv_stop event init failed"); result = FALSE; } pthread_attr_init(&thread_attr); pthread_attr_setdetachstate(&thread_attr, PTHREAD_CREATE_JOINABLE); pthread_create(&bcmdec->recv_thread, &thread_attr, bcmdec_process_output, bcmdec); pthread_attr_destroy(&thread_attr); if (!bcmdec->recv_thread) { GST_ERROR_OBJECT(bcmdec, "Failed to create RxThread"); result = FALSE; } else { GST_DEBUG_OBJECT(bcmdec, "Success to create RxThread"); } return result; } static GstClockTime bcmdec_get_time_stamp(GstBcmDec *bcmdec, guint32 pic_no, GstClockTime spes_time) { GstClockTime time_stamp = 0; GstClockTime frame_time = (GstClockTime)(UNITS / bcmdec->output_params.framerate); if (bcmdec->enable_spes) { if (spes_time) { time_stamp = spes_time ; if (bcmdec->spes_frame_cnt && bcmdec->last_output_spes_time) { bcmdec->frame_time = (time_stamp - bcmdec->last_output_spes_time) / bcmdec->spes_frame_cnt; bcmdec->spes_frame_cnt = 0; } if (bcmdec->frame_time > 0) frame_time = bcmdec->frame_time; bcmdec->spes_frame_cnt++; bcmdec->last_output_spes_time = bcmdec->last_spes_time = time_stamp; } else { if (bcmdec->frame_time > 0) frame_time = bcmdec->frame_time; bcmdec->last_spes_time += frame_time; time_stamp = bcmdec->last_spes_time; bcmdec->spes_frame_cnt++; } } else { time_stamp = (GstClockTime)(bcmdec->base_time + frame_time * pic_no); } if (!bcmdec->enable_spes) { if (bcmdec->interlace) { if (bcmdec->prev_pic == pic_no) bcmdec->rpt_pic_cnt++; time_stamp += bcmdec->rpt_pic_cnt * frame_time; } } return time_stamp; } static void bcmdec_process_flush_stop(GstBcmDec *bcmdec) { bcmdec->ses_change = TRUE; bcmdec->base_time = 0; bcmdec->flushing = FALSE; bcmdec->streaming = TRUE; bcmdec->rpt_pic_cnt = 0; GST_DEBUG_OBJECT(bcmdec, "flush stop started"); if (sem_post(&bcmdec->play_event) == -1) GST_ERROR_OBJECT(bcmdec, "sem_post failed"); bcmdec->push_exit = FALSE; if (sem_post(&bcmdec->push_start_event) == -1) GST_ERROR_OBJECT(bcmdec, "push_start post failed"); GST_DEBUG_OBJECT(bcmdec, "flush stop complete"); } static void bcmdec_process_flush_start(GstBcmDec *bcmdec) { gint ret = 1; BC_STATUS sts = BC_STS_SUCCESS; struct timespec ts; ts.tv_sec=time(NULL) + 5; ts.tv_nsec = 0; bcmdec->flushing = TRUE; bcmdec->streaming = FALSE; ret = sem_timedwait(&bcmdec->recv_stop_event, &ts); if (ret < 0) { switch (errno) { case ETIMEDOUT: GST_DEBUG_OBJECT(bcmdec, "recv_stop_event sig timed out "); break; case EINTR: GST_DEBUG_OBJECT(bcmdec, "Sig interrupt "); break; default: GST_ERROR_OBJECT(bcmdec, "sem wait failed %d ",errno); break; } } bcmdec->push_exit = TRUE; ret = sem_timedwait(&bcmdec->push_stop_event, &ts); if (ret < 0) { switch (errno) { case ETIMEDOUT: GST_DEBUG_OBJECT(bcmdec, "push_stop_event sig timed out "); break; case EINTR: GST_DEBUG_OBJECT(bcmdec, "Sig interrupt "); break; default: GST_ERROR_OBJECT(bcmdec, "sem wait failed %d ",errno); break; } } sts = decif_flush_dec(&bcmdec->decif, 2); if (sts != BC_STS_SUCCESS) GST_ERROR_OBJECT(bcmdec, "flush_dec failed sts %d", sts); } static BC_STATUS gst_bcmdec_cleanup(GstBcmDec *bcmdec) { BC_STATUS sts = BC_STS_SUCCESS; GST_DEBUG_OBJECT(bcmdec, "gst_bcmdec_cleanup - enter"); bcmdec->streaming = FALSE; bcmdec_release_mem_buf_que_pool(bcmdec); // bcmdec_release_mem_rbuf_que_pool(bcmdec); if (bcmdec->decif.hdev) sts = decif_close(&bcmdec->decif); sem_destroy(&bcmdec->quit_event); sem_destroy(&bcmdec->play_event); sem_destroy(&bcmdec->push_start_event); sem_destroy(&bcmdec->buf_event); sem_destroy(&bcmdec->rbuf_start_event); sem_destroy(&bcmdec->rbuf_stop_event); sem_destroy(&bcmdec->rbuf_ins_event); sem_destroy(&bcmdec->push_stop_event); sem_destroy(&bcmdec->recv_stop_event); pthread_mutex_destroy(&bcmdec->gst_buf_que_lock); pthread_mutex_destroy(&bcmdec->gst_padbuf_que_lock); //pthread_mutex_destroy(&bcmdec->fn_lock); if (bcmdec->codec_params.sps_pps_buf) { free(bcmdec->codec_params.sps_pps_buf); bcmdec->codec_params.sps_pps_buf = NULL; } if (bcmdec->dest_buf) { free(bcmdec->dest_buf); bcmdec->dest_buf = NULL; } // if (bcmdec->vc1_dest_buffer) { // free(bcmdec->vc1_dest_buffer); // bcmdec->vc1_dest_buffer = NULL; // } if (bcmdec->gst_clock) { gst_object_unref(bcmdec->gst_clock); bcmdec->gst_clock = NULL; } if (sem_post(&g_inst_sts->inst_ctrl_event) == -1) GST_ERROR_OBJECT(bcmdec, "inst_ctrl_event post failed"); else GST_DEBUG_OBJECT(bcmdec, "inst_ctrl_event posted"); return sts; } static void bcmdec_reset(GstBcmDec * bcmdec) { bcmdec->dec_ready = FALSE; bcmdec->streaming = FALSE; bcmdec->format_reset = TRUE; bcmdec->interlace = FALSE; bcmdec->output_params.width = 720; bcmdec->output_params.height = 480; bcmdec->output_params.framerate = 29; bcmdec->output_params.aspectratio_x = 16; bcmdec->output_params.aspectratio_y = 9; bcmdec->output_params.clr_space = BUF_MODE; if (bcmdec->output_params.clr_space == MODE420) { /* MODE420 */ bcmdec->output_params.y_size = 720 * 480; bcmdec->output_params.uv_size = 720 * 480 / 2; } else { /* MODE422_YUV */ bcmdec->output_params.y_size = 720 * 480 * 2; bcmdec->output_params.uv_size = 0; } bcmdec->output_params.stride = 0; bcmdec->base_time = 0; bcmdec->fhnd = NULL; bcmdec->play_pending = FALSE; bcmdec->gst_buf_que_hd = NULL; bcmdec->gst_buf_que_tl = NULL; bcmdec->gst_que_cnt = 0; bcmdec->last_picture_set = FALSE; bcmdec->gst_buf_que_sz = GST_BUF_LIST_POOL_SZ; bcmdec->gst_padbuf_que_sz = GST_RENDERER_BUF_POOL_SZ; bcmdec->rbuf_thread_running = FALSE; bcmdec->insert_start_code = FALSE; bcmdec->codec_params.sps_pps_buf = NULL; bcmdec->input_framerate = 0; bcmdec->input_par_x = 0; bcmdec->input_par_y = 0; bcmdec->prev_pic = -1; bcmdec->codec_params.inside_buffer = TRUE; bcmdec->codec_params.consumed_offset = 0; bcmdec->codec_params.strtcode_offset = 0; bcmdec->codec_params.nal_sz = 0; bcmdec->codec_params.pps_size = 0; bcmdec->codec_params.nal_size_bytes = 4; bcmdec->paused = FALSE; bcmdec->flushing = FALSE; bcmdec->ses_nbr = 0; bcmdec->insert_pps = TRUE; bcmdec->ses_change = FALSE; bcmdec->push_exit = FALSE; bcmdec->suspend_mode = FALSE; bcmdec->gst_clock = NULL; bcmdec->rpt_pic_cnt = 0; //bcmdec->enable_spes = FALSE; bcmdec->enable_spes = TRUE; bcmdec->dest_buf = NULL; bcmdec->catchup_on = FALSE; bcmdec->last_output_spes_time = 0; pthread_mutex_init(&bcmdec->gst_buf_que_lock, NULL); pthread_mutex_init(&bcmdec->gst_padbuf_que_lock, NULL); //pthread_mutex_init(&bcmdec->fn_lock,NULL); } static void bcmdec_put_que_mem_buf(GstBcmDec *bcmdec, GSTBUF_LIST *gst_queue_element) { pthread_mutex_lock(&bcmdec->gst_buf_que_lock); gst_queue_element->next = bcmdec->gst_mem_buf_que_hd; bcmdec->gst_mem_buf_que_hd = gst_queue_element; bcmdec->gst_que_cnt++; GST_DEBUG_OBJECT(bcmdec, "mem pool inc is %u", bcmdec->gst_que_cnt); pthread_mutex_unlock(&bcmdec->gst_buf_que_lock); } static GSTBUF_LIST * bcmdec_get_que_mem_buf(GstBcmDec *bcmdec) { GSTBUF_LIST *gst_queue_element = NULL; pthread_mutex_lock(&bcmdec->gst_buf_que_lock); gst_queue_element = bcmdec->gst_mem_buf_que_hd; if (gst_queue_element) { bcmdec->gst_mem_buf_que_hd = bcmdec->gst_mem_buf_que_hd->next; bcmdec->gst_que_cnt--; GST_DEBUG_OBJECT(bcmdec, "mem pool dec is %u", bcmdec->gst_que_cnt); } pthread_mutex_unlock(&bcmdec->gst_buf_que_lock); return gst_queue_element; } static gboolean bcmdec_alloc_mem_buf_que_pool(GstBcmDec *bcmdec) { GSTBUF_LIST *gst_queue_element = NULL; guint i = 0; bcmdec->gst_mem_buf_que_hd = NULL; while (i++gst_buf_que_sz) { if (!(gst_queue_element = (GSTBUF_LIST *)malloc(sizeof(GSTBUF_LIST)))) { GST_ERROR_OBJECT(bcmdec, "mempool malloc failed "); return FALSE; } memset(gst_queue_element, 0, sizeof(GSTBUF_LIST)); bcmdec_put_que_mem_buf(bcmdec, gst_queue_element); } return TRUE; } static gboolean bcmdec_release_mem_buf_que_pool(GstBcmDec *bcmdec) { GSTBUF_LIST *gst_queue_element; guint i = 0; do { gst_queue_element = bcmdec_get_que_mem_buf(bcmdec); if (gst_queue_element) { free(gst_queue_element); i++; } } while (gst_queue_element); bcmdec->gst_mem_buf_que_hd = NULL; if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "mem_buf_que_pool released... %d", i); return TRUE; } static void bcmdec_ins_buf(GstBcmDec *bcmdec,GSTBUF_LIST *gst_queue_element) { pthread_mutex_lock(&bcmdec->gst_buf_que_lock); if (!bcmdec->gst_buf_que_hd) { bcmdec->gst_buf_que_hd = bcmdec->gst_buf_que_tl = gst_queue_element; } else { bcmdec->gst_buf_que_tl->next = gst_queue_element; bcmdec->gst_buf_que_tl = gst_queue_element; gst_queue_element->next = NULL; } if (sem_post(&bcmdec->buf_event) == -1) GST_ERROR_OBJECT(bcmdec, "buf sem_post failed"); else GST_DEBUG_OBJECT(bcmdec, "buffer inserted and buf_event signalled"); pthread_mutex_unlock(&bcmdec->gst_buf_que_lock); } static GSTBUF_LIST * bcmdec_rem_buf(GstBcmDec *bcmdec) { GSTBUF_LIST *temp; pthread_mutex_lock(&bcmdec->gst_buf_que_lock); if (bcmdec->gst_buf_que_hd == bcmdec->gst_buf_que_tl) { temp = bcmdec->gst_buf_que_hd; bcmdec->gst_buf_que_hd = bcmdec->gst_buf_que_tl = NULL; } else { temp = bcmdec->gst_buf_que_hd; bcmdec->gst_buf_que_hd = temp->next; } pthread_mutex_unlock(&bcmdec->gst_buf_que_lock); return temp; } static BC_STATUS bcmdec_insert_sps_pps(GstBcmDec *bcmdec, GstBuffer* gstbuf) { BC_STATUS sts = BC_STS_SUCCESS; guint8 *data = GST_BUFFER_DATA(gstbuf); guint32 data_size = GST_BUFFER_SIZE(gstbuf); gint profile; guint nal_size; guint num_sps, num_pps, i; bcmdec->codec_params.pps_size = 0; profile = (data[1] << 16) | (data[2] << 8) | data[3]; GST_DEBUG_OBJECT(bcmdec, "profile %06x",profile); bcmdec->codec_params.nal_size_bytes = (data[4] & 0x03) + 1; GST_DEBUG_OBJECT(bcmdec, "nal size %d",bcmdec->codec_params.nal_size_bytes); num_sps = data[5] & 0x1f; GST_DEBUG_OBJECT(bcmdec, "num sps %d",num_sps); data += 6; data_size -= 6; for (i = 0; i < num_sps; i++) { if (data_size < 2) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "too small 2"); return BC_STS_ERROR; } nal_size = (data[0] << 8) | data[1]; data += 2; data_size -= 2; if (data_size < nal_size) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "too small 3"); return BC_STS_ERROR; } bcmdec->codec_params.sps_pps_buf[0] = 0; bcmdec->codec_params.sps_pps_buf[1] = 0; bcmdec->codec_params.sps_pps_buf[2] = 0; bcmdec->codec_params.sps_pps_buf[3] = 1; bcmdec->codec_params.pps_size += 4; memcpy(bcmdec->codec_params.sps_pps_buf + bcmdec->codec_params.pps_size, data, nal_size); bcmdec->codec_params.pps_size += nal_size; data += nal_size; data_size -= nal_size; } if (data_size < 1) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "too small 4"); return BC_STS_ERROR; } num_pps = data[0]; data += 1; data_size -= 1; for (i = 0; i < num_pps; i++) { if (data_size < 2) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "too small 5"); return BC_STS_ERROR; } nal_size = (data[0] << 8) | data[1]; data += 2; data_size -= 2; if (data_size < nal_size) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "too small 6"); return BC_STS_ERROR; } bcmdec->codec_params.sps_pps_buf[bcmdec->codec_params.pps_size+0] = 0; bcmdec->codec_params.sps_pps_buf[bcmdec->codec_params.pps_size+1] = 0; bcmdec->codec_params.sps_pps_buf[bcmdec->codec_params.pps_size+2] = 0; bcmdec->codec_params.sps_pps_buf[bcmdec->codec_params.pps_size+3] = 1; bcmdec->codec_params.pps_size += 4; memcpy(bcmdec->codec_params.sps_pps_buf + bcmdec->codec_params.pps_size, data, nal_size); bcmdec->codec_params.pps_size += nal_size; data += nal_size; data_size -= nal_size; } GST_DEBUG_OBJECT(bcmdec, "data size at end = %d ",data_size); return sts; } static gboolean bcmdec_mul_inst_cor(GstBcmDec *bcmdec) { struct timespec ts; gint ret = 0; int i = 0; if ((intptr_t)g_inst_sts == -1) { GST_ERROR_OBJECT(bcmdec, "mul_inst_cor :shmem ptr invalid"); return FALSE; } if (g_inst_sts->cur_decode == PLAYBACK) { GST_DEBUG_OBJECT(bcmdec, "mul_inst_cor : ret false %d", g_inst_sts->cur_decode); return FALSE; } for (i = 0; i < 15; i++) { ts.tv_sec = time(NULL) + 3; ts.tv_nsec = 0; ret = sem_timedwait(&g_inst_sts->inst_ctrl_event, &ts); if (ret < 0) { if (errno == ETIMEDOUT) { if (g_inst_sts->cur_decode == PLAYBACK) { GST_DEBUG_OBJECT(bcmdec, "mul_inst_cor :playback is set , exit"); return FALSE; } else { GST_DEBUG_OBJECT(bcmdec, "mul_inst_cor :wait for thumb nail decode finish"); continue; } } else if (errno == EINTR) { return FALSE; } } else { GST_DEBUG_OBJECT(bcmdec, "mul_inst_cor :ctrl_event is given"); return TRUE; } } GST_DEBUG_OBJECT(bcmdec, "mul_inst_cor : ret false cur_dec = %d wait = %d", g_inst_sts->cur_decode, g_inst_sts->waiting); return FALSE; } static BC_STATUS bcmdec_create_shmem(GstBcmDec *bcmdec, int *shmem_id) { int shmid = -1; key_t shmkey = BCM_GST_SHMEM_KEY; shmid_ds buf; if (shmem_id == NULL) { GST_ERROR_OBJECT(bcmdec, "Invalid argument ..."); return BC_STS_INSUFF_RES; } *shmem_id = shmid; //First Try to create it. shmid = shmget(shmkey, 1024, 0644 | IPC_CREAT | IPC_EXCL); if (shmid == -1) { if (errno == EEXIST) { GST_DEBUG_OBJECT(bcmdec, "bcmdec_create_shmem:shmem already exists :%d", errno); shmid = shmget(shmkey, 1024, 0644); if (shmid == -1) { GST_ERROR_OBJECT(bcmdec, "bcmdec_create_shmem:unable to get shmid :%d", errno); return BC_STS_INSUFF_RES; } //we got the shmid, see if any process is alreday attached to it if (shmctl(shmid,IPC_STAT,&buf) == -1) { GST_ERROR_OBJECT(bcmdec, "bcmdec_create_shmem:shmctl failed ..."); return BC_STS_ERROR; } if (buf.shm_nattch == 0) { sem_destroy(&g_inst_sts->inst_ctrl_event); //No process is currently attached to the shmem seg. go ahead and delete it as its contents are stale. if (shmctl(shmid, IPC_RMID, NULL) != -1) GST_DEBUG_OBJECT(bcmdec, "bcmdec_create_shmem:deleted shmem segment and creating a new one ..."); //create a new shmem shmid = shmget(shmkey, 1024, 0644 | IPC_CREAT | IPC_EXCL); if (shmid == -1) { GST_ERROR_OBJECT(bcmdec, "bcmdec_create_shmem:unable to get shmid :%d", errno); return BC_STS_INSUFF_RES; } //attach to it bcmdec_get_shmem(bcmdec, shmid, TRUE); } else { //attach to it bcmdec_get_shmem(bcmdec, shmid, FALSE); } } else { GST_ERROR_OBJECT(bcmdec, "shmcreate failed with err %d",errno); return BC_STS_ERROR; } } else { //we created just attach to it bcmdec_get_shmem(bcmdec, shmid, TRUE); } *shmem_id = shmid; return BC_STS_SUCCESS; } static BC_STATUS bcmdec_get_shmem(GstBcmDec *bcmdec, int shmid, gboolean newmem) { gint ret = 0; g_inst_sts = (GLB_INST_STS *)shmat(shmid, (void *)0, 0); if ((intptr_t)g_inst_sts == -1) { GST_ERROR_OBJECT(bcmdec, "Unable to open shared memory ...errno = %d", errno); return BC_STS_ERROR; } if (newmem) { ret = sem_init(&g_inst_sts->inst_ctrl_event, 5, 1); if (ret != 0) { GST_ERROR_OBJECT(bcmdec, "inst_ctrl_event failed"); return BC_STS_ERROR; } } return BC_STS_SUCCESS; } static BC_STATUS bcmdec_del_shmem(GstBcmDec *bcmdec) { int shmid = 0; shmid_ds buf; //First dettach the shared mem segment if (shmdt(g_inst_sts) == -1) GST_ERROR_OBJECT(bcmdec, "Unable to detach shared memory ..."); //delete the shared mem segment if there are no other attachments shmid = shmget((key_t)BCM_GST_SHMEM_KEY, 0, 0); if (shmid == -1) { GST_ERROR_OBJECT(bcmdec, "bcmdec_del_shmem:Unable get shmid ..."); return BC_STS_ERROR; } if (shmctl(shmid, IPC_STAT, &buf) == -1) { GST_ERROR_OBJECT(bcmdec, "bcmdec_del_shmem:shmctl failed ..."); return BC_STS_ERROR; } if (buf.shm_nattch == 0) { sem_destroy(&g_inst_sts->inst_ctrl_event); //No process is currently attached to the shmem seg. go ahead and delete it if (shmctl(shmid, IPC_RMID, NULL) != -1) { GST_ERROR_OBJECT(bcmdec, "bcmdec_del_shmem:deleted shmem segment ..."); return BC_STS_ERROR; } else { GST_ERROR_OBJECT(bcmdec, "bcmdec_del_shmem:unable to delete shmem segment ..."); } } return BC_STS_SUCCESS; } // For renderer buffer static void bcmdec_flush_gstrbuf_queue(GstBcmDec *bcmdec) { GSTBUF_LIST *gst_queue_element = NULL; while (1) { gst_queue_element = bcmdec_rem_padbuf(bcmdec); if (gst_queue_element) { if (gst_queue_element->gstbuf) { gst_buffer_unref (gst_queue_element->gstbuf); bcmdec_put_que_mem_buf(bcmdec, gst_queue_element); } else { break; } } else { GST_DEBUG_OBJECT(bcmdec, "no gst_queue_element"); break; } } } static void * bcmdec_process_get_rbuf(void *ctx) { GstBcmDec *bcmdec = (GstBcmDec *)ctx; GstFlowReturn ret = GST_FLOW_ERROR; GSTBUF_LIST *gst_queue_element = NULL; gboolean result = FALSE, done = FALSE; GstBuffer *gstbuf = NULL; guint bufSz = 0; gboolean get_buf_start = FALSE; int revent = -1; while (1) { revent = sem_trywait(&bcmdec->rbuf_start_event); if (revent == 0) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "got start get buf event "); get_buf_start = TRUE; bcmdec->rbuf_thread_running = TRUE; } revent = sem_trywait(&bcmdec->rbuf_stop_event); if (revent == 0) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "quit event set, exit"); break; } if (!bcmdec->streaming || !get_buf_start) { GST_DEBUG_OBJECT(bcmdec, "SLEEPING in get bufs"); usleep(100 * 1000); } while (bcmdec->streaming && get_buf_start) { //GST_DEBUG_OBJECT(bcmdec, "process get rbuf start...."); gstbuf = NULL; if (!bcmdec->recv_thread && !bcmdec->streaming) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "process get rbuf prepare exiting.."); done = TRUE; break; } // If we have enough buffers from the renderer then don't get any more if(bcmdec->gst_padbuf_que_cnt >= GST_RENDERER_BUF_POOL_SZ) { usleep(100 * 1000); GST_DEBUG_OBJECT(bcmdec, "SLEEPING because we have enough buffers"); continue; } if (gst_queue_element == NULL) gst_queue_element = bcmdec_get_que_mem_buf(bcmdec); if (!gst_queue_element) { if (!bcmdec->silent) GST_DEBUG_OBJECT(bcmdec, "mbuf full == TRUE %u", bcmdec->gst_buf_que_sz); usleep(100 * 1000); // Sleep since we have buffers queued up continue; } bufSz = bcmdec->output_params.width * bcmdec->output_params.height * BUF_MULT; GST_DEBUG_OBJECT(bcmdec, "process get rbuf gst_pad_alloc_buffer_and_set_caps ...."); ret = gst_pad_alloc_buffer_and_set_caps(bcmdec->srcpad, GST_BUFFER_OFFSET_NONE, bufSz, GST_PAD_CAPS(bcmdec->srcpad), &gstbuf); if (ret != GST_FLOW_OK) { if (!bcmdec->silent) GST_ERROR_OBJECT(bcmdec, "gst_pad_alloc_buffer_and_set_caps failed %d ",ret); usleep(30 * 1000); continue; } GST_DEBUG_OBJECT(bcmdec, "Got GST Buf RCnt:%d", bcmdec->gst_padbuf_que_cnt); gst_queue_element->gstbuf = gstbuf; bcmdec_ins_padbuf(bcmdec, gst_queue_element); gst_queue_element = NULL; usleep(5 * 1000); } if (done) { GST_DEBUG_OBJECT(bcmdec, "process get rbuf done "); break; } } bcmdec_flush_gstrbuf_queue(bcmdec); GST_DEBUG_OBJECT(bcmdec, "process get rbuf exiting.. "); pthread_exit((void *)&result); } static gboolean bcmdec_start_get_rbuf_thread(GstBcmDec *bcmdec) { gboolean result = TRUE; gint ret = 0; pthread_attr_t thread_attr; // if (!bcmdec_alloc_mem_rbuf_que_pool(bcmdec)) // GST_ERROR_OBJECT(bcmdec, "rend pool alloc failed/n"); bcmdec->gst_padbuf_que_hd = bcmdec->gst_padbuf_que_tl = NULL; ret = sem_init(&bcmdec->rbuf_ins_event, 0, 0); if (ret != 0) { GST_ERROR_OBJECT(bcmdec, "get rbuf ins event init failed"); result = FALSE; } ret = sem_init(&bcmdec->rbuf_start_event, 0, 0); if (ret != 0) { GST_ERROR_OBJECT(bcmdec, "get rbuf start event init failed"); result = FALSE; } ret = sem_init(&bcmdec->rbuf_stop_event, 0, 0); if (ret != 0) { GST_ERROR_OBJECT(bcmdec, "get rbuf stop event init failed"); result = FALSE; } pthread_attr_init(&thread_attr); pthread_attr_setdetachstate(&thread_attr, PTHREAD_CREATE_JOINABLE); pthread_create(&bcmdec->get_rbuf_thread, &thread_attr, bcmdec_process_get_rbuf, bcmdec); pthread_attr_destroy(&thread_attr); if (!bcmdec->get_rbuf_thread) { GST_ERROR_OBJECT(bcmdec, "Failed to create Renderer buffer Thread"); result = FALSE; } else { GST_DEBUG_OBJECT(bcmdec, "Success to create Renderer buffer Thread"); } return result; } // static void bcmdec_put_que_mem_padbuf(GstBcmDec *bcmdec, GSTBUF_LIST *gst_queue_element) // { // pthread_mutex_lock(&bcmdec->gst_padbuf_que_lock); // // gst_queue_element->next = bcmdec->gst_mem_padbuf_que_hd; // bcmdec->gst_mem_padbuf_que_hd = gst_queue_element; // // pthread_mutex_unlock(&bcmdec->gst_padbuf_que_lock); // } // // static GSTBUF_LIST * bcmdec_get_que_mem_padbuf(GstBcmDec *bcmdec) // { // GSTBUF_LIST *gst_queue_element; // // pthread_mutex_lock(&bcmdec->gst_padbuf_que_lock); // // gst_queue_element = bcmdec->gst_mem_padbuf_que_hd; // if (gst_queue_element !=NULL) // bcmdec->gst_mem_padbuf_que_hd = bcmdec->gst_mem_padbuf_que_hd->next; // // pthread_mutex_unlock(&bcmdec->gst_padbuf_que_lock); // // return gst_queue_element; // } // // static gboolean bcmdec_alloc_mem_rbuf_que_pool(GstBcmDec *bcmdec) // { // GSTBUF_LIST *gst_queue_element; // guint i; // // bcmdec->gst_mem_padbuf_que_hd = NULL; // for (i = 1; i < bcmdec->gst_padbuf_que_sz; i++) { // gst_queue_element = (GSTBUF_LIST *)malloc(sizeof(GSTBUF_LIST)); // if (!gst_queue_element) { // GST_ERROR_OBJECT(bcmdec, "mem_rbuf_que_pool malloc failed "); // return FALSE; // } // memset(gst_queue_element, 0, sizeof(GSTBUF_LIST)); // bcmdec_put_que_mem_padbuf(bcmdec, gst_queue_element); // } // // return TRUE; // } // // static gboolean bcmdec_release_mem_rbuf_que_pool(GstBcmDec *bcmdec) // { // GSTBUF_LIST *gst_queue_element; // guint i = 0; // // do { // gst_queue_element = bcmdec_get_que_mem_padbuf(bcmdec); // if (gst_queue_element) { // free(gst_queue_element); // i++; // } // } while (gst_queue_element); // // bcmdec->gst_mem_padbuf_que_hd = NULL; // if (!bcmdec->silent) // GST_DEBUG_OBJECT(bcmdec, "rend_rbuf_que_pool released... %d", i); // // return TRUE; // } static void bcmdec_ins_padbuf(GstBcmDec *bcmdec, GSTBUF_LIST *gst_queue_element) { pthread_mutex_lock(&bcmdec->gst_padbuf_que_lock); if (!bcmdec->gst_padbuf_que_hd) { bcmdec->gst_padbuf_que_hd = bcmdec->gst_padbuf_que_tl = gst_queue_element; } else { bcmdec->gst_padbuf_que_tl->next = gst_queue_element; bcmdec->gst_padbuf_que_tl = gst_queue_element; gst_queue_element->next = NULL; } bcmdec->gst_padbuf_que_cnt++; GST_DEBUG_OBJECT(bcmdec, "Inc rbuf:%d", bcmdec->gst_padbuf_que_cnt); if (sem_post(&bcmdec->rbuf_ins_event) == -1) GST_ERROR_OBJECT(bcmdec, "rbuf sem_post failed"); pthread_mutex_unlock(&bcmdec->gst_padbuf_que_lock); } static GSTBUF_LIST *bcmdec_rem_padbuf(GstBcmDec *bcmdec) { GSTBUF_LIST *temp; pthread_mutex_lock(&bcmdec->gst_padbuf_que_lock); if (bcmdec->gst_padbuf_que_hd == bcmdec->gst_padbuf_que_tl) { temp = bcmdec->gst_padbuf_que_hd; bcmdec->gst_padbuf_que_hd = bcmdec->gst_padbuf_que_tl = NULL; } else { temp = bcmdec->gst_padbuf_que_hd; bcmdec->gst_padbuf_que_hd = temp->next; } if (temp) bcmdec->gst_padbuf_que_cnt--; GST_DEBUG_OBJECT(bcmdec, "Dec rbuf:%d", bcmdec->gst_padbuf_que_cnt); pthread_mutex_unlock(&bcmdec->gst_padbuf_que_lock); return temp; } // End of renderer buffer /* * entry point to initialize the plug-in * initialize the plug-in itself * register the element factories and other features */ static gboolean plugin_init(GstPlugin *bcmdec) { //printf("BcmDec_init"); /* * debug category for fltering log messages * * exchange the string 'Template bcmdec' with your description */ GST_DEBUG_CATEGORY_INIT(gst_bcmdec_debug, "bcmdec", 0, "Broadcom video decoder"); return gst_element_register(bcmdec, "bcmdec", GST_BCMDEC_RANK, GST_TYPE_BCMDEC); } /* gstreamer looks for this structure to register bcmdec */ GST_PLUGIN_DEFINE(GST_VERSION_MAJOR, GST_VERSION_MINOR, "bcmdec", "Video decoder", plugin_init, VERSION, "LGPL", "bcmdec", "http://broadcom.com/") crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/src/decif.c0000644000175000017500000001133411610313111024072 0ustar andresandres/******************************************************************** * Copyright(c) 2008 Broadcom Corporation. * * Name: decif.cpp * * Description: Device Interface API. * * AU * * HISTORY: * ******************************************************************* * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #include #include #include #include #include #include #include #include #include #include #include #include #include "decif.h" BC_STATUS decif_getcaps(BcmDecIF *decif, BC_HW_CAPS *hwCaps) { BC_STATUS sts = BC_STS_SUCCESS; if(decif != NULL) sts = DtsGetCapabilities(decif->hdev, hwCaps); else sts = DtsGetCapabilities(NULL, hwCaps); return sts; } BC_STATUS decif_open(BcmDecIF *decif) { BC_STATUS sts = BC_STS_SUCCESS; guint32 mode = DTS_PLAYBACK_MODE | DTS_LOAD_FILE_PLAY_FW | DTS_SKIP_TX_CHK_CPB | DTS_DFLT_RESOLUTION(vdecRESOLUTION_720p29_97); sts = DtsDeviceOpen(&decif->hdev,mode); if (sts != BC_STS_SUCCESS) decif->hdev = NULL; return sts; } BC_STATUS decif_close(BcmDecIF *decif) { BC_STATUS sts = BC_STS_SUCCESS; if (decif->hdev) { sts = DtsDeviceClose(decif->hdev); decif->hdev = NULL; } return sts; } BC_STATUS decif_prepare_play(BcmDecIF *decif) { BC_STATUS sts = BC_STS_SUCCESS; uint32_t stream_type = BC_STREAM_TYPE_ES; sts = DtsOpenDecoder(decif->hdev, stream_type); return sts; } BC_STATUS decif_start_play(BcmDecIF *decif) { BC_STATUS sts = DtsStartDecoder(decif->hdev); if (sts != BC_STS_SUCCESS) return sts; sts = DtsStartCapture(decif->hdev); return sts; } BC_STATUS decif_pause(BcmDecIF *decif, gboolean pause) { BC_STATUS sts; if (pause) sts = DtsPauseDecoder(decif->hdev); else sts = DtsResumeDecoder(decif->hdev); return sts; } BC_STATUS decif_stop(BcmDecIF *decif) { BC_STATUS sts = DtsStopDecoder(decif->hdev); if (sts != BC_STS_SUCCESS) return sts; sts = DtsCloseDecoder(decif->hdev); return sts; } BC_STATUS decif_flush_dec(BcmDecIF *decif, gint8 flush_type) { return DtsFlushInput(decif->hdev, flush_type); } BC_STATUS decif_flush_rxbuf(BcmDecIF *decif, gboolean discard_only) { return DtsFlushRxCapture(decif->hdev, discard_only); } BC_STATUS decif_setcolorspace(BcmDecIF *decif, BC_OUTPUT_FORMAT mode) { return DtsSetColorSpace(decif->hdev,mode); } BC_STATUS decif_send_buffer(BcmDecIF *decif, guint8 *buffer, guint32 size, GstClockTime time_stamp, guint8 flags) { BC_STATUS sts = BC_STS_SUCCESS; // guint8 odd_bytes = 0; // guint8 *psend_buff = decif->aligned_buf; // // while(((uintptr_t)psend_buff) & 0x03) // psend_buff++; // // if (((uintptr_t)buffer) % 4) odd_bytes = 4 - ((guint8)((uintptr_t)buffer % 4)); // // if (odd_bytes) { // memcpy(psend_buff, buffer, odd_bytes); // sts = DtsProcInput(decif->hdev, psend_buff, odd_bytes, time_stamp, flags); // time_stamp = 0; // if (sts != BC_STS_SUCCESS) // return sts; // buffer += odd_bytes; // size -= odd_bytes; // if (!size) // return BC_STS_SUCCESS; // } sts = DtsProcInput(decif->hdev, buffer, size, time_stamp, flags); return sts; } BC_STATUS decif_get_drv_status(BcmDecIF *decif, gboolean *suspended, guint32 *rll, guint32 *picNumFlags) { BC_DTS_STATUS drv_status; BC_STATUS sts = DtsGetDriverStatus(decif->hdev, &drv_status); if (sts == BC_STS_SUCCESS) { if (drv_status.PowerStateChange) *suspended = TRUE; else *suspended = FALSE; *rll = drv_status.ReadyListCount; *picNumFlags = drv_status.picNumFlags; } return sts; } BC_STATUS decif_get_eos(BcmDecIF *decif, gboolean *bEOS) { return DtsIsEndOfStream(decif->hdev, (uint8_t *)bEOS); } BC_STATUS decif_decode_catchup(BcmDecIF *decif, gboolean catchup) { BC_STATUS sts; return sts=BC_STS_SUCCESS; // Temporarily disable Catchup if (catchup) sts = DtsSetFFRate(decif->hdev, 2); else sts = DtsSetFFRate(decif->hdev, 1); return sts; } BC_STATUS decif_setinputformat(BcmDecIF *decif, BC_INPUT_FORMAT bcInputFormat) { BC_STATUS sts = BC_STS_SUCCESS; sts = DtsSetInputFormat(decif->hdev, &bcInputFormat); return sts; }crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/src/Makefile.am0000644000175000017500000000277011610313111024714 0ustar andresandres# plugindir is set in configure ROOTDIR = ../../../.. CC = g++ CPP = g++ INCLUDES = -I./ -I/usr/include -I/usr/include/libcrystalhd BCMDEC_CFLAGS = $(INCLUDES) -D__LINUX_USER__ -DWMV_FILE_HANDLING BCMDEC_CFLAGS += -O2 -g -Wall BCMDEC_LDFLAGS = -lcrystalhd ############################################################################## # change libgstplugin.la to something more suitable, e.g. libmysomething.la # ############################################################################## plugin_LTLIBRARIES = libgstbcmdec.la ############################################################################## # for the next set of variables, rename the prefix if you renamed the .la, # # e.g. libgstplugin_la_SOURCES => libgstbcmdec_la_SOURCES # # libgstplugin_la_CFLAGS => libgstbcmdec_la_CFLAGS # # libgstplugin_la_LIBADD => libgstbcmdec_la_LIBADD # # libgstplugin_la_LDFLAGS => libgstbcmdec_la_LDFLAGS # ############################################################################## # sources used to compile this plug-in libgstbcmdec_la_SOURCES = gstbcmdec.c decif.c parse.c # flags used to compile this plugin # add other _CFLAGS and _LIBS as needed libgstbcmdec_la_CFLAGS = $(GST_CFLAGS) $(BCMDEC_CFLAGS) libgstbcmdec_la_LIBADD = $(GST_LIBS) $(GST_PLUGINS_BASE_LIBS) libgstbcmdec_la_LDFLAGS = $(GST_PLUGIN_LDFLAGS) $(BCMDEC_LDFLAGS) # headers we need but don't want installed noinst_HEADERS = gstbcmdec.h decif.h parse.h crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/src/parse.c0000644000175000017500000001604411610313111024135 0ustar andresandres /******************************************************************* * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #include #include #include #include #include #include #include #include #include #include #include #include #include "bc_dts_defs.h" #include "bc_dts_types.h" #include "parse.h" void parse_init(Parse *parse) { parse->bIsFirstByteStreamNALU = TRUE; } gboolean parse_find_strt_code(Parse *parse, guint8 input_format, guint8 *in_buffer, guint32 size, guint32 *poffset) { guint32 i = 0; guint8 Suffix1 = 0; guint8 Suffix2 = 0; if (input_format == BC_VID_ALGO_VC1) { Suffix1 = VC1_FRM_SUFFIX; Suffix2 = VC1_SEQ_SUFFIX; } else if (input_format == BC_VID_ALGO_MPEG2) { Suffix1 = MPEG2_FRM_SUFFIX; Suffix2 = MPEG2_SEQ_SUFFIX; } /* For VC-1 SP/MP */ else if (input_format == BC_VID_ALGO_VC1MP) { Suffix1 = VC1_SM_FRM_SUFFIX; } if (input_format == BC_VID_ALGO_H264) { int nNalType = 0; uint32_t ulPos = 0; nNalType = parseAVC(parse, in_buffer, size, &ulPos); if ((nNalType == NALU_TYPE_SEI) || (nNalType == NALU_TYPE_PPS) || (nNalType == NALU_TYPE_SPS)) { *poffset = ulPos; return TRUE; } else if ((nNalType == NALU_TYPE_SLICE) | (nNalType == NALU_TYPE_IDR)) { *poffset = 0; return TRUE; } } else { /* VC1, MPEG2 */ while (i < size) { if ((*(in_buffer + i) == Suffix1) || (*(in_buffer + i) == Suffix2)) { if (i >= 3) { if ((*(in_buffer + (i - 3)) == 0x00) && (*(in_buffer + (i - 2)) == 0x00) && (*(in_buffer + (i - 1)) == 0x01)) { *poffset = i-3; return TRUE; } } } i++; } } return FALSE; } gint FindBSStartCode(guint8 *Buf, gint ZerosInStartcode) { gboolean bStartCode = TRUE; gint i; for (i = 0; i < ZerosInStartcode; i++) if (Buf[i] != 0) bStartCode = FALSE; if (Buf[i] != 1) bStartCode = FALSE; return bStartCode; } gint GetNaluType(Parse *parse, guint8 *pInputBuf, guint32 ulSize, NALU_t *pNalu) { gint b20sInSC, b30sInSC; gint bStartCodeFound, Rewind; gint nLeadingZero8BitsCount = 0, TrailingZero8Bits = 0; guint32 Pos = 0; while (Pos <= ulSize) { if ((pInputBuf[Pos++]) == 0) continue; else break; } if (pInputBuf[Pos - 1] != 1) return -1; if (Pos < 3) { return -1; } else if (Pos == 3) { pNalu->StartcodePrefixLen = 3; nLeadingZero8BitsCount = 0; } else { nLeadingZero8BitsCount = Pos - 4; pNalu->StartcodePrefixLen = 4; } /* * the 1st byte stream NAL unit can has nLeadingZero8BitsCount, but subsequent * ones are not allowed to contain it since these zeros (if any) are considered * trailing_zero_8bits of the previous byte stream NAL unit. */ if (!parse->bIsFirstByteStreamNALU && nLeadingZero8BitsCount > 0) return -1; parse->bIsFirstByteStreamNALU = false; bStartCodeFound = 0; b20sInSC = 0; b30sInSC = 0; while ((!bStartCodeFound) && (Pos < ulSize)) { Pos++; if (Pos > ulSize) printf("GetNaluType : Pos > size = %d\n", ulSize); b30sInSC = FindBSStartCode((pInputBuf + Pos - 4), 3); if (b30sInSC != 1) b20sInSC = FindBSStartCode((pInputBuf + Pos - 3), 2); bStartCodeFound = (b20sInSC || b30sInSC); } Rewind = 0; #if 0 if (!bStartCodeFound) { //even if next start code is not found pprocess this NAL. return -1; } #endif if (bStartCodeFound) { //Count the trailing_zero_8bits //TrailingZero8Bits is present only for start code 00 00 00 01 if (b30sInSC) { while(pInputBuf[Pos - 5 - TrailingZero8Bits] == 0) TrailingZero8Bits++; } // Here, we have found another start code (and read length of startcode bytes more than we should // have. Hence, go back in the file if (b30sInSC) Rewind = -4; else if (b20sInSC) Rewind = -3; } // Here the leading zeros(if any), Start code, the complete NALU, trailing zeros(if any) // until the next start code . // Total size traversed is Pos, Pos+rewind are the number of bytes excluding the next // start code, and (Pos+rewind)-StartcodePrefixLen-LeadingZero8BitsCount-TrailingZero8Bits // is the size of the NALU. pNalu->Len = (Pos + Rewind) - pNalu->StartcodePrefixLen - nLeadingZero8BitsCount - TrailingZero8Bits; pNalu->NalUnitType = (pInputBuf[nLeadingZero8BitsCount + pNalu->StartcodePrefixLen]) & 0x1f; return (Pos+Rewind); } gint parseAVC(Parse *parse, guint8 *pInputBuf, guint32 ulSize, guint32 *Offset) { NALU_t Nalu; gint ret = 0; guint32 Pos = 0; gboolean bResult = false; while (1) { ret = GetNaluType(parse, pInputBuf + Pos, ulSize - Pos, &Nalu); if (ret <= 0) return -1; Pos += ret; switch (Nalu.NalUnitType) { case NALU_TYPE_SLICE: case NALU_TYPE_IDR: bResult = true; break; case NALU_TYPE_SEI: case NALU_TYPE_PPS: case NALU_TYPE_SPS: bResult = true; break; case NALU_TYPE_DPA: case NALU_TYPE_DPC: case NALU_TYPE_AUD: case NALU_TYPE_EOSEQ: case NALU_TYPE_EOSTREAM: case NALU_TYPE_FILL: default: break; } if (bResult) { *Offset = Pos; break; } } return Nalu.NalUnitType; } gboolean SiBuffer(SymbInt *simb_int, guint8 *pInputBuffer, guint32 ulSize) { simb_int->m_pCurrent = simb_int->m_pInputBuffer = (guint8 *)pInputBuffer; simb_int->m_nSize = ulSize; simb_int->m_pInputBufferEnd = simb_int->m_pInputBuffer + ulSize; simb_int->m_nUsed = 1; simb_int->m_ulOffset = 0; simb_int->m_ulMask = 0x80; return TRUE; } gboolean SiUe(SymbInt *simb_int, guint32 *pCode) { guint32 ulSuffix; int nLeadingZeros; int nBit; nLeadingZeros = -1; for (nBit = 0; nBit == 0; nLeadingZeros++) { nBit = NextBit(simb_int); if (simb_int->m_nUsed >= simb_int->m_nSize) return FALSE; } *pCode = (1 << nLeadingZeros) - 1; ulSuffix = 0; while (nLeadingZeros-- > 0) { ulSuffix = (ulSuffix << 1) | NextBit(simb_int); if (simb_int->m_nUsed >= simb_int->m_nSize) return FALSE; } *pCode += ulSuffix; return TRUE; } inline gint NextBit(SymbInt *simb_int) { int nBit; nBit = (simb_int->m_pCurrent[0] & simb_int->m_ulMask) ? 1 : 0; if ((simb_int->m_ulMask >>= 1) == 0) { simb_int->m_ulMask = 0x80; if (simb_int->m_nUsed == simb_int->m_nSize) simb_int->m_pCurrent = simb_int->m_pInputBuffer; //reset look again else { if (++simb_int->m_pCurrent == simb_int->m_pInputBufferEnd) simb_int->m_pCurrent = simb_int->m_pInputBuffer; simb_int->m_nUsed++; } } simb_int->m_ulOffset++; return nBit; } guint32 SiOffset(SymbInt *simb_int) { return simb_int->m_ulOffset; } crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/src/version_lnx.h0000644000175000017500000001026711610313111025377 0ustar andresandres/******************************************************************** * Copyright(c) 2006 Broadcom Corporation. * * Name: version_lnx.h * * Description: Version numbering for the driver use. * * AU * * HISTORY: * ******************************************************************* * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #ifndef _BC_DTS_VERSION_LNX_ #define _BC_DTS_VERSION_LNX_ // // The version format that we are adopting is // MajorVersion.MinorVersion.Revision // This will be the same for all the components. // // #define STRINGIFY_VERSION(MAJ,MIN,REV) STRINGIFIED_VERSION(MAJ,MIN,REV) #define STRINGIFIED_VERSION(MAJ,MIN,REV) #MAJ "." #MIN "." #REV #define STRINGIFY_VERSION_W(MAJ,MIN,REV) STRINGIFIED_VERSION_W(MAJ,MIN,REV) #define STRINGIFIED_VERSION_W(MAJ,MIN,REV) #MAJ "." #MIN "." #REV // // Product Version number is: // x.y.z.a // // x = Major release. 1 = Dozer, 2 = Dozer + Link // y = Minor release. Should increase +1 per "real" release. // z = Branch release. 0 for main branch. This is +1 per branch release. // a = Build number +1 per candidate release. Reset to 0 every "real" release. // // // Enabling Check-In rules enforcement 08092007 // #define INVALID_VERSION 0xFFFF /*========================== Common For All Components =================================*/ #define RC_COMPANY_NAME "Broadcom Corporation\0" #define RC_PRODUCT_VERSION "2.7.0.23" #define RC_W_PRODUCT_VERSION L"2.7.0.23" #define RC_PRODUCT_NAME "Broadcom Video Decoder\0" #define RC_COMMENTS "Broadcom BCM70010/BCM70012 Controller\0" #define RC_COPYRIGHT "Copyright(c) 2007 Broadcom Corporation" #define RC_PRIVATE_BUILD "Broadcom Corp. Private\0" #define RC_LEGAL_TRADEMARKS " \0" #define BRCM_MAJOR_VERSION 0 /*========================== WDM Driver =================================*/ /* * Version number scheme for driver DVMJVer.DVMNVer.DVRev.UNMODIFIED * Where DVMJVer = DRIVER_MAJOR_VERSION * DVMNVer = DRIVER_MINOR_VERSION * DVRev = DRIVER_REVISION * UNMODIFIED = This is for Compatibility with windows INF file version scheme. */ #define RC_FILE_DESCRIPTION "Broadcom BCM70010/BCM70012 Driver\0" #define RC_INTERNAL_NAME "" #define RC_ORIGINAL_NAME RC_INTERNAL_NAME #define RC_SPECIAL_BUILD "" #define DRIVER_MAJOR_VERSION BRCM_MAJOR_VERSION #define DRIVER_MINOR_VERSION 1 #define DRIVER_REVISION 0 #define RC_FILE_VERSION STRINGIFY_VERSION(DRIVER_MAJOR_VERSION,DRIVER_MINOR_VERSION,DRIVER_REVISION) ".0" /*======================= Device Interface Library ========================*/ #define DIL_MAJOR_VERSION BRCM_MAJOR_VERSION #define DIL_MINOR_VERSION 1 #define DIL_REVISION 0 #define DIL_RC_FILE_VERSION STRINGIFY_VERSION(DIL_MAJOR_VERSION,DIL_MINOR_VERSION,DIL_REVISION) /*========================== deconf utility ==============================*/ #define DECONF_MAJOR_VERSION BRCM_MAJOR_VERSION #define DECONF_MINOR_VERSION 1 #define DECONF_REVISION 0 #define DECONF_RC_FILE_VERSION STRINGIFY_VERSION(DIL_MAJOR_VERSION,DIL_MINOR_VERSION,DIL_REVISION) #ifndef _PB_FIX_ME_ /*======================= deconft utility ========================*/ #define DECONFT_MAJOR_VERSION BRCM_MAJOR_VERSION #define DECONFT_MINOR_VERSION 1 #define DECONFT_REVISION 0 #define DECONFT_RC_FILE_VERSION STRINGIFY_VERSION(DECONFT_MAJOR_VERSION,DECONFT_MINOR_VERSION,DECONFT_REVISION) #endif #endif crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/src/parse.h0000644000175000017500000000515711610313111024145 0ustar andresandres/******************************************************************* * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #ifndef CPARSE #define CPARSE //VC1 prefix 000001 #define VC1_FRM_SUFFIX 0x0D #define VC1_SEQ_SUFFIX 0x0F //VC1 SM Profile prefix 000001 #define VC1_SM_FRM_SUFFIX 0xE0 //Check WMV SP/MP PES Payload for PTS Info #define VC1_SM_MAGIC_WORD 0x5A5A5A5A #define VC1_SM_PTS_INFO_START_CODE 0xBD //MPEG2 prefix 000001 #define MPEG2_FRM_SUFFIX 0x00 #define MPEG2_SEQ_SUFFIX 0xB3 typedef enum { P_SLICE = 0, B_SLICE, I_SLICE, SP_SLICE, SI_SLICE } SliceType; typedef enum { NALU_TYPE_SLICE = 1, NALU_TYPE_DPA, NALU_TYPE_DPB, NALU_TYPE_DPC, NALU_TYPE_IDR, NALU_TYPE_SEI, NALU_TYPE_SPS, NALU_TYPE_PPS, NALU_TYPE_AUD, NALU_TYPE_EOSEQ, NALU_TYPE_EOSTREAM, NALU_TYPE_FILL }NALuType; typedef struct { gint StartcodePrefixLen; //! 4 for parameter sets and first slice in picture, 3 for everything else (suggested) guint Len; //! Length of the NAL unit (Excluding the start code, which does not belong to the NALU) guint MaxSize; //! Nal Unit Buffer size gint NalUnitType; //! NALU_TYPE_xxxx gint ForbiddenBit; //! should be always FALSE guint8* pNalBuf; } NALU_t; typedef struct { guint8* m_pInputBuffer; guint8* m_pInputBufferEnd; guint8* m_pCurrent; guint32 m_ulMask; guint32 m_ulOffset; gint m_nSize; gint m_nUsed; guint32 m_ulZero; }SymbInt; typedef struct { gboolean bIsFirstByteStreamNALU; SymbInt symb_int; }Parse; void parse_init(Parse* parse); gint parseAVC(Parse* parse,guint8* pInputBuf,guint32 ulSize,guint32* Offset); gboolean parse_find_strt_code(Parse* parse,guint8 input_format,guint8* in_buffer,guint32 size,guint32* poffset); gint GetNaluType(Parse* parse,guint8* pInputBuf, guint32 ulSize, NALU_t* pNalu); gboolean SiBuffer(SymbInt* simb_int,guint8 * pInputBuffer, guint32 ulSize); gboolean SiUe(SymbInt* simb_int,guint32* pCode); guint32 SiOffset(SymbInt*); inline gint NextBit ( SymbInt*); #endif crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/src/version.h0000644000175000017500000002057511610313111024521 0ustar andresandres/******************************************************************** * Copyright(c) 2006 Broadcom Corporation. * * Name: version.h * * Description: Version numbering for the driver use. * * AU * * HISTORY: * ******************************************************************* * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #ifndef _BC_DTS_VERSION_ #define _BC_DTS_VERSION_ // // The version format that we are adopting is // MajorVersion.MinorVersion.Revision // This will be the same for all the components. // // #define STRINGIFY_VERSION(MAJ,MIN,REV) STRINGIFIED_VERSION(MAJ,MIN,REV) #define STRINGIFIED_VERSION(MAJ,MIN,REV) #MAJ "." #MIN "." #REV #define STRINGIFY_VERSION_W(MAJ,MIN,REV) STRINGIFIED_VERSION_W(MAJ,MIN,REV) #define STRINGIFIED_VERSION_W(MAJ,MIN,REV) #MAJ "." #MIN "." #REV // // Product Version number is: // x.y.z.a // // x = Major release. 1 = Dozer, 2 = Dozer + Link // y = Minor release. Should increase +1 per "real" release. // z = Branch release. 0 for main branch. This is +1 per branch release. // a = Build number +1 per candidate release. Reset to 0 every "real" release. // // // Enabling Check-In rules enforcement 08092007 // #define INVALID_VERSION 0xFFFF /*========================== Common For All Components =================================*/ #define RC_COMPANY_NAME "Broadcom Corporation\0" #define RC_PRODUCT_VERSION "2.7.0.25" #define RC_W_PRODUCT_VERSION L"2.7.0.25" #define RC_PRODUCT_NAME "Broadcom Video Decoder\0" #define RC_COMMENTS "Broadcom BCM70010/BCM70012 Controller\0" #define RC_COPYRIGHT "Copyright(c) 2007 Broadcom Corporation" #define RC_PRIVATE_BUILD "Broadcom Corp. Private\0" #define RC_LEGAL_TRADEMARKS " \0" #define BRCM_MAJOR_VERSION 2 /*========================== WDM Driver =================================*/ /* * Version number scheme for driver DVMJVer.DVMNVer.DVRev.UNMODIFIED * Where DVMJVer = DRIVER_MAJOR_VERSION * DVMNVer = DRIVER_MINOR_VERSION * DVRev = DRIVER_REVISION * UNMODIFIED = This is for Compatibility with windows INF file version scheme. */ #define RC_FILE_DESCRIPTION "Broadcom BCM70010/BCM70012 Driver\0" #define RC_INTERNAL_NAME "" #define RC_ORIGINAL_NAME RC_INTERNAL_NAME #define RC_SPECIAL_BUILD "" #define DRIVER_MAJOR_VERSION BRCM_MAJOR_VERSION #define DRIVER_MINOR_VERSION 31 #define DRIVER_REVISION 0 #define RC_FILE_VERSION STRINGIFY_VERSION(DRIVER_MAJOR_VERSION,DRIVER_MINOR_VERSION,DRIVER_REVISION) ".0" /*======================= Device Interface Library ========================*/ #define DIL_MAJOR_VERSION BRCM_MAJOR_VERSION #define DIL_MINOR_VERSION 26 #define DIL_REVISION 0 #define DIL_RC_FILE_VERSION STRINGIFY_VERSION(DIL_MAJOR_VERSION,DIL_MINOR_VERSION,DIL_REVISION) /*========================== Direct Show Filter ==============================*/ #define DFILTER_MAJOR_VERSION BRCM_MAJOR_VERSION #define DFILTER_MINOR_VERSION 26 #define DFILTER_REVISION 0 #define DFILTER_RC_FILE_VERSION STRINGIFY_VERSION(DFILTER_MAJOR_VERSION,DFILTER_MINOR_VERSION,DFILTER_REVISION) /*========================== Direct Show NS Filter ==============================*/ #define NS_DFILTER_MAJOR_VERSION BRCM_MAJOR_VERSION #define NS_DFILTER_MINOR_VERSION 41 #define NS_DFILTER_REVISION 0 #define NS_DFILTER_RC_FILE_VERSION STRINGIFY_VERSION(NS_DFILTER_MAJOR_VERSION,NS_DFILTER_MINOR_VERSION,NS_DFILTER_REVISION) /*========================== deconf utility ==============================*/ #define DECONF_MAJOR_VERSION BRCM_MAJOR_VERSION #define DECONF_MINOR_VERSION 10 #define DECONF_REVISION 0 /*========================== MP-4 Demux Filter ==============================*/ #define MP4DEMUX_MAJOR_VERSION BRCM_MAJOR_VERSION #define MP4DEMUX_MINOR_VERSION 7 #define MP4DEMUX_REVISION 0 #define MP4DEMUX_RC_FILE_VERSION STRINGIFY_VERSION(MP4DEMUX_MAJOR_VERSION,MP4DEMUX_MINOR_VERSION,MP4DEMUX_REVISION) /*========================== MFT Decoder ==============================*/ #define MFTDECODER_MAJOR_VERSION BRCM_MAJOR_VERSION #define MFTDECODER_MINOR_VERSION 4 #define MFTDECODER_REVISION 0 #define MFTDECODER_RC_FILE_VERSION STRINGIFY_VERSION(MFTDECODER_MAJOR_VERSION,MFTDECODER_MINOR_VERSION,MFTDECODER_REVISION) /*======================= deconft utility ========================*/ #define DECONFT_MAJOR_VERSION BRCM_MAJOR_VERSION #define DECONFT_MINOR_VERSION 8 #define DECONFT_REVISION 0 #define DECONFT_RC_FILE_VERSION STRINGIFY_VERSION(DECONFT_MAJOR_VERSION,DECONFT_MINOR_VERSION,DECONFT_REVISION) /*======================= Gensig utility ========================*/ #define GENSIG_MAJOR_VERSION BRCM_MAJOR_VERSION #define GENSIG_MINOR_VERSION 7 #define GENSIG_REVISION 0 #define GENSIG_RC_FILE_VERSION STRINGIFY_VERSION(GENSIG_MAJOR_VERSION,GENSIG_MINOR_VERSION,GENSIG_REVISION) /*======================= FpgaProg utility ========================*/ #define FPGAPROG_MAJOR_VERSION BRCM_MAJOR_VERSION #define FPGAPROG_MINOR_VERSION 1 #define FPGAPROG_REVISION 0 #define FPGAPROG_RC_FILE_VERSION STRINGIFY_VERSION(FPGAPROG_MAJOR_VERSION,FPGAPROG_MINOR_VERSION,FPGAPROG_REVISION) /*======================= CHDGensig DataBase Library ========================*/ #define CHDGSDB_MAJOR_VERSION BRCM_MAJOR_VERSION #define CHDGSDB_MINOR_VERSION 3 #define CHDGSDB_REVISION 0 #define CHDGSDB_RC_FILE_VERSION STRINGIFY_VERSION(CHDGSDB_MAJOR_VERSION,CHDGSDB_MINOR_VERSION,CHDGSDB_REVISION) /*======================= CHDDosDiag utility ========================*/ #define DOSDIAG_MAJOR_VERSION BRCM_MAJOR_VERSION #define DOSDIAG_MINOR_VERSION 9 #define DOSDIAG_REVISION 0 #define DOSDIAG_RC_FILE_VERSION STRINGIFY_VERSION(DOSDIAG_MAJOR_VERSION,DOSDIAG_MINOR_VERSION,DOSDIAG_REVISION) /*======================= CHDWinDiag utility ========================*/ #define WINDIAG_MAJOR_VERSION BRCM_MAJOR_VERSION #define WINDIAG_MINOR_VERSION 12 #define WINDIAG_REVISION 0 #define WINDIAG_RC_FILE_VERSION STRINGIFY_VERSION(WINDIAG_MAJOR_VERSION,WINDIAG_MINOR_VERSION,WINDIAG_REVISION) /*======================= CHDWinInfo utility ========================*/ #define WININFO_MAJOR_VERSION BRCM_MAJOR_VERSION #define WININFO_MINOR_VERSION 1 #define WININFO_REVISION 0 #define WININFO_RC_FILE_VERSION STRINGIFY_VERSION(WININFO_MAJOR_VERSION,WININFO_MINOR_VERSION,WININFO_REVISION) /*========================== WDM Encode Driver =================================*/ #define ENCODE_WDM_COMMENTS "Broadcom Corp. BCM70013 Encoder\0" #define ENCODE_WDM_PRODUCT_NAME "Broadcom Corp. MediaPC HD Video Encoder\0" #define ENCODE_WDM_PRIVATE_BUILD "Broadcom Corp. Private\0" #define ENCODE_WDM_FILE_DESC "Broadcom Corp BCM70013 WDM Driver\0" #define ENCODE_WDM_INTRL_NAME "Link B0" #define ENCODE_WDM_ORIG_NAME ENCODE_WDM_INTRL_NAME #define ENCODE_WDM_SPECIAL_BUILD "" #define ENCODE_WDM_MAJOR_VERSION BRCM_MAJOR_VERSION #define ENCODE_WDM_MINOR_VERSION 0 #define ENCODE_WDM_REVISION 1 #define ENCODE_WDM_FILE_VERSION STRINGIFY_VERSION(ENCODE_WDM_MAJOR_VERSION,ENCODE_WDM_MINOR_VERSION,ENCODE_WDM_REVISION) ".0" /*========================== CmdUtil Application ==============================*/ #define CMDUTIL_MAJOR_VERSION BRCM_MAJOR_VERSION #define CMDUTIL_MINOR_VERSION 0 #define CMDUTIL_REVISION 0 /*========================== CmdUtilt utility ==============================*/ #define CMDUTILT_MAJOR_VERSION BRCM_MAJOR_VERSION #define CMDUTILT_MINOR_VERSION 0 #define CMDUTILT_REVISION #endif crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/src/Makefile.in0000644000175000017500000005320511610313116024731 0ustar andresandres# Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ # plugindir is set in configure VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : PRE_INSTALL = : POST_INSTALL = : NORMAL_UNINSTALL = : PRE_UNINSTALL = : POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ subdir = src DIST_COMMON = $(noinst_HEADERS) $(srcdir)/Makefile.am \ $(srcdir)/Makefile.in ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/m4/as-compiler-flag.m4 \ $(top_srcdir)/m4/as-version.m4 $(top_srcdir)/configure.ac am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) mkinstalldirs = $(install_sh) -d CONFIG_HEADER = $(top_builddir)/config.h CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = am__vpath_adj_setup = srcdirstrip=`echo "$(srcdir)" | sed 's|.|.|g'`; am__vpath_adj = case $$p in \ $(srcdir)/*) f=`echo "$$p" | sed "s|^$$srcdirstrip/||"`;; \ *) f=$$p;; \ esac; am__strip_dir = f=`echo $$p | sed -e 's|^.*/||'`; am__install_max = 40 am__nobase_strip_setup = \ srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*|]/\\\\&/g'` am__nobase_strip = \ for p in $$list; do echo "$$p"; done | sed -e "s|$$srcdirstrip/||" am__nobase_list = $(am__nobase_strip_setup); \ for p in $$list; do echo "$$p $$p"; done | \ sed "s| $$srcdirstrip/| |;"' / .*\//!s/ .*/ ./; s,\( .*\)/[^/]*$$,\1,' | \ $(AWK) 'BEGIN { files["."] = "" } { files[$$2] = files[$$2] " " $$1; \ if (++n[$$2] == $(am__install_max)) \ { print $$2, files[$$2]; n[$$2] = 0; files[$$2] = "" } } \ END { for (dir in files) print dir, files[dir] }' am__base_list = \ sed '$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;$$!N;s/\n/ /g' | \ sed '$$!N;$$!N;$$!N;$$!N;s/\n/ /g' am__installdirs = "$(DESTDIR)$(plugindir)" LTLIBRARIES = $(plugin_LTLIBRARIES) am__DEPENDENCIES_1 = libgstbcmdec_la_DEPENDENCIES = $(am__DEPENDENCIES_1) am_libgstbcmdec_la_OBJECTS = libgstbcmdec_la-gstbcmdec.lo \ libgstbcmdec_la-decif.lo libgstbcmdec_la-parse.lo libgstbcmdec_la_OBJECTS = $(am_libgstbcmdec_la_OBJECTS) libgstbcmdec_la_LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) \ $(LIBTOOLFLAGS) --mode=link $(CCLD) $(libgstbcmdec_la_CFLAGS) \ $(CFLAGS) $(libgstbcmdec_la_LDFLAGS) $(LDFLAGS) -o $@ DEFAULT_INCLUDES = -I.@am__isrc@ -I$(top_builddir) depcomp = $(SHELL) $(top_srcdir)/depcomp am__depfiles_maybe = depfiles am__mv = mv -f COMPILE = $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) \ $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) LTCOMPILE = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) \ $(AM_CPPFLAGS) $(CPPFLAGS) $(AM_CFLAGS) $(CFLAGS) CCLD = $(CC) LINK = $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) \ --mode=link $(CCLD) $(AM_CFLAGS) $(CFLAGS) $(AM_LDFLAGS) \ $(LDFLAGS) -o $@ SOURCES = $(libgstbcmdec_la_SOURCES) DIST_SOURCES = $(libgstbcmdec_la_SOURCES) HEADERS = $(noinst_HEADERS) ETAGS = etags CTAGS = ctags DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) ACLOCAL = @ACLOCAL@ ACLOCAL_AMFLAGS = @ACLOCAL_AMFLAGS@ AMTAR = @AMTAR@ AR = @AR@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ CC = g++ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ CPP = g++ CPPFLAGS = @CPPFLAGS@ CYGPATH_W = @CYGPATH_W@ DEFS = @DEFS@ DEPDIR = @DEPDIR@ DLLTOOL = @DLLTOOL@ DSYMUTIL = @DSYMUTIL@ DUMPBIN = @DUMPBIN@ ECHO_C = @ECHO_C@ ECHO_N = @ECHO_N@ ECHO_T = @ECHO_T@ EGREP = @EGREP@ EXEEXT = @EXEEXT@ FGREP = @FGREP@ GREP = @GREP@ GSTCTRL_CFLAGS = @GSTCTRL_CFLAGS@ GSTCTRL_LIBS = @GSTCTRL_LIBS@ GSTPB_BASE_CFLAGS = @GSTPB_BASE_CFLAGS@ GSTPB_BASE_LIBS = @GSTPB_BASE_LIBS@ GST_BASE_CFLAGS = @GST_BASE_CFLAGS@ GST_BASE_LIBS = @GST_BASE_LIBS@ GST_CFLAGS = @GST_CFLAGS@ GST_LIBS = @GST_LIBS@ GST_MAJORMINOR = @GST_MAJORMINOR@ GST_PLUGIN_LDFLAGS = @GST_PLUGIN_LDFLAGS@ GST_PLUGIN_VERSION = @GST_PLUGIN_VERSION@ GST_PLUGIN_VERSION_MAJOR = @GST_PLUGIN_VERSION_MAJOR@ GST_PLUGIN_VERSION_MICRO = @GST_PLUGIN_VERSION_MICRO@ GST_PLUGIN_VERSION_MINOR = @GST_PLUGIN_VERSION_MINOR@ GST_PLUGIN_VERSION_NANO = @GST_PLUGIN_VERSION_NANO@ GST_PLUGIN_VERSION_RELEASE = @GST_PLUGIN_VERSION_RELEASE@ HAVE_PKGCONFIG = @HAVE_PKGCONFIG@ INSTALL = @INSTALL@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_SCRIPT = @INSTALL_SCRIPT@ INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ LD = @LD@ LDFLAGS = @LDFLAGS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIPO = @LIPO@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAKEINFO = @MAKEINFO@ MANIFEST_TOOL = @MANIFEST_TOOL@ MKDIR_P = @MKDIR_P@ NM = @NM@ NMEDIT = @NMEDIT@ OBJDUMP = @OBJDUMP@ OBJEXT = @OBJEXT@ OTOOL = @OTOOL@ OTOOL64 = @OTOOL64@ PACKAGE = @PACKAGE@ PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ PACKAGE_NAME = @PACKAGE_NAME@ PACKAGE_STRING = @PACKAGE_STRING@ PACKAGE_TARNAME = @PACKAGE_TARNAME@ PACKAGE_URL = @PACKAGE_URL@ PACKAGE_VERSION = @PACKAGE_VERSION@ PATH_SEPARATOR = @PATH_SEPARATOR@ PKG_CONFIG = @PKG_CONFIG@ PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ abs_builddir = @abs_builddir@ abs_srcdir = @abs_srcdir@ abs_top_builddir = @abs_top_builddir@ abs_top_srcdir = @abs_top_srcdir@ ac_ct_AR = @ac_ct_AR@ ac_ct_CC = @ac_ct_CC@ ac_ct_DUMPBIN = @ac_ct_DUMPBIN@ am__include = @am__include@ am__leading_dot = @am__leading_dot@ am__quote = @am__quote@ am__tar = @am__tar@ am__untar = @am__untar@ bindir = @bindir@ build = @build@ build_alias = @build_alias@ build_cpu = @build_cpu@ build_os = @build_os@ build_vendor = @build_vendor@ builddir = @builddir@ datadir = @datadir@ datarootdir = @datarootdir@ docdir = @docdir@ dvidir = @dvidir@ exec_prefix = @exec_prefix@ host = @host@ host_alias = @host_alias@ host_cpu = @host_cpu@ host_os = @host_os@ host_vendor = @host_vendor@ htmldir = @htmldir@ includedir = @includedir@ infodir = @infodir@ install_sh = @install_sh@ libdir = @libdir@ libexecdir = @libexecdir@ localedir = @localedir@ localstatedir = @localstatedir@ mandir = @mandir@ mkdir_p = @mkdir_p@ oldincludedir = @oldincludedir@ pdfdir = @pdfdir@ plugindir = @plugindir@ prefix = @prefix@ program_transform_name = @program_transform_name@ psdir = @psdir@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ srcdir = @srcdir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ ROOTDIR = ../../../.. INCLUDES = -I./ -I/usr/include -I/usr/include/libcrystalhd BCMDEC_CFLAGS = $(INCLUDES) -D__LINUX_USER__ -DWMV_FILE_HANDLING -O2 \ -g -Wall BCMDEC_LDFLAGS = -lcrystalhd ############################################################################## # change libgstplugin.la to something more suitable, e.g. libmysomething.la # ############################################################################## plugin_LTLIBRARIES = libgstbcmdec.la ############################################################################## # for the next set of variables, rename the prefix if you renamed the .la, # # e.g. libgstplugin_la_SOURCES => libgstbcmdec_la_SOURCES # # libgstplugin_la_CFLAGS => libgstbcmdec_la_CFLAGS # # libgstplugin_la_LIBADD => libgstbcmdec_la_LIBADD # # libgstplugin_la_LDFLAGS => libgstbcmdec_la_LDFLAGS # ############################################################################## # sources used to compile this plug-in libgstbcmdec_la_SOURCES = gstbcmdec.c decif.c parse.c # flags used to compile this plugin # add other _CFLAGS and _LIBS as needed libgstbcmdec_la_CFLAGS = $(GST_CFLAGS) $(BCMDEC_CFLAGS) libgstbcmdec_la_LIBADD = $(GST_LIBS) $(GST_PLUGINS_BASE_LIBS) libgstbcmdec_la_LDFLAGS = $(GST_PLUGIN_LDFLAGS) $(BCMDEC_LDFLAGS) # headers we need but don't want installed noinst_HEADERS = gstbcmdec.h decif.h parse.h all: all-am .SUFFIXES: .SUFFIXES: .c .lo .o .obj $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \ && { if test -f $@; then exit 0; else break; fi; }; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --gnu src/Makefile'; \ $(am__cd) $(top_srcdir) && \ $(AUTOMAKE) --gnu src/Makefile .PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ *) \ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ esac; $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(am__aclocal_m4_deps): install-pluginLTLIBRARIES: $(plugin_LTLIBRARIES) @$(NORMAL_INSTALL) test -z "$(plugindir)" || $(MKDIR_P) "$(DESTDIR)$(plugindir)" @list='$(plugin_LTLIBRARIES)'; test -n "$(plugindir)" || list=; \ list2=; for p in $$list; do \ if test -f $$p; then \ list2="$$list2 $$p"; \ else :; fi; \ done; \ test -z "$$list2" || { \ echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(INSTALL) $(INSTALL_STRIP_FLAG) $$list2 '$(DESTDIR)$(plugindir)'"; \ $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=install $(INSTALL) $(INSTALL_STRIP_FLAG) $$list2 "$(DESTDIR)$(plugindir)"; \ } uninstall-pluginLTLIBRARIES: @$(NORMAL_UNINSTALL) @list='$(plugin_LTLIBRARIES)'; test -n "$(plugindir)" || list=; \ for p in $$list; do \ $(am__strip_dir) \ echo " $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f '$(DESTDIR)$(plugindir)/$$f'"; \ $(LIBTOOL) $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=uninstall rm -f "$(DESTDIR)$(plugindir)/$$f"; \ done clean-pluginLTLIBRARIES: -test -z "$(plugin_LTLIBRARIES)" || rm -f $(plugin_LTLIBRARIES) @list='$(plugin_LTLIBRARIES)'; for p in $$list; do \ dir="`echo $$p | sed -e 's|/[^/]*$$||'`"; \ test "$$dir" != "$$p" || dir=.; \ echo "rm -f \"$${dir}/so_locations\""; \ rm -f "$${dir}/so_locations"; \ done libgstbcmdec.la: $(libgstbcmdec_la_OBJECTS) $(libgstbcmdec_la_DEPENDENCIES) $(libgstbcmdec_la_LINK) -rpath $(plugindir) $(libgstbcmdec_la_OBJECTS) $(libgstbcmdec_la_LIBADD) $(LIBS) mostlyclean-compile: -rm -f *.$(OBJEXT) distclean-compile: -rm -f *.tab.c @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libgstbcmdec_la-decif.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libgstbcmdec_la-gstbcmdec.Plo@am__quote@ @AMDEP_TRUE@@am__include@ @am__quote@./$(DEPDIR)/libgstbcmdec_la-parse.Plo@am__quote@ .c.o: @am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $< @am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po @AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(COMPILE) -c $< .c.obj: @am__fastdepCC_TRUE@ $(COMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ `$(CYGPATH_W) '$<'` @am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Po @AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=no @AMDEPBACKSLASH@ @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(COMPILE) -c `$(CYGPATH_W) '$<'` .c.lo: @am__fastdepCC_TRUE@ $(LTCOMPILE) -MT $@ -MD -MP -MF $(DEPDIR)/$*.Tpo -c -o $@ $< @am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/$*.Tpo $(DEPDIR)/$*.Plo @AMDEP_TRUE@@am__fastdepCC_FALSE@ source='$<' object='$@' libtool=yes @AMDEPBACKSLASH@ @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(LTCOMPILE) -c -o $@ $< libgstbcmdec_la-gstbcmdec.lo: gstbcmdec.c @am__fastdepCC_TRUE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libgstbcmdec_la_CFLAGS) $(CFLAGS) -MT libgstbcmdec_la-gstbcmdec.lo -MD -MP -MF $(DEPDIR)/libgstbcmdec_la-gstbcmdec.Tpo -c -o libgstbcmdec_la-gstbcmdec.lo `test -f 'gstbcmdec.c' || echo '$(srcdir)/'`gstbcmdec.c @am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libgstbcmdec_la-gstbcmdec.Tpo $(DEPDIR)/libgstbcmdec_la-gstbcmdec.Plo @AMDEP_TRUE@@am__fastdepCC_FALSE@ source='gstbcmdec.c' object='libgstbcmdec_la-gstbcmdec.lo' libtool=yes @AMDEPBACKSLASH@ @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libgstbcmdec_la_CFLAGS) $(CFLAGS) -c -o libgstbcmdec_la-gstbcmdec.lo `test -f 'gstbcmdec.c' || echo '$(srcdir)/'`gstbcmdec.c libgstbcmdec_la-decif.lo: decif.c @am__fastdepCC_TRUE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libgstbcmdec_la_CFLAGS) $(CFLAGS) -MT libgstbcmdec_la-decif.lo -MD -MP -MF $(DEPDIR)/libgstbcmdec_la-decif.Tpo -c -o libgstbcmdec_la-decif.lo `test -f 'decif.c' || echo '$(srcdir)/'`decif.c @am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libgstbcmdec_la-decif.Tpo $(DEPDIR)/libgstbcmdec_la-decif.Plo @AMDEP_TRUE@@am__fastdepCC_FALSE@ source='decif.c' object='libgstbcmdec_la-decif.lo' libtool=yes @AMDEPBACKSLASH@ @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libgstbcmdec_la_CFLAGS) $(CFLAGS) -c -o libgstbcmdec_la-decif.lo `test -f 'decif.c' || echo '$(srcdir)/'`decif.c libgstbcmdec_la-parse.lo: parse.c @am__fastdepCC_TRUE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libgstbcmdec_la_CFLAGS) $(CFLAGS) -MT libgstbcmdec_la-parse.lo -MD -MP -MF $(DEPDIR)/libgstbcmdec_la-parse.Tpo -c -o libgstbcmdec_la-parse.lo `test -f 'parse.c' || echo '$(srcdir)/'`parse.c @am__fastdepCC_TRUE@ $(am__mv) $(DEPDIR)/libgstbcmdec_la-parse.Tpo $(DEPDIR)/libgstbcmdec_la-parse.Plo @AMDEP_TRUE@@am__fastdepCC_FALSE@ source='parse.c' object='libgstbcmdec_la-parse.lo' libtool=yes @AMDEPBACKSLASH@ @AMDEP_TRUE@@am__fastdepCC_FALSE@ DEPDIR=$(DEPDIR) $(CCDEPMODE) $(depcomp) @AMDEPBACKSLASH@ @am__fastdepCC_FALSE@ $(LIBTOOL) --tag=CC $(AM_LIBTOOLFLAGS) $(LIBTOOLFLAGS) --mode=compile $(CC) $(DEFS) $(DEFAULT_INCLUDES) $(INCLUDES) $(AM_CPPFLAGS) $(CPPFLAGS) $(libgstbcmdec_la_CFLAGS) $(CFLAGS) -c -o libgstbcmdec_la-parse.lo `test -f 'parse.c' || echo '$(srcdir)/'`parse.c mostlyclean-libtool: -rm -f *.lo clean-libtool: -rm -rf .libs _libs ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES) list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ unique=`for i in $$list; do \ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ done | \ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \ END { if (nonempty) { for (i in files) print i; }; }'`; \ mkid -fID $$unique tags: TAGS TAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ $(TAGS_FILES) $(LISP) set x; \ here=`pwd`; \ list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ unique=`for i in $$list; do \ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ done | \ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \ END { if (nonempty) { for (i in files) print i; }; }'`; \ shift; \ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \ test -n "$$unique" || unique=$$empty_fix; \ if test $$# -gt 0; then \ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \ "$$@" $$unique; \ else \ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \ $$unique; \ fi; \ fi ctags: CTAGS CTAGS: $(HEADERS) $(SOURCES) $(TAGS_DEPENDENCIES) \ $(TAGS_FILES) $(LISP) list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ unique=`for i in $$list; do \ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ done | \ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \ END { if (nonempty) { for (i in files) print i; }; }'`; \ test -z "$(CTAGS_ARGS)$$unique" \ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \ $$unique GTAGS: here=`$(am__cd) $(top_builddir) && pwd` \ && $(am__cd) $(top_srcdir) \ && gtags -i $(GTAGS_ARGS) "$$here" distclean-tags: -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags distdir: $(DISTFILES) @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ list='$(DISTFILES)'; \ dist_files=`for file in $$list; do echo $$file; done | \ sed -e "s|^$$srcdirstrip/||;t" \ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \ case $$dist_files in \ */*) $(MKDIR_P) `echo "$$dist_files" | \ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \ sort -u` ;; \ esac; \ for file in $$dist_files; do \ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ if test -d $$d/$$file; then \ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \ if test -d "$(distdir)/$$file"; then \ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ fi; \ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ fi; \ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \ else \ test -f "$(distdir)/$$file" \ || cp -p $$d/$$file "$(distdir)/$$file" \ || exit 1; \ fi; \ done check-am: all-am check: check-am all-am: Makefile $(LTLIBRARIES) $(HEADERS) installdirs: for dir in "$(DESTDIR)$(plugindir)"; do \ test -z "$$dir" || $(MKDIR_P) "$$dir"; \ done install: install-am install-exec: install-exec-am install-data: install-data-am uninstall: uninstall-am install-am: all-am @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am installcheck: installcheck-am install-strip: $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ `test -z '$(STRIP)' || \ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install mostlyclean-generic: clean-generic: distclean-generic: -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES) maintainer-clean-generic: @echo "This command is intended for maintainers to use" @echo "it deletes files that may require special tools to rebuild." clean: clean-am clean-am: clean-generic clean-libtool clean-pluginLTLIBRARIES \ mostlyclean-am distclean: distclean-am -rm -rf ./$(DEPDIR) -rm -f Makefile distclean-am: clean-am distclean-compile distclean-generic \ distclean-tags dvi: dvi-am dvi-am: html: html-am html-am: info: info-am info-am: install-data-am: install-pluginLTLIBRARIES install-dvi: install-dvi-am install-dvi-am: install-exec-am: install-html: install-html-am install-html-am: install-info: install-info-am install-info-am: install-man: install-pdf: install-pdf-am install-pdf-am: install-ps: install-ps-am install-ps-am: installcheck-am: maintainer-clean: maintainer-clean-am -rm -rf ./$(DEPDIR) -rm -f Makefile maintainer-clean-am: distclean-am maintainer-clean-generic mostlyclean: mostlyclean-am mostlyclean-am: mostlyclean-compile mostlyclean-generic \ mostlyclean-libtool pdf: pdf-am pdf-am: ps: ps-am ps-am: uninstall-am: uninstall-pluginLTLIBRARIES .MAKE: install-am install-strip .PHONY: CTAGS GTAGS all all-am check check-am clean clean-generic \ clean-libtool clean-pluginLTLIBRARIES ctags distclean \ distclean-compile distclean-generic distclean-libtool \ distclean-tags distdir dvi dvi-am html html-am info info-am \ install install-am install-data install-data-am install-dvi \ install-dvi-am install-exec install-exec-am install-html \ install-html-am install-info install-info-am install-man \ install-pdf install-pdf-am install-pluginLTLIBRARIES \ install-ps install-ps-am install-strip installcheck \ installcheck-am installdirs maintainer-clean \ maintainer-clean-generic mostlyclean mostlyclean-compile \ mostlyclean-generic mostlyclean-libtool pdf pdf-am ps ps-am \ tags uninstall uninstall-am uninstall-pluginLTLIBRARIES # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/missing0000644000175000017500000002557711610313111023477 0ustar andresandres#! /bin/sh # Common stub for a few missing GNU programs while installing. scriptversion=2006-05-10.23 # Copyright (C) 1996, 1997, 1999, 2000, 2002, 2003, 2004, 2005, 2006 # Free Software Foundation, Inc. # Originally by Fran,cois Pinard , 1996. # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2, or (at your option) # any later version. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA # 02110-1301, USA. # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. if test $# -eq 0; then echo 1>&2 "Try \`$0 --help' for more information" exit 1 fi run=: sed_output='s/.* --output[ =]\([^ ]*\).*/\1/p' sed_minuso='s/.* -o \([^ ]*\).*/\1/p' # In the cases where this matters, `missing' is being run in the # srcdir already. if test -f configure.ac; then configure_ac=configure.ac else configure_ac=configure.in fi msg="missing on your system" case $1 in --run) # Try to run requested program, and just exit if it succeeds. run= shift "$@" && exit 0 # Exit code 63 means version mismatch. This often happens # when the user try to use an ancient version of a tool on # a file that requires a minimum version. In this case we # we should proceed has if the program had been absent, or # if --run hadn't been passed. if test $? = 63; then run=: msg="probably too old" fi ;; -h|--h|--he|--hel|--help) echo "\ $0 [OPTION]... PROGRAM [ARGUMENT]... Handle \`PROGRAM [ARGUMENT]...' for when PROGRAM is missing, or return an error status if there is no known handling for PROGRAM. Options: -h, --help display this help and exit -v, --version output version information and exit --run try to run the given command, and emulate it if it fails Supported PROGRAM values: aclocal touch file \`aclocal.m4' autoconf touch file \`configure' autoheader touch file \`config.h.in' autom4te touch the output file, or create a stub one automake touch all \`Makefile.in' files bison create \`y.tab.[ch]', if possible, from existing .[ch] flex create \`lex.yy.c', if possible, from existing .c help2man touch the output file lex create \`lex.yy.c', if possible, from existing .c makeinfo touch the output file tar try tar, gnutar, gtar, then tar without non-portable flags yacc create \`y.tab.[ch]', if possible, from existing .[ch] Send bug reports to ." exit $? ;; -v|--v|--ve|--ver|--vers|--versi|--versio|--version) echo "missing $scriptversion (GNU Automake)" exit $? ;; -*) echo 1>&2 "$0: Unknown \`$1' option" echo 1>&2 "Try \`$0 --help' for more information" exit 1 ;; esac # Now exit if we have it, but it failed. Also exit now if we # don't have it and --version was passed (most likely to detect # the program). case $1 in lex|yacc) # Not GNU programs, they don't have --version. ;; tar) if test -n "$run"; then echo 1>&2 "ERROR: \`tar' requires --run" exit 1 elif test "x$2" = "x--version" || test "x$2" = "x--help"; then exit 1 fi ;; *) if test -z "$run" && ($1 --version) > /dev/null 2>&1; then # We have it, but it failed. exit 1 elif test "x$2" = "x--version" || test "x$2" = "x--help"; then # Could not run --version or --help. This is probably someone # running `$TOOL --version' or `$TOOL --help' to check whether # $TOOL exists and not knowing $TOOL uses missing. exit 1 fi ;; esac # If it does not exist, or fails to run (possibly an outdated version), # try to emulate it. case $1 in aclocal*) echo 1>&2 "\ WARNING: \`$1' is $msg. You should only need it if you modified \`acinclude.m4' or \`${configure_ac}'. You might want to install the \`Automake' and \`Perl' packages. Grab them from any GNU archive site." touch aclocal.m4 ;; autoconf) echo 1>&2 "\ WARNING: \`$1' is $msg. You should only need it if you modified \`${configure_ac}'. You might want to install the \`Autoconf' and \`GNU m4' packages. Grab them from any GNU archive site." touch configure ;; autoheader) echo 1>&2 "\ WARNING: \`$1' is $msg. You should only need it if you modified \`acconfig.h' or \`${configure_ac}'. You might want to install the \`Autoconf' and \`GNU m4' packages. Grab them from any GNU archive site." files=`sed -n 's/^[ ]*A[CM]_CONFIG_HEADER(\([^)]*\)).*/\1/p' ${configure_ac}` test -z "$files" && files="config.h" touch_files= for f in $files; do case $f in *:*) touch_files="$touch_files "`echo "$f" | sed -e 's/^[^:]*://' -e 's/:.*//'`;; *) touch_files="$touch_files $f.in";; esac done touch $touch_files ;; automake*) echo 1>&2 "\ WARNING: \`$1' is $msg. You should only need it if you modified \`Makefile.am', \`acinclude.m4' or \`${configure_ac}'. You might want to install the \`Automake' and \`Perl' packages. Grab them from any GNU archive site." find . -type f -name Makefile.am -print | sed 's/\.am$/.in/' | while read f; do touch "$f"; done ;; autom4te) echo 1>&2 "\ WARNING: \`$1' is needed, but is $msg. You might have modified some files without having the proper tools for further handling them. You can get \`$1' as part of \`Autoconf' from any GNU archive site." file=`echo "$*" | sed -n "$sed_output"` test -z "$file" && file=`echo "$*" | sed -n "$sed_minuso"` if test -f "$file"; then touch $file else test -z "$file" || exec >$file echo "#! /bin/sh" echo "# Created by GNU Automake missing as a replacement of" echo "# $ $@" echo "exit 0" chmod +x $file exit 1 fi ;; bison|yacc) echo 1>&2 "\ WARNING: \`$1' $msg. You should only need it if you modified a \`.y' file. You may need the \`Bison' package in order for those modifications to take effect. You can get \`Bison' from any GNU archive site." rm -f y.tab.c y.tab.h if test $# -ne 1; then eval LASTARG="\${$#}" case $LASTARG in *.y) SRCFILE=`echo "$LASTARG" | sed 's/y$/c/'` if test -f "$SRCFILE"; then cp "$SRCFILE" y.tab.c fi SRCFILE=`echo "$LASTARG" | sed 's/y$/h/'` if test -f "$SRCFILE"; then cp "$SRCFILE" y.tab.h fi ;; esac fi if test ! -f y.tab.h; then echo >y.tab.h fi if test ! -f y.tab.c; then echo 'main() { return 0; }' >y.tab.c fi ;; lex|flex) echo 1>&2 "\ WARNING: \`$1' is $msg. You should only need it if you modified a \`.l' file. You may need the \`Flex' package in order for those modifications to take effect. You can get \`Flex' from any GNU archive site." rm -f lex.yy.c if test $# -ne 1; then eval LASTARG="\${$#}" case $LASTARG in *.l) SRCFILE=`echo "$LASTARG" | sed 's/l$/c/'` if test -f "$SRCFILE"; then cp "$SRCFILE" lex.yy.c fi ;; esac fi if test ! -f lex.yy.c; then echo 'main() { return 0; }' >lex.yy.c fi ;; help2man) echo 1>&2 "\ WARNING: \`$1' is $msg. You should only need it if you modified a dependency of a manual page. You may need the \`Help2man' package in order for those modifications to take effect. You can get \`Help2man' from any GNU archive site." file=`echo "$*" | sed -n "$sed_output"` test -z "$file" && file=`echo "$*" | sed -n "$sed_minuso"` if test -f "$file"; then touch $file else test -z "$file" || exec >$file echo ".ab help2man is required to generate this page" exit 1 fi ;; makeinfo) echo 1>&2 "\ WARNING: \`$1' is $msg. You should only need it if you modified a \`.texi' or \`.texinfo' file, or any other file indirectly affecting the aspect of the manual. The spurious call might also be the consequence of using a buggy \`make' (AIX, DU, IRIX). You might want to install the \`Texinfo' package or the \`GNU make' package. Grab either from any GNU archive site." # The file to touch is that specified with -o ... file=`echo "$*" | sed -n "$sed_output"` test -z "$file" && file=`echo "$*" | sed -n "$sed_minuso"` if test -z "$file"; then # ... or it is the one specified with @setfilename ... infile=`echo "$*" | sed 's/.* \([^ ]*\) *$/\1/'` file=`sed -n ' /^@setfilename/{ s/.* \([^ ]*\) *$/\1/ p q }' $infile` # ... or it is derived from the source name (dir/f.texi becomes f.info) test -z "$file" && file=`echo "$infile" | sed 's,.*/,,;s,.[^.]*$,,'`.info fi # If the file does not exist, the user really needs makeinfo; # let's fail without touching anything. test -f $file || exit 1 touch $file ;; tar) shift # We have already tried tar in the generic part. # Look for gnutar/gtar before invocation to avoid ugly error # messages. if (gnutar --version > /dev/null 2>&1); then gnutar "$@" && exit 0 fi if (gtar --version > /dev/null 2>&1); then gtar "$@" && exit 0 fi firstarg="$1" if shift; then case $firstarg in *o*) firstarg=`echo "$firstarg" | sed s/o//` tar "$firstarg" "$@" && exit 0 ;; esac case $firstarg in *h*) firstarg=`echo "$firstarg" | sed s/h//` tar "$firstarg" "$@" && exit 0 ;; esac fi echo 1>&2 "\ WARNING: I can't seem to be able to run \`tar' with the given arguments. You may want to install GNU tar or Free paxutils, or check the command line arguments." exit 1 ;; *) echo 1>&2 "\ WARNING: \`$1' is needed, and is $msg. You might have modified some files without having the proper tools for further handling them. Check the \`README' file, it often tells you about the needed prerequisites for installing this package. You may also peek at any GNU archive site, in case some other package would contain this missing \`$1' program." exit 1 ;; esac exit 0 # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "scriptversion=" # time-stamp-format: "%:y-%02m-%02d.%02H" # time-stamp-end: "$" # End: crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/depcomp0000644000175000017500000004271311610313111023444 0ustar andresandres#! /bin/sh # depcomp - compile a program generating dependencies as side-effects scriptversion=2007-03-29.01 # Copyright (C) 1999, 2000, 2003, 2004, 2005, 2006, 2007 Free Software # Foundation, Inc. # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2, or (at your option) # any later version. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA # 02110-1301, USA. # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Originally written by Alexandre Oliva . case $1 in '') echo "$0: No command. Try \`$0 --help' for more information." 1>&2 exit 1; ;; -h | --h*) cat <<\EOF Usage: depcomp [--help] [--version] PROGRAM [ARGS] Run PROGRAMS ARGS to compile a file, generating dependencies as side-effects. Environment variables: depmode Dependency tracking mode. source Source file read by `PROGRAMS ARGS'. object Object file output by `PROGRAMS ARGS'. DEPDIR directory where to store dependencies. depfile Dependency file to output. tmpdepfile Temporary file to use when outputing dependencies. libtool Whether libtool is used (yes/no). Report bugs to . EOF exit $? ;; -v | --v*) echo "depcomp $scriptversion" exit $? ;; esac if test -z "$depmode" || test -z "$source" || test -z "$object"; then echo "depcomp: Variables source, object and depmode must be set" 1>&2 exit 1 fi # Dependencies for sub/bar.o or sub/bar.obj go into sub/.deps/bar.Po. depfile=${depfile-`echo "$object" | sed 's|[^\\/]*$|'${DEPDIR-.deps}'/&|;s|\.\([^.]*\)$|.P\1|;s|Pobj$|Po|'`} tmpdepfile=${tmpdepfile-`echo "$depfile" | sed 's/\.\([^.]*\)$/.T\1/'`} rm -f "$tmpdepfile" # Some modes work just like other modes, but use different flags. We # parameterize here, but still list the modes in the big case below, # to make depend.m4 easier to write. Note that we *cannot* use a case # here, because this file can only contain one case statement. if test "$depmode" = hp; then # HP compiler uses -M and no extra arg. gccflag=-M depmode=gcc fi if test "$depmode" = dashXmstdout; then # This is just like dashmstdout with a different argument. dashmflag=-xM depmode=dashmstdout fi case "$depmode" in gcc3) ## gcc 3 implements dependency tracking that does exactly what ## we want. Yay! Note: for some reason libtool 1.4 doesn't like ## it if -MD -MP comes after the -MF stuff. Hmm. ## Unfortunately, FreeBSD c89 acceptance of flags depends upon ## the command line argument order; so add the flags where they ## appear in depend2.am. Note that the slowdown incurred here ## affects only configure: in makefiles, %FASTDEP% shortcuts this. for arg do case $arg in -c) set fnord "$@" -MT "$object" -MD -MP -MF "$tmpdepfile" "$arg" ;; *) set fnord "$@" "$arg" ;; esac shift # fnord shift # $arg done "$@" stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile" exit $stat fi mv "$tmpdepfile" "$depfile" ;; gcc) ## There are various ways to get dependency output from gcc. Here's ## why we pick this rather obscure method: ## - Don't want to use -MD because we'd like the dependencies to end ## up in a subdir. Having to rename by hand is ugly. ## (We might end up doing this anyway to support other compilers.) ## - The DEPENDENCIES_OUTPUT environment variable makes gcc act like ## -MM, not -M (despite what the docs say). ## - Using -M directly means running the compiler twice (even worse ## than renaming). if test -z "$gccflag"; then gccflag=-MD, fi "$@" -Wp,"$gccflag$tmpdepfile" stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile" exit $stat fi rm -f "$depfile" echo "$object : \\" > "$depfile" alpha=ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz ## The second -e expression handles DOS-style file names with drive letters. sed -e 's/^[^:]*: / /' \ -e 's/^['$alpha']:\/[^:]*: / /' < "$tmpdepfile" >> "$depfile" ## This next piece of magic avoids the `deleted header file' problem. ## The problem is that when a header file which appears in a .P file ## is deleted, the dependency causes make to die (because there is ## typically no way to rebuild the header). We avoid this by adding ## dummy dependencies for each header file. Too bad gcc doesn't do ## this for us directly. tr ' ' ' ' < "$tmpdepfile" | ## Some versions of gcc put a space before the `:'. On the theory ## that the space means something, we add a space to the output as ## well. ## Some versions of the HPUX 10.20 sed can't process this invocation ## correctly. Breaking it into two sed invocations is a workaround. sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile" rm -f "$tmpdepfile" ;; hp) # This case exists only to let depend.m4 do its work. It works by # looking at the text of this script. This case will never be run, # since it is checked for above. exit 1 ;; sgi) if test "$libtool" = yes; then "$@" "-Wp,-MDupdate,$tmpdepfile" else "$@" -MDupdate "$tmpdepfile" fi stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile" exit $stat fi rm -f "$depfile" if test -f "$tmpdepfile"; then # yes, the sourcefile depend on other files echo "$object : \\" > "$depfile" # Clip off the initial element (the dependent). Don't try to be # clever and replace this with sed code, as IRIX sed won't handle # lines with more than a fixed number of characters (4096 in # IRIX 6.2 sed, 8192 in IRIX 6.5). We also remove comment lines; # the IRIX cc adds comments like `#:fec' to the end of the # dependency line. tr ' ' ' ' < "$tmpdepfile" \ | sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' | \ tr ' ' ' ' >> $depfile echo >> $depfile # The second pass generates a dummy entry for each header file. tr ' ' ' ' < "$tmpdepfile" \ | sed -e 's/^.*\.o://' -e 's/#.*$//' -e '/^$/ d' -e 's/$/:/' \ >> $depfile else # The sourcefile does not contain any dependencies, so just # store a dummy comment line, to avoid errors with the Makefile # "include basename.Plo" scheme. echo "#dummy" > "$depfile" fi rm -f "$tmpdepfile" ;; aix) # The C for AIX Compiler uses -M and outputs the dependencies # in a .u file. In older versions, this file always lives in the # current directory. Also, the AIX compiler puts `$object:' at the # start of each line; $object doesn't have directory information. # Version 6 uses the directory in both cases. dir=`echo "$object" | sed -e 's|/[^/]*$|/|'` test "x$dir" = "x$object" && dir= base=`echo "$object" | sed -e 's|^.*/||' -e 's/\.o$//' -e 's/\.lo$//'` if test "$libtool" = yes; then tmpdepfile1=$dir$base.u tmpdepfile2=$base.u tmpdepfile3=$dir.libs/$base.u "$@" -Wc,-M else tmpdepfile1=$dir$base.u tmpdepfile2=$dir$base.u tmpdepfile3=$dir$base.u "$@" -M fi stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" exit $stat fi for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" do test -f "$tmpdepfile" && break done if test -f "$tmpdepfile"; then # Each line is of the form `foo.o: dependent.h'. # Do two passes, one to just change these to # `$object: dependent.h' and one to simply `dependent.h:'. sed -e "s,^.*\.[a-z]*:,$object:," < "$tmpdepfile" > "$depfile" # That's a tab and a space in the []. sed -e 's,^.*\.[a-z]*:[ ]*,,' -e 's,$,:,' < "$tmpdepfile" >> "$depfile" else # The sourcefile does not contain any dependencies, so just # store a dummy comment line, to avoid errors with the Makefile # "include basename.Plo" scheme. echo "#dummy" > "$depfile" fi rm -f "$tmpdepfile" ;; icc) # Intel's C compiler understands `-MD -MF file'. However on # icc -MD -MF foo.d -c -o sub/foo.o sub/foo.c # ICC 7.0 will fill foo.d with something like # foo.o: sub/foo.c # foo.o: sub/foo.h # which is wrong. We want: # sub/foo.o: sub/foo.c # sub/foo.o: sub/foo.h # sub/foo.c: # sub/foo.h: # ICC 7.1 will output # foo.o: sub/foo.c sub/foo.h # and will wrap long lines using \ : # foo.o: sub/foo.c ... \ # sub/foo.h ... \ # ... "$@" -MD -MF "$tmpdepfile" stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile" exit $stat fi rm -f "$depfile" # Each line is of the form `foo.o: dependent.h', # or `foo.o: dep1.h dep2.h \', or ` dep3.h dep4.h \'. # Do two passes, one to just change these to # `$object: dependent.h' and one to simply `dependent.h:'. sed "s,^[^:]*:,$object :," < "$tmpdepfile" > "$depfile" # Some versions of the HPUX 10.20 sed can't process this invocation # correctly. Breaking it into two sed invocations is a workaround. sed 's,^[^:]*: \(.*\)$,\1,;s/^\\$//;/^$/d;/:$/d' < "$tmpdepfile" | sed -e 's/$/ :/' >> "$depfile" rm -f "$tmpdepfile" ;; hp2) # The "hp" stanza above does not work with aCC (C++) and HP's ia64 # compilers, which have integrated preprocessors. The correct option # to use with these is +Maked; it writes dependencies to a file named # 'foo.d', which lands next to the object file, wherever that # happens to be. # Much of this is similar to the tru64 case; see comments there. dir=`echo "$object" | sed -e 's|/[^/]*$|/|'` test "x$dir" = "x$object" && dir= base=`echo "$object" | sed -e 's|^.*/||' -e 's/\.o$//' -e 's/\.lo$//'` if test "$libtool" = yes; then tmpdepfile1=$dir$base.d tmpdepfile2=$dir.libs/$base.d "$@" -Wc,+Maked else tmpdepfile1=$dir$base.d tmpdepfile2=$dir$base.d "$@" +Maked fi stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile1" "$tmpdepfile2" exit $stat fi for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" do test -f "$tmpdepfile" && break done if test -f "$tmpdepfile"; then sed -e "s,^.*\.[a-z]*:,$object:," "$tmpdepfile" > "$depfile" # Add `dependent.h:' lines. sed -ne '2,${; s/^ *//; s/ \\*$//; s/$/:/; p;}' "$tmpdepfile" >> "$depfile" else echo "#dummy" > "$depfile" fi rm -f "$tmpdepfile" "$tmpdepfile2" ;; tru64) # The Tru64 compiler uses -MD to generate dependencies as a side # effect. `cc -MD -o foo.o ...' puts the dependencies into `foo.o.d'. # At least on Alpha/Redhat 6.1, Compaq CCC V6.2-504 seems to put # dependencies in `foo.d' instead, so we check for that too. # Subdirectories are respected. dir=`echo "$object" | sed -e 's|/[^/]*$|/|'` test "x$dir" = "x$object" && dir= base=`echo "$object" | sed -e 's|^.*/||' -e 's/\.o$//' -e 's/\.lo$//'` if test "$libtool" = yes; then # With Tru64 cc, shared objects can also be used to make a # static library. This mechanism is used in libtool 1.4 series to # handle both shared and static libraries in a single compilation. # With libtool 1.4, dependencies were output in $dir.libs/$base.lo.d. # # With libtool 1.5 this exception was removed, and libtool now # generates 2 separate objects for the 2 libraries. These two # compilations output dependencies in $dir.libs/$base.o.d and # in $dir$base.o.d. We have to check for both files, because # one of the two compilations can be disabled. We should prefer # $dir$base.o.d over $dir.libs/$base.o.d because the latter is # automatically cleaned when .libs/ is deleted, while ignoring # the former would cause a distcleancheck panic. tmpdepfile1=$dir.libs/$base.lo.d # libtool 1.4 tmpdepfile2=$dir$base.o.d # libtool 1.5 tmpdepfile3=$dir.libs/$base.o.d # libtool 1.5 tmpdepfile4=$dir.libs/$base.d # Compaq CCC V6.2-504 "$@" -Wc,-MD else tmpdepfile1=$dir$base.o.d tmpdepfile2=$dir$base.d tmpdepfile3=$dir$base.d tmpdepfile4=$dir$base.d "$@" -MD fi stat=$? if test $stat -eq 0; then : else rm -f "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" "$tmpdepfile4" exit $stat fi for tmpdepfile in "$tmpdepfile1" "$tmpdepfile2" "$tmpdepfile3" "$tmpdepfile4" do test -f "$tmpdepfile" && break done if test -f "$tmpdepfile"; then sed -e "s,^.*\.[a-z]*:,$object:," < "$tmpdepfile" > "$depfile" # That's a tab and a space in the []. sed -e 's,^.*\.[a-z]*:[ ]*,,' -e 's,$,:,' < "$tmpdepfile" >> "$depfile" else echo "#dummy" > "$depfile" fi rm -f "$tmpdepfile" ;; #nosideeffect) # This comment above is used by automake to tell side-effect # dependency tracking mechanisms from slower ones. dashmstdout) # Important note: in order to support this mode, a compiler *must* # always write the preprocessed file to stdout, regardless of -o. "$@" || exit $? # Remove the call to Libtool. if test "$libtool" = yes; then while test $1 != '--mode=compile'; do shift done shift fi # Remove `-o $object'. IFS=" " for arg do case $arg in -o) shift ;; $object) shift ;; *) set fnord "$@" "$arg" shift # fnord shift # $arg ;; esac done test -z "$dashmflag" && dashmflag=-M # Require at least two characters before searching for `:' # in the target name. This is to cope with DOS-style filenames: # a dependency such as `c:/foo/bar' could be seen as target `c' otherwise. "$@" $dashmflag | sed 's:^[ ]*[^: ][^:][^:]*\:[ ]*:'"$object"'\: :' > "$tmpdepfile" rm -f "$depfile" cat < "$tmpdepfile" > "$depfile" tr ' ' ' ' < "$tmpdepfile" | \ ## Some versions of the HPUX 10.20 sed can't process this invocation ## correctly. Breaking it into two sed invocations is a workaround. sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile" rm -f "$tmpdepfile" ;; dashXmstdout) # This case only exists to satisfy depend.m4. It is never actually # run, as this mode is specially recognized in the preamble. exit 1 ;; makedepend) "$@" || exit $? # Remove any Libtool call if test "$libtool" = yes; then while test $1 != '--mode=compile'; do shift done shift fi # X makedepend shift cleared=no for arg in "$@"; do case $cleared in no) set ""; shift cleared=yes ;; esac case "$arg" in -D*|-I*) set fnord "$@" "$arg"; shift ;; # Strip any option that makedepend may not understand. Remove # the object too, otherwise makedepend will parse it as a source file. -*|$object) ;; *) set fnord "$@" "$arg"; shift ;; esac done obj_suffix="`echo $object | sed 's/^.*\././'`" touch "$tmpdepfile" ${MAKEDEPEND-makedepend} -o"$obj_suffix" -f"$tmpdepfile" "$@" rm -f "$depfile" cat < "$tmpdepfile" > "$depfile" sed '1,2d' "$tmpdepfile" | tr ' ' ' ' | \ ## Some versions of the HPUX 10.20 sed can't process this invocation ## correctly. Breaking it into two sed invocations is a workaround. sed -e 's/^\\$//' -e '/^$/d' -e '/:$/d' | sed -e 's/$/ :/' >> "$depfile" rm -f "$tmpdepfile" "$tmpdepfile".bak ;; cpp) # Important note: in order to support this mode, a compiler *must* # always write the preprocessed file to stdout. "$@" || exit $? # Remove the call to Libtool. if test "$libtool" = yes; then while test $1 != '--mode=compile'; do shift done shift fi # Remove `-o $object'. IFS=" " for arg do case $arg in -o) shift ;; $object) shift ;; *) set fnord "$@" "$arg" shift # fnord shift # $arg ;; esac done "$@" -E | sed -n -e '/^# [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' \ -e '/^#line [0-9][0-9]* "\([^"]*\)".*/ s:: \1 \\:p' | sed '$ s: \\$::' > "$tmpdepfile" rm -f "$depfile" echo "$object : \\" > "$depfile" cat < "$tmpdepfile" >> "$depfile" sed < "$tmpdepfile" '/^$/d;s/^ //;s/ \\$//;s/$/ :/' >> "$depfile" rm -f "$tmpdepfile" ;; msvisualcpp) # Important note: in order to support this mode, a compiler *must* # always write the preprocessed file to stdout, regardless of -o, # because we must use -o when running libtool. "$@" || exit $? IFS=" " for arg do case "$arg" in "-Gm"|"/Gm"|"-Gi"|"/Gi"|"-ZI"|"/ZI") set fnord "$@" shift shift ;; *) set fnord "$@" "$arg" shift shift ;; esac done "$@" -E | sed -n '/^#line [0-9][0-9]* "\([^"]*\)"/ s::echo "`cygpath -u \\"\1\\"`":p' | sort | uniq > "$tmpdepfile" rm -f "$depfile" echo "$object : \\" > "$depfile" . "$tmpdepfile" | sed 's% %\\ %g' | sed -n '/^\(.*\)$/ s:: \1 \\:p' >> "$depfile" echo " " >> "$depfile" . "$tmpdepfile" | sed 's% %\\ %g' | sed -n '/^\(.*\)$/ s::\1\::p' >> "$depfile" rm -f "$tmpdepfile" ;; none) exec "$@" ;; *) echo "Unknown depmode $depmode" 1>&2 exit 1 ;; esac exit 0 # Local Variables: # mode: shell-script # sh-indentation: 2 # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "scriptversion=" # time-stamp-format: "%:y-%02m-%02d.%02H" # time-stamp-end: "$" # End: crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/configure.ac0000644000175000017500000001017011610313111024350 0ustar andresandresAC_INIT dnl versions of gstreamer and plugins-base GST_MAJORMINOR=0.10 GST_REQUIRED=0.10.0 GSTPB_REQUIRED=0.10.0 dnl fill in your package name and version here dnl the fourth (nano) number should be 0 for a release, 1 for CVS, dnl and 2... for a prerelease dnl when going to/from release please set the nano correctly ! dnl releases only do Wall, cvs and prerelease does Werror too AS_VERSION(gst-bcmdec, GST_PLUGIN_VERSION, 0, 10, 40, 0, GST_PLUGIN_CVS="no", GST_PLUGIN_CVS="yes") dnl AM_MAINTAINER_MODE provides the option to enable maintainer mode AM_MAINTAINER_MODE AM_INIT_AUTOMAKE($PACKAGE, $VERSION) AC_PREFIX_DEFAULT(/usr) dnl make aclocal work in maintainer mode AC_SUBST(ACLOCAL_AMFLAGS, "-I m4") AM_CONFIG_HEADER(config.h) dnl check for tools AC_PROG_CC AC_PROG_LIBTOOL dnl decide on error flags AS_COMPILER_FLAG(-Wall, GST_WALL="yes", GST_WALL="no") if test "x$GST_WALL" = "xyes"; then GST_ERROR="$GST_ERROR -Wall" if test "x$GST_PLUGIN_CVS" = "xyes"; then AS_COMPILER_FLAG(-Werror,GST_ERROR="$GST_ERROR -Werror",GST_ERROR="$GST_ERROR") fi fi dnl Check for pkgconfig first AC_CHECK_PROG(HAVE_PKGCONFIG, pkg-config, yes, no) dnl Give error and exit if we don't have pkgconfig if test "x$HAVE_PKGCONFIG" = "xno"; then AC_MSG_ERROR(you need to have pkgconfig installed !) fi dnl Now we're ready to ask for gstreamer libs and cflags dnl And we can also ask for the right version of gstreamer PKG_CHECK_MODULES(GST, \ gstreamer-$GST_MAJORMINOR >= $GST_REQUIRED gstreamer-video-0.10, HAVE_GST=yes,HAVE_GST=no) dnl Give error and exit if we don't have gstreamer if test "x$HAVE_GST" = "xno"; then AC_MSG_ERROR(you need gstreamer development packages installed !) fi dnl append GST_ERROR cflags to GST_CFLAGS GST_CFLAGS="$GST_CFLAGS $GST_ERROR" dnl make GST_CFLAGS and GST_LIBS available AC_SUBST(GST_CFLAGS) AC_SUBST(GST_LIBS) dnl make GST_MAJORMINOR available in Makefile.am AC_SUBST(GST_MAJORMINOR) dnl If we need them, we can also use the base class libraries PKG_CHECK_MODULES(GST_BASE, gstreamer-base-$GST_MAJORMINOR >= $GST_REQUIRED, HAVE_GST_BASE=yes, HAVE_GST_BASE=no) dnl Give a warning if we don't have gstreamer libs dnl you can turn this into an error if you need them if test "x$HAVE_GST_BASE" = "xno"; then AC_MSG_NOTICE(no GStreamer base class libraries found (gstreamer-base-$GST_MAJORMINOR)) fi dnl make _CFLAGS and _LIBS available AC_SUBST(GST_BASE_CFLAGS) AC_SUBST(GST_BASE_LIBS) dnl If we need them, we can also use the gstreamer-plugins-base libraries PKG_CHECK_MODULES(GSTPB_BASE, gstreamer-plugins-base-$GST_MAJORMINOR >= $GSTPB_REQUIRED, HAVE_GSTPB_BASE=yes, HAVE_GSTPB_BASE=no) dnl Give a warning if we don't have gstreamer libs dnl you can turn this into an error if you need them if test "x$HAVE_GSTPB_BASE" = "xno"; then AC_MSG_NOTICE(no GStreamer Plugins Base libraries found (gstreamer-plugins-base-$GST_MAJORMINOR)) fi dnl make _CFLAGS and _LIBS available AC_SUBST(GSTPB_BASE_CFLAGS) AC_SUBST(GSTPB_BASE_LIBS) dnl If we need them, we can also use the gstreamer-controller libraries PKG_CHECK_MODULES(GSTCTRL, gstreamer-controller-$GST_MAJORMINOR >= $GSTPB_REQUIRED, HAVE_GSTCTRL=yes, HAVE_GSTCTRL=no) dnl Give a warning if we don't have gstreamer-controller dnl you can turn this into an error if you need them if test "x$HAVE_GSTCTRL" = "xno"; then AC_MSG_NOTICE(no GStreamer Controller libraries found (gstreamer-controller-$GST_MAJORMINOR)) fi dnl make _CFLAGS and _LIBS available AC_SUBST(GSTCTRL_CFLAGS) AC_SUBST(GSTCTRL_LIBS) dnl set the plugindir where plugins should be installed if test "x${prefix}" = "x$HOME"; then plugindir="$HOME/.gstreamer-$GST_MAJORMINOR/plugins" else plugindir="\$(libdir)/gstreamer-$GST_MAJORMINOR" fi AC_SUBST(plugindir) dnl set proper LDFLAGS for plugins GST_PLUGIN_LDFLAGS='-module -avoid-version -export-symbols-regex [_]*\(gst_\|Gst\|GST_\).*' AC_SUBST(GST_PLUGIN_LDFLAGS) AC_OUTPUT(Makefile m4/Makefile src/Makefile) crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/m4/0000755000175000017500000000000011610313122022405 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/m4/as-compiler-flag.m40000644000175000017500000000066311610313111025774 0ustar andresandresdnl as-compiler-flag.m4 0.0.1 dnl autostars m4 macro for detection of compiler flags dnl dnl ds@schleef.org AC_DEFUN([AS_COMPILER_FLAG], [ AC_MSG_CHECKING([to see if compiler understands $1]) save_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS $1" AC_TRY_COMPILE([ ], [], [flag_ok=yes], [flag_ok=no]) CFLAGS="$save_CFLAGS" if test "X$flag_ok" = Xyes ; then $2 true else $3 true fi AC_MSG_RESULT([$flag_ok]) ]) crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/m4/as-version.m40000644000175000017500000000362211610313111024736 0ustar andresandresdnl as-version.m4 0.1.0 dnl autostars m4 macro for versioning dnl Thomas Vander Stichele dnl $Id: as-version.m4,v 1.2 2004-09-17 22:18:03 leroutier Exp $ dnl AS_VERSION(PACKAGE, PREFIX, MAJOR, MINOR, MICRO, NANO, dnl ACTION-IF-NO-NANO, [ACTION-IF-NANO]) dnl example dnl AS_VERSION(gstreamer, GST_VERSION, 0, 3, 2,) dnl for a 0.3.2 release version dnl this macro dnl - defines [$PREFIX]_MAJOR, MINOR and MICRO dnl - if NANO is empty, then we're in release mode, else in cvs/dev mode dnl - defines [$PREFIX], VERSION, and [$PREFIX]_RELEASE dnl - executes the relevant action dnl - AC_SUBST's PACKAGE, VERSION, [$PREFIX] and [$PREFIX]_RELEASE dnl as well as the little ones dnl - doesn't call AM_INIT_AUTOMAKE anymore because it prevents dnl maintainer mode from running ok dnl dnl don't forget to put #undef [$2] and [$2]_RELEASE in acconfig.h dnl if you use acconfig.h AC_DEFUN([AS_VERSION], [ PACKAGE=[$1] [$2]_MAJOR=[$3] [$2]_MINOR=[$4] [$2]_MICRO=[$5] NANO=[$6] [$2]_NANO=$NANO if test "x$NANO" = "x" || test "x$NANO" = "x0"; then AC_MSG_NOTICE(configuring [$1] for release) VERSION=[$3].[$4].[$5] [$2]_RELEASE=1 dnl execute action ifelse([$7], , :, [$7]) else AC_MSG_NOTICE(configuring [$1] for development with nano $NANO) VERSION=[$3].[$4].[$5].$NANO [$2]_RELEASE=0.`date +%Y%m%d.%H%M%S` dnl execute action ifelse([$8], , :, [$8]) fi [$2]=$VERSION AC_DEFINE_UNQUOTED([$2], "$[$2]", [Define the version]) AC_SUBST([$2]) AC_DEFINE_UNQUOTED([$2]_RELEASE, "$[$2]_RELEASE", [Define the release version]) AC_SUBST([$2]_RELEASE) AC_SUBST([$2]_MAJOR) AC_SUBST([$2]_MINOR) AC_SUBST([$2]_MICRO) AC_SUBST([$2]_NANO) AC_DEFINE_UNQUOTED(PACKAGE, "$PACKAGE", [Define the package name]) AC_SUBST(PACKAGE) AC_DEFINE_UNQUOTED(VERSION, "$VERSION", [Define the version]) AC_SUBST(VERSION) ]) crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/m4/Makefile.am0000644000175000017500000000005711610313111024441 0ustar andresandresEXTRA_DIST = as-version.m4 as-compiler-flag.m4 crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/m4/Makefile.in0000644000175000017500000002415211610313116024461 0ustar andresandres# Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : PRE_INSTALL = : POST_INSTALL = : NORMAL_UNINSTALL = : PRE_UNINSTALL = : POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ subdir = m4 DIST_COMMON = $(srcdir)/Makefile.am $(srcdir)/Makefile.in ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/m4/as-compiler-flag.m4 \ $(top_srcdir)/m4/as-version.m4 $(top_srcdir)/configure.ac am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) mkinstalldirs = $(install_sh) -d CONFIG_HEADER = $(top_builddir)/config.h CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = SOURCES = DIST_SOURCES = DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) ACLOCAL = @ACLOCAL@ ACLOCAL_AMFLAGS = @ACLOCAL_AMFLAGS@ AMTAR = @AMTAR@ AR = @AR@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ CPP = @CPP@ CPPFLAGS = @CPPFLAGS@ CYGPATH_W = @CYGPATH_W@ DEFS = @DEFS@ DEPDIR = @DEPDIR@ DLLTOOL = @DLLTOOL@ DSYMUTIL = @DSYMUTIL@ DUMPBIN = @DUMPBIN@ ECHO_C = @ECHO_C@ ECHO_N = @ECHO_N@ ECHO_T = @ECHO_T@ EGREP = @EGREP@ EXEEXT = @EXEEXT@ FGREP = @FGREP@ GREP = @GREP@ GSTCTRL_CFLAGS = @GSTCTRL_CFLAGS@ GSTCTRL_LIBS = @GSTCTRL_LIBS@ GSTPB_BASE_CFLAGS = @GSTPB_BASE_CFLAGS@ GSTPB_BASE_LIBS = @GSTPB_BASE_LIBS@ GST_BASE_CFLAGS = @GST_BASE_CFLAGS@ GST_BASE_LIBS = @GST_BASE_LIBS@ GST_CFLAGS = @GST_CFLAGS@ GST_LIBS = @GST_LIBS@ GST_MAJORMINOR = @GST_MAJORMINOR@ GST_PLUGIN_LDFLAGS = @GST_PLUGIN_LDFLAGS@ GST_PLUGIN_VERSION = @GST_PLUGIN_VERSION@ GST_PLUGIN_VERSION_MAJOR = @GST_PLUGIN_VERSION_MAJOR@ GST_PLUGIN_VERSION_MICRO = @GST_PLUGIN_VERSION_MICRO@ GST_PLUGIN_VERSION_MINOR = @GST_PLUGIN_VERSION_MINOR@ GST_PLUGIN_VERSION_NANO = @GST_PLUGIN_VERSION_NANO@ GST_PLUGIN_VERSION_RELEASE = @GST_PLUGIN_VERSION_RELEASE@ HAVE_PKGCONFIG = @HAVE_PKGCONFIG@ INSTALL = @INSTALL@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_SCRIPT = @INSTALL_SCRIPT@ INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ LD = @LD@ LDFLAGS = @LDFLAGS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIPO = @LIPO@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAKEINFO = @MAKEINFO@ MANIFEST_TOOL = @MANIFEST_TOOL@ MKDIR_P = @MKDIR_P@ NM = @NM@ NMEDIT = @NMEDIT@ OBJDUMP = @OBJDUMP@ OBJEXT = @OBJEXT@ OTOOL = @OTOOL@ OTOOL64 = @OTOOL64@ PACKAGE = @PACKAGE@ PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ PACKAGE_NAME = @PACKAGE_NAME@ PACKAGE_STRING = @PACKAGE_STRING@ PACKAGE_TARNAME = @PACKAGE_TARNAME@ PACKAGE_URL = @PACKAGE_URL@ PACKAGE_VERSION = @PACKAGE_VERSION@ PATH_SEPARATOR = @PATH_SEPARATOR@ PKG_CONFIG = @PKG_CONFIG@ PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ abs_builddir = @abs_builddir@ abs_srcdir = @abs_srcdir@ abs_top_builddir = @abs_top_builddir@ abs_top_srcdir = @abs_top_srcdir@ ac_ct_AR = @ac_ct_AR@ ac_ct_CC = @ac_ct_CC@ ac_ct_DUMPBIN = @ac_ct_DUMPBIN@ am__include = @am__include@ am__leading_dot = @am__leading_dot@ am__quote = @am__quote@ am__tar = @am__tar@ am__untar = @am__untar@ bindir = @bindir@ build = @build@ build_alias = @build_alias@ build_cpu = @build_cpu@ build_os = @build_os@ build_vendor = @build_vendor@ builddir = @builddir@ datadir = @datadir@ datarootdir = @datarootdir@ docdir = @docdir@ dvidir = @dvidir@ exec_prefix = @exec_prefix@ host = @host@ host_alias = @host_alias@ host_cpu = @host_cpu@ host_os = @host_os@ host_vendor = @host_vendor@ htmldir = @htmldir@ includedir = @includedir@ infodir = @infodir@ install_sh = @install_sh@ libdir = @libdir@ libexecdir = @libexecdir@ localedir = @localedir@ localstatedir = @localstatedir@ mandir = @mandir@ mkdir_p = @mkdir_p@ oldincludedir = @oldincludedir@ pdfdir = @pdfdir@ plugindir = @plugindir@ prefix = @prefix@ program_transform_name = @program_transform_name@ psdir = @psdir@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ srcdir = @srcdir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ EXTRA_DIST = as-version.m4 as-compiler-flag.m4 all: all-am .SUFFIXES: $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ ( cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh ) \ && { if test -f $@; then exit 0; else break; fi; }; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --gnu m4/Makefile'; \ $(am__cd) $(top_srcdir) && \ $(AUTOMAKE) --gnu m4/Makefile .PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh;; \ *) \ echo ' cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $(subdir)/$@ $(am__depfiles_maybe);; \ esac; $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) cd $(top_builddir) && $(MAKE) $(AM_MAKEFLAGS) am--refresh $(am__aclocal_m4_deps): mostlyclean-libtool: -rm -f *.lo clean-libtool: -rm -rf .libs _libs tags: TAGS TAGS: ctags: CTAGS CTAGS: distdir: $(DISTFILES) @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ list='$(DISTFILES)'; \ dist_files=`for file in $$list; do echo $$file; done | \ sed -e "s|^$$srcdirstrip/||;t" \ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \ case $$dist_files in \ */*) $(MKDIR_P) `echo "$$dist_files" | \ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \ sort -u` ;; \ esac; \ for file in $$dist_files; do \ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ if test -d $$d/$$file; then \ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \ if test -d "$(distdir)/$$file"; then \ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ fi; \ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ fi; \ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \ else \ test -f "$(distdir)/$$file" \ || cp -p $$d/$$file "$(distdir)/$$file" \ || exit 1; \ fi; \ done check-am: all-am check: check-am all-am: Makefile installdirs: install: install-am install-exec: install-exec-am install-data: install-data-am uninstall: uninstall-am install-am: all-am @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am installcheck: installcheck-am install-strip: $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ `test -z '$(STRIP)' || \ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install mostlyclean-generic: clean-generic: distclean-generic: -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES) maintainer-clean-generic: @echo "This command is intended for maintainers to use" @echo "it deletes files that may require special tools to rebuild." clean: clean-am clean-am: clean-generic clean-libtool mostlyclean-am distclean: distclean-am -rm -f Makefile distclean-am: clean-am distclean-generic dvi: dvi-am dvi-am: html: html-am html-am: info: info-am info-am: install-data-am: install-dvi: install-dvi-am install-dvi-am: install-exec-am: install-html: install-html-am install-html-am: install-info: install-info-am install-info-am: install-man: install-pdf: install-pdf-am install-pdf-am: install-ps: install-ps-am install-ps-am: installcheck-am: maintainer-clean: maintainer-clean-am -rm -f Makefile maintainer-clean-am: distclean-am maintainer-clean-generic mostlyclean: mostlyclean-am mostlyclean-am: mostlyclean-generic mostlyclean-libtool pdf: pdf-am pdf-am: ps: ps-am ps-am: uninstall-am: .MAKE: install-am install-strip .PHONY: all all-am check check-am clean clean-generic clean-libtool \ distclean distclean-generic distclean-libtool distdir dvi \ dvi-am html html-am info info-am install install-am \ install-data install-data-am install-dvi install-dvi-am \ install-exec install-exec-am install-html install-html-am \ install-info install-info-am install-man install-pdf \ install-pdf-am install-ps install-ps-am install-strip \ installcheck installcheck-am installdirs maintainer-clean \ maintainer-clean-generic mostlyclean mostlyclean-generic \ mostlyclean-libtool pdf pdf-am ps ps-am uninstall uninstall-am # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/gst-autogen.sh0000644000175000017500000002111311610313111024652 0ustar andresandres# a silly hack that generates autoregen.sh but it's handy # Remove the old autoregen.sh first to create a new file, # as the current one may be being read by the shell executing # this script. if [ -f "autoregen.sh" ]; then rm autoregen.sh fi echo "#!/bin/sh" > autoregen.sh echo "./autogen.sh $@ \$@" >> autoregen.sh chmod +x autoregen.sh # helper functions for autogen.sh debug () # print out a debug message if DEBUG is a defined variable { if test ! -z "$DEBUG" then echo "DEBUG: $1" fi } version_check () # check the version of a package # first argument : package name (executable) # second argument : optional path where to look for it instead # third argument : source download url # rest of arguments : major, minor, micro version # all consecutive ones : suggestions for binaries to use # (if not specified in second argument) { PACKAGE=$1 PKG_PATH=$2 URL=$3 MAJOR=$4 MINOR=$5 MICRO=$6 # for backwards compatibility, we let PKG_PATH=PACKAGE when PKG_PATH null if test -z "$PKG_PATH"; then PKG_PATH=$PACKAGE; fi debug "major $MAJOR minor $MINOR micro $MICRO" VERSION=$MAJOR if test ! -z "$MINOR"; then VERSION=$VERSION.$MINOR; else MINOR=0; fi if test ! -z "$MICRO"; then VERSION=$VERSION.$MICRO; else MICRO=0; fi debug "major $MAJOR minor $MINOR micro $MICRO" for SUGGESTION in $PKG_PATH; do COMMAND="$SUGGESTION" # don't check if asked not to test -z "$NOCHECK" && { echo -n " checking for $COMMAND >= $VERSION ... " } || { # we set a var with the same name as the package, but stripped of # unwanted chars VAR=`echo $PACKAGE | sed 's/-//g'` debug "setting $VAR" eval $VAR="$COMMAND" return 0 } debug "checking version with $COMMAND" ($COMMAND --version) < /dev/null > /dev/null 2>&1 || { echo "not found." continue } # strip everything that's not a digit, then use cut to get the first field pkg_version=`$COMMAND --version|head -n 1|sed 's/^.*)[^0-9]*//'|cut -d' ' -f1` debug "pkg_version $pkg_version" # remove any non-digit characters from the version numbers to permit numeric # comparison pkg_major=`echo $pkg_version | cut -d. -f1 | sed s/[a-zA-Z\-].*//g` pkg_minor=`echo $pkg_version | cut -d. -f2 | sed s/[a-zA-Z\-].*//g` pkg_micro=`echo $pkg_version | cut -d. -f3 | sed s/[a-zA-Z\-].*//g` test -z "$pkg_major" && pkg_major=0 test -z "$pkg_minor" && pkg_minor=0 test -z "$pkg_micro" && pkg_micro=0 debug "found major $pkg_major minor $pkg_minor micro $pkg_micro" #start checking the version debug "version check" # reset check WRONG= if [ ! "$pkg_major" -gt "$MAJOR" ]; then debug "major: $pkg_major <= $MAJOR" if [ "$pkg_major" -lt "$MAJOR" ]; then debug "major: $pkg_major < $MAJOR" WRONG=1 elif [ ! "$pkg_minor" -gt "$MINOR" ]; then debug "minor: $pkg_minor <= $MINOR" if [ "$pkg_minor" -lt "$MINOR" ]; then debug "minor: $pkg_minor < $MINOR" WRONG=1 elif [ "$pkg_micro" -lt "$MICRO" ]; then debug "micro: $pkg_micro < $MICRO" WRONG=1 fi fi fi if test ! -z "$WRONG"; then echo "found $pkg_version, not ok !" continue else echo "found $pkg_version, ok." # we set a var with the same name as the package, but stripped of # unwanted chars VAR=`echo $PACKAGE | sed 's/-//g'` debug "setting $VAR" eval $VAR="$COMMAND" return 0 fi done echo "not found !" echo "You must have $PACKAGE installed to compile $package." echo "Download the appropriate package for your distribution," echo "or get the source tarball at $URL" return 1; } aclocal_check () { # normally aclocal is part of automake # so we expect it to be in the same place as automake # so if a different automake is supplied, we need to adapt as well # so how's about replacing automake with aclocal in the set var, # and saving that in $aclocal ? # note, this will fail if the actual automake isn't called automake* # or if part of the path before it contains it if [ -z "$automake" ]; then echo "Error: no automake variable set !" return 1 else aclocal=`echo $automake | sed s/automake/aclocal/` debug "aclocal: $aclocal" if [ "$aclocal" != "aclocal" ]; then CONFIGURE_DEF_OPT="$CONFIGURE_DEF_OPT --with-aclocal=$aclocal" fi if [ ! -x `which $aclocal` ]; then echo "Error: cannot execute $aclocal !" return 1 fi fi } autoheader_check () { # same here - autoheader is part of autoconf # use the same voodoo if [ -z "$autoconf" ]; then echo "Error: no autoconf variable set !" return 1 else autoheader=`echo $autoconf | sed s/autoconf/autoheader/` debug "autoheader: $autoheader" if [ "$autoheader" != "autoheader" ]; then CONFIGURE_DEF_OPT="$CONFIGURE_DEF_OPT --with-autoheader=$autoheader" fi if [ ! -x `which $autoheader` ]; then echo "Error: cannot execute $autoheader !" return 1 fi fi } autoconf_2_52d_check () { # autoconf 2.52d has a weird issue involving a yes:no error # so don't allow it's use test -z "$NOCHECK" && { ac_version=`$autoconf --version|head -n 1|sed 's/^[a-zA-Z\.\ ()]*//;s/ .*$//'` if test "$ac_version" = "2.52d"; then echo "autoconf 2.52d has an issue with our current build." echo "We don't know who's to blame however. So until we do, get a" echo "regular version. RPM's of a working version are on the gstreamer site." exit 1 fi } return 0 } die_check () { # call with $DIE # if set to 1, we need to print something helpful then die DIE=$1 if test "x$DIE" = "x1"; then echo echo "- Please get the right tools before proceeding." echo "- Alternatively, if you're sure we're wrong, run with --nocheck." exit 1 fi } autogen_options () { if test "x$1" = "x"; then return 0 fi while test "x$1" != "x" ; do optarg=`expr "x$1" : 'x[^=]*=\(.*\)'` case "$1" in --noconfigure) NOCONFIGURE=defined AUTOGEN_EXT_OPT="$AUTOGEN_EXT_OPT --noconfigure" echo "+ configure run disabled" shift ;; --nocheck) AUTOGEN_EXT_OPT="$AUTOGEN_EXT_OPT --nocheck" NOCHECK=defined echo "+ autotools version check disabled" shift ;; --debug) DEBUG=defined AUTOGEN_EXT_OPT="$AUTOGEN_EXT_OPT --debug" echo "+ debug output enabled" shift ;; --prefix=*) CONFIGURE_EXT_OPT="$CONFIGURE_EXT_OPT --prefix=$optarg" echo "+ passing --prefix=$optarg to configure" shift ;; --prefix) shift echo "DEBUG: $1" CONFIGURE_EXT_OPT="$CONFIGURE_EXT_OPT --prefix=$1" echo "+ passing --prefix=$1 to configure" shift ;; -h|--help) echo "autogen.sh (autogen options) -- (configure options)" echo "autogen.sh help options: " echo " --noconfigure don't run the configure script" echo " --nocheck don't do version checks" echo " --debug debug the autogen process" echo " --prefix will be passed on to configure" echo echo " --with-autoconf PATH use autoconf in PATH" echo " --with-automake PATH use automake in PATH" echo echo "to pass options to configure, put them as arguments after -- " exit 1 ;; --with-automake=*) AUTOMAKE=$optarg echo "+ using alternate automake in $optarg" CONFIGURE_DEF_OPT="$CONFIGURE_DEF_OPT --with-automake=$AUTOMAKE" shift ;; --with-autoconf=*) AUTOCONF=$optarg echo "+ using alternate autoconf in $optarg" CONFIGURE_DEF_OPT="$CONFIGURE_DEF_OPT --with-autoconf=$AUTOCONF" shift ;; --disable*|--enable*|--with*) echo "+ passing option $1 to configure" CONFIGURE_EXT_OPT="$CONFIGURE_EXT_OPT $1" shift ;; --) shift ; break ;; *) echo "- ignoring unknown autogen.sh argument $1"; shift ;; esac done for arg do CONFIGURE_EXT_OPT="$CONFIGURE_EXT_OPT $arg"; done if test ! -z "$CONFIGURE_EXT_OPT" then echo "+ options passed to configure: $CONFIGURE_EXT_OPT" fi } toplevel_check () { srcfile=$1 test -f $srcfile || { echo "You must run this script in the top-level $package directory" exit 1 } } tool_run () { tool=$1 options=$2 run_if_fail=$3 echo "+ running $tool $options..." $tool $options || { echo echo $tool failed eval $run_if_fail exit 1 } } crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/autogen.sh0000755000175000017500000000620711610313111024071 0ustar andresandres#!/bin/sh # you can either set the environment variables AUTOCONF and AUTOMAKE # to the right versions, or leave them unset and get the RedHat 7.3 defaults DIE=0 package=gst-plugin srcfile=src/main.c # autogen.sh helper functions (copied from GStreamer's common/ CVS module) if test ! -f ./gst-autogen.sh; then echo There is something wrong with your source tree. echo You are either missing ./gst-autogen.sh or not echo running autogen.sh from the top-level source echo directory. exit 1 fi . ./gst-autogen.sh CONFIGURE_DEF_OPT='--enable-maintainer-mode --enable-debug' autogen_options $@ echo -n "+ check for build tools" if test ! -z "$NOCHECK"; then echo " skipped"; else echo; fi version_check "autoconf" "$AUTOCONF autoconf autoconf259 autoconf257 autoconf-2.54 autoconf-2.53 autoconf-2.52" \ "ftp://ftp.gnu.org/pub/gnu/autoconf/" 2 52 || DIE=1 version_check "automake" "$AUTOMAKE automake automake-1.9 automake19 automake-1.7 automake-1.6 automake-1.5" \ "ftp://ftp.gnu.org/pub/gnu/automake/" 1 7 || DIE=1 ###version_check "autopoint" "autopoint" \ ### "ftp://ftp.gnu.org/pub/gnu/gettext/" 0 11 5 || DIE=1 version_check "libtoolize" "$LIBTOOLIZE libtoolize glibtoolize" \ "ftp://ftp.gnu.org/pub/gnu/libtool/" 1 5 0 || DIE=1 version_check "pkg-config" "" \ "http://www.freedesktop.org/software/pkgconfig" 0 8 0 || DIE=1 die_check $DIE autoconf_2_52d_check || DIE=1 aclocal_check || DIE=1 autoheader_check || DIE=1 die_check $DIE # if no arguments specified then this will be printed if test -z "$*"; then echo "+ checking for autogen.sh options" echo " This autogen script will automatically run ./configure as:" echo " ./configure $CONFIGURE_DEF_OPT" echo " To pass any additional options, please specify them on the $0" echo " command line." fi tool_run "$aclocal" "-I m4/ $ACLOCAL_FLAGS" tool_run "$libtoolize" "--copy --force" tool_run "$autoheader" tool_run "$autoconf" tool_run "$automake" "-a -c" if test ! -f /usr/include/libcrystalhd/libcrystalhd_if.h; then echo libcrystalhd is not installed echo install it from source or a binary package and re-run this script exit 1 fi # if enable exists, add an -enable option for each of the lines in that file if test -f enable; then for a in `cat enable`; do CONFIGURE_FILE_OPT="--enable-$a" done fi # if disable exists, add an -disable option for each of the lines in that file if test -f disable; then for a in `cat disable`; do CONFIGURE_FILE_OPT="$CONFIGURE_FILE_OPT --disable-$a" done fi test -n "$NOCONFIGURE" && { echo "+ skipping configure stage for package $package, as requested." echo "+ autogen.sh done." exit 0 } echo "+ running configure ... " test ! -z "$CONFIGURE_DEF_OPT" && echo " ./configure default flags: $CONFIGURE_DEF_OPT" test ! -z "$CONFIGURE_EXT_OPT" && echo " ./configure external flags: $CONFIGURE_EXT_OPT" test ! -z "$CONFIGURE_FILE_OPT" && echo " ./configure enable/disable flags: $CONFIGURE_FILE_OPT" echo ./configure $CONFIGURE_DEF_OPT $CONFIGURE_EXT_OPT $CONFIGURE_FILE_OPT || { echo " configure failed" exit 1 } echo "Now type 'make' to compile $package." crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/NEWS0000644000175000017500000000010411610313111022555 0ustar andresandresPlease refer to the release notes for all comments and instructions.crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/Makefile.am0000644000175000017500000000007111610313111024115 0ustar andresandresSUBDIRS = m4 src EXTRA_DIST = autogen.sh gst-autogen.sh crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/ChangeLog0000644000175000017500000000004211610313111023631 0ustar andresandresPlease refer to the release notes.crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/config.h.in0000644000175000017500000000331111610313116024111 0ustar andresandres/* config.h.in. Generated from configure.ac by autoheader. */ /* Define the version */ #undef GST_PLUGIN_VERSION /* Define the release version */ #undef GST_PLUGIN_VERSION_RELEASE /* Define to 1 if you have the header file. */ #undef HAVE_DLFCN_H /* Define to 1 if you have the header file. */ #undef HAVE_INTTYPES_H /* Define to 1 if you have the header file. */ #undef HAVE_MEMORY_H /* Define to 1 if you have the header file. */ #undef HAVE_STDINT_H /* Define to 1 if you have the header file. */ #undef HAVE_STDLIB_H /* Define to 1 if you have the header file. */ #undef HAVE_STRINGS_H /* Define to 1 if you have the header file. */ #undef HAVE_STRING_H /* Define to 1 if you have the header file. */ #undef HAVE_SYS_STAT_H /* Define to 1 if you have the header file. */ #undef HAVE_SYS_TYPES_H /* Define to 1 if you have the header file. */ #undef HAVE_UNISTD_H /* Define to the sub-directory in which libtool stores uninstalled libraries. */ #undef LT_OBJDIR /* Name of package */ #undef PACKAGE /* Define to the address where bug reports for this package should be sent. */ #undef PACKAGE_BUGREPORT /* Define to the full name of this package. */ #undef PACKAGE_NAME /* Define to the full name and version of this package. */ #undef PACKAGE_STRING /* Define to the one symbol short name of this package. */ #undef PACKAGE_TARNAME /* Define to the home page for this package. */ #undef PACKAGE_URL /* Define to the version of this package. */ #undef PACKAGE_VERSION /* Define to 1 if you have the ANSI C header files. */ #undef STDC_HEADERS /* Version number of package */ #undef VERSION crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/configure0000755000175000017500000147253411610313116024017 0ustar andresandres#! /bin/sh # Guess values for system-dependent variables and create Makefiles. # Generated by GNU Autoconf 2.68. # # # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, # 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software # Foundation, Inc. # # # This configure script is free software; the Free Software Foundation # gives unlimited permission to copy, distribute and modify it. ## -------------------- ## ## M4sh Initialization. ## ## -------------------- ## # Be more Bourne compatible DUALCASE=1; export DUALCASE # for MKS sh if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : emulate sh NULLCMD=: # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which # is contrary to our usage. Disable this feature. alias -g '${1+"$@"}'='"$@"' setopt NO_GLOB_SUBST else case `(set -o) 2>/dev/null` in #( *posix*) : set -o posix ;; #( *) : ;; esac fi as_nl=' ' export as_nl # Printing a long string crashes Solaris 7 /usr/bin/printf. as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo # Prefer a ksh shell builtin over an external printf program on Solaris, # but without wasting forks for bash or zsh. if test -z "$BASH_VERSION$ZSH_VERSION" \ && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then as_echo='print -r --' as_echo_n='print -rn --' elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then as_echo='printf %s\n' as_echo_n='printf %s' else if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' as_echo_n='/usr/ucb/echo -n' else as_echo_body='eval expr "X$1" : "X\\(.*\\)"' as_echo_n_body='eval arg=$1; case $arg in #( *"$as_nl"*) expr "X$arg" : "X\\(.*\\)$as_nl"; arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; esac; expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" ' export as_echo_n_body as_echo_n='sh -c $as_echo_n_body as_echo' fi export as_echo_body as_echo='sh -c $as_echo_body as_echo' fi # The user is always right. if test "${PATH_SEPARATOR+set}" != set; then PATH_SEPARATOR=: (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || PATH_SEPARATOR=';' } fi # IFS # We need space, tab and new line, in precisely that order. Quoting is # there to prevent editors from complaining about space-tab. # (If _AS_PATH_WALK were called with IFS unset, it would disable word # splitting by setting IFS to empty value.) IFS=" "" $as_nl" # Find who we are. Look in the path if we contain no directory separator. as_myself= case $0 in #(( *[\\/]* ) as_myself=$0 ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break done IFS=$as_save_IFS ;; esac # We did not find ourselves, most probably we were run as `sh COMMAND' # in which case we are not to be found in the path. if test "x$as_myself" = x; then as_myself=$0 fi if test ! -f "$as_myself"; then $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 exit 1 fi # Unset variables that we do not need and which cause bugs (e.g. in # pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" # suppresses any "Segmentation fault" message there. '((' could # trigger a bug in pdksh 5.2.14. for as_var in BASH_ENV ENV MAIL MAILPATH do eval test x\${$as_var+set} = xset \ && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : done PS1='$ ' PS2='> ' PS4='+ ' # NLS nuisances. LC_ALL=C export LC_ALL LANGUAGE=C export LANGUAGE # CDPATH. (unset CDPATH) >/dev/null 2>&1 && unset CDPATH if test "x$CONFIG_SHELL" = x; then as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : emulate sh NULLCMD=: # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which # is contrary to our usage. Disable this feature. alias -g '\${1+\"\$@\"}'='\"\$@\"' setopt NO_GLOB_SUBST else case \`(set -o) 2>/dev/null\` in #( *posix*) : set -o posix ;; #( *) : ;; esac fi " as_required="as_fn_return () { (exit \$1); } as_fn_success () { as_fn_return 0; } as_fn_failure () { as_fn_return 1; } as_fn_ret_success () { return 0; } as_fn_ret_failure () { return 1; } exitcode=0 as_fn_success || { exitcode=1; echo as_fn_success failed.; } as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : else exitcode=1; echo positional parameters were not saved. fi test x\$exitcode = x0 || exit 1" as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1 test -n \"\${ZSH_VERSION+set}\${BASH_VERSION+set}\" || ( ECHO='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' ECHO=\$ECHO\$ECHO\$ECHO\$ECHO\$ECHO ECHO=\$ECHO\$ECHO\$ECHO\$ECHO\$ECHO\$ECHO PATH=/empty FPATH=/empty; export PATH FPATH test \"X\`printf %s \$ECHO\`\" = \"X\$ECHO\" \\ || test \"X\`print -r -- \$ECHO\`\" = \"X\$ECHO\" ) || exit 1 test \$(( 1 + 1 )) = 2 || exit 1" if (eval "$as_required") 2>/dev/null; then : as_have_required=yes else as_have_required=no fi if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR as_found=false for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. as_found=: case $as_dir in #( /*) for as_base in sh bash ksh sh5; do # Try only shells that exist, to save several forks. as_shell=$as_dir/$as_base if { test -f "$as_shell" || test -f "$as_shell.exe"; } && { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : CONFIG_SHELL=$as_shell as_have_required=yes if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : break 2 fi fi done;; esac as_found=false done $as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : CONFIG_SHELL=$SHELL as_have_required=yes fi; } IFS=$as_save_IFS if test "x$CONFIG_SHELL" != x; then : # We cannot yet assume a decent shell, so we have to provide a # neutralization value for shells without unset; and this also # works around shells that cannot unset nonexistent variables. # Preserve -v and -x to the replacement shell. BASH_ENV=/dev/null ENV=/dev/null (unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV export CONFIG_SHELL case $- in # (((( *v*x* | *x*v* ) as_opts=-vx ;; *v* ) as_opts=-v ;; *x* ) as_opts=-x ;; * ) as_opts= ;; esac exec "$CONFIG_SHELL" $as_opts "$as_myself" ${1+"$@"} fi if test x$as_have_required = xno; then : $as_echo "$0: This script requires a shell more modern than all" $as_echo "$0: the shells that I found on your system." if test x${ZSH_VERSION+set} = xset ; then $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" $as_echo "$0: be upgraded to zsh 4.3.4 or later." else $as_echo "$0: Please tell bug-autoconf@gnu.org about your system, $0: including any error possibly output before this $0: message. Then install a modern shell, or manually run $0: the script under such a shell if you do have one." fi exit 1 fi fi fi SHELL=${CONFIG_SHELL-/bin/sh} export SHELL # Unset more variables known to interfere with behavior of common tools. CLICOLOR_FORCE= GREP_OPTIONS= unset CLICOLOR_FORCE GREP_OPTIONS ## --------------------- ## ## M4sh Shell Functions. ## ## --------------------- ## # as_fn_unset VAR # --------------- # Portably unset VAR. as_fn_unset () { { eval $1=; unset $1;} } as_unset=as_fn_unset # as_fn_set_status STATUS # ----------------------- # Set $? to STATUS, without forking. as_fn_set_status () { return $1 } # as_fn_set_status # as_fn_exit STATUS # ----------------- # Exit the shell with STATUS, even in a "trap 0" or "set -e" context. as_fn_exit () { set +e as_fn_set_status $1 exit $1 } # as_fn_exit # as_fn_mkdir_p # ------------- # Create "$as_dir" as a directory, including parents if necessary. as_fn_mkdir_p () { case $as_dir in #( -*) as_dir=./$as_dir;; esac test -d "$as_dir" || eval $as_mkdir_p || { as_dirs= while :; do case $as_dir in #( *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( *) as_qdir=$as_dir;; esac as_dirs="'$as_qdir' $as_dirs" as_dir=`$as_dirname -- "$as_dir" || $as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ X"$as_dir" : 'X\(//\)[^/]' \| \ X"$as_dir" : 'X\(//\)$' \| \ X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || $as_echo X"$as_dir" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/ q } /^X\(\/\/\)[^/].*/{ s//\1/ q } /^X\(\/\/\)$/{ s//\1/ q } /^X\(\/\).*/{ s//\1/ q } s/.*/./; q'` test -d "$as_dir" && break done test -z "$as_dirs" || eval "mkdir $as_dirs" } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir" } # as_fn_mkdir_p # as_fn_append VAR VALUE # ---------------------- # Append the text in VALUE to the end of the definition contained in VAR. Take # advantage of any shell optimizations that allow amortized linear growth over # repeated appends, instead of the typical quadratic growth present in naive # implementations. if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : eval 'as_fn_append () { eval $1+=\$2 }' else as_fn_append () { eval $1=\$$1\$2 } fi # as_fn_append # as_fn_arith ARG... # ------------------ # Perform arithmetic evaluation on the ARGs, and store the result in the # global $as_val. Take advantage of shells that can avoid forks. The arguments # must be portable across $(()) and expr. if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : eval 'as_fn_arith () { as_val=$(( $* )) }' else as_fn_arith () { as_val=`expr "$@" || test $? -eq 1` } fi # as_fn_arith # as_fn_error STATUS ERROR [LINENO LOG_FD] # ---------------------------------------- # Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are # provided, also output the error to LOG_FD, referencing LINENO. Then exit the # script with STATUS, using 1 if that was 0. as_fn_error () { as_status=$1; test $as_status -eq 0 && as_status=1 if test "$4"; then as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 fi $as_echo "$as_me: error: $2" >&2 as_fn_exit $as_status } # as_fn_error if expr a : '\(a\)' >/dev/null 2>&1 && test "X`expr 00001 : '.*\(...\)'`" = X001; then as_expr=expr else as_expr=false fi if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then as_basename=basename else as_basename=false fi if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then as_dirname=dirname else as_dirname=false fi as_me=`$as_basename -- "$0" || $as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ X"$0" : 'X\(//\)$' \| \ X"$0" : 'X\(/\)' \| . 2>/dev/null || $as_echo X/"$0" | sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/ q } /^X\/\(\/\/\)$/{ s//\1/ q } /^X\/\(\/\).*/{ s//\1/ q } s/.*/./; q'` # Avoid depending upon Character Ranges. as_cr_letters='abcdefghijklmnopqrstuvwxyz' as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' as_cr_Letters=$as_cr_letters$as_cr_LETTERS as_cr_digits='0123456789' as_cr_alnum=$as_cr_Letters$as_cr_digits as_lineno_1=$LINENO as_lineno_1a=$LINENO as_lineno_2=$LINENO as_lineno_2a=$LINENO eval 'test "x$as_lineno_1'$as_run'" != "x$as_lineno_2'$as_run'" && test "x`expr $as_lineno_1'$as_run' + 1`" = "x$as_lineno_2'$as_run'"' || { # Blame Lee E. McMahon (1931-1989) for sed's syntax. :-) sed -n ' p /[$]LINENO/= ' <$as_myself | sed ' s/[$]LINENO.*/&-/ t lineno b :lineno N :loop s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/ t loop s/-\n.*// ' >$as_me.lineno && chmod +x "$as_me.lineno" || { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; } # Don't try to exec as it changes $[0], causing all sort of problems # (the dirname of $[0] is not the place where we might find the # original and so on. Autoconf is especially sensitive to this). . "./$as_me.lineno" # Exit status is that of the last command. exit } ECHO_C= ECHO_N= ECHO_T= case `echo -n x` in #((((( -n*) case `echo 'xy\c'` in *c*) ECHO_T=' ';; # ECHO_T is single tab character. xy) ECHO_C='\c';; *) echo `echo ksh88 bug on AIX 6.1` > /dev/null ECHO_T=' ';; esac;; *) ECHO_N='-n';; esac rm -f conf$$ conf$$.exe conf$$.file if test -d conf$$.dir; then rm -f conf$$.dir/conf$$.file else rm -f conf$$.dir mkdir conf$$.dir 2>/dev/null fi if (echo >conf$$.file) 2>/dev/null; then if ln -s conf$$.file conf$$ 2>/dev/null; then as_ln_s='ln -s' # ... but there are two gotchas: # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. # In both cases, we have to default to `cp -p'. ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || as_ln_s='cp -p' elif ln conf$$.file conf$$ 2>/dev/null; then as_ln_s=ln else as_ln_s='cp -p' fi else as_ln_s='cp -p' fi rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file rmdir conf$$.dir 2>/dev/null if mkdir -p . 2>/dev/null; then as_mkdir_p='mkdir -p "$as_dir"' else test -d ./-p && rmdir ./-p as_mkdir_p=false fi if test -x / >/dev/null 2>&1; then as_test_x='test -x' else if ls -dL / >/dev/null 2>&1; then as_ls_L_option=L else as_ls_L_option= fi as_test_x=' eval sh -c '\'' if test -d "$1"; then test -d "$1/."; else case $1 in #( -*)set "./$1";; esac; case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( ???[sx]*):;;*)false;;esac;fi '\'' sh ' fi as_executable_p=$as_test_x # Sed expression to map a string onto a valid CPP name. as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" # Sed expression to map a string onto a valid variable name. as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" SHELL=${CONFIG_SHELL-/bin/sh} test -n "$DJDIR" || exec 7<&0 &1 # Name of the host. # hostname on some systems (SVR3.2, old GNU/Linux) returns a bogus exit status, # so uname gets run too. ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q` # # Initializations. # ac_default_prefix=/usr/local ac_clean_files= ac_config_libobj_dir=. LIBOBJS= cross_compiling=no subdirs= MFLAGS= MAKEFLAGS= # Identity of this package. PACKAGE_NAME= PACKAGE_TARNAME= PACKAGE_VERSION= PACKAGE_STRING= PACKAGE_BUGREPORT= PACKAGE_URL= ac_default_prefix=/usr # Factoring default headers for most tests. ac_includes_default="\ #include #ifdef HAVE_SYS_TYPES_H # include #endif #ifdef HAVE_SYS_STAT_H # include #endif #ifdef STDC_HEADERS # include # include #else # ifdef HAVE_STDLIB_H # include # endif #endif #ifdef HAVE_STRING_H # if !defined STDC_HEADERS && defined HAVE_MEMORY_H # include # endif # include #endif #ifdef HAVE_STRINGS_H # include #endif #ifdef HAVE_INTTYPES_H # include #endif #ifdef HAVE_STDINT_H # include #endif #ifdef HAVE_UNISTD_H # include #endif" ac_subst_vars='am__EXEEXT_FALSE am__EXEEXT_TRUE LTLIBOBJS LIBOBJS GST_PLUGIN_LDFLAGS plugindir GSTCTRL_LIBS GSTCTRL_CFLAGS GSTPB_BASE_LIBS GSTPB_BASE_CFLAGS GST_BASE_LIBS GST_BASE_CFLAGS GST_MAJORMINOR GST_LIBS GST_CFLAGS PKG_CONFIG_LIBDIR PKG_CONFIG_PATH PKG_CONFIG HAVE_PKGCONFIG CPP OTOOL64 OTOOL LIPO NMEDIT DSYMUTIL MANIFEST_TOOL RANLIB ac_ct_AR AR DLLTOOL OBJDUMP LN_S NM ac_ct_DUMPBIN DUMPBIN LD FGREP EGREP GREP SED host_os host_vendor host_cpu host build_os build_vendor build_cpu build LIBTOOL am__fastdepCC_FALSE am__fastdepCC_TRUE CCDEPMODE AMDEPBACKSLASH AMDEP_FALSE AMDEP_TRUE am__quote am__include DEPDIR OBJEXT EXEEXT ac_ct_CC CPPFLAGS LDFLAGS CFLAGS CC ACLOCAL_AMFLAGS am__untar am__tar AMTAR am__leading_dot SET_MAKE AWK mkdir_p MKDIR_P INSTALL_STRIP_PROGRAM STRIP install_sh MAKEINFO AUTOHEADER AUTOMAKE AUTOCONF ACLOCAL CYGPATH_W am__isrc INSTALL_DATA INSTALL_SCRIPT INSTALL_PROGRAM MAINT MAINTAINER_MODE_FALSE MAINTAINER_MODE_TRUE VERSION PACKAGE GST_PLUGIN_VERSION_NANO GST_PLUGIN_VERSION_MICRO GST_PLUGIN_VERSION_MINOR GST_PLUGIN_VERSION_MAJOR GST_PLUGIN_VERSION_RELEASE GST_PLUGIN_VERSION target_alias host_alias build_alias LIBS ECHO_T ECHO_N ECHO_C DEFS mandir localedir libdir psdir pdfdir dvidir htmldir infodir docdir oldincludedir includedir localstatedir sharedstatedir sysconfdir datadir datarootdir libexecdir sbindir bindir program_transform_name prefix exec_prefix PACKAGE_URL PACKAGE_BUGREPORT PACKAGE_STRING PACKAGE_VERSION PACKAGE_TARNAME PACKAGE_NAME PATH_SEPARATOR SHELL' ac_subst_files='' ac_user_opts=' enable_option_checking enable_maintainer_mode enable_dependency_tracking enable_shared enable_static with_pic enable_fast_install with_gnu_ld with_sysroot enable_libtool_lock ' ac_precious_vars='build_alias host_alias target_alias CC CFLAGS LDFLAGS LIBS CPPFLAGS CPP PKG_CONFIG PKG_CONFIG_PATH PKG_CONFIG_LIBDIR GST_CFLAGS GST_LIBS GST_BASE_CFLAGS GST_BASE_LIBS GSTPB_BASE_CFLAGS GSTPB_BASE_LIBS GSTCTRL_CFLAGS GSTCTRL_LIBS' # Initialize some variables set by options. ac_init_help= ac_init_version=false ac_unrecognized_opts= ac_unrecognized_sep= # The variables have the same names as the options, with # dashes changed to underlines. cache_file=/dev/null exec_prefix=NONE no_create= no_recursion= prefix=NONE program_prefix=NONE program_suffix=NONE program_transform_name=s,x,x, silent= site= srcdir= verbose= x_includes=NONE x_libraries=NONE # Installation directory options. # These are left unexpanded so users can "make install exec_prefix=/foo" # and all the variables that are supposed to be based on exec_prefix # by default will actually change. # Use braces instead of parens because sh, perl, etc. also accept them. # (The list follows the same order as the GNU Coding Standards.) bindir='${exec_prefix}/bin' sbindir='${exec_prefix}/sbin' libexecdir='${exec_prefix}/libexec' datarootdir='${prefix}/share' datadir='${datarootdir}' sysconfdir='${prefix}/etc' sharedstatedir='${prefix}/com' localstatedir='${prefix}/var' includedir='${prefix}/include' oldincludedir='/usr/include' docdir='${datarootdir}/doc/${PACKAGE}' infodir='${datarootdir}/info' htmldir='${docdir}' dvidir='${docdir}' pdfdir='${docdir}' psdir='${docdir}' libdir='${exec_prefix}/lib' localedir='${datarootdir}/locale' mandir='${datarootdir}/man' ac_prev= ac_dashdash= for ac_option do # If the previous option needs an argument, assign it. if test -n "$ac_prev"; then eval $ac_prev=\$ac_option ac_prev= continue fi case $ac_option in *=?*) ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;; *=) ac_optarg= ;; *) ac_optarg=yes ;; esac # Accept the important Cygnus configure options, so we can diagnose typos. case $ac_dashdash$ac_option in --) ac_dashdash=yes ;; -bindir | --bindir | --bindi | --bind | --bin | --bi) ac_prev=bindir ;; -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*) bindir=$ac_optarg ;; -build | --build | --buil | --bui | --bu) ac_prev=build_alias ;; -build=* | --build=* | --buil=* | --bui=* | --bu=*) build_alias=$ac_optarg ;; -cache-file | --cache-file | --cache-fil | --cache-fi \ | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c) ac_prev=cache_file ;; -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \ | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*) cache_file=$ac_optarg ;; --config-cache | -C) cache_file=config.cache ;; -datadir | --datadir | --datadi | --datad) ac_prev=datadir ;; -datadir=* | --datadir=* | --datadi=* | --datad=*) datadir=$ac_optarg ;; -datarootdir | --datarootdir | --datarootdi | --datarootd | --dataroot \ | --dataroo | --dataro | --datar) ac_prev=datarootdir ;; -datarootdir=* | --datarootdir=* | --datarootdi=* | --datarootd=* \ | --dataroot=* | --dataroo=* | --dataro=* | --datar=*) datarootdir=$ac_optarg ;; -disable-* | --disable-*) ac_useropt=`expr "x$ac_option" : 'x-*disable-\(.*\)'` # Reject names that are not valid shell variable names. expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && as_fn_error $? "invalid feature name: $ac_useropt" ac_useropt_orig=$ac_useropt ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` case $ac_user_opts in *" "enable_$ac_useropt" "*) ;; *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--disable-$ac_useropt_orig" ac_unrecognized_sep=', ';; esac eval enable_$ac_useropt=no ;; -docdir | --docdir | --docdi | --doc | --do) ac_prev=docdir ;; -docdir=* | --docdir=* | --docdi=* | --doc=* | --do=*) docdir=$ac_optarg ;; -dvidir | --dvidir | --dvidi | --dvid | --dvi | --dv) ac_prev=dvidir ;; -dvidir=* | --dvidir=* | --dvidi=* | --dvid=* | --dvi=* | --dv=*) dvidir=$ac_optarg ;; -enable-* | --enable-*) ac_useropt=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'` # Reject names that are not valid shell variable names. expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && as_fn_error $? "invalid feature name: $ac_useropt" ac_useropt_orig=$ac_useropt ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` case $ac_user_opts in *" "enable_$ac_useropt" "*) ;; *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--enable-$ac_useropt_orig" ac_unrecognized_sep=', ';; esac eval enable_$ac_useropt=\$ac_optarg ;; -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \ | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \ | --exec | --exe | --ex) ac_prev=exec_prefix ;; -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \ | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \ | --exec=* | --exe=* | --ex=*) exec_prefix=$ac_optarg ;; -gas | --gas | --ga | --g) # Obsolete; use --with-gas. with_gas=yes ;; -help | --help | --hel | --he | -h) ac_init_help=long ;; -help=r* | --help=r* | --hel=r* | --he=r* | -hr*) ac_init_help=recursive ;; -help=s* | --help=s* | --hel=s* | --he=s* | -hs*) ac_init_help=short ;; -host | --host | --hos | --ho) ac_prev=host_alias ;; -host=* | --host=* | --hos=* | --ho=*) host_alias=$ac_optarg ;; -htmldir | --htmldir | --htmldi | --htmld | --html | --htm | --ht) ac_prev=htmldir ;; -htmldir=* | --htmldir=* | --htmldi=* | --htmld=* | --html=* | --htm=* \ | --ht=*) htmldir=$ac_optarg ;; -includedir | --includedir | --includedi | --included | --include \ | --includ | --inclu | --incl | --inc) ac_prev=includedir ;; -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \ | --includ=* | --inclu=* | --incl=* | --inc=*) includedir=$ac_optarg ;; -infodir | --infodir | --infodi | --infod | --info | --inf) ac_prev=infodir ;; -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*) infodir=$ac_optarg ;; -libdir | --libdir | --libdi | --libd) ac_prev=libdir ;; -libdir=* | --libdir=* | --libdi=* | --libd=*) libdir=$ac_optarg ;; -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \ | --libexe | --libex | --libe) ac_prev=libexecdir ;; -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \ | --libexe=* | --libex=* | --libe=*) libexecdir=$ac_optarg ;; -localedir | --localedir | --localedi | --localed | --locale) ac_prev=localedir ;; -localedir=* | --localedir=* | --localedi=* | --localed=* | --locale=*) localedir=$ac_optarg ;; -localstatedir | --localstatedir | --localstatedi | --localstated \ | --localstate | --localstat | --localsta | --localst | --locals) ac_prev=localstatedir ;; -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \ | --localstate=* | --localstat=* | --localsta=* | --localst=* | --locals=*) localstatedir=$ac_optarg ;; -mandir | --mandir | --mandi | --mand | --man | --ma | --m) ac_prev=mandir ;; -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*) mandir=$ac_optarg ;; -nfp | --nfp | --nf) # Obsolete; use --without-fp. with_fp=no ;; -no-create | --no-create | --no-creat | --no-crea | --no-cre \ | --no-cr | --no-c | -n) no_create=yes ;; -no-recursion | --no-recursion | --no-recursio | --no-recursi \ | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) no_recursion=yes ;; -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \ | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \ | --oldin | --oldi | --old | --ol | --o) ac_prev=oldincludedir ;; -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \ | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \ | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*) oldincludedir=$ac_optarg ;; -prefix | --prefix | --prefi | --pref | --pre | --pr | --p) ac_prev=prefix ;; -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*) prefix=$ac_optarg ;; -program-prefix | --program-prefix | --program-prefi | --program-pref \ | --program-pre | --program-pr | --program-p) ac_prev=program_prefix ;; -program-prefix=* | --program-prefix=* | --program-prefi=* \ | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*) program_prefix=$ac_optarg ;; -program-suffix | --program-suffix | --program-suffi | --program-suff \ | --program-suf | --program-su | --program-s) ac_prev=program_suffix ;; -program-suffix=* | --program-suffix=* | --program-suffi=* \ | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*) program_suffix=$ac_optarg ;; -program-transform-name | --program-transform-name \ | --program-transform-nam | --program-transform-na \ | --program-transform-n | --program-transform- \ | --program-transform | --program-transfor \ | --program-transfo | --program-transf \ | --program-trans | --program-tran \ | --progr-tra | --program-tr | --program-t) ac_prev=program_transform_name ;; -program-transform-name=* | --program-transform-name=* \ | --program-transform-nam=* | --program-transform-na=* \ | --program-transform-n=* | --program-transform-=* \ | --program-transform=* | --program-transfor=* \ | --program-transfo=* | --program-transf=* \ | --program-trans=* | --program-tran=* \ | --progr-tra=* | --program-tr=* | --program-t=*) program_transform_name=$ac_optarg ;; -pdfdir | --pdfdir | --pdfdi | --pdfd | --pdf | --pd) ac_prev=pdfdir ;; -pdfdir=* | --pdfdir=* | --pdfdi=* | --pdfd=* | --pdf=* | --pd=*) pdfdir=$ac_optarg ;; -psdir | --psdir | --psdi | --psd | --ps) ac_prev=psdir ;; -psdir=* | --psdir=* | --psdi=* | --psd=* | --ps=*) psdir=$ac_optarg ;; -q | -quiet | --quiet | --quie | --qui | --qu | --q \ | -silent | --silent | --silen | --sile | --sil) silent=yes ;; -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb) ac_prev=sbindir ;; -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \ | --sbi=* | --sb=*) sbindir=$ac_optarg ;; -sharedstatedir | --sharedstatedir | --sharedstatedi \ | --sharedstated | --sharedstate | --sharedstat | --sharedsta \ | --sharedst | --shareds | --shared | --share | --shar \ | --sha | --sh) ac_prev=sharedstatedir ;; -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \ | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \ | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \ | --sha=* | --sh=*) sharedstatedir=$ac_optarg ;; -site | --site | --sit) ac_prev=site ;; -site=* | --site=* | --sit=*) site=$ac_optarg ;; -srcdir | --srcdir | --srcdi | --srcd | --src | --sr) ac_prev=srcdir ;; -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*) srcdir=$ac_optarg ;; -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \ | --syscon | --sysco | --sysc | --sys | --sy) ac_prev=sysconfdir ;; -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \ | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*) sysconfdir=$ac_optarg ;; -target | --target | --targe | --targ | --tar | --ta | --t) ac_prev=target_alias ;; -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*) target_alias=$ac_optarg ;; -v | -verbose | --verbose | --verbos | --verbo | --verb) verbose=yes ;; -version | --version | --versio | --versi | --vers | -V) ac_init_version=: ;; -with-* | --with-*) ac_useropt=`expr "x$ac_option" : 'x-*with-\([^=]*\)'` # Reject names that are not valid shell variable names. expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && as_fn_error $? "invalid package name: $ac_useropt" ac_useropt_orig=$ac_useropt ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` case $ac_user_opts in *" "with_$ac_useropt" "*) ;; *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--with-$ac_useropt_orig" ac_unrecognized_sep=', ';; esac eval with_$ac_useropt=\$ac_optarg ;; -without-* | --without-*) ac_useropt=`expr "x$ac_option" : 'x-*without-\(.*\)'` # Reject names that are not valid shell variable names. expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && as_fn_error $? "invalid package name: $ac_useropt" ac_useropt_orig=$ac_useropt ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` case $ac_user_opts in *" "with_$ac_useropt" "*) ;; *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--without-$ac_useropt_orig" ac_unrecognized_sep=', ';; esac eval with_$ac_useropt=no ;; --x) # Obsolete; use --with-x. with_x=yes ;; -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \ | --x-incl | --x-inc | --x-in | --x-i) ac_prev=x_includes ;; -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \ | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*) x_includes=$ac_optarg ;; -x-libraries | --x-libraries | --x-librarie | --x-librari \ | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l) ac_prev=x_libraries ;; -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \ | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*) x_libraries=$ac_optarg ;; -*) as_fn_error $? "unrecognized option: \`$ac_option' Try \`$0 --help' for more information" ;; *=*) ac_envvar=`expr "x$ac_option" : 'x\([^=]*\)='` # Reject names that are not valid shell variable names. case $ac_envvar in #( '' | [0-9]* | *[!_$as_cr_alnum]* ) as_fn_error $? "invalid variable name: \`$ac_envvar'" ;; esac eval $ac_envvar=\$ac_optarg export $ac_envvar ;; *) # FIXME: should be removed in autoconf 3.0. $as_echo "$as_me: WARNING: you should use --build, --host, --target" >&2 expr "x$ac_option" : ".*[^-._$as_cr_alnum]" >/dev/null && $as_echo "$as_me: WARNING: invalid host type: $ac_option" >&2 : "${build_alias=$ac_option} ${host_alias=$ac_option} ${target_alias=$ac_option}" ;; esac done if test -n "$ac_prev"; then ac_option=--`echo $ac_prev | sed 's/_/-/g'` as_fn_error $? "missing argument to $ac_option" fi if test -n "$ac_unrecognized_opts"; then case $enable_option_checking in no) ;; fatal) as_fn_error $? "unrecognized options: $ac_unrecognized_opts" ;; *) $as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2 ;; esac fi # Check all directory arguments for consistency. for ac_var in exec_prefix prefix bindir sbindir libexecdir datarootdir \ datadir sysconfdir sharedstatedir localstatedir includedir \ oldincludedir docdir infodir htmldir dvidir pdfdir psdir \ libdir localedir mandir do eval ac_val=\$$ac_var # Remove trailing slashes. case $ac_val in */ ) ac_val=`expr "X$ac_val" : 'X\(.*[^/]\)' \| "X$ac_val" : 'X\(.*\)'` eval $ac_var=\$ac_val;; esac # Be sure to have absolute directory names. case $ac_val in [\\/$]* | ?:[\\/]* ) continue;; NONE | '' ) case $ac_var in *prefix ) continue;; esac;; esac as_fn_error $? "expected an absolute directory name for --$ac_var: $ac_val" done # There might be people who depend on the old broken behavior: `$host' # used to hold the argument of --host etc. # FIXME: To remove some day. build=$build_alias host=$host_alias target=$target_alias # FIXME: To remove some day. if test "x$host_alias" != x; then if test "x$build_alias" = x; then cross_compiling=maybe $as_echo "$as_me: WARNING: if you wanted to set the --build type, don't use --host. If a cross compiler is detected then cross compile mode will be used" >&2 elif test "x$build_alias" != "x$host_alias"; then cross_compiling=yes fi fi ac_tool_prefix= test -n "$host_alias" && ac_tool_prefix=$host_alias- test "$silent" = yes && exec 6>/dev/null ac_pwd=`pwd` && test -n "$ac_pwd" && ac_ls_di=`ls -di .` && ac_pwd_ls_di=`cd "$ac_pwd" && ls -di .` || as_fn_error $? "working directory cannot be determined" test "X$ac_ls_di" = "X$ac_pwd_ls_di" || as_fn_error $? "pwd does not report name of working directory" # Find the source files, if location was not specified. if test -z "$srcdir"; then ac_srcdir_defaulted=yes # Try the directory containing this script, then the parent directory. ac_confdir=`$as_dirname -- "$as_myself" || $as_expr X"$as_myself" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ X"$as_myself" : 'X\(//\)[^/]' \| \ X"$as_myself" : 'X\(//\)$' \| \ X"$as_myself" : 'X\(/\)' \| . 2>/dev/null || $as_echo X"$as_myself" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/ q } /^X\(\/\/\)[^/].*/{ s//\1/ q } /^X\(\/\/\)$/{ s//\1/ q } /^X\(\/\).*/{ s//\1/ q } s/.*/./; q'` srcdir=$ac_confdir if test ! -r "$srcdir/$ac_unique_file"; then srcdir=.. fi else ac_srcdir_defaulted=no fi if test ! -r "$srcdir/$ac_unique_file"; then test "$ac_srcdir_defaulted" = yes && srcdir="$ac_confdir or .." as_fn_error $? "cannot find sources ($ac_unique_file) in $srcdir" fi ac_msg="sources are in $srcdir, but \`cd $srcdir' does not work" ac_abs_confdir=`( cd "$srcdir" && test -r "./$ac_unique_file" || as_fn_error $? "$ac_msg" pwd)` # When building in place, set srcdir=. if test "$ac_abs_confdir" = "$ac_pwd"; then srcdir=. fi # Remove unnecessary trailing slashes from srcdir. # Double slashes in file names in object file debugging info # mess up M-x gdb in Emacs. case $srcdir in */) srcdir=`expr "X$srcdir" : 'X\(.*[^/]\)' \| "X$srcdir" : 'X\(.*\)'`;; esac for ac_var in $ac_precious_vars; do eval ac_env_${ac_var}_set=\${${ac_var}+set} eval ac_env_${ac_var}_value=\$${ac_var} eval ac_cv_env_${ac_var}_set=\${${ac_var}+set} eval ac_cv_env_${ac_var}_value=\$${ac_var} done # # Report the --help message. # if test "$ac_init_help" = "long"; then # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF \`configure' configures this package to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... To assign environment variables (e.g., CC, CFLAGS...), specify them as VAR=VALUE. See below for descriptions of some of the useful variables. Defaults for the options are specified in brackets. Configuration: -h, --help display this help and exit --help=short display options specific to this package --help=recursive display the short help of all the included packages -V, --version display version information and exit -q, --quiet, --silent do not print \`checking ...' messages --cache-file=FILE cache test results in FILE [disabled] -C, --config-cache alias for \`--cache-file=config.cache' -n, --no-create do not create output files --srcdir=DIR find the sources in DIR [configure dir or \`..'] Installation directories: --prefix=PREFIX install architecture-independent files in PREFIX [$ac_default_prefix] --exec-prefix=EPREFIX install architecture-dependent files in EPREFIX [PREFIX] By default, \`make install' will install all the files in \`$ac_default_prefix/bin', \`$ac_default_prefix/lib' etc. You can specify an installation prefix other than \`$ac_default_prefix' using \`--prefix', for instance \`--prefix=\$HOME'. For better control, use the options below. Fine tuning of the installation directories: --bindir=DIR user executables [EPREFIX/bin] --sbindir=DIR system admin executables [EPREFIX/sbin] --libexecdir=DIR program executables [EPREFIX/libexec] --sysconfdir=DIR read-only single-machine data [PREFIX/etc] --sharedstatedir=DIR modifiable architecture-independent data [PREFIX/com] --localstatedir=DIR modifiable single-machine data [PREFIX/var] --libdir=DIR object code libraries [EPREFIX/lib] --includedir=DIR C header files [PREFIX/include] --oldincludedir=DIR C header files for non-gcc [/usr/include] --datarootdir=DIR read-only arch.-independent data root [PREFIX/share] --datadir=DIR read-only architecture-independent data [DATAROOTDIR] --infodir=DIR info documentation [DATAROOTDIR/info] --localedir=DIR locale-dependent data [DATAROOTDIR/locale] --mandir=DIR man documentation [DATAROOTDIR/man] --docdir=DIR documentation root [DATAROOTDIR/doc/PACKAGE] --htmldir=DIR html documentation [DOCDIR] --dvidir=DIR dvi documentation [DOCDIR] --pdfdir=DIR pdf documentation [DOCDIR] --psdir=DIR ps documentation [DOCDIR] _ACEOF cat <<\_ACEOF Program names: --program-prefix=PREFIX prepend PREFIX to installed program names --program-suffix=SUFFIX append SUFFIX to installed program names --program-transform-name=PROGRAM run sed PROGRAM on installed program names System types: --build=BUILD configure for building on BUILD [guessed] --host=HOST cross-compile to build programs to run on HOST [BUILD] _ACEOF fi if test -n "$ac_init_help"; then cat <<\_ACEOF Optional Features: --disable-option-checking ignore unrecognized --enable/--with options --disable-FEATURE do not include FEATURE (same as --enable-FEATURE=no) --enable-FEATURE[=ARG] include FEATURE [ARG=yes] --enable-maintainer-mode enable make rules and dependencies not useful (and sometimes confusing) to the casual installer --disable-dependency-tracking speeds up one-time build --enable-dependency-tracking do not reject slow dependency extractors --enable-shared[=PKGS] build shared libraries [default=yes] --enable-static[=PKGS] build static libraries [default=yes] --enable-fast-install[=PKGS] optimize for fast installation [default=yes] --disable-libtool-lock avoid locking (might break parallel builds) Optional Packages: --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no) --with-pic try to use only PIC/non-PIC objects [default=use both] --with-gnu-ld assume the C compiler uses GNU ld [default=no] --with-sysroot=DIR Search for dependent libraries within DIR (or the compiler's sysroot if not specified). Some influential environment variables: CC C compiler command CFLAGS C compiler flags LDFLAGS linker flags, e.g. -L if you have libraries in a nonstandard directory LIBS libraries to pass to the linker, e.g. -l CPPFLAGS (Objective) C/C++ preprocessor flags, e.g. -I if you have headers in a nonstandard directory CPP C preprocessor PKG_CONFIG path to pkg-config utility PKG_CONFIG_PATH directories to add to pkg-config's search path PKG_CONFIG_LIBDIR path overriding pkg-config's built-in search path GST_CFLAGS C compiler flags for GST, overriding pkg-config GST_LIBS linker flags for GST, overriding pkg-config GST_BASE_CFLAGS C compiler flags for GST_BASE, overriding pkg-config GST_BASE_LIBS linker flags for GST_BASE, overriding pkg-config GSTPB_BASE_CFLAGS C compiler flags for GSTPB_BASE, overriding pkg-config GSTPB_BASE_LIBS linker flags for GSTPB_BASE, overriding pkg-config GSTCTRL_CFLAGS C compiler flags for GSTCTRL, overriding pkg-config GSTCTRL_LIBS linker flags for GSTCTRL, overriding pkg-config Use these variables to override the choices made by `configure' or to help it to find libraries and programs with nonstandard names/locations. Report bugs to the package provider. _ACEOF ac_status=$? fi if test "$ac_init_help" = "recursive"; then # If there are subdirs, report their specific --help. for ac_dir in : $ac_subdirs_all; do test "x$ac_dir" = x: && continue test -d "$ac_dir" || { cd "$srcdir" && ac_pwd=`pwd` && srcdir=. && test -d "$ac_dir"; } || continue ac_builddir=. case "$ac_dir" in .) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;; *) ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'` # A ".." for each directory in $ac_dir_suffix. ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'` case $ac_top_builddir_sub in "") ac_top_builddir_sub=. ac_top_build_prefix= ;; *) ac_top_build_prefix=$ac_top_builddir_sub/ ;; esac ;; esac ac_abs_top_builddir=$ac_pwd ac_abs_builddir=$ac_pwd$ac_dir_suffix # for backward compatibility: ac_top_builddir=$ac_top_build_prefix case $srcdir in .) # We are building in place. ac_srcdir=. ac_top_srcdir=$ac_top_builddir_sub ac_abs_top_srcdir=$ac_pwd ;; [\\/]* | ?:[\\/]* ) # Absolute name. ac_srcdir=$srcdir$ac_dir_suffix; ac_top_srcdir=$srcdir ac_abs_top_srcdir=$srcdir ;; *) # Relative name. ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix ac_top_srcdir=$ac_top_build_prefix$srcdir ac_abs_top_srcdir=$ac_pwd/$srcdir ;; esac ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix cd "$ac_dir" || { ac_status=$?; continue; } # Check for guested configure. if test -f "$ac_srcdir/configure.gnu"; then echo && $SHELL "$ac_srcdir/configure.gnu" --help=recursive elif test -f "$ac_srcdir/configure"; then echo && $SHELL "$ac_srcdir/configure" --help=recursive else $as_echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2 fi || ac_status=$? cd "$ac_pwd" || { ac_status=$?; break; } done fi test -n "$ac_init_help" && exit $ac_status if $ac_init_version; then cat <<\_ACEOF configure generated by GNU Autoconf 2.68 Copyright (C) 2010 Free Software Foundation, Inc. This configure script is free software; the Free Software Foundation gives unlimited permission to copy, distribute and modify it. _ACEOF exit fi ## ------------------------ ## ## Autoconf initialization. ## ## ------------------------ ## # ac_fn_c_try_compile LINENO # -------------------------- # Try to compile conftest.$ac_ext, and return whether this succeeded. ac_fn_c_try_compile () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack rm -f conftest.$ac_objext if { { ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" $as_echo "$ac_try_echo"; } >&5 (eval "$ac_compile") 2>conftest.err ac_status=$? if test -s conftest.err; then grep -v '^ *+' conftest.err >conftest.er1 cat conftest.er1 >&5 mv -f conftest.er1 conftest.err fi $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest.$ac_objext; then : ac_retval=0 else $as_echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_retval=1 fi eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno as_fn_set_status $ac_retval } # ac_fn_c_try_compile # ac_fn_c_try_link LINENO # ----------------------- # Try to link conftest.$ac_ext, and return whether this succeeded. ac_fn_c_try_link () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack rm -f conftest.$ac_objext conftest$ac_exeext if { { ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" $as_echo "$ac_try_echo"; } >&5 (eval "$ac_link") 2>conftest.err ac_status=$? if test -s conftest.err; then grep -v '^ *+' conftest.err >conftest.er1 cat conftest.er1 >&5 mv -f conftest.er1 conftest.err fi $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } && { test -z "$ac_c_werror_flag" || test ! -s conftest.err } && test -s conftest$ac_exeext && { test "$cross_compiling" = yes || $as_test_x conftest$ac_exeext }; then : ac_retval=0 else $as_echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_retval=1 fi # Delete the IPA/IPO (Inter Procedural Analysis/Optimization) information # created by the PGI compiler (conftest_ipa8_conftest.oo), as it would # interfere with the next link command; also delete a directory that is # left behind by Apple's compiler. We do this before executing the actions. rm -rf conftest.dSYM conftest_ipa8_conftest.oo eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno as_fn_set_status $ac_retval } # ac_fn_c_try_link # ac_fn_c_check_header_compile LINENO HEADER VAR INCLUDES # ------------------------------------------------------- # Tests whether HEADER exists and can be compiled using the include files in # INCLUDES, setting the cache variable VAR accordingly. ac_fn_c_check_header_compile () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 $as_echo_n "checking for $2... " >&6; } if eval \${$3+:} false; then : $as_echo_n "(cached) " >&6 else cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ $4 #include <$2> _ACEOF if ac_fn_c_try_compile "$LINENO"; then : eval "$3=yes" else eval "$3=no" fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi eval ac_res=\$$3 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 $as_echo "$ac_res" >&6; } eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno } # ac_fn_c_check_header_compile # ac_fn_c_try_cpp LINENO # ---------------------- # Try to preprocess conftest.$ac_ext, and return whether this succeeded. ac_fn_c_try_cpp () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack if { { ac_try="$ac_cpp conftest.$ac_ext" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" $as_echo "$ac_try_echo"; } >&5 (eval "$ac_cpp conftest.$ac_ext") 2>conftest.err ac_status=$? if test -s conftest.err; then grep -v '^ *+' conftest.err >conftest.er1 cat conftest.er1 >&5 mv -f conftest.er1 conftest.err fi $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } > conftest.i && { test -z "$ac_c_preproc_warn_flag$ac_c_werror_flag" || test ! -s conftest.err }; then : ac_retval=0 else $as_echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_retval=1 fi eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno as_fn_set_status $ac_retval } # ac_fn_c_try_cpp # ac_fn_c_try_run LINENO # ---------------------- # Try to link conftest.$ac_ext, and return whether this succeeded. Assumes # that executables *can* be run. ac_fn_c_try_run () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack if { { ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" $as_echo "$ac_try_echo"; } >&5 (eval "$ac_link") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } && { ac_try='./conftest$ac_exeext' { { case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" $as_echo "$ac_try_echo"; } >&5 (eval "$ac_try") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; }; then : ac_retval=0 else $as_echo "$as_me: program exited with status $ac_status" >&5 $as_echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 ac_retval=$ac_status fi rm -rf conftest.dSYM conftest_ipa8_conftest.oo eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno as_fn_set_status $ac_retval } # ac_fn_c_try_run # ac_fn_c_check_func LINENO FUNC VAR # ---------------------------------- # Tests whether FUNC exists, setting the cache variable VAR accordingly ac_fn_c_check_func () { as_lineno=${as_lineno-"$1"} as_lineno_stack=as_lineno_stack=$as_lineno_stack { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $2" >&5 $as_echo_n "checking for $2... " >&6; } if eval \${$3+:} false; then : $as_echo_n "(cached) " >&6 else cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Define $2 to an innocuous variant, in case declares $2. For example, HP-UX 11i declares gettimeofday. */ #define $2 innocuous_$2 /* System header to define __stub macros and hopefully few prototypes, which can conflict with char $2 (); below. Prefer to if __STDC__ is defined, since exists even on freestanding compilers. */ #ifdef __STDC__ # include #else # include #endif #undef $2 /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char $2 (); /* The GNU C library defines this for functions which it implements to always fail with ENOSYS. Some functions are actually named something starting with __ and the normal name is an alias. */ #if defined __stub_$2 || defined __stub___$2 choke me #endif int main () { return $2 (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : eval "$3=yes" else eval "$3=no" fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext fi eval ac_res=\$$3 { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_res" >&5 $as_echo "$ac_res" >&6; } eval $as_lineno_stack; ${as_lineno_stack:+:} unset as_lineno } # ac_fn_c_check_func cat >config.log <<_ACEOF This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. It was created by $as_me, which was generated by GNU Autoconf 2.68. Invocation command line was $ $0 $@ _ACEOF exec 5>>config.log { cat <<_ASUNAME ## --------- ## ## Platform. ## ## --------- ## hostname = `(hostname || uname -n) 2>/dev/null | sed 1q` uname -m = `(uname -m) 2>/dev/null || echo unknown` uname -r = `(uname -r) 2>/dev/null || echo unknown` uname -s = `(uname -s) 2>/dev/null || echo unknown` uname -v = `(uname -v) 2>/dev/null || echo unknown` /usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown` /bin/uname -X = `(/bin/uname -X) 2>/dev/null || echo unknown` /bin/arch = `(/bin/arch) 2>/dev/null || echo unknown` /usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null || echo unknown` /usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown` /usr/bin/hostinfo = `(/usr/bin/hostinfo) 2>/dev/null || echo unknown` /bin/machine = `(/bin/machine) 2>/dev/null || echo unknown` /usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null || echo unknown` /bin/universe = `(/bin/universe) 2>/dev/null || echo unknown` _ASUNAME as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. $as_echo "PATH: $as_dir" done IFS=$as_save_IFS } >&5 cat >&5 <<_ACEOF ## ----------- ## ## Core tests. ## ## ----------- ## _ACEOF # Keep a trace of the command line. # Strip out --no-create and --no-recursion so they do not pile up. # Strip out --silent because we don't want to record it for future runs. # Also quote any args containing shell meta-characters. # Make two passes to allow for proper duplicate-argument suppression. ac_configure_args= ac_configure_args0= ac_configure_args1= ac_must_keep_next=false for ac_pass in 1 2 do for ac_arg do case $ac_arg in -no-create | --no-c* | -n | -no-recursion | --no-r*) continue ;; -q | -quiet | --quiet | --quie | --qui | --qu | --q \ | -silent | --silent | --silen | --sile | --sil) continue ;; *\'*) ac_arg=`$as_echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;; esac case $ac_pass in 1) as_fn_append ac_configure_args0 " '$ac_arg'" ;; 2) as_fn_append ac_configure_args1 " '$ac_arg'" if test $ac_must_keep_next = true; then ac_must_keep_next=false # Got value, back to normal. else case $ac_arg in *=* | --config-cache | -C | -disable-* | --disable-* \ | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \ | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \ | -with-* | --with-* | -without-* | --without-* | --x) case "$ac_configure_args0 " in "$ac_configure_args1"*" '$ac_arg' "* ) continue ;; esac ;; -* ) ac_must_keep_next=true ;; esac fi as_fn_append ac_configure_args " '$ac_arg'" ;; esac done done { ac_configure_args0=; unset ac_configure_args0;} { ac_configure_args1=; unset ac_configure_args1;} # When interrupted or exit'd, cleanup temporary files, and complete # config.log. We remove comments because anyway the quotes in there # would cause problems or look ugly. # WARNING: Use '\'' to represent an apostrophe within the trap. # WARNING: Do not start the trap code with a newline, due to a FreeBSD 4.0 bug. trap 'exit_status=$? # Save into config.log some information that might help in debugging. { echo $as_echo "## ---------------- ## ## Cache variables. ## ## ---------------- ##" echo # The following way of writing the cache mishandles newlines in values, ( for ac_var in `(set) 2>&1 | sed -n '\''s/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'\''`; do eval ac_val=\$$ac_var case $ac_val in #( *${as_nl}*) case $ac_var in #( *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 $as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; esac case $ac_var in #( _ | IFS | as_nl) ;; #( BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( *) { eval $ac_var=; unset $ac_var;} ;; esac ;; esac done (set) 2>&1 | case $as_nl`(ac_space='\'' '\''; set) 2>&1` in #( *${as_nl}ac_space=\ *) sed -n \ "s/'\''/'\''\\\\'\'''\''/g; s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\''\\2'\''/p" ;; #( *) sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" ;; esac | sort ) echo $as_echo "## ----------------- ## ## Output variables. ## ## ----------------- ##" echo for ac_var in $ac_subst_vars do eval ac_val=\$$ac_var case $ac_val in *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;; esac $as_echo "$ac_var='\''$ac_val'\''" done | sort echo if test -n "$ac_subst_files"; then $as_echo "## ------------------- ## ## File substitutions. ## ## ------------------- ##" echo for ac_var in $ac_subst_files do eval ac_val=\$$ac_var case $ac_val in *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;; esac $as_echo "$ac_var='\''$ac_val'\''" done | sort echo fi if test -s confdefs.h; then $as_echo "## ----------- ## ## confdefs.h. ## ## ----------- ##" echo cat confdefs.h echo fi test "$ac_signal" != 0 && $as_echo "$as_me: caught signal $ac_signal" $as_echo "$as_me: exit $exit_status" } >&5 rm -f core *.core core.conftest.* && rm -f -r conftest* confdefs* conf$$* $ac_clean_files && exit $exit_status ' 0 for ac_signal in 1 2 13 15; do trap 'ac_signal='$ac_signal'; as_fn_exit 1' $ac_signal done ac_signal=0 # confdefs.h avoids OS command line length limits that DEFS can exceed. rm -f -r conftest* confdefs.h $as_echo "/* confdefs.h */" > confdefs.h # Predefined preprocessor variables. cat >>confdefs.h <<_ACEOF #define PACKAGE_NAME "$PACKAGE_NAME" _ACEOF cat >>confdefs.h <<_ACEOF #define PACKAGE_TARNAME "$PACKAGE_TARNAME" _ACEOF cat >>confdefs.h <<_ACEOF #define PACKAGE_VERSION "$PACKAGE_VERSION" _ACEOF cat >>confdefs.h <<_ACEOF #define PACKAGE_STRING "$PACKAGE_STRING" _ACEOF cat >>confdefs.h <<_ACEOF #define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT" _ACEOF cat >>confdefs.h <<_ACEOF #define PACKAGE_URL "$PACKAGE_URL" _ACEOF # Let the site file select an alternate cache file if it wants to. # Prefer an explicitly selected file to automatically selected ones. ac_site_file1=NONE ac_site_file2=NONE if test -n "$CONFIG_SITE"; then # We do not want a PATH search for config.site. case $CONFIG_SITE in #(( -*) ac_site_file1=./$CONFIG_SITE;; */*) ac_site_file1=$CONFIG_SITE;; *) ac_site_file1=./$CONFIG_SITE;; esac elif test "x$prefix" != xNONE; then ac_site_file1=$prefix/share/config.site ac_site_file2=$prefix/etc/config.site else ac_site_file1=$ac_default_prefix/share/config.site ac_site_file2=$ac_default_prefix/etc/config.site fi for ac_site_file in "$ac_site_file1" "$ac_site_file2" do test "x$ac_site_file" = xNONE && continue if test /dev/null != "$ac_site_file" && test -r "$ac_site_file"; then { $as_echo "$as_me:${as_lineno-$LINENO}: loading site script $ac_site_file" >&5 $as_echo "$as_me: loading site script $ac_site_file" >&6;} sed 's/^/| /' "$ac_site_file" >&5 . "$ac_site_file" \ || { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error $? "failed to load site script $ac_site_file See \`config.log' for more details" "$LINENO" 5; } fi done if test -r "$cache_file"; then # Some versions of bash will fail to source /dev/null (special files # actually), so we avoid doing that. DJGPP emulates it as a regular file. if test /dev/null != "$cache_file" && test -f "$cache_file"; then { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5 $as_echo "$as_me: loading cache $cache_file" >&6;} case $cache_file in [\\/]* | ?:[\\/]* ) . "$cache_file";; *) . "./$cache_file";; esac fi else { $as_echo "$as_me:${as_lineno-$LINENO}: creating cache $cache_file" >&5 $as_echo "$as_me: creating cache $cache_file" >&6;} >$cache_file fi # Check that the precious variables saved in the cache have kept the same # value. ac_cache_corrupted=false for ac_var in $ac_precious_vars; do eval ac_old_set=\$ac_cv_env_${ac_var}_set eval ac_new_set=\$ac_env_${ac_var}_set eval ac_old_val=\$ac_cv_env_${ac_var}_value eval ac_new_val=\$ac_env_${ac_var}_value case $ac_old_set,$ac_new_set in set,) { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5 $as_echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;} ac_cache_corrupted=: ;; ,set) { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was not set in the previous run" >&5 $as_echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;} ac_cache_corrupted=: ;; ,);; *) if test "x$ac_old_val" != "x$ac_new_val"; then # differences in whitespace do not lead to failure. ac_old_val_w=`echo x $ac_old_val` ac_new_val_w=`echo x $ac_new_val` if test "$ac_old_val_w" != "$ac_new_val_w"; then { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' has changed since the previous run:" >&5 $as_echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;} ac_cache_corrupted=: else { $as_echo "$as_me:${as_lineno-$LINENO}: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&5 $as_echo "$as_me: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&2;} eval $ac_var=\$ac_old_val fi { $as_echo "$as_me:${as_lineno-$LINENO}: former value: \`$ac_old_val'" >&5 $as_echo "$as_me: former value: \`$ac_old_val'" >&2;} { $as_echo "$as_me:${as_lineno-$LINENO}: current value: \`$ac_new_val'" >&5 $as_echo "$as_me: current value: \`$ac_new_val'" >&2;} fi;; esac # Pass precious variables to config.status. if test "$ac_new_set" = set; then case $ac_new_val in *\'*) ac_arg=$ac_var=`$as_echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;; *) ac_arg=$ac_var=$ac_new_val ;; esac case " $ac_configure_args " in *" '$ac_arg' "*) ;; # Avoid dups. Use of quotes ensures accuracy. *) as_fn_append ac_configure_args " '$ac_arg'" ;; esac fi done if $ac_cache_corrupted; then { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} { $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5 $as_echo "$as_me: error: changes in the environment can compromise the build" >&2;} as_fn_error $? "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5 fi ## -------------------- ## ## Main body of script. ## ## -------------------- ## ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu GST_MAJORMINOR=0.10 GST_REQUIRED=0.10.0 GSTPB_REQUIRED=0.10.0 PACKAGE=gst-bcmdec GST_PLUGIN_VERSION_MAJOR=0 GST_PLUGIN_VERSION_MINOR=10 GST_PLUGIN_VERSION_MICRO=40 NANO=0 GST_PLUGIN_VERSION_NANO=$NANO if test "x$NANO" = "x" || test "x$NANO" = "x0"; then { $as_echo "$as_me:${as_lineno-$LINENO}: configuring gst-bcmdec for release" >&5 $as_echo "$as_me: configuring gst-bcmdec for release" >&6;} VERSION=0.10.40 GST_PLUGIN_VERSION_RELEASE=1 GST_PLUGIN_CVS="no" else { $as_echo "$as_me:${as_lineno-$LINENO}: configuring gst-bcmdec for development with nano $NANO" >&5 $as_echo "$as_me: configuring gst-bcmdec for development with nano $NANO" >&6;} VERSION=0.10.40.$NANO GST_PLUGIN_VERSION_RELEASE=0.`date +%Y%m%d.%H%M%S` GST_PLUGIN_CVS="yes" fi GST_PLUGIN_VERSION=$VERSION cat >>confdefs.h <<_ACEOF #define GST_PLUGIN_VERSION "$GST_PLUGIN_VERSION" _ACEOF cat >>confdefs.h <<_ACEOF #define GST_PLUGIN_VERSION_RELEASE "$GST_PLUGIN_VERSION_RELEASE" _ACEOF cat >>confdefs.h <<_ACEOF #define PACKAGE "$PACKAGE" _ACEOF cat >>confdefs.h <<_ACEOF #define VERSION "$VERSION" _ACEOF { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to enable maintainer-specific portions of Makefiles" >&5 $as_echo_n "checking whether to enable maintainer-specific portions of Makefiles... " >&6; } # Check whether --enable-maintainer-mode was given. if test "${enable_maintainer_mode+set}" = set; then : enableval=$enable_maintainer_mode; USE_MAINTAINER_MODE=$enableval else USE_MAINTAINER_MODE=no fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $USE_MAINTAINER_MODE" >&5 $as_echo "$USE_MAINTAINER_MODE" >&6; } if test $USE_MAINTAINER_MODE = yes; then MAINTAINER_MODE_TRUE= MAINTAINER_MODE_FALSE='#' else MAINTAINER_MODE_TRUE='#' MAINTAINER_MODE_FALSE= fi MAINT=$MAINTAINER_MODE_TRUE am__api_version='1.11' ac_aux_dir= for ac_dir in "$srcdir" "$srcdir/.." "$srcdir/../.."; do if test -f "$ac_dir/install-sh"; then ac_aux_dir=$ac_dir ac_install_sh="$ac_aux_dir/install-sh -c" break elif test -f "$ac_dir/install.sh"; then ac_aux_dir=$ac_dir ac_install_sh="$ac_aux_dir/install.sh -c" break elif test -f "$ac_dir/shtool"; then ac_aux_dir=$ac_dir ac_install_sh="$ac_aux_dir/shtool install -c" break fi done if test -z "$ac_aux_dir"; then as_fn_error $? "cannot find install-sh, install.sh, or shtool in \"$srcdir\" \"$srcdir/..\" \"$srcdir/../..\"" "$LINENO" 5 fi # These three variables are undocumented and unsupported, # and are intended to be withdrawn in a future Autoconf release. # They can cause serious problems if a builder's source tree is in a directory # whose full name contains unusual characters. ac_config_guess="$SHELL $ac_aux_dir/config.guess" # Please don't use this var. ac_config_sub="$SHELL $ac_aux_dir/config.sub" # Please don't use this var. ac_configure="$SHELL $ac_aux_dir/configure" # Please don't use this var. # Find a good install program. We prefer a C program (faster), # so one script is as good as another. But avoid the broken or # incompatible versions: # SysV /etc/install, /usr/sbin/install # SunOS /usr/etc/install # IRIX /sbin/install # AIX /bin/install # AmigaOS /C/install, which installs bootblocks on floppy discs # AIX 4 /usr/bin/installbsd, which doesn't work without a -g flag # AFS /usr/afsws/bin/install, which mishandles nonexistent args # SVR4 /usr/ucb/install, which tries to use the nonexistent group "staff" # OS/2's system install, which has a completely different semantic # ./install, which can be erroneously created by make from ./install.sh. # Reject install programs that cannot install multiple files. { $as_echo "$as_me:${as_lineno-$LINENO}: checking for a BSD-compatible install" >&5 $as_echo_n "checking for a BSD-compatible install... " >&6; } if test -z "$INSTALL"; then if ${ac_cv_path_install+:} false; then : $as_echo_n "(cached) " >&6 else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. # Account for people who put trailing slashes in PATH elements. case $as_dir/ in #(( ./ | .// | /[cC]/* | \ /etc/* | /usr/sbin/* | /usr/etc/* | /sbin/* | /usr/afsws/bin/* | \ ?:[\\/]os2[\\/]install[\\/]* | ?:[\\/]OS2[\\/]INSTALL[\\/]* | \ /usr/ucb/* ) ;; *) # OSF1 and SCO ODT 3.0 have their own names for install. # Don't use installbsd from OSF since it installs stuff as root # by default. for ac_prog in ginstall scoinst install; do for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; }; then if test $ac_prog = install && grep dspmsg "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then # AIX install. It has an incompatible calling convention. : elif test $ac_prog = install && grep pwplus "$as_dir/$ac_prog$ac_exec_ext" >/dev/null 2>&1; then # program-specific install script used by HP pwplus--don't use. : else rm -rf conftest.one conftest.two conftest.dir echo one > conftest.one echo two > conftest.two mkdir conftest.dir if "$as_dir/$ac_prog$ac_exec_ext" -c conftest.one conftest.two "`pwd`/conftest.dir" && test -s conftest.one && test -s conftest.two && test -s conftest.dir/conftest.one && test -s conftest.dir/conftest.two then ac_cv_path_install="$as_dir/$ac_prog$ac_exec_ext -c" break 3 fi fi fi done done ;; esac done IFS=$as_save_IFS rm -rf conftest.one conftest.two conftest.dir fi if test "${ac_cv_path_install+set}" = set; then INSTALL=$ac_cv_path_install else # As a last resort, use the slow shell script. Don't cache a # value for INSTALL within a source directory, because that will # break other packages using the cache if that directory is # removed, or if the value is a relative name. INSTALL=$ac_install_sh fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $INSTALL" >&5 $as_echo "$INSTALL" >&6; } # Use test -z because SunOS4 sh mishandles braces in ${var-val}. # It thinks the first close brace ends the variable substitution. test -z "$INSTALL_PROGRAM" && INSTALL_PROGRAM='${INSTALL}' test -z "$INSTALL_SCRIPT" && INSTALL_SCRIPT='${INSTALL}' test -z "$INSTALL_DATA" && INSTALL_DATA='${INSTALL} -m 644' { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether build environment is sane" >&5 $as_echo_n "checking whether build environment is sane... " >&6; } # Just in case sleep 1 echo timestamp > conftest.file # Reject unsafe characters in $srcdir or the absolute working directory # name. Accept space and tab only in the latter. am_lf=' ' case `pwd` in *[\\\"\#\$\&\'\`$am_lf]*) as_fn_error $? "unsafe absolute working directory name" "$LINENO" 5;; esac case $srcdir in *[\\\"\#\$\&\'\`$am_lf\ \ ]*) as_fn_error $? "unsafe srcdir value: \`$srcdir'" "$LINENO" 5;; esac # Do `set' in a subshell so we don't clobber the current shell's # arguments. Must try -L first in case configure is actually a # symlink; some systems play weird games with the mod time of symlinks # (eg FreeBSD returns the mod time of the symlink's containing # directory). if ( set X `ls -Lt "$srcdir/configure" conftest.file 2> /dev/null` if test "$*" = "X"; then # -L didn't work. set X `ls -t "$srcdir/configure" conftest.file` fi rm -f conftest.file if test "$*" != "X $srcdir/configure conftest.file" \ && test "$*" != "X conftest.file $srcdir/configure"; then # If neither matched, then we have a broken ls. This can happen # if, for instance, CONFIG_SHELL is bash and it inherits a # broken ls alias from the environment. This has actually # happened. Such a system could not be considered "sane". as_fn_error $? "ls -t appears to fail. Make sure there is not a broken alias in your environment" "$LINENO" 5 fi test "$2" = conftest.file ) then # Ok. : else as_fn_error $? "newly created file is older than distributed files! Check your system clock" "$LINENO" 5 fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } test "$program_prefix" != NONE && program_transform_name="s&^&$program_prefix&;$program_transform_name" # Use a double $ so make ignores it. test "$program_suffix" != NONE && program_transform_name="s&\$&$program_suffix&;$program_transform_name" # Double any \ or $. # By default was `s,x,x', remove it if useless. ac_script='s/[\\$]/&&/g;s/;s,x,x,$//' program_transform_name=`$as_echo "$program_transform_name" | sed "$ac_script"` # expand $ac_aux_dir to an absolute path am_aux_dir=`cd $ac_aux_dir && pwd` if test x"${MISSING+set}" != xset; then case $am_aux_dir in *\ * | *\ *) MISSING="\${SHELL} \"$am_aux_dir/missing\"" ;; *) MISSING="\${SHELL} $am_aux_dir/missing" ;; esac fi # Use eval to expand $SHELL if eval "$MISSING --run true"; then am_missing_run="$MISSING --run " else am_missing_run= { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: \`missing' script is too old or missing" >&5 $as_echo "$as_me: WARNING: \`missing' script is too old or missing" >&2;} fi if test x"${install_sh}" != xset; then case $am_aux_dir in *\ * | *\ *) install_sh="\${SHELL} '$am_aux_dir/install-sh'" ;; *) install_sh="\${SHELL} $am_aux_dir/install-sh" esac fi # Installed binaries are usually stripped using `strip' when the user # run `make install-strip'. However `strip' might not be the right # tool to use in cross-compilation environments, therefore Automake # will honor the `STRIP' environment variable to overrule this program. if test "$cross_compiling" != no; then if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. set dummy ${ac_tool_prefix}strip; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_STRIP+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$STRIP"; then ac_cv_prog_STRIP="$STRIP" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_STRIP="${ac_tool_prefix}strip" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi STRIP=$ac_cv_prog_STRIP if test -n "$STRIP"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $STRIP" >&5 $as_echo "$STRIP" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$ac_cv_prog_STRIP"; then ac_ct_STRIP=$STRIP # Extract the first word of "strip", so it can be a program name with args. set dummy strip; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_STRIP+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_STRIP"; then ac_cv_prog_ac_ct_STRIP="$ac_ct_STRIP" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_STRIP="strip" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_STRIP=$ac_cv_prog_ac_ct_STRIP if test -n "$ac_ct_STRIP"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_STRIP" >&5 $as_echo "$ac_ct_STRIP" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$ac_ct_STRIP" = x; then STRIP=":" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac STRIP=$ac_ct_STRIP fi else STRIP="$ac_cv_prog_STRIP" fi fi INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s" { $as_echo "$as_me:${as_lineno-$LINENO}: checking for a thread-safe mkdir -p" >&5 $as_echo_n "checking for a thread-safe mkdir -p... " >&6; } if test -z "$MKDIR_P"; then if ${ac_cv_path_mkdir+:} false; then : $as_echo_n "(cached) " >&6 else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH$PATH_SEPARATOR/opt/sfw/bin do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in mkdir gmkdir; do for ac_exec_ext in '' $ac_executable_extensions; do { test -f "$as_dir/$ac_prog$ac_exec_ext" && $as_test_x "$as_dir/$ac_prog$ac_exec_ext"; } || continue case `"$as_dir/$ac_prog$ac_exec_ext" --version 2>&1` in #( 'mkdir (GNU coreutils) '* | \ 'mkdir (coreutils) '* | \ 'mkdir (fileutils) '4.1*) ac_cv_path_mkdir=$as_dir/$ac_prog$ac_exec_ext break 3;; esac done done done IFS=$as_save_IFS fi test -d ./--version && rmdir ./--version if test "${ac_cv_path_mkdir+set}" = set; then MKDIR_P="$ac_cv_path_mkdir -p" else # As a last resort, use the slow shell script. Don't cache a # value for MKDIR_P within a source directory, because that will # break other packages using the cache if that directory is # removed, or if the value is a relative name. MKDIR_P="$ac_install_sh -d" fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MKDIR_P" >&5 $as_echo "$MKDIR_P" >&6; } mkdir_p="$MKDIR_P" case $mkdir_p in [\\/$]* | ?:[\\/]*) ;; */*) mkdir_p="\$(top_builddir)/$mkdir_p" ;; esac for ac_prog in gawk mawk nawk awk do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_AWK+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$AWK"; then ac_cv_prog_AWK="$AWK" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_AWK="$ac_prog" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi AWK=$ac_cv_prog_AWK if test -n "$AWK"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AWK" >&5 $as_echo "$AWK" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi test -n "$AWK" && break done { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ${MAKE-make} sets \$(MAKE)" >&5 $as_echo_n "checking whether ${MAKE-make} sets \$(MAKE)... " >&6; } set x ${MAKE-make} ac_make=`$as_echo "$2" | sed 's/+/p/g; s/[^a-zA-Z0-9_]/_/g'` if eval \${ac_cv_prog_make_${ac_make}_set+:} false; then : $as_echo_n "(cached) " >&6 else cat >conftest.make <<\_ACEOF SHELL = /bin/sh all: @echo '@@@%%%=$(MAKE)=@@@%%%' _ACEOF # GNU make sometimes prints "make[1]: Entering ...", which would confuse us. case `${MAKE-make} -f conftest.make 2>/dev/null` in *@@@%%%=?*=@@@%%%*) eval ac_cv_prog_make_${ac_make}_set=yes;; *) eval ac_cv_prog_make_${ac_make}_set=no;; esac rm -f conftest.make fi if eval test \$ac_cv_prog_make_${ac_make}_set = yes; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } SET_MAKE= else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } SET_MAKE="MAKE=${MAKE-make}" fi rm -rf .tst 2>/dev/null mkdir .tst 2>/dev/null if test -d .tst; then am__leading_dot=. else am__leading_dot=_ fi rmdir .tst 2>/dev/null if test "`cd $srcdir && pwd`" != "`pwd`"; then # Use -I$(srcdir) only when $(srcdir) != ., so that make's output # is not polluted with repeated "-I." am__isrc=' -I$(srcdir)' # test to see if srcdir already configured if test -f $srcdir/config.status; then as_fn_error $? "source directory already configured; run \"make distclean\" there first" "$LINENO" 5 fi fi # test whether we have cygpath if test -z "$CYGPATH_W"; then if (cygpath --version) >/dev/null 2>/dev/null; then CYGPATH_W='cygpath -w' else CYGPATH_W=echo fi fi # Define the identity of the package. PACKAGE=$PACKAGE VERSION=$VERSION cat >>confdefs.h <<_ACEOF #define PACKAGE "$PACKAGE" _ACEOF cat >>confdefs.h <<_ACEOF #define VERSION "$VERSION" _ACEOF # Some tools Automake needs. ACLOCAL=${ACLOCAL-"${am_missing_run}aclocal-${am__api_version}"} AUTOCONF=${AUTOCONF-"${am_missing_run}autoconf"} AUTOMAKE=${AUTOMAKE-"${am_missing_run}automake-${am__api_version}"} AUTOHEADER=${AUTOHEADER-"${am_missing_run}autoheader"} MAKEINFO=${MAKEINFO-"${am_missing_run}makeinfo"} # We need awk for the "check" target. The system "awk" is bad on # some platforms. # Always define AMTAR for backward compatibility. AMTAR=${AMTAR-"${am_missing_run}tar"} am__tar='${AMTAR} chof - "$$tardir"'; am__untar='${AMTAR} xf -' ACLOCAL_AMFLAGS="-I m4" ac_config_headers="$ac_config_headers config.h" ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}gcc", so it can be a program name with args. set dummy ${ac_tool_prefix}gcc; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_CC+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$CC"; then ac_cv_prog_CC="$CC" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_CC="${ac_tool_prefix}gcc" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi CC=$ac_cv_prog_CC if test -n "$CC"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 $as_echo "$CC" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$ac_cv_prog_CC"; then ac_ct_CC=$CC # Extract the first word of "gcc", so it can be a program name with args. set dummy gcc; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_CC+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_CC"; then ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_CC="gcc" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_CC=$ac_cv_prog_ac_ct_CC if test -n "$ac_ct_CC"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 $as_echo "$ac_ct_CC" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$ac_ct_CC" = x; then CC="" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac CC=$ac_ct_CC fi else CC="$ac_cv_prog_CC" fi if test -z "$CC"; then if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}cc", so it can be a program name with args. set dummy ${ac_tool_prefix}cc; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_CC+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$CC"; then ac_cv_prog_CC="$CC" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_CC="${ac_tool_prefix}cc" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi CC=$ac_cv_prog_CC if test -n "$CC"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 $as_echo "$CC" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi fi if test -z "$CC"; then # Extract the first word of "cc", so it can be a program name with args. set dummy cc; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_CC+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$CC"; then ac_cv_prog_CC="$CC" # Let the user override the test. else ac_prog_rejected=no as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then if test "$as_dir/$ac_word$ac_exec_ext" = "/usr/ucb/cc"; then ac_prog_rejected=yes continue fi ac_cv_prog_CC="cc" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS if test $ac_prog_rejected = yes; then # We found a bogon in the path, so make sure we never use it. set dummy $ac_cv_prog_CC shift if test $# != 0; then # We chose a different compiler from the bogus one. # However, it has the same basename, so the bogon will be chosen # first if we set CC to just the basename; use the full file name. shift ac_cv_prog_CC="$as_dir/$ac_word${1+' '}$@" fi fi fi fi CC=$ac_cv_prog_CC if test -n "$CC"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 $as_echo "$CC" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$CC"; then if test -n "$ac_tool_prefix"; then for ac_prog in cl.exe do # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. set dummy $ac_tool_prefix$ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_CC+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$CC"; then ac_cv_prog_CC="$CC" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_CC="$ac_tool_prefix$ac_prog" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi CC=$ac_cv_prog_CC if test -n "$CC"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CC" >&5 $as_echo "$CC" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi test -n "$CC" && break done fi if test -z "$CC"; then ac_ct_CC=$CC for ac_prog in cl.exe do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_CC+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_CC"; then ac_cv_prog_ac_ct_CC="$ac_ct_CC" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_CC="$ac_prog" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_CC=$ac_cv_prog_ac_ct_CC if test -n "$ac_ct_CC"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_CC" >&5 $as_echo "$ac_ct_CC" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi test -n "$ac_ct_CC" && break done if test "x$ac_ct_CC" = x; then CC="" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac CC=$ac_ct_CC fi fi fi test -z "$CC" && { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error $? "no acceptable C compiler found in \$PATH See \`config.log' for more details" "$LINENO" 5; } # Provide some information about the compiler. $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler version" >&5 set X $ac_compile ac_compiler=$2 for ac_option in --version -v -V -qversion; do { { ac_try="$ac_compiler $ac_option >&5" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" $as_echo "$ac_try_echo"; } >&5 (eval "$ac_compiler $ac_option >&5") 2>conftest.err ac_status=$? if test -s conftest.err; then sed '10a\ ... rest of stderr output deleted ... 10q' conftest.err >conftest.er1 cat conftest.er1 >&5 fi rm -f conftest.er1 conftest.err $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } done cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF ac_clean_files_save=$ac_clean_files ac_clean_files="$ac_clean_files a.out a.out.dSYM a.exe b.out" # Try to create an executable without -o first, disregard a.out. # It will help us diagnose broken compilers, and finding out an intuition # of exeext. { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler works" >&5 $as_echo_n "checking whether the C compiler works... " >&6; } ac_link_default=`$as_echo "$ac_link" | sed 's/ -o *conftest[^ ]*//'` # The possible output files: ac_files="a.out conftest.exe conftest a.exe a_out.exe b.out conftest.*" ac_rmfiles= for ac_file in $ac_files do case $ac_file in *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; * ) ac_rmfiles="$ac_rmfiles $ac_file";; esac done rm -f $ac_rmfiles if { { ac_try="$ac_link_default" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" $as_echo "$ac_try_echo"; } >&5 (eval "$ac_link_default") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then : # Autoconf-2.13 could set the ac_cv_exeext variable to `no'. # So ignore a value of `no', otherwise this would lead to `EXEEXT = no' # in a Makefile. We should not override ac_cv_exeext if it was cached, # so that the user can short-circuit this test for compilers unknown to # Autoconf. for ac_file in $ac_files '' do test -f "$ac_file" || continue case $ac_file in *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; [ab].out ) # We found the default executable, but exeext='' is most # certainly right. break;; *.* ) if test "${ac_cv_exeext+set}" = set && test "$ac_cv_exeext" != no; then :; else ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` fi # We set ac_cv_exeext here because the later test for it is not # safe: cross compilers may not add the suffix if given an `-o' # argument, so we may need to know it at that point already. # Even if this section looks crufty: it has the advantage of # actually working. break;; * ) break;; esac done test "$ac_cv_exeext" = no && ac_cv_exeext= else ac_file='' fi if test -z "$ac_file"; then : { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } $as_echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error 77 "C compiler cannot create executables See \`config.log' for more details" "$LINENO" 5; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } fi { $as_echo "$as_me:${as_lineno-$LINENO}: checking for C compiler default output file name" >&5 $as_echo_n "checking for C compiler default output file name... " >&6; } { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_file" >&5 $as_echo "$ac_file" >&6; } ac_exeext=$ac_cv_exeext rm -f -r a.out a.out.dSYM a.exe conftest$ac_cv_exeext b.out ac_clean_files=$ac_clean_files_save { $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of executables" >&5 $as_echo_n "checking for suffix of executables... " >&6; } if { { ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" $as_echo "$ac_try_echo"; } >&5 (eval "$ac_link") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then : # If both `conftest.exe' and `conftest' are `present' (well, observable) # catch `conftest.exe'. For instance with Cygwin, `ls conftest' will # work properly (i.e., refer to `conftest.exe'), while it won't with # `rm'. for ac_file in conftest.exe conftest conftest.*; do test -f "$ac_file" || continue case $ac_file in *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM | *.o | *.obj ) ;; *.* ) ac_cv_exeext=`expr "$ac_file" : '[^.]*\(\..*\)'` break;; * ) break;; esac done else { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error $? "cannot compute suffix of executables: cannot compile and link See \`config.log' for more details" "$LINENO" 5; } fi rm -f conftest conftest$ac_cv_exeext { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_exeext" >&5 $as_echo "$ac_cv_exeext" >&6; } rm -f conftest.$ac_ext EXEEXT=$ac_cv_exeext ac_exeext=$EXEEXT cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include int main () { FILE *f = fopen ("conftest.out", "w"); return ferror (f) || fclose (f) != 0; ; return 0; } _ACEOF ac_clean_files="$ac_clean_files conftest.out" # Check that the compiler produces executables we can run. If not, either # the compiler is broken, or we cross compile. { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are cross compiling" >&5 $as_echo_n "checking whether we are cross compiling... " >&6; } if test "$cross_compiling" != yes; then { { ac_try="$ac_link" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" $as_echo "$ac_try_echo"; } >&5 (eval "$ac_link") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } if { ac_try='./conftest$ac_cv_exeext' { { case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" $as_echo "$ac_try_echo"; } >&5 (eval "$ac_try") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; }; then cross_compiling=no else if test "$cross_compiling" = maybe; then cross_compiling=yes else { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error $? "cannot run C compiled programs. If you meant to cross compile, use \`--host'. See \`config.log' for more details" "$LINENO" 5; } fi fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $cross_compiling" >&5 $as_echo "$cross_compiling" >&6; } rm -f conftest.$ac_ext conftest$ac_cv_exeext conftest.out ac_clean_files=$ac_clean_files_save { $as_echo "$as_me:${as_lineno-$LINENO}: checking for suffix of object files" >&5 $as_echo_n "checking for suffix of object files... " >&6; } if ${ac_cv_objext+:} false; then : $as_echo_n "(cached) " >&6 else cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF rm -f conftest.o conftest.obj if { { ac_try="$ac_compile" case "(($ac_try" in *\"* | *\`* | *\\*) ac_try_echo=\$ac_try;; *) ac_try_echo=$ac_try;; esac eval ac_try_echo="\"\$as_me:${as_lineno-$LINENO}: $ac_try_echo\"" $as_echo "$ac_try_echo"; } >&5 (eval "$ac_compile") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then : for ac_file in conftest.o conftest.obj conftest.*; do test -f "$ac_file" || continue; case $ac_file in *.$ac_ext | *.xcoff | *.tds | *.d | *.pdb | *.xSYM | *.bb | *.bbg | *.map | *.inf | *.dSYM ) ;; *) ac_cv_objext=`expr "$ac_file" : '.*\.\(.*\)'` break;; esac done else $as_echo "$as_me: failed program was:" >&5 sed 's/^/| /' conftest.$ac_ext >&5 { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error $? "cannot compute suffix of object files: cannot compile See \`config.log' for more details" "$LINENO" 5; } fi rm -f conftest.$ac_cv_objext conftest.$ac_ext fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_objext" >&5 $as_echo "$ac_cv_objext" >&6; } OBJEXT=$ac_cv_objext ac_objext=$OBJEXT { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether we are using the GNU C compiler" >&5 $as_echo_n "checking whether we are using the GNU C compiler... " >&6; } if ${ac_cv_c_compiler_gnu+:} false; then : $as_echo_n "(cached) " >&6 else cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { #ifndef __GNUC__ choke me #endif ; return 0; } _ACEOF if ac_fn_c_try_compile "$LINENO"; then : ac_compiler_gnu=yes else ac_compiler_gnu=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ac_cv_c_compiler_gnu=$ac_compiler_gnu fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_c_compiler_gnu" >&5 $as_echo "$ac_cv_c_compiler_gnu" >&6; } if test $ac_compiler_gnu = yes; then GCC=yes else GCC= fi ac_test_CFLAGS=${CFLAGS+set} ac_save_CFLAGS=$CFLAGS { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether $CC accepts -g" >&5 $as_echo_n "checking whether $CC accepts -g... " >&6; } if ${ac_cv_prog_cc_g+:} false; then : $as_echo_n "(cached) " >&6 else ac_save_c_werror_flag=$ac_c_werror_flag ac_c_werror_flag=yes ac_cv_prog_cc_g=no CFLAGS="-g" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_compile "$LINENO"; then : ac_cv_prog_cc_g=yes else CFLAGS="" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_compile "$LINENO"; then : else ac_c_werror_flag=$ac_save_c_werror_flag CFLAGS="-g" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_compile "$LINENO"; then : ac_cv_prog_cc_g=yes fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext ac_c_werror_flag=$ac_save_c_werror_flag fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_g" >&5 $as_echo "$ac_cv_prog_cc_g" >&6; } if test "$ac_test_CFLAGS" = set; then CFLAGS=$ac_save_CFLAGS elif test $ac_cv_prog_cc_g = yes; then if test "$GCC" = yes; then CFLAGS="-g -O2" else CFLAGS="-g" fi else if test "$GCC" = yes; then CFLAGS="-O2" else CFLAGS= fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $CC option to accept ISO C89" >&5 $as_echo_n "checking for $CC option to accept ISO C89... " >&6; } if ${ac_cv_prog_cc_c89+:} false; then : $as_echo_n "(cached) " >&6 else ac_cv_prog_cc_c89=no ac_save_CC=$CC cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include #include #include #include /* Most of the following tests are stolen from RCS 5.7's src/conf.sh. */ struct buf { int x; }; FILE * (*rcsopen) (struct buf *, struct stat *, int); static char *e (p, i) char **p; int i; { return p[i]; } static char *f (char * (*g) (char **, int), char **p, ...) { char *s; va_list v; va_start (v,p); s = g (p, va_arg (v,int)); va_end (v); return s; } /* OSF 4.0 Compaq cc is some sort of almost-ANSI by default. It has function prototypes and stuff, but not '\xHH' hex character constants. These don't provoke an error unfortunately, instead are silently treated as 'x'. The following induces an error, until -std is added to get proper ANSI mode. Curiously '\x00'!='x' always comes out true, for an array size at least. It's necessary to write '\x00'==0 to get something that's true only with -std. */ int osf4_cc_array ['\x00' == 0 ? 1 : -1]; /* IBM C 6 for AIX is almost-ANSI by default, but it replaces macro parameters inside strings and character constants. */ #define FOO(x) 'x' int xlc6_cc_array[FOO(a) == 'x' ? 1 : -1]; int test (int i, double x); struct s1 {int (*f) (int a);}; struct s2 {int (*f) (double a);}; int pairnames (int, char **, FILE *(*)(struct buf *, struct stat *, int), int, int); int argc; char **argv; int main () { return f (e, argv, 0) != argv[0] || f (e, argv, 1) != argv[1]; ; return 0; } _ACEOF for ac_arg in '' -qlanglvl=extc89 -qlanglvl=ansi -std \ -Ae "-Aa -D_HPUX_SOURCE" "-Xc -D__EXTENSIONS__" do CC="$ac_save_CC $ac_arg" if ac_fn_c_try_compile "$LINENO"; then : ac_cv_prog_cc_c89=$ac_arg fi rm -f core conftest.err conftest.$ac_objext test "x$ac_cv_prog_cc_c89" != "xno" && break done rm -f conftest.$ac_ext CC=$ac_save_CC fi # AC_CACHE_VAL case "x$ac_cv_prog_cc_c89" in x) { $as_echo "$as_me:${as_lineno-$LINENO}: result: none needed" >&5 $as_echo "none needed" >&6; } ;; xno) { $as_echo "$as_me:${as_lineno-$LINENO}: result: unsupported" >&5 $as_echo "unsupported" >&6; } ;; *) CC="$CC $ac_cv_prog_cc_c89" { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_prog_cc_c89" >&5 $as_echo "$ac_cv_prog_cc_c89" >&6; } ;; esac if test "x$ac_cv_prog_cc_c89" != xno; then : fi ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu DEPDIR="${am__leading_dot}deps" ac_config_commands="$ac_config_commands depfiles" am_make=${MAKE-make} cat > confinc << 'END' am__doit: @echo this is the am__doit target .PHONY: am__doit END # If we don't find an include directive, just comment out the code. { $as_echo "$as_me:${as_lineno-$LINENO}: checking for style of include used by $am_make" >&5 $as_echo_n "checking for style of include used by $am_make... " >&6; } am__include="#" am__quote= _am_result=none # First try GNU make style include. echo "include confinc" > confmf # Ignore all kinds of additional output from `make'. case `$am_make -s -f confmf 2> /dev/null` in #( *the\ am__doit\ target*) am__include=include am__quote= _am_result=GNU ;; esac # Now try BSD make style include. if test "$am__include" = "#"; then echo '.include "confinc"' > confmf case `$am_make -s -f confmf 2> /dev/null` in #( *the\ am__doit\ target*) am__include=.include am__quote="\"" _am_result=BSD ;; esac fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $_am_result" >&5 $as_echo "$_am_result" >&6; } rm -f confinc confmf # Check whether --enable-dependency-tracking was given. if test "${enable_dependency_tracking+set}" = set; then : enableval=$enable_dependency_tracking; fi if test "x$enable_dependency_tracking" != xno; then am_depcomp="$ac_aux_dir/depcomp" AMDEPBACKSLASH='\' fi if test "x$enable_dependency_tracking" != xno; then AMDEP_TRUE= AMDEP_FALSE='#' else AMDEP_TRUE='#' AMDEP_FALSE= fi depcc="$CC" am_compiler_list= { $as_echo "$as_me:${as_lineno-$LINENO}: checking dependency style of $depcc" >&5 $as_echo_n "checking dependency style of $depcc... " >&6; } if ${am_cv_CC_dependencies_compiler_type+:} false; then : $as_echo_n "(cached) " >&6 else if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then # We make a subdir and do the tests there. Otherwise we can end up # making bogus files that we don't know about and never remove. For # instance it was reported that on HP-UX the gcc test will end up # making a dummy file named `D' -- because `-MD' means `put the output # in D'. mkdir conftest.dir # Copy depcomp to subdir because otherwise we won't find it if we're # using a relative directory. cp "$am_depcomp" conftest.dir cd conftest.dir # We will build objects and dependencies in a subdirectory because # it helps to detect inapplicable dependency modes. For instance # both Tru64's cc and ICC support -MD to output dependencies as a # side effect of compilation, but ICC will put the dependencies in # the current directory while Tru64 will put them in the object # directory. mkdir sub am_cv_CC_dependencies_compiler_type=none if test "$am_compiler_list" = ""; then am_compiler_list=`sed -n 's/^#*\([a-zA-Z0-9]*\))$/\1/p' < ./depcomp` fi am__universal=false case " $depcc " in #( *\ -arch\ *\ -arch\ *) am__universal=true ;; esac for depmode in $am_compiler_list; do # Setup a source with many dependencies, because some compilers # like to wrap large dependency lists on column 80 (with \), and # we should not choose a depcomp mode which is confused by this. # # We need to recreate these files for each test, as the compiler may # overwrite some of them when testing with obscure command lines. # This happens at least with the AIX C compiler. : > sub/conftest.c for i in 1 2 3 4 5 6; do echo '#include "conftst'$i'.h"' >> sub/conftest.c # Using `: > sub/conftst$i.h' creates only sub/conftst1.h with # Solaris 8's {/usr,}/bin/sh. touch sub/conftst$i.h done echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf # We check with `-c' and `-o' for the sake of the "dashmstdout" # mode. It turns out that the SunPro C++ compiler does not properly # handle `-M -o', and we need to detect this. Also, some Intel # versions had trouble with output in subdirs am__obj=sub/conftest.${OBJEXT-o} am__minus_obj="-o $am__obj" case $depmode in gcc) # This depmode causes a compiler race in universal mode. test "$am__universal" = false || continue ;; nosideeffect) # after this tag, mechanisms are not by side-effect, so they'll # only be used when explicitly requested if test "x$enable_dependency_tracking" = xyes; then continue else break fi ;; msvisualcpp | msvcmsys) # This compiler won't grok `-c -o', but also, the minuso test has # not run yet. These depmodes are late enough in the game, and # so weak that their functioning should not be impacted. am__obj=conftest.${OBJEXT-o} am__minus_obj= ;; none) break ;; esac if depmode=$depmode \ source=sub/conftest.c object=$am__obj \ depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \ >/dev/null 2>conftest.err && grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 && grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && grep $am__obj sub/conftest.Po > /dev/null 2>&1 && ${MAKE-make} -s -f confmf > /dev/null 2>&1; then # icc doesn't choke on unknown options, it will just issue warnings # or remarks (even with -Werror). So we grep stderr for any message # that says an option was ignored or not supported. # When given -MP, icc 7.0 and 7.1 complain thusly: # icc: Command line warning: ignoring option '-M'; no argument required # The diagnosis changed in icc 8.0: # icc: Command line remark: option '-MP' not supported if (grep 'ignoring option' conftest.err || grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else am_cv_CC_dependencies_compiler_type=$depmode break fi fi done cd .. rm -rf conftest.dir else am_cv_CC_dependencies_compiler_type=none fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $am_cv_CC_dependencies_compiler_type" >&5 $as_echo "$am_cv_CC_dependencies_compiler_type" >&6; } CCDEPMODE=depmode=$am_cv_CC_dependencies_compiler_type if test "x$enable_dependency_tracking" != xno \ && test "$am_cv_CC_dependencies_compiler_type" = gcc3; then am__fastdepCC_TRUE= am__fastdepCC_FALSE='#' else am__fastdepCC_TRUE='#' am__fastdepCC_FALSE= fi case `pwd` in *\ * | *\ *) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: Libtool does not cope well with whitespace in \`pwd\`" >&5 $as_echo "$as_me: WARNING: Libtool does not cope well with whitespace in \`pwd\`" >&2;} ;; esac macro_version='2.4' macro_revision='1.3293' ltmain="$ac_aux_dir/ltmain.sh" # Make sure we can run config.sub. $SHELL "$ac_aux_dir/config.sub" sun4 >/dev/null 2>&1 || as_fn_error $? "cannot run $SHELL $ac_aux_dir/config.sub" "$LINENO" 5 { $as_echo "$as_me:${as_lineno-$LINENO}: checking build system type" >&5 $as_echo_n "checking build system type... " >&6; } if ${ac_cv_build+:} false; then : $as_echo_n "(cached) " >&6 else ac_build_alias=$build_alias test "x$ac_build_alias" = x && ac_build_alias=`$SHELL "$ac_aux_dir/config.guess"` test "x$ac_build_alias" = x && as_fn_error $? "cannot guess build type; you must specify one" "$LINENO" 5 ac_cv_build=`$SHELL "$ac_aux_dir/config.sub" $ac_build_alias` || as_fn_error $? "$SHELL $ac_aux_dir/config.sub $ac_build_alias failed" "$LINENO" 5 fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_build" >&5 $as_echo "$ac_cv_build" >&6; } case $ac_cv_build in *-*-*) ;; *) as_fn_error $? "invalid value of canonical build" "$LINENO" 5;; esac build=$ac_cv_build ac_save_IFS=$IFS; IFS='-' set x $ac_cv_build shift build_cpu=$1 build_vendor=$2 shift; shift # Remember, the first character of IFS is used to create $*, # except with old shells: build_os=$* IFS=$ac_save_IFS case $build_os in *\ *) build_os=`echo "$build_os" | sed 's/ /-/g'`;; esac { $as_echo "$as_me:${as_lineno-$LINENO}: checking host system type" >&5 $as_echo_n "checking host system type... " >&6; } if ${ac_cv_host+:} false; then : $as_echo_n "(cached) " >&6 else if test "x$host_alias" = x; then ac_cv_host=$ac_cv_build else ac_cv_host=`$SHELL "$ac_aux_dir/config.sub" $host_alias` || as_fn_error $? "$SHELL $ac_aux_dir/config.sub $host_alias failed" "$LINENO" 5 fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_host" >&5 $as_echo "$ac_cv_host" >&6; } case $ac_cv_host in *-*-*) ;; *) as_fn_error $? "invalid value of canonical host" "$LINENO" 5;; esac host=$ac_cv_host ac_save_IFS=$IFS; IFS='-' set x $ac_cv_host shift host_cpu=$1 host_vendor=$2 shift; shift # Remember, the first character of IFS is used to create $*, # except with old shells: host_os=$* IFS=$ac_save_IFS case $host_os in *\ *) host_os=`echo "$host_os" | sed 's/ /-/g'`;; esac # Backslashify metacharacters that are still active within # double-quoted strings. sed_quote_subst='s/\(["`$\\]\)/\\\1/g' # Same as above, but do not quote variable references. double_quote_subst='s/\(["`\\]\)/\\\1/g' # Sed substitution to delay expansion of an escaped shell variable in a # double_quote_subst'ed string. delay_variable_subst='s/\\\\\\\\\\\$/\\\\\\$/g' # Sed substitution to delay expansion of an escaped single quote. delay_single_quote_subst='s/'\''/'\'\\\\\\\'\''/g' # Sed substitution to avoid accidental globbing in evaled expressions no_glob_subst='s/\*/\\\*/g' ECHO='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO$ECHO { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to print strings" >&5 $as_echo_n "checking how to print strings... " >&6; } # Test print first, because it will be a builtin if present. if test "X`( print -r -- -n ) 2>/dev/null`" = X-n && \ test "X`print -r -- $ECHO 2>/dev/null`" = "X$ECHO"; then ECHO='print -r --' elif test "X`printf %s $ECHO 2>/dev/null`" = "X$ECHO"; then ECHO='printf %s\n' else # Use this function as a fallback that always works. func_fallback_echo () { eval 'cat <<_LTECHO_EOF $1 _LTECHO_EOF' } ECHO='func_fallback_echo' fi # func_echo_all arg... # Invoke $ECHO with all args, space-separated. func_echo_all () { $ECHO "" } case "$ECHO" in printf*) { $as_echo "$as_me:${as_lineno-$LINENO}: result: printf" >&5 $as_echo "printf" >&6; } ;; print*) { $as_echo "$as_me:${as_lineno-$LINENO}: result: print -r" >&5 $as_echo "print -r" >&6; } ;; *) { $as_echo "$as_me:${as_lineno-$LINENO}: result: cat" >&5 $as_echo "cat" >&6; } ;; esac { $as_echo "$as_me:${as_lineno-$LINENO}: checking for a sed that does not truncate output" >&5 $as_echo_n "checking for a sed that does not truncate output... " >&6; } if ${ac_cv_path_SED+:} false; then : $as_echo_n "(cached) " >&6 else ac_script=s/aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa/bbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbbb/ for ac_i in 1 2 3 4 5 6 7; do ac_script="$ac_script$as_nl$ac_script" done echo "$ac_script" 2>/dev/null | sed 99q >conftest.sed { ac_script=; unset ac_script;} if test -z "$SED"; then ac_path_SED_found=false # Loop through the user's path and test for each of PROGNAME-LIST as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in sed gsed; do for ac_exec_ext in '' $ac_executable_extensions; do ac_path_SED="$as_dir/$ac_prog$ac_exec_ext" { test -f "$ac_path_SED" && $as_test_x "$ac_path_SED"; } || continue # Check for GNU ac_path_SED and select it if it is found. # Check for GNU $ac_path_SED case `"$ac_path_SED" --version 2>&1` in *GNU*) ac_cv_path_SED="$ac_path_SED" ac_path_SED_found=:;; *) ac_count=0 $as_echo_n 0123456789 >"conftest.in" while : do cat "conftest.in" "conftest.in" >"conftest.tmp" mv "conftest.tmp" "conftest.in" cp "conftest.in" "conftest.nl" $as_echo '' >> "conftest.nl" "$ac_path_SED" -f conftest.sed < "conftest.nl" >"conftest.out" 2>/dev/null || break diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break as_fn_arith $ac_count + 1 && ac_count=$as_val if test $ac_count -gt ${ac_path_SED_max-0}; then # Best one so far, save it but keep looking for a better one ac_cv_path_SED="$ac_path_SED" ac_path_SED_max=$ac_count fi # 10*(2^10) chars as input seems more than enough test $ac_count -gt 10 && break done rm -f conftest.in conftest.tmp conftest.nl conftest.out;; esac $ac_path_SED_found && break 3 done done done IFS=$as_save_IFS if test -z "$ac_cv_path_SED"; then as_fn_error $? "no acceptable sed could be found in \$PATH" "$LINENO" 5 fi else ac_cv_path_SED=$SED fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_SED" >&5 $as_echo "$ac_cv_path_SED" >&6; } SED="$ac_cv_path_SED" rm -f conftest.sed test -z "$SED" && SED=sed Xsed="$SED -e 1s/^X//" { $as_echo "$as_me:${as_lineno-$LINENO}: checking for grep that handles long lines and -e" >&5 $as_echo_n "checking for grep that handles long lines and -e... " >&6; } if ${ac_cv_path_GREP+:} false; then : $as_echo_n "(cached) " >&6 else if test -z "$GREP"; then ac_path_GREP_found=false # Loop through the user's path and test for each of PROGNAME-LIST as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in grep ggrep; do for ac_exec_ext in '' $ac_executable_extensions; do ac_path_GREP="$as_dir/$ac_prog$ac_exec_ext" { test -f "$ac_path_GREP" && $as_test_x "$ac_path_GREP"; } || continue # Check for GNU ac_path_GREP and select it if it is found. # Check for GNU $ac_path_GREP case `"$ac_path_GREP" --version 2>&1` in *GNU*) ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_found=:;; *) ac_count=0 $as_echo_n 0123456789 >"conftest.in" while : do cat "conftest.in" "conftest.in" >"conftest.tmp" mv "conftest.tmp" "conftest.in" cp "conftest.in" "conftest.nl" $as_echo 'GREP' >> "conftest.nl" "$ac_path_GREP" -e 'GREP$' -e '-(cannot match)-' < "conftest.nl" >"conftest.out" 2>/dev/null || break diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break as_fn_arith $ac_count + 1 && ac_count=$as_val if test $ac_count -gt ${ac_path_GREP_max-0}; then # Best one so far, save it but keep looking for a better one ac_cv_path_GREP="$ac_path_GREP" ac_path_GREP_max=$ac_count fi # 10*(2^10) chars as input seems more than enough test $ac_count -gt 10 && break done rm -f conftest.in conftest.tmp conftest.nl conftest.out;; esac $ac_path_GREP_found && break 3 done done done IFS=$as_save_IFS if test -z "$ac_cv_path_GREP"; then as_fn_error $? "no acceptable grep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 fi else ac_cv_path_GREP=$GREP fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_GREP" >&5 $as_echo "$ac_cv_path_GREP" >&6; } GREP="$ac_cv_path_GREP" { $as_echo "$as_me:${as_lineno-$LINENO}: checking for egrep" >&5 $as_echo_n "checking for egrep... " >&6; } if ${ac_cv_path_EGREP+:} false; then : $as_echo_n "(cached) " >&6 else if echo a | $GREP -E '(a|b)' >/dev/null 2>&1 then ac_cv_path_EGREP="$GREP -E" else if test -z "$EGREP"; then ac_path_EGREP_found=false # Loop through the user's path and test for each of PROGNAME-LIST as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in egrep; do for ac_exec_ext in '' $ac_executable_extensions; do ac_path_EGREP="$as_dir/$ac_prog$ac_exec_ext" { test -f "$ac_path_EGREP" && $as_test_x "$ac_path_EGREP"; } || continue # Check for GNU ac_path_EGREP and select it if it is found. # Check for GNU $ac_path_EGREP case `"$ac_path_EGREP" --version 2>&1` in *GNU*) ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_found=:;; *) ac_count=0 $as_echo_n 0123456789 >"conftest.in" while : do cat "conftest.in" "conftest.in" >"conftest.tmp" mv "conftest.tmp" "conftest.in" cp "conftest.in" "conftest.nl" $as_echo 'EGREP' >> "conftest.nl" "$ac_path_EGREP" 'EGREP$' < "conftest.nl" >"conftest.out" 2>/dev/null || break diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break as_fn_arith $ac_count + 1 && ac_count=$as_val if test $ac_count -gt ${ac_path_EGREP_max-0}; then # Best one so far, save it but keep looking for a better one ac_cv_path_EGREP="$ac_path_EGREP" ac_path_EGREP_max=$ac_count fi # 10*(2^10) chars as input seems more than enough test $ac_count -gt 10 && break done rm -f conftest.in conftest.tmp conftest.nl conftest.out;; esac $ac_path_EGREP_found && break 3 done done done IFS=$as_save_IFS if test -z "$ac_cv_path_EGREP"; then as_fn_error $? "no acceptable egrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 fi else ac_cv_path_EGREP=$EGREP fi fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_EGREP" >&5 $as_echo "$ac_cv_path_EGREP" >&6; } EGREP="$ac_cv_path_EGREP" { $as_echo "$as_me:${as_lineno-$LINENO}: checking for fgrep" >&5 $as_echo_n "checking for fgrep... " >&6; } if ${ac_cv_path_FGREP+:} false; then : $as_echo_n "(cached) " >&6 else if echo 'ab*c' | $GREP -F 'ab*c' >/dev/null 2>&1 then ac_cv_path_FGREP="$GREP -F" else if test -z "$FGREP"; then ac_path_FGREP_found=false # Loop through the user's path and test for each of PROGNAME-LIST as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH$PATH_SEPARATOR/usr/xpg4/bin do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_prog in fgrep; do for ac_exec_ext in '' $ac_executable_extensions; do ac_path_FGREP="$as_dir/$ac_prog$ac_exec_ext" { test -f "$ac_path_FGREP" && $as_test_x "$ac_path_FGREP"; } || continue # Check for GNU ac_path_FGREP and select it if it is found. # Check for GNU $ac_path_FGREP case `"$ac_path_FGREP" --version 2>&1` in *GNU*) ac_cv_path_FGREP="$ac_path_FGREP" ac_path_FGREP_found=:;; *) ac_count=0 $as_echo_n 0123456789 >"conftest.in" while : do cat "conftest.in" "conftest.in" >"conftest.tmp" mv "conftest.tmp" "conftest.in" cp "conftest.in" "conftest.nl" $as_echo 'FGREP' >> "conftest.nl" "$ac_path_FGREP" FGREP < "conftest.nl" >"conftest.out" 2>/dev/null || break diff "conftest.out" "conftest.nl" >/dev/null 2>&1 || break as_fn_arith $ac_count + 1 && ac_count=$as_val if test $ac_count -gt ${ac_path_FGREP_max-0}; then # Best one so far, save it but keep looking for a better one ac_cv_path_FGREP="$ac_path_FGREP" ac_path_FGREP_max=$ac_count fi # 10*(2^10) chars as input seems more than enough test $ac_count -gt 10 && break done rm -f conftest.in conftest.tmp conftest.nl conftest.out;; esac $ac_path_FGREP_found && break 3 done done done IFS=$as_save_IFS if test -z "$ac_cv_path_FGREP"; then as_fn_error $? "no acceptable fgrep could be found in $PATH$PATH_SEPARATOR/usr/xpg4/bin" "$LINENO" 5 fi else ac_cv_path_FGREP=$FGREP fi fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_path_FGREP" >&5 $as_echo "$ac_cv_path_FGREP" >&6; } FGREP="$ac_cv_path_FGREP" test -z "$GREP" && GREP=grep # Check whether --with-gnu-ld was given. if test "${with_gnu_ld+set}" = set; then : withval=$with_gnu_ld; test "$withval" = no || with_gnu_ld=yes else with_gnu_ld=no fi ac_prog=ld if test "$GCC" = yes; then # Check if gcc -print-prog-name=ld gives a path. { $as_echo "$as_me:${as_lineno-$LINENO}: checking for ld used by $CC" >&5 $as_echo_n "checking for ld used by $CC... " >&6; } case $host in *-*-mingw*) # gcc leaves a trailing carriage return which upsets mingw ac_prog=`($CC -print-prog-name=ld) 2>&5 | tr -d '\015'` ;; *) ac_prog=`($CC -print-prog-name=ld) 2>&5` ;; esac case $ac_prog in # Accept absolute paths. [\\/]* | ?:[\\/]*) re_direlt='/[^/][^/]*/\.\./' # Canonicalize the pathname of ld ac_prog=`$ECHO "$ac_prog"| $SED 's%\\\\%/%g'` while $ECHO "$ac_prog" | $GREP "$re_direlt" > /dev/null 2>&1; do ac_prog=`$ECHO $ac_prog| $SED "s%$re_direlt%/%"` done test -z "$LD" && LD="$ac_prog" ;; "") # If it fails, then pretend we aren't using GCC. ac_prog=ld ;; *) # If it is relative, then search for the first ld in PATH. with_gnu_ld=unknown ;; esac elif test "$with_gnu_ld" = yes; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for GNU ld" >&5 $as_echo_n "checking for GNU ld... " >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: checking for non-GNU ld" >&5 $as_echo_n "checking for non-GNU ld... " >&6; } fi if ${lt_cv_path_LD+:} false; then : $as_echo_n "(cached) " >&6 else if test -z "$LD"; then lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR for ac_dir in $PATH; do IFS="$lt_save_ifs" test -z "$ac_dir" && ac_dir=. if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then lt_cv_path_LD="$ac_dir/$ac_prog" # Check to see if the program is GNU ld. I'd rather use --version, # but apparently some variants of GNU ld only accept -v. # Break only if it was the GNU/non-GNU ld that we prefer. case `"$lt_cv_path_LD" -v 2>&1 &5 $as_echo "$LD" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi test -z "$LD" && as_fn_error $? "no acceptable ld found in \$PATH" "$LINENO" 5 { $as_echo "$as_me:${as_lineno-$LINENO}: checking if the linker ($LD) is GNU ld" >&5 $as_echo_n "checking if the linker ($LD) is GNU ld... " >&6; } if ${lt_cv_prog_gnu_ld+:} false; then : $as_echo_n "(cached) " >&6 else # I'd rather use --version here, but apparently some GNU lds only accept -v. case `$LD -v 2>&1 &5 $as_echo "$lt_cv_prog_gnu_ld" >&6; } with_gnu_ld=$lt_cv_prog_gnu_ld { $as_echo "$as_me:${as_lineno-$LINENO}: checking for BSD- or MS-compatible name lister (nm)" >&5 $as_echo_n "checking for BSD- or MS-compatible name lister (nm)... " >&6; } if ${lt_cv_path_NM+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$NM"; then # Let the user override the test. lt_cv_path_NM="$NM" else lt_nm_to_check="${ac_tool_prefix}nm" if test -n "$ac_tool_prefix" && test "$build" = "$host"; then lt_nm_to_check="$lt_nm_to_check nm" fi for lt_tmp_nm in $lt_nm_to_check; do lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR for ac_dir in $PATH /usr/ccs/bin/elf /usr/ccs/bin /usr/ucb /bin; do IFS="$lt_save_ifs" test -z "$ac_dir" && ac_dir=. tmp_nm="$ac_dir/$lt_tmp_nm" if test -f "$tmp_nm" || test -f "$tmp_nm$ac_exeext" ; then # Check to see if the nm accepts a BSD-compat flag. # Adding the `sed 1q' prevents false positives on HP-UX, which says: # nm: unknown option "B" ignored # Tru64's nm complains that /dev/null is an invalid object file case `"$tmp_nm" -B /dev/null 2>&1 | sed '1q'` in */dev/null* | *'Invalid file or object type'*) lt_cv_path_NM="$tmp_nm -B" break ;; *) case `"$tmp_nm" -p /dev/null 2>&1 | sed '1q'` in */dev/null*) lt_cv_path_NM="$tmp_nm -p" break ;; *) lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but continue # so that we can try to find one that supports BSD flags ;; esac ;; esac fi done IFS="$lt_save_ifs" done : ${lt_cv_path_NM=no} fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_path_NM" >&5 $as_echo "$lt_cv_path_NM" >&6; } if test "$lt_cv_path_NM" != "no"; then NM="$lt_cv_path_NM" else # Didn't find any BSD compatible name lister, look for dumpbin. if test -n "$DUMPBIN"; then : # Let the user override the test. else if test -n "$ac_tool_prefix"; then for ac_prog in dumpbin "link -dump" do # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. set dummy $ac_tool_prefix$ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_DUMPBIN+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$DUMPBIN"; then ac_cv_prog_DUMPBIN="$DUMPBIN" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_DUMPBIN="$ac_tool_prefix$ac_prog" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi DUMPBIN=$ac_cv_prog_DUMPBIN if test -n "$DUMPBIN"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $DUMPBIN" >&5 $as_echo "$DUMPBIN" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi test -n "$DUMPBIN" && break done fi if test -z "$DUMPBIN"; then ac_ct_DUMPBIN=$DUMPBIN for ac_prog in dumpbin "link -dump" do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_DUMPBIN+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_DUMPBIN"; then ac_cv_prog_ac_ct_DUMPBIN="$ac_ct_DUMPBIN" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_DUMPBIN="$ac_prog" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_DUMPBIN=$ac_cv_prog_ac_ct_DUMPBIN if test -n "$ac_ct_DUMPBIN"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_DUMPBIN" >&5 $as_echo "$ac_ct_DUMPBIN" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi test -n "$ac_ct_DUMPBIN" && break done if test "x$ac_ct_DUMPBIN" = x; then DUMPBIN=":" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac DUMPBIN=$ac_ct_DUMPBIN fi fi case `$DUMPBIN -symbols /dev/null 2>&1 | sed '1q'` in *COFF*) DUMPBIN="$DUMPBIN -symbols" ;; *) DUMPBIN=: ;; esac fi if test "$DUMPBIN" != ":"; then NM="$DUMPBIN" fi fi test -z "$NM" && NM=nm { $as_echo "$as_me:${as_lineno-$LINENO}: checking the name lister ($NM) interface" >&5 $as_echo_n "checking the name lister ($NM) interface... " >&6; } if ${lt_cv_nm_interface+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_nm_interface="BSD nm" echo "int some_variable = 0;" > conftest.$ac_ext (eval echo "\"\$as_me:$LINENO: $ac_compile\"" >&5) (eval "$ac_compile" 2>conftest.err) cat conftest.err >&5 (eval echo "\"\$as_me:$LINENO: $NM \\\"conftest.$ac_objext\\\"\"" >&5) (eval "$NM \"conftest.$ac_objext\"" 2>conftest.err > conftest.out) cat conftest.err >&5 (eval echo "\"\$as_me:$LINENO: output\"" >&5) cat conftest.out >&5 if $GREP 'External.*some_variable' conftest.out > /dev/null; then lt_cv_nm_interface="MS dumpbin" fi rm -f conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_nm_interface" >&5 $as_echo "$lt_cv_nm_interface" >&6; } { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether ln -s works" >&5 $as_echo_n "checking whether ln -s works... " >&6; } LN_S=$as_ln_s if test "$LN_S" = "ln -s"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no, using $LN_S" >&5 $as_echo "no, using $LN_S" >&6; } fi # find the maximum length of command line arguments { $as_echo "$as_me:${as_lineno-$LINENO}: checking the maximum length of command line arguments" >&5 $as_echo_n "checking the maximum length of command line arguments... " >&6; } if ${lt_cv_sys_max_cmd_len+:} false; then : $as_echo_n "(cached) " >&6 else i=0 teststring="ABCD" case $build_os in msdosdjgpp*) # On DJGPP, this test can blow up pretty badly due to problems in libc # (any single argument exceeding 2000 bytes causes a buffer overrun # during glob expansion). Even if it were fixed, the result of this # check would be larger than it should be. lt_cv_sys_max_cmd_len=12288; # 12K is about right ;; gnu*) # Under GNU Hurd, this test is not required because there is # no limit to the length of command line arguments. # Libtool will interpret -1 as no limit whatsoever lt_cv_sys_max_cmd_len=-1; ;; cygwin* | mingw* | cegcc*) # On Win9x/ME, this test blows up -- it succeeds, but takes # about 5 minutes as the teststring grows exponentially. # Worse, since 9x/ME are not pre-emptively multitasking, # you end up with a "frozen" computer, even though with patience # the test eventually succeeds (with a max line length of 256k). # Instead, let's just punt: use the minimum linelength reported by # all of the supported platforms: 8192 (on NT/2K/XP). lt_cv_sys_max_cmd_len=8192; ;; mint*) # On MiNT this can take a long time and run out of memory. lt_cv_sys_max_cmd_len=8192; ;; amigaos*) # On AmigaOS with pdksh, this test takes hours, literally. # So we just punt and use a minimum line length of 8192. lt_cv_sys_max_cmd_len=8192; ;; netbsd* | freebsd* | openbsd* | darwin* | dragonfly*) # This has been around since 386BSD, at least. Likely further. if test -x /sbin/sysctl; then lt_cv_sys_max_cmd_len=`/sbin/sysctl -n kern.argmax` elif test -x /usr/sbin/sysctl; then lt_cv_sys_max_cmd_len=`/usr/sbin/sysctl -n kern.argmax` else lt_cv_sys_max_cmd_len=65536 # usable default for all BSDs fi # And add a safety zone lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4` lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3` ;; interix*) # We know the value 262144 and hardcode it with a safety zone (like BSD) lt_cv_sys_max_cmd_len=196608 ;; osf*) # Dr. Hans Ekkehard Plesser reports seeing a kernel panic running configure # due to this test when exec_disable_arg_limit is 1 on Tru64. It is not # nice to cause kernel panics so lets avoid the loop below. # First set a reasonable default. lt_cv_sys_max_cmd_len=16384 # if test -x /sbin/sysconfig; then case `/sbin/sysconfig -q proc exec_disable_arg_limit` in *1*) lt_cv_sys_max_cmd_len=-1 ;; esac fi ;; sco3.2v5*) lt_cv_sys_max_cmd_len=102400 ;; sysv5* | sco5v6* | sysv4.2uw2*) kargmax=`grep ARG_MAX /etc/conf/cf.d/stune 2>/dev/null` if test -n "$kargmax"; then lt_cv_sys_max_cmd_len=`echo $kargmax | sed 's/.*[ ]//'` else lt_cv_sys_max_cmd_len=32768 fi ;; *) lt_cv_sys_max_cmd_len=`(getconf ARG_MAX) 2> /dev/null` if test -n "$lt_cv_sys_max_cmd_len"; then lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4` lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3` else # Make teststring a little bigger before we do anything with it. # a 1K string should be a reasonable start. for i in 1 2 3 4 5 6 7 8 ; do teststring=$teststring$teststring done SHELL=${SHELL-${CONFIG_SHELL-/bin/sh}} # If test is not a shell built-in, we'll probably end up computing a # maximum length that is only half of the actual maximum length, but # we can't tell. while { test "X"`func_fallback_echo "$teststring$teststring" 2>/dev/null` \ = "X$teststring$teststring"; } >/dev/null 2>&1 && test $i != 17 # 1/2 MB should be enough do i=`expr $i + 1` teststring=$teststring$teststring done # Only check the string length outside the loop. lt_cv_sys_max_cmd_len=`expr "X$teststring" : ".*" 2>&1` teststring= # Add a significant safety factor because C++ compilers can tack on # massive amounts of additional arguments before passing them to the # linker. It appears as though 1/2 is a usable value. lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 2` fi ;; esac fi if test -n $lt_cv_sys_max_cmd_len ; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_sys_max_cmd_len" >&5 $as_echo "$lt_cv_sys_max_cmd_len" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: none" >&5 $as_echo "none" >&6; } fi max_cmd_len=$lt_cv_sys_max_cmd_len : ${CP="cp -f"} : ${MV="mv -f"} : ${RM="rm -f"} { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the shell understands some XSI constructs" >&5 $as_echo_n "checking whether the shell understands some XSI constructs... " >&6; } # Try some XSI features xsi_shell=no ( _lt_dummy="a/b/c" test "${_lt_dummy##*/},${_lt_dummy%/*},${_lt_dummy#??}"${_lt_dummy%"$_lt_dummy"}, \ = c,a/b,b/c, \ && eval 'test $(( 1 + 1 )) -eq 2 \ && test "${#_lt_dummy}" -eq 5' ) >/dev/null 2>&1 \ && xsi_shell=yes { $as_echo "$as_me:${as_lineno-$LINENO}: result: $xsi_shell" >&5 $as_echo "$xsi_shell" >&6; } { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the shell understands \"+=\"" >&5 $as_echo_n "checking whether the shell understands \"+=\"... " >&6; } lt_shell_append=no ( foo=bar; set foo baz; eval "$1+=\$2" && test "$foo" = barbaz ) \ >/dev/null 2>&1 \ && lt_shell_append=yes { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_shell_append" >&5 $as_echo "$lt_shell_append" >&6; } if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then lt_unset=unset else lt_unset=false fi # test EBCDIC or ASCII case `echo X|tr X '\101'` in A) # ASCII based system # \n is not interpreted correctly by Solaris 8 /usr/ucb/tr lt_SP2NL='tr \040 \012' lt_NL2SP='tr \015\012 \040\040' ;; *) # EBCDIC based system lt_SP2NL='tr \100 \n' lt_NL2SP='tr \r\n \100\100' ;; esac { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to convert $build file names to $host format" >&5 $as_echo_n "checking how to convert $build file names to $host format... " >&6; } if ${lt_cv_to_host_file_cmd+:} false; then : $as_echo_n "(cached) " >&6 else case $host in *-*-mingw* ) case $build in *-*-mingw* ) # actually msys lt_cv_to_host_file_cmd=func_convert_file_msys_to_w32 ;; *-*-cygwin* ) lt_cv_to_host_file_cmd=func_convert_file_cygwin_to_w32 ;; * ) # otherwise, assume *nix lt_cv_to_host_file_cmd=func_convert_file_nix_to_w32 ;; esac ;; *-*-cygwin* ) case $build in *-*-mingw* ) # actually msys lt_cv_to_host_file_cmd=func_convert_file_msys_to_cygwin ;; *-*-cygwin* ) lt_cv_to_host_file_cmd=func_convert_file_noop ;; * ) # otherwise, assume *nix lt_cv_to_host_file_cmd=func_convert_file_nix_to_cygwin ;; esac ;; * ) # unhandled hosts (and "normal" native builds) lt_cv_to_host_file_cmd=func_convert_file_noop ;; esac fi to_host_file_cmd=$lt_cv_to_host_file_cmd { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_to_host_file_cmd" >&5 $as_echo "$lt_cv_to_host_file_cmd" >&6; } { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to convert $build file names to toolchain format" >&5 $as_echo_n "checking how to convert $build file names to toolchain format... " >&6; } if ${lt_cv_to_tool_file_cmd+:} false; then : $as_echo_n "(cached) " >&6 else #assume ordinary cross tools, or native build. lt_cv_to_tool_file_cmd=func_convert_file_noop case $host in *-*-mingw* ) case $build in *-*-mingw* ) # actually msys lt_cv_to_tool_file_cmd=func_convert_file_msys_to_w32 ;; esac ;; esac fi to_tool_file_cmd=$lt_cv_to_tool_file_cmd { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_to_tool_file_cmd" >&5 $as_echo "$lt_cv_to_tool_file_cmd" >&6; } { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $LD option to reload object files" >&5 $as_echo_n "checking for $LD option to reload object files... " >&6; } if ${lt_cv_ld_reload_flag+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_ld_reload_flag='-r' fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_ld_reload_flag" >&5 $as_echo "$lt_cv_ld_reload_flag" >&6; } reload_flag=$lt_cv_ld_reload_flag case $reload_flag in "" | " "*) ;; *) reload_flag=" $reload_flag" ;; esac reload_cmds='$LD$reload_flag -o $output$reload_objs' case $host_os in cygwin* | mingw* | pw32* | cegcc*) if test "$GCC" != yes; then reload_cmds=false fi ;; darwin*) if test "$GCC" = yes; then reload_cmds='$LTCC $LTCFLAGS -nostdlib ${wl}-r -o $output$reload_objs' else reload_cmds='$LD$reload_flag -o $output$reload_objs' fi ;; esac if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}objdump", so it can be a program name with args. set dummy ${ac_tool_prefix}objdump; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_OBJDUMP+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$OBJDUMP"; then ac_cv_prog_OBJDUMP="$OBJDUMP" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_OBJDUMP="${ac_tool_prefix}objdump" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi OBJDUMP=$ac_cv_prog_OBJDUMP if test -n "$OBJDUMP"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $OBJDUMP" >&5 $as_echo "$OBJDUMP" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$ac_cv_prog_OBJDUMP"; then ac_ct_OBJDUMP=$OBJDUMP # Extract the first word of "objdump", so it can be a program name with args. set dummy objdump; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_OBJDUMP+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_OBJDUMP"; then ac_cv_prog_ac_ct_OBJDUMP="$ac_ct_OBJDUMP" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_OBJDUMP="objdump" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_OBJDUMP=$ac_cv_prog_ac_ct_OBJDUMP if test -n "$ac_ct_OBJDUMP"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_OBJDUMP" >&5 $as_echo "$ac_ct_OBJDUMP" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$ac_ct_OBJDUMP" = x; then OBJDUMP="false" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac OBJDUMP=$ac_ct_OBJDUMP fi else OBJDUMP="$ac_cv_prog_OBJDUMP" fi test -z "$OBJDUMP" && OBJDUMP=objdump { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to recognize dependent libraries" >&5 $as_echo_n "checking how to recognize dependent libraries... " >&6; } if ${lt_cv_deplibs_check_method+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_file_magic_cmd='$MAGIC_CMD' lt_cv_file_magic_test_file= lt_cv_deplibs_check_method='unknown' # Need to set the preceding variable on all platforms that support # interlibrary dependencies. # 'none' -- dependencies not supported. # `unknown' -- same as none, but documents that we really don't know. # 'pass_all' -- all dependencies passed with no checks. # 'test_compile' -- check by making test program. # 'file_magic [[regex]]' -- check by looking for files in library path # which responds to the $file_magic_cmd with a given extended regex. # If you have `file' or equivalent on your system and you're not sure # whether `pass_all' will *always* work, you probably want this one. case $host_os in aix[4-9]*) lt_cv_deplibs_check_method=pass_all ;; beos*) lt_cv_deplibs_check_method=pass_all ;; bsdi[45]*) lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib)' lt_cv_file_magic_cmd='/usr/bin/file -L' lt_cv_file_magic_test_file=/shlib/libc.so ;; cygwin*) # func_win32_libid is a shell function defined in ltmain.sh lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL' lt_cv_file_magic_cmd='func_win32_libid' ;; mingw* | pw32*) # Base MSYS/MinGW do not provide the 'file' command needed by # func_win32_libid shell function, so use a weaker test based on 'objdump', # unless we find 'file', for example because we are cross-compiling. # func_win32_libid assumes BSD nm, so disallow it if using MS dumpbin. if ( test "$lt_cv_nm_interface" = "BSD nm" && file / ) >/dev/null 2>&1; then lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL' lt_cv_file_magic_cmd='func_win32_libid' else # Keep this pattern in sync with the one in func_win32_libid. lt_cv_deplibs_check_method='file_magic file format (pei*-i386(.*architecture: i386)?|pe-arm-wince|pe-x86-64)' lt_cv_file_magic_cmd='$OBJDUMP -f' fi ;; cegcc*) # use the weaker test based on 'objdump'. See mingw*. lt_cv_deplibs_check_method='file_magic file format pe-arm-.*little(.*architecture: arm)?' lt_cv_file_magic_cmd='$OBJDUMP -f' ;; darwin* | rhapsody*) lt_cv_deplibs_check_method=pass_all ;; freebsd* | dragonfly*) if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then case $host_cpu in i*86 ) # Not sure whether the presence of OpenBSD here was a mistake. # Let's accept both of them until this is cleared up. lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD|DragonFly)/i[3-9]86 (compact )?demand paged shared library' lt_cv_file_magic_cmd=/usr/bin/file lt_cv_file_magic_test_file=`echo /usr/lib/libc.so.*` ;; esac else lt_cv_deplibs_check_method=pass_all fi ;; gnu*) lt_cv_deplibs_check_method=pass_all ;; haiku*) lt_cv_deplibs_check_method=pass_all ;; hpux10.20* | hpux11*) lt_cv_file_magic_cmd=/usr/bin/file case $host_cpu in ia64*) lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF-[0-9][0-9]) shared object file - IA64' lt_cv_file_magic_test_file=/usr/lib/hpux32/libc.so ;; hppa*64*) lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]' lt_cv_file_magic_test_file=/usr/lib/pa20_64/libc.sl ;; *) lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|PA-RISC[0-9]\.[0-9]) shared library' lt_cv_file_magic_test_file=/usr/lib/libc.sl ;; esac ;; interix[3-9]*) # PIC code is broken on Interix 3.x, that's why |\.a not |_pic\.a here lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|\.a)$' ;; irix5* | irix6* | nonstopux*) case $LD in *-32|*"-32 ") libmagic=32-bit;; *-n32|*"-n32 ") libmagic=N32;; *-64|*"-64 ") libmagic=64-bit;; *) libmagic=never-match;; esac lt_cv_deplibs_check_method=pass_all ;; # This must be Linux ELF. linux* | k*bsd*-gnu | kopensolaris*-gnu) lt_cv_deplibs_check_method=pass_all ;; netbsd* | netbsdelf*-gnu) if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$' else lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so|_pic\.a)$' fi ;; newos6*) lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (executable|dynamic lib)' lt_cv_file_magic_cmd=/usr/bin/file lt_cv_file_magic_test_file=/usr/lib/libnls.so ;; *nto* | *qnx*) lt_cv_deplibs_check_method=pass_all ;; openbsd*) if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|\.so|_pic\.a)$' else lt_cv_deplibs_check_method='match_pattern /lib[^/]+(\.so\.[0-9]+\.[0-9]+|_pic\.a)$' fi ;; osf3* | osf4* | osf5*) lt_cv_deplibs_check_method=pass_all ;; rdos*) lt_cv_deplibs_check_method=pass_all ;; solaris*) lt_cv_deplibs_check_method=pass_all ;; sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*) lt_cv_deplibs_check_method=pass_all ;; sysv4 | sysv4.3*) case $host_vendor in motorola) lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [ML]SB (shared object|dynamic lib) M[0-9][0-9]* Version [0-9]' lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*` ;; ncr) lt_cv_deplibs_check_method=pass_all ;; sequent) lt_cv_file_magic_cmd='/bin/file' lt_cv_deplibs_check_method='file_magic ELF [0-9][0-9]*-bit [LM]SB (shared object|dynamic lib )' ;; sni) lt_cv_file_magic_cmd='/bin/file' lt_cv_deplibs_check_method="file_magic ELF [0-9][0-9]*-bit [LM]SB dynamic lib" lt_cv_file_magic_test_file=/lib/libc.so ;; siemens) lt_cv_deplibs_check_method=pass_all ;; pc) lt_cv_deplibs_check_method=pass_all ;; esac ;; tpf*) lt_cv_deplibs_check_method=pass_all ;; esac fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_deplibs_check_method" >&5 $as_echo "$lt_cv_deplibs_check_method" >&6; } file_magic_glob= want_nocaseglob=no if test "$build" = "$host"; then case $host_os in mingw* | pw32*) if ( shopt | grep nocaseglob ) >/dev/null 2>&1; then want_nocaseglob=yes else file_magic_glob=`echo aAbBcCdDeEfFgGhHiIjJkKlLmMnNoOpPqQrRsStTuUvVwWxXyYzZ | $SED -e "s/\(..\)/s\/[\1]\/[\1]\/g;/g"` fi ;; esac fi file_magic_cmd=$lt_cv_file_magic_cmd deplibs_check_method=$lt_cv_deplibs_check_method test -z "$deplibs_check_method" && deplibs_check_method=unknown if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}dlltool", so it can be a program name with args. set dummy ${ac_tool_prefix}dlltool; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_DLLTOOL+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$DLLTOOL"; then ac_cv_prog_DLLTOOL="$DLLTOOL" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_DLLTOOL="${ac_tool_prefix}dlltool" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi DLLTOOL=$ac_cv_prog_DLLTOOL if test -n "$DLLTOOL"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $DLLTOOL" >&5 $as_echo "$DLLTOOL" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$ac_cv_prog_DLLTOOL"; then ac_ct_DLLTOOL=$DLLTOOL # Extract the first word of "dlltool", so it can be a program name with args. set dummy dlltool; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_DLLTOOL+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_DLLTOOL"; then ac_cv_prog_ac_ct_DLLTOOL="$ac_ct_DLLTOOL" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_DLLTOOL="dlltool" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_DLLTOOL=$ac_cv_prog_ac_ct_DLLTOOL if test -n "$ac_ct_DLLTOOL"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_DLLTOOL" >&5 $as_echo "$ac_ct_DLLTOOL" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$ac_ct_DLLTOOL" = x; then DLLTOOL="false" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac DLLTOOL=$ac_ct_DLLTOOL fi else DLLTOOL="$ac_cv_prog_DLLTOOL" fi test -z "$DLLTOOL" && DLLTOOL=dlltool { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to associate runtime and link libraries" >&5 $as_echo_n "checking how to associate runtime and link libraries... " >&6; } if ${lt_cv_sharedlib_from_linklib_cmd+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_sharedlib_from_linklib_cmd='unknown' case $host_os in cygwin* | mingw* | pw32* | cegcc*) # two different shell functions defined in ltmain.sh # decide which to use based on capabilities of $DLLTOOL case `$DLLTOOL --help 2>&1` in *--identify-strict*) lt_cv_sharedlib_from_linklib_cmd=func_cygming_dll_for_implib ;; *) lt_cv_sharedlib_from_linklib_cmd=func_cygming_dll_for_implib_fallback ;; esac ;; *) # fallback: assume linklib IS sharedlib lt_cv_sharedlib_from_linklib_cmd="$ECHO" ;; esac fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_sharedlib_from_linklib_cmd" >&5 $as_echo "$lt_cv_sharedlib_from_linklib_cmd" >&6; } sharedlib_from_linklib_cmd=$lt_cv_sharedlib_from_linklib_cmd test -z "$sharedlib_from_linklib_cmd" && sharedlib_from_linklib_cmd=$ECHO if test -n "$ac_tool_prefix"; then for ac_prog in ar do # Extract the first word of "$ac_tool_prefix$ac_prog", so it can be a program name with args. set dummy $ac_tool_prefix$ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_AR+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$AR"; then ac_cv_prog_AR="$AR" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_AR="$ac_tool_prefix$ac_prog" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi AR=$ac_cv_prog_AR if test -n "$AR"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $AR" >&5 $as_echo "$AR" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi test -n "$AR" && break done fi if test -z "$AR"; then ac_ct_AR=$AR for ac_prog in ar do # Extract the first word of "$ac_prog", so it can be a program name with args. set dummy $ac_prog; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_AR+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_AR"; then ac_cv_prog_ac_ct_AR="$ac_ct_AR" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_AR="$ac_prog" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_AR=$ac_cv_prog_ac_ct_AR if test -n "$ac_ct_AR"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_AR" >&5 $as_echo "$ac_ct_AR" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi test -n "$ac_ct_AR" && break done if test "x$ac_ct_AR" = x; then AR="false" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac AR=$ac_ct_AR fi fi : ${AR=ar} : ${AR_FLAGS=cru} { $as_echo "$as_me:${as_lineno-$LINENO}: checking for archiver @FILE support" >&5 $as_echo_n "checking for archiver @FILE support... " >&6; } if ${lt_cv_ar_at_file+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_ar_at_file=no cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_compile "$LINENO"; then : echo conftest.$ac_objext > conftest.lst lt_ar_try='$AR $AR_FLAGS libconftest.a @conftest.lst >&5' { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$lt_ar_try\""; } >&5 (eval $lt_ar_try) 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } if test "$ac_status" -eq 0; then # Ensure the archiver fails upon bogus file names. rm -f conftest.$ac_objext libconftest.a { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$lt_ar_try\""; } >&5 (eval $lt_ar_try) 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } if test "$ac_status" -ne 0; then lt_cv_ar_at_file=@ fi fi rm -f conftest.* libconftest.a fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_ar_at_file" >&5 $as_echo "$lt_cv_ar_at_file" >&6; } if test "x$lt_cv_ar_at_file" = xno; then archiver_list_spec= else archiver_list_spec=$lt_cv_ar_at_file fi if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}strip", so it can be a program name with args. set dummy ${ac_tool_prefix}strip; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_STRIP+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$STRIP"; then ac_cv_prog_STRIP="$STRIP" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_STRIP="${ac_tool_prefix}strip" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi STRIP=$ac_cv_prog_STRIP if test -n "$STRIP"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $STRIP" >&5 $as_echo "$STRIP" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$ac_cv_prog_STRIP"; then ac_ct_STRIP=$STRIP # Extract the first word of "strip", so it can be a program name with args. set dummy strip; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_STRIP+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_STRIP"; then ac_cv_prog_ac_ct_STRIP="$ac_ct_STRIP" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_STRIP="strip" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_STRIP=$ac_cv_prog_ac_ct_STRIP if test -n "$ac_ct_STRIP"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_STRIP" >&5 $as_echo "$ac_ct_STRIP" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$ac_ct_STRIP" = x; then STRIP=":" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac STRIP=$ac_ct_STRIP fi else STRIP="$ac_cv_prog_STRIP" fi test -z "$STRIP" && STRIP=: if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}ranlib", so it can be a program name with args. set dummy ${ac_tool_prefix}ranlib; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_RANLIB+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$RANLIB"; then ac_cv_prog_RANLIB="$RANLIB" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_RANLIB="${ac_tool_prefix}ranlib" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi RANLIB=$ac_cv_prog_RANLIB if test -n "$RANLIB"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $RANLIB" >&5 $as_echo "$RANLIB" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$ac_cv_prog_RANLIB"; then ac_ct_RANLIB=$RANLIB # Extract the first word of "ranlib", so it can be a program name with args. set dummy ranlib; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_RANLIB+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_RANLIB"; then ac_cv_prog_ac_ct_RANLIB="$ac_ct_RANLIB" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_RANLIB="ranlib" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_RANLIB=$ac_cv_prog_ac_ct_RANLIB if test -n "$ac_ct_RANLIB"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_RANLIB" >&5 $as_echo "$ac_ct_RANLIB" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$ac_ct_RANLIB" = x; then RANLIB=":" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac RANLIB=$ac_ct_RANLIB fi else RANLIB="$ac_cv_prog_RANLIB" fi test -z "$RANLIB" && RANLIB=: # Determine commands to create old-style static archives. old_archive_cmds='$AR $AR_FLAGS $oldlib$oldobjs' old_postinstall_cmds='chmod 644 $oldlib' old_postuninstall_cmds= if test -n "$RANLIB"; then case $host_os in openbsd*) old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB -t \$oldlib" ;; *) old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB \$oldlib" ;; esac old_archive_cmds="$old_archive_cmds~\$RANLIB \$oldlib" fi case $host_os in darwin*) lock_old_archive_extraction=yes ;; *) lock_old_archive_extraction=no ;; esac # If no C compiler was specified, use CC. LTCC=${LTCC-"$CC"} # If no C compiler flags were specified, use CFLAGS. LTCFLAGS=${LTCFLAGS-"$CFLAGS"} # Allow CC to be a program name with arguments. compiler=$CC # Check for command to grab the raw symbol name followed by C symbol from nm. { $as_echo "$as_me:${as_lineno-$LINENO}: checking command to parse $NM output from $compiler object" >&5 $as_echo_n "checking command to parse $NM output from $compiler object... " >&6; } if ${lt_cv_sys_global_symbol_pipe+:} false; then : $as_echo_n "(cached) " >&6 else # These are sane defaults that work on at least a few old systems. # [They come from Ultrix. What could be older than Ultrix?!! ;)] # Character class describing NM global symbol codes. symcode='[BCDEGRST]' # Regexp to match symbols that can be accessed directly from C. sympat='\([_A-Za-z][_A-Za-z0-9]*\)' # Define system-specific variables. case $host_os in aix*) symcode='[BCDT]' ;; cygwin* | mingw* | pw32* | cegcc*) symcode='[ABCDGISTW]' ;; hpux*) if test "$host_cpu" = ia64; then symcode='[ABCDEGRST]' fi ;; irix* | nonstopux*) symcode='[BCDEGRST]' ;; osf*) symcode='[BCDEGQRST]' ;; solaris*) symcode='[BDRT]' ;; sco3.2v5*) symcode='[DT]' ;; sysv4.2uw2*) symcode='[DT]' ;; sysv5* | sco5v6* | unixware* | OpenUNIX*) symcode='[ABDT]' ;; sysv4) symcode='[DFNSTU]' ;; esac # If we're using GNU nm, then use its standard symbol codes. case `$NM -V 2>&1` in *GNU* | *'with BFD'*) symcode='[ABCDGIRSTW]' ;; esac # Transform an extracted symbol line into a proper C declaration. # Some systems (esp. on ia64) link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl="sed -n -e 's/^T .* \(.*\)$/extern int \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" # Transform an extracted symbol line into symbol name and symbol address lt_cv_sys_global_symbol_to_c_name_address="sed -n -e 's/^: \([^ ]*\)[ ]*$/ {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([^ ]*\) \([^ ]*\)$/ {\"\2\", (void *) \&\2},/p'" lt_cv_sys_global_symbol_to_c_name_address_lib_prefix="sed -n -e 's/^: \([^ ]*\)[ ]*$/ {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([^ ]*\) \(lib[^ ]*\)$/ {\"\2\", (void *) \&\2},/p' -e 's/^$symcode* \([^ ]*\) \([^ ]*\)$/ {\"lib\2\", (void *) \&\2},/p'" # Handle CRLF in mingw tool chain opt_cr= case $build_os in mingw*) opt_cr=`$ECHO 'x\{0,1\}' | tr x '\015'` # option cr in regexp ;; esac # Try without a prefix underscore, then with it. for ac_symprfx in "" "_"; do # Transform symcode, sympat, and symprfx into a raw symbol and a C symbol. symxfrm="\\1 $ac_symprfx\\2 \\2" # Write the raw and C identifiers. if test "$lt_cv_nm_interface" = "MS dumpbin"; then # Fake it for dumpbin and say T for any non-static function # and D for any global variable. # Also find C++ and __fastcall symbols from MSVC++, # which start with @ or ?. lt_cv_sys_global_symbol_pipe="$AWK '"\ " {last_section=section; section=\$ 3};"\ " /Section length .*#relocs.*(pick any)/{hide[last_section]=1};"\ " \$ 0!~/External *\|/{next};"\ " / 0+ UNDEF /{next}; / UNDEF \([^|]\)*()/{next};"\ " {if(hide[section]) next};"\ " {f=0}; \$ 0~/\(\).*\|/{f=1}; {printf f ? \"T \" : \"D \"};"\ " {split(\$ 0, a, /\||\r/); split(a[2], s)};"\ " s[1]~/^[@?]/{print s[1], s[1]; next};"\ " s[1]~prfx {split(s[1],t,\"@\"); print t[1], substr(t[1],length(prfx))}"\ " ' prfx=^$ac_symprfx" else lt_cv_sys_global_symbol_pipe="sed -n -e 's/^.*[ ]\($symcode$symcode*\)[ ][ ]*$ac_symprfx$sympat$opt_cr$/$symxfrm/p'" fi lt_cv_sys_global_symbol_pipe="$lt_cv_sys_global_symbol_pipe | sed '/ __gnu_lto/d'" # Check to see that the pipe works correctly. pipe_works=no rm -f conftest* cat > conftest.$ac_ext <<_LT_EOF #ifdef __cplusplus extern "C" { #endif char nm_test_var; void nm_test_func(void); void nm_test_func(void){} #ifdef __cplusplus } #endif int main(){nm_test_var='a';nm_test_func();return(0);} _LT_EOF if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 (eval $ac_compile) 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then # Now try to grab the symbols. nlist=conftest.nm if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$NM conftest.$ac_objext \| "$lt_cv_sys_global_symbol_pipe" \> $nlist\""; } >&5 (eval $NM conftest.$ac_objext \| "$lt_cv_sys_global_symbol_pipe" \> $nlist) 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } && test -s "$nlist"; then # Try sorting and uniquifying the output. if sort "$nlist" | uniq > "$nlist"T; then mv -f "$nlist"T "$nlist" else rm -f "$nlist"T fi # Make sure that we snagged all the symbols we need. if $GREP ' nm_test_var$' "$nlist" >/dev/null; then if $GREP ' nm_test_func$' "$nlist" >/dev/null; then cat <<_LT_EOF > conftest.$ac_ext /* Keep this code in sync between libtool.m4, ltmain, lt_system.h, and tests. */ #if defined(_WIN32) || defined(__CYGWIN__) || defined(_WIN32_WCE) /* DATA imports from DLLs on WIN32 con't be const, because runtime relocations are performed -- see ld's documentation on pseudo-relocs. */ # define LT_DLSYM_CONST #elif defined(__osf__) /* This system does not cope well with relocations in const data. */ # define LT_DLSYM_CONST #else # define LT_DLSYM_CONST const #endif #ifdef __cplusplus extern "C" { #endif _LT_EOF # Now generate the symbol file. eval "$lt_cv_sys_global_symbol_to_cdecl"' < "$nlist" | $GREP -v main >> conftest.$ac_ext' cat <<_LT_EOF >> conftest.$ac_ext /* The mapping between symbol names and symbols. */ LT_DLSYM_CONST struct { const char *name; void *address; } lt__PROGRAM__LTX_preloaded_symbols[] = { { "@PROGRAM@", (void *) 0 }, _LT_EOF $SED "s/^$symcode$symcode* \(.*\) \(.*\)$/ {\"\2\", (void *) \&\2},/" < "$nlist" | $GREP -v main >> conftest.$ac_ext cat <<\_LT_EOF >> conftest.$ac_ext {0, (void *) 0} }; /* This works around a problem in FreeBSD linker */ #ifdef FREEBSD_WORKAROUND static const void *lt_preloaded_setup() { return lt__PROGRAM__LTX_preloaded_symbols; } #endif #ifdef __cplusplus } #endif _LT_EOF # Now try linking the two files. mv conftest.$ac_objext conftstm.$ac_objext lt_globsym_save_LIBS=$LIBS lt_globsym_save_CFLAGS=$CFLAGS LIBS="conftstm.$ac_objext" CFLAGS="$CFLAGS$lt_prog_compiler_no_builtin_flag" if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_link\""; } >&5 (eval $ac_link) 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } && test -s conftest${ac_exeext}; then pipe_works=yes fi LIBS=$lt_globsym_save_LIBS CFLAGS=$lt_globsym_save_CFLAGS else echo "cannot find nm_test_func in $nlist" >&5 fi else echo "cannot find nm_test_var in $nlist" >&5 fi else echo "cannot run $lt_cv_sys_global_symbol_pipe" >&5 fi else echo "$progname: failed program was:" >&5 cat conftest.$ac_ext >&5 fi rm -rf conftest* conftst* # Do not use the global_symbol_pipe unless it works. if test "$pipe_works" = yes; then break else lt_cv_sys_global_symbol_pipe= fi done fi if test -z "$lt_cv_sys_global_symbol_pipe"; then lt_cv_sys_global_symbol_to_cdecl= fi if test -z "$lt_cv_sys_global_symbol_pipe$lt_cv_sys_global_symbol_to_cdecl"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: failed" >&5 $as_echo "failed" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: ok" >&5 $as_echo "ok" >&6; } fi # Response file support. if test "$lt_cv_nm_interface" = "MS dumpbin"; then nm_file_list_spec='@' elif $NM --help 2>/dev/null | grep '[@]FILE' >/dev/null; then nm_file_list_spec='@' fi { $as_echo "$as_me:${as_lineno-$LINENO}: checking for sysroot" >&5 $as_echo_n "checking for sysroot... " >&6; } # Check whether --with-sysroot was given. if test "${with_sysroot+set}" = set; then : withval=$with_sysroot; else with_sysroot=no fi lt_sysroot= case ${with_sysroot} in #( yes) if test "$GCC" = yes; then lt_sysroot=`$CC --print-sysroot 2>/dev/null` fi ;; #( /*) lt_sysroot=`echo "$with_sysroot" | sed -e "$sed_quote_subst"` ;; #( no|'') ;; #( *) { $as_echo "$as_me:${as_lineno-$LINENO}: result: ${with_sysroot}" >&5 $as_echo "${with_sysroot}" >&6; } as_fn_error $? "The sysroot must be an absolute path." "$LINENO" 5 ;; esac { $as_echo "$as_me:${as_lineno-$LINENO}: result: ${lt_sysroot:-no}" >&5 $as_echo "${lt_sysroot:-no}" >&6; } # Check whether --enable-libtool-lock was given. if test "${enable_libtool_lock+set}" = set; then : enableval=$enable_libtool_lock; fi test "x$enable_libtool_lock" != xno && enable_libtool_lock=yes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in ia64-*-hpux*) # Find out which ABI we are using. echo 'int i;' > conftest.$ac_ext if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 (eval $ac_compile) 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then case `/usr/bin/file conftest.$ac_objext` in *ELF-32*) HPUX_IA64_MODE="32" ;; *ELF-64*) HPUX_IA64_MODE="64" ;; esac fi rm -rf conftest* ;; *-*-irix6*) # Find out which ABI we are using. echo '#line '$LINENO' "configure"' > conftest.$ac_ext if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 (eval $ac_compile) 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then if test "$lt_cv_prog_gnu_ld" = yes; then case `/usr/bin/file conftest.$ac_objext` in *32-bit*) LD="${LD-ld} -melf32bsmip" ;; *N32*) LD="${LD-ld} -melf32bmipn32" ;; *64-bit*) LD="${LD-ld} -melf64bmip" ;; esac else case `/usr/bin/file conftest.$ac_objext` in *32-bit*) LD="${LD-ld} -32" ;; *N32*) LD="${LD-ld} -n32" ;; *64-bit*) LD="${LD-ld} -64" ;; esac fi fi rm -rf conftest* ;; x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ s390*-*linux*|s390*-*tpf*|sparc*-*linux*) # Find out which ABI we are using. echo 'int i;' > conftest.$ac_ext if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 (eval $ac_compile) 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then case `/usr/bin/file conftest.o` in *32-bit*) case $host in x86_64-*kfreebsd*-gnu) LD="${LD-ld} -m elf_i386_fbsd" ;; x86_64-*linux*) LD="${LD-ld} -m elf_i386" ;; ppc64-*linux*|powerpc64-*linux*) LD="${LD-ld} -m elf32ppclinux" ;; s390x-*linux*) LD="${LD-ld} -m elf_s390" ;; sparc64-*linux*) LD="${LD-ld} -m elf32_sparc" ;; esac ;; *64-bit*) case $host in x86_64-*kfreebsd*-gnu) LD="${LD-ld} -m elf_x86_64_fbsd" ;; x86_64-*linux*) LD="${LD-ld} -m elf_x86_64" ;; ppc*-*linux*|powerpc*-*linux*) LD="${LD-ld} -m elf64ppc" ;; s390*-*linux*|s390*-*tpf*) LD="${LD-ld} -m elf64_s390" ;; sparc*-*linux*) LD="${LD-ld} -m elf64_sparc" ;; esac ;; esac fi rm -rf conftest* ;; *-*-sco3.2v5*) # On SCO OpenServer 5, we need -belf to get full-featured binaries. SAVE_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS -belf" { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the C compiler needs -belf" >&5 $as_echo_n "checking whether the C compiler needs -belf... " >&6; } if ${lt_cv_cc_needs_belf+:} false; then : $as_echo_n "(cached) " >&6 else ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : lt_cv_cc_needs_belf=yes else lt_cv_cc_needs_belf=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_cc_needs_belf" >&5 $as_echo "$lt_cv_cc_needs_belf" >&6; } if test x"$lt_cv_cc_needs_belf" != x"yes"; then # this is probably gcc 2.8.0, egcs 1.0 or newer; no need for -belf CFLAGS="$SAVE_CFLAGS" fi ;; sparc*-*solaris*) # Find out which ABI we are using. echo 'int i;' > conftest.$ac_ext if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 (eval $ac_compile) 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then case `/usr/bin/file conftest.o` in *64-bit*) case $lt_cv_prog_gnu_ld in yes*) LD="${LD-ld} -m elf64_sparc" ;; *) if ${LD-ld} -64 -r -o conftest2.o conftest.o >/dev/null 2>&1; then LD="${LD-ld} -64" fi ;; esac ;; esac fi rm -rf conftest* ;; esac need_locks="$enable_libtool_lock" if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}mt", so it can be a program name with args. set dummy ${ac_tool_prefix}mt; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_MANIFEST_TOOL+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$MANIFEST_TOOL"; then ac_cv_prog_MANIFEST_TOOL="$MANIFEST_TOOL" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_MANIFEST_TOOL="${ac_tool_prefix}mt" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi MANIFEST_TOOL=$ac_cv_prog_MANIFEST_TOOL if test -n "$MANIFEST_TOOL"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MANIFEST_TOOL" >&5 $as_echo "$MANIFEST_TOOL" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$ac_cv_prog_MANIFEST_TOOL"; then ac_ct_MANIFEST_TOOL=$MANIFEST_TOOL # Extract the first word of "mt", so it can be a program name with args. set dummy mt; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_MANIFEST_TOOL+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_MANIFEST_TOOL"; then ac_cv_prog_ac_ct_MANIFEST_TOOL="$ac_ct_MANIFEST_TOOL" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_MANIFEST_TOOL="mt" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_MANIFEST_TOOL=$ac_cv_prog_ac_ct_MANIFEST_TOOL if test -n "$ac_ct_MANIFEST_TOOL"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_MANIFEST_TOOL" >&5 $as_echo "$ac_ct_MANIFEST_TOOL" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$ac_ct_MANIFEST_TOOL" = x; then MANIFEST_TOOL=":" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac MANIFEST_TOOL=$ac_ct_MANIFEST_TOOL fi else MANIFEST_TOOL="$ac_cv_prog_MANIFEST_TOOL" fi test -z "$MANIFEST_TOOL" && MANIFEST_TOOL=mt { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $MANIFEST_TOOL is a manifest tool" >&5 $as_echo_n "checking if $MANIFEST_TOOL is a manifest tool... " >&6; } if ${lt_cv_path_mainfest_tool+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_path_mainfest_tool=no echo "$as_me:$LINENO: $MANIFEST_TOOL '-?'" >&5 $MANIFEST_TOOL '-?' 2>conftest.err > conftest.out cat conftest.err >&5 if $GREP 'Manifest Tool' conftest.out > /dev/null; then lt_cv_path_mainfest_tool=yes fi rm -f conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_path_mainfest_tool" >&5 $as_echo "$lt_cv_path_mainfest_tool" >&6; } if test "x$lt_cv_path_mainfest_tool" != xyes; then MANIFEST_TOOL=: fi case $host_os in rhapsody* | darwin*) if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}dsymutil", so it can be a program name with args. set dummy ${ac_tool_prefix}dsymutil; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_DSYMUTIL+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$DSYMUTIL"; then ac_cv_prog_DSYMUTIL="$DSYMUTIL" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_DSYMUTIL="${ac_tool_prefix}dsymutil" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi DSYMUTIL=$ac_cv_prog_DSYMUTIL if test -n "$DSYMUTIL"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $DSYMUTIL" >&5 $as_echo "$DSYMUTIL" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$ac_cv_prog_DSYMUTIL"; then ac_ct_DSYMUTIL=$DSYMUTIL # Extract the first word of "dsymutil", so it can be a program name with args. set dummy dsymutil; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_DSYMUTIL+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_DSYMUTIL"; then ac_cv_prog_ac_ct_DSYMUTIL="$ac_ct_DSYMUTIL" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_DSYMUTIL="dsymutil" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_DSYMUTIL=$ac_cv_prog_ac_ct_DSYMUTIL if test -n "$ac_ct_DSYMUTIL"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_DSYMUTIL" >&5 $as_echo "$ac_ct_DSYMUTIL" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$ac_ct_DSYMUTIL" = x; then DSYMUTIL=":" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac DSYMUTIL=$ac_ct_DSYMUTIL fi else DSYMUTIL="$ac_cv_prog_DSYMUTIL" fi if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}nmedit", so it can be a program name with args. set dummy ${ac_tool_prefix}nmedit; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_NMEDIT+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$NMEDIT"; then ac_cv_prog_NMEDIT="$NMEDIT" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_NMEDIT="${ac_tool_prefix}nmedit" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi NMEDIT=$ac_cv_prog_NMEDIT if test -n "$NMEDIT"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $NMEDIT" >&5 $as_echo "$NMEDIT" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$ac_cv_prog_NMEDIT"; then ac_ct_NMEDIT=$NMEDIT # Extract the first word of "nmedit", so it can be a program name with args. set dummy nmedit; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_NMEDIT+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_NMEDIT"; then ac_cv_prog_ac_ct_NMEDIT="$ac_ct_NMEDIT" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_NMEDIT="nmedit" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_NMEDIT=$ac_cv_prog_ac_ct_NMEDIT if test -n "$ac_ct_NMEDIT"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_NMEDIT" >&5 $as_echo "$ac_ct_NMEDIT" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$ac_ct_NMEDIT" = x; then NMEDIT=":" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac NMEDIT=$ac_ct_NMEDIT fi else NMEDIT="$ac_cv_prog_NMEDIT" fi if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}lipo", so it can be a program name with args. set dummy ${ac_tool_prefix}lipo; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_LIPO+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$LIPO"; then ac_cv_prog_LIPO="$LIPO" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_LIPO="${ac_tool_prefix}lipo" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi LIPO=$ac_cv_prog_LIPO if test -n "$LIPO"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LIPO" >&5 $as_echo "$LIPO" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$ac_cv_prog_LIPO"; then ac_ct_LIPO=$LIPO # Extract the first word of "lipo", so it can be a program name with args. set dummy lipo; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_LIPO+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_LIPO"; then ac_cv_prog_ac_ct_LIPO="$ac_ct_LIPO" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_LIPO="lipo" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_LIPO=$ac_cv_prog_ac_ct_LIPO if test -n "$ac_ct_LIPO"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_LIPO" >&5 $as_echo "$ac_ct_LIPO" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$ac_ct_LIPO" = x; then LIPO=":" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac LIPO=$ac_ct_LIPO fi else LIPO="$ac_cv_prog_LIPO" fi if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}otool", so it can be a program name with args. set dummy ${ac_tool_prefix}otool; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_OTOOL+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$OTOOL"; then ac_cv_prog_OTOOL="$OTOOL" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_OTOOL="${ac_tool_prefix}otool" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi OTOOL=$ac_cv_prog_OTOOL if test -n "$OTOOL"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $OTOOL" >&5 $as_echo "$OTOOL" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$ac_cv_prog_OTOOL"; then ac_ct_OTOOL=$OTOOL # Extract the first word of "otool", so it can be a program name with args. set dummy otool; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_OTOOL+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_OTOOL"; then ac_cv_prog_ac_ct_OTOOL="$ac_ct_OTOOL" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_OTOOL="otool" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_OTOOL=$ac_cv_prog_ac_ct_OTOOL if test -n "$ac_ct_OTOOL"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_OTOOL" >&5 $as_echo "$ac_ct_OTOOL" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$ac_ct_OTOOL" = x; then OTOOL=":" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac OTOOL=$ac_ct_OTOOL fi else OTOOL="$ac_cv_prog_OTOOL" fi if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}otool64", so it can be a program name with args. set dummy ${ac_tool_prefix}otool64; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_OTOOL64+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$OTOOL64"; then ac_cv_prog_OTOOL64="$OTOOL64" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_OTOOL64="${ac_tool_prefix}otool64" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi OTOOL64=$ac_cv_prog_OTOOL64 if test -n "$OTOOL64"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $OTOOL64" >&5 $as_echo "$OTOOL64" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$ac_cv_prog_OTOOL64"; then ac_ct_OTOOL64=$OTOOL64 # Extract the first word of "otool64", so it can be a program name with args. set dummy otool64; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_OTOOL64+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_OTOOL64"; then ac_cv_prog_ac_ct_OTOOL64="$ac_ct_OTOOL64" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_OTOOL64="otool64" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_OTOOL64=$ac_cv_prog_ac_ct_OTOOL64 if test -n "$ac_ct_OTOOL64"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_OTOOL64" >&5 $as_echo "$ac_ct_OTOOL64" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$ac_ct_OTOOL64" = x; then OTOOL64=":" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac OTOOL64=$ac_ct_OTOOL64 fi else OTOOL64="$ac_cv_prog_OTOOL64" fi { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -single_module linker flag" >&5 $as_echo_n "checking for -single_module linker flag... " >&6; } if ${lt_cv_apple_cc_single_mod+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_apple_cc_single_mod=no if test -z "${LT_MULTI_MODULE}"; then # By default we will add the -single_module flag. You can override # by either setting the environment variable LT_MULTI_MODULE # non-empty at configure time, or by adding -multi_module to the # link flags. rm -rf libconftest.dylib* echo "int foo(void){return 1;}" > conftest.c echo "$LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \ -dynamiclib -Wl,-single_module conftest.c" >&5 $LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \ -dynamiclib -Wl,-single_module conftest.c 2>conftest.err _lt_result=$? if test -f libconftest.dylib && test ! -s conftest.err && test $_lt_result = 0; then lt_cv_apple_cc_single_mod=yes else cat conftest.err >&5 fi rm -rf libconftest.dylib* rm -f conftest.* fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_apple_cc_single_mod" >&5 $as_echo "$lt_cv_apple_cc_single_mod" >&6; } { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -exported_symbols_list linker flag" >&5 $as_echo_n "checking for -exported_symbols_list linker flag... " >&6; } if ${lt_cv_ld_exported_symbols_list+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_ld_exported_symbols_list=no save_LDFLAGS=$LDFLAGS echo "_main" > conftest.sym LDFLAGS="$LDFLAGS -Wl,-exported_symbols_list,conftest.sym" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : lt_cv_ld_exported_symbols_list=yes else lt_cv_ld_exported_symbols_list=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LDFLAGS="$save_LDFLAGS" fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_ld_exported_symbols_list" >&5 $as_echo "$lt_cv_ld_exported_symbols_list" >&6; } { $as_echo "$as_me:${as_lineno-$LINENO}: checking for -force_load linker flag" >&5 $as_echo_n "checking for -force_load linker flag... " >&6; } if ${lt_cv_ld_force_load+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_ld_force_load=no cat > conftest.c << _LT_EOF int forced_loaded() { return 2;} _LT_EOF echo "$LTCC $LTCFLAGS -c -o conftest.o conftest.c" >&5 $LTCC $LTCFLAGS -c -o conftest.o conftest.c 2>&5 echo "$AR cru libconftest.a conftest.o" >&5 $AR cru libconftest.a conftest.o 2>&5 echo "$RANLIB libconftest.a" >&5 $RANLIB libconftest.a 2>&5 cat > conftest.c << _LT_EOF int main() { return 0;} _LT_EOF echo "$LTCC $LTCFLAGS $LDFLAGS -o conftest conftest.c -Wl,-force_load,./libconftest.a" >&5 $LTCC $LTCFLAGS $LDFLAGS -o conftest conftest.c -Wl,-force_load,./libconftest.a 2>conftest.err _lt_result=$? if test -f conftest && test ! -s conftest.err && test $_lt_result = 0 && $GREP forced_load conftest 2>&1 >/dev/null; then lt_cv_ld_force_load=yes else cat conftest.err >&5 fi rm -f conftest.err libconftest.a conftest conftest.c rm -rf conftest.dSYM fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_ld_force_load" >&5 $as_echo "$lt_cv_ld_force_load" >&6; } case $host_os in rhapsody* | darwin1.[012]) _lt_dar_allow_undefined='${wl}-undefined ${wl}suppress' ;; darwin1.*) _lt_dar_allow_undefined='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;; darwin*) # darwin 5.x on # if running on 10.5 or later, the deployment target defaults # to the OS version, if on x86, and 10.4, the deployment # target defaults to 10.4. Don't you love it? case ${MACOSX_DEPLOYMENT_TARGET-10.0},$host in 10.0,*86*-darwin8*|10.0,*-darwin[91]*) _lt_dar_allow_undefined='${wl}-undefined ${wl}dynamic_lookup' ;; 10.[012]*) _lt_dar_allow_undefined='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;; 10.*) _lt_dar_allow_undefined='${wl}-undefined ${wl}dynamic_lookup' ;; esac ;; esac if test "$lt_cv_apple_cc_single_mod" = "yes"; then _lt_dar_single_mod='$single_module' fi if test "$lt_cv_ld_exported_symbols_list" = "yes"; then _lt_dar_export_syms=' ${wl}-exported_symbols_list,$output_objdir/${libname}-symbols.expsym' else _lt_dar_export_syms='~$NMEDIT -s $output_objdir/${libname}-symbols.expsym ${lib}' fi if test "$DSYMUTIL" != ":" && test "$lt_cv_ld_force_load" = "no"; then _lt_dsymutil='~$DSYMUTIL $lib || :' else _lt_dsymutil= fi ;; esac ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to run the C preprocessor" >&5 $as_echo_n "checking how to run the C preprocessor... " >&6; } # On Suns, sometimes $CPP names a directory. if test -n "$CPP" && test -d "$CPP"; then CPP= fi if test -z "$CPP"; then if ${ac_cv_prog_CPP+:} false; then : $as_echo_n "(cached) " >&6 else # Double quotes because CPP needs to be expanded for CPP in "$CC -E" "$CC -E -traditional-cpp" "/lib/cpp" do ac_preproc_ok=false for ac_c_preproc_warn_flag in '' yes do # Use a header file that comes with gcc, so configuring glibc # with a fresh cross-compiler works. # Prefer to if __STDC__ is defined, since # exists even on freestanding compilers. # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. "Syntax error" is here to catch this case. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #ifdef __STDC__ # include #else # include #endif Syntax error _ACEOF if ac_fn_c_try_cpp "$LINENO"; then : else # Broken: fails on valid input. continue fi rm -f conftest.err conftest.i conftest.$ac_ext # OK, works on sane cases. Now check whether nonexistent headers # can be detected and how. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include _ACEOF if ac_fn_c_try_cpp "$LINENO"; then : # Broken: success on invalid input. continue else # Passes both tests. ac_preproc_ok=: break fi rm -f conftest.err conftest.i conftest.$ac_ext done # Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. rm -f conftest.i conftest.err conftest.$ac_ext if $ac_preproc_ok; then : break fi done ac_cv_prog_CPP=$CPP fi CPP=$ac_cv_prog_CPP else ac_cv_prog_CPP=$CPP fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $CPP" >&5 $as_echo "$CPP" >&6; } ac_preproc_ok=false for ac_c_preproc_warn_flag in '' yes do # Use a header file that comes with gcc, so configuring glibc # with a fresh cross-compiler works. # Prefer to if __STDC__ is defined, since # exists even on freestanding compilers. # On the NeXT, cc -E runs the code through the compiler's parser, # not just through cpp. "Syntax error" is here to catch this case. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #ifdef __STDC__ # include #else # include #endif Syntax error _ACEOF if ac_fn_c_try_cpp "$LINENO"; then : else # Broken: fails on valid input. continue fi rm -f conftest.err conftest.i conftest.$ac_ext # OK, works on sane cases. Now check whether nonexistent headers # can be detected and how. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include _ACEOF if ac_fn_c_try_cpp "$LINENO"; then : # Broken: success on invalid input. continue else # Passes both tests. ac_preproc_ok=: break fi rm -f conftest.err conftest.i conftest.$ac_ext done # Because of `break', _AC_PREPROC_IFELSE's cleaning code was skipped. rm -f conftest.i conftest.err conftest.$ac_ext if $ac_preproc_ok; then : else { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error $? "C preprocessor \"$CPP\" fails sanity check See \`config.log' for more details" "$LINENO" 5; } fi ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu { $as_echo "$as_me:${as_lineno-$LINENO}: checking for ANSI C header files" >&5 $as_echo_n "checking for ANSI C header files... " >&6; } if ${ac_cv_header_stdc+:} false; then : $as_echo_n "(cached) " >&6 else cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include #include #include #include int main () { ; return 0; } _ACEOF if ac_fn_c_try_compile "$LINENO"; then : ac_cv_header_stdc=yes else ac_cv_header_stdc=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext if test $ac_cv_header_stdc = yes; then # SunOS 4.x string.h does not declare mem*, contrary to ANSI. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "memchr" >/dev/null 2>&1; then : else ac_cv_header_stdc=no fi rm -f conftest* fi if test $ac_cv_header_stdc = yes; then # ISC 2.0.2 stdlib.h does not declare free, contrary to ANSI. cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include _ACEOF if (eval "$ac_cpp conftest.$ac_ext") 2>&5 | $EGREP "free" >/dev/null 2>&1; then : else ac_cv_header_stdc=no fi rm -f conftest* fi if test $ac_cv_header_stdc = yes; then # /bin/cc in Irix-4.0.5 gets non-ANSI ctype macros unless using -ansi. if test "$cross_compiling" = yes; then : : else cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ #include #include #if ((' ' & 0x0FF) == 0x020) # define ISLOWER(c) ('a' <= (c) && (c) <= 'z') # define TOUPPER(c) (ISLOWER(c) ? 'A' + ((c) - 'a') : (c)) #else # define ISLOWER(c) \ (('a' <= (c) && (c) <= 'i') \ || ('j' <= (c) && (c) <= 'r') \ || ('s' <= (c) && (c) <= 'z')) # define TOUPPER(c) (ISLOWER(c) ? ((c) | 0x40) : (c)) #endif #define XOR(e, f) (((e) && !(f)) || (!(e) && (f))) int main () { int i; for (i = 0; i < 256; i++) if (XOR (islower (i), ISLOWER (i)) || toupper (i) != TOUPPER (i)) return 2; return 0; } _ACEOF if ac_fn_c_try_run "$LINENO"; then : else ac_cv_header_stdc=no fi rm -f core *.core core.conftest.* gmon.out bb.out conftest$ac_exeext \ conftest.$ac_objext conftest.beam conftest.$ac_ext fi fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_header_stdc" >&5 $as_echo "$ac_cv_header_stdc" >&6; } if test $ac_cv_header_stdc = yes; then $as_echo "#define STDC_HEADERS 1" >>confdefs.h fi # On IRIX 5.3, sys/types and inttypes.h are conflicting. for ac_header in sys/types.h sys/stat.h stdlib.h string.h memory.h strings.h \ inttypes.h stdint.h unistd.h do : as_ac_Header=`$as_echo "ac_cv_header_$ac_header" | $as_tr_sh` ac_fn_c_check_header_compile "$LINENO" "$ac_header" "$as_ac_Header" "$ac_includes_default " if eval test \"x\$"$as_ac_Header"\" = x"yes"; then : cat >>confdefs.h <<_ACEOF #define `$as_echo "HAVE_$ac_header" | $as_tr_cpp` 1 _ACEOF fi done for ac_header in dlfcn.h do : ac_fn_c_check_header_compile "$LINENO" "dlfcn.h" "ac_cv_header_dlfcn_h" "$ac_includes_default " if test "x$ac_cv_header_dlfcn_h" = xyes; then : cat >>confdefs.h <<_ACEOF #define HAVE_DLFCN_H 1 _ACEOF fi done # Set options enable_dlopen=no enable_win32_dll=no # Check whether --enable-shared was given. if test "${enable_shared+set}" = set; then : enableval=$enable_shared; p=${PACKAGE-default} case $enableval in yes) enable_shared=yes ;; no) enable_shared=no ;; *) enable_shared=no # Look at the argument we got. We use all the common list separators. lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," for pkg in $enableval; do IFS="$lt_save_ifs" if test "X$pkg" = "X$p"; then enable_shared=yes fi done IFS="$lt_save_ifs" ;; esac else enable_shared=yes fi # Check whether --enable-static was given. if test "${enable_static+set}" = set; then : enableval=$enable_static; p=${PACKAGE-default} case $enableval in yes) enable_static=yes ;; no) enable_static=no ;; *) enable_static=no # Look at the argument we got. We use all the common list separators. lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," for pkg in $enableval; do IFS="$lt_save_ifs" if test "X$pkg" = "X$p"; then enable_static=yes fi done IFS="$lt_save_ifs" ;; esac else enable_static=yes fi # Check whether --with-pic was given. if test "${with_pic+set}" = set; then : withval=$with_pic; pic_mode="$withval" else pic_mode=default fi test -z "$pic_mode" && pic_mode=default # Check whether --enable-fast-install was given. if test "${enable_fast_install+set}" = set; then : enableval=$enable_fast_install; p=${PACKAGE-default} case $enableval in yes) enable_fast_install=yes ;; no) enable_fast_install=no ;; *) enable_fast_install=no # Look at the argument we got. We use all the common list separators. lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," for pkg in $enableval; do IFS="$lt_save_ifs" if test "X$pkg" = "X$p"; then enable_fast_install=yes fi done IFS="$lt_save_ifs" ;; esac else enable_fast_install=yes fi # This can be used to rebuild libtool when needed LIBTOOL_DEPS="$ltmain" # Always use our own libtool. LIBTOOL='$(SHELL) $(top_builddir)/libtool' test -z "$LN_S" && LN_S="ln -s" if test -n "${ZSH_VERSION+set}" ; then setopt NO_GLOB_SUBST fi { $as_echo "$as_me:${as_lineno-$LINENO}: checking for objdir" >&5 $as_echo_n "checking for objdir... " >&6; } if ${lt_cv_objdir+:} false; then : $as_echo_n "(cached) " >&6 else rm -f .libs 2>/dev/null mkdir .libs 2>/dev/null if test -d .libs; then lt_cv_objdir=.libs else # MS-DOS does not allow filenames that begin with a dot. lt_cv_objdir=_libs fi rmdir .libs 2>/dev/null fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_objdir" >&5 $as_echo "$lt_cv_objdir" >&6; } objdir=$lt_cv_objdir cat >>confdefs.h <<_ACEOF #define LT_OBJDIR "$lt_cv_objdir/" _ACEOF case $host_os in aix3*) # AIX sometimes has problems with the GCC collect2 program. For some # reason, if we set the COLLECT_NAMES environment variable, the problems # vanish in a puff of smoke. if test "X${COLLECT_NAMES+set}" != Xset; then COLLECT_NAMES= export COLLECT_NAMES fi ;; esac # Global variables: ofile=libtool can_build_shared=yes # All known linkers require a `.a' archive for static linking (except MSVC, # which needs '.lib'). libext=a with_gnu_ld="$lt_cv_prog_gnu_ld" old_CC="$CC" old_CFLAGS="$CFLAGS" # Set sane defaults for various variables test -z "$CC" && CC=cc test -z "$LTCC" && LTCC=$CC test -z "$LTCFLAGS" && LTCFLAGS=$CFLAGS test -z "$LD" && LD=ld test -z "$ac_objext" && ac_objext=o for cc_temp in $compiler""; do case $cc_temp in compile | *[\\/]compile | ccache | *[\\/]ccache ) ;; distcc | *[\\/]distcc | purify | *[\\/]purify ) ;; \-*) ;; *) break;; esac done cc_basename=`$ECHO "$cc_temp" | $SED "s%.*/%%; s%^$host_alias-%%"` # Only perform the check for file, if the check method requires it test -z "$MAGIC_CMD" && MAGIC_CMD=file case $deplibs_check_method in file_magic*) if test "$file_magic_cmd" = '$MAGIC_CMD'; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for ${ac_tool_prefix}file" >&5 $as_echo_n "checking for ${ac_tool_prefix}file... " >&6; } if ${lt_cv_path_MAGIC_CMD+:} false; then : $as_echo_n "(cached) " >&6 else case $MAGIC_CMD in [\\/*] | ?:[\\/]*) lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. ;; *) lt_save_MAGIC_CMD="$MAGIC_CMD" lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR ac_dummy="/usr/bin$PATH_SEPARATOR$PATH" for ac_dir in $ac_dummy; do IFS="$lt_save_ifs" test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/${ac_tool_prefix}file; then lt_cv_path_MAGIC_CMD="$ac_dir/${ac_tool_prefix}file" if test -n "$file_magic_test_file"; then case $deplibs_check_method in "file_magic "*) file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"` MAGIC_CMD="$lt_cv_path_MAGIC_CMD" if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null | $EGREP "$file_magic_regex" > /dev/null; then : else cat <<_LT_EOF 1>&2 *** Warning: the command libtool uses to detect shared libraries, *** $file_magic_cmd, produces output that libtool cannot recognize. *** The result is that libtool may fail to recognize shared libraries *** as such. This will affect the creation of libtool libraries that *** depend on shared libraries, but programs linked with such libtool *** libraries will work regardless of this problem. Nevertheless, you *** may want to report the problem to your system manager and/or to *** bug-libtool@gnu.org _LT_EOF fi ;; esac fi break fi done IFS="$lt_save_ifs" MAGIC_CMD="$lt_save_MAGIC_CMD" ;; esac fi MAGIC_CMD="$lt_cv_path_MAGIC_CMD" if test -n "$MAGIC_CMD"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MAGIC_CMD" >&5 $as_echo "$MAGIC_CMD" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test -z "$lt_cv_path_MAGIC_CMD"; then if test -n "$ac_tool_prefix"; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking for file" >&5 $as_echo_n "checking for file... " >&6; } if ${lt_cv_path_MAGIC_CMD+:} false; then : $as_echo_n "(cached) " >&6 else case $MAGIC_CMD in [\\/*] | ?:[\\/]*) lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. ;; *) lt_save_MAGIC_CMD="$MAGIC_CMD" lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR ac_dummy="/usr/bin$PATH_SEPARATOR$PATH" for ac_dir in $ac_dummy; do IFS="$lt_save_ifs" test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/file; then lt_cv_path_MAGIC_CMD="$ac_dir/file" if test -n "$file_magic_test_file"; then case $deplibs_check_method in "file_magic "*) file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"` MAGIC_CMD="$lt_cv_path_MAGIC_CMD" if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null | $EGREP "$file_magic_regex" > /dev/null; then : else cat <<_LT_EOF 1>&2 *** Warning: the command libtool uses to detect shared libraries, *** $file_magic_cmd, produces output that libtool cannot recognize. *** The result is that libtool may fail to recognize shared libraries *** as such. This will affect the creation of libtool libraries that *** depend on shared libraries, but programs linked with such libtool *** libraries will work regardless of this problem. Nevertheless, you *** may want to report the problem to your system manager and/or to *** bug-libtool@gnu.org _LT_EOF fi ;; esac fi break fi done IFS="$lt_save_ifs" MAGIC_CMD="$lt_save_MAGIC_CMD" ;; esac fi MAGIC_CMD="$lt_cv_path_MAGIC_CMD" if test -n "$MAGIC_CMD"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $MAGIC_CMD" >&5 $as_echo "$MAGIC_CMD" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi else MAGIC_CMD=: fi fi fi ;; esac # Use C for the default configuration in the libtool script lt_save_CC="$CC" ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu # Source file extension for C test sources. ac_ext=c # Object file extension for compiled C test sources. objext=o objext=$objext # Code to be used in simple compile tests lt_simple_compile_test_code="int some_variable = 0;" # Code to be used in simple link tests lt_simple_link_test_code='int main(){return(0);}' # If no C compiler was specified, use CC. LTCC=${LTCC-"$CC"} # If no C compiler flags were specified, use CFLAGS. LTCFLAGS=${LTCFLAGS-"$CFLAGS"} # Allow CC to be a program name with arguments. compiler=$CC # Save the default compiler, since it gets overwritten when the other # tags are being tested, and _LT_TAGVAR(compiler, []) is a NOP. compiler_DEFAULT=$CC # save warnings/boilerplate of simple test code ac_outfile=conftest.$ac_objext echo "$lt_simple_compile_test_code" >conftest.$ac_ext eval "$ac_compile" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err _lt_compiler_boilerplate=`cat conftest.err` $RM conftest* ac_outfile=conftest.$ac_objext echo "$lt_simple_link_test_code" >conftest.$ac_ext eval "$ac_link" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err _lt_linker_boilerplate=`cat conftest.err` $RM -r conftest* if test -n "$compiler"; then lt_prog_compiler_no_builtin_flag= if test "$GCC" = yes; then case $cc_basename in nvcc*) lt_prog_compiler_no_builtin_flag=' -Xcompiler -fno-builtin' ;; *) lt_prog_compiler_no_builtin_flag=' -fno-builtin' ;; esac { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -fno-rtti -fno-exceptions" >&5 $as_echo_n "checking if $compiler supports -fno-rtti -fno-exceptions... " >&6; } if ${lt_cv_prog_compiler_rtti_exceptions+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_prog_compiler_rtti_exceptions=no ac_outfile=conftest.$ac_objext echo "$lt_simple_compile_test_code" > conftest.$ac_ext lt_compiler_flag="-fno-rtti -fno-exceptions" # Insert the option either (1) after the last *FLAGS variable, or # (2) before a word containing "conftest.", or (3) at the end. # Note that $ac_compile itself does not contain backslashes and begins # with a dollar sign (not a hyphen), so the echo should work correctly. # The option is referenced via a variable to avoid confusing sed. lt_compile=`echo "$ac_compile" | $SED \ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' >conftest.exp $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then lt_cv_prog_compiler_rtti_exceptions=yes fi fi $RM conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_rtti_exceptions" >&5 $as_echo "$lt_cv_prog_compiler_rtti_exceptions" >&6; } if test x"$lt_cv_prog_compiler_rtti_exceptions" = xyes; then lt_prog_compiler_no_builtin_flag="$lt_prog_compiler_no_builtin_flag -fno-rtti -fno-exceptions" else : fi fi lt_prog_compiler_wl= lt_prog_compiler_pic= lt_prog_compiler_static= if test "$GCC" = yes; then lt_prog_compiler_wl='-Wl,' lt_prog_compiler_static='-static' case $host_os in aix*) # All AIX code is PIC. if test "$host_cpu" = ia64; then # AIX 5 now supports IA64 processor lt_prog_compiler_static='-Bstatic' fi ;; amigaos*) case $host_cpu in powerpc) # see comment about AmigaOS4 .so support lt_prog_compiler_pic='-fPIC' ;; m68k) # FIXME: we need at least 68020 code to build shared libraries, but # adding the `-m68020' flag to GCC prevents building anything better, # like `-m68040'. lt_prog_compiler_pic='-m68020 -resident32 -malways-restore-a4' ;; esac ;; beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*) # PIC is the default for these OSes. ;; mingw* | cygwin* | pw32* | os2* | cegcc*) # This hack is so that the source file can tell whether it is being # built for inclusion in a dll (and should export symbols for example). # Although the cygwin gcc ignores -fPIC, still need this for old-style # (--disable-auto-import) libraries lt_prog_compiler_pic='-DDLL_EXPORT' ;; darwin* | rhapsody*) # PIC is the default on this platform # Common symbols not allowed in MH_DYLIB files lt_prog_compiler_pic='-fno-common' ;; haiku*) # PIC is the default for Haiku. # The "-static" flag exists, but is broken. lt_prog_compiler_static= ;; hpux*) # PIC is the default for 64-bit PA HP-UX, but not for 32-bit # PA HP-UX. On IA64 HP-UX, PIC is the default but the pic flag # sets the default TLS model and affects inlining. case $host_cpu in hppa*64*) # +Z the default ;; *) lt_prog_compiler_pic='-fPIC' ;; esac ;; interix[3-9]*) # Interix 3.x gcc -fpic/-fPIC options generate broken code. # Instead, we relocate shared libraries at runtime. ;; msdosdjgpp*) # Just because we use GCC doesn't mean we suddenly get shared libraries # on systems that don't support them. lt_prog_compiler_can_build_shared=no enable_shared=no ;; *nto* | *qnx*) # QNX uses GNU C++, but need to define -shared option too, otherwise # it will coredump. lt_prog_compiler_pic='-fPIC -shared' ;; sysv4*MP*) if test -d /usr/nec; then lt_prog_compiler_pic=-Kconform_pic fi ;; *) lt_prog_compiler_pic='-fPIC' ;; esac case $cc_basename in nvcc*) # Cuda Compiler Driver 2.2 lt_prog_compiler_wl='-Xlinker ' lt_prog_compiler_pic='-Xcompiler -fPIC' ;; esac else # PORTME Check for flag to pass linker flags through the system compiler. case $host_os in aix*) lt_prog_compiler_wl='-Wl,' if test "$host_cpu" = ia64; then # AIX 5 now supports IA64 processor lt_prog_compiler_static='-Bstatic' else lt_prog_compiler_static='-bnso -bI:/lib/syscalls.exp' fi ;; mingw* | cygwin* | pw32* | os2* | cegcc*) # This hack is so that the source file can tell whether it is being # built for inclusion in a dll (and should export symbols for example). lt_prog_compiler_pic='-DDLL_EXPORT' ;; hpux9* | hpux10* | hpux11*) lt_prog_compiler_wl='-Wl,' # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in hppa*64*|ia64*) # +Z the default ;; *) lt_prog_compiler_pic='+Z' ;; esac # Is there a better lt_prog_compiler_static that works with the bundled CC? lt_prog_compiler_static='${wl}-a ${wl}archive' ;; irix5* | irix6* | nonstopux*) lt_prog_compiler_wl='-Wl,' # PIC (with -KPIC) is the default. lt_prog_compiler_static='-non_shared' ;; linux* | k*bsd*-gnu | kopensolaris*-gnu) case $cc_basename in # old Intel for x86_64 which still supported -KPIC. ecc*) lt_prog_compiler_wl='-Wl,' lt_prog_compiler_pic='-KPIC' lt_prog_compiler_static='-static' ;; # icc used to be incompatible with GCC. # ICC 10 doesn't accept -KPIC any more. icc* | ifort*) lt_prog_compiler_wl='-Wl,' lt_prog_compiler_pic='-fPIC' lt_prog_compiler_static='-static' ;; # Lahey Fortran 8.1. lf95*) lt_prog_compiler_wl='-Wl,' lt_prog_compiler_pic='--shared' lt_prog_compiler_static='--static' ;; nagfor*) # NAG Fortran compiler lt_prog_compiler_wl='-Wl,-Wl,,' lt_prog_compiler_pic='-PIC' lt_prog_compiler_static='-Bstatic' ;; pgcc* | pgf77* | pgf90* | pgf95* | pgfortran*) # Portland Group compilers (*not* the Pentium gcc compiler, # which looks to be a dead project) lt_prog_compiler_wl='-Wl,' lt_prog_compiler_pic='-fpic' lt_prog_compiler_static='-Bstatic' ;; ccc*) lt_prog_compiler_wl='-Wl,' # All Alpha code is PIC. lt_prog_compiler_static='-non_shared' ;; xl* | bgxl* | bgf* | mpixl*) # IBM XL C 8.0/Fortran 10.1, 11.1 on PPC and BlueGene lt_prog_compiler_wl='-Wl,' lt_prog_compiler_pic='-qpic' lt_prog_compiler_static='-qstaticlink' ;; *) case `$CC -V 2>&1 | sed 5q` in *Sun\ F* | *Sun*Fortran*) # Sun Fortran 8.3 passes all unrecognized flags to the linker lt_prog_compiler_pic='-KPIC' lt_prog_compiler_static='-Bstatic' lt_prog_compiler_wl='' ;; *Sun\ C*) # Sun C 5.9 lt_prog_compiler_pic='-KPIC' lt_prog_compiler_static='-Bstatic' lt_prog_compiler_wl='-Wl,' ;; esac ;; esac ;; newsos6) lt_prog_compiler_pic='-KPIC' lt_prog_compiler_static='-Bstatic' ;; *nto* | *qnx*) # QNX uses GNU C++, but need to define -shared option too, otherwise # it will coredump. lt_prog_compiler_pic='-fPIC -shared' ;; osf3* | osf4* | osf5*) lt_prog_compiler_wl='-Wl,' # All OSF/1 code is PIC. lt_prog_compiler_static='-non_shared' ;; rdos*) lt_prog_compiler_static='-non_shared' ;; solaris*) lt_prog_compiler_pic='-KPIC' lt_prog_compiler_static='-Bstatic' case $cc_basename in f77* | f90* | f95* | sunf77* | sunf90* | sunf95*) lt_prog_compiler_wl='-Qoption ld ';; *) lt_prog_compiler_wl='-Wl,';; esac ;; sunos4*) lt_prog_compiler_wl='-Qoption ld ' lt_prog_compiler_pic='-PIC' lt_prog_compiler_static='-Bstatic' ;; sysv4 | sysv4.2uw2* | sysv4.3*) lt_prog_compiler_wl='-Wl,' lt_prog_compiler_pic='-KPIC' lt_prog_compiler_static='-Bstatic' ;; sysv4*MP*) if test -d /usr/nec ;then lt_prog_compiler_pic='-Kconform_pic' lt_prog_compiler_static='-Bstatic' fi ;; sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*) lt_prog_compiler_wl='-Wl,' lt_prog_compiler_pic='-KPIC' lt_prog_compiler_static='-Bstatic' ;; unicos*) lt_prog_compiler_wl='-Wl,' lt_prog_compiler_can_build_shared=no ;; uts4*) lt_prog_compiler_pic='-pic' lt_prog_compiler_static='-Bstatic' ;; *) lt_prog_compiler_can_build_shared=no ;; esac fi case $host_os in # For platforms which do not support PIC, -DPIC is meaningless: *djgpp*) lt_prog_compiler_pic= ;; *) lt_prog_compiler_pic="$lt_prog_compiler_pic -DPIC" ;; esac { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $compiler option to produce PIC" >&5 $as_echo_n "checking for $compiler option to produce PIC... " >&6; } if ${lt_cv_prog_compiler_pic+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_prog_compiler_pic=$lt_prog_compiler_pic fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_pic" >&5 $as_echo "$lt_cv_prog_compiler_pic" >&6; } lt_prog_compiler_pic=$lt_cv_prog_compiler_pic # # Check to make sure the PIC flag actually works. # if test -n "$lt_prog_compiler_pic"; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler PIC flag $lt_prog_compiler_pic works" >&5 $as_echo_n "checking if $compiler PIC flag $lt_prog_compiler_pic works... " >&6; } if ${lt_cv_prog_compiler_pic_works+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_prog_compiler_pic_works=no ac_outfile=conftest.$ac_objext echo "$lt_simple_compile_test_code" > conftest.$ac_ext lt_compiler_flag="$lt_prog_compiler_pic -DPIC" # Insert the option either (1) after the last *FLAGS variable, or # (2) before a word containing "conftest.", or (3) at the end. # Note that $ac_compile itself does not contain backslashes and begins # with a dollar sign (not a hyphen), so the echo should work correctly. # The option is referenced via a variable to avoid confusing sed. lt_compile=`echo "$ac_compile" | $SED \ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' >conftest.exp $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then lt_cv_prog_compiler_pic_works=yes fi fi $RM conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_pic_works" >&5 $as_echo "$lt_cv_prog_compiler_pic_works" >&6; } if test x"$lt_cv_prog_compiler_pic_works" = xyes; then case $lt_prog_compiler_pic in "" | " "*) ;; *) lt_prog_compiler_pic=" $lt_prog_compiler_pic" ;; esac else lt_prog_compiler_pic= lt_prog_compiler_can_build_shared=no fi fi # # Check to make sure the static flag actually works. # wl=$lt_prog_compiler_wl eval lt_tmp_static_flag=\"$lt_prog_compiler_static\" { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler static flag $lt_tmp_static_flag works" >&5 $as_echo_n "checking if $compiler static flag $lt_tmp_static_flag works... " >&6; } if ${lt_cv_prog_compiler_static_works+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_prog_compiler_static_works=no save_LDFLAGS="$LDFLAGS" LDFLAGS="$LDFLAGS $lt_tmp_static_flag" echo "$lt_simple_link_test_code" > conftest.$ac_ext if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then # The linker can only warn and ignore the option if not recognized # So say no if there are warnings if test -s conftest.err; then # Append any errors to the config.log. cat conftest.err 1>&5 $ECHO "$_lt_linker_boilerplate" | $SED '/^$/d' > conftest.exp $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 if diff conftest.exp conftest.er2 >/dev/null; then lt_cv_prog_compiler_static_works=yes fi else lt_cv_prog_compiler_static_works=yes fi fi $RM -r conftest* LDFLAGS="$save_LDFLAGS" fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_static_works" >&5 $as_echo "$lt_cv_prog_compiler_static_works" >&6; } if test x"$lt_cv_prog_compiler_static_works" = xyes; then : else lt_prog_compiler_static= fi { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -c -o file.$ac_objext" >&5 $as_echo_n "checking if $compiler supports -c -o file.$ac_objext... " >&6; } if ${lt_cv_prog_compiler_c_o+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_prog_compiler_c_o=no $RM -r conftest 2>/dev/null mkdir conftest cd conftest mkdir out echo "$lt_simple_compile_test_code" > conftest.$ac_ext lt_compiler_flag="-o out/conftest2.$ac_objext" # Insert the option either (1) after the last *FLAGS variable, or # (2) before a word containing "conftest.", or (3) at the end. # Note that $ac_compile itself does not contain backslashes and begins # with a dollar sign (not a hyphen), so the echo should work correctly. lt_compile=`echo "$ac_compile" | $SED \ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' > out/conftest.exp $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2 if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then lt_cv_prog_compiler_c_o=yes fi fi chmod u+w . 2>&5 $RM conftest* # SGI C++ compiler will create directory out/ii_files/ for # template instantiation test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files $RM out/* && rmdir out cd .. $RM -r conftest $RM conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_c_o" >&5 $as_echo "$lt_cv_prog_compiler_c_o" >&6; } { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $compiler supports -c -o file.$ac_objext" >&5 $as_echo_n "checking if $compiler supports -c -o file.$ac_objext... " >&6; } if ${lt_cv_prog_compiler_c_o+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_prog_compiler_c_o=no $RM -r conftest 2>/dev/null mkdir conftest cd conftest mkdir out echo "$lt_simple_compile_test_code" > conftest.$ac_ext lt_compiler_flag="-o out/conftest2.$ac_objext" # Insert the option either (1) after the last *FLAGS variable, or # (2) before a word containing "conftest.", or (3) at the end. # Note that $ac_compile itself does not contain backslashes and begins # with a dollar sign (not a hyphen), so the echo should work correctly. lt_compile=`echo "$ac_compile" | $SED \ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [^ ]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&5) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&5 echo "$as_me:$LINENO: \$? = $ac_status" >&5 if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' > out/conftest.exp $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2 if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then lt_cv_prog_compiler_c_o=yes fi fi chmod u+w . 2>&5 $RM conftest* # SGI C++ compiler will create directory out/ii_files/ for # template instantiation test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files $RM out/* && rmdir out cd .. $RM -r conftest $RM conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler_c_o" >&5 $as_echo "$lt_cv_prog_compiler_c_o" >&6; } hard_links="nottested" if test "$lt_cv_prog_compiler_c_o" = no && test "$need_locks" != no; then # do not overwrite the value of need_locks provided by the user { $as_echo "$as_me:${as_lineno-$LINENO}: checking if we can lock with hard links" >&5 $as_echo_n "checking if we can lock with hard links... " >&6; } hard_links=yes $RM conftest* ln conftest.a conftest.b 2>/dev/null && hard_links=no touch conftest.a ln conftest.a conftest.b 2>&5 || hard_links=no ln conftest.a conftest.b 2>/dev/null && hard_links=no { $as_echo "$as_me:${as_lineno-$LINENO}: result: $hard_links" >&5 $as_echo "$hard_links" >&6; } if test "$hard_links" = no; then { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&5 $as_echo "$as_me: WARNING: \`$CC' does not support \`-c -o', so \`make -j' may be unsafe" >&2;} need_locks=warn fi else need_locks=no fi { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the $compiler linker ($LD) supports shared libraries" >&5 $as_echo_n "checking whether the $compiler linker ($LD) supports shared libraries... " >&6; } runpath_var= allow_undefined_flag= always_export_symbols=no archive_cmds= archive_expsym_cmds= compiler_needs_object=no enable_shared_with_static_runtimes=no export_dynamic_flag_spec= export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols' hardcode_automatic=no hardcode_direct=no hardcode_direct_absolute=no hardcode_libdir_flag_spec= hardcode_libdir_flag_spec_ld= hardcode_libdir_separator= hardcode_minus_L=no hardcode_shlibpath_var=unsupported inherit_rpath=no link_all_deplibs=unknown module_cmds= module_expsym_cmds= old_archive_from_new_cmds= old_archive_from_expsyms_cmds= thread_safe_flag_spec= whole_archive_flag_spec= # include_expsyms should be a list of space-separated symbols to be *always* # included in the symbol list include_expsyms= # exclude_expsyms can be an extended regexp of symbols to exclude # it will be wrapped by ` (' and `)$', so one must not match beginning or # end of line. Example: `a|bc|.*d.*' will exclude the symbols `a' and `bc', # as well as any symbol that contains `d'. exclude_expsyms='_GLOBAL_OFFSET_TABLE_|_GLOBAL__F[ID]_.*' # Although _GLOBAL_OFFSET_TABLE_ is a valid symbol C name, most a.out # platforms (ab)use it in PIC code, but their linkers get confused if # the symbol is explicitly referenced. Since portable code cannot # rely on this symbol name, it's probably fine to never include it in # preloaded symbol tables. # Exclude shared library initialization/finalization symbols. extract_expsyms_cmds= case $host_os in cygwin* | mingw* | pw32* | cegcc*) # FIXME: the MSVC++ port hasn't been tested in a loooong time # When not using gcc, we currently assume that we are using # Microsoft Visual C++. if test "$GCC" != yes; then with_gnu_ld=no fi ;; interix*) # we just hope/assume this is gcc and not c89 (= MSVC++) with_gnu_ld=yes ;; openbsd*) with_gnu_ld=no ;; linux* | k*bsd*-gnu | gnu*) link_all_deplibs=no ;; esac ld_shlibs=yes # On some targets, GNU ld is compatible enough with the native linker # that we're better off using the native interface for both. lt_use_gnu_ld_interface=no if test "$with_gnu_ld" = yes; then case $host_os in aix*) # The AIX port of GNU ld has always aspired to compatibility # with the native linker. However, as the warning in the GNU ld # block says, versions before 2.19.5* couldn't really create working # shared libraries, regardless of the interface used. case `$LD -v 2>&1` in *\ \(GNU\ Binutils\)\ 2.19.5*) ;; *\ \(GNU\ Binutils\)\ 2.[2-9]*) ;; *\ \(GNU\ Binutils\)\ [3-9]*) ;; *) lt_use_gnu_ld_interface=yes ;; esac ;; *) lt_use_gnu_ld_interface=yes ;; esac fi if test "$lt_use_gnu_ld_interface" = yes; then # If archive_cmds runs LD, not CC, wlarc should be empty wlarc='${wl}' # Set some defaults for GNU ld with shared library support. These # are reset later if shared libraries are not supported. Putting them # here allows them to be overridden if necessary. runpath_var=LD_RUN_PATH hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' export_dynamic_flag_spec='${wl}--export-dynamic' # ancient GNU ld didn't support --whole-archive et. al. if $LD --help 2>&1 | $GREP 'no-whole-archive' > /dev/null; then whole_archive_flag_spec="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive' else whole_archive_flag_spec= fi supports_anon_versioning=no case `$LD -v 2>&1` in *GNU\ gold*) supports_anon_versioning=yes ;; *\ [01].* | *\ 2.[0-9].* | *\ 2.10.*) ;; # catch versions < 2.11 *\ 2.11.93.0.2\ *) supports_anon_versioning=yes ;; # RH7.3 ... *\ 2.11.92.0.12\ *) supports_anon_versioning=yes ;; # Mandrake 8.2 ... *\ 2.11.*) ;; # other 2.11 versions *) supports_anon_versioning=yes ;; esac # See if GNU ld supports shared libraries. case $host_os in aix[3-9]*) # On AIX/PPC, the GNU linker is very broken if test "$host_cpu" != ia64; then ld_shlibs=no cat <<_LT_EOF 1>&2 *** Warning: the GNU linker, at least up to release 2.19, is reported *** to be unable to reliably create shared libraries on AIX. *** Therefore, libtool is disabling shared libraries support. If you *** really care for shared libraries, you may want to install binutils *** 2.20 or above, or modify your PATH so that a non-GNU linker is found. *** You will then need to restart the configuration process. _LT_EOF fi ;; amigaos*) case $host_cpu in powerpc) # see comment about AmigaOS4 .so support archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' archive_expsym_cmds='' ;; m68k) archive_cmds='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)' hardcode_libdir_flag_spec='-L$libdir' hardcode_minus_L=yes ;; esac ;; beos*) if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then allow_undefined_flag=unsupported # Joseph Beckenbach says some releases of gcc # support --undefined. This deserves some investigation. FIXME archive_cmds='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' else ld_shlibs=no fi ;; cygwin* | mingw* | pw32* | cegcc*) # _LT_TAGVAR(hardcode_libdir_flag_spec, ) is actually meaningless, # as there is no search path for DLLs. hardcode_libdir_flag_spec='-L$libdir' export_dynamic_flag_spec='${wl}--export-all-symbols' allow_undefined_flag=unsupported always_export_symbols=no enable_shared_with_static_runtimes=yes export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[BCDGRS][ ]/s/.*[ ]\([^ ]*\)/\1 DATA/;s/^.*[ ]__nm__\([^ ]*\)[ ][^ ]*/\1 DATA/;/^I[ ]/d;/^[AITW][ ]/s/.* //'\'' | sort | uniq > $export_symbols' exclude_expsyms='[_]+GLOBAL_OFFSET_TABLE_|[_]+GLOBAL__[FID]_.*|[_]+head_[A-Za-z0-9_]+_dll|[A-Za-z0-9_]+_dll_iname' if $LD --help 2>&1 | $GREP 'auto-import' > /dev/null; then archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' # If the export-symbols file already is a .def file (1st line # is EXPORTS), use it as is; otherwise, prepend... archive_expsym_cmds='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then cp $export_symbols $output_objdir/$soname.def; else echo EXPORTS > $output_objdir/$soname.def; cat $export_symbols >> $output_objdir/$soname.def; fi~ $CC -shared $output_objdir/$soname.def $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' else ld_shlibs=no fi ;; haiku*) archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' link_all_deplibs=yes ;; interix[3-9]*) hardcode_direct=no hardcode_shlibpath_var=no hardcode_libdir_flag_spec='${wl}-rpath,$libdir' export_dynamic_flag_spec='${wl}-E' # Hack: On Interix 3.x, we cannot compile PIC because of a broken gcc. # Instead, shared libraries are loaded at an image base (0x10000000 by # default) and relocated if they conflict, which is a slow very memory # consuming and fragmenting process. To avoid this, we pick a random, # 256 KiB-aligned image base between 0x50000000 and 0x6FFC0000 at link # time. Moving up from 0x10000000 also allows more sbrk(2) space. archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' archive_expsym_cmds='sed "s,^,_," $export_symbols >$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--retain-symbols-file,$output_objdir/$soname.expsym ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' ;; gnu* | linux* | tpf* | k*bsd*-gnu | kopensolaris*-gnu) tmp_diet=no if test "$host_os" = linux-dietlibc; then case $cc_basename in diet\ *) tmp_diet=yes;; # linux-dietlibc with static linking (!diet-dyn) esac fi if $LD --help 2>&1 | $EGREP ': supported targets:.* elf' > /dev/null \ && test "$tmp_diet" = no then tmp_addflag=' $pic_flag' tmp_sharedflag='-shared' case $cc_basename,$host_cpu in pgcc*) # Portland Group C compiler whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=' $pic_flag' ;; pgf77* | pgf90* | pgf95* | pgfortran*) # Portland Group f77 and f90 compilers whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=' $pic_flag -Mnomain' ;; ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 tmp_addflag=' -i_dynamic' ;; efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 tmp_addflag=' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 whole_archive_flag_spec= tmp_sharedflag='--shared' ;; xl[cC]* | bgxl[cC]* | mpixl[cC]*) # IBM XL C 8.0 on PPC (deal with xlf below) tmp_sharedflag='-qmkshrobj' tmp_addflag= ;; nvcc*) # Cuda Compiler Driver 2.2 whole_archive_flag_spec='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' compiler_needs_object=yes ;; esac case `$CC -V 2>&1 | sed 5q` in *Sun\ C*) # Sun C 5.9 whole_archive_flag_spec='${wl}--whole-archive`new_convenience=; for conv in $convenience\"\"; do test -z \"$conv\" || new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' compiler_needs_object=yes tmp_sharedflag='-G' ;; *Sun\ F*) # Sun Fortran 8.3 tmp_sharedflag='-G' ;; esac archive_cmds='$CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' if test "x$supports_anon_versioning" = xyes; then archive_expsym_cmds='echo "{ global:" > $output_objdir/$libname.ver~ cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~ echo "local: *; };" >> $output_objdir/$libname.ver~ $CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-version-script ${wl}$output_objdir/$libname.ver -o $lib' fi case $cc_basename in xlf* | bgf* | bgxlf* | mpixlf*) # IBM XL Fortran 10.1 on PPC cannot create shared libs itself whole_archive_flag_spec='--whole-archive$convenience --no-whole-archive' hardcode_libdir_flag_spec= hardcode_libdir_flag_spec_ld='-rpath $libdir' archive_cmds='$LD -shared $libobjs $deplibs $linker_flags -soname $soname -o $lib' if test "x$supports_anon_versioning" = xyes; then archive_expsym_cmds='echo "{ global:" > $output_objdir/$libname.ver~ cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~ echo "local: *; };" >> $output_objdir/$libname.ver~ $LD -shared $libobjs $deplibs $linker_flags -soname $soname -version-script $output_objdir/$libname.ver -o $lib' fi ;; esac else ld_shlibs=no fi ;; netbsd* | netbsdelf*-gnu) if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then archive_cmds='$LD -Bshareable $libobjs $deplibs $linker_flags -o $lib' wlarc= else archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' archive_expsym_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' fi ;; solaris*) if $LD -v 2>&1 | $GREP 'BFD 2\.8' > /dev/null; then ld_shlibs=no cat <<_LT_EOF 1>&2 *** Warning: The releases 2.8.* of the GNU linker cannot reliably *** create shared libraries on Solaris systems. Therefore, libtool *** is disabling shared libraries support. We urge you to upgrade GNU *** binutils to release 2.9.1 or newer. Another option is to modify *** your PATH or compiler configuration so that the native linker is *** used, and then restart. _LT_EOF elif $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' archive_expsym_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' else ld_shlibs=no fi ;; sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX*) case `$LD -v 2>&1` in *\ [01].* | *\ 2.[0-9].* | *\ 2.1[0-5].*) ld_shlibs=no cat <<_LT_EOF 1>&2 *** Warning: Releases of the GNU linker prior to 2.16.91.0.3 can not *** reliably create shared libraries on SCO systems. Therefore, libtool *** is disabling shared libraries support. We urge you to upgrade GNU *** binutils to release 2.16.91.0.3 or newer. Another option is to modify *** your PATH or compiler configuration so that the native linker is *** used, and then restart. _LT_EOF ;; *) # For security reasons, it is highly recommended that you always # use absolute paths for naming shared libraries, and exclude the # DT_RUNPATH tag from executables and libraries. But doing so # requires that you compile everything twice, which is a pain. if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' else ld_shlibs=no fi ;; esac ;; sunos4*) archive_cmds='$LD -assert pure-text -Bshareable -o $lib $libobjs $deplibs $linker_flags' wlarc= hardcode_direct=yes hardcode_shlibpath_var=no ;; *) if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' archive_expsym_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' else ld_shlibs=no fi ;; esac if test "$ld_shlibs" = no; then runpath_var= hardcode_libdir_flag_spec= export_dynamic_flag_spec= whole_archive_flag_spec= fi else # PORTME fill in a description of your system's linker (not GNU ld) case $host_os in aix3*) allow_undefined_flag=unsupported always_export_symbols=yes archive_expsym_cmds='$LD -o $output_objdir/$soname $libobjs $deplibs $linker_flags -bE:$export_symbols -T512 -H512 -bM:SRE~$AR $AR_FLAGS $lib $output_objdir/$soname' # Note: this linker hardcodes the directories in LIBPATH if there # are no directories specified by -L. hardcode_minus_L=yes if test "$GCC" = yes && test -z "$lt_prog_compiler_static"; then # Neither direct hardcoding nor static linking is supported with a # broken collect2. hardcode_direct=unsupported fi ;; aix[4-9]*) if test "$host_cpu" = ia64; then # On IA64, the linker does run time linking by default, so we don't # have to do anything special. aix_use_runtimelinking=no exp_sym_flag='-Bexport' no_entry_flag="" else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global # defined symbols, whereas GNU nm marks them as "W". if $NM -V 2>&1 | $GREP 'GNU' > /dev/null; then export_symbols_cmds='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B") || (\$ 2 == "W")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols' else export_symbols_cmds='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && (substr(\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols' fi aix_use_runtimelinking=no # Test if we are trying to use run time linking or normal # AIX style linking. If -brtl is somewhere in LDFLAGS, we # need to do runtime linking. case $host_os in aix4.[23]|aix4.[23].*|aix[5-9]*) for ld_flag in $LDFLAGS; do if (test $ld_flag = "-brtl" || test $ld_flag = "-Wl,-brtl"); then aix_use_runtimelinking=yes break fi done ;; esac exp_sym_flag='-bexport' no_entry_flag='-bnoentry' fi # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library # or program results in "error TOC overflow" add -mminimal-toc to # CXXFLAGS/CFLAGS for g++/gcc. In the cases where that is not # enough to fix the problem, add -Wl,-bbigtoc to LDFLAGS. archive_cmds='' hardcode_direct=yes hardcode_direct_absolute=yes hardcode_libdir_separator=':' link_all_deplibs=yes file_list_spec='${wl}-f,' if test "$GCC" = yes; then case $host_os in aix4.[012]|aix4.[012].*) # We only want to do this on AIX 4.2 and lower, the check # below for broken collect2 doesn't work under 4.3+ collect2name=`${CC} -print-prog-name=collect2` if test -f "$collect2name" && strings "$collect2name" | $GREP resolve_lib_name >/dev/null then # We have reworked collect2 : else # We have old collect2 hardcode_direct=unsupported # It fails to find uninstalled libraries when the uninstalled # path is not listed in the libpath. Setting hardcode_minus_L # to unsupported forces relinking hardcode_minus_L=yes hardcode_libdir_flag_spec='-L$libdir' hardcode_libdir_separator= fi ;; esac shared_flag='-shared' if test "$aix_use_runtimelinking" = yes; then shared_flag="$shared_flag "'${wl}-G' fi link_all_deplibs=no else # not using gcc if test "$host_cpu" = ia64; then # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release # chokes on -Wl,-G. The following line is correct: shared_flag='-G' else if test "$aix_use_runtimelinking" = yes; then shared_flag='${wl}-G' else shared_flag='${wl}-bM:SRE' fi fi fi export_dynamic_flag_spec='${wl}-bexpall' # It seems that -bexpall does not export symbols beginning with # underscore (_), so it is better to generate a list of symbols to export. always_export_symbols=yes if test "$aix_use_runtimelinking" = yes; then # Warning - without using the other runtime loading flags (-brtl), # -berok will link without error, but may produce a broken library. allow_undefined_flag='-berok' # Determine the default libpath from the value encoded in an # empty executable. if test "${lt_cv_aix_libpath+set}" = set; then aix_libpath=$lt_cv_aix_libpath else if ${lt_cv_aix_libpath_+:} false; then : $as_echo_n "(cached) " >&6 else cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : lt_aix_libpath_sed=' /Import File Strings/,/^$/ { /^0/ { s/^0 *\([^ ]*\) *$/\1/ p } }' lt_cv_aix_libpath_=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` # Check for a 64-bit object if we didn't find anything. if test -z "$lt_cv_aix_libpath_"; then lt_cv_aix_libpath_=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` fi fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext if test -z "$lt_cv_aix_libpath_"; then lt_cv_aix_libpath_="/usr/lib:/lib" fi fi aix_libpath=$lt_cv_aix_libpath_ fi hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath" archive_expsym_cmds='$CC -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else if test "$host_cpu" = ia64; then hardcode_libdir_flag_spec='${wl}-R $libdir:/usr/lib:/lib' allow_undefined_flag="-z nodefs" archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" else # Determine the default libpath from the value encoded in an # empty executable. if test "${lt_cv_aix_libpath+set}" = set; then aix_libpath=$lt_cv_aix_libpath else if ${lt_cv_aix_libpath_+:} false; then : $as_echo_n "(cached) " >&6 else cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : lt_aix_libpath_sed=' /Import File Strings/,/^$/ { /^0/ { s/^0 *\([^ ]*\) *$/\1/ p } }' lt_cv_aix_libpath_=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` # Check for a 64-bit object if we didn't find anything. if test -z "$lt_cv_aix_libpath_"; then lt_cv_aix_libpath_=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` fi fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext if test -z "$lt_cv_aix_libpath_"; then lt_cv_aix_libpath_="/usr/lib:/lib" fi fi aix_libpath=$lt_cv_aix_libpath_ fi hardcode_libdir_flag_spec='${wl}-blibpath:$libdir:'"$aix_libpath" # Warning - without using the other run time loading flags, # -berok will link without error, but may produce a broken library. no_undefined_flag=' ${wl}-bernotok' allow_undefined_flag=' ${wl}-berok' if test "$with_gnu_ld" = yes; then # We only use this code for GNU lds that support --whole-archive. whole_archive_flag_spec='${wl}--whole-archive$convenience ${wl}--no-whole-archive' else # Exported symbols can be pulled into shared objects from archives whole_archive_flag_spec='$convenience' fi archive_cmds_need_lc=yes # This is similar to how AIX traditionally builds its shared libraries. archive_expsym_cmds="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname' fi fi ;; amigaos*) case $host_cpu in powerpc) # see comment about AmigaOS4 .so support archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' archive_expsym_cmds='' ;; m68k) archive_cmds='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)' hardcode_libdir_flag_spec='-L$libdir' hardcode_minus_L=yes ;; esac ;; bsdi[45]*) export_dynamic_flag_spec=-rdynamic ;; cygwin* | mingw* | pw32* | cegcc*) # When not using gcc, we currently assume that we are using # Microsoft Visual C++. # hardcode_libdir_flag_spec is actually meaningless, as there is # no search path for DLLs. case $cc_basename in cl*) # Native MSVC hardcode_libdir_flag_spec=' ' allow_undefined_flag=unsupported always_export_symbols=yes file_list_spec='@' # Tell ltmain to make .lib files, not .a files. libext=lib # Tell ltmain to make .dll files, not .so files. shrext_cmds=".dll" # FIXME: Setting linknames here is a bad hack. archive_cmds='$CC -o $output_objdir/$soname $libobjs $compiler_flags $deplibs -Wl,-dll~linknames=' archive_expsym_cmds='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then sed -n -e 's/\\\\\\\(.*\\\\\\\)/-link\\\ -EXPORT:\\\\\\\1/' -e '1\\\!p' < $export_symbols > $output_objdir/$soname.exp; else sed -e 's/\\\\\\\(.*\\\\\\\)/-link\\\ -EXPORT:\\\\\\\1/' < $export_symbols > $output_objdir/$soname.exp; fi~ $CC -o $tool_output_objdir$soname $libobjs $compiler_flags $deplibs "@$tool_output_objdir$soname.exp" -Wl,-DLL,-IMPLIB:"$tool_output_objdir$libname.dll.lib"~ linknames=' # The linker will not automatically build a static lib if we build a DLL. # _LT_TAGVAR(old_archive_from_new_cmds, )='true' enable_shared_with_static_runtimes=yes export_symbols_cmds='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[BCDGRS][ ]/s/.*[ ]\([^ ]*\)/\1,DATA/'\'' | $SED -e '\''/^[AITW][ ]/s/.*[ ]//'\'' | sort | uniq > $export_symbols' # Don't use ranlib old_postinstall_cmds='chmod 644 $oldlib' postlink_cmds='lt_outputfile="@OUTPUT@"~ lt_tool_outputfile="@TOOL_OUTPUT@"~ case $lt_outputfile in *.exe|*.EXE) ;; *) lt_outputfile="$lt_outputfile.exe" lt_tool_outputfile="$lt_tool_outputfile.exe" ;; esac~ if test "$MANIFEST_TOOL" != ":" && test -f "$lt_outputfile.manifest"; then $MANIFEST_TOOL -manifest "$lt_tool_outputfile.manifest" -outputresource:"$lt_tool_outputfile" || exit 1; $RM "$lt_outputfile.manifest"; fi' ;; *) # Assume MSVC wrapper hardcode_libdir_flag_spec=' ' allow_undefined_flag=unsupported # Tell ltmain to make .lib files, not .a files. libext=lib # Tell ltmain to make .dll files, not .so files. shrext_cmds=".dll" # FIXME: Setting linknames here is a bad hack. archive_cmds='$CC -o $lib $libobjs $compiler_flags `func_echo_all "$deplibs" | $SED '\''s/ -lc$//'\''` -link -dll~linknames=' # The linker will automatically build a .lib file if we build a DLL. old_archive_from_new_cmds='true' # FIXME: Should let the user specify the lib program. old_archive_cmds='lib -OUT:$oldlib$oldobjs$old_deplibs' enable_shared_with_static_runtimes=yes ;; esac ;; darwin* | rhapsody*) archive_cmds_need_lc=no hardcode_direct=no hardcode_automatic=yes hardcode_shlibpath_var=unsupported if test "$lt_cv_ld_force_load" = "yes"; then whole_archive_flag_spec='`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience ${wl}-force_load,$conv\"; done; func_echo_all \"$new_convenience\"`' else whole_archive_flag_spec='' fi link_all_deplibs=yes allow_undefined_flag="$_lt_dar_allow_undefined" case $cc_basename in ifort*) _lt_dar_can_shared=yes ;; *) _lt_dar_can_shared=$GCC ;; esac if test "$_lt_dar_can_shared" = "yes"; then output_verbose_link_cmd=func_echo_all archive_cmds="\$CC -dynamiclib \$allow_undefined_flag -o \$lib \$libobjs \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring $_lt_dar_single_mod${_lt_dsymutil}" module_cmds="\$CC \$allow_undefined_flag -o \$lib -bundle \$libobjs \$deplibs \$compiler_flags${_lt_dsymutil}" archive_expsym_cmds="sed 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC -dynamiclib \$allow_undefined_flag -o \$lib \$libobjs \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring ${_lt_dar_single_mod}${_lt_dar_export_syms}${_lt_dsymutil}" module_expsym_cmds="sed -e 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC \$allow_undefined_flag -o \$lib -bundle \$libobjs \$deplibs \$compiler_flags${_lt_dar_export_syms}${_lt_dsymutil}" else ld_shlibs=no fi ;; dgux*) archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_libdir_flag_spec='-L$libdir' hardcode_shlibpath_var=no ;; freebsd1*) ld_shlibs=no ;; # FreeBSD 2.2.[012] allows us to include c++rt0.o to get C++ constructor # support. Future versions do this automatically, but an explicit c++rt0.o # does not break anything, and helps significantly (at the cost of a little # extra space). freebsd2.2*) archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags /usr/lib/c++rt0.o' hardcode_libdir_flag_spec='-R$libdir' hardcode_direct=yes hardcode_shlibpath_var=no ;; # Unfortunately, older versions of FreeBSD 2 do not have this feature. freebsd2*) archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' hardcode_direct=yes hardcode_minus_L=yes hardcode_shlibpath_var=no ;; # FreeBSD 3 and greater uses gcc -shared to do shared libraries. freebsd* | dragonfly*) archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' hardcode_libdir_flag_spec='-R$libdir' hardcode_direct=yes hardcode_shlibpath_var=no ;; hpux9*) if test "$GCC" = yes; then archive_cmds='$RM $output_objdir/$soname~$CC -shared $pic_flag ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $libobjs $deplibs $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' else archive_cmds='$RM $output_objdir/$soname~$LD -b +b $install_libdir -o $output_objdir/$soname $libobjs $deplibs $linker_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' fi hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' hardcode_libdir_separator=: hardcode_direct=yes # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. hardcode_minus_L=yes export_dynamic_flag_spec='${wl}-E' ;; hpux10*) if test "$GCC" = yes && test "$with_gnu_ld" = no; then archive_cmds='$CC -shared $pic_flag ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags' fi if test "$with_gnu_ld" = no; then hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' hardcode_libdir_flag_spec_ld='+b $libdir' hardcode_libdir_separator=: hardcode_direct=yes hardcode_direct_absolute=yes export_dynamic_flag_spec='${wl}-E' # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. hardcode_minus_L=yes fi ;; hpux11*) if test "$GCC" = yes && test "$with_gnu_ld" = no; then case $host_cpu in hppa*64*) archive_cmds='$CC -shared ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' ;; ia64*) archive_cmds='$CC -shared $pic_flag ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' ;; *) archive_cmds='$CC -shared $pic_flag ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; esac else case $host_cpu in hppa*64*) archive_cmds='$CC -b ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' ;; ia64*) archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' ;; *) # Older versions of the 11.00 compiler do not understand -b yet # (HP92453-01 A.11.01.20 doesn't, HP92453-01 B.11.X.35175-35176.GP does) { $as_echo "$as_me:${as_lineno-$LINENO}: checking if $CC understands -b" >&5 $as_echo_n "checking if $CC understands -b... " >&6; } if ${lt_cv_prog_compiler__b+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_prog_compiler__b=no save_LDFLAGS="$LDFLAGS" LDFLAGS="$LDFLAGS -b" echo "$lt_simple_link_test_code" > conftest.$ac_ext if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then # The linker can only warn and ignore the option if not recognized # So say no if there are warnings if test -s conftest.err; then # Append any errors to the config.log. cat conftest.err 1>&5 $ECHO "$_lt_linker_boilerplate" | $SED '/^$/d' > conftest.exp $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 if diff conftest.exp conftest.er2 >/dev/null; then lt_cv_prog_compiler__b=yes fi else lt_cv_prog_compiler__b=yes fi fi $RM -r conftest* LDFLAGS="$save_LDFLAGS" fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_prog_compiler__b" >&5 $as_echo "$lt_cv_prog_compiler__b" >&6; } if test x"$lt_cv_prog_compiler__b" = xyes; then archive_cmds='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags' fi ;; esac fi if test "$with_gnu_ld" = no; then hardcode_libdir_flag_spec='${wl}+b ${wl}$libdir' hardcode_libdir_separator=: case $host_cpu in hppa*64*|ia64*) hardcode_direct=no hardcode_shlibpath_var=no ;; *) hardcode_direct=yes hardcode_direct_absolute=yes export_dynamic_flag_spec='${wl}-E' # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. hardcode_minus_L=yes ;; esac fi ;; irix5* | irix6* | nonstopux*) if test "$GCC" = yes; then archive_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' # Try to use the -exported_symbol ld option, if it does not # work, assume that -exports_file does not work either and # implicitly export all symbols. # This should be the same for all languages, so no per-tag cache variable. { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether the $host_os linker accepts -exported_symbol" >&5 $as_echo_n "checking whether the $host_os linker accepts -exported_symbol... " >&6; } if ${lt_cv_irix_exported_symbol+:} false; then : $as_echo_n "(cached) " >&6 else save_LDFLAGS="$LDFLAGS" LDFLAGS="$LDFLAGS -shared ${wl}-exported_symbol ${wl}foo ${wl}-update_registry ${wl}/dev/null" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int foo (void) { return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : lt_cv_irix_exported_symbol=yes else lt_cv_irix_exported_symbol=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LDFLAGS="$save_LDFLAGS" fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_irix_exported_symbol" >&5 $as_echo "$lt_cv_irix_exported_symbol" >&6; } if test "$lt_cv_irix_exported_symbol" = yes; then archive_expsym_cmds='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations ${wl}-exports_file ${wl}$export_symbols -o $lib' fi else archive_cmds='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' archive_expsym_cmds='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -exports_file $export_symbols -o $lib' fi archive_cmds_need_lc='no' hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' hardcode_libdir_separator=: inherit_rpath=yes link_all_deplibs=yes ;; netbsd* | netbsdelf*-gnu) if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' # a.out else archive_cmds='$LD -shared -o $lib $libobjs $deplibs $linker_flags' # ELF fi hardcode_libdir_flag_spec='-R$libdir' hardcode_direct=yes hardcode_shlibpath_var=no ;; newsos6) archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_direct=yes hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' hardcode_libdir_separator=: hardcode_shlibpath_var=no ;; *nto* | *qnx*) ;; openbsd*) if test -f /usr/libexec/ld.so; then hardcode_direct=yes hardcode_shlibpath_var=no hardcode_direct_absolute=yes if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-retain-symbols-file,$export_symbols' hardcode_libdir_flag_spec='${wl}-rpath,$libdir' export_dynamic_flag_spec='${wl}-E' else case $host_os in openbsd[01].* | openbsd2.[0-7] | openbsd2.[0-7].*) archive_cmds='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' hardcode_libdir_flag_spec='-R$libdir' ;; *) archive_cmds='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' hardcode_libdir_flag_spec='${wl}-rpath,$libdir' ;; esac fi else ld_shlibs=no fi ;; os2*) hardcode_libdir_flag_spec='-L$libdir' hardcode_minus_L=yes allow_undefined_flag=unsupported archive_cmds='$ECHO "LIBRARY $libname INITINSTANCE" > $output_objdir/$libname.def~$ECHO "DESCRIPTION \"$libname\"" >> $output_objdir/$libname.def~echo DATA >> $output_objdir/$libname.def~echo " SINGLE NONSHARED" >> $output_objdir/$libname.def~echo EXPORTS >> $output_objdir/$libname.def~emxexp $libobjs >> $output_objdir/$libname.def~$CC -Zdll -Zcrtdll -o $lib $libobjs $deplibs $compiler_flags $output_objdir/$libname.def' old_archive_from_new_cmds='emximp -o $output_objdir/$libname.a $output_objdir/$libname.def' ;; osf3*) if test "$GCC" = yes; then allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*' archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' else allow_undefined_flag=' -expect_unresolved \*' archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' fi archive_cmds_need_lc='no' hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' hardcode_libdir_separator=: ;; osf4* | osf5*) # as osf3* with the addition of -msym flag if test "$GCC" = yes; then allow_undefined_flag=' ${wl}-expect_unresolved ${wl}\*' archive_cmds='$CC -shared${allow_undefined_flag} $pic_flag $libobjs $deplibs $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' hardcode_libdir_flag_spec='${wl}-rpath ${wl}$libdir' else allow_undefined_flag=' -expect_unresolved \*' archive_cmds='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -msym -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' archive_expsym_cmds='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done; printf "%s\\n" "-hidden">> $lib.exp~ $CC -shared${allow_undefined_flag} ${wl}-input ${wl}$lib.exp $compiler_flags $libobjs $deplibs -soname $soname `test -n "$verstring" && $ECHO "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib~$RM $lib.exp' # Both c and cxx compiler support -rpath directly hardcode_libdir_flag_spec='-rpath $libdir' fi archive_cmds_need_lc='no' hardcode_libdir_separator=: ;; solaris*) no_undefined_flag=' -z defs' if test "$GCC" = yes; then wlarc='${wl}' archive_cmds='$CC -shared $pic_flag ${wl}-z ${wl}text ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ $CC -shared $pic_flag ${wl}-z ${wl}text ${wl}-M ${wl}$lib.exp ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp' else case `$CC -V 2>&1` in *"Compilers 5.0"*) wlarc='' archive_cmds='$LD -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $linker_flags' archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ $LD -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $linker_flags~$RM $lib.exp' ;; *) wlarc='${wl}' archive_cmds='$CC -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ $CC -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp' ;; esac fi hardcode_libdir_flag_spec='-R$libdir' hardcode_shlibpath_var=no case $host_os in solaris2.[0-5] | solaris2.[0-5].*) ;; *) # The compiler driver will combine and reorder linker options, # but understands `-z linker_flag'. GCC discards it without `$wl', # but is careful enough not to reorder. # Supported since Solaris 2.6 (maybe 2.5.1?) if test "$GCC" = yes; then whole_archive_flag_spec='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract' else whole_archive_flag_spec='-z allextract$convenience -z defaultextract' fi ;; esac link_all_deplibs=yes ;; sunos4*) if test "x$host_vendor" = xsequent; then # Use $CC to link under sequent, because it throws in some extra .o # files that make .init and .fini sections work. archive_cmds='$CC -G ${wl}-h $soname -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds='$LD -assert pure-text -Bstatic -o $lib $libobjs $deplibs $linker_flags' fi hardcode_libdir_flag_spec='-L$libdir' hardcode_direct=yes hardcode_minus_L=yes hardcode_shlibpath_var=no ;; sysv4) case $host_vendor in sni) archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_direct=yes # is this really true??? ;; siemens) ## LD is ld it makes a PLAMLIB ## CC just makes a GrossModule. archive_cmds='$LD -G -o $lib $libobjs $deplibs $linker_flags' reload_cmds='$CC -r -o $output$reload_objs' hardcode_direct=no ;; motorola) archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_direct=no #Motorola manual says yes, but my tests say they lie ;; esac runpath_var='LD_RUN_PATH' hardcode_shlibpath_var=no ;; sysv4.3*) archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_shlibpath_var=no export_dynamic_flag_spec='-Bexport' ;; sysv4*MP*) if test -d /usr/nec; then archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_shlibpath_var=no runpath_var=LD_RUN_PATH hardcode_runpath_var=yes ld_shlibs=yes fi ;; sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[01].[10]* | unixware7* | sco3.2v5.0.[024]*) no_undefined_flag='${wl}-z,text' archive_cmds_need_lc=no hardcode_shlibpath_var=no runpath_var='LD_RUN_PATH' if test "$GCC" = yes; then archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' fi ;; sysv5* | sco3.2v5* | sco5v6*) # Note: We can NOT use -z defs as we might desire, because we do not # link with -lc, and that would cause any symbols used from libc to # always be unresolved, which means just about no library would # ever link correctly. If we're not using GNU ld we use -z text # though, which does catch some bad symbols but isn't as heavy-handed # as -z defs. no_undefined_flag='${wl}-z,text' allow_undefined_flag='${wl}-z,nodefs' archive_cmds_need_lc=no hardcode_shlibpath_var=no hardcode_libdir_flag_spec='${wl}-R,$libdir' hardcode_libdir_separator=':' link_all_deplibs=yes export_dynamic_flag_spec='${wl}-Bexport' runpath_var='LD_RUN_PATH' if test "$GCC" = yes; then archive_cmds='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' else archive_cmds='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' archive_expsym_cmds='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' fi ;; uts4*) archive_cmds='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' hardcode_libdir_flag_spec='-L$libdir' hardcode_shlibpath_var=no ;; *) ld_shlibs=no ;; esac if test x$host_vendor = xsni; then case $host in sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*) export_dynamic_flag_spec='${wl}-Blargedynsym' ;; esac fi fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ld_shlibs" >&5 $as_echo "$ld_shlibs" >&6; } test "$ld_shlibs" = no && can_build_shared=no with_gnu_ld=$with_gnu_ld # # Do we need to explicitly link libc? # case "x$archive_cmds_need_lc" in x|xyes) # Assume -lc should be added archive_cmds_need_lc=yes if test "$enable_shared" = yes && test "$GCC" = yes; then case $archive_cmds in *'~'*) # FIXME: we may have to deal with multi-command sequences. ;; '$CC '*) # Test whether the compiler implicitly links with -lc since on some # systems, -lgcc has to come before -lc. If gcc already passes -lc # to ld, don't add -lc before -lgcc. { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether -lc should be explicitly linked in" >&5 $as_echo_n "checking whether -lc should be explicitly linked in... " >&6; } if ${lt_cv_archive_cmds_need_lc+:} false; then : $as_echo_n "(cached) " >&6 else $RM conftest* echo "$lt_simple_compile_test_code" > conftest.$ac_ext if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_compile\""; } >&5 (eval $ac_compile) 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } 2>conftest.err; then soname=conftest lib=conftest libobjs=conftest.$ac_objext deplibs= wl=$lt_prog_compiler_wl pic_flag=$lt_prog_compiler_pic compiler_flags=-v linker_flags=-v verstring= output_objdir=. libname=conftest lt_save_allow_undefined_flag=$allow_undefined_flag allow_undefined_flag= if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$archive_cmds 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1\""; } >&5 (eval $archive_cmds 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1) 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } then lt_cv_archive_cmds_need_lc=no else lt_cv_archive_cmds_need_lc=yes fi allow_undefined_flag=$lt_save_allow_undefined_flag else cat conftest.err 1>&5 fi $RM conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_archive_cmds_need_lc" >&5 $as_echo "$lt_cv_archive_cmds_need_lc" >&6; } archive_cmds_need_lc=$lt_cv_archive_cmds_need_lc ;; esac fi ;; esac { $as_echo "$as_me:${as_lineno-$LINENO}: checking dynamic linker characteristics" >&5 $as_echo_n "checking dynamic linker characteristics... " >&6; } if test "$GCC" = yes; then case $host_os in darwin*) lt_awk_arg="/^libraries:/,/LR/" ;; *) lt_awk_arg="/^libraries:/" ;; esac case $host_os in mingw* | cegcc*) lt_sed_strip_eq="s,=\([A-Za-z]:\),\1,g" ;; *) lt_sed_strip_eq="s,=/,/,g" ;; esac lt_search_path_spec=`$CC -print-search-dirs | awk $lt_awk_arg | $SED -e "s/^libraries://" -e $lt_sed_strip_eq` case $lt_search_path_spec in *\;*) # if the path contains ";" then we assume it to be the separator # otherwise default to the standard path separator (i.e. ":") - it is # assumed that no part of a normal pathname contains ";" but that should # okay in the real world where ";" in dirpaths is itself problematic. lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED 's/;/ /g'` ;; *) lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED "s/$PATH_SEPARATOR/ /g"` ;; esac # Ok, now we have the path, separated by spaces, we can step through it # and add multilib dir if necessary. lt_tmp_lt_search_path_spec= lt_multi_os_dir=`$CC $CPPFLAGS $CFLAGS $LDFLAGS -print-multi-os-directory 2>/dev/null` for lt_sys_path in $lt_search_path_spec; do if test -d "$lt_sys_path/$lt_multi_os_dir"; then lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path/$lt_multi_os_dir" else test -d "$lt_sys_path" && \ lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path" fi done lt_search_path_spec=`$ECHO "$lt_tmp_lt_search_path_spec" | awk ' BEGIN {RS=" "; FS="/|\n";} { lt_foo=""; lt_count=0; for (lt_i = NF; lt_i > 0; lt_i--) { if ($lt_i != "" && $lt_i != ".") { if ($lt_i == "..") { lt_count++; } else { if (lt_count == 0) { lt_foo="/" $lt_i lt_foo; } else { lt_count--; } } } } if (lt_foo != "") { lt_freq[lt_foo]++; } if (lt_freq[lt_foo] == 1) { print lt_foo; } }'` # AWK program above erroneously prepends '/' to C:/dos/paths # for these hosts. case $host_os in mingw* | cegcc*) lt_search_path_spec=`$ECHO "$lt_search_path_spec" |\ $SED 's,/\([A-Za-z]:\),\1,g'` ;; esac sys_lib_search_path_spec=`$ECHO "$lt_search_path_spec" | $lt_NL2SP` else sys_lib_search_path_spec="/lib /usr/lib /usr/local/lib" fi library_names_spec= libname_spec='lib$name' soname_spec= shrext_cmds=".so" postinstall_cmds= postuninstall_cmds= finish_cmds= finish_eval= shlibpath_var= shlibpath_overrides_runpath=unknown version_type=none dynamic_linker="$host_os ld.so" sys_lib_dlsearch_path_spec="/lib /usr/lib" need_lib_prefix=unknown hardcode_into_libs=no # when you set need_version to no, make sure it does not cause -set_version # flags to be left without arguments need_version=unknown case $host_os in aix3*) version_type=linux library_names_spec='${libname}${release}${shared_ext}$versuffix $libname.a' shlibpath_var=LIBPATH # AIX 3 has no versioning support, so we append a major version to the name. soname_spec='${libname}${release}${shared_ext}$major' ;; aix[4-9]*) version_type=linux need_lib_prefix=no need_version=no hardcode_into_libs=yes if test "$host_cpu" = ia64; then # AIX 5 supports IA64 library_names_spec='${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext}$versuffix $libname${shared_ext}' shlibpath_var=LD_LIBRARY_PATH else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to # depend on `.', always an invalid library. This was fixed in # development snapshots of GCC prior to 3.0. case $host_os in aix4 | aix4.[01] | aix4.[01].*) if { echo '#if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 97)' echo ' yes ' echo '#endif'; } | ${CC} -E - | $GREP yes > /dev/null; then : else can_build_shared=no fi ;; esac # AIX (on Power*) has no versioning support, so currently we can not hardcode correct # soname into executable. Probably we can add versioning support to # collect2, so additional links can be useful in future. if test "$aix_use_runtimelinking" = yes; then # If using run time linking (on AIX 4.2 or later) use lib.so # instead of lib.a to let people know that these are not # typical AIX shared libraries. library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' else # We preserve .a as extension for shared libraries through AIX4.2 # and later when we are not doing run time linking. library_names_spec='${libname}${release}.a $libname.a' soname_spec='${libname}${release}${shared_ext}$major' fi shlibpath_var=LIBPATH fi ;; amigaos*) case $host_cpu in powerpc) # Since July 2007 AmigaOS4 officially supports .so libraries. # When compiling the executable, add -use-dynld -Lsobjs: to the compileline. library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' ;; m68k) library_names_spec='$libname.ixlibrary $libname.a' # Create ${libname}_ixlibrary.a entries in /sys/libs. finish_eval='for lib in `ls $libdir/*.ixlibrary 2>/dev/null`; do libname=`func_echo_all "$lib" | $SED '\''s%^.*/\([^/]*\)\.ixlibrary$%\1%'\''`; test $RM /sys/libs/${libname}_ixlibrary.a; $show "cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a"; cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a || exit 1; done' ;; esac ;; beos*) library_names_spec='${libname}${shared_ext}' dynamic_linker="$host_os ld.so" shlibpath_var=LIBRARY_PATH ;; bsdi[45]*) version_type=linux need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' finish_cmds='PATH="\$PATH:/sbin" ldconfig $libdir' shlibpath_var=LD_LIBRARY_PATH sys_lib_search_path_spec="/shlib /usr/lib /usr/X11/lib /usr/contrib/lib /lib /usr/local/lib" sys_lib_dlsearch_path_spec="/shlib /usr/lib /usr/local/lib" # the default ld.so.conf also contains /usr/contrib/lib and # /usr/X11R6/lib (/usr/X11 is a link to /usr/X11R6), but let us allow # libtool to hard-code these into programs ;; cygwin* | mingw* | pw32* | cegcc*) version_type=windows shrext_cmds=".dll" need_version=no need_lib_prefix=no case $GCC,$cc_basename in yes,*) # gcc library_names_spec='$libname.dll.a' # DLL is installed to $(libdir)/../bin by postinstall_cmds postinstall_cmds='base_file=`basename \${file}`~ dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~ dldir=$destdir/`dirname \$dlpath`~ test -d \$dldir || mkdir -p \$dldir~ $install_prog $dir/$dlname \$dldir/$dlname~ chmod a+x \$dldir/$dlname~ if test -n '\''$stripme'\'' && test -n '\''$striplib'\''; then eval '\''$striplib \$dldir/$dlname'\'' || exit \$?; fi' postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~ dlpath=$dir/\$dldll~ $RM \$dlpath' shlibpath_overrides_runpath=yes case $host_os in cygwin*) # Cygwin DLLs use 'cyg' prefix rather than 'lib' soname_spec='`echo ${libname} | sed -e 's/^lib/cyg/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/lib/w32api" ;; mingw* | cegcc*) # MinGW DLLs use traditional 'lib' prefix soname_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' ;; pw32*) # pw32 DLLs use 'pw' prefix rather than 'lib' library_names_spec='`echo ${libname} | sed -e 's/^lib/pw/'``echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' ;; esac dynamic_linker='Win32 ld.exe' ;; *,cl*) # Native MSVC libname_spec='$name' soname_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext}' library_names_spec='${libname}.dll.lib' case $build_os in mingw*) sys_lib_search_path_spec= lt_save_ifs=$IFS IFS=';' for lt_path in $LIB do IFS=$lt_save_ifs # Let DOS variable expansion print the short 8.3 style file name. lt_path=`cd "$lt_path" 2>/dev/null && cmd //C "for %i in (".") do @echo %~si"` sys_lib_search_path_spec="$sys_lib_search_path_spec $lt_path" done IFS=$lt_save_ifs # Convert to MSYS style. sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | sed -e 's|\\\\|/|g' -e 's| \\([a-zA-Z]\\):| /\\1|g' -e 's|^ ||'` ;; cygwin*) # Convert to unix form, then to dos form, then back to unix form # but this time dos style (no spaces!) so that the unix form looks # like /cygdrive/c/PROGRA~1:/cygdr... sys_lib_search_path_spec=`cygpath --path --unix "$LIB"` sys_lib_search_path_spec=`cygpath --path --dos "$sys_lib_search_path_spec" 2>/dev/null` sys_lib_search_path_spec=`cygpath --path --unix "$sys_lib_search_path_spec" | $SED -e "s/$PATH_SEPARATOR/ /g"` ;; *) sys_lib_search_path_spec="$LIB" if $ECHO "$sys_lib_search_path_spec" | $GREP ';[c-zC-Z]:/' >/dev/null; then # It is most probably a Windows format PATH. sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED -e 's/;/ /g'` else sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED -e "s/$PATH_SEPARATOR/ /g"` fi # FIXME: find the short name or the path components, as spaces are # common. (e.g. "Program Files" -> "PROGRA~1") ;; esac # DLL is installed to $(libdir)/../bin by postinstall_cmds postinstall_cmds='base_file=`basename \${file}`~ dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~ dldir=$destdir/`dirname \$dlpath`~ test -d \$dldir || mkdir -p \$dldir~ $install_prog $dir/$dlname \$dldir/$dlname' postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~ dlpath=$dir/\$dldll~ $RM \$dlpath' shlibpath_overrides_runpath=yes dynamic_linker='Win32 link.exe' ;; *) # Assume MSVC wrapper library_names_spec='${libname}`echo ${release} | $SED -e 's/[.]/-/g'`${versuffix}${shared_ext} $libname.lib' dynamic_linker='Win32 ld.exe' ;; esac # FIXME: first we should search . and the directory the executable is in shlibpath_var=PATH ;; darwin* | rhapsody*) dynamic_linker="$host_os dyld" version_type=darwin need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${major}$shared_ext ${libname}$shared_ext' soname_spec='${libname}${release}${major}$shared_ext' shlibpath_overrides_runpath=yes shlibpath_var=DYLD_LIBRARY_PATH shrext_cmds='`test .$module = .yes && echo .so || echo .dylib`' sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/local/lib" sys_lib_dlsearch_path_spec='/usr/local/lib /lib /usr/lib' ;; dgux*) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname$shared_ext' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH ;; freebsd1*) dynamic_linker=no ;; freebsd* | dragonfly*) # DragonFly does not have aout. When/if they implement a new # versioning mechanism, adjust this. if test -x /usr/bin/objformat; then objformat=`/usr/bin/objformat` else case $host_os in freebsd[123]*) objformat=aout ;; *) objformat=elf ;; esac fi version_type=freebsd-$objformat case $version_type in freebsd-elf*) library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}' need_version=no need_lib_prefix=no ;; freebsd-*) library_names_spec='${libname}${release}${shared_ext}$versuffix $libname${shared_ext}$versuffix' need_version=yes ;; esac shlibpath_var=LD_LIBRARY_PATH case $host_os in freebsd2*) shlibpath_overrides_runpath=yes ;; freebsd3.[01]* | freebsdelf3.[01]*) shlibpath_overrides_runpath=yes hardcode_into_libs=yes ;; freebsd3.[2-9]* | freebsdelf3.[2-9]* | \ freebsd4.[0-5] | freebsdelf4.[0-5] | freebsd4.1.1 | freebsdelf4.1.1) shlibpath_overrides_runpath=no hardcode_into_libs=yes ;; *) # from 4.6 on, and DragonFly shlibpath_overrides_runpath=yes hardcode_into_libs=yes ;; esac ;; gnu*) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=no hardcode_into_libs=yes ;; haiku*) version_type=linux need_lib_prefix=no need_version=no dynamic_linker="$host_os runtime_loader" library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LIBRARY_PATH shlibpath_overrides_runpath=yes sys_lib_dlsearch_path_spec='/boot/home/config/lib /boot/common/lib /boot/system/lib' hardcode_into_libs=yes ;; hpux9* | hpux10* | hpux11*) # Give a soname corresponding to the major version so that dld.sl refuses to # link against other versions. version_type=sunos need_lib_prefix=no need_version=no case $host_cpu in ia64*) shrext_cmds='.so' hardcode_into_libs=yes dynamic_linker="$host_os dld.so" shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=yes # Unless +noenvvar is specified. library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' if test "X$HPUX_IA64_MODE" = X32; then sys_lib_search_path_spec="/usr/lib/hpux32 /usr/local/lib/hpux32 /usr/local/lib" else sys_lib_search_path_spec="/usr/lib/hpux64 /usr/local/lib/hpux64" fi sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec ;; hppa*64*) shrext_cmds='.sl' hardcode_into_libs=yes dynamic_linker="$host_os dld.sl" shlibpath_var=LD_LIBRARY_PATH # How should we handle SHLIB_PATH shlibpath_overrides_runpath=yes # Unless +noenvvar is specified. library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' sys_lib_search_path_spec="/usr/lib/pa20_64 /usr/ccs/lib/pa20_64" sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec ;; *) shrext_cmds='.sl' dynamic_linker="$host_os dld.sl" shlibpath_var=SHLIB_PATH shlibpath_overrides_runpath=no # +s is required to enable SHLIB_PATH library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' ;; esac # HP-UX runs *really* slowly unless shared libraries are mode 555, ... postinstall_cmds='chmod 555 $lib' # or fails outright, so override atomically: install_override_mode=555 ;; interix[3-9]*) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' dynamic_linker='Interix 3.x ld.so.1 (PE, like ELF)' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=no hardcode_into_libs=yes ;; irix5* | irix6* | nonstopux*) case $host_os in nonstopux*) version_type=nonstopux ;; *) if test "$lt_cv_prog_gnu_ld" = yes; then version_type=linux else version_type=irix fi ;; esac need_lib_prefix=no need_version=no soname_spec='${libname}${release}${shared_ext}$major' library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext} $libname${shared_ext}' case $host_os in irix5* | nonstopux*) libsuff= shlibsuff= ;; *) case $LD in # libtool.m4 will add one of these switches to LD *-32|*"-32 "|*-melf32bsmip|*"-melf32bsmip ") libsuff= shlibsuff= libmagic=32-bit;; *-n32|*"-n32 "|*-melf32bmipn32|*"-melf32bmipn32 ") libsuff=32 shlibsuff=N32 libmagic=N32;; *-64|*"-64 "|*-melf64bmip|*"-melf64bmip ") libsuff=64 shlibsuff=64 libmagic=64-bit;; *) libsuff= shlibsuff= libmagic=never-match;; esac ;; esac shlibpath_var=LD_LIBRARY${shlibsuff}_PATH shlibpath_overrides_runpath=no sys_lib_search_path_spec="/usr/lib${libsuff} /lib${libsuff} /usr/local/lib${libsuff}" sys_lib_dlsearch_path_spec="/usr/lib${libsuff} /lib${libsuff}" hardcode_into_libs=yes ;; # No shared lib support for Linux oldld, aout, or coff. linux*oldld* | linux*aout* | linux*coff*) dynamic_linker=no ;; # This must be Linux ELF. linux* | k*bsd*-gnu | kopensolaris*-gnu) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' finish_cmds='PATH="\$PATH:/sbin" ldconfig -n $libdir' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=no # Some binutils ld are patched to set DT_RUNPATH if ${lt_cv_shlibpath_overrides_runpath+:} false; then : $as_echo_n "(cached) " >&6 else lt_cv_shlibpath_overrides_runpath=no save_LDFLAGS=$LDFLAGS save_libdir=$libdir eval "libdir=/foo; wl=\"$lt_prog_compiler_wl\"; \ LDFLAGS=\"\$LDFLAGS $hardcode_libdir_flag_spec\"" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : if ($OBJDUMP -p conftest$ac_exeext) 2>/dev/null | grep "RUNPATH.*$libdir" >/dev/null; then : lt_cv_shlibpath_overrides_runpath=yes fi fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LDFLAGS=$save_LDFLAGS libdir=$save_libdir fi shlibpath_overrides_runpath=$lt_cv_shlibpath_overrides_runpath # This implies no fast_install, which is unacceptable. # Some rework will be needed to allow for fast_install # before this can be enabled. hardcode_into_libs=yes # Append ld.so.conf contents to the search path if test -f /etc/ld.so.conf; then lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \$2)); skip = 1; } { if (!skip) print \$0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '` sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra" fi # We used to test for /lib/ld.so.1 and disable shared libraries on # powerpc, because MkLinux only supported shared libraries with the # GNU dynamic linker. Since this was broken with cross compilers, # most powerpc-linux boxes support dynamic linking these days and # people can always --disable-shared, the test was removed, and we # assume the GNU/Linux dynamic linker is in use. dynamic_linker='GNU/Linux ld.so' ;; netbsdelf*-gnu) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=no hardcode_into_libs=yes dynamic_linker='NetBSD ld.elf_so' ;; netbsd*) version_type=sunos need_lib_prefix=no need_version=no if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir' dynamic_linker='NetBSD (a.out) ld.so' else library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' dynamic_linker='NetBSD ld.elf_so' fi shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=yes hardcode_into_libs=yes ;; newsos6) version_type=linux library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=yes ;; *nto* | *qnx*) version_type=qnx need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=no hardcode_into_libs=yes dynamic_linker='ldqnx.so' ;; openbsd*) version_type=sunos sys_lib_dlsearch_path_spec="/usr/lib" need_lib_prefix=no # Some older versions of OpenBSD (3.3 at least) *do* need versioned libs. case $host_os in openbsd3.3 | openbsd3.3.*) need_version=yes ;; *) need_version=no ;; esac library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir' shlibpath_var=LD_LIBRARY_PATH if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then case $host_os in openbsd2.[89] | openbsd2.[89].*) shlibpath_overrides_runpath=no ;; *) shlibpath_overrides_runpath=yes ;; esac else shlibpath_overrides_runpath=yes fi ;; os2*) libname_spec='$name' shrext_cmds=".dll" need_lib_prefix=no library_names_spec='$libname${shared_ext} $libname.a' dynamic_linker='OS/2 ld.exe' shlibpath_var=LIBPATH ;; osf3* | osf4* | osf5*) version_type=osf need_lib_prefix=no need_version=no soname_spec='${libname}${release}${shared_ext}$major' library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' shlibpath_var=LD_LIBRARY_PATH sys_lib_search_path_spec="/usr/shlib /usr/ccs/lib /usr/lib/cmplrs/cc /usr/lib /usr/local/lib /var/shlib" sys_lib_dlsearch_path_spec="$sys_lib_search_path_spec" ;; rdos*) dynamic_linker=no ;; solaris*) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=yes hardcode_into_libs=yes # ldd complains unless libraries are executable postinstall_cmds='chmod +x $lib' ;; sunos4*) version_type=sunos library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' finish_cmds='PATH="\$PATH:/usr/etc" ldconfig $libdir' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=yes if test "$with_gnu_ld" = yes; then need_lib_prefix=no fi need_version=yes ;; sysv4 | sysv4.3*) version_type=linux library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH case $host_vendor in sni) shlibpath_overrides_runpath=no need_lib_prefix=no runpath_var=LD_RUN_PATH ;; siemens) need_lib_prefix=no ;; motorola) need_lib_prefix=no need_version=no shlibpath_overrides_runpath=no sys_lib_search_path_spec='/lib /usr/lib /usr/ccs/lib' ;; esac ;; sysv4*MP*) if test -d /usr/nec ;then version_type=linux library_names_spec='$libname${shared_ext}.$versuffix $libname${shared_ext}.$major $libname${shared_ext}' soname_spec='$libname${shared_ext}.$major' shlibpath_var=LD_LIBRARY_PATH fi ;; sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*) version_type=freebsd-elf need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=yes hardcode_into_libs=yes if test "$with_gnu_ld" = yes; then sys_lib_search_path_spec='/usr/local/lib /usr/gnu/lib /usr/ccs/lib /usr/lib /lib' else sys_lib_search_path_spec='/usr/ccs/lib /usr/lib' case $host_os in sco3.2v5*) sys_lib_search_path_spec="$sys_lib_search_path_spec /lib" ;; esac fi sys_lib_dlsearch_path_spec='/usr/lib' ;; tpf*) # TPF is a cross-target only. Preferred cross-host = GNU/Linux. version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=no hardcode_into_libs=yes ;; uts4*) version_type=linux library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH ;; *) dynamic_linker=no ;; esac { $as_echo "$as_me:${as_lineno-$LINENO}: result: $dynamic_linker" >&5 $as_echo "$dynamic_linker" >&6; } test "$dynamic_linker" = no && can_build_shared=no variables_saved_for_relink="PATH $shlibpath_var $runpath_var" if test "$GCC" = yes; then variables_saved_for_relink="$variables_saved_for_relink GCC_EXEC_PREFIX COMPILER_PATH LIBRARY_PATH" fi if test "${lt_cv_sys_lib_search_path_spec+set}" = set; then sys_lib_search_path_spec="$lt_cv_sys_lib_search_path_spec" fi if test "${lt_cv_sys_lib_dlsearch_path_spec+set}" = set; then sys_lib_dlsearch_path_spec="$lt_cv_sys_lib_dlsearch_path_spec" fi { $as_echo "$as_me:${as_lineno-$LINENO}: checking how to hardcode library paths into programs" >&5 $as_echo_n "checking how to hardcode library paths into programs... " >&6; } hardcode_action= if test -n "$hardcode_libdir_flag_spec" || test -n "$runpath_var" || test "X$hardcode_automatic" = "Xyes" ; then # We can hardcode non-existent directories. if test "$hardcode_direct" != no && # If the only mechanism to avoid hardcoding is shlibpath_var, we # have to relink, otherwise we might link with an installed library # when we should be linking with a yet-to-be-installed one ## test "$_LT_TAGVAR(hardcode_shlibpath_var, )" != no && test "$hardcode_minus_L" != no; then # Linking always hardcodes the temporary library directory. hardcode_action=relink else # We can link without hardcoding, and we can hardcode nonexisting dirs. hardcode_action=immediate fi else # We cannot hardcode anything, or else we can only hardcode existing # directories. hardcode_action=unsupported fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $hardcode_action" >&5 $as_echo "$hardcode_action" >&6; } if test "$hardcode_action" = relink || test "$inherit_rpath" = yes; then # Fast installation is not supported enable_fast_install=no elif test "$shlibpath_overrides_runpath" = yes || test "$enable_shared" = no; then # Fast installation is not necessary enable_fast_install=needless fi if test "x$enable_dlopen" != xyes; then enable_dlopen=unknown enable_dlopen_self=unknown enable_dlopen_self_static=unknown else lt_cv_dlopen=no lt_cv_dlopen_libs= case $host_os in beos*) lt_cv_dlopen="load_add_on" lt_cv_dlopen_libs= lt_cv_dlopen_self=yes ;; mingw* | pw32* | cegcc*) lt_cv_dlopen="LoadLibrary" lt_cv_dlopen_libs= ;; cygwin*) lt_cv_dlopen="dlopen" lt_cv_dlopen_libs= ;; darwin*) # if libdl is installed we need to link against it { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -ldl" >&5 $as_echo_n "checking for dlopen in -ldl... " >&6; } if ${ac_cv_lib_dl_dlopen+:} false; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldl $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dlopen (); int main () { return dlopen (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_dl_dlopen=yes else ac_cv_lib_dl_dlopen=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dl_dlopen" >&5 $as_echo "$ac_cv_lib_dl_dlopen" >&6; } if test "x$ac_cv_lib_dl_dlopen" = xyes; then : lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl" else lt_cv_dlopen="dyld" lt_cv_dlopen_libs= lt_cv_dlopen_self=yes fi ;; *) ac_fn_c_check_func "$LINENO" "shl_load" "ac_cv_func_shl_load" if test "x$ac_cv_func_shl_load" = xyes; then : lt_cv_dlopen="shl_load" else { $as_echo "$as_me:${as_lineno-$LINENO}: checking for shl_load in -ldld" >&5 $as_echo_n "checking for shl_load in -ldld... " >&6; } if ${ac_cv_lib_dld_shl_load+:} false; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldld $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char shl_load (); int main () { return shl_load (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_dld_shl_load=yes else ac_cv_lib_dld_shl_load=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dld_shl_load" >&5 $as_echo "$ac_cv_lib_dld_shl_load" >&6; } if test "x$ac_cv_lib_dld_shl_load" = xyes; then : lt_cv_dlopen="shl_load" lt_cv_dlopen_libs="-ldld" else ac_fn_c_check_func "$LINENO" "dlopen" "ac_cv_func_dlopen" if test "x$ac_cv_func_dlopen" = xyes; then : lt_cv_dlopen="dlopen" else { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -ldl" >&5 $as_echo_n "checking for dlopen in -ldl... " >&6; } if ${ac_cv_lib_dl_dlopen+:} false; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldl $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dlopen (); int main () { return dlopen (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_dl_dlopen=yes else ac_cv_lib_dl_dlopen=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dl_dlopen" >&5 $as_echo "$ac_cv_lib_dl_dlopen" >&6; } if test "x$ac_cv_lib_dl_dlopen" = xyes; then : lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl" else { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dlopen in -lsvld" >&5 $as_echo_n "checking for dlopen in -lsvld... " >&6; } if ${ac_cv_lib_svld_dlopen+:} false; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-lsvld $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dlopen (); int main () { return dlopen (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_svld_dlopen=yes else ac_cv_lib_svld_dlopen=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_svld_dlopen" >&5 $as_echo "$ac_cv_lib_svld_dlopen" >&6; } if test "x$ac_cv_lib_svld_dlopen" = xyes; then : lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-lsvld" else { $as_echo "$as_me:${as_lineno-$LINENO}: checking for dld_link in -ldld" >&5 $as_echo_n "checking for dld_link in -ldld... " >&6; } if ${ac_cv_lib_dld_dld_link+:} false; then : $as_echo_n "(cached) " >&6 else ac_check_lib_save_LIBS=$LIBS LIBS="-ldld $LIBS" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ /* Override any GCC internal prototype to avoid an error. Use char because int might match the return type of a GCC builtin and then its argument prototype would still apply. */ #ifdef __cplusplus extern "C" #endif char dld_link (); int main () { return dld_link (); ; return 0; } _ACEOF if ac_fn_c_try_link "$LINENO"; then : ac_cv_lib_dld_dld_link=yes else ac_cv_lib_dld_dld_link=no fi rm -f core conftest.err conftest.$ac_objext \ conftest$ac_exeext conftest.$ac_ext LIBS=$ac_check_lib_save_LIBS fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_cv_lib_dld_dld_link" >&5 $as_echo "$ac_cv_lib_dld_dld_link" >&6; } if test "x$ac_cv_lib_dld_dld_link" = xyes; then : lt_cv_dlopen="dld_link" lt_cv_dlopen_libs="-ldld" fi fi fi fi fi fi ;; esac if test "x$lt_cv_dlopen" != xno; then enable_dlopen=yes else enable_dlopen=no fi case $lt_cv_dlopen in dlopen) save_CPPFLAGS="$CPPFLAGS" test "x$ac_cv_header_dlfcn_h" = xyes && CPPFLAGS="$CPPFLAGS -DHAVE_DLFCN_H" save_LDFLAGS="$LDFLAGS" wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $export_dynamic_flag_spec\" save_LIBS="$LIBS" LIBS="$lt_cv_dlopen_libs $LIBS" { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether a program can dlopen itself" >&5 $as_echo_n "checking whether a program can dlopen itself... " >&6; } if ${lt_cv_dlopen_self+:} false; then : $as_echo_n "(cached) " >&6 else if test "$cross_compiling" = yes; then : lt_cv_dlopen_self=cross else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF #line $LINENO "configure" #include "confdefs.h" #if HAVE_DLFCN_H #include #endif #include #ifdef RTLD_GLOBAL # define LT_DLGLOBAL RTLD_GLOBAL #else # ifdef DL_GLOBAL # define LT_DLGLOBAL DL_GLOBAL # else # define LT_DLGLOBAL 0 # endif #endif /* We may have to define LT_DLLAZY_OR_NOW in the command line if we find out it does not work in some platform. */ #ifndef LT_DLLAZY_OR_NOW # ifdef RTLD_LAZY # define LT_DLLAZY_OR_NOW RTLD_LAZY # else # ifdef DL_LAZY # define LT_DLLAZY_OR_NOW DL_LAZY # else # ifdef RTLD_NOW # define LT_DLLAZY_OR_NOW RTLD_NOW # else # ifdef DL_NOW # define LT_DLLAZY_OR_NOW DL_NOW # else # define LT_DLLAZY_OR_NOW 0 # endif # endif # endif # endif #endif /* When -fvisbility=hidden is used, assume the code has been annotated correspondingly for the symbols needed. */ #if defined(__GNUC__) && (((__GNUC__ == 3) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 3)) int fnord () __attribute__((visibility("default"))); #endif int fnord () { return 42; } int main () { void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW); int status = $lt_dlunknown; if (self) { if (dlsym (self,"fnord")) status = $lt_dlno_uscore; else { if (dlsym( self,"_fnord")) status = $lt_dlneed_uscore; else puts (dlerror ()); } /* dlclose (self); */ } else puts (dlerror ()); return status; } _LT_EOF if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_link\""; } >&5 (eval $ac_link) 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } && test -s conftest${ac_exeext} 2>/dev/null; then (./conftest; exit; ) >&5 2>/dev/null lt_status=$? case x$lt_status in x$lt_dlno_uscore) lt_cv_dlopen_self=yes ;; x$lt_dlneed_uscore) lt_cv_dlopen_self=yes ;; x$lt_dlunknown|x*) lt_cv_dlopen_self=no ;; esac else : # compilation failed lt_cv_dlopen_self=no fi fi rm -fr conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_dlopen_self" >&5 $as_echo "$lt_cv_dlopen_self" >&6; } if test "x$lt_cv_dlopen_self" = xyes; then wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $lt_prog_compiler_static\" { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether a statically linked program can dlopen itself" >&5 $as_echo_n "checking whether a statically linked program can dlopen itself... " >&6; } if ${lt_cv_dlopen_self_static+:} false; then : $as_echo_n "(cached) " >&6 else if test "$cross_compiling" = yes; then : lt_cv_dlopen_self_static=cross else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF #line $LINENO "configure" #include "confdefs.h" #if HAVE_DLFCN_H #include #endif #include #ifdef RTLD_GLOBAL # define LT_DLGLOBAL RTLD_GLOBAL #else # ifdef DL_GLOBAL # define LT_DLGLOBAL DL_GLOBAL # else # define LT_DLGLOBAL 0 # endif #endif /* We may have to define LT_DLLAZY_OR_NOW in the command line if we find out it does not work in some platform. */ #ifndef LT_DLLAZY_OR_NOW # ifdef RTLD_LAZY # define LT_DLLAZY_OR_NOW RTLD_LAZY # else # ifdef DL_LAZY # define LT_DLLAZY_OR_NOW DL_LAZY # else # ifdef RTLD_NOW # define LT_DLLAZY_OR_NOW RTLD_NOW # else # ifdef DL_NOW # define LT_DLLAZY_OR_NOW DL_NOW # else # define LT_DLLAZY_OR_NOW 0 # endif # endif # endif # endif #endif /* When -fvisbility=hidden is used, assume the code has been annotated correspondingly for the symbols needed. */ #if defined(__GNUC__) && (((__GNUC__ == 3) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 3)) int fnord () __attribute__((visibility("default"))); #endif int fnord () { return 42; } int main () { void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW); int status = $lt_dlunknown; if (self) { if (dlsym (self,"fnord")) status = $lt_dlno_uscore; else { if (dlsym( self,"_fnord")) status = $lt_dlneed_uscore; else puts (dlerror ()); } /* dlclose (self); */ } else puts (dlerror ()); return status; } _LT_EOF if { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_link\""; } >&5 (eval $ac_link) 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; } && test -s conftest${ac_exeext} 2>/dev/null; then (./conftest; exit; ) >&5 2>/dev/null lt_status=$? case x$lt_status in x$lt_dlno_uscore) lt_cv_dlopen_self_static=yes ;; x$lt_dlneed_uscore) lt_cv_dlopen_self_static=yes ;; x$lt_dlunknown|x*) lt_cv_dlopen_self_static=no ;; esac else : # compilation failed lt_cv_dlopen_self_static=no fi fi rm -fr conftest* fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $lt_cv_dlopen_self_static" >&5 $as_echo "$lt_cv_dlopen_self_static" >&6; } fi CPPFLAGS="$save_CPPFLAGS" LDFLAGS="$save_LDFLAGS" LIBS="$save_LIBS" ;; esac case $lt_cv_dlopen_self in yes|no) enable_dlopen_self=$lt_cv_dlopen_self ;; *) enable_dlopen_self=unknown ;; esac case $lt_cv_dlopen_self_static in yes|no) enable_dlopen_self_static=$lt_cv_dlopen_self_static ;; *) enable_dlopen_self_static=unknown ;; esac fi striplib= old_striplib= { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether stripping libraries is possible" >&5 $as_echo_n "checking whether stripping libraries is possible... " >&6; } if test -n "$STRIP" && $STRIP -V 2>&1 | $GREP "GNU strip" >/dev/null; then test -z "$old_striplib" && old_striplib="$STRIP --strip-debug" test -z "$striplib" && striplib="$STRIP --strip-unneeded" { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } else # FIXME - insert some real tests, host_os isn't really good enough case $host_os in darwin*) if test -n "$STRIP" ; then striplib="$STRIP -x" old_striplib="$STRIP -S" { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi ;; *) { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } ;; esac fi # Report which library types will actually be built { $as_echo "$as_me:${as_lineno-$LINENO}: checking if libtool supports shared libraries" >&5 $as_echo_n "checking if libtool supports shared libraries... " >&6; } { $as_echo "$as_me:${as_lineno-$LINENO}: result: $can_build_shared" >&5 $as_echo "$can_build_shared" >&6; } { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to build shared libraries" >&5 $as_echo_n "checking whether to build shared libraries... " >&6; } test "$can_build_shared" = "no" && enable_shared=no # On AIX, shared libraries and static libraries use the same namespace, and # are all built from PIC. case $host_os in aix3*) test "$enable_shared" = yes && enable_static=no if test -n "$RANLIB"; then archive_cmds="$archive_cmds~\$RANLIB \$lib" postinstall_cmds='$RANLIB $lib' fi ;; aix[4-9]*) if test "$host_cpu" != ia64 && test "$aix_use_runtimelinking" = no ; then test "$enable_shared" = yes && enable_static=no fi ;; esac { $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_shared" >&5 $as_echo "$enable_shared" >&6; } { $as_echo "$as_me:${as_lineno-$LINENO}: checking whether to build static libraries" >&5 $as_echo_n "checking whether to build static libraries... " >&6; } # Make sure either enable_shared or enable_static is yes. test "$enable_shared" = yes || enable_static=yes { $as_echo "$as_me:${as_lineno-$LINENO}: result: $enable_static" >&5 $as_echo "$enable_static" >&6; } fi ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu CC="$lt_save_CC" ac_config_commands="$ac_config_commands libtool" # Only expand once: { $as_echo "$as_me:${as_lineno-$LINENO}: checking to see if compiler understands -Wall" >&5 $as_echo_n "checking to see if compiler understands -Wall... " >&6; } save_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS -Wall" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_compile "$LINENO"; then : flag_ok=yes else flag_ok=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext CFLAGS="$save_CFLAGS" if test "X$flag_ok" = Xyes ; then GST_WALL="yes" true else GST_WALL="no" true fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $flag_ok" >&5 $as_echo "$flag_ok" >&6; } if test "x$GST_WALL" = "xyes"; then GST_ERROR="$GST_ERROR -Wall" if test "x$GST_PLUGIN_CVS" = "xyes"; then { $as_echo "$as_me:${as_lineno-$LINENO}: checking to see if compiler understands -Werror" >&5 $as_echo_n "checking to see if compiler understands -Werror... " >&6; } save_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS -Werror" cat confdefs.h - <<_ACEOF >conftest.$ac_ext /* end confdefs.h. */ int main () { ; return 0; } _ACEOF if ac_fn_c_try_compile "$LINENO"; then : flag_ok=yes else flag_ok=no fi rm -f core conftest.err conftest.$ac_objext conftest.$ac_ext CFLAGS="$save_CFLAGS" if test "X$flag_ok" = Xyes ; then GST_ERROR="$GST_ERROR -Werror" true else GST_ERROR="$GST_ERROR" true fi { $as_echo "$as_me:${as_lineno-$LINENO}: result: $flag_ok" >&5 $as_echo "$flag_ok" >&6; } fi fi # Extract the first word of "pkg-config", so it can be a program name with args. set dummy pkg-config; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_HAVE_PKGCONFIG+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$HAVE_PKGCONFIG"; then ac_cv_prog_HAVE_PKGCONFIG="$HAVE_PKGCONFIG" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_HAVE_PKGCONFIG="yes" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS test -z "$ac_cv_prog_HAVE_PKGCONFIG" && ac_cv_prog_HAVE_PKGCONFIG="no" fi fi HAVE_PKGCONFIG=$ac_cv_prog_HAVE_PKGCONFIG if test -n "$HAVE_PKGCONFIG"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $HAVE_PKGCONFIG" >&5 $as_echo "$HAVE_PKGCONFIG" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$HAVE_PKGCONFIG" = "xno"; then as_fn_error $? "you need to have pkgconfig installed !" "$LINENO" 5 fi if test "x$ac_cv_env_PKG_CONFIG_set" != "xset"; then if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}pkg-config", so it can be a program name with args. set dummy ${ac_tool_prefix}pkg-config; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_path_PKG_CONFIG+:} false; then : $as_echo_n "(cached) " >&6 else case $PKG_CONFIG in [\\/]* | ?:[\\/]*) ac_cv_path_PKG_CONFIG="$PKG_CONFIG" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_path_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi PKG_CONFIG=$ac_cv_path_PKG_CONFIG if test -n "$PKG_CONFIG"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $PKG_CONFIG" >&5 $as_echo "$PKG_CONFIG" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$ac_cv_path_PKG_CONFIG"; then ac_pt_PKG_CONFIG=$PKG_CONFIG # Extract the first word of "pkg-config", so it can be a program name with args. set dummy pkg-config; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_path_ac_pt_PKG_CONFIG+:} false; then : $as_echo_n "(cached) " >&6 else case $ac_pt_PKG_CONFIG in [\\/]* | ?:[\\/]*) ac_cv_path_ac_pt_PKG_CONFIG="$ac_pt_PKG_CONFIG" # Let the user override the test with a path. ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_path_ac_pt_PKG_CONFIG="$as_dir/$ac_word$ac_exec_ext" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS ;; esac fi ac_pt_PKG_CONFIG=$ac_cv_path_ac_pt_PKG_CONFIG if test -n "$ac_pt_PKG_CONFIG"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_pt_PKG_CONFIG" >&5 $as_echo "$ac_pt_PKG_CONFIG" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$ac_pt_PKG_CONFIG" = x; then PKG_CONFIG="" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac PKG_CONFIG=$ac_pt_PKG_CONFIG fi else PKG_CONFIG="$ac_cv_path_PKG_CONFIG" fi fi if test -n "$PKG_CONFIG"; then _pkg_min_version=0.9.0 { $as_echo "$as_me:${as_lineno-$LINENO}: checking pkg-config is at least version $_pkg_min_version" >&5 $as_echo_n "checking pkg-config is at least version $_pkg_min_version... " >&6; } if $PKG_CONFIG --atleast-pkgconfig-version $_pkg_min_version; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } PKG_CONFIG="" fi fi pkg_failed=no { $as_echo "$as_me:${as_lineno-$LINENO}: checking for GST" >&5 $as_echo_n "checking for GST... " >&6; } if test -n "$GST_CFLAGS"; then pkg_cv_GST_CFLAGS="$GST_CFLAGS" elif test -n "$PKG_CONFIG"; then if test -n "$PKG_CONFIG" && \ { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"\\ gstreamer-\$GST_MAJORMINOR >= \$GST_REQUIRED gstreamer-video-0.10\""; } >&5 ($PKG_CONFIG --exists --print-errors "\ gstreamer-$GST_MAJORMINOR >= $GST_REQUIRED gstreamer-video-0.10") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then pkg_cv_GST_CFLAGS=`$PKG_CONFIG --cflags "\ gstreamer-$GST_MAJORMINOR >= $GST_REQUIRED gstreamer-video-0.10" 2>/dev/null` test "x$?" != "x0" && pkg_failed=yes else pkg_failed=yes fi else pkg_failed=untried fi if test -n "$GST_LIBS"; then pkg_cv_GST_LIBS="$GST_LIBS" elif test -n "$PKG_CONFIG"; then if test -n "$PKG_CONFIG" && \ { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"\\ gstreamer-\$GST_MAJORMINOR >= \$GST_REQUIRED gstreamer-video-0.10\""; } >&5 ($PKG_CONFIG --exists --print-errors "\ gstreamer-$GST_MAJORMINOR >= $GST_REQUIRED gstreamer-video-0.10") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then pkg_cv_GST_LIBS=`$PKG_CONFIG --libs "\ gstreamer-$GST_MAJORMINOR >= $GST_REQUIRED gstreamer-video-0.10" 2>/dev/null` test "x$?" != "x0" && pkg_failed=yes else pkg_failed=yes fi else pkg_failed=untried fi if test $pkg_failed = yes; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then _pkg_short_errors_supported=yes else _pkg_short_errors_supported=no fi if test $_pkg_short_errors_supported = yes; then GST_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "\ gstreamer-$GST_MAJORMINOR >= $GST_REQUIRED gstreamer-video-0.10" 2>&1` else GST_PKG_ERRORS=`$PKG_CONFIG --print-errors --cflags --libs "\ gstreamer-$GST_MAJORMINOR >= $GST_REQUIRED gstreamer-video-0.10" 2>&1` fi # Put the nasty error message in config.log where it belongs echo "$GST_PKG_ERRORS" >&5 HAVE_GST=no elif test $pkg_failed = untried; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } HAVE_GST=no else GST_CFLAGS=$pkg_cv_GST_CFLAGS GST_LIBS=$pkg_cv_GST_LIBS { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } HAVE_GST=yes fi if test "x$HAVE_GST" = "xno"; then as_fn_error $? "you need gstreamer development packages installed !" "$LINENO" 5 fi GST_CFLAGS="$GST_CFLAGS $GST_ERROR" pkg_failed=no { $as_echo "$as_me:${as_lineno-$LINENO}: checking for GST_BASE" >&5 $as_echo_n "checking for GST_BASE... " >&6; } if test -n "$GST_BASE_CFLAGS"; then pkg_cv_GST_BASE_CFLAGS="$GST_BASE_CFLAGS" elif test -n "$PKG_CONFIG"; then if test -n "$PKG_CONFIG" && \ { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"gstreamer-base-\$GST_MAJORMINOR >= \$GST_REQUIRED\""; } >&5 ($PKG_CONFIG --exists --print-errors "gstreamer-base-$GST_MAJORMINOR >= $GST_REQUIRED") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then pkg_cv_GST_BASE_CFLAGS=`$PKG_CONFIG --cflags "gstreamer-base-$GST_MAJORMINOR >= $GST_REQUIRED" 2>/dev/null` test "x$?" != "x0" && pkg_failed=yes else pkg_failed=yes fi else pkg_failed=untried fi if test -n "$GST_BASE_LIBS"; then pkg_cv_GST_BASE_LIBS="$GST_BASE_LIBS" elif test -n "$PKG_CONFIG"; then if test -n "$PKG_CONFIG" && \ { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"gstreamer-base-\$GST_MAJORMINOR >= \$GST_REQUIRED\""; } >&5 ($PKG_CONFIG --exists --print-errors "gstreamer-base-$GST_MAJORMINOR >= $GST_REQUIRED") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then pkg_cv_GST_BASE_LIBS=`$PKG_CONFIG --libs "gstreamer-base-$GST_MAJORMINOR >= $GST_REQUIRED" 2>/dev/null` test "x$?" != "x0" && pkg_failed=yes else pkg_failed=yes fi else pkg_failed=untried fi if test $pkg_failed = yes; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then _pkg_short_errors_supported=yes else _pkg_short_errors_supported=no fi if test $_pkg_short_errors_supported = yes; then GST_BASE_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "gstreamer-base-$GST_MAJORMINOR >= $GST_REQUIRED" 2>&1` else GST_BASE_PKG_ERRORS=`$PKG_CONFIG --print-errors --cflags --libs "gstreamer-base-$GST_MAJORMINOR >= $GST_REQUIRED" 2>&1` fi # Put the nasty error message in config.log where it belongs echo "$GST_BASE_PKG_ERRORS" >&5 HAVE_GST_BASE=no elif test $pkg_failed = untried; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } HAVE_GST_BASE=no else GST_BASE_CFLAGS=$pkg_cv_GST_BASE_CFLAGS GST_BASE_LIBS=$pkg_cv_GST_BASE_LIBS { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } HAVE_GST_BASE=yes fi if test "x$HAVE_GST_BASE" = "xno"; then { $as_echo "$as_me:${as_lineno-$LINENO}: no GStreamer base class libraries found (gstreamer-base-$GST_MAJORMINOR)" >&5 $as_echo "$as_me: no GStreamer base class libraries found (gstreamer-base-$GST_MAJORMINOR)" >&6;} fi pkg_failed=no { $as_echo "$as_me:${as_lineno-$LINENO}: checking for GSTPB_BASE" >&5 $as_echo_n "checking for GSTPB_BASE... " >&6; } if test -n "$GSTPB_BASE_CFLAGS"; then pkg_cv_GSTPB_BASE_CFLAGS="$GSTPB_BASE_CFLAGS" elif test -n "$PKG_CONFIG"; then if test -n "$PKG_CONFIG" && \ { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"gstreamer-plugins-base-\$GST_MAJORMINOR >= \$GSTPB_REQUIRED\""; } >&5 ($PKG_CONFIG --exists --print-errors "gstreamer-plugins-base-$GST_MAJORMINOR >= $GSTPB_REQUIRED") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then pkg_cv_GSTPB_BASE_CFLAGS=`$PKG_CONFIG --cflags "gstreamer-plugins-base-$GST_MAJORMINOR >= $GSTPB_REQUIRED" 2>/dev/null` test "x$?" != "x0" && pkg_failed=yes else pkg_failed=yes fi else pkg_failed=untried fi if test -n "$GSTPB_BASE_LIBS"; then pkg_cv_GSTPB_BASE_LIBS="$GSTPB_BASE_LIBS" elif test -n "$PKG_CONFIG"; then if test -n "$PKG_CONFIG" && \ { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"gstreamer-plugins-base-\$GST_MAJORMINOR >= \$GSTPB_REQUIRED\""; } >&5 ($PKG_CONFIG --exists --print-errors "gstreamer-plugins-base-$GST_MAJORMINOR >= $GSTPB_REQUIRED") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then pkg_cv_GSTPB_BASE_LIBS=`$PKG_CONFIG --libs "gstreamer-plugins-base-$GST_MAJORMINOR >= $GSTPB_REQUIRED" 2>/dev/null` test "x$?" != "x0" && pkg_failed=yes else pkg_failed=yes fi else pkg_failed=untried fi if test $pkg_failed = yes; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then _pkg_short_errors_supported=yes else _pkg_short_errors_supported=no fi if test $_pkg_short_errors_supported = yes; then GSTPB_BASE_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "gstreamer-plugins-base-$GST_MAJORMINOR >= $GSTPB_REQUIRED" 2>&1` else GSTPB_BASE_PKG_ERRORS=`$PKG_CONFIG --print-errors --cflags --libs "gstreamer-plugins-base-$GST_MAJORMINOR >= $GSTPB_REQUIRED" 2>&1` fi # Put the nasty error message in config.log where it belongs echo "$GSTPB_BASE_PKG_ERRORS" >&5 HAVE_GSTPB_BASE=no elif test $pkg_failed = untried; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } HAVE_GSTPB_BASE=no else GSTPB_BASE_CFLAGS=$pkg_cv_GSTPB_BASE_CFLAGS GSTPB_BASE_LIBS=$pkg_cv_GSTPB_BASE_LIBS { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } HAVE_GSTPB_BASE=yes fi if test "x$HAVE_GSTPB_BASE" = "xno"; then { $as_echo "$as_me:${as_lineno-$LINENO}: no GStreamer Plugins Base libraries found (gstreamer-plugins-base-$GST_MAJORMINOR)" >&5 $as_echo "$as_me: no GStreamer Plugins Base libraries found (gstreamer-plugins-base-$GST_MAJORMINOR)" >&6;} fi pkg_failed=no { $as_echo "$as_me:${as_lineno-$LINENO}: checking for GSTCTRL" >&5 $as_echo_n "checking for GSTCTRL... " >&6; } if test -n "$GSTCTRL_CFLAGS"; then pkg_cv_GSTCTRL_CFLAGS="$GSTCTRL_CFLAGS" elif test -n "$PKG_CONFIG"; then if test -n "$PKG_CONFIG" && \ { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"gstreamer-controller-\$GST_MAJORMINOR >= \$GSTPB_REQUIRED\""; } >&5 ($PKG_CONFIG --exists --print-errors "gstreamer-controller-$GST_MAJORMINOR >= $GSTPB_REQUIRED") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then pkg_cv_GSTCTRL_CFLAGS=`$PKG_CONFIG --cflags "gstreamer-controller-$GST_MAJORMINOR >= $GSTPB_REQUIRED" 2>/dev/null` test "x$?" != "x0" && pkg_failed=yes else pkg_failed=yes fi else pkg_failed=untried fi if test -n "$GSTCTRL_LIBS"; then pkg_cv_GSTCTRL_LIBS="$GSTCTRL_LIBS" elif test -n "$PKG_CONFIG"; then if test -n "$PKG_CONFIG" && \ { { $as_echo "$as_me:${as_lineno-$LINENO}: \$PKG_CONFIG --exists --print-errors \"gstreamer-controller-\$GST_MAJORMINOR >= \$GSTPB_REQUIRED\""; } >&5 ($PKG_CONFIG --exists --print-errors "gstreamer-controller-$GST_MAJORMINOR >= $GSTPB_REQUIRED") 2>&5 ac_status=$? $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 test $ac_status = 0; }; then pkg_cv_GSTCTRL_LIBS=`$PKG_CONFIG --libs "gstreamer-controller-$GST_MAJORMINOR >= $GSTPB_REQUIRED" 2>/dev/null` test "x$?" != "x0" && pkg_failed=yes else pkg_failed=yes fi else pkg_failed=untried fi if test $pkg_failed = yes; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then _pkg_short_errors_supported=yes else _pkg_short_errors_supported=no fi if test $_pkg_short_errors_supported = yes; then GSTCTRL_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "gstreamer-controller-$GST_MAJORMINOR >= $GSTPB_REQUIRED" 2>&1` else GSTCTRL_PKG_ERRORS=`$PKG_CONFIG --print-errors --cflags --libs "gstreamer-controller-$GST_MAJORMINOR >= $GSTPB_REQUIRED" 2>&1` fi # Put the nasty error message in config.log where it belongs echo "$GSTCTRL_PKG_ERRORS" >&5 HAVE_GSTCTRL=no elif test $pkg_failed = untried; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } HAVE_GSTCTRL=no else GSTCTRL_CFLAGS=$pkg_cv_GSTCTRL_CFLAGS GSTCTRL_LIBS=$pkg_cv_GSTCTRL_LIBS { $as_echo "$as_me:${as_lineno-$LINENO}: result: yes" >&5 $as_echo "yes" >&6; } HAVE_GSTCTRL=yes fi if test "x$HAVE_GSTCTRL" = "xno"; then { $as_echo "$as_me:${as_lineno-$LINENO}: no GStreamer Controller libraries found (gstreamer-controller-$GST_MAJORMINOR)" >&5 $as_echo "$as_me: no GStreamer Controller libraries found (gstreamer-controller-$GST_MAJORMINOR)" >&6;} fi if test "x${prefix}" = "x$HOME"; then plugindir="$HOME/.gstreamer-$GST_MAJORMINOR/plugins" else plugindir="\$(libdir)/gstreamer-$GST_MAJORMINOR" fi GST_PLUGIN_LDFLAGS='-module -avoid-version -export-symbols-regex _*\(gst_\|Gst\|GST_\).*' ac_config_files="$ac_config_files Makefile m4/Makefile src/Makefile" cat >confcache <<\_ACEOF # This file is a shell script that caches the results of configure # tests run on this system so they can be shared between configure # scripts and configure runs, see configure's option --config-cache. # It is not useful on other systems. If it contains results you don't # want to keep, you may remove or edit it. # # config.status only pays attention to the cache file if you give it # the --recheck option to rerun configure. # # `ac_cv_env_foo' variables (set or unset) will be overridden when # loading this file, other *unset* `ac_cv_foo' will be assigned the # following values. _ACEOF # The following way of writing the cache mishandles newlines in values, # but we know of no workaround that is simple, portable, and efficient. # So, we kill variables containing newlines. # Ultrix sh set writes to stderr and can't be redirected directly, # and sets the high bit in the cache file unless we assign to the vars. ( for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do eval ac_val=\$$ac_var case $ac_val in #( *${as_nl}*) case $ac_var in #( *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 $as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; esac case $ac_var in #( _ | IFS | as_nl) ;; #( BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( *) { eval $ac_var=; unset $ac_var;} ;; esac ;; esac done (set) 2>&1 | case $as_nl`(ac_space=' '; set) 2>&1` in #( *${as_nl}ac_space=\ *) # `set' does not quote correctly, so add quotes: double-quote # substitution turns \\\\ into \\, and sed turns \\ into \. sed -n \ "s/'/'\\\\''/g; s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" ;; #( *) # `set' quotes correctly as required by POSIX, so do not add quotes. sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" ;; esac | sort ) | sed ' /^ac_cv_env_/b end t clear :clear s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ t end s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ :end' >>confcache if diff "$cache_file" confcache >/dev/null 2>&1; then :; else if test -w "$cache_file"; then if test "x$cache_file" != "x/dev/null"; then { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 $as_echo "$as_me: updating cache $cache_file" >&6;} if test ! -f "$cache_file" || test -h "$cache_file"; then cat confcache >"$cache_file" else case $cache_file in #( */* | ?:*) mv -f confcache "$cache_file"$$ && mv -f "$cache_file"$$ "$cache_file" ;; #( *) mv -f confcache "$cache_file" ;; esac fi fi else { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 $as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} fi fi rm -f confcache test "x$prefix" = xNONE && prefix=$ac_default_prefix # Let make expand exec_prefix. test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' DEFS=-DHAVE_CONFIG_H ac_libobjs= ac_ltlibobjs= U= for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue # 1. Remove the extension, and $U if already installed. ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' ac_i=`$as_echo "$ac_i" | sed "$ac_script"` # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR # will be set to the directory where LIBOBJS objects are built. as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' done LIBOBJS=$ac_libobjs LTLIBOBJS=$ac_ltlibobjs if test -z "${MAINTAINER_MODE_TRUE}" && test -z "${MAINTAINER_MODE_FALSE}"; then as_fn_error $? "conditional \"MAINTAINER_MODE\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -n "$EXEEXT"; then am__EXEEXT_TRUE= am__EXEEXT_FALSE='#' else am__EXEEXT_TRUE='#' am__EXEEXT_FALSE= fi if test -z "${AMDEP_TRUE}" && test -z "${AMDEP_FALSE}"; then as_fn_error $? "conditional \"AMDEP\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi if test -z "${am__fastdepCC_TRUE}" && test -z "${am__fastdepCC_FALSE}"; then as_fn_error $? "conditional \"am__fastdepCC\" was never defined. Usually this means the macro was only invoked conditionally." "$LINENO" 5 fi : "${CONFIG_STATUS=./config.status}" ac_write_fail=0 ac_clean_files_save=$ac_clean_files ac_clean_files="$ac_clean_files $CONFIG_STATUS" { $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 $as_echo "$as_me: creating $CONFIG_STATUS" >&6;} as_write_fail=0 cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 #! $SHELL # Generated by $as_me. # Run this file to recreate the current configuration. # Compiler output produced by configure, useful for debugging # configure, is in config.log if it exists. debug=false ac_cs_recheck=false ac_cs_silent=false SHELL=\${CONFIG_SHELL-$SHELL} export SHELL _ASEOF cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1 ## -------------------- ## ## M4sh Initialization. ## ## -------------------- ## # Be more Bourne compatible DUALCASE=1; export DUALCASE # for MKS sh if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : emulate sh NULLCMD=: # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which # is contrary to our usage. Disable this feature. alias -g '${1+"$@"}'='"$@"' setopt NO_GLOB_SUBST else case `(set -o) 2>/dev/null` in #( *posix*) : set -o posix ;; #( *) : ;; esac fi as_nl=' ' export as_nl # Printing a long string crashes Solaris 7 /usr/bin/printf. as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo # Prefer a ksh shell builtin over an external printf program on Solaris, # but without wasting forks for bash or zsh. if test -z "$BASH_VERSION$ZSH_VERSION" \ && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then as_echo='print -r --' as_echo_n='print -rn --' elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then as_echo='printf %s\n' as_echo_n='printf %s' else if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' as_echo_n='/usr/ucb/echo -n' else as_echo_body='eval expr "X$1" : "X\\(.*\\)"' as_echo_n_body='eval arg=$1; case $arg in #( *"$as_nl"*) expr "X$arg" : "X\\(.*\\)$as_nl"; arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; esac; expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" ' export as_echo_n_body as_echo_n='sh -c $as_echo_n_body as_echo' fi export as_echo_body as_echo='sh -c $as_echo_body as_echo' fi # The user is always right. if test "${PATH_SEPARATOR+set}" != set; then PATH_SEPARATOR=: (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || PATH_SEPARATOR=';' } fi # IFS # We need space, tab and new line, in precisely that order. Quoting is # there to prevent editors from complaining about space-tab. # (If _AS_PATH_WALK were called with IFS unset, it would disable word # splitting by setting IFS to empty value.) IFS=" "" $as_nl" # Find who we are. Look in the path if we contain no directory separator. as_myself= case $0 in #(( *[\\/]* ) as_myself=$0 ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break done IFS=$as_save_IFS ;; esac # We did not find ourselves, most probably we were run as `sh COMMAND' # in which case we are not to be found in the path. if test "x$as_myself" = x; then as_myself=$0 fi if test ! -f "$as_myself"; then $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 exit 1 fi # Unset variables that we do not need and which cause bugs (e.g. in # pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" # suppresses any "Segmentation fault" message there. '((' could # trigger a bug in pdksh 5.2.14. for as_var in BASH_ENV ENV MAIL MAILPATH do eval test x\${$as_var+set} = xset \ && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : done PS1='$ ' PS2='> ' PS4='+ ' # NLS nuisances. LC_ALL=C export LC_ALL LANGUAGE=C export LANGUAGE # CDPATH. (unset CDPATH) >/dev/null 2>&1 && unset CDPATH # as_fn_error STATUS ERROR [LINENO LOG_FD] # ---------------------------------------- # Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are # provided, also output the error to LOG_FD, referencing LINENO. Then exit the # script with STATUS, using 1 if that was 0. as_fn_error () { as_status=$1; test $as_status -eq 0 && as_status=1 if test "$4"; then as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 fi $as_echo "$as_me: error: $2" >&2 as_fn_exit $as_status } # as_fn_error # as_fn_set_status STATUS # ----------------------- # Set $? to STATUS, without forking. as_fn_set_status () { return $1 } # as_fn_set_status # as_fn_exit STATUS # ----------------- # Exit the shell with STATUS, even in a "trap 0" or "set -e" context. as_fn_exit () { set +e as_fn_set_status $1 exit $1 } # as_fn_exit # as_fn_unset VAR # --------------- # Portably unset VAR. as_fn_unset () { { eval $1=; unset $1;} } as_unset=as_fn_unset # as_fn_append VAR VALUE # ---------------------- # Append the text in VALUE to the end of the definition contained in VAR. Take # advantage of any shell optimizations that allow amortized linear growth over # repeated appends, instead of the typical quadratic growth present in naive # implementations. if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : eval 'as_fn_append () { eval $1+=\$2 }' else as_fn_append () { eval $1=\$$1\$2 } fi # as_fn_append # as_fn_arith ARG... # ------------------ # Perform arithmetic evaluation on the ARGs, and store the result in the # global $as_val. Take advantage of shells that can avoid forks. The arguments # must be portable across $(()) and expr. if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : eval 'as_fn_arith () { as_val=$(( $* )) }' else as_fn_arith () { as_val=`expr "$@" || test $? -eq 1` } fi # as_fn_arith if expr a : '\(a\)' >/dev/null 2>&1 && test "X`expr 00001 : '.*\(...\)'`" = X001; then as_expr=expr else as_expr=false fi if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then as_basename=basename else as_basename=false fi if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then as_dirname=dirname else as_dirname=false fi as_me=`$as_basename -- "$0" || $as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ X"$0" : 'X\(//\)$' \| \ X"$0" : 'X\(/\)' \| . 2>/dev/null || $as_echo X/"$0" | sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/ q } /^X\/\(\/\/\)$/{ s//\1/ q } /^X\/\(\/\).*/{ s//\1/ q } s/.*/./; q'` # Avoid depending upon Character Ranges. as_cr_letters='abcdefghijklmnopqrstuvwxyz' as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' as_cr_Letters=$as_cr_letters$as_cr_LETTERS as_cr_digits='0123456789' as_cr_alnum=$as_cr_Letters$as_cr_digits ECHO_C= ECHO_N= ECHO_T= case `echo -n x` in #((((( -n*) case `echo 'xy\c'` in *c*) ECHO_T=' ';; # ECHO_T is single tab character. xy) ECHO_C='\c';; *) echo `echo ksh88 bug on AIX 6.1` > /dev/null ECHO_T=' ';; esac;; *) ECHO_N='-n';; esac rm -f conf$$ conf$$.exe conf$$.file if test -d conf$$.dir; then rm -f conf$$.dir/conf$$.file else rm -f conf$$.dir mkdir conf$$.dir 2>/dev/null fi if (echo >conf$$.file) 2>/dev/null; then if ln -s conf$$.file conf$$ 2>/dev/null; then as_ln_s='ln -s' # ... but there are two gotchas: # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. # In both cases, we have to default to `cp -p'. ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || as_ln_s='cp -p' elif ln conf$$.file conf$$ 2>/dev/null; then as_ln_s=ln else as_ln_s='cp -p' fi else as_ln_s='cp -p' fi rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file rmdir conf$$.dir 2>/dev/null # as_fn_mkdir_p # ------------- # Create "$as_dir" as a directory, including parents if necessary. as_fn_mkdir_p () { case $as_dir in #( -*) as_dir=./$as_dir;; esac test -d "$as_dir" || eval $as_mkdir_p || { as_dirs= while :; do case $as_dir in #( *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( *) as_qdir=$as_dir;; esac as_dirs="'$as_qdir' $as_dirs" as_dir=`$as_dirname -- "$as_dir" || $as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ X"$as_dir" : 'X\(//\)[^/]' \| \ X"$as_dir" : 'X\(//\)$' \| \ X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || $as_echo X"$as_dir" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/ q } /^X\(\/\/\)[^/].*/{ s//\1/ q } /^X\(\/\/\)$/{ s//\1/ q } /^X\(\/\).*/{ s//\1/ q } s/.*/./; q'` test -d "$as_dir" && break done test -z "$as_dirs" || eval "mkdir $as_dirs" } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir" } # as_fn_mkdir_p if mkdir -p . 2>/dev/null; then as_mkdir_p='mkdir -p "$as_dir"' else test -d ./-p && rmdir ./-p as_mkdir_p=false fi if test -x / >/dev/null 2>&1; then as_test_x='test -x' else if ls -dL / >/dev/null 2>&1; then as_ls_L_option=L else as_ls_L_option= fi as_test_x=' eval sh -c '\'' if test -d "$1"; then test -d "$1/."; else case $1 in #( -*)set "./$1";; esac; case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( ???[sx]*):;;*)false;;esac;fi '\'' sh ' fi as_executable_p=$as_test_x # Sed expression to map a string onto a valid CPP name. as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" # Sed expression to map a string onto a valid variable name. as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" exec 6>&1 ## ----------------------------------- ## ## Main body of $CONFIG_STATUS script. ## ## ----------------------------------- ## _ASEOF test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1 cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 # Save the log message, to keep $0 and so on meaningful, and to # report actual input values of CONFIG_FILES etc. instead of their # values after options handling. ac_log=" This file was extended by $as_me, which was generated by GNU Autoconf 2.68. Invocation command line was CONFIG_FILES = $CONFIG_FILES CONFIG_HEADERS = $CONFIG_HEADERS CONFIG_LINKS = $CONFIG_LINKS CONFIG_COMMANDS = $CONFIG_COMMANDS $ $0 $@ on `(hostname || uname -n) 2>/dev/null | sed 1q` " _ACEOF case $ac_config_files in *" "*) set x $ac_config_files; shift; ac_config_files=$*;; esac case $ac_config_headers in *" "*) set x $ac_config_headers; shift; ac_config_headers=$*;; esac cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 # Files that config.status was made for. config_files="$ac_config_files" config_headers="$ac_config_headers" config_commands="$ac_config_commands" _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 ac_cs_usage="\ \`$as_me' instantiates files and other configuration actions from templates according to the current configuration. Unless the files and actions are specified as TAGs, all are instantiated by default. Usage: $0 [OPTION]... [TAG]... -h, --help print this help, then exit -V, --version print version number and configuration settings, then exit --config print configuration, then exit -q, --quiet, --silent do not print progress messages -d, --debug don't remove temporary files --recheck update $as_me by reconfiguring in the same conditions --file=FILE[:TEMPLATE] instantiate the configuration file FILE --header=FILE[:TEMPLATE] instantiate the configuration header FILE Configuration files: $config_files Configuration headers: $config_headers Configuration commands: $config_commands Report bugs to the package provider." _ACEOF cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`" ac_cs_version="\\ config.status configured by $0, generated by GNU Autoconf 2.68, with options \\"\$ac_cs_config\\" Copyright (C) 2010 Free Software Foundation, Inc. This config.status script is free software; the Free Software Foundation gives unlimited permission to copy, distribute and modify it." ac_pwd='$ac_pwd' srcdir='$srcdir' INSTALL='$INSTALL' MKDIR_P='$MKDIR_P' AWK='$AWK' test -n "\$AWK" || AWK=awk _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 # The default lists apply if the user does not specify any file. ac_need_defaults=: while test $# != 0 do case $1 in --*=?*) ac_option=`expr "X$1" : 'X\([^=]*\)='` ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'` ac_shift=: ;; --*=) ac_option=`expr "X$1" : 'X\([^=]*\)='` ac_optarg= ac_shift=: ;; *) ac_option=$1 ac_optarg=$2 ac_shift=shift ;; esac case $ac_option in # Handling of the options. -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) ac_cs_recheck=: ;; --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) $as_echo "$ac_cs_version"; exit ;; --config | --confi | --conf | --con | --co | --c ) $as_echo "$ac_cs_config"; exit ;; --debug | --debu | --deb | --de | --d | -d ) debug=: ;; --file | --fil | --fi | --f ) $ac_shift case $ac_optarg in *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; '') as_fn_error $? "missing file argument" ;; esac as_fn_append CONFIG_FILES " '$ac_optarg'" ac_need_defaults=false;; --header | --heade | --head | --hea ) $ac_shift case $ac_optarg in *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; esac as_fn_append CONFIG_HEADERS " '$ac_optarg'" ac_need_defaults=false;; --he | --h) # Conflict between --help and --header as_fn_error $? "ambiguous option: \`$1' Try \`$0 --help' for more information.";; --help | --hel | -h ) $as_echo "$ac_cs_usage"; exit ;; -q | -quiet | --quiet | --quie | --qui | --qu | --q \ | -silent | --silent | --silen | --sile | --sil | --si | --s) ac_cs_silent=: ;; # This is an error. -*) as_fn_error $? "unrecognized option: \`$1' Try \`$0 --help' for more information." ;; *) as_fn_append ac_config_targets " $1" ac_need_defaults=false ;; esac shift done ac_configure_extra_args= if $ac_cs_silent; then exec 6>/dev/null ac_configure_extra_args="$ac_configure_extra_args --silent" fi _ACEOF cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 if \$ac_cs_recheck; then set X '$SHELL' '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion shift \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6 CONFIG_SHELL='$SHELL' export CONFIG_SHELL exec "\$@" fi _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 exec 5>>config.log { echo sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX ## Running $as_me. ## _ASBOX $as_echo "$ac_log" } >&5 _ACEOF cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 # # INIT-COMMANDS # AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir" # The HP-UX ksh and POSIX shell print the target directory to stdout # if CDPATH is set. (unset CDPATH) >/dev/null 2>&1 && unset CDPATH sed_quote_subst='$sed_quote_subst' double_quote_subst='$double_quote_subst' delay_variable_subst='$delay_variable_subst' macro_version='`$ECHO "$macro_version" | $SED "$delay_single_quote_subst"`' macro_revision='`$ECHO "$macro_revision" | $SED "$delay_single_quote_subst"`' enable_shared='`$ECHO "$enable_shared" | $SED "$delay_single_quote_subst"`' enable_static='`$ECHO "$enable_static" | $SED "$delay_single_quote_subst"`' pic_mode='`$ECHO "$pic_mode" | $SED "$delay_single_quote_subst"`' enable_fast_install='`$ECHO "$enable_fast_install" | $SED "$delay_single_quote_subst"`' SHELL='`$ECHO "$SHELL" | $SED "$delay_single_quote_subst"`' ECHO='`$ECHO "$ECHO" | $SED "$delay_single_quote_subst"`' host_alias='`$ECHO "$host_alias" | $SED "$delay_single_quote_subst"`' host='`$ECHO "$host" | $SED "$delay_single_quote_subst"`' host_os='`$ECHO "$host_os" | $SED "$delay_single_quote_subst"`' build_alias='`$ECHO "$build_alias" | $SED "$delay_single_quote_subst"`' build='`$ECHO "$build" | $SED "$delay_single_quote_subst"`' build_os='`$ECHO "$build_os" | $SED "$delay_single_quote_subst"`' SED='`$ECHO "$SED" | $SED "$delay_single_quote_subst"`' Xsed='`$ECHO "$Xsed" | $SED "$delay_single_quote_subst"`' GREP='`$ECHO "$GREP" | $SED "$delay_single_quote_subst"`' EGREP='`$ECHO "$EGREP" | $SED "$delay_single_quote_subst"`' FGREP='`$ECHO "$FGREP" | $SED "$delay_single_quote_subst"`' LD='`$ECHO "$LD" | $SED "$delay_single_quote_subst"`' NM='`$ECHO "$NM" | $SED "$delay_single_quote_subst"`' LN_S='`$ECHO "$LN_S" | $SED "$delay_single_quote_subst"`' max_cmd_len='`$ECHO "$max_cmd_len" | $SED "$delay_single_quote_subst"`' ac_objext='`$ECHO "$ac_objext" | $SED "$delay_single_quote_subst"`' exeext='`$ECHO "$exeext" | $SED "$delay_single_quote_subst"`' lt_unset='`$ECHO "$lt_unset" | $SED "$delay_single_quote_subst"`' lt_SP2NL='`$ECHO "$lt_SP2NL" | $SED "$delay_single_quote_subst"`' lt_NL2SP='`$ECHO "$lt_NL2SP" | $SED "$delay_single_quote_subst"`' lt_cv_to_host_file_cmd='`$ECHO "$lt_cv_to_host_file_cmd" | $SED "$delay_single_quote_subst"`' lt_cv_to_tool_file_cmd='`$ECHO "$lt_cv_to_tool_file_cmd" | $SED "$delay_single_quote_subst"`' reload_flag='`$ECHO "$reload_flag" | $SED "$delay_single_quote_subst"`' reload_cmds='`$ECHO "$reload_cmds" | $SED "$delay_single_quote_subst"`' OBJDUMP='`$ECHO "$OBJDUMP" | $SED "$delay_single_quote_subst"`' deplibs_check_method='`$ECHO "$deplibs_check_method" | $SED "$delay_single_quote_subst"`' file_magic_cmd='`$ECHO "$file_magic_cmd" | $SED "$delay_single_quote_subst"`' file_magic_glob='`$ECHO "$file_magic_glob" | $SED "$delay_single_quote_subst"`' want_nocaseglob='`$ECHO "$want_nocaseglob" | $SED "$delay_single_quote_subst"`' DLLTOOL='`$ECHO "$DLLTOOL" | $SED "$delay_single_quote_subst"`' sharedlib_from_linklib_cmd='`$ECHO "$sharedlib_from_linklib_cmd" | $SED "$delay_single_quote_subst"`' AR='`$ECHO "$AR" | $SED "$delay_single_quote_subst"`' AR_FLAGS='`$ECHO "$AR_FLAGS" | $SED "$delay_single_quote_subst"`' archiver_list_spec='`$ECHO "$archiver_list_spec" | $SED "$delay_single_quote_subst"`' STRIP='`$ECHO "$STRIP" | $SED "$delay_single_quote_subst"`' RANLIB='`$ECHO "$RANLIB" | $SED "$delay_single_quote_subst"`' old_postinstall_cmds='`$ECHO "$old_postinstall_cmds" | $SED "$delay_single_quote_subst"`' old_postuninstall_cmds='`$ECHO "$old_postuninstall_cmds" | $SED "$delay_single_quote_subst"`' old_archive_cmds='`$ECHO "$old_archive_cmds" | $SED "$delay_single_quote_subst"`' lock_old_archive_extraction='`$ECHO "$lock_old_archive_extraction" | $SED "$delay_single_quote_subst"`' CC='`$ECHO "$CC" | $SED "$delay_single_quote_subst"`' CFLAGS='`$ECHO "$CFLAGS" | $SED "$delay_single_quote_subst"`' compiler='`$ECHO "$compiler" | $SED "$delay_single_quote_subst"`' GCC='`$ECHO "$GCC" | $SED "$delay_single_quote_subst"`' lt_cv_sys_global_symbol_pipe='`$ECHO "$lt_cv_sys_global_symbol_pipe" | $SED "$delay_single_quote_subst"`' lt_cv_sys_global_symbol_to_cdecl='`$ECHO "$lt_cv_sys_global_symbol_to_cdecl" | $SED "$delay_single_quote_subst"`' lt_cv_sys_global_symbol_to_c_name_address='`$ECHO "$lt_cv_sys_global_symbol_to_c_name_address" | $SED "$delay_single_quote_subst"`' lt_cv_sys_global_symbol_to_c_name_address_lib_prefix='`$ECHO "$lt_cv_sys_global_symbol_to_c_name_address_lib_prefix" | $SED "$delay_single_quote_subst"`' nm_file_list_spec='`$ECHO "$nm_file_list_spec" | $SED "$delay_single_quote_subst"`' lt_sysroot='`$ECHO "$lt_sysroot" | $SED "$delay_single_quote_subst"`' objdir='`$ECHO "$objdir" | $SED "$delay_single_quote_subst"`' MAGIC_CMD='`$ECHO "$MAGIC_CMD" | $SED "$delay_single_quote_subst"`' lt_prog_compiler_no_builtin_flag='`$ECHO "$lt_prog_compiler_no_builtin_flag" | $SED "$delay_single_quote_subst"`' lt_prog_compiler_pic='`$ECHO "$lt_prog_compiler_pic" | $SED "$delay_single_quote_subst"`' lt_prog_compiler_wl='`$ECHO "$lt_prog_compiler_wl" | $SED "$delay_single_quote_subst"`' lt_prog_compiler_static='`$ECHO "$lt_prog_compiler_static" | $SED "$delay_single_quote_subst"`' lt_cv_prog_compiler_c_o='`$ECHO "$lt_cv_prog_compiler_c_o" | $SED "$delay_single_quote_subst"`' need_locks='`$ECHO "$need_locks" | $SED "$delay_single_quote_subst"`' MANIFEST_TOOL='`$ECHO "$MANIFEST_TOOL" | $SED "$delay_single_quote_subst"`' DSYMUTIL='`$ECHO "$DSYMUTIL" | $SED "$delay_single_quote_subst"`' NMEDIT='`$ECHO "$NMEDIT" | $SED "$delay_single_quote_subst"`' LIPO='`$ECHO "$LIPO" | $SED "$delay_single_quote_subst"`' OTOOL='`$ECHO "$OTOOL" | $SED "$delay_single_quote_subst"`' OTOOL64='`$ECHO "$OTOOL64" | $SED "$delay_single_quote_subst"`' libext='`$ECHO "$libext" | $SED "$delay_single_quote_subst"`' shrext_cmds='`$ECHO "$shrext_cmds" | $SED "$delay_single_quote_subst"`' extract_expsyms_cmds='`$ECHO "$extract_expsyms_cmds" | $SED "$delay_single_quote_subst"`' archive_cmds_need_lc='`$ECHO "$archive_cmds_need_lc" | $SED "$delay_single_quote_subst"`' enable_shared_with_static_runtimes='`$ECHO "$enable_shared_with_static_runtimes" | $SED "$delay_single_quote_subst"`' export_dynamic_flag_spec='`$ECHO "$export_dynamic_flag_spec" | $SED "$delay_single_quote_subst"`' whole_archive_flag_spec='`$ECHO "$whole_archive_flag_spec" | $SED "$delay_single_quote_subst"`' compiler_needs_object='`$ECHO "$compiler_needs_object" | $SED "$delay_single_quote_subst"`' old_archive_from_new_cmds='`$ECHO "$old_archive_from_new_cmds" | $SED "$delay_single_quote_subst"`' old_archive_from_expsyms_cmds='`$ECHO "$old_archive_from_expsyms_cmds" | $SED "$delay_single_quote_subst"`' archive_cmds='`$ECHO "$archive_cmds" | $SED "$delay_single_quote_subst"`' archive_expsym_cmds='`$ECHO "$archive_expsym_cmds" | $SED "$delay_single_quote_subst"`' module_cmds='`$ECHO "$module_cmds" | $SED "$delay_single_quote_subst"`' module_expsym_cmds='`$ECHO "$module_expsym_cmds" | $SED "$delay_single_quote_subst"`' with_gnu_ld='`$ECHO "$with_gnu_ld" | $SED "$delay_single_quote_subst"`' allow_undefined_flag='`$ECHO "$allow_undefined_flag" | $SED "$delay_single_quote_subst"`' no_undefined_flag='`$ECHO "$no_undefined_flag" | $SED "$delay_single_quote_subst"`' hardcode_libdir_flag_spec='`$ECHO "$hardcode_libdir_flag_spec" | $SED "$delay_single_quote_subst"`' hardcode_libdir_flag_spec_ld='`$ECHO "$hardcode_libdir_flag_spec_ld" | $SED "$delay_single_quote_subst"`' hardcode_libdir_separator='`$ECHO "$hardcode_libdir_separator" | $SED "$delay_single_quote_subst"`' hardcode_direct='`$ECHO "$hardcode_direct" | $SED "$delay_single_quote_subst"`' hardcode_direct_absolute='`$ECHO "$hardcode_direct_absolute" | $SED "$delay_single_quote_subst"`' hardcode_minus_L='`$ECHO "$hardcode_minus_L" | $SED "$delay_single_quote_subst"`' hardcode_shlibpath_var='`$ECHO "$hardcode_shlibpath_var" | $SED "$delay_single_quote_subst"`' hardcode_automatic='`$ECHO "$hardcode_automatic" | $SED "$delay_single_quote_subst"`' inherit_rpath='`$ECHO "$inherit_rpath" | $SED "$delay_single_quote_subst"`' link_all_deplibs='`$ECHO "$link_all_deplibs" | $SED "$delay_single_quote_subst"`' always_export_symbols='`$ECHO "$always_export_symbols" | $SED "$delay_single_quote_subst"`' export_symbols_cmds='`$ECHO "$export_symbols_cmds" | $SED "$delay_single_quote_subst"`' exclude_expsyms='`$ECHO "$exclude_expsyms" | $SED "$delay_single_quote_subst"`' include_expsyms='`$ECHO "$include_expsyms" | $SED "$delay_single_quote_subst"`' prelink_cmds='`$ECHO "$prelink_cmds" | $SED "$delay_single_quote_subst"`' postlink_cmds='`$ECHO "$postlink_cmds" | $SED "$delay_single_quote_subst"`' file_list_spec='`$ECHO "$file_list_spec" | $SED "$delay_single_quote_subst"`' variables_saved_for_relink='`$ECHO "$variables_saved_for_relink" | $SED "$delay_single_quote_subst"`' need_lib_prefix='`$ECHO "$need_lib_prefix" | $SED "$delay_single_quote_subst"`' need_version='`$ECHO "$need_version" | $SED "$delay_single_quote_subst"`' version_type='`$ECHO "$version_type" | $SED "$delay_single_quote_subst"`' runpath_var='`$ECHO "$runpath_var" | $SED "$delay_single_quote_subst"`' shlibpath_var='`$ECHO "$shlibpath_var" | $SED "$delay_single_quote_subst"`' shlibpath_overrides_runpath='`$ECHO "$shlibpath_overrides_runpath" | $SED "$delay_single_quote_subst"`' libname_spec='`$ECHO "$libname_spec" | $SED "$delay_single_quote_subst"`' library_names_spec='`$ECHO "$library_names_spec" | $SED "$delay_single_quote_subst"`' soname_spec='`$ECHO "$soname_spec" | $SED "$delay_single_quote_subst"`' install_override_mode='`$ECHO "$install_override_mode" | $SED "$delay_single_quote_subst"`' postinstall_cmds='`$ECHO "$postinstall_cmds" | $SED "$delay_single_quote_subst"`' postuninstall_cmds='`$ECHO "$postuninstall_cmds" | $SED "$delay_single_quote_subst"`' finish_cmds='`$ECHO "$finish_cmds" | $SED "$delay_single_quote_subst"`' finish_eval='`$ECHO "$finish_eval" | $SED "$delay_single_quote_subst"`' hardcode_into_libs='`$ECHO "$hardcode_into_libs" | $SED "$delay_single_quote_subst"`' sys_lib_search_path_spec='`$ECHO "$sys_lib_search_path_spec" | $SED "$delay_single_quote_subst"`' sys_lib_dlsearch_path_spec='`$ECHO "$sys_lib_dlsearch_path_spec" | $SED "$delay_single_quote_subst"`' hardcode_action='`$ECHO "$hardcode_action" | $SED "$delay_single_quote_subst"`' enable_dlopen='`$ECHO "$enable_dlopen" | $SED "$delay_single_quote_subst"`' enable_dlopen_self='`$ECHO "$enable_dlopen_self" | $SED "$delay_single_quote_subst"`' enable_dlopen_self_static='`$ECHO "$enable_dlopen_self_static" | $SED "$delay_single_quote_subst"`' old_striplib='`$ECHO "$old_striplib" | $SED "$delay_single_quote_subst"`' striplib='`$ECHO "$striplib" | $SED "$delay_single_quote_subst"`' LTCC='$LTCC' LTCFLAGS='$LTCFLAGS' compiler='$compiler_DEFAULT' # A function that is used when there is no print builtin or printf. func_fallback_echo () { eval 'cat <<_LTECHO_EOF \$1 _LTECHO_EOF' } # Quote evaled strings. for var in SHELL \ ECHO \ SED \ GREP \ EGREP \ FGREP \ LD \ NM \ LN_S \ lt_SP2NL \ lt_NL2SP \ reload_flag \ OBJDUMP \ deplibs_check_method \ file_magic_cmd \ file_magic_glob \ want_nocaseglob \ DLLTOOL \ sharedlib_from_linklib_cmd \ AR \ AR_FLAGS \ archiver_list_spec \ STRIP \ RANLIB \ CC \ CFLAGS \ compiler \ lt_cv_sys_global_symbol_pipe \ lt_cv_sys_global_symbol_to_cdecl \ lt_cv_sys_global_symbol_to_c_name_address \ lt_cv_sys_global_symbol_to_c_name_address_lib_prefix \ nm_file_list_spec \ lt_prog_compiler_no_builtin_flag \ lt_prog_compiler_pic \ lt_prog_compiler_wl \ lt_prog_compiler_static \ lt_cv_prog_compiler_c_o \ need_locks \ MANIFEST_TOOL \ DSYMUTIL \ NMEDIT \ LIPO \ OTOOL \ OTOOL64 \ shrext_cmds \ export_dynamic_flag_spec \ whole_archive_flag_spec \ compiler_needs_object \ with_gnu_ld \ allow_undefined_flag \ no_undefined_flag \ hardcode_libdir_flag_spec \ hardcode_libdir_flag_spec_ld \ hardcode_libdir_separator \ exclude_expsyms \ include_expsyms \ file_list_spec \ variables_saved_for_relink \ libname_spec \ library_names_spec \ soname_spec \ install_override_mode \ finish_eval \ old_striplib \ striplib; do case \`eval \\\\\$ECHO \\\\""\\\\\$\$var"\\\\"\` in *[\\\\\\\`\\"\\\$]*) eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"\\\$\$var\\" | \\\$SED \\"\\\$sed_quote_subst\\"\\\`\\\\\\"" ;; *) eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\"" ;; esac done # Double-quote double-evaled strings. for var in reload_cmds \ old_postinstall_cmds \ old_postuninstall_cmds \ old_archive_cmds \ extract_expsyms_cmds \ old_archive_from_new_cmds \ old_archive_from_expsyms_cmds \ archive_cmds \ archive_expsym_cmds \ module_cmds \ module_expsym_cmds \ export_symbols_cmds \ prelink_cmds \ postlink_cmds \ postinstall_cmds \ postuninstall_cmds \ finish_cmds \ sys_lib_search_path_spec \ sys_lib_dlsearch_path_spec; do case \`eval \\\\\$ECHO \\\\""\\\\\$\$var"\\\\"\` in *[\\\\\\\`\\"\\\$]*) eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"\\\$\$var\\" | \\\$SED -e \\"\\\$double_quote_subst\\" -e \\"\\\$sed_quote_subst\\" -e \\"\\\$delay_variable_subst\\"\\\`\\\\\\"" ;; *) eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\"" ;; esac done ac_aux_dir='$ac_aux_dir' xsi_shell='$xsi_shell' lt_shell_append='$lt_shell_append' # See if we are running on zsh, and set the options which allow our # commands through without removal of \ escapes INIT. if test -n "\${ZSH_VERSION+set}" ; then setopt NO_GLOB_SUBST fi PACKAGE='$PACKAGE' VERSION='$VERSION' TIMESTAMP='$TIMESTAMP' RM='$RM' ofile='$ofile' _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 # Handling of arguments. for ac_config_target in $ac_config_targets do case $ac_config_target in "config.h") CONFIG_HEADERS="$CONFIG_HEADERS config.h" ;; "depfiles") CONFIG_COMMANDS="$CONFIG_COMMANDS depfiles" ;; "libtool") CONFIG_COMMANDS="$CONFIG_COMMANDS libtool" ;; "Makefile") CONFIG_FILES="$CONFIG_FILES Makefile" ;; "m4/Makefile") CONFIG_FILES="$CONFIG_FILES m4/Makefile" ;; "src/Makefile") CONFIG_FILES="$CONFIG_FILES src/Makefile" ;; *) as_fn_error $? "invalid argument: \`$ac_config_target'" "$LINENO" 5;; esac done # If the user did not use the arguments to specify the items to instantiate, # then the envvar interface is used. Set only those that are not. # We use the long form for the default assignment because of an extremely # bizarre bug on SunOS 4.1.3. if $ac_need_defaults; then test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files test "${CONFIG_HEADERS+set}" = set || CONFIG_HEADERS=$config_headers test "${CONFIG_COMMANDS+set}" = set || CONFIG_COMMANDS=$config_commands fi # Have a temporary directory for convenience. Make it in the build tree # simply because there is no reason against having it here, and in addition, # creating and moving files from /tmp can sometimes cause problems. # Hook for its removal unless debugging. # Note that there is a small window in which the directory will not be cleaned: # after its creation but before its name has been assigned to `$tmp'. $debug || { tmp= ac_tmp= trap 'exit_status=$? : "${ac_tmp:=$tmp}" { test ! -d "$ac_tmp" || rm -fr "$ac_tmp"; } && exit $exit_status ' 0 trap 'as_fn_exit 1' 1 2 13 15 } # Create a (secure) tmp directory for tmp files. { tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && test -d "$tmp" } || { tmp=./conf$$-$RANDOM (umask 077 && mkdir "$tmp") } || as_fn_error $? "cannot create a temporary directory in ." "$LINENO" 5 ac_tmp=$tmp # Set up the scripts for CONFIG_FILES section. # No need to generate them if there are no CONFIG_FILES. # This happens for instance with `./config.status config.h'. if test -n "$CONFIG_FILES"; then ac_cr=`echo X | tr X '\015'` # On cygwin, bash can eat \r inside `` if the user requested igncr. # But we know of no other shell where ac_cr would be empty at this # point, so we can use a bashism as a fallback. if test "x$ac_cr" = x; then eval ac_cr=\$\'\\r\' fi ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null` if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then ac_cs_awk_cr='\\r' else ac_cs_awk_cr=$ac_cr fi echo 'BEGIN {' >"$ac_tmp/subs1.awk" && _ACEOF { echo "cat >conf$$subs.awk <<_ACEOF" && echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && echo "_ACEOF" } >conf$$subs.sh || as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 ac_delim_num=`echo "$ac_subst_vars" | grep -c '^'` ac_delim='%!_!# ' for ac_last_try in false false false false false :; do . ./conf$$subs.sh || as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` if test $ac_delim_n = $ac_delim_num; then break elif $ac_last_try; then as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 else ac_delim="$ac_delim!$ac_delim _$ac_delim!! " fi done rm -f conf$$subs.sh cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 cat >>"\$ac_tmp/subs1.awk" <<\\_ACAWK && _ACEOF sed -n ' h s/^/S["/; s/!.*/"]=/ p g s/^[^!]*!// :repl t repl s/'"$ac_delim"'$// t delim :nl h s/\(.\{148\}\)..*/\1/ t more1 s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ p n b repl :more1 s/["\\]/\\&/g; s/^/"/; s/$/"\\/ p g s/.\{148\}// t nl :delim h s/\(.\{148\}\)..*/\1/ t more2 s/["\\]/\\&/g; s/^/"/; s/$/"/ p b :more2 s/["\\]/\\&/g; s/^/"/; s/$/"\\/ p g s/.\{148\}// t delim ' >$CONFIG_STATUS || ac_write_fail=1 rm -f conf$$subs.awk cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 _ACAWK cat >>"\$ac_tmp/subs1.awk" <<_ACAWK && for (key in S) S_is_set[key] = 1 FS = "" } { line = $ 0 nfields = split(line, field, "@") substed = 0 len = length(field[1]) for (i = 2; i < nfields; i++) { key = field[i] keylen = length(key) if (S_is_set[key]) { value = S[key] line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3) len += length(value) + length(field[++i]) substed = 1 } else len += 1 + keylen } print line } _ACAWK _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" else cat fi < "$ac_tmp/subs1.awk" > "$ac_tmp/subs.awk" \ || as_fn_error $? "could not setup config files machinery" "$LINENO" 5 _ACEOF # VPATH may cause trouble with some makes, so we remove sole $(srcdir), # ${srcdir} and @srcdir@ entries from VPATH if srcdir is ".", strip leading and # trailing colons and then remove the whole line if VPATH becomes empty # (actually we leave an empty line to preserve line numbers). if test "x$srcdir" = x.; then ac_vpsub='/^[ ]*VPATH[ ]*=[ ]*/{ h s/// s/^/:/ s/[ ]*$/:/ s/:\$(srcdir):/:/g s/:\${srcdir}:/:/g s/:@srcdir@:/:/g s/^:*// s/:*$// x s/\(=[ ]*\).*/\1/ G s/\n// s/^[^=]*=[ ]*$// }' fi cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 fi # test -n "$CONFIG_FILES" # Set up the scripts for CONFIG_HEADERS section. # No need to generate them if there are no CONFIG_HEADERS. # This happens for instance with `./config.status Makefile'. if test -n "$CONFIG_HEADERS"; then cat >"$ac_tmp/defines.awk" <<\_ACAWK || BEGIN { _ACEOF # Transform confdefs.h into an awk script `defines.awk', embedded as # here-document in config.status, that substitutes the proper values into # config.h.in to produce config.h. # Create a delimiter string that does not exist in confdefs.h, to ease # handling of long lines. ac_delim='%!_!# ' for ac_last_try in false false :; do ac_tt=`sed -n "/$ac_delim/p" confdefs.h` if test -z "$ac_tt"; then break elif $ac_last_try; then as_fn_error $? "could not make $CONFIG_HEADERS" "$LINENO" 5 else ac_delim="$ac_delim!$ac_delim _$ac_delim!! " fi done # For the awk script, D is an array of macro values keyed by name, # likewise P contains macro parameters if any. Preserve backslash # newline sequences. ac_word_re=[_$as_cr_Letters][_$as_cr_alnum]* sed -n ' s/.\{148\}/&'"$ac_delim"'/g t rset :rset s/^[ ]*#[ ]*define[ ][ ]*/ / t def d :def s/\\$// t bsnl s/["\\]/\\&/g s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ D["\1"]=" \3"/p s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2"/p d :bsnl s/["\\]/\\&/g s/^ \('"$ac_word_re"'\)\(([^()]*)\)[ ]*\(.*\)/P["\1"]="\2"\ D["\1"]=" \3\\\\\\n"\\/p t cont s/^ \('"$ac_word_re"'\)[ ]*\(.*\)/D["\1"]=" \2\\\\\\n"\\/p t cont d :cont n s/.\{148\}/&'"$ac_delim"'/g t clear :clear s/\\$// t bsnlc s/["\\]/\\&/g; s/^/"/; s/$/"/p d :bsnlc s/["\\]/\\&/g; s/^/"/; s/$/\\\\\\n"\\/p b cont ' >$CONFIG_STATUS || ac_write_fail=1 cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 for (key in D) D_is_set[key] = 1 FS = "" } /^[\t ]*#[\t ]*(define|undef)[\t ]+$ac_word_re([\t (]|\$)/ { line = \$ 0 split(line, arg, " ") if (arg[1] == "#") { defundef = arg[2] mac1 = arg[3] } else { defundef = substr(arg[1], 2) mac1 = arg[2] } split(mac1, mac2, "(") #) macro = mac2[1] prefix = substr(line, 1, index(line, defundef) - 1) if (D_is_set[macro]) { # Preserve the white space surrounding the "#". print prefix "define", macro P[macro] D[macro] next } else { # Replace #undef with comments. This is necessary, for example, # in the case of _POSIX_SOURCE, which is predefined and required # on some systems where configure will not decide to define it. if (defundef == "undef") { print "/*", prefix defundef, macro, "*/" next } } } { print } _ACAWK _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 as_fn_error $? "could not setup config headers machinery" "$LINENO" 5 fi # test -n "$CONFIG_HEADERS" eval set X " :F $CONFIG_FILES :H $CONFIG_HEADERS :C $CONFIG_COMMANDS" shift for ac_tag do case $ac_tag in :[FHLC]) ac_mode=$ac_tag; continue;; esac case $ac_mode$ac_tag in :[FHL]*:*);; :L* | :C*:*) as_fn_error $? "invalid tag \`$ac_tag'" "$LINENO" 5;; :[FH]-) ac_tag=-:-;; :[FH]*) ac_tag=$ac_tag:$ac_tag.in;; esac ac_save_IFS=$IFS IFS=: set x $ac_tag IFS=$ac_save_IFS shift ac_file=$1 shift case $ac_mode in :L) ac_source=$1;; :[FH]) ac_file_inputs= for ac_f do case $ac_f in -) ac_f="$ac_tmp/stdin";; *) # Look for the file first in the build tree, then in the source tree # (if the path is not absolute). The absolute path cannot be DOS-style, # because $ac_f cannot contain `:'. test -f "$ac_f" || case $ac_f in [\\/$]*) false;; *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";; esac || as_fn_error 1 "cannot find input file: \`$ac_f'" "$LINENO" 5;; esac case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac as_fn_append ac_file_inputs " '$ac_f'" done # Let's still pretend it is `configure' which instantiates (i.e., don't # use $as_me), people would be surprised to read: # /* config.h. Generated by config.status. */ configure_input='Generated from '` $as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g' `' by configure.' if test x"$ac_file" != x-; then configure_input="$ac_file. $configure_input" { $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5 $as_echo "$as_me: creating $ac_file" >&6;} fi # Neutralize special characters interpreted by sed in replacement strings. case $configure_input in #( *\&* | *\|* | *\\* ) ac_sed_conf_input=`$as_echo "$configure_input" | sed 's/[\\\\&|]/\\\\&/g'`;; #( *) ac_sed_conf_input=$configure_input;; esac case $ac_tag in *:-:* | *:-) cat >"$ac_tmp/stdin" \ || as_fn_error $? "could not create $ac_file" "$LINENO" 5 ;; esac ;; esac ac_dir=`$as_dirname -- "$ac_file" || $as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ X"$ac_file" : 'X\(//\)[^/]' \| \ X"$ac_file" : 'X\(//\)$' \| \ X"$ac_file" : 'X\(/\)' \| . 2>/dev/null || $as_echo X"$ac_file" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/ q } /^X\(\/\/\)[^/].*/{ s//\1/ q } /^X\(\/\/\)$/{ s//\1/ q } /^X\(\/\).*/{ s//\1/ q } s/.*/./; q'` as_dir="$ac_dir"; as_fn_mkdir_p ac_builddir=. case "$ac_dir" in .) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;; *) ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'` # A ".." for each directory in $ac_dir_suffix. ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'` case $ac_top_builddir_sub in "") ac_top_builddir_sub=. ac_top_build_prefix= ;; *) ac_top_build_prefix=$ac_top_builddir_sub/ ;; esac ;; esac ac_abs_top_builddir=$ac_pwd ac_abs_builddir=$ac_pwd$ac_dir_suffix # for backward compatibility: ac_top_builddir=$ac_top_build_prefix case $srcdir in .) # We are building in place. ac_srcdir=. ac_top_srcdir=$ac_top_builddir_sub ac_abs_top_srcdir=$ac_pwd ;; [\\/]* | ?:[\\/]* ) # Absolute name. ac_srcdir=$srcdir$ac_dir_suffix; ac_top_srcdir=$srcdir ac_abs_top_srcdir=$srcdir ;; *) # Relative name. ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix ac_top_srcdir=$ac_top_build_prefix$srcdir ac_abs_top_srcdir=$ac_pwd/$srcdir ;; esac ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix case $ac_mode in :F) # # CONFIG_FILE # case $INSTALL in [\\/$]* | ?:[\\/]* ) ac_INSTALL=$INSTALL ;; *) ac_INSTALL=$ac_top_build_prefix$INSTALL ;; esac ac_MKDIR_P=$MKDIR_P case $MKDIR_P in [\\/$]* | ?:[\\/]* ) ;; */*) ac_MKDIR_P=$ac_top_build_prefix$MKDIR_P ;; esac _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 # If the template does not know about datarootdir, expand it. # FIXME: This hack should be removed a few years after 2.60. ac_datarootdir_hack=; ac_datarootdir_seen= ac_sed_dataroot=' /datarootdir/ { p q } /@datadir@/p /@docdir@/p /@infodir@/p /@localedir@/p /@mandir@/p' case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in *datarootdir*) ac_datarootdir_seen=yes;; *@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5 $as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;} _ACEOF cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 ac_datarootdir_hack=' s&@datadir@&$datadir&g s&@docdir@&$docdir&g s&@infodir@&$infodir&g s&@localedir@&$localedir&g s&@mandir@&$mandir&g s&\\\${datarootdir}&$datarootdir&g' ;; esac _ACEOF # Neutralize VPATH when `$srcdir' = `.'. # Shell code in configure.ac might set extrasub. # FIXME: do we really want to maintain this feature? cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 ac_sed_extra="$ac_vpsub $extrasub _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 :t /@[a-zA-Z_][a-zA-Z_0-9]*@/!b s|@configure_input@|$ac_sed_conf_input|;t t s&@top_builddir@&$ac_top_builddir_sub&;t t s&@top_build_prefix@&$ac_top_build_prefix&;t t s&@srcdir@&$ac_srcdir&;t t s&@abs_srcdir@&$ac_abs_srcdir&;t t s&@top_srcdir@&$ac_top_srcdir&;t t s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t s&@builddir@&$ac_builddir&;t t s&@abs_builddir@&$ac_abs_builddir&;t t s&@abs_top_builddir@&$ac_abs_top_builddir&;t t s&@INSTALL@&$ac_INSTALL&;t t s&@MKDIR_P@&$ac_MKDIR_P&;t t $ac_datarootdir_hack " eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$ac_tmp/subs.awk" \ >$ac_tmp/out || as_fn_error $? "could not create $ac_file" "$LINENO" 5 test -z "$ac_datarootdir_hack$ac_datarootdir_seen" && { ac_out=`sed -n '/\${datarootdir}/p' "$ac_tmp/out"`; test -n "$ac_out"; } && { ac_out=`sed -n '/^[ ]*datarootdir[ ]*:*=/p' \ "$ac_tmp/out"`; test -z "$ac_out"; } && { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir' which seems to be undefined. Please make sure it is defined" >&5 $as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir' which seems to be undefined. Please make sure it is defined" >&2;} rm -f "$ac_tmp/stdin" case $ac_file in -) cat "$ac_tmp/out" && rm -f "$ac_tmp/out";; *) rm -f "$ac_file" && mv "$ac_tmp/out" "$ac_file";; esac \ || as_fn_error $? "could not create $ac_file" "$LINENO" 5 ;; :H) # # CONFIG_HEADER # if test x"$ac_file" != x-; then { $as_echo "/* $configure_input */" \ && eval '$AWK -f "$ac_tmp/defines.awk"' "$ac_file_inputs" } >"$ac_tmp/config.h" \ || as_fn_error $? "could not create $ac_file" "$LINENO" 5 if diff "$ac_file" "$ac_tmp/config.h" >/dev/null 2>&1; then { $as_echo "$as_me:${as_lineno-$LINENO}: $ac_file is unchanged" >&5 $as_echo "$as_me: $ac_file is unchanged" >&6;} else rm -f "$ac_file" mv "$ac_tmp/config.h" "$ac_file" \ || as_fn_error $? "could not create $ac_file" "$LINENO" 5 fi else $as_echo "/* $configure_input */" \ && eval '$AWK -f "$ac_tmp/defines.awk"' "$ac_file_inputs" \ || as_fn_error $? "could not create -" "$LINENO" 5 fi # Compute "$ac_file"'s index in $config_headers. _am_arg="$ac_file" _am_stamp_count=1 for _am_header in $config_headers :; do case $_am_header in $_am_arg | $_am_arg:* ) break ;; * ) _am_stamp_count=`expr $_am_stamp_count + 1` ;; esac done echo "timestamp for $_am_arg" >`$as_dirname -- "$_am_arg" || $as_expr X"$_am_arg" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ X"$_am_arg" : 'X\(//\)[^/]' \| \ X"$_am_arg" : 'X\(//\)$' \| \ X"$_am_arg" : 'X\(/\)' \| . 2>/dev/null || $as_echo X"$_am_arg" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/ q } /^X\(\/\/\)[^/].*/{ s//\1/ q } /^X\(\/\/\)$/{ s//\1/ q } /^X\(\/\).*/{ s//\1/ q } s/.*/./; q'`/stamp-h$_am_stamp_count ;; :C) { $as_echo "$as_me:${as_lineno-$LINENO}: executing $ac_file commands" >&5 $as_echo "$as_me: executing $ac_file commands" >&6;} ;; esac case $ac_file$ac_mode in "depfiles":C) test x"$AMDEP_TRUE" != x"" || { # Autoconf 2.62 quotes --file arguments for eval, but not when files # are listed without --file. Let's play safe and only enable the eval # if we detect the quoting. case $CONFIG_FILES in *\'*) eval set x "$CONFIG_FILES" ;; *) set x $CONFIG_FILES ;; esac shift for mf do # Strip MF so we end up with the name of the file. mf=`echo "$mf" | sed -e 's/:.*$//'` # Check whether this is an Automake generated Makefile or not. # We used to match only the files named `Makefile.in', but # some people rename them; so instead we look at the file content. # Grep'ing the first line is not enough: some people post-process # each Makefile.in and add a new line on top of each file to say so. # Grep'ing the whole file is not good either: AIX grep has a line # limit of 2048, but all sed's we know have understand at least 4000. if sed -n 's,^#.*generated by automake.*,X,p' "$mf" | grep X >/dev/null 2>&1; then dirpart=`$as_dirname -- "$mf" || $as_expr X"$mf" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ X"$mf" : 'X\(//\)[^/]' \| \ X"$mf" : 'X\(//\)$' \| \ X"$mf" : 'X\(/\)' \| . 2>/dev/null || $as_echo X"$mf" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/ q } /^X\(\/\/\)[^/].*/{ s//\1/ q } /^X\(\/\/\)$/{ s//\1/ q } /^X\(\/\).*/{ s//\1/ q } s/.*/./; q'` else continue fi # Extract the definition of DEPDIR, am__include, and am__quote # from the Makefile without running `make'. DEPDIR=`sed -n 's/^DEPDIR = //p' < "$mf"` test -z "$DEPDIR" && continue am__include=`sed -n 's/^am__include = //p' < "$mf"` test -z "am__include" && continue am__quote=`sed -n 's/^am__quote = //p' < "$mf"` # When using ansi2knr, U may be empty or an underscore; expand it U=`sed -n 's/^U = //p' < "$mf"` # Find all dependency output files, they are included files with # $(DEPDIR) in their names. We invoke sed twice because it is the # simplest approach to changing $(DEPDIR) to its actual value in the # expansion. for file in `sed -n " s/^$am__include $am__quote\(.*(DEPDIR).*\)$am__quote"'$/\1/p' <"$mf" | \ sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g' -e 's/\$U/'"$U"'/g'`; do # Make sure the directory exists. test -f "$dirpart/$file" && continue fdir=`$as_dirname -- "$file" || $as_expr X"$file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ X"$file" : 'X\(//\)[^/]' \| \ X"$file" : 'X\(//\)$' \| \ X"$file" : 'X\(/\)' \| . 2>/dev/null || $as_echo X"$file" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/ q } /^X\(\/\/\)[^/].*/{ s//\1/ q } /^X\(\/\/\)$/{ s//\1/ q } /^X\(\/\).*/{ s//\1/ q } s/.*/./; q'` as_dir=$dirpart/$fdir; as_fn_mkdir_p # echo "creating $dirpart/$file" echo '# dummy' > "$dirpart/$file" done done } ;; "libtool":C) # See if we are running on zsh, and set the options which allow our # commands through without removal of \ escapes. if test -n "${ZSH_VERSION+set}" ; then setopt NO_GLOB_SUBST fi cfgfile="${ofile}T" trap "$RM \"$cfgfile\"; exit 1" 1 2 15 $RM "$cfgfile" cat <<_LT_EOF >> "$cfgfile" #! $SHELL # `$ECHO "$ofile" | sed 's%^.*/%%'` - Provide generalized library-building support services. # Generated automatically by $as_me ($PACKAGE$TIMESTAMP) $VERSION # Libtool was configured on host `(hostname || uname -n) 2>/dev/null | sed 1q`: # NOTE: Changes made to this file will be lost: look at ltmain.sh. # # Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, # 2006, 2007, 2008, 2009, 2010 Free Software Foundation, # Inc. # Written by Gordon Matzigkeit, 1996 # # This file is part of GNU Libtool. # # GNU Libtool is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # As a special exception to the GNU General Public License, # if you distribute this file as part of a program or library that # is built using GNU Libtool, you may include this file under the # same distribution terms that you use for the rest of that program. # # GNU Libtool is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with GNU Libtool; see the file COPYING. If not, a copy # can be downloaded from http://www.gnu.org/licenses/gpl.html, or # obtained by writing to the Free Software Foundation, Inc., # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. # The names of the tagged configurations supported by this script. available_tags="" # ### BEGIN LIBTOOL CONFIG # Which release of libtool.m4 was used? macro_version=$macro_version macro_revision=$macro_revision # Whether or not to build shared libraries. build_libtool_libs=$enable_shared # Whether or not to build static libraries. build_old_libs=$enable_static # What type of objects to build. pic_mode=$pic_mode # Whether or not to optimize for fast installation. fast_install=$enable_fast_install # Shell to use when invoking shell scripts. SHELL=$lt_SHELL # An echo program that protects backslashes. ECHO=$lt_ECHO # The host system. host_alias=$host_alias host=$host host_os=$host_os # The build system. build_alias=$build_alias build=$build build_os=$build_os # A sed program that does not truncate output. SED=$lt_SED # Sed that helps us avoid accidentally triggering echo(1) options like -n. Xsed="\$SED -e 1s/^X//" # A grep program that handles long lines. GREP=$lt_GREP # An ERE matcher. EGREP=$lt_EGREP # A literal string matcher. FGREP=$lt_FGREP # A BSD- or MS-compatible name lister. NM=$lt_NM # Whether we need soft or hard links. LN_S=$lt_LN_S # What is the maximum length of a command? max_cmd_len=$max_cmd_len # Object file suffix (normally "o"). objext=$ac_objext # Executable file suffix (normally ""). exeext=$exeext # whether the shell understands "unset". lt_unset=$lt_unset # turn spaces into newlines. SP2NL=$lt_lt_SP2NL # turn newlines into spaces. NL2SP=$lt_lt_NL2SP # convert \$build file names to \$host format. to_host_file_cmd=$lt_cv_to_host_file_cmd # convert \$build files to toolchain format. to_tool_file_cmd=$lt_cv_to_tool_file_cmd # An object symbol dumper. OBJDUMP=$lt_OBJDUMP # Method to check whether dependent libraries are shared objects. deplibs_check_method=$lt_deplibs_check_method # Command to use when deplibs_check_method = "file_magic". file_magic_cmd=$lt_file_magic_cmd # How to find potential files when deplibs_check_method = "file_magic". file_magic_glob=$lt_file_magic_glob # Find potential files using nocaseglob when deplibs_check_method = "file_magic". want_nocaseglob=$lt_want_nocaseglob # DLL creation program. DLLTOOL=$lt_DLLTOOL # Command to associate shared and link libraries. sharedlib_from_linklib_cmd=$lt_sharedlib_from_linklib_cmd # The archiver. AR=$lt_AR # Flags to create an archive. AR_FLAGS=$lt_AR_FLAGS # How to feed a file listing to the archiver. archiver_list_spec=$lt_archiver_list_spec # A symbol stripping program. STRIP=$lt_STRIP # Commands used to install an old-style archive. RANLIB=$lt_RANLIB old_postinstall_cmds=$lt_old_postinstall_cmds old_postuninstall_cmds=$lt_old_postuninstall_cmds # Whether to use a lock for old archive extraction. lock_old_archive_extraction=$lock_old_archive_extraction # A C compiler. LTCC=$lt_CC # LTCC compiler flags. LTCFLAGS=$lt_CFLAGS # Take the output of nm and produce a listing of raw symbols and C names. global_symbol_pipe=$lt_lt_cv_sys_global_symbol_pipe # Transform the output of nm in a proper C declaration. global_symbol_to_cdecl=$lt_lt_cv_sys_global_symbol_to_cdecl # Transform the output of nm in a C name address pair. global_symbol_to_c_name_address=$lt_lt_cv_sys_global_symbol_to_c_name_address # Transform the output of nm in a C name address pair when lib prefix is needed. global_symbol_to_c_name_address_lib_prefix=$lt_lt_cv_sys_global_symbol_to_c_name_address_lib_prefix # Specify filename containing input files for \$NM. nm_file_list_spec=$lt_nm_file_list_spec # The root where to search for dependent libraries,and in which our libraries should be installed. lt_sysroot=$lt_sysroot # The name of the directory that contains temporary libtool files. objdir=$objdir # Used to examine libraries when file_magic_cmd begins with "file". MAGIC_CMD=$MAGIC_CMD # Must we lock files when doing compilation? need_locks=$lt_need_locks # Manifest tool. MANIFEST_TOOL=$lt_MANIFEST_TOOL # Tool to manipulate archived DWARF debug symbol files on Mac OS X. DSYMUTIL=$lt_DSYMUTIL # Tool to change global to local symbols on Mac OS X. NMEDIT=$lt_NMEDIT # Tool to manipulate fat objects and archives on Mac OS X. LIPO=$lt_LIPO # ldd/readelf like tool for Mach-O binaries on Mac OS X. OTOOL=$lt_OTOOL # ldd/readelf like tool for 64 bit Mach-O binaries on Mac OS X 10.4. OTOOL64=$lt_OTOOL64 # Old archive suffix (normally "a"). libext=$libext # Shared library suffix (normally ".so"). shrext_cmds=$lt_shrext_cmds # The commands to extract the exported symbol list from a shared archive. extract_expsyms_cmds=$lt_extract_expsyms_cmds # Variables whose values should be saved in libtool wrapper scripts and # restored at link time. variables_saved_for_relink=$lt_variables_saved_for_relink # Do we need the "lib" prefix for modules? need_lib_prefix=$need_lib_prefix # Do we need a version for libraries? need_version=$need_version # Library versioning type. version_type=$version_type # Shared library runtime path variable. runpath_var=$runpath_var # Shared library path variable. shlibpath_var=$shlibpath_var # Is shlibpath searched before the hard-coded library search path? shlibpath_overrides_runpath=$shlibpath_overrides_runpath # Format of library name prefix. libname_spec=$lt_libname_spec # List of archive names. First name is the real one, the rest are links. # The last name is the one that the linker finds with -lNAME library_names_spec=$lt_library_names_spec # The coded name of the library, if different from the real name. soname_spec=$lt_soname_spec # Permission mode override for installation of shared libraries. install_override_mode=$lt_install_override_mode # Command to use after installation of a shared archive. postinstall_cmds=$lt_postinstall_cmds # Command to use after uninstallation of a shared archive. postuninstall_cmds=$lt_postuninstall_cmds # Commands used to finish a libtool library installation in a directory. finish_cmds=$lt_finish_cmds # As "finish_cmds", except a single script fragment to be evaled but # not shown. finish_eval=$lt_finish_eval # Whether we should hardcode library paths into libraries. hardcode_into_libs=$hardcode_into_libs # Compile-time system search path for libraries. sys_lib_search_path_spec=$lt_sys_lib_search_path_spec # Run-time system search path for libraries. sys_lib_dlsearch_path_spec=$lt_sys_lib_dlsearch_path_spec # Whether dlopen is supported. dlopen_support=$enable_dlopen # Whether dlopen of programs is supported. dlopen_self=$enable_dlopen_self # Whether dlopen of statically linked programs is supported. dlopen_self_static=$enable_dlopen_self_static # Commands to strip libraries. old_striplib=$lt_old_striplib striplib=$lt_striplib # The linker used to build libraries. LD=$lt_LD # How to create reloadable object files. reload_flag=$lt_reload_flag reload_cmds=$lt_reload_cmds # Commands used to build an old-style archive. old_archive_cmds=$lt_old_archive_cmds # A language specific compiler. CC=$lt_compiler # Is the compiler the GNU compiler? with_gcc=$GCC # Compiler flag to turn off builtin functions. no_builtin_flag=$lt_lt_prog_compiler_no_builtin_flag # Additional compiler flags for building library objects. pic_flag=$lt_lt_prog_compiler_pic # How to pass a linker flag through the compiler. wl=$lt_lt_prog_compiler_wl # Compiler flag to prevent dynamic linking. link_static_flag=$lt_lt_prog_compiler_static # Does compiler simultaneously support -c and -o options? compiler_c_o=$lt_lt_cv_prog_compiler_c_o # Whether or not to add -lc for building shared libraries. build_libtool_need_lc=$archive_cmds_need_lc # Whether or not to disallow shared libs when runtime libs are static. allow_libtool_libs_with_static_runtimes=$enable_shared_with_static_runtimes # Compiler flag to allow reflexive dlopens. export_dynamic_flag_spec=$lt_export_dynamic_flag_spec # Compiler flag to generate shared objects directly from archives. whole_archive_flag_spec=$lt_whole_archive_flag_spec # Whether the compiler copes with passing no objects directly. compiler_needs_object=$lt_compiler_needs_object # Create an old-style archive from a shared archive. old_archive_from_new_cmds=$lt_old_archive_from_new_cmds # Create a temporary old-style archive to link instead of a shared archive. old_archive_from_expsyms_cmds=$lt_old_archive_from_expsyms_cmds # Commands used to build a shared archive. archive_cmds=$lt_archive_cmds archive_expsym_cmds=$lt_archive_expsym_cmds # Commands used to build a loadable module if different from building # a shared archive. module_cmds=$lt_module_cmds module_expsym_cmds=$lt_module_expsym_cmds # Whether we are building with GNU ld or not. with_gnu_ld=$lt_with_gnu_ld # Flag that allows shared libraries with undefined symbols to be built. allow_undefined_flag=$lt_allow_undefined_flag # Flag that enforces no undefined symbols. no_undefined_flag=$lt_no_undefined_flag # Flag to hardcode \$libdir into a binary during linking. # This must work even if \$libdir does not exist hardcode_libdir_flag_spec=$lt_hardcode_libdir_flag_spec # If ld is used when linking, flag to hardcode \$libdir into a binary # during linking. This must work even if \$libdir does not exist. hardcode_libdir_flag_spec_ld=$lt_hardcode_libdir_flag_spec_ld # Whether we need a single "-rpath" flag with a separated argument. hardcode_libdir_separator=$lt_hardcode_libdir_separator # Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes # DIR into the resulting binary. hardcode_direct=$hardcode_direct # Set to "yes" if using DIR/libNAME\${shared_ext} during linking hardcodes # DIR into the resulting binary and the resulting library dependency is # "absolute",i.e impossible to change by setting \${shlibpath_var} if the # library is relocated. hardcode_direct_absolute=$hardcode_direct_absolute # Set to "yes" if using the -LDIR flag during linking hardcodes DIR # into the resulting binary. hardcode_minus_L=$hardcode_minus_L # Set to "yes" if using SHLIBPATH_VAR=DIR during linking hardcodes DIR # into the resulting binary. hardcode_shlibpath_var=$hardcode_shlibpath_var # Set to "yes" if building a shared library automatically hardcodes DIR # into the library and all subsequent libraries and executables linked # against it. hardcode_automatic=$hardcode_automatic # Set to yes if linker adds runtime paths of dependent libraries # to runtime path list. inherit_rpath=$inherit_rpath # Whether libtool must link a program against all its dependency libraries. link_all_deplibs=$link_all_deplibs # Set to "yes" if exported symbols are required. always_export_symbols=$always_export_symbols # The commands to list exported symbols. export_symbols_cmds=$lt_export_symbols_cmds # Symbols that should not be listed in the preloaded symbols. exclude_expsyms=$lt_exclude_expsyms # Symbols that must always be exported. include_expsyms=$lt_include_expsyms # Commands necessary for linking programs (against libraries) with templates. prelink_cmds=$lt_prelink_cmds # Commands necessary for finishing linking programs. postlink_cmds=$lt_postlink_cmds # Specify filename containing input files. file_list_spec=$lt_file_list_spec # How to hardcode a shared library path into an executable. hardcode_action=$hardcode_action # ### END LIBTOOL CONFIG _LT_EOF case $host_os in aix3*) cat <<\_LT_EOF >> "$cfgfile" # AIX sometimes has problems with the GCC collect2 program. For some # reason, if we set the COLLECT_NAMES environment variable, the problems # vanish in a puff of smoke. if test "X${COLLECT_NAMES+set}" != Xset; then COLLECT_NAMES= export COLLECT_NAMES fi _LT_EOF ;; esac ltmain="$ac_aux_dir/ltmain.sh" # We use sed instead of cat because bash on DJGPP gets confused if # if finds mixed CR/LF and LF-only lines. Since sed operates in # text mode, it properly converts lines to CR/LF. This bash problem # is reportedly fixed, but why not run on old versions too? sed '$q' "$ltmain" >> "$cfgfile" \ || (rm -f "$cfgfile"; exit 1) if test x"$xsi_shell" = xyes; then sed -e '/^func_dirname ()$/,/^} # func_dirname /c\ func_dirname ()\ {\ \ case ${1} in\ \ */*) func_dirname_result="${1%/*}${2}" ;;\ \ * ) func_dirname_result="${3}" ;;\ \ esac\ } # Extended-shell func_dirname implementation' "$cfgfile" > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: sed -e '/^func_basename ()$/,/^} # func_basename /c\ func_basename ()\ {\ \ func_basename_result="${1##*/}"\ } # Extended-shell func_basename implementation' "$cfgfile" > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: sed -e '/^func_dirname_and_basename ()$/,/^} # func_dirname_and_basename /c\ func_dirname_and_basename ()\ {\ \ case ${1} in\ \ */*) func_dirname_result="${1%/*}${2}" ;;\ \ * ) func_dirname_result="${3}" ;;\ \ esac\ \ func_basename_result="${1##*/}"\ } # Extended-shell func_dirname_and_basename implementation' "$cfgfile" > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: sed -e '/^func_stripname ()$/,/^} # func_stripname /c\ func_stripname ()\ {\ \ # pdksh 5.2.14 does not do ${X%$Y} correctly if both X and Y are\ \ # positional parameters, so assign one to ordinary parameter first.\ \ func_stripname_result=${3}\ \ func_stripname_result=${func_stripname_result#"${1}"}\ \ func_stripname_result=${func_stripname_result%"${2}"}\ } # Extended-shell func_stripname implementation' "$cfgfile" > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: sed -e '/^func_split_long_opt ()$/,/^} # func_split_long_opt /c\ func_split_long_opt ()\ {\ \ func_split_long_opt_name=${1%%=*}\ \ func_split_long_opt_arg=${1#*=}\ } # Extended-shell func_split_long_opt implementation' "$cfgfile" > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: sed -e '/^func_split_short_opt ()$/,/^} # func_split_short_opt /c\ func_split_short_opt ()\ {\ \ func_split_short_opt_arg=${1#??}\ \ func_split_short_opt_name=${1%"$func_split_short_opt_arg"}\ } # Extended-shell func_split_short_opt implementation' "$cfgfile" > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: sed -e '/^func_lo2o ()$/,/^} # func_lo2o /c\ func_lo2o ()\ {\ \ case ${1} in\ \ *.lo) func_lo2o_result=${1%.lo}.${objext} ;;\ \ *) func_lo2o_result=${1} ;;\ \ esac\ } # Extended-shell func_lo2o implementation' "$cfgfile" > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: sed -e '/^func_xform ()$/,/^} # func_xform /c\ func_xform ()\ {\ func_xform_result=${1%.*}.lo\ } # Extended-shell func_xform implementation' "$cfgfile" > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: sed -e '/^func_arith ()$/,/^} # func_arith /c\ func_arith ()\ {\ func_arith_result=$(( $* ))\ } # Extended-shell func_arith implementation' "$cfgfile" > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: sed -e '/^func_len ()$/,/^} # func_len /c\ func_len ()\ {\ func_len_result=${#1}\ } # Extended-shell func_len implementation' "$cfgfile" > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: fi if test x"$lt_shell_append" = xyes; then sed -e '/^func_append ()$/,/^} # func_append /c\ func_append ()\ {\ eval "${1}+=\\${2}"\ } # Extended-shell func_append implementation' "$cfgfile" > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: sed -e '/^func_append_quoted ()$/,/^} # func_append_quoted /c\ func_append_quoted ()\ {\ \ func_quote_for_eval "${2}"\ \ eval "${1}+=\\\\ \\$func_quote_for_eval_result"\ } # Extended-shell func_append_quoted implementation' "$cfgfile" > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: # Save a `func_append' function call where possible by direct use of '+=' sed -e 's%func_append \([a-zA-Z_]\{1,\}\) "%\1+="%g' $cfgfile > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: else # Save a `func_append' function call even when '+=' is not available sed -e 's%func_append \([a-zA-Z_]\{1,\}\) "%\1="$\1%g' $cfgfile > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: fi if test x"$_lt_function_replace_fail" = x":"; then { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: Unable to substitute extended shell functions in $ofile" >&5 $as_echo "$as_me: WARNING: Unable to substitute extended shell functions in $ofile" >&2;} fi mv -f "$cfgfile" "$ofile" || (rm -f "$ofile" && cp "$cfgfile" "$ofile" && rm -f "$cfgfile") chmod +x "$ofile" ;; esac done # for ac_tag as_fn_exit 0 _ACEOF ac_clean_files=$ac_clean_files_save test $ac_write_fail = 0 || as_fn_error $? "write failure creating $CONFIG_STATUS" "$LINENO" 5 # configure is writing to config.log, and then calls config.status. # config.status does its own redirection, appending to config.log. # Unfortunately, on DOS this fails, as config.log is still kept open # by configure, so config.status won't be able to write to it; its # output is simply discarded. So we exec the FD to /dev/null, # effectively closing config.log, so it can be properly (re)opened and # appended to by config.status. When coming back to configure, we # need to make the FD available again. if test "$no_create" != yes; then ac_cs_success=: ac_config_status_args= test "$silent" = yes && ac_config_status_args="$ac_config_status_args --quiet" exec 5>/dev/null $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false exec 5>>config.log # Use ||, not &&, to avoid exiting from the if with $? = 1, which # would make configure fail if this is the last instruction. $ac_cs_success || as_fn_exit 1 fi if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 $as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} fi crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/autoregen.sh0000755000175000017500000000003311610313113024411 0ustar andresandres#!/bin/sh ./autogen.sh $@ crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/COPYING0000644000175000017500000006351011610313111023123 0ustar andresandres GNU LESSER GENERAL PUBLIC LICENSE Version 2.1, February 1999 Copyright (C) 1991, 1999 Free Software Foundation, Inc. 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. [This is the first released version of the Lesser GPL. It also counts as the successor of the GNU Library Public License, version 2, hence the version number 2.1.] Preamble The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public Licenses are intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This license, the Lesser General Public License, applies to some specially designated software packages--typically libraries--of the Free Software Foundation and other authors who decide to use it. You can use it too, but we suggest you first think carefully about whether this license or the ordinary General Public License is the better strategy to use in any particular case, based on the explanations below. When we speak of free software, we are referring to freedom of use, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish); that you receive source code or can get it if you want it; that you can change the software and use pieces of it in new free programs; and that you are informed that you can do these things. To protect your rights, we need to make restrictions that forbid distributors to deny you these rights or to ask you to surrender these rights. These restrictions translate to certain responsibilities for you if you distribute copies of the library or if you modify it. For example, if you distribute copies of the library, whether gratis or for a fee, you must give the recipients all the rights that we gave you. You must make sure that they, too, receive or can get the source code. If you link other code with the library, you must provide complete object files to the recipients, so that they can relink them with the library after making changes to the library and recompiling it. And you must show them these terms so they know their rights. We protect your rights with a two-step method: (1) we copyright the library, and (2) we offer you this license, which gives you legal permission to copy, distribute and/or modify the library. To protect each distributor, we want to make it very clear that there is no warranty for the free library. Also, if the library is modified by someone else and passed on, the recipients should know that what they have is not the original version, so that the original author's reputation will not be affected by problems that might be introduced by others. Finally, software patents pose a constant threat to the existence of any free program. We wish to make sure that a company cannot effectively restrict the users of a free program by obtaining a restrictive license from a patent holder. Therefore, we insist that any patent license obtained for a version of the library must be consistent with the full freedom of use specified in this license. Most GNU software, including some libraries, is covered by the ordinary GNU General Public License. This license, the GNU Lesser General Public License, applies to certain designated libraries, and is quite different from the ordinary General Public License. We use this license for certain libraries in order to permit linking those libraries into non-free programs. When a program is linked with a library, whether statically or using a shared library, the combination of the two is legally speaking a combined work, a derivative of the original library. The ordinary General Public License therefore permits such linking only if the entire combination fits its criteria of freedom. The Lesser General Public License permits more lax criteria for linking other code with the library. We call this license the "Lesser" General Public License because it does Less to protect the user's freedom than the ordinary General Public License. It also provides other free software developers Less of an advantage over competing non-free programs. These disadvantages are the reason we use the ordinary General Public License for many libraries. However, the Lesser license provides advantages in certain special circumstances. For example, on rare occasions, there may be a special need to encourage the widest possible use of a certain library, so that it becomes a de-facto standard. To achieve this, non-free programs must be allowed to use the library. A more frequent case is that a free library does the same job as widely used non-free libraries. In this case, there is little to gain by limiting the free library to free software only, so we use the Lesser General Public License. In other cases, permission to use a particular library in non-free programs enables a greater number of people to use a large body of free software. For example, permission to use the GNU C Library in non-free programs enables many more people to use the whole GNU operating system, as well as its variant, the GNU/Linux operating system. Although the Lesser General Public License is Less protective of the users' freedom, it does ensure that the user of a program that is linked with the Library has the freedom and the wherewithal to run that program using a modified version of the Library. The precise terms and conditions for copying, distribution and modification follow. Pay close attention to the difference between a "work based on the library" and a "work that uses the library". The former contains code derived from the library, whereas the latter must be combined with the library in order to run. GNU LESSER GENERAL PUBLIC LICENSE TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION 0. This License Agreement applies to any software library or other program which contains a notice placed by the copyright holder or other authorized party saying it may be distributed under the terms of this Lesser General Public License (also called "this License"). Each licensee is addressed as "you". A "library" means a collection of software functions and/or data prepared so as to be conveniently linked with application programs (which use some of those functions and data) to form executables. The "Library", below, refers to any such software library or work which has been distributed under these terms. A "work based on the Library" means either the Library or any derivative work under copyright law: that is to say, a work containing the Library or a portion of it, either verbatim or with modifications and/or translated straightforwardly into another language. (Hereinafter, translation is included without limitation in the term "modification".) "Source code" for a work means the preferred form of the work for making modifications to it. For a library, complete source code means all the source code for all modules it contains, plus any associated interface definition files, plus the scripts used to control compilation and installation of the library. Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running a program using the Library is not restricted, and output from such a program is covered only if its contents constitute a work based on the Library (independent of the use of the Library in a tool for writing it). Whether that is true depends on what the Library does and what the program that uses the Library does. 1. You may copy and distribute verbatim copies of the Library's complete source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and distribute a copy of this License along with the Library. You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. 2. You may modify your copy or copies of the Library or any portion of it, thus forming a work based on the Library, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: a) The modified work must itself be a software library. b) You must cause the files modified to carry prominent notices stating that you changed the files and the date of any change. c) You must cause the whole of the work to be licensed at no charge to all third parties under the terms of this License. d) If a facility in the modified Library refers to a function or a table of data to be supplied by an application program that uses the facility, other than as an argument passed when the facility is invoked, then you must make a good faith effort to ensure that, in the event an application does not supply such function or table, the facility still operates, and performs whatever part of its purpose remains meaningful. (For example, a function in a library to compute square roots has a purpose that is entirely well-defined independent of the application. Therefore, Subsection 2d requires that any application-supplied function or table used by this function must be optional: if the application does not supply it, the square root function must still compute square roots.) These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Library, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Library, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Library. In addition, mere aggregation of another work not based on the Library with the Library (or with a work based on the Library) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. 3. You may opt to apply the terms of the ordinary GNU General Public License instead of this License to a given copy of the Library. To do this, you must alter all the notices that refer to this License, so that they refer to the ordinary GNU General Public License, version 2, instead of to this License. (If a newer version than version 2 of the ordinary GNU General Public License has appeared, then you can specify that version instead if you wish.) Do not make any other change in these notices. Once this change is made in a given copy, it is irreversible for that copy, so the ordinary GNU General Public License applies to all subsequent copies and derivative works made from that copy. This option is useful when you wish to copy part of the code of the Library into a program that is not a library. 4. You may copy and distribute the Library (or a portion or derivative of it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange. If distribution of object code is made by offering access to copy from a designated place, then offering equivalent access to copy the source code from the same place satisfies the requirement to distribute the source code, even though third parties are not compelled to copy the source along with the object code. 5. A program that contains no derivative of any portion of the Library, but is designed to work with the Library by being compiled or linked with it, is called a "work that uses the Library". Such a work, in isolation, is not a derivative work of the Library, and therefore falls outside the scope of this License. However, linking a "work that uses the Library" with the Library creates an executable that is a derivative of the Library (because it contains portions of the Library), rather than a "work that uses the library". The executable is therefore covered by this License. Section 6 states terms for distribution of such executables. When a "work that uses the Library" uses material from a header file that is part of the Library, the object code for the work may be a derivative work of the Library even though the source code is not. Whether this is true is especially significant if the work can be linked without the Library, or if the work is itself a library. The threshold for this to be true is not precisely defined by law. If such an object file uses only numerical parameters, data structure layouts and accessors, and small macros and small inline functions (ten lines or less in length), then the use of the object file is unrestricted, regardless of whether it is legally a derivative work. (Executables containing this object code plus portions of the Library will still fall under Section 6.) Otherwise, if the work is a derivative of the Library, you may distribute the object code for the work under the terms of Section 6. Any executables containing that work also fall under Section 6, whether or not they are linked directly with the Library itself. 6. As an exception to the Sections above, you may also combine or link a "work that uses the Library" with the Library to produce a work containing portions of the Library, and distribute that work under terms of your choice, provided that the terms permit modification of the work for the customer's own use and reverse engineering for debugging such modifications. You must give prominent notice with each copy of the work that the Library is used in it and that the Library and its use are covered by this License. You must supply a copy of this License. If the work during execution displays copyright notices, you must include the copyright notice for the Library among them, as well as a reference directing the user to the copy of this License. Also, you must do one of these things: a) Accompany the work with the complete corresponding machine-readable source code for the Library including whatever changes were used in the work (which must be distributed under Sections 1 and 2 above); and, if the work is an executable linked with the Library, with the complete machine-readable "work that uses the Library", as object code and/or source code, so that the user can modify the Library and then relink to produce a modified executable containing the modified Library. (It is understood that the user who changes the contents of definitions files in the Library will not necessarily be able to recompile the application to use the modified definitions.) b) Use a suitable shared library mechanism for linking with the Library. A suitable mechanism is one that (1) uses at run time a copy of the library already present on the user's computer system, rather than copying library functions into the executable, and (2) will operate properly with a modified version of the library, if the user installs one, as long as the modified version is interface-compatible with the version that the work was made with. c) Accompany the work with a written offer, valid for at least three years, to give the same user the materials specified in Subsection 6a, above, for a charge no more than the cost of performing this distribution. d) If distribution of the work is made by offering access to copy from a designated place, offer equivalent access to copy the above specified materials from the same place. e) Verify that the user has already received a copy of these materials or that you have already sent this user a copy. For an executable, the required form of the "work that uses the Library" must include any data and utility programs needed for reproducing the executable from it. However, as a special exception, the materials to be distributed need not include anything that is normally distributed (in either source or binary form) with the major components (compiler, kernel, and so on) of the operating system on which the executable runs, unless that component itself accompanies the executable. It may happen that this requirement contradicts the license restrictions of other proprietary libraries that do not normally accompany the operating system. Such a contradiction means you cannot use both them and the Library together in an executable that you distribute. 7. You may place library facilities that are a work based on the Library side-by-side in a single library together with other library facilities not covered by this License, and distribute such a combined library, provided that the separate distribution of the work based on the Library and of the other library facilities is otherwise permitted, and provided that you do these two things: a) Accompany the combined library with a copy of the same work based on the Library, uncombined with any other library facilities. This must be distributed under the terms of the Sections above. b) Give prominent notice with the combined library of the fact that part of it is a work based on the Library, and explaining where to find the accompanying uncombined form of the same work. 8. You may not copy, modify, sublicense, link with, or distribute the Library except as expressly provided under this License. Any attempt otherwise to copy, modify, sublicense, link with, or distribute the Library is void, and will automatically terminate your rights under this License. However, parties who have received copies, or rights, from you under this License will not have their licenses terminated so long as such parties remain in full compliance. 9. You are not required to accept this License, since you have not signed it. However, nothing else grants you permission to modify or distribute the Library or its derivative works. These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Library (or any work based on the Library), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Library or works based on it. 10. Each time you redistribute the Library (or any work based on the Library), the recipient automatically receives a license from the original licensor to copy, distribute, link with or modify the Library subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties with this License. 11. If, as a consequence of a court judgment or allegation of patent infringement or for any other reason (not limited to patent issues), conditions are imposed on you (whether by court order, agreement or otherwise) that contradict the conditions of this License, they do not excuse you from the conditions of this License. If you cannot distribute so as to satisfy simultaneously your obligations under this License and any other pertinent obligations, then as a consequence you may not distribute the Library at all. For example, if a patent license would not permit royalty-free redistribution of the Library by all those who receive copies directly or indirectly through you, then the only way you could satisfy both it and this License would be to refrain entirely from distribution of the Library. If any portion of this section is held invalid or unenforceable under any particular circumstance, the balance of the section is intended to apply, and the section as a whole is intended to apply in other circumstances. It is not the purpose of this section to induce you to infringe any patents or other property right claims or to contest validity of any such claims; this section has the sole purpose of protecting the integrity of the free software distribution system which is implemented by public license practices. Many people have made generous contributions to the wide range of software distributed through that system in reliance on consistent application of that system; it is up to the author/donor to decide if he or she is willing to distribute software through any other system and a licensee cannot impose that choice. This section is intended to make thoroughly clear what is believed to be a consequence of the rest of this License. 12. If the distribution and/or use of the Library is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Library under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. 13. The Free Software Foundation may publish revised and/or new versions of the Lesser General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. Each version is given a distinguishing version number. If the Library specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Library does not specify a license version number, you may choose any version ever published by the Free Software Foundation. 14. If you wish to incorporate parts of the Library into other free programs whose distribution conditions are incompatible with these, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. NO WARRANTY 15. BECAUSE THE LIBRARY IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE LIBRARY, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE LIBRARY "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE LIBRARY IS WITH YOU. SHOULD THE LIBRARY PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 16. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE LIBRARY AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE LIBRARY (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE LIBRARY TO OPERATE WITH ANY OTHER SOFTWARE), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. END OF TERMS AND CONDITIONS How to Apply These Terms to Your New Libraries If you develop a new library, and you want it to be of the greatest possible use to the public, we recommend making it free software that everyone can redistribute and change. You can do so by permitting redistribution under these terms (or, alternatively, under the terms of the ordinary General Public License). To apply these terms, attach the following notices to the library. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. Copyright (C) This library is free software; you can redistribute it and/or modify it under the terms of the GNU Lesser General Public License as published by the Free Software Foundation; either version 2.1 of the License, or (at your option) any later version. This library is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU Lesser General Public License for more details. You should have received a copy of the GNU Lesser General Public License along with this library; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA Also add information on how to contact you by electronic and paper mail. You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the library, if necessary. Here is a sample; alter the names: Yoyodyne, Inc., hereby disclaims all copyright interest in the library `Frob' (a library for tweaking knobs) written by James Random Hacker. , 1 April 1990 Ty Coon, President of Vice That's all there is to it! crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/install-sh0000644000175000017500000003246411610313111024075 0ustar andresandres#!/bin/sh # install - install a program, script, or datafile scriptversion=2006-12-25.00 # This originates from X11R5 (mit/util/scripts/install.sh), which was # later released in X11R6 (xc/config/util/install.sh) with the # following copyright and license. # # Copyright (C) 1994 X Consortium # # Permission is hereby granted, free of charge, to any person obtaining a copy # of this software and associated documentation files (the "Software"), to # deal in the Software without restriction, including without limitation the # rights to use, copy, modify, merge, publish, distribute, sublicense, and/or # sell copies of the Software, and to permit persons to whom the Software is # furnished to do so, subject to the following conditions: # # The above copyright notice and this permission notice shall be included in # all copies or substantial portions of the Software. # # THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR # IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, # FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE # X CONSORTIUM BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN # AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNEC- # TION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. # # Except as contained in this notice, the name of the X Consortium shall not # be used in advertising or otherwise to promote the sale, use or other deal- # ings in this Software without prior written authorization from the X Consor- # tium. # # # FSF changes to this file are in the public domain. # # Calling this script install-sh is preferred over install.sh, to prevent # `make' implicit rules from creating a file called install from it # when there is no Makefile. # # This script is compatible with the BSD install script, but was written # from scratch. nl=' ' IFS=" "" $nl" # set DOITPROG to echo to test this script # Don't use :- since 4.3BSD and earlier shells don't like it. doit=${DOITPROG-} if test -z "$doit"; then doit_exec=exec else doit_exec=$doit fi # Put in absolute file names if you don't have them in your path; # or use environment vars. chgrpprog=${CHGRPPROG-chgrp} chmodprog=${CHMODPROG-chmod} chownprog=${CHOWNPROG-chown} cmpprog=${CMPPROG-cmp} cpprog=${CPPROG-cp} mkdirprog=${MKDIRPROG-mkdir} mvprog=${MVPROG-mv} rmprog=${RMPROG-rm} stripprog=${STRIPPROG-strip} posix_glob='?' initialize_posix_glob=' test "$posix_glob" != "?" || { if (set -f) 2>/dev/null; then posix_glob= else posix_glob=: fi } ' posix_mkdir= # Desired mode of installed file. mode=0755 chgrpcmd= chmodcmd=$chmodprog chowncmd= mvcmd=$mvprog rmcmd="$rmprog -f" stripcmd= src= dst= dir_arg= dst_arg= copy_on_change=false no_target_directory= usage="\ Usage: $0 [OPTION]... [-T] SRCFILE DSTFILE or: $0 [OPTION]... SRCFILES... DIRECTORY or: $0 [OPTION]... -t DIRECTORY SRCFILES... or: $0 [OPTION]... -d DIRECTORIES... In the 1st form, copy SRCFILE to DSTFILE. In the 2nd and 3rd, copy all SRCFILES to DIRECTORY. In the 4th, create DIRECTORIES. Options: --help display this help and exit. --version display version info and exit. -c (ignored) -C install only if different (preserve the last data modification time) -d create directories instead of installing files. -g GROUP $chgrpprog installed files to GROUP. -m MODE $chmodprog installed files to MODE. -o USER $chownprog installed files to USER. -s $stripprog installed files. -t DIRECTORY install into DIRECTORY. -T report an error if DSTFILE is a directory. Environment variables override the default commands: CHGRPPROG CHMODPROG CHOWNPROG CMPPROG CPPROG MKDIRPROG MVPROG RMPROG STRIPPROG " while test $# -ne 0; do case $1 in -c) ;; -C) copy_on_change=true;; -d) dir_arg=true;; -g) chgrpcmd="$chgrpprog $2" shift;; --help) echo "$usage"; exit $?;; -m) mode=$2 case $mode in *' '* | *' '* | *' '* | *'*'* | *'?'* | *'['*) echo "$0: invalid mode: $mode" >&2 exit 1;; esac shift;; -o) chowncmd="$chownprog $2" shift;; -s) stripcmd=$stripprog;; -t) dst_arg=$2 shift;; -T) no_target_directory=true;; --version) echo "$0 $scriptversion"; exit $?;; --) shift break;; -*) echo "$0: invalid option: $1" >&2 exit 1;; *) break;; esac shift done if test $# -ne 0 && test -z "$dir_arg$dst_arg"; then # When -d is used, all remaining arguments are directories to create. # When -t is used, the destination is already specified. # Otherwise, the last argument is the destination. Remove it from $@. for arg do if test -n "$dst_arg"; then # $@ is not empty: it contains at least $arg. set fnord "$@" "$dst_arg" shift # fnord fi shift # arg dst_arg=$arg done fi if test $# -eq 0; then if test -z "$dir_arg"; then echo "$0: no input file specified." >&2 exit 1 fi # It's OK to call `install-sh -d' without argument. # This can happen when creating conditional directories. exit 0 fi if test -z "$dir_arg"; then trap '(exit $?); exit' 1 2 13 15 # Set umask so as not to create temps with too-generous modes. # However, 'strip' requires both read and write access to temps. case $mode in # Optimize common cases. *644) cp_umask=133;; *755) cp_umask=22;; *[0-7]) if test -z "$stripcmd"; then u_plus_rw= else u_plus_rw='% 200' fi cp_umask=`expr '(' 777 - $mode % 1000 ')' $u_plus_rw`;; *) if test -z "$stripcmd"; then u_plus_rw= else u_plus_rw=,u+rw fi cp_umask=$mode$u_plus_rw;; esac fi for src do # Protect names starting with `-'. case $src in -*) src=./$src;; esac if test -n "$dir_arg"; then dst=$src dstdir=$dst test -d "$dstdir" dstdir_status=$? else # Waiting for this to be detected by the "$cpprog $src $dsttmp" command # might cause directories to be created, which would be especially bad # if $src (and thus $dsttmp) contains '*'. if test ! -f "$src" && test ! -d "$src"; then echo "$0: $src does not exist." >&2 exit 1 fi if test -z "$dst_arg"; then echo "$0: no destination specified." >&2 exit 1 fi dst=$dst_arg # Protect names starting with `-'. case $dst in -*) dst=./$dst;; esac # If destination is a directory, append the input filename; won't work # if double slashes aren't ignored. if test -d "$dst"; then if test -n "$no_target_directory"; then echo "$0: $dst_arg: Is a directory" >&2 exit 1 fi dstdir=$dst dst=$dstdir/`basename "$src"` dstdir_status=0 else # Prefer dirname, but fall back on a substitute if dirname fails. dstdir=` (dirname "$dst") 2>/dev/null || expr X"$dst" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ X"$dst" : 'X\(//\)[^/]' \| \ X"$dst" : 'X\(//\)$' \| \ X"$dst" : 'X\(/\)' \| . 2>/dev/null || echo X"$dst" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/ q } /^X\(\/\/\)[^/].*/{ s//\1/ q } /^X\(\/\/\)$/{ s//\1/ q } /^X\(\/\).*/{ s//\1/ q } s/.*/./; q' ` test -d "$dstdir" dstdir_status=$? fi fi obsolete_mkdir_used=false if test $dstdir_status != 0; then case $posix_mkdir in '') # Create intermediate dirs using mode 755 as modified by the umask. # This is like FreeBSD 'install' as of 1997-10-28. umask=`umask` case $stripcmd.$umask in # Optimize common cases. *[2367][2367]) mkdir_umask=$umask;; .*0[02][02] | .[02][02] | .[02]) mkdir_umask=22;; *[0-7]) mkdir_umask=`expr $umask + 22 \ - $umask % 100 % 40 + $umask % 20 \ - $umask % 10 % 4 + $umask % 2 `;; *) mkdir_umask=$umask,go-w;; esac # With -d, create the new directory with the user-specified mode. # Otherwise, rely on $mkdir_umask. if test -n "$dir_arg"; then mkdir_mode=-m$mode else mkdir_mode= fi posix_mkdir=false case $umask in *[123567][0-7][0-7]) # POSIX mkdir -p sets u+wx bits regardless of umask, which # is incompatible with FreeBSD 'install' when (umask & 300) != 0. ;; *) tmpdir=${TMPDIR-/tmp}/ins$RANDOM-$$ trap 'ret=$?; rmdir "$tmpdir/d" "$tmpdir" 2>/dev/null; exit $ret' 0 if (umask $mkdir_umask && exec $mkdirprog $mkdir_mode -p -- "$tmpdir/d") >/dev/null 2>&1 then if test -z "$dir_arg" || { # Check for POSIX incompatibilities with -m. # HP-UX 11.23 and IRIX 6.5 mkdir -m -p sets group- or # other-writeable bit of parent directory when it shouldn't. # FreeBSD 6.1 mkdir -m -p sets mode of existing directory. ls_ld_tmpdir=`ls -ld "$tmpdir"` case $ls_ld_tmpdir in d????-?r-*) different_mode=700;; d????-?--*) different_mode=755;; *) false;; esac && $mkdirprog -m$different_mode -p -- "$tmpdir" && { ls_ld_tmpdir_1=`ls -ld "$tmpdir"` test "$ls_ld_tmpdir" = "$ls_ld_tmpdir_1" } } then posix_mkdir=: fi rmdir "$tmpdir/d" "$tmpdir" else # Remove any dirs left behind by ancient mkdir implementations. rmdir ./$mkdir_mode ./-p ./-- 2>/dev/null fi trap '' 0;; esac;; esac if $posix_mkdir && ( umask $mkdir_umask && $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir" ) then : else # The umask is ridiculous, or mkdir does not conform to POSIX, # or it failed possibly due to a race condition. Create the # directory the slow way, step by step, checking for races as we go. case $dstdir in /*) prefix='/';; -*) prefix='./';; *) prefix='';; esac eval "$initialize_posix_glob" oIFS=$IFS IFS=/ $posix_glob set -f set fnord $dstdir shift $posix_glob set +f IFS=$oIFS prefixes= for d do test -z "$d" && continue prefix=$prefix$d if test -d "$prefix"; then prefixes= else if $posix_mkdir; then (umask=$mkdir_umask && $doit_exec $mkdirprog $mkdir_mode -p -- "$dstdir") && break # Don't fail if two instances are running concurrently. test -d "$prefix" || exit 1 else case $prefix in *\'*) qprefix=`echo "$prefix" | sed "s/'/'\\\\\\\\''/g"`;; *) qprefix=$prefix;; esac prefixes="$prefixes '$qprefix'" fi fi prefix=$prefix/ done if test -n "$prefixes"; then # Don't fail if two instances are running concurrently. (umask $mkdir_umask && eval "\$doit_exec \$mkdirprog $prefixes") || test -d "$dstdir" || exit 1 obsolete_mkdir_used=true fi fi fi if test -n "$dir_arg"; then { test -z "$chowncmd" || $doit $chowncmd "$dst"; } && { test -z "$chgrpcmd" || $doit $chgrpcmd "$dst"; } && { test "$obsolete_mkdir_used$chowncmd$chgrpcmd" = false || test -z "$chmodcmd" || $doit $chmodcmd $mode "$dst"; } || exit 1 else # Make a couple of temp file names in the proper directory. dsttmp=$dstdir/_inst.$$_ rmtmp=$dstdir/_rm.$$_ # Trap to clean up those temp files at exit. trap 'ret=$?; rm -f "$dsttmp" "$rmtmp" && exit $ret' 0 # Copy the file name to the temp name. (umask $cp_umask && $doit_exec $cpprog "$src" "$dsttmp") && # and set any options; do chmod last to preserve setuid bits. # # If any of these fail, we abort the whole thing. If we want to # ignore errors from any of these, just make sure not to ignore # errors from the above "$doit $cpprog $src $dsttmp" command. # { test -z "$chowncmd" || $doit $chowncmd "$dsttmp"; } && { test -z "$chgrpcmd" || $doit $chgrpcmd "$dsttmp"; } && { test -z "$stripcmd" || $doit $stripcmd "$dsttmp"; } && { test -z "$chmodcmd" || $doit $chmodcmd $mode "$dsttmp"; } && # If -C, don't bother to copy if it wouldn't change the file. if $copy_on_change && old=`LC_ALL=C ls -dlL "$dst" 2>/dev/null` && new=`LC_ALL=C ls -dlL "$dsttmp" 2>/dev/null` && eval "$initialize_posix_glob" && $posix_glob set -f && set X $old && old=:$2:$4:$5:$6 && set X $new && new=:$2:$4:$5:$6 && $posix_glob set +f && test "$old" = "$new" && $cmpprog "$dst" "$dsttmp" >/dev/null 2>&1 then rm -f "$dsttmp" else # Rename the file to the real destination. $doit $mvcmd -f "$dsttmp" "$dst" 2>/dev/null || # The rename failed, perhaps because mv can't rename something else # to itself, or perhaps because mv is so ancient that it does not # support -f. { # Now remove or move aside any old file at destination location. # We try this two ways since rm can't unlink itself on some # systems and the destination file might be busy for other # reasons. In this case, the final cleanup might fail but the new # file should still install successfully. { test ! -f "$dst" || $doit $rmcmd -f "$dst" 2>/dev/null || { $doit $mvcmd -f "$dst" "$rmtmp" 2>/dev/null && { $doit $rmcmd -f "$rmtmp" 2>/dev/null; :; } } || { echo "$0: cannot unlink or rename $dst" >&2 (exit 1); exit 1 } } && # Now rename the file to the real destination. $doit $mvcmd "$dsttmp" "$dst" } fi || exit 1 trap '' 0 fi done # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "scriptversion=" # time-stamp-format: "%:y-%02m-%02d.%02H" # time-stamp-end: "$" # End: crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/config.guess0000644000175000017500000012753411610313111024414 0ustar andresandres#! /bin/sh # Attempt to guess a canonical system name. # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, # 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 # Free Software Foundation, Inc. timestamp='2008-01-23' # This file is free software; you can redistribute it and/or modify it # under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, MA # 02110-1301, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # Originally written by Per Bothner . # Please send patches to . Submit a context # diff and a properly formatted ChangeLog entry. # # This script attempts to guess a canonical system name similar to # config.sub. If it succeeds, it prints the system name on stdout, and # exits with 0. Otherwise, it exits with 1. # # The plan is that this can be called by configure scripts if you # don't specify an explicit build system type. me=`echo "$0" | sed -e 's,.*/,,'` usage="\ Usage: $0 [OPTION] Output the configuration name of the system \`$me' is run on. Operation modes: -h, --help print this help, then exit -t, --time-stamp print date of last modification, then exit -v, --version print version number, then exit Report bugs and patches to ." version="\ GNU config.guess ($timestamp) Originally written by Per Bothner. Copyright (C) 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. This is free software; see the source for copying conditions. There is NO warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE." help=" Try \`$me --help' for more information." # Parse command line while test $# -gt 0 ; do case $1 in --time-stamp | --time* | -t ) echo "$timestamp" ; exit ;; --version | -v ) echo "$version" ; exit ;; --help | --h* | -h ) echo "$usage"; exit ;; -- ) # Stop option processing shift; break ;; - ) # Use stdin as input. break ;; -* ) echo "$me: invalid option $1$help" >&2 exit 1 ;; * ) break ;; esac done if test $# != 0; then echo "$me: too many arguments$help" >&2 exit 1 fi trap 'exit 1' 1 2 15 # CC_FOR_BUILD -- compiler used by this script. Note that the use of a # compiler to aid in system detection is discouraged as it requires # temporary files to be created and, as you can see below, it is a # headache to deal with in a portable fashion. # Historically, `CC_FOR_BUILD' used to be named `HOST_CC'. We still # use `HOST_CC' if defined, but it is deprecated. # Portable tmp directory creation inspired by the Autoconf team. set_cc_for_build=' trap "exitcode=\$?; (rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null) && exit \$exitcode" 0 ; trap "rm -f \$tmpfiles 2>/dev/null; rmdir \$tmp 2>/dev/null; exit 1" 1 2 13 15 ; : ${TMPDIR=/tmp} ; { tmp=`(umask 077 && mktemp -d "$TMPDIR/cgXXXXXX") 2>/dev/null` && test -n "$tmp" && test -d "$tmp" ; } || { test -n "$RANDOM" && tmp=$TMPDIR/cg$$-$RANDOM && (umask 077 && mkdir $tmp) ; } || { tmp=$TMPDIR/cg-$$ && (umask 077 && mkdir $tmp) && echo "Warning: creating insecure temp directory" >&2 ; } || { echo "$me: cannot create a temporary directory in $TMPDIR" >&2 ; exit 1 ; } ; dummy=$tmp/dummy ; tmpfiles="$dummy.c $dummy.o $dummy.rel $dummy" ; case $CC_FOR_BUILD,$HOST_CC,$CC in ,,) echo "int x;" > $dummy.c ; for c in cc gcc c89 c99 ; do if ($c -c -o $dummy.o $dummy.c) >/dev/null 2>&1 ; then CC_FOR_BUILD="$c"; break ; fi ; done ; if test x"$CC_FOR_BUILD" = x ; then CC_FOR_BUILD=no_compiler_found ; fi ;; ,,*) CC_FOR_BUILD=$CC ;; ,*,*) CC_FOR_BUILD=$HOST_CC ;; esac ; set_cc_for_build= ;' # This is needed to find uname on a Pyramid OSx when run in the BSD universe. # (ghazi@noc.rutgers.edu 1994-08-24) if (test -f /.attbin/uname) >/dev/null 2>&1 ; then PATH=$PATH:/.attbin ; export PATH fi UNAME_MACHINE=`(uname -m) 2>/dev/null` || UNAME_MACHINE=unknown UNAME_RELEASE=`(uname -r) 2>/dev/null` || UNAME_RELEASE=unknown UNAME_SYSTEM=`(uname -s) 2>/dev/null` || UNAME_SYSTEM=unknown UNAME_VERSION=`(uname -v) 2>/dev/null` || UNAME_VERSION=unknown # Note: order is significant - the case branches are not exclusive. case "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" in *:NetBSD:*:*) # NetBSD (nbsd) targets should (where applicable) match one or # more of the tupples: *-*-netbsdelf*, *-*-netbsdaout*, # *-*-netbsdecoff* and *-*-netbsd*. For targets that recently # switched to ELF, *-*-netbsd* would select the old # object file format. This provides both forward # compatibility and a consistent mechanism for selecting the # object file format. # # Note: NetBSD doesn't particularly care about the vendor # portion of the name. We always set it to "unknown". sysctl="sysctl -n hw.machine_arch" UNAME_MACHINE_ARCH=`(/sbin/$sysctl 2>/dev/null || \ /usr/sbin/$sysctl 2>/dev/null || echo unknown)` case "${UNAME_MACHINE_ARCH}" in armeb) machine=armeb-unknown ;; arm*) machine=arm-unknown ;; sh3el) machine=shl-unknown ;; sh3eb) machine=sh-unknown ;; sh5el) machine=sh5le-unknown ;; *) machine=${UNAME_MACHINE_ARCH}-unknown ;; esac # The Operating System including object format, if it has switched # to ELF recently, or will in the future. case "${UNAME_MACHINE_ARCH}" in arm*|i386|m68k|ns32k|sh3*|sparc|vax) eval $set_cc_for_build if echo __ELF__ | $CC_FOR_BUILD -E - 2>/dev/null \ | grep __ELF__ >/dev/null then # Once all utilities can be ECOFF (netbsdecoff) or a.out (netbsdaout). # Return netbsd for either. FIX? os=netbsd else os=netbsdelf fi ;; *) os=netbsd ;; esac # The OS release # Debian GNU/NetBSD machines have a different userland, and # thus, need a distinct triplet. However, they do not need # kernel version information, so it can be replaced with a # suitable tag, in the style of linux-gnu. case "${UNAME_VERSION}" in Debian*) release='-gnu' ;; *) release=`echo ${UNAME_RELEASE}|sed -e 's/[-_].*/\./'` ;; esac # Since CPU_TYPE-MANUFACTURER-KERNEL-OPERATING_SYSTEM: # contains redundant information, the shorter form: # CPU_TYPE-MANUFACTURER-OPERATING_SYSTEM is used. echo "${machine}-${os}${release}" exit ;; *:OpenBSD:*:*) UNAME_MACHINE_ARCH=`arch | sed 's/OpenBSD.//'` echo ${UNAME_MACHINE_ARCH}-unknown-openbsd${UNAME_RELEASE} exit ;; *:ekkoBSD:*:*) echo ${UNAME_MACHINE}-unknown-ekkobsd${UNAME_RELEASE} exit ;; *:SolidBSD:*:*) echo ${UNAME_MACHINE}-unknown-solidbsd${UNAME_RELEASE} exit ;; macppc:MirBSD:*:*) echo powerpc-unknown-mirbsd${UNAME_RELEASE} exit ;; *:MirBSD:*:*) echo ${UNAME_MACHINE}-unknown-mirbsd${UNAME_RELEASE} exit ;; alpha:OSF1:*:*) case $UNAME_RELEASE in *4.0) UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $3}'` ;; *5.*) UNAME_RELEASE=`/usr/sbin/sizer -v | awk '{print $4}'` ;; esac # According to Compaq, /usr/sbin/psrinfo has been available on # OSF/1 and Tru64 systems produced since 1995. I hope that # covers most systems running today. This code pipes the CPU # types through head -n 1, so we only detect the type of CPU 0. ALPHA_CPU_TYPE=`/usr/sbin/psrinfo -v | sed -n -e 's/^ The alpha \(.*\) processor.*$/\1/p' | head -n 1` case "$ALPHA_CPU_TYPE" in "EV4 (21064)") UNAME_MACHINE="alpha" ;; "EV4.5 (21064)") UNAME_MACHINE="alpha" ;; "LCA4 (21066/21068)") UNAME_MACHINE="alpha" ;; "EV5 (21164)") UNAME_MACHINE="alphaev5" ;; "EV5.6 (21164A)") UNAME_MACHINE="alphaev56" ;; "EV5.6 (21164PC)") UNAME_MACHINE="alphapca56" ;; "EV5.7 (21164PC)") UNAME_MACHINE="alphapca57" ;; "EV6 (21264)") UNAME_MACHINE="alphaev6" ;; "EV6.7 (21264A)") UNAME_MACHINE="alphaev67" ;; "EV6.8CB (21264C)") UNAME_MACHINE="alphaev68" ;; "EV6.8AL (21264B)") UNAME_MACHINE="alphaev68" ;; "EV6.8CX (21264D)") UNAME_MACHINE="alphaev68" ;; "EV6.9A (21264/EV69A)") UNAME_MACHINE="alphaev69" ;; "EV7 (21364)") UNAME_MACHINE="alphaev7" ;; "EV7.9 (21364A)") UNAME_MACHINE="alphaev79" ;; esac # A Pn.n version is a patched version. # A Vn.n version is a released version. # A Tn.n version is a released field test version. # A Xn.n version is an unreleased experimental baselevel. # 1.2 uses "1.2" for uname -r. echo ${UNAME_MACHINE}-dec-osf`echo ${UNAME_RELEASE} | sed -e 's/^[PVTX]//' | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` exit ;; Alpha\ *:Windows_NT*:*) # How do we know it's Interix rather than the generic POSIX subsystem? # Should we change UNAME_MACHINE based on the output of uname instead # of the specific Alpha model? echo alpha-pc-interix exit ;; 21064:Windows_NT:50:3) echo alpha-dec-winnt3.5 exit ;; Amiga*:UNIX_System_V:4.0:*) echo m68k-unknown-sysv4 exit ;; *:[Aa]miga[Oo][Ss]:*:*) echo ${UNAME_MACHINE}-unknown-amigaos exit ;; *:[Mm]orph[Oo][Ss]:*:*) echo ${UNAME_MACHINE}-unknown-morphos exit ;; *:OS/390:*:*) echo i370-ibm-openedition exit ;; *:z/VM:*:*) echo s390-ibm-zvmoe exit ;; *:OS400:*:*) echo powerpc-ibm-os400 exit ;; arm:RISC*:1.[012]*:*|arm:riscix:1.[012]*:*) echo arm-acorn-riscix${UNAME_RELEASE} exit ;; arm:riscos:*:*|arm:RISCOS:*:*) echo arm-unknown-riscos exit ;; SR2?01:HI-UX/MPP:*:* | SR8000:HI-UX/MPP:*:*) echo hppa1.1-hitachi-hiuxmpp exit ;; Pyramid*:OSx*:*:* | MIS*:OSx*:*:* | MIS*:SMP_DC-OSx*:*:*) # akee@wpdis03.wpafb.af.mil (Earle F. Ake) contributed MIS and NILE. if test "`(/bin/universe) 2>/dev/null`" = att ; then echo pyramid-pyramid-sysv3 else echo pyramid-pyramid-bsd fi exit ;; NILE*:*:*:dcosx) echo pyramid-pyramid-svr4 exit ;; DRS?6000:unix:4.0:6*) echo sparc-icl-nx6 exit ;; DRS?6000:UNIX_SV:4.2*:7* | DRS?6000:isis:4.2*:7*) case `/usr/bin/uname -p` in sparc) echo sparc-icl-nx7; exit ;; esac ;; sun4H:SunOS:5.*:*) echo sparc-hal-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit ;; sun4*:SunOS:5.*:* | tadpole*:SunOS:5.*:*) echo sparc-sun-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit ;; i86pc:SunOS:5.*:* | i86xen:SunOS:5.*:*) echo i386-pc-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit ;; sun4*:SunOS:6*:*) # According to config.sub, this is the proper way to canonicalize # SunOS6. Hard to guess exactly what SunOS6 will be like, but # it's likely to be more like Solaris than SunOS4. echo sparc-sun-solaris3`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit ;; sun4*:SunOS:*:*) case "`/usr/bin/arch -k`" in Series*|S4*) UNAME_RELEASE=`uname -v` ;; esac # Japanese Language versions have a version number like `4.1.3-JL'. echo sparc-sun-sunos`echo ${UNAME_RELEASE}|sed -e 's/-/_/'` exit ;; sun3*:SunOS:*:*) echo m68k-sun-sunos${UNAME_RELEASE} exit ;; sun*:*:4.2BSD:*) UNAME_RELEASE=`(sed 1q /etc/motd | awk '{print substr($5,1,3)}') 2>/dev/null` test "x${UNAME_RELEASE}" = "x" && UNAME_RELEASE=3 case "`/bin/arch`" in sun3) echo m68k-sun-sunos${UNAME_RELEASE} ;; sun4) echo sparc-sun-sunos${UNAME_RELEASE} ;; esac exit ;; aushp:SunOS:*:*) echo sparc-auspex-sunos${UNAME_RELEASE} exit ;; # The situation for MiNT is a little confusing. The machine name # can be virtually everything (everything which is not # "atarist" or "atariste" at least should have a processor # > m68000). The system name ranges from "MiNT" over "FreeMiNT" # to the lowercase version "mint" (or "freemint"). Finally # the system name "TOS" denotes a system which is actually not # MiNT. But MiNT is downward compatible to TOS, so this should # be no problem. atarist[e]:*MiNT:*:* | atarist[e]:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit ;; atari*:*MiNT:*:* | atari*:*mint:*:* | atarist[e]:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit ;; *falcon*:*MiNT:*:* | *falcon*:*mint:*:* | *falcon*:*TOS:*:*) echo m68k-atari-mint${UNAME_RELEASE} exit ;; milan*:*MiNT:*:* | milan*:*mint:*:* | *milan*:*TOS:*:*) echo m68k-milan-mint${UNAME_RELEASE} exit ;; hades*:*MiNT:*:* | hades*:*mint:*:* | *hades*:*TOS:*:*) echo m68k-hades-mint${UNAME_RELEASE} exit ;; *:*MiNT:*:* | *:*mint:*:* | *:*TOS:*:*) echo m68k-unknown-mint${UNAME_RELEASE} exit ;; m68k:machten:*:*) echo m68k-apple-machten${UNAME_RELEASE} exit ;; powerpc:machten:*:*) echo powerpc-apple-machten${UNAME_RELEASE} exit ;; RISC*:Mach:*:*) echo mips-dec-mach_bsd4.3 exit ;; RISC*:ULTRIX:*:*) echo mips-dec-ultrix${UNAME_RELEASE} exit ;; VAX*:ULTRIX*:*:*) echo vax-dec-ultrix${UNAME_RELEASE} exit ;; 2020:CLIX:*:* | 2430:CLIX:*:*) echo clipper-intergraph-clix${UNAME_RELEASE} exit ;; mips:*:*:UMIPS | mips:*:*:RISCos) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #ifdef __cplusplus #include /* for printf() prototype */ int main (int argc, char *argv[]) { #else int main (argc, argv) int argc; char *argv[]; { #endif #if defined (host_mips) && defined (MIPSEB) #if defined (SYSTYPE_SYSV) printf ("mips-mips-riscos%ssysv\n", argv[1]); exit (0); #endif #if defined (SYSTYPE_SVR4) printf ("mips-mips-riscos%ssvr4\n", argv[1]); exit (0); #endif #if defined (SYSTYPE_BSD43) || defined(SYSTYPE_BSD) printf ("mips-mips-riscos%sbsd\n", argv[1]); exit (0); #endif #endif exit (-1); } EOF $CC_FOR_BUILD -o $dummy $dummy.c && dummyarg=`echo "${UNAME_RELEASE}" | sed -n 's/\([0-9]*\).*/\1/p'` && SYSTEM_NAME=`$dummy $dummyarg` && { echo "$SYSTEM_NAME"; exit; } echo mips-mips-riscos${UNAME_RELEASE} exit ;; Motorola:PowerMAX_OS:*:*) echo powerpc-motorola-powermax exit ;; Motorola:*:4.3:PL8-*) echo powerpc-harris-powermax exit ;; Night_Hawk:*:*:PowerMAX_OS | Synergy:PowerMAX_OS:*:*) echo powerpc-harris-powermax exit ;; Night_Hawk:Power_UNIX:*:*) echo powerpc-harris-powerunix exit ;; m88k:CX/UX:7*:*) echo m88k-harris-cxux7 exit ;; m88k:*:4*:R4*) echo m88k-motorola-sysv4 exit ;; m88k:*:3*:R3*) echo m88k-motorola-sysv3 exit ;; AViiON:dgux:*:*) # DG/UX returns AViiON for all architectures UNAME_PROCESSOR=`/usr/bin/uname -p` if [ $UNAME_PROCESSOR = mc88100 ] || [ $UNAME_PROCESSOR = mc88110 ] then if [ ${TARGET_BINARY_INTERFACE}x = m88kdguxelfx ] || \ [ ${TARGET_BINARY_INTERFACE}x = x ] then echo m88k-dg-dgux${UNAME_RELEASE} else echo m88k-dg-dguxbcs${UNAME_RELEASE} fi else echo i586-dg-dgux${UNAME_RELEASE} fi exit ;; M88*:DolphinOS:*:*) # DolphinOS (SVR3) echo m88k-dolphin-sysv3 exit ;; M88*:*:R3*:*) # Delta 88k system running SVR3 echo m88k-motorola-sysv3 exit ;; XD88*:*:*:*) # Tektronix XD88 system running UTekV (SVR3) echo m88k-tektronix-sysv3 exit ;; Tek43[0-9][0-9]:UTek:*:*) # Tektronix 4300 system running UTek (BSD) echo m68k-tektronix-bsd exit ;; *:IRIX*:*:*) echo mips-sgi-irix`echo ${UNAME_RELEASE}|sed -e 's/-/_/g'` exit ;; ????????:AIX?:[12].1:2) # AIX 2.2.1 or AIX 2.1.1 is RT/PC AIX. echo romp-ibm-aix # uname -m gives an 8 hex-code CPU id exit ;; # Note that: echo "'`uname -s`'" gives 'AIX ' i*86:AIX:*:*) echo i386-ibm-aix exit ;; ia64:AIX:*:*) if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` else IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${UNAME_MACHINE}-ibm-aix${IBM_REV} exit ;; *:AIX:2:3) if grep bos325 /usr/include/stdio.h >/dev/null 2>&1; then eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include main() { if (!__power_pc()) exit(1); puts("powerpc-ibm-aix3.2.5"); exit(0); } EOF if $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` then echo "$SYSTEM_NAME" else echo rs6000-ibm-aix3.2.5 fi elif grep bos324 /usr/include/stdio.h >/dev/null 2>&1; then echo rs6000-ibm-aix3.2.4 else echo rs6000-ibm-aix3.2 fi exit ;; *:AIX:*:[456]) IBM_CPU_ID=`/usr/sbin/lsdev -C -c processor -S available | sed 1q | awk '{ print $1 }'` if /usr/sbin/lsattr -El ${IBM_CPU_ID} | grep ' POWER' >/dev/null 2>&1; then IBM_ARCH=rs6000 else IBM_ARCH=powerpc fi if [ -x /usr/bin/oslevel ] ; then IBM_REV=`/usr/bin/oslevel` else IBM_REV=${UNAME_VERSION}.${UNAME_RELEASE} fi echo ${IBM_ARCH}-ibm-aix${IBM_REV} exit ;; *:AIX:*:*) echo rs6000-ibm-aix exit ;; ibmrt:4.4BSD:*|romp-ibm:BSD:*) echo romp-ibm-bsd4.4 exit ;; ibmrt:*BSD:*|romp-ibm:BSD:*) # covers RT/PC BSD and echo romp-ibm-bsd${UNAME_RELEASE} # 4.3 with uname added to exit ;; # report: romp-ibm BSD 4.3 *:BOSX:*:*) echo rs6000-bull-bosx exit ;; DPX/2?00:B.O.S.:*:*) echo m68k-bull-sysv3 exit ;; 9000/[34]??:4.3bsd:1.*:*) echo m68k-hp-bsd exit ;; hp300:4.4BSD:*:* | 9000/[34]??:4.3bsd:2.*:*) echo m68k-hp-bsd4.4 exit ;; 9000/[34678]??:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` case "${UNAME_MACHINE}" in 9000/31? ) HP_ARCH=m68000 ;; 9000/[34]?? ) HP_ARCH=m68k ;; 9000/[678][0-9][0-9]) if [ -x /usr/bin/getconf ]; then sc_cpu_version=`/usr/bin/getconf SC_CPU_VERSION 2>/dev/null` sc_kernel_bits=`/usr/bin/getconf SC_KERNEL_BITS 2>/dev/null` case "${sc_cpu_version}" in 523) HP_ARCH="hppa1.0" ;; # CPU_PA_RISC1_0 528) HP_ARCH="hppa1.1" ;; # CPU_PA_RISC1_1 532) # CPU_PA_RISC2_0 case "${sc_kernel_bits}" in 32) HP_ARCH="hppa2.0n" ;; 64) HP_ARCH="hppa2.0w" ;; '') HP_ARCH="hppa2.0" ;; # HP-UX 10.20 esac ;; esac fi if [ "${HP_ARCH}" = "" ]; then eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #define _HPUX_SOURCE #include #include int main () { #if defined(_SC_KERNEL_BITS) long bits = sysconf(_SC_KERNEL_BITS); #endif long cpu = sysconf (_SC_CPU_VERSION); switch (cpu) { case CPU_PA_RISC1_0: puts ("hppa1.0"); break; case CPU_PA_RISC1_1: puts ("hppa1.1"); break; case CPU_PA_RISC2_0: #if defined(_SC_KERNEL_BITS) switch (bits) { case 64: puts ("hppa2.0w"); break; case 32: puts ("hppa2.0n"); break; default: puts ("hppa2.0"); break; } break; #else /* !defined(_SC_KERNEL_BITS) */ puts ("hppa2.0"); break; #endif default: puts ("hppa1.0"); break; } exit (0); } EOF (CCOPTS= $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null) && HP_ARCH=`$dummy` test -z "$HP_ARCH" && HP_ARCH=hppa fi ;; esac if [ ${HP_ARCH} = "hppa2.0w" ] then eval $set_cc_for_build # hppa2.0w-hp-hpux* has a 64-bit kernel and a compiler generating # 32-bit code. hppa64-hp-hpux* has the same kernel and a compiler # generating 64-bit code. GNU and HP use different nomenclature: # # $ CC_FOR_BUILD=cc ./config.guess # => hppa2.0w-hp-hpux11.23 # $ CC_FOR_BUILD="cc +DA2.0w" ./config.guess # => hppa64-hp-hpux11.23 if echo __LP64__ | (CCOPTS= $CC_FOR_BUILD -E - 2>/dev/null) | grep __LP64__ >/dev/null then HP_ARCH="hppa2.0w" else HP_ARCH="hppa64" fi fi echo ${HP_ARCH}-hp-hpux${HPUX_REV} exit ;; ia64:HP-UX:*:*) HPUX_REV=`echo ${UNAME_RELEASE}|sed -e 's/[^.]*.[0B]*//'` echo ia64-hp-hpux${HPUX_REV} exit ;; 3050*:HI-UX:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include int main () { long cpu = sysconf (_SC_CPU_VERSION); /* The order matters, because CPU_IS_HP_MC68K erroneously returns true for CPU_PA_RISC1_0. CPU_IS_PA_RISC returns correct results, however. */ if (CPU_IS_PA_RISC (cpu)) { switch (cpu) { case CPU_PA_RISC1_0: puts ("hppa1.0-hitachi-hiuxwe2"); break; case CPU_PA_RISC1_1: puts ("hppa1.1-hitachi-hiuxwe2"); break; case CPU_PA_RISC2_0: puts ("hppa2.0-hitachi-hiuxwe2"); break; default: puts ("hppa-hitachi-hiuxwe2"); break; } } else if (CPU_IS_HP_MC68K (cpu)) puts ("m68k-hitachi-hiuxwe2"); else puts ("unknown-hitachi-hiuxwe2"); exit (0); } EOF $CC_FOR_BUILD -o $dummy $dummy.c && SYSTEM_NAME=`$dummy` && { echo "$SYSTEM_NAME"; exit; } echo unknown-hitachi-hiuxwe2 exit ;; 9000/7??:4.3bsd:*:* | 9000/8?[79]:4.3bsd:*:* ) echo hppa1.1-hp-bsd exit ;; 9000/8??:4.3bsd:*:*) echo hppa1.0-hp-bsd exit ;; *9??*:MPE/iX:*:* | *3000*:MPE/iX:*:*) echo hppa1.0-hp-mpeix exit ;; hp7??:OSF1:*:* | hp8?[79]:OSF1:*:* ) echo hppa1.1-hp-osf exit ;; hp8??:OSF1:*:*) echo hppa1.0-hp-osf exit ;; i*86:OSF1:*:*) if [ -x /usr/sbin/sysversion ] ; then echo ${UNAME_MACHINE}-unknown-osf1mk else echo ${UNAME_MACHINE}-unknown-osf1 fi exit ;; parisc*:Lites*:*:*) echo hppa1.1-hp-lites exit ;; C1*:ConvexOS:*:* | convex:ConvexOS:C1*:*) echo c1-convex-bsd exit ;; C2*:ConvexOS:*:* | convex:ConvexOS:C2*:*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi exit ;; C34*:ConvexOS:*:* | convex:ConvexOS:C34*:*) echo c34-convex-bsd exit ;; C38*:ConvexOS:*:* | convex:ConvexOS:C38*:*) echo c38-convex-bsd exit ;; C4*:ConvexOS:*:* | convex:ConvexOS:C4*:*) echo c4-convex-bsd exit ;; CRAY*Y-MP:*:*:*) echo ymp-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; CRAY*[A-Z]90:*:*:*) echo ${UNAME_MACHINE}-cray-unicos${UNAME_RELEASE} \ | sed -e 's/CRAY.*\([A-Z]90\)/\1/' \ -e y/ABCDEFGHIJKLMNOPQRSTUVWXYZ/abcdefghijklmnopqrstuvwxyz/ \ -e 's/\.[^.]*$/.X/' exit ;; CRAY*TS:*:*:*) echo t90-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; CRAY*T3E:*:*:*) echo alphaev5-cray-unicosmk${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; CRAY*SV1:*:*:*) echo sv1-cray-unicos${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; *:UNICOS/mp:*:*) echo craynv-cray-unicosmp${UNAME_RELEASE} | sed -e 's/\.[^.]*$/.X/' exit ;; F30[01]:UNIX_System_V:*:* | F700:UNIX_System_V:*:*) FUJITSU_PROC=`uname -m | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz'` FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` FUJITSU_REL=`echo ${UNAME_RELEASE} | sed -e 's/ /_/'` echo "${FUJITSU_PROC}-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" exit ;; 5000:UNIX_System_V:4.*:*) FUJITSU_SYS=`uname -p | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/\///'` FUJITSU_REL=`echo ${UNAME_RELEASE} | tr 'ABCDEFGHIJKLMNOPQRSTUVWXYZ' 'abcdefghijklmnopqrstuvwxyz' | sed -e 's/ /_/'` echo "sparc-fujitsu-${FUJITSU_SYS}${FUJITSU_REL}" exit ;; i*86:BSD/386:*:* | i*86:BSD/OS:*:* | *:Ascend\ Embedded/OS:*:*) echo ${UNAME_MACHINE}-pc-bsdi${UNAME_RELEASE} exit ;; sparc*:BSD/OS:*:*) echo sparc-unknown-bsdi${UNAME_RELEASE} exit ;; *:BSD/OS:*:*) echo ${UNAME_MACHINE}-unknown-bsdi${UNAME_RELEASE} exit ;; *:FreeBSD:*:*) case ${UNAME_MACHINE} in pc98) echo i386-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; amd64) echo x86_64-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; *) echo ${UNAME_MACHINE}-unknown-freebsd`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` ;; esac exit ;; i*:CYGWIN*:*) echo ${UNAME_MACHINE}-pc-cygwin exit ;; *:MINGW*:*) echo ${UNAME_MACHINE}-pc-mingw32 exit ;; i*:windows32*:*) # uname -m includes "-pc" on this system. echo ${UNAME_MACHINE}-mingw32 exit ;; i*:PW*:*) echo ${UNAME_MACHINE}-pc-pw32 exit ;; *:Interix*:[3456]*) case ${UNAME_MACHINE} in x86) echo i586-pc-interix${UNAME_RELEASE} exit ;; EM64T | authenticamd) echo x86_64-unknown-interix${UNAME_RELEASE} exit ;; IA64) echo ia64-unknown-interix${UNAME_RELEASE} exit ;; esac ;; [345]86:Windows_95:* | [345]86:Windows_98:* | [345]86:Windows_NT:*) echo i${UNAME_MACHINE}-pc-mks exit ;; i*:Windows_NT*:* | Pentium*:Windows_NT*:*) # How do we know it's Interix rather than the generic POSIX subsystem? # It also conflicts with pre-2.0 versions of AT&T UWIN. Should we # UNAME_MACHINE based on the output of uname instead of i386? echo i586-pc-interix exit ;; i*:UWIN*:*) echo ${UNAME_MACHINE}-pc-uwin exit ;; amd64:CYGWIN*:*:* | x86_64:CYGWIN*:*:*) echo x86_64-unknown-cygwin exit ;; p*:CYGWIN*:*) echo powerpcle-unknown-cygwin exit ;; prep*:SunOS:5.*:*) echo powerpcle-unknown-solaris2`echo ${UNAME_RELEASE}|sed -e 's/[^.]*//'` exit ;; *:GNU:*:*) # the GNU system echo `echo ${UNAME_MACHINE}|sed -e 's,[-/].*$,,'`-unknown-gnu`echo ${UNAME_RELEASE}|sed -e 's,/.*$,,'` exit ;; *:GNU/*:*:*) # other systems with GNU libc and userland echo ${UNAME_MACHINE}-unknown-`echo ${UNAME_SYSTEM} | sed 's,^[^/]*/,,' | tr '[A-Z]' '[a-z]'``echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'`-gnu exit ;; i*86:Minix:*:*) echo ${UNAME_MACHINE}-pc-minix exit ;; arm*:Linux:*:*) eval $set_cc_for_build if echo __ARM_EABI__ | $CC_FOR_BUILD -E - 2>/dev/null \ | grep -q __ARM_EABI__ then echo ${UNAME_MACHINE}-unknown-linux-gnu else echo ${UNAME_MACHINE}-unknown-linux-gnueabi fi exit ;; avr32*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; cris:Linux:*:*) echo cris-axis-linux-gnu exit ;; crisv32:Linux:*:*) echo crisv32-axis-linux-gnu exit ;; frv:Linux:*:*) echo frv-unknown-linux-gnu exit ;; ia64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; m32r*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; m68*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; mips:Linux:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #undef CPU #undef mips #undef mipsel #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) CPU=mipsel #else #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) CPU=mips #else CPU= #endif #endif EOF eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' /^CPU/{ s: ::g p }'`" test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } ;; mips64:Linux:*:*) eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #undef CPU #undef mips64 #undef mips64el #if defined(__MIPSEL__) || defined(__MIPSEL) || defined(_MIPSEL) || defined(MIPSEL) CPU=mips64el #else #if defined(__MIPSEB__) || defined(__MIPSEB) || defined(_MIPSEB) || defined(MIPSEB) CPU=mips64 #else CPU= #endif #endif EOF eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' /^CPU/{ s: ::g p }'`" test x"${CPU}" != x && { echo "${CPU}-unknown-linux-gnu"; exit; } ;; or32:Linux:*:*) echo or32-unknown-linux-gnu exit ;; ppc:Linux:*:*) echo powerpc-unknown-linux-gnu exit ;; ppc64:Linux:*:*) echo powerpc64-unknown-linux-gnu exit ;; alpha:Linux:*:*) case `sed -n '/^cpu model/s/^.*: \(.*\)/\1/p' < /proc/cpuinfo` in EV5) UNAME_MACHINE=alphaev5 ;; EV56) UNAME_MACHINE=alphaev56 ;; PCA56) UNAME_MACHINE=alphapca56 ;; PCA57) UNAME_MACHINE=alphapca56 ;; EV6) UNAME_MACHINE=alphaev6 ;; EV67) UNAME_MACHINE=alphaev67 ;; EV68*) UNAME_MACHINE=alphaev68 ;; esac objdump --private-headers /bin/sh | grep ld.so.1 >/dev/null if test "$?" = 0 ; then LIBC="libc1" ; else LIBC="" ; fi echo ${UNAME_MACHINE}-unknown-linux-gnu${LIBC} exit ;; parisc:Linux:*:* | hppa:Linux:*:*) # Look for CPU level case `grep '^cpu[^a-z]*:' /proc/cpuinfo 2>/dev/null | cut -d' ' -f2` in PA7*) echo hppa1.1-unknown-linux-gnu ;; PA8*) echo hppa2.0-unknown-linux-gnu ;; *) echo hppa-unknown-linux-gnu ;; esac exit ;; parisc64:Linux:*:* | hppa64:Linux:*:*) echo hppa64-unknown-linux-gnu exit ;; s390:Linux:*:* | s390x:Linux:*:*) echo ${UNAME_MACHINE}-ibm-linux exit ;; sh64*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; sh*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; sparc:Linux:*:* | sparc64:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; vax:Linux:*:*) echo ${UNAME_MACHINE}-dec-linux-gnu exit ;; x86_64:Linux:*:*) echo x86_64-unknown-linux-gnu exit ;; xtensa*:Linux:*:*) echo ${UNAME_MACHINE}-unknown-linux-gnu exit ;; i*86:Linux:*:*) # The BFD linker knows what the default object file format is, so # first see if it will tell us. cd to the root directory to prevent # problems with other programs or directories called `ld' in the path. # Set LC_ALL=C to ensure ld outputs messages in English. ld_supported_targets=`cd /; LC_ALL=C ld --help 2>&1 \ | sed -ne '/supported targets:/!d s/[ ][ ]*/ /g s/.*supported targets: *// s/ .*// p'` case "$ld_supported_targets" in elf32-i386) TENTATIVE="${UNAME_MACHINE}-pc-linux-gnu" ;; a.out-i386-linux) echo "${UNAME_MACHINE}-pc-linux-gnuaout" exit ;; coff-i386) echo "${UNAME_MACHINE}-pc-linux-gnucoff" exit ;; "") # Either a pre-BFD a.out linker (linux-gnuoldld) or # one that does not give us useful --help. echo "${UNAME_MACHINE}-pc-linux-gnuoldld" exit ;; esac # Determine whether the default compiler is a.out or elf eval $set_cc_for_build sed 's/^ //' << EOF >$dummy.c #include #ifdef __ELF__ # ifdef __GLIBC__ # if __GLIBC__ >= 2 LIBC=gnu # else LIBC=gnulibc1 # endif # else LIBC=gnulibc1 # endif #else #if defined(__INTEL_COMPILER) || defined(__PGI) || defined(__SUNPRO_C) || defined(__SUNPRO_CC) LIBC=gnu #else LIBC=gnuaout #endif #endif #ifdef __dietlibc__ LIBC=dietlibc #endif EOF eval "`$CC_FOR_BUILD -E $dummy.c 2>/dev/null | sed -n ' /^LIBC/{ s: ::g p }'`" test x"${LIBC}" != x && { echo "${UNAME_MACHINE}-pc-linux-${LIBC}" exit } test x"${TENTATIVE}" != x && { echo "${TENTATIVE}"; exit; } ;; i*86:DYNIX/ptx:4*:*) # ptx 4.0 does uname -s correctly, with DYNIX/ptx in there. # earlier versions are messed up and put the nodename in both # sysname and nodename. echo i386-sequent-sysv4 exit ;; i*86:UNIX_SV:4.2MP:2.*) # Unixware is an offshoot of SVR4, but it has its own version # number series starting with 2... # I am not positive that other SVR4 systems won't match this, # I just have to hope. -- rms. # Use sysv4.2uw... so that sysv4* matches it. echo ${UNAME_MACHINE}-pc-sysv4.2uw${UNAME_VERSION} exit ;; i*86:OS/2:*:*) # If we were able to find `uname', then EMX Unix compatibility # is probably installed. echo ${UNAME_MACHINE}-pc-os2-emx exit ;; i*86:XTS-300:*:STOP) echo ${UNAME_MACHINE}-unknown-stop exit ;; i*86:atheos:*:*) echo ${UNAME_MACHINE}-unknown-atheos exit ;; i*86:syllable:*:*) echo ${UNAME_MACHINE}-pc-syllable exit ;; i*86:LynxOS:2.*:* | i*86:LynxOS:3.[01]*:* | i*86:LynxOS:4.0*:*) echo i386-unknown-lynxos${UNAME_RELEASE} exit ;; i*86:*DOS:*:*) echo ${UNAME_MACHINE}-pc-msdosdjgpp exit ;; i*86:*:4.*:* | i*86:SYSTEM_V:4.*:*) UNAME_REL=`echo ${UNAME_RELEASE} | sed 's/\/MP$//'` if grep Novell /usr/include/link.h >/dev/null 2>/dev/null; then echo ${UNAME_MACHINE}-univel-sysv${UNAME_REL} else echo ${UNAME_MACHINE}-pc-sysv${UNAME_REL} fi exit ;; i*86:*:5:[678]*) # UnixWare 7.x, OpenUNIX and OpenServer 6. case `/bin/uname -X | grep "^Machine"` in *486*) UNAME_MACHINE=i486 ;; *Pentium) UNAME_MACHINE=i586 ;; *Pent*|*Celeron) UNAME_MACHINE=i686 ;; esac echo ${UNAME_MACHINE}-unknown-sysv${UNAME_RELEASE}${UNAME_SYSTEM}${UNAME_VERSION} exit ;; i*86:*:3.2:*) if test -f /usr/options/cb.name; then UNAME_REL=`sed -n 's/.*Version //p' /dev/null >/dev/null ; then UNAME_REL=`(/bin/uname -X|grep Release|sed -e 's/.*= //')` (/bin/uname -X|grep i80486 >/dev/null) && UNAME_MACHINE=i486 (/bin/uname -X|grep '^Machine.*Pentium' >/dev/null) \ && UNAME_MACHINE=i586 (/bin/uname -X|grep '^Machine.*Pent *II' >/dev/null) \ && UNAME_MACHINE=i686 (/bin/uname -X|grep '^Machine.*Pentium Pro' >/dev/null) \ && UNAME_MACHINE=i686 echo ${UNAME_MACHINE}-pc-sco$UNAME_REL else echo ${UNAME_MACHINE}-pc-sysv32 fi exit ;; pc:*:*:*) # Left here for compatibility: # uname -m prints for DJGPP always 'pc', but it prints nothing about # the processor, so we play safe by assuming i386. echo i386-pc-msdosdjgpp exit ;; Intel:Mach:3*:*) echo i386-pc-mach3 exit ;; paragon:*:*:*) echo i860-intel-osf1 exit ;; i860:*:4.*:*) # i860-SVR4 if grep Stardent /usr/include/sys/uadmin.h >/dev/null 2>&1 ; then echo i860-stardent-sysv${UNAME_RELEASE} # Stardent Vistra i860-SVR4 else # Add other i860-SVR4 vendors below as they are discovered. echo i860-unknown-sysv${UNAME_RELEASE} # Unknown i860-SVR4 fi exit ;; mini*:CTIX:SYS*5:*) # "miniframe" echo m68010-convergent-sysv exit ;; mc68k:UNIX:SYSTEM5:3.51m) echo m68k-convergent-sysv exit ;; M680?0:D-NIX:5.3:*) echo m68k-diab-dnix exit ;; M68*:*:R3V[5678]*:*) test -r /sysV68 && { echo 'm68k-motorola-sysv'; exit; } ;; 3[345]??:*:4.0:3.0 | 3[34]??A:*:4.0:3.0 | 3[34]??,*:*:4.0:3.0 | 3[34]??/*:*:4.0:3.0 | 4400:*:4.0:3.0 | 4850:*:4.0:3.0 | SKA40:*:4.0:3.0 | SDS2:*:4.0:3.0 | SHG2:*:4.0:3.0 | S7501*:*:4.0:3.0) OS_REL='' test -r /etc/.relid \ && OS_REL=.`sed -n 's/[^ ]* [^ ]* \([0-9][0-9]\).*/\1/p' < /etc/.relid` /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ && { echo i486-ncr-sysv4.3${OS_REL}; exit; } /bin/uname -p 2>/dev/null | /bin/grep entium >/dev/null \ && { echo i586-ncr-sysv4.3${OS_REL}; exit; } ;; 3[34]??:*:4.0:* | 3[34]??,*:*:4.0:*) /bin/uname -p 2>/dev/null | grep 86 >/dev/null \ && { echo i486-ncr-sysv4; exit; } ;; m68*:LynxOS:2.*:* | m68*:LynxOS:3.0*:*) echo m68k-unknown-lynxos${UNAME_RELEASE} exit ;; mc68030:UNIX_System_V:4.*:*) echo m68k-atari-sysv4 exit ;; TSUNAMI:LynxOS:2.*:*) echo sparc-unknown-lynxos${UNAME_RELEASE} exit ;; rs6000:LynxOS:2.*:*) echo rs6000-unknown-lynxos${UNAME_RELEASE} exit ;; PowerPC:LynxOS:2.*:* | PowerPC:LynxOS:3.[01]*:* | PowerPC:LynxOS:4.0*:*) echo powerpc-unknown-lynxos${UNAME_RELEASE} exit ;; SM[BE]S:UNIX_SV:*:*) echo mips-dde-sysv${UNAME_RELEASE} exit ;; RM*:ReliantUNIX-*:*:*) echo mips-sni-sysv4 exit ;; RM*:SINIX-*:*:*) echo mips-sni-sysv4 exit ;; *:SINIX-*:*:*) if uname -p 2>/dev/null >/dev/null ; then UNAME_MACHINE=`(uname -p) 2>/dev/null` echo ${UNAME_MACHINE}-sni-sysv4 else echo ns32k-sni-sysv fi exit ;; PENTIUM:*:4.0*:*) # Unisys `ClearPath HMP IX 4000' SVR4/MP effort # says echo i586-unisys-sysv4 exit ;; *:UNIX_System_V:4*:FTX*) # From Gerald Hewes . # How about differentiating between stratus architectures? -djm echo hppa1.1-stratus-sysv4 exit ;; *:*:*:FTX*) # From seanf@swdc.stratus.com. echo i860-stratus-sysv4 exit ;; i*86:VOS:*:*) # From Paul.Green@stratus.com. echo ${UNAME_MACHINE}-stratus-vos exit ;; *:VOS:*:*) # From Paul.Green@stratus.com. echo hppa1.1-stratus-vos exit ;; mc68*:A/UX:*:*) echo m68k-apple-aux${UNAME_RELEASE} exit ;; news*:NEWS-OS:6*:*) echo mips-sony-newsos6 exit ;; R[34]000:*System_V*:*:* | R4000:UNIX_SYSV:*:* | R*000:UNIX_SV:*:*) if [ -d /usr/nec ]; then echo mips-nec-sysv${UNAME_RELEASE} else echo mips-unknown-sysv${UNAME_RELEASE} fi exit ;; BeBox:BeOS:*:*) # BeOS running on hardware made by Be, PPC only. echo powerpc-be-beos exit ;; BeMac:BeOS:*:*) # BeOS running on Mac or Mac clone, PPC only. echo powerpc-apple-beos exit ;; BePC:BeOS:*:*) # BeOS running on Intel PC compatible. echo i586-pc-beos exit ;; SX-4:SUPER-UX:*:*) echo sx4-nec-superux${UNAME_RELEASE} exit ;; SX-5:SUPER-UX:*:*) echo sx5-nec-superux${UNAME_RELEASE} exit ;; SX-6:SUPER-UX:*:*) echo sx6-nec-superux${UNAME_RELEASE} exit ;; SX-7:SUPER-UX:*:*) echo sx7-nec-superux${UNAME_RELEASE} exit ;; SX-8:SUPER-UX:*:*) echo sx8-nec-superux${UNAME_RELEASE} exit ;; SX-8R:SUPER-UX:*:*) echo sx8r-nec-superux${UNAME_RELEASE} exit ;; Power*:Rhapsody:*:*) echo powerpc-apple-rhapsody${UNAME_RELEASE} exit ;; *:Rhapsody:*:*) echo ${UNAME_MACHINE}-apple-rhapsody${UNAME_RELEASE} exit ;; *:Darwin:*:*) UNAME_PROCESSOR=`uname -p` || UNAME_PROCESSOR=unknown case $UNAME_PROCESSOR in unknown) UNAME_PROCESSOR=powerpc ;; esac echo ${UNAME_PROCESSOR}-apple-darwin${UNAME_RELEASE} exit ;; *:procnto*:*:* | *:QNX:[0123456789]*:*) UNAME_PROCESSOR=`uname -p` if test "$UNAME_PROCESSOR" = "x86"; then UNAME_PROCESSOR=i386 UNAME_MACHINE=pc fi echo ${UNAME_PROCESSOR}-${UNAME_MACHINE}-nto-qnx${UNAME_RELEASE} exit ;; *:QNX:*:4*) echo i386-pc-qnx exit ;; NSE-?:NONSTOP_KERNEL:*:*) echo nse-tandem-nsk${UNAME_RELEASE} exit ;; NSR-?:NONSTOP_KERNEL:*:*) echo nsr-tandem-nsk${UNAME_RELEASE} exit ;; *:NonStop-UX:*:*) echo mips-compaq-nonstopux exit ;; BS2000:POSIX*:*:*) echo bs2000-siemens-sysv exit ;; DS/*:UNIX_System_V:*:*) echo ${UNAME_MACHINE}-${UNAME_SYSTEM}-${UNAME_RELEASE} exit ;; *:Plan9:*:*) # "uname -m" is not consistent, so use $cputype instead. 386 # is converted to i386 for consistency with other x86 # operating systems. if test "$cputype" = "386"; then UNAME_MACHINE=i386 else UNAME_MACHINE="$cputype" fi echo ${UNAME_MACHINE}-unknown-plan9 exit ;; *:TOPS-10:*:*) echo pdp10-unknown-tops10 exit ;; *:TENEX:*:*) echo pdp10-unknown-tenex exit ;; KS10:TOPS-20:*:* | KL10:TOPS-20:*:* | TYPE4:TOPS-20:*:*) echo pdp10-dec-tops20 exit ;; XKL-1:TOPS-20:*:* | TYPE5:TOPS-20:*:*) echo pdp10-xkl-tops20 exit ;; *:TOPS-20:*:*) echo pdp10-unknown-tops20 exit ;; *:ITS:*:*) echo pdp10-unknown-its exit ;; SEI:*:*:SEIUX) echo mips-sei-seiux${UNAME_RELEASE} exit ;; *:DragonFly:*:*) echo ${UNAME_MACHINE}-unknown-dragonfly`echo ${UNAME_RELEASE}|sed -e 's/[-(].*//'` exit ;; *:*VMS:*:*) UNAME_MACHINE=`(uname -p) 2>/dev/null` case "${UNAME_MACHINE}" in A*) echo alpha-dec-vms ; exit ;; I*) echo ia64-dec-vms ; exit ;; V*) echo vax-dec-vms ; exit ;; esac ;; *:XENIX:*:SysV) echo i386-pc-xenix exit ;; i*86:skyos:*:*) echo ${UNAME_MACHINE}-pc-skyos`echo ${UNAME_RELEASE}` | sed -e 's/ .*$//' exit ;; i*86:rdos:*:*) echo ${UNAME_MACHINE}-pc-rdos exit ;; esac #echo '(No uname command or uname output not recognized.)' 1>&2 #echo "${UNAME_MACHINE}:${UNAME_SYSTEM}:${UNAME_RELEASE}:${UNAME_VERSION}" 1>&2 eval $set_cc_for_build cat >$dummy.c < # include #endif main () { #if defined (sony) #if defined (MIPSEB) /* BFD wants "bsd" instead of "newsos". Perhaps BFD should be changed, I don't know.... */ printf ("mips-sony-bsd\n"); exit (0); #else #include printf ("m68k-sony-newsos%s\n", #ifdef NEWSOS4 "4" #else "" #endif ); exit (0); #endif #endif #if defined (__arm) && defined (__acorn) && defined (__unix) printf ("arm-acorn-riscix\n"); exit (0); #endif #if defined (hp300) && !defined (hpux) printf ("m68k-hp-bsd\n"); exit (0); #endif #if defined (NeXT) #if !defined (__ARCHITECTURE__) #define __ARCHITECTURE__ "m68k" #endif int version; version=`(hostinfo | sed -n 's/.*NeXT Mach \([0-9]*\).*/\1/p') 2>/dev/null`; if (version < 4) printf ("%s-next-nextstep%d\n", __ARCHITECTURE__, version); else printf ("%s-next-openstep%d\n", __ARCHITECTURE__, version); exit (0); #endif #if defined (MULTIMAX) || defined (n16) #if defined (UMAXV) printf ("ns32k-encore-sysv\n"); exit (0); #else #if defined (CMU) printf ("ns32k-encore-mach\n"); exit (0); #else printf ("ns32k-encore-bsd\n"); exit (0); #endif #endif #endif #if defined (__386BSD__) printf ("i386-pc-bsd\n"); exit (0); #endif #if defined (sequent) #if defined (i386) printf ("i386-sequent-dynix\n"); exit (0); #endif #if defined (ns32000) printf ("ns32k-sequent-dynix\n"); exit (0); #endif #endif #if defined (_SEQUENT_) struct utsname un; uname(&un); if (strncmp(un.version, "V2", 2) == 0) { printf ("i386-sequent-ptx2\n"); exit (0); } if (strncmp(un.version, "V1", 2) == 0) { /* XXX is V1 correct? */ printf ("i386-sequent-ptx1\n"); exit (0); } printf ("i386-sequent-ptx\n"); exit (0); #endif #if defined (vax) # if !defined (ultrix) # include # if defined (BSD) # if BSD == 43 printf ("vax-dec-bsd4.3\n"); exit (0); # else # if BSD == 199006 printf ("vax-dec-bsd4.3reno\n"); exit (0); # else printf ("vax-dec-bsd\n"); exit (0); # endif # endif # else printf ("vax-dec-bsd\n"); exit (0); # endif # else printf ("vax-dec-ultrix\n"); exit (0); # endif #endif #if defined (alliant) && defined (i860) printf ("i860-alliant-bsd\n"); exit (0); #endif exit (1); } EOF $CC_FOR_BUILD -o $dummy $dummy.c 2>/dev/null && SYSTEM_NAME=`$dummy` && { echo "$SYSTEM_NAME"; exit; } # Apollos put the system type in the environment. test -d /usr/apollo && { echo ${ISP}-apollo-${SYSTYPE}; exit; } # Convex versions that predate uname can use getsysinfo(1) if [ -x /usr/convex/getsysinfo ] then case `getsysinfo -f cpu_type` in c1*) echo c1-convex-bsd exit ;; c2*) if getsysinfo -f scalar_acc then echo c32-convex-bsd else echo c2-convex-bsd fi exit ;; c34*) echo c34-convex-bsd exit ;; c38*) echo c38-convex-bsd exit ;; c4*) echo c4-convex-bsd exit ;; esac fi cat >&2 < in order to provide the needed information to handle your system. config.guess timestamp = $timestamp uname -m = `(uname -m) 2>/dev/null || echo unknown` uname -r = `(uname -r) 2>/dev/null || echo unknown` uname -s = `(uname -s) 2>/dev/null || echo unknown` uname -v = `(uname -v) 2>/dev/null || echo unknown` /usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null` /bin/uname -X = `(/bin/uname -X) 2>/dev/null` hostinfo = `(hostinfo) 2>/dev/null` /bin/universe = `(/bin/universe) 2>/dev/null` /usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null` /bin/arch = `(/bin/arch) 2>/dev/null` /usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null` /usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null` UNAME_MACHINE = ${UNAME_MACHINE} UNAME_RELEASE = ${UNAME_RELEASE} UNAME_SYSTEM = ${UNAME_SYSTEM} UNAME_VERSION = ${UNAME_VERSION} EOF exit 1 # Local variables: # eval: (add-hook 'write-file-hooks 'time-stamp) # time-stamp-start: "timestamp='" # time-stamp-format: "%:y-%02m-%02d" # time-stamp-end: "'" # End: crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/Makefile.in0000644000175000017500000005542711610313116024152 0ustar andresandres# Makefile.in generated by automake 1.11.1 from Makefile.am. # @configure_input@ # Copyright (C) 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, # 2003, 2004, 2005, 2006, 2007, 2008, 2009 Free Software Foundation, # Inc. # This Makefile.in is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. @SET_MAKE@ VPATH = @srcdir@ pkgdatadir = $(datadir)/@PACKAGE@ pkgincludedir = $(includedir)/@PACKAGE@ pkglibdir = $(libdir)/@PACKAGE@ pkglibexecdir = $(libexecdir)/@PACKAGE@ am__cd = CDPATH="$${ZSH_VERSION+.}$(PATH_SEPARATOR)" && cd install_sh_DATA = $(install_sh) -c -m 644 install_sh_PROGRAM = $(install_sh) -c install_sh_SCRIPT = $(install_sh) -c INSTALL_HEADER = $(INSTALL_DATA) transform = $(program_transform_name) NORMAL_INSTALL = : PRE_INSTALL = : POST_INSTALL = : NORMAL_UNINSTALL = : PRE_UNINSTALL = : POST_UNINSTALL = : build_triplet = @build@ host_triplet = @host@ subdir = . DIST_COMMON = README $(am__configure_deps) $(srcdir)/Makefile.am \ $(srcdir)/Makefile.in $(srcdir)/config.h.in \ $(top_srcdir)/configure AUTHORS COPYING ChangeLog INSTALL NEWS \ config.guess config.sub depcomp install-sh ltmain.sh missing ACLOCAL_M4 = $(top_srcdir)/aclocal.m4 am__aclocal_m4_deps = $(top_srcdir)/m4/as-compiler-flag.m4 \ $(top_srcdir)/m4/as-version.m4 $(top_srcdir)/configure.ac am__configure_deps = $(am__aclocal_m4_deps) $(CONFIGURE_DEPENDENCIES) \ $(ACLOCAL_M4) am__CONFIG_DISTCLEAN_FILES = config.status config.cache config.log \ configure.lineno config.status.lineno mkinstalldirs = $(install_sh) -d CONFIG_HEADER = config.h CONFIG_CLEAN_FILES = CONFIG_CLEAN_VPATH_FILES = SOURCES = DIST_SOURCES = RECURSIVE_TARGETS = all-recursive check-recursive dvi-recursive \ html-recursive info-recursive install-data-recursive \ install-dvi-recursive install-exec-recursive \ install-html-recursive install-info-recursive \ install-pdf-recursive install-ps-recursive install-recursive \ installcheck-recursive installdirs-recursive pdf-recursive \ ps-recursive uninstall-recursive RECURSIVE_CLEAN_TARGETS = mostlyclean-recursive clean-recursive \ distclean-recursive maintainer-clean-recursive AM_RECURSIVE_TARGETS = $(RECURSIVE_TARGETS:-recursive=) \ $(RECURSIVE_CLEAN_TARGETS:-recursive=) tags TAGS ctags CTAGS \ distdir dist dist-all distcheck ETAGS = etags CTAGS = ctags DIST_SUBDIRS = $(SUBDIRS) DISTFILES = $(DIST_COMMON) $(DIST_SOURCES) $(TEXINFOS) $(EXTRA_DIST) distdir = $(PACKAGE)-$(VERSION) top_distdir = $(distdir) am__remove_distdir = \ { test ! -d "$(distdir)" \ || { find "$(distdir)" -type d ! -perm -200 -exec chmod u+w {} ';' \ && rm -fr "$(distdir)"; }; } am__relativize = \ dir0=`pwd`; \ sed_first='s,^\([^/]*\)/.*$$,\1,'; \ sed_rest='s,^[^/]*/*,,'; \ sed_last='s,^.*/\([^/]*\)$$,\1,'; \ sed_butlast='s,/*[^/]*$$,,'; \ while test -n "$$dir1"; do \ first=`echo "$$dir1" | sed -e "$$sed_first"`; \ if test "$$first" != "."; then \ if test "$$first" = ".."; then \ dir2=`echo "$$dir0" | sed -e "$$sed_last"`/"$$dir2"; \ dir0=`echo "$$dir0" | sed -e "$$sed_butlast"`; \ else \ first2=`echo "$$dir2" | sed -e "$$sed_first"`; \ if test "$$first2" = "$$first"; then \ dir2=`echo "$$dir2" | sed -e "$$sed_rest"`; \ else \ dir2="../$$dir2"; \ fi; \ dir0="$$dir0"/"$$first"; \ fi; \ fi; \ dir1=`echo "$$dir1" | sed -e "$$sed_rest"`; \ done; \ reldir="$$dir2" DIST_ARCHIVES = $(distdir).tar.gz GZIP_ENV = --best distuninstallcheck_listfiles = find . -type f -print distcleancheck_listfiles = find . -type f -print ACLOCAL = @ACLOCAL@ ACLOCAL_AMFLAGS = @ACLOCAL_AMFLAGS@ AMTAR = @AMTAR@ AR = @AR@ AUTOCONF = @AUTOCONF@ AUTOHEADER = @AUTOHEADER@ AUTOMAKE = @AUTOMAKE@ AWK = @AWK@ CC = @CC@ CCDEPMODE = @CCDEPMODE@ CFLAGS = @CFLAGS@ CPP = @CPP@ CPPFLAGS = @CPPFLAGS@ CYGPATH_W = @CYGPATH_W@ DEFS = @DEFS@ DEPDIR = @DEPDIR@ DLLTOOL = @DLLTOOL@ DSYMUTIL = @DSYMUTIL@ DUMPBIN = @DUMPBIN@ ECHO_C = @ECHO_C@ ECHO_N = @ECHO_N@ ECHO_T = @ECHO_T@ EGREP = @EGREP@ EXEEXT = @EXEEXT@ FGREP = @FGREP@ GREP = @GREP@ GSTCTRL_CFLAGS = @GSTCTRL_CFLAGS@ GSTCTRL_LIBS = @GSTCTRL_LIBS@ GSTPB_BASE_CFLAGS = @GSTPB_BASE_CFLAGS@ GSTPB_BASE_LIBS = @GSTPB_BASE_LIBS@ GST_BASE_CFLAGS = @GST_BASE_CFLAGS@ GST_BASE_LIBS = @GST_BASE_LIBS@ GST_CFLAGS = @GST_CFLAGS@ GST_LIBS = @GST_LIBS@ GST_MAJORMINOR = @GST_MAJORMINOR@ GST_PLUGIN_LDFLAGS = @GST_PLUGIN_LDFLAGS@ GST_PLUGIN_VERSION = @GST_PLUGIN_VERSION@ GST_PLUGIN_VERSION_MAJOR = @GST_PLUGIN_VERSION_MAJOR@ GST_PLUGIN_VERSION_MICRO = @GST_PLUGIN_VERSION_MICRO@ GST_PLUGIN_VERSION_MINOR = @GST_PLUGIN_VERSION_MINOR@ GST_PLUGIN_VERSION_NANO = @GST_PLUGIN_VERSION_NANO@ GST_PLUGIN_VERSION_RELEASE = @GST_PLUGIN_VERSION_RELEASE@ HAVE_PKGCONFIG = @HAVE_PKGCONFIG@ INSTALL = @INSTALL@ INSTALL_DATA = @INSTALL_DATA@ INSTALL_PROGRAM = @INSTALL_PROGRAM@ INSTALL_SCRIPT = @INSTALL_SCRIPT@ INSTALL_STRIP_PROGRAM = @INSTALL_STRIP_PROGRAM@ LD = @LD@ LDFLAGS = @LDFLAGS@ LIBOBJS = @LIBOBJS@ LIBS = @LIBS@ LIBTOOL = @LIBTOOL@ LIPO = @LIPO@ LN_S = @LN_S@ LTLIBOBJS = @LTLIBOBJS@ MAINT = @MAINT@ MAKEINFO = @MAKEINFO@ MANIFEST_TOOL = @MANIFEST_TOOL@ MKDIR_P = @MKDIR_P@ NM = @NM@ NMEDIT = @NMEDIT@ OBJDUMP = @OBJDUMP@ OBJEXT = @OBJEXT@ OTOOL = @OTOOL@ OTOOL64 = @OTOOL64@ PACKAGE = @PACKAGE@ PACKAGE_BUGREPORT = @PACKAGE_BUGREPORT@ PACKAGE_NAME = @PACKAGE_NAME@ PACKAGE_STRING = @PACKAGE_STRING@ PACKAGE_TARNAME = @PACKAGE_TARNAME@ PACKAGE_URL = @PACKAGE_URL@ PACKAGE_VERSION = @PACKAGE_VERSION@ PATH_SEPARATOR = @PATH_SEPARATOR@ PKG_CONFIG = @PKG_CONFIG@ PKG_CONFIG_LIBDIR = @PKG_CONFIG_LIBDIR@ PKG_CONFIG_PATH = @PKG_CONFIG_PATH@ RANLIB = @RANLIB@ SED = @SED@ SET_MAKE = @SET_MAKE@ SHELL = @SHELL@ STRIP = @STRIP@ VERSION = @VERSION@ abs_builddir = @abs_builddir@ abs_srcdir = @abs_srcdir@ abs_top_builddir = @abs_top_builddir@ abs_top_srcdir = @abs_top_srcdir@ ac_ct_AR = @ac_ct_AR@ ac_ct_CC = @ac_ct_CC@ ac_ct_DUMPBIN = @ac_ct_DUMPBIN@ am__include = @am__include@ am__leading_dot = @am__leading_dot@ am__quote = @am__quote@ am__tar = @am__tar@ am__untar = @am__untar@ bindir = @bindir@ build = @build@ build_alias = @build_alias@ build_cpu = @build_cpu@ build_os = @build_os@ build_vendor = @build_vendor@ builddir = @builddir@ datadir = @datadir@ datarootdir = @datarootdir@ docdir = @docdir@ dvidir = @dvidir@ exec_prefix = @exec_prefix@ host = @host@ host_alias = @host_alias@ host_cpu = @host_cpu@ host_os = @host_os@ host_vendor = @host_vendor@ htmldir = @htmldir@ includedir = @includedir@ infodir = @infodir@ install_sh = @install_sh@ libdir = @libdir@ libexecdir = @libexecdir@ localedir = @localedir@ localstatedir = @localstatedir@ mandir = @mandir@ mkdir_p = @mkdir_p@ oldincludedir = @oldincludedir@ pdfdir = @pdfdir@ plugindir = @plugindir@ prefix = @prefix@ program_transform_name = @program_transform_name@ psdir = @psdir@ sbindir = @sbindir@ sharedstatedir = @sharedstatedir@ srcdir = @srcdir@ sysconfdir = @sysconfdir@ target_alias = @target_alias@ top_build_prefix = @top_build_prefix@ top_builddir = @top_builddir@ top_srcdir = @top_srcdir@ SUBDIRS = m4 src EXTRA_DIST = autogen.sh gst-autogen.sh all: config.h $(MAKE) $(AM_MAKEFLAGS) all-recursive .SUFFIXES: am--refresh: @: $(srcdir)/Makefile.in: @MAINTAINER_MODE_TRUE@ $(srcdir)/Makefile.am $(am__configure_deps) @for dep in $?; do \ case '$(am__configure_deps)' in \ *$$dep*) \ echo ' cd $(srcdir) && $(AUTOMAKE) --gnu'; \ $(am__cd) $(srcdir) && $(AUTOMAKE) --gnu \ && exit 0; \ exit 1;; \ esac; \ done; \ echo ' cd $(top_srcdir) && $(AUTOMAKE) --gnu Makefile'; \ $(am__cd) $(top_srcdir) && \ $(AUTOMAKE) --gnu Makefile .PRECIOUS: Makefile Makefile: $(srcdir)/Makefile.in $(top_builddir)/config.status @case '$?' in \ *config.status*) \ echo ' $(SHELL) ./config.status'; \ $(SHELL) ./config.status;; \ *) \ echo ' cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe)'; \ cd $(top_builddir) && $(SHELL) ./config.status $@ $(am__depfiles_maybe);; \ esac; $(top_builddir)/config.status: $(top_srcdir)/configure $(CONFIG_STATUS_DEPENDENCIES) $(SHELL) ./config.status --recheck $(top_srcdir)/configure: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) $(am__cd) $(srcdir) && $(AUTOCONF) $(ACLOCAL_M4): @MAINTAINER_MODE_TRUE@ $(am__aclocal_m4_deps) $(am__cd) $(srcdir) && $(ACLOCAL) $(ACLOCAL_AMFLAGS) $(am__aclocal_m4_deps): config.h: stamp-h1 @if test ! -f $@; then \ rm -f stamp-h1; \ $(MAKE) $(AM_MAKEFLAGS) stamp-h1; \ else :; fi stamp-h1: $(srcdir)/config.h.in $(top_builddir)/config.status @rm -f stamp-h1 cd $(top_builddir) && $(SHELL) ./config.status config.h $(srcdir)/config.h.in: @MAINTAINER_MODE_TRUE@ $(am__configure_deps) ($(am__cd) $(top_srcdir) && $(AUTOHEADER)) rm -f stamp-h1 touch $@ distclean-hdr: -rm -f config.h stamp-h1 mostlyclean-libtool: -rm -f *.lo clean-libtool: -rm -rf .libs _libs distclean-libtool: -rm -f libtool config.lt # This directory's subdirectories are mostly independent; you can cd # into them and run `make' without going through this Makefile. # To change the values of `make' variables: instead of editing Makefiles, # (1) if the variable is set in `config.status', edit `config.status' # (which will cause the Makefiles to be regenerated when you run `make'); # (2) otherwise, pass the desired values on the `make' command line. $(RECURSIVE_TARGETS): @fail= failcom='exit 1'; \ for f in x $$MAKEFLAGS; do \ case $$f in \ *=* | --[!k]*);; \ *k*) failcom='fail=yes';; \ esac; \ done; \ dot_seen=no; \ target=`echo $@ | sed s/-recursive//`; \ list='$(SUBDIRS)'; for subdir in $$list; do \ echo "Making $$target in $$subdir"; \ if test "$$subdir" = "."; then \ dot_seen=yes; \ local_target="$$target-am"; \ else \ local_target="$$target"; \ fi; \ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \ || eval $$failcom; \ done; \ if test "$$dot_seen" = "no"; then \ $(MAKE) $(AM_MAKEFLAGS) "$$target-am" || exit 1; \ fi; test -z "$$fail" $(RECURSIVE_CLEAN_TARGETS): @fail= failcom='exit 1'; \ for f in x $$MAKEFLAGS; do \ case $$f in \ *=* | --[!k]*);; \ *k*) failcom='fail=yes';; \ esac; \ done; \ dot_seen=no; \ case "$@" in \ distclean-* | maintainer-clean-*) list='$(DIST_SUBDIRS)' ;; \ *) list='$(SUBDIRS)' ;; \ esac; \ rev=''; for subdir in $$list; do \ if test "$$subdir" = "."; then :; else \ rev="$$subdir $$rev"; \ fi; \ done; \ rev="$$rev ."; \ target=`echo $@ | sed s/-recursive//`; \ for subdir in $$rev; do \ echo "Making $$target in $$subdir"; \ if test "$$subdir" = "."; then \ local_target="$$target-am"; \ else \ local_target="$$target"; \ fi; \ ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) $$local_target) \ || eval $$failcom; \ done && test -z "$$fail" tags-recursive: list='$(SUBDIRS)'; for subdir in $$list; do \ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) tags); \ done ctags-recursive: list='$(SUBDIRS)'; for subdir in $$list; do \ test "$$subdir" = . || ($(am__cd) $$subdir && $(MAKE) $(AM_MAKEFLAGS) ctags); \ done ID: $(HEADERS) $(SOURCES) $(LISP) $(TAGS_FILES) list='$(SOURCES) $(HEADERS) $(LISP) $(TAGS_FILES)'; \ unique=`for i in $$list; do \ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ done | \ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \ END { if (nonempty) { for (i in files) print i; }; }'`; \ mkid -fID $$unique tags: TAGS TAGS: tags-recursive $(HEADERS) $(SOURCES) config.h.in $(TAGS_DEPENDENCIES) \ $(TAGS_FILES) $(LISP) set x; \ here=`pwd`; \ if ($(ETAGS) --etags-include --version) >/dev/null 2>&1; then \ include_option=--etags-include; \ empty_fix=.; \ else \ include_option=--include; \ empty_fix=; \ fi; \ list='$(SUBDIRS)'; for subdir in $$list; do \ if test "$$subdir" = .; then :; else \ test ! -f $$subdir/TAGS || \ set "$$@" "$$include_option=$$here/$$subdir/TAGS"; \ fi; \ done; \ list='$(SOURCES) $(HEADERS) config.h.in $(LISP) $(TAGS_FILES)'; \ unique=`for i in $$list; do \ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ done | \ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \ END { if (nonempty) { for (i in files) print i; }; }'`; \ shift; \ if test -z "$(ETAGS_ARGS)$$*$$unique"; then :; else \ test -n "$$unique" || unique=$$empty_fix; \ if test $$# -gt 0; then \ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \ "$$@" $$unique; \ else \ $(ETAGS) $(ETAGSFLAGS) $(AM_ETAGSFLAGS) $(ETAGS_ARGS) \ $$unique; \ fi; \ fi ctags: CTAGS CTAGS: ctags-recursive $(HEADERS) $(SOURCES) config.h.in $(TAGS_DEPENDENCIES) \ $(TAGS_FILES) $(LISP) list='$(SOURCES) $(HEADERS) config.h.in $(LISP) $(TAGS_FILES)'; \ unique=`for i in $$list; do \ if test -f "$$i"; then echo $$i; else echo $(srcdir)/$$i; fi; \ done | \ $(AWK) '{ files[$$0] = 1; nonempty = 1; } \ END { if (nonempty) { for (i in files) print i; }; }'`; \ test -z "$(CTAGS_ARGS)$$unique" \ || $(CTAGS) $(CTAGSFLAGS) $(AM_CTAGSFLAGS) $(CTAGS_ARGS) \ $$unique GTAGS: here=`$(am__cd) $(top_builddir) && pwd` \ && $(am__cd) $(top_srcdir) \ && gtags -i $(GTAGS_ARGS) "$$here" distclean-tags: -rm -f TAGS ID GTAGS GRTAGS GSYMS GPATH tags distdir: $(DISTFILES) $(am__remove_distdir) test -d "$(distdir)" || mkdir "$(distdir)" @srcdirstrip=`echo "$(srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ topsrcdirstrip=`echo "$(top_srcdir)" | sed 's/[].[^$$\\*]/\\\\&/g'`; \ list='$(DISTFILES)'; \ dist_files=`for file in $$list; do echo $$file; done | \ sed -e "s|^$$srcdirstrip/||;t" \ -e "s|^$$topsrcdirstrip/|$(top_builddir)/|;t"`; \ case $$dist_files in \ */*) $(MKDIR_P) `echo "$$dist_files" | \ sed '/\//!d;s|^|$(distdir)/|;s,/[^/]*$$,,' | \ sort -u` ;; \ esac; \ for file in $$dist_files; do \ if test -f $$file || test -d $$file; then d=.; else d=$(srcdir); fi; \ if test -d $$d/$$file; then \ dir=`echo "/$$file" | sed -e 's,/[^/]*$$,,'`; \ if test -d "$(distdir)/$$file"; then \ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ fi; \ if test -d $(srcdir)/$$file && test $$d != $(srcdir); then \ cp -fpR $(srcdir)/$$file "$(distdir)$$dir" || exit 1; \ find "$(distdir)/$$file" -type d ! -perm -700 -exec chmod u+rwx {} \;; \ fi; \ cp -fpR $$d/$$file "$(distdir)$$dir" || exit 1; \ else \ test -f "$(distdir)/$$file" \ || cp -p $$d/$$file "$(distdir)/$$file" \ || exit 1; \ fi; \ done @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \ if test "$$subdir" = .; then :; else \ test -d "$(distdir)/$$subdir" \ || $(MKDIR_P) "$(distdir)/$$subdir" \ || exit 1; \ fi; \ done @list='$(DIST_SUBDIRS)'; for subdir in $$list; do \ if test "$$subdir" = .; then :; else \ dir1=$$subdir; dir2="$(distdir)/$$subdir"; \ $(am__relativize); \ new_distdir=$$reldir; \ dir1=$$subdir; dir2="$(top_distdir)"; \ $(am__relativize); \ new_top_distdir=$$reldir; \ echo " (cd $$subdir && $(MAKE) $(AM_MAKEFLAGS) top_distdir="$$new_top_distdir" distdir="$$new_distdir" \\"; \ echo " am__remove_distdir=: am__skip_length_check=: am__skip_mode_fix=: distdir)"; \ ($(am__cd) $$subdir && \ $(MAKE) $(AM_MAKEFLAGS) \ top_distdir="$$new_top_distdir" \ distdir="$$new_distdir" \ am__remove_distdir=: \ am__skip_length_check=: \ am__skip_mode_fix=: \ distdir) \ || exit 1; \ fi; \ done -test -n "$(am__skip_mode_fix)" \ || find "$(distdir)" -type d ! -perm -755 \ -exec chmod u+rwx,go+rx {} \; -o \ ! -type d ! -perm -444 -links 1 -exec chmod a+r {} \; -o \ ! -type d ! -perm -400 -exec chmod a+r {} \; -o \ ! -type d ! -perm -444 -exec $(install_sh) -c -m a+r {} {} \; \ || chmod -R a+r "$(distdir)" dist-gzip: distdir tardir=$(distdir) && $(am__tar) | GZIP=$(GZIP_ENV) gzip -c >$(distdir).tar.gz $(am__remove_distdir) dist-bzip2: distdir tardir=$(distdir) && $(am__tar) | bzip2 -9 -c >$(distdir).tar.bz2 $(am__remove_distdir) dist-lzma: distdir tardir=$(distdir) && $(am__tar) | lzma -9 -c >$(distdir).tar.lzma $(am__remove_distdir) dist-xz: distdir tardir=$(distdir) && $(am__tar) | xz -c >$(distdir).tar.xz $(am__remove_distdir) dist-tarZ: distdir tardir=$(distdir) && $(am__tar) | compress -c >$(distdir).tar.Z $(am__remove_distdir) dist-shar: distdir shar $(distdir) | GZIP=$(GZIP_ENV) gzip -c >$(distdir).shar.gz $(am__remove_distdir) dist-zip: distdir -rm -f $(distdir).zip zip -rq $(distdir).zip $(distdir) $(am__remove_distdir) dist dist-all: distdir tardir=$(distdir) && $(am__tar) | GZIP=$(GZIP_ENV) gzip -c >$(distdir).tar.gz $(am__remove_distdir) # This target untars the dist file and tries a VPATH configuration. Then # it guarantees that the distribution is self-contained by making another # tarfile. distcheck: dist case '$(DIST_ARCHIVES)' in \ *.tar.gz*) \ GZIP=$(GZIP_ENV) gzip -dc $(distdir).tar.gz | $(am__untar) ;;\ *.tar.bz2*) \ bzip2 -dc $(distdir).tar.bz2 | $(am__untar) ;;\ *.tar.lzma*) \ lzma -dc $(distdir).tar.lzma | $(am__untar) ;;\ *.tar.xz*) \ xz -dc $(distdir).tar.xz | $(am__untar) ;;\ *.tar.Z*) \ uncompress -c $(distdir).tar.Z | $(am__untar) ;;\ *.shar.gz*) \ GZIP=$(GZIP_ENV) gzip -dc $(distdir).shar.gz | unshar ;;\ *.zip*) \ unzip $(distdir).zip ;;\ esac chmod -R a-w $(distdir); chmod a+w $(distdir) mkdir $(distdir)/_build mkdir $(distdir)/_inst chmod a-w $(distdir) test -d $(distdir)/_build || exit 0; \ dc_install_base=`$(am__cd) $(distdir)/_inst && pwd | sed -e 's,^[^:\\/]:[\\/],/,'` \ && dc_destdir="$${TMPDIR-/tmp}/am-dc-$$$$/" \ && am__cwd=`pwd` \ && $(am__cd) $(distdir)/_build \ && ../configure --srcdir=.. --prefix="$$dc_install_base" \ $(DISTCHECK_CONFIGURE_FLAGS) \ && $(MAKE) $(AM_MAKEFLAGS) \ && $(MAKE) $(AM_MAKEFLAGS) dvi \ && $(MAKE) $(AM_MAKEFLAGS) check \ && $(MAKE) $(AM_MAKEFLAGS) install \ && $(MAKE) $(AM_MAKEFLAGS) installcheck \ && $(MAKE) $(AM_MAKEFLAGS) uninstall \ && $(MAKE) $(AM_MAKEFLAGS) distuninstallcheck_dir="$$dc_install_base" \ distuninstallcheck \ && chmod -R a-w "$$dc_install_base" \ && ({ \ (cd ../.. && umask 077 && mkdir "$$dc_destdir") \ && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" install \ && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" uninstall \ && $(MAKE) $(AM_MAKEFLAGS) DESTDIR="$$dc_destdir" \ distuninstallcheck_dir="$$dc_destdir" distuninstallcheck; \ } || { rm -rf "$$dc_destdir"; exit 1; }) \ && rm -rf "$$dc_destdir" \ && $(MAKE) $(AM_MAKEFLAGS) dist \ && rm -rf $(DIST_ARCHIVES) \ && $(MAKE) $(AM_MAKEFLAGS) distcleancheck \ && cd "$$am__cwd" \ || exit 1 $(am__remove_distdir) @(echo "$(distdir) archives ready for distribution: "; \ list='$(DIST_ARCHIVES)'; for i in $$list; do echo $$i; done) | \ sed -e 1h -e 1s/./=/g -e 1p -e 1x -e '$$p' -e '$$x' distuninstallcheck: @$(am__cd) '$(distuninstallcheck_dir)' \ && test `$(distuninstallcheck_listfiles) | wc -l` -le 1 \ || { echo "ERROR: files left after uninstall:" ; \ if test -n "$(DESTDIR)"; then \ echo " (check DESTDIR support)"; \ fi ; \ $(distuninstallcheck_listfiles) ; \ exit 1; } >&2 distcleancheck: distclean @if test '$(srcdir)' = . ; then \ echo "ERROR: distcleancheck can only run from a VPATH build" ; \ exit 1 ; \ fi @test `$(distcleancheck_listfiles) | wc -l` -eq 0 \ || { echo "ERROR: files left in build directory after distclean:" ; \ $(distcleancheck_listfiles) ; \ exit 1; } >&2 check-am: all-am check: check-recursive all-am: Makefile config.h installdirs: installdirs-recursive installdirs-am: install: install-recursive install-exec: install-exec-recursive install-data: install-data-recursive uninstall: uninstall-recursive install-am: all-am @$(MAKE) $(AM_MAKEFLAGS) install-exec-am install-data-am installcheck: installcheck-recursive install-strip: $(MAKE) $(AM_MAKEFLAGS) INSTALL_PROGRAM="$(INSTALL_STRIP_PROGRAM)" \ install_sh_PROGRAM="$(INSTALL_STRIP_PROGRAM)" INSTALL_STRIP_FLAG=-s \ `test -z '$(STRIP)' || \ echo "INSTALL_PROGRAM_ENV=STRIPPROG='$(STRIP)'"` install mostlyclean-generic: clean-generic: distclean-generic: -test -z "$(CONFIG_CLEAN_FILES)" || rm -f $(CONFIG_CLEAN_FILES) -test . = "$(srcdir)" || test -z "$(CONFIG_CLEAN_VPATH_FILES)" || rm -f $(CONFIG_CLEAN_VPATH_FILES) maintainer-clean-generic: @echo "This command is intended for maintainers to use" @echo "it deletes files that may require special tools to rebuild." clean: clean-recursive clean-am: clean-generic clean-libtool mostlyclean-am distclean: distclean-recursive -rm -f $(am__CONFIG_DISTCLEAN_FILES) -rm -f Makefile distclean-am: clean-am distclean-generic distclean-hdr \ distclean-libtool distclean-tags dvi: dvi-recursive dvi-am: html: html-recursive html-am: info: info-recursive info-am: install-data-am: install-dvi: install-dvi-recursive install-dvi-am: install-exec-am: install-html: install-html-recursive install-html-am: install-info: install-info-recursive install-info-am: install-man: install-pdf: install-pdf-recursive install-pdf-am: install-ps: install-ps-recursive install-ps-am: installcheck-am: maintainer-clean: maintainer-clean-recursive -rm -f $(am__CONFIG_DISTCLEAN_FILES) -rm -rf $(top_srcdir)/autom4te.cache -rm -f Makefile maintainer-clean-am: distclean-am maintainer-clean-generic mostlyclean: mostlyclean-recursive mostlyclean-am: mostlyclean-generic mostlyclean-libtool pdf: pdf-recursive pdf-am: ps: ps-recursive ps-am: uninstall-am: .MAKE: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) all \ ctags-recursive install-am install-strip tags-recursive .PHONY: $(RECURSIVE_CLEAN_TARGETS) $(RECURSIVE_TARGETS) CTAGS GTAGS \ all all-am am--refresh check check-am clean clean-generic \ clean-libtool ctags ctags-recursive dist dist-all dist-bzip2 \ dist-gzip dist-lzma dist-shar dist-tarZ dist-xz dist-zip \ distcheck distclean distclean-generic distclean-hdr \ distclean-libtool distclean-tags distcleancheck distdir \ distuninstallcheck dvi dvi-am html html-am info info-am \ install install-am install-data install-data-am install-dvi \ install-dvi-am install-exec install-exec-am install-html \ install-html-am install-info install-info-am install-man \ install-pdf install-pdf-am install-ps install-ps-am \ install-strip installcheck installcheck-am installdirs \ installdirs-am maintainer-clean maintainer-clean-generic \ mostlyclean mostlyclean-generic mostlyclean-libtool pdf pdf-am \ ps ps-am tags tags-recursive uninstall uninstall-am # Tell versions [3.59,3.63) of GNU make to not export all variables. # Otherwise a system limit (for SysV at least) may be exceeded. .NOEXPORT: crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/aclocal.m40000644000175000017500000124454711610313115023750 0ustar andresandres# generated automatically by aclocal 1.11.1 -*- Autoconf -*- # Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, # 2005, 2006, 2007, 2008, 2009 Free Software Foundation, Inc. # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # This program is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY, to the extent permitted by law; without # even the implied warranty of MERCHANTABILITY or FITNESS FOR A # PARTICULAR PURPOSE. m4_ifndef([AC_AUTOCONF_VERSION], [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl m4_if(m4_defn([AC_AUTOCONF_VERSION]), [2.68],, [m4_warning([this file was generated for autoconf 2.68. You have another version of autoconf. It may work, but is not guaranteed to. If you have problems, you may need to regenerate the build system entirely. To do so, use the procedure documented by the package, typically `autoreconf'.])]) # libtool.m4 - Configure libtool for the host system. -*-Autoconf-*- # # Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, # 2006, 2007, 2008, 2009, 2010 Free Software Foundation, # Inc. # Written by Gordon Matzigkeit, 1996 # # This file is free software; the Free Software Foundation gives # unlimited permission to copy and/or distribute it, with or without # modifications, as long as this notice is preserved. m4_define([_LT_COPYING], [dnl # Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2003, 2004, 2005, # 2006, 2007, 2008, 2009, 2010 Free Software Foundation, # Inc. # Written by Gordon Matzigkeit, 1996 # # This file is part of GNU Libtool. # # GNU Libtool is free software; you can redistribute it and/or # modify it under the terms of the GNU General Public License as # published by the Free Software Foundation; either version 2 of # the License, or (at your option) any later version. # # As a special exception to the GNU General Public License, # if you distribute this file as part of a program or library that # is built using GNU Libtool, you may include this file under the # same distribution terms that you use for the rest of that program. # # GNU Libtool is distributed in the hope that it will be useful, # but WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # # You should have received a copy of the GNU General Public License # along with GNU Libtool; see the file COPYING. If not, a copy # can be downloaded from http://www.gnu.org/licenses/gpl.html, or # obtained by writing to the Free Software Foundation, Inc., # 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. ]) # serial 57 LT_INIT # LT_PREREQ(VERSION) # ------------------ # Complain and exit if this libtool version is less that VERSION. m4_defun([LT_PREREQ], [m4_if(m4_version_compare(m4_defn([LT_PACKAGE_VERSION]), [$1]), -1, [m4_default([$3], [m4_fatal([Libtool version $1 or higher is required], 63)])], [$2])]) # _LT_CHECK_BUILDDIR # ------------------ # Complain if the absolute build directory name contains unusual characters m4_defun([_LT_CHECK_BUILDDIR], [case `pwd` in *\ * | *\ *) AC_MSG_WARN([Libtool does not cope well with whitespace in `pwd`]) ;; esac ]) # LT_INIT([OPTIONS]) # ------------------ AC_DEFUN([LT_INIT], [AC_PREREQ([2.58])dnl We use AC_INCLUDES_DEFAULT AC_REQUIRE([AC_CONFIG_AUX_DIR_DEFAULT])dnl AC_BEFORE([$0], [LT_LANG])dnl AC_BEFORE([$0], [LT_OUTPUT])dnl AC_BEFORE([$0], [LTDL_INIT])dnl m4_require([_LT_CHECK_BUILDDIR])dnl dnl Autoconf doesn't catch unexpanded LT_ macros by default: m4_pattern_forbid([^_?LT_[A-Z_]+$])dnl m4_pattern_allow([^(_LT_EOF|LT_DLGLOBAL|LT_DLLAZY_OR_NOW|LT_MULTI_MODULE)$])dnl dnl aclocal doesn't pull ltoptions.m4, ltsugar.m4, or ltversion.m4 dnl unless we require an AC_DEFUNed macro: AC_REQUIRE([LTOPTIONS_VERSION])dnl AC_REQUIRE([LTSUGAR_VERSION])dnl AC_REQUIRE([LTVERSION_VERSION])dnl AC_REQUIRE([LTOBSOLETE_VERSION])dnl m4_require([_LT_PROG_LTMAIN])dnl _LT_SHELL_INIT([SHELL=${CONFIG_SHELL-/bin/sh}]) dnl Parse OPTIONS _LT_SET_OPTIONS([$0], [$1]) # This can be used to rebuild libtool when needed LIBTOOL_DEPS="$ltmain" # Always use our own libtool. LIBTOOL='$(SHELL) $(top_builddir)/libtool' AC_SUBST(LIBTOOL)dnl _LT_SETUP # Only expand once: m4_define([LT_INIT]) ])# LT_INIT # Old names: AU_ALIAS([AC_PROG_LIBTOOL], [LT_INIT]) AU_ALIAS([AM_PROG_LIBTOOL], [LT_INIT]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AC_PROG_LIBTOOL], []) dnl AC_DEFUN([AM_PROG_LIBTOOL], []) # _LT_CC_BASENAME(CC) # ------------------- # Calculate cc_basename. Skip known compiler wrappers and cross-prefix. m4_defun([_LT_CC_BASENAME], [for cc_temp in $1""; do case $cc_temp in compile | *[[\\/]]compile | ccache | *[[\\/]]ccache ) ;; distcc | *[[\\/]]distcc | purify | *[[\\/]]purify ) ;; \-*) ;; *) break;; esac done cc_basename=`$ECHO "$cc_temp" | $SED "s%.*/%%; s%^$host_alias-%%"` ]) # _LT_FILEUTILS_DEFAULTS # ---------------------- # It is okay to use these file commands and assume they have been set # sensibly after `m4_require([_LT_FILEUTILS_DEFAULTS])'. m4_defun([_LT_FILEUTILS_DEFAULTS], [: ${CP="cp -f"} : ${MV="mv -f"} : ${RM="rm -f"} ])# _LT_FILEUTILS_DEFAULTS # _LT_SETUP # --------- m4_defun([_LT_SETUP], [AC_REQUIRE([AC_CANONICAL_HOST])dnl AC_REQUIRE([AC_CANONICAL_BUILD])dnl AC_REQUIRE([_LT_PREPARE_SED_QUOTE_VARS])dnl AC_REQUIRE([_LT_PROG_ECHO_BACKSLASH])dnl _LT_DECL([], [host_alias], [0], [The host system])dnl _LT_DECL([], [host], [0])dnl _LT_DECL([], [host_os], [0])dnl dnl _LT_DECL([], [build_alias], [0], [The build system])dnl _LT_DECL([], [build], [0])dnl _LT_DECL([], [build_os], [0])dnl dnl AC_REQUIRE([AC_PROG_CC])dnl AC_REQUIRE([LT_PATH_LD])dnl AC_REQUIRE([LT_PATH_NM])dnl dnl AC_REQUIRE([AC_PROG_LN_S])dnl test -z "$LN_S" && LN_S="ln -s" _LT_DECL([], [LN_S], [1], [Whether we need soft or hard links])dnl dnl AC_REQUIRE([LT_CMD_MAX_LEN])dnl _LT_DECL([objext], [ac_objext], [0], [Object file suffix (normally "o")])dnl _LT_DECL([], [exeext], [0], [Executable file suffix (normally "")])dnl dnl m4_require([_LT_FILEUTILS_DEFAULTS])dnl m4_require([_LT_CHECK_SHELL_FEATURES])dnl m4_require([_LT_PATH_CONVERSION_FUNCTIONS])dnl m4_require([_LT_CMD_RELOAD])dnl m4_require([_LT_CHECK_MAGIC_METHOD])dnl m4_require([_LT_CHECK_SHAREDLIB_FROM_LINKLIB])dnl m4_require([_LT_CMD_OLD_ARCHIVE])dnl m4_require([_LT_CMD_GLOBAL_SYMBOLS])dnl m4_require([_LT_WITH_SYSROOT])dnl _LT_CONFIG_LIBTOOL_INIT([ # See if we are running on zsh, and set the options which allow our # commands through without removal of \ escapes INIT. if test -n "\${ZSH_VERSION+set}" ; then setopt NO_GLOB_SUBST fi ]) if test -n "${ZSH_VERSION+set}" ; then setopt NO_GLOB_SUBST fi _LT_CHECK_OBJDIR m4_require([_LT_TAG_COMPILER])dnl case $host_os in aix3*) # AIX sometimes has problems with the GCC collect2 program. For some # reason, if we set the COLLECT_NAMES environment variable, the problems # vanish in a puff of smoke. if test "X${COLLECT_NAMES+set}" != Xset; then COLLECT_NAMES= export COLLECT_NAMES fi ;; esac # Global variables: ofile=libtool can_build_shared=yes # All known linkers require a `.a' archive for static linking (except MSVC, # which needs '.lib'). libext=a with_gnu_ld="$lt_cv_prog_gnu_ld" old_CC="$CC" old_CFLAGS="$CFLAGS" # Set sane defaults for various variables test -z "$CC" && CC=cc test -z "$LTCC" && LTCC=$CC test -z "$LTCFLAGS" && LTCFLAGS=$CFLAGS test -z "$LD" && LD=ld test -z "$ac_objext" && ac_objext=o _LT_CC_BASENAME([$compiler]) # Only perform the check for file, if the check method requires it test -z "$MAGIC_CMD" && MAGIC_CMD=file case $deplibs_check_method in file_magic*) if test "$file_magic_cmd" = '$MAGIC_CMD'; then _LT_PATH_MAGIC fi ;; esac # Use C for the default configuration in the libtool script LT_SUPPORTED_TAG([CC]) _LT_LANG_C_CONFIG _LT_LANG_DEFAULT_CONFIG _LT_CONFIG_COMMANDS ])# _LT_SETUP # _LT_PREPARE_SED_QUOTE_VARS # -------------------------- # Define a few sed substitution that help us do robust quoting. m4_defun([_LT_PREPARE_SED_QUOTE_VARS], [# Backslashify metacharacters that are still active within # double-quoted strings. sed_quote_subst='s/\([["`$\\]]\)/\\\1/g' # Same as above, but do not quote variable references. double_quote_subst='s/\([["`\\]]\)/\\\1/g' # Sed substitution to delay expansion of an escaped shell variable in a # double_quote_subst'ed string. delay_variable_subst='s/\\\\\\\\\\\$/\\\\\\$/g' # Sed substitution to delay expansion of an escaped single quote. delay_single_quote_subst='s/'\''/'\'\\\\\\\'\''/g' # Sed substitution to avoid accidental globbing in evaled expressions no_glob_subst='s/\*/\\\*/g' ]) # _LT_PROG_LTMAIN # --------------- # Note that this code is called both from `configure', and `config.status' # now that we use AC_CONFIG_COMMANDS to generate libtool. Notably, # `config.status' has no value for ac_aux_dir unless we are using Automake, # so we pass a copy along to make sure it has a sensible value anyway. m4_defun([_LT_PROG_LTMAIN], [m4_ifdef([AC_REQUIRE_AUX_FILE], [AC_REQUIRE_AUX_FILE([ltmain.sh])])dnl _LT_CONFIG_LIBTOOL_INIT([ac_aux_dir='$ac_aux_dir']) ltmain="$ac_aux_dir/ltmain.sh" ])# _LT_PROG_LTMAIN # So that we can recreate a full libtool script including additional # tags, we accumulate the chunks of code to send to AC_CONFIG_COMMANDS # in macros and then make a single call at the end using the `libtool' # label. # _LT_CONFIG_LIBTOOL_INIT([INIT-COMMANDS]) # ---------------------------------------- # Register INIT-COMMANDS to be passed to AC_CONFIG_COMMANDS later. m4_define([_LT_CONFIG_LIBTOOL_INIT], [m4_ifval([$1], [m4_append([_LT_OUTPUT_LIBTOOL_INIT], [$1 ])])]) # Initialize. m4_define([_LT_OUTPUT_LIBTOOL_INIT]) # _LT_CONFIG_LIBTOOL([COMMANDS]) # ------------------------------ # Register COMMANDS to be passed to AC_CONFIG_COMMANDS later. m4_define([_LT_CONFIG_LIBTOOL], [m4_ifval([$1], [m4_append([_LT_OUTPUT_LIBTOOL_COMMANDS], [$1 ])])]) # Initialize. m4_define([_LT_OUTPUT_LIBTOOL_COMMANDS]) # _LT_CONFIG_SAVE_COMMANDS([COMMANDS], [INIT_COMMANDS]) # ----------------------------------------------------- m4_defun([_LT_CONFIG_SAVE_COMMANDS], [_LT_CONFIG_LIBTOOL([$1]) _LT_CONFIG_LIBTOOL_INIT([$2]) ]) # _LT_FORMAT_COMMENT([COMMENT]) # ----------------------------- # Add leading comment marks to the start of each line, and a trailing # full-stop to the whole comment if one is not present already. m4_define([_LT_FORMAT_COMMENT], [m4_ifval([$1], [ m4_bpatsubst([m4_bpatsubst([$1], [^ *], [# ])], [['`$\]], [\\\&])]m4_bmatch([$1], [[!?.]$], [], [.]) )]) # _LT_DECL([CONFIGNAME], VARNAME, VALUE, [DESCRIPTION], [IS-TAGGED?]) # ------------------------------------------------------------------- # CONFIGNAME is the name given to the value in the libtool script. # VARNAME is the (base) name used in the configure script. # VALUE may be 0, 1 or 2 for a computed quote escaped value based on # VARNAME. Any other value will be used directly. m4_define([_LT_DECL], [lt_if_append_uniq([lt_decl_varnames], [$2], [, ], [lt_dict_add_subkey([lt_decl_dict], [$2], [libtool_name], [m4_ifval([$1], [$1], [$2])]) lt_dict_add_subkey([lt_decl_dict], [$2], [value], [$3]) m4_ifval([$4], [lt_dict_add_subkey([lt_decl_dict], [$2], [description], [$4])]) lt_dict_add_subkey([lt_decl_dict], [$2], [tagged?], [m4_ifval([$5], [yes], [no])])]) ]) # _LT_TAGDECL([CONFIGNAME], VARNAME, VALUE, [DESCRIPTION]) # -------------------------------------------------------- m4_define([_LT_TAGDECL], [_LT_DECL([$1], [$2], [$3], [$4], [yes])]) # lt_decl_tag_varnames([SEPARATOR], [VARNAME1...]) # ------------------------------------------------ m4_define([lt_decl_tag_varnames], [_lt_decl_filter([tagged?], [yes], $@)]) # _lt_decl_filter(SUBKEY, VALUE, [SEPARATOR], [VARNAME1..]) # --------------------------------------------------------- m4_define([_lt_decl_filter], [m4_case([$#], [0], [m4_fatal([$0: too few arguments: $#])], [1], [m4_fatal([$0: too few arguments: $#: $1])], [2], [lt_dict_filter([lt_decl_dict], [$1], [$2], [], lt_decl_varnames)], [3], [lt_dict_filter([lt_decl_dict], [$1], [$2], [$3], lt_decl_varnames)], [lt_dict_filter([lt_decl_dict], $@)])[]dnl ]) # lt_decl_quote_varnames([SEPARATOR], [VARNAME1...]) # -------------------------------------------------- m4_define([lt_decl_quote_varnames], [_lt_decl_filter([value], [1], $@)]) # lt_decl_dquote_varnames([SEPARATOR], [VARNAME1...]) # --------------------------------------------------- m4_define([lt_decl_dquote_varnames], [_lt_decl_filter([value], [2], $@)]) # lt_decl_varnames_tagged([SEPARATOR], [VARNAME1...]) # --------------------------------------------------- m4_define([lt_decl_varnames_tagged], [m4_assert([$# <= 2])dnl _$0(m4_quote(m4_default([$1], [[, ]])), m4_ifval([$2], [[$2]], [m4_dquote(lt_decl_tag_varnames)]), m4_split(m4_normalize(m4_quote(_LT_TAGS)), [ ]))]) m4_define([_lt_decl_varnames_tagged], [m4_ifval([$3], [lt_combine([$1], [$2], [_], $3)])]) # lt_decl_all_varnames([SEPARATOR], [VARNAME1...]) # ------------------------------------------------ m4_define([lt_decl_all_varnames], [_$0(m4_quote(m4_default([$1], [[, ]])), m4_if([$2], [], m4_quote(lt_decl_varnames), m4_quote(m4_shift($@))))[]dnl ]) m4_define([_lt_decl_all_varnames], [lt_join($@, lt_decl_varnames_tagged([$1], lt_decl_tag_varnames([[, ]], m4_shift($@))))dnl ]) # _LT_CONFIG_STATUS_DECLARE([VARNAME]) # ------------------------------------ # Quote a variable value, and forward it to `config.status' so that its # declaration there will have the same value as in `configure'. VARNAME # must have a single quote delimited value for this to work. m4_define([_LT_CONFIG_STATUS_DECLARE], [$1='`$ECHO "$][$1" | $SED "$delay_single_quote_subst"`']) # _LT_CONFIG_STATUS_DECLARATIONS # ------------------------------ # We delimit libtool config variables with single quotes, so when # we write them to config.status, we have to be sure to quote all # embedded single quotes properly. In configure, this macro expands # each variable declared with _LT_DECL (and _LT_TAGDECL) into: # # ='`$ECHO "$" | $SED "$delay_single_quote_subst"`' m4_defun([_LT_CONFIG_STATUS_DECLARATIONS], [m4_foreach([_lt_var], m4_quote(lt_decl_all_varnames), [m4_n([_LT_CONFIG_STATUS_DECLARE(_lt_var)])])]) # _LT_LIBTOOL_TAGS # ---------------- # Output comment and list of tags supported by the script m4_defun([_LT_LIBTOOL_TAGS], [_LT_FORMAT_COMMENT([The names of the tagged configurations supported by this script])dnl available_tags="_LT_TAGS"dnl ]) # _LT_LIBTOOL_DECLARE(VARNAME, [TAG]) # ----------------------------------- # Extract the dictionary values for VARNAME (optionally with TAG) and # expand to a commented shell variable setting: # # # Some comment about what VAR is for. # visible_name=$lt_internal_name m4_define([_LT_LIBTOOL_DECLARE], [_LT_FORMAT_COMMENT(m4_quote(lt_dict_fetch([lt_decl_dict], [$1], [description])))[]dnl m4_pushdef([_libtool_name], m4_quote(lt_dict_fetch([lt_decl_dict], [$1], [libtool_name])))[]dnl m4_case(m4_quote(lt_dict_fetch([lt_decl_dict], [$1], [value])), [0], [_libtool_name=[$]$1], [1], [_libtool_name=$lt_[]$1], [2], [_libtool_name=$lt_[]$1], [_libtool_name=lt_dict_fetch([lt_decl_dict], [$1], [value])])[]dnl m4_ifval([$2], [_$2])[]m4_popdef([_libtool_name])[]dnl ]) # _LT_LIBTOOL_CONFIG_VARS # ----------------------- # Produce commented declarations of non-tagged libtool config variables # suitable for insertion in the LIBTOOL CONFIG section of the `libtool' # script. Tagged libtool config variables (even for the LIBTOOL CONFIG # section) are produced by _LT_LIBTOOL_TAG_VARS. m4_defun([_LT_LIBTOOL_CONFIG_VARS], [m4_foreach([_lt_var], m4_quote(_lt_decl_filter([tagged?], [no], [], lt_decl_varnames)), [m4_n([_LT_LIBTOOL_DECLARE(_lt_var)])])]) # _LT_LIBTOOL_TAG_VARS(TAG) # ------------------------- m4_define([_LT_LIBTOOL_TAG_VARS], [m4_foreach([_lt_var], m4_quote(lt_decl_tag_varnames), [m4_n([_LT_LIBTOOL_DECLARE(_lt_var, [$1])])])]) # _LT_TAGVAR(VARNAME, [TAGNAME]) # ------------------------------ m4_define([_LT_TAGVAR], [m4_ifval([$2], [$1_$2], [$1])]) # _LT_CONFIG_COMMANDS # ------------------- # Send accumulated output to $CONFIG_STATUS. Thanks to the lists of # variables for single and double quote escaping we saved from calls # to _LT_DECL, we can put quote escaped variables declarations # into `config.status', and then the shell code to quote escape them in # for loops in `config.status'. Finally, any additional code accumulated # from calls to _LT_CONFIG_LIBTOOL_INIT is expanded. m4_defun([_LT_CONFIG_COMMANDS], [AC_PROVIDE_IFELSE([LT_OUTPUT], dnl If the libtool generation code has been placed in $CONFIG_LT, dnl instead of duplicating it all over again into config.status, dnl then we will have config.status run $CONFIG_LT later, so it dnl needs to know what name is stored there: [AC_CONFIG_COMMANDS([libtool], [$SHELL $CONFIG_LT || AS_EXIT(1)], [CONFIG_LT='$CONFIG_LT'])], dnl If the libtool generation code is destined for config.status, dnl expand the accumulated commands and init code now: [AC_CONFIG_COMMANDS([libtool], [_LT_OUTPUT_LIBTOOL_COMMANDS], [_LT_OUTPUT_LIBTOOL_COMMANDS_INIT])]) ])#_LT_CONFIG_COMMANDS # Initialize. m4_define([_LT_OUTPUT_LIBTOOL_COMMANDS_INIT], [ # The HP-UX ksh and POSIX shell print the target directory to stdout # if CDPATH is set. (unset CDPATH) >/dev/null 2>&1 && unset CDPATH sed_quote_subst='$sed_quote_subst' double_quote_subst='$double_quote_subst' delay_variable_subst='$delay_variable_subst' _LT_CONFIG_STATUS_DECLARATIONS LTCC='$LTCC' LTCFLAGS='$LTCFLAGS' compiler='$compiler_DEFAULT' # A function that is used when there is no print builtin or printf. func_fallback_echo () { eval 'cat <<_LTECHO_EOF \$[]1 _LTECHO_EOF' } # Quote evaled strings. for var in lt_decl_all_varnames([[ \ ]], lt_decl_quote_varnames); do case \`eval \\\\\$ECHO \\\\""\\\\\$\$var"\\\\"\` in *[[\\\\\\\`\\"\\\$]]*) eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"\\\$\$var\\" | \\\$SED \\"\\\$sed_quote_subst\\"\\\`\\\\\\"" ;; *) eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\"" ;; esac done # Double-quote double-evaled strings. for var in lt_decl_all_varnames([[ \ ]], lt_decl_dquote_varnames); do case \`eval \\\\\$ECHO \\\\""\\\\\$\$var"\\\\"\` in *[[\\\\\\\`\\"\\\$]]*) eval "lt_\$var=\\\\\\"\\\`\\\$ECHO \\"\\\$\$var\\" | \\\$SED -e \\"\\\$double_quote_subst\\" -e \\"\\\$sed_quote_subst\\" -e \\"\\\$delay_variable_subst\\"\\\`\\\\\\"" ;; *) eval "lt_\$var=\\\\\\"\\\$\$var\\\\\\"" ;; esac done _LT_OUTPUT_LIBTOOL_INIT ]) # _LT_GENERATED_FILE_INIT(FILE, [COMMENT]) # ------------------------------------ # Generate a child script FILE with all initialization necessary to # reuse the environment learned by the parent script, and make the # file executable. If COMMENT is supplied, it is inserted after the # `#!' sequence but before initialization text begins. After this # macro, additional text can be appended to FILE to form the body of # the child script. The macro ends with non-zero status if the # file could not be fully written (such as if the disk is full). m4_ifdef([AS_INIT_GENERATED], [m4_defun([_LT_GENERATED_FILE_INIT],[AS_INIT_GENERATED($@)])], [m4_defun([_LT_GENERATED_FILE_INIT], [m4_require([AS_PREPARE])]dnl [m4_pushdef([AS_MESSAGE_LOG_FD])]dnl [lt_write_fail=0 cat >$1 <<_ASEOF || lt_write_fail=1 #! $SHELL # Generated by $as_me. $2 SHELL=\${CONFIG_SHELL-$SHELL} export SHELL _ASEOF cat >>$1 <<\_ASEOF || lt_write_fail=1 AS_SHELL_SANITIZE _AS_PREPARE exec AS_MESSAGE_FD>&1 _ASEOF test $lt_write_fail = 0 && chmod +x $1[]dnl m4_popdef([AS_MESSAGE_LOG_FD])])])# _LT_GENERATED_FILE_INIT # LT_OUTPUT # --------- # This macro allows early generation of the libtool script (before # AC_OUTPUT is called), incase it is used in configure for compilation # tests. AC_DEFUN([LT_OUTPUT], [: ${CONFIG_LT=./config.lt} AC_MSG_NOTICE([creating $CONFIG_LT]) _LT_GENERATED_FILE_INIT(["$CONFIG_LT"], [# Run this file to recreate a libtool stub with the current configuration.]) cat >>"$CONFIG_LT" <<\_LTEOF lt_cl_silent=false exec AS_MESSAGE_LOG_FD>>config.log { echo AS_BOX([Running $as_me.]) } >&AS_MESSAGE_LOG_FD lt_cl_help="\ \`$as_me' creates a local libtool stub from the current configuration, for use in further configure time tests before the real libtool is generated. Usage: $[0] [[OPTIONS]] -h, --help print this help, then exit -V, --version print version number, then exit -q, --quiet do not print progress messages -d, --debug don't remove temporary files Report bugs to ." lt_cl_version="\ m4_ifset([AC_PACKAGE_NAME], [AC_PACKAGE_NAME ])config.lt[]dnl m4_ifset([AC_PACKAGE_VERSION], [ AC_PACKAGE_VERSION]) configured by $[0], generated by m4_PACKAGE_STRING. Copyright (C) 2010 Free Software Foundation, Inc. This config.lt script is free software; the Free Software Foundation gives unlimited permision to copy, distribute and modify it." while test $[#] != 0 do case $[1] in --version | --v* | -V ) echo "$lt_cl_version"; exit 0 ;; --help | --h* | -h ) echo "$lt_cl_help"; exit 0 ;; --debug | --d* | -d ) debug=: ;; --quiet | --q* | --silent | --s* | -q ) lt_cl_silent=: ;; -*) AC_MSG_ERROR([unrecognized option: $[1] Try \`$[0] --help' for more information.]) ;; *) AC_MSG_ERROR([unrecognized argument: $[1] Try \`$[0] --help' for more information.]) ;; esac shift done if $lt_cl_silent; then exec AS_MESSAGE_FD>/dev/null fi _LTEOF cat >>"$CONFIG_LT" <<_LTEOF _LT_OUTPUT_LIBTOOL_COMMANDS_INIT _LTEOF cat >>"$CONFIG_LT" <<\_LTEOF AC_MSG_NOTICE([creating $ofile]) _LT_OUTPUT_LIBTOOL_COMMANDS AS_EXIT(0) _LTEOF chmod +x "$CONFIG_LT" # configure is writing to config.log, but config.lt does its own redirection, # appending to config.log, which fails on DOS, as config.log is still kept # open by configure. Here we exec the FD to /dev/null, effectively closing # config.log, so it can be properly (re)opened and appended to by config.lt. lt_cl_success=: test "$silent" = yes && lt_config_lt_args="$lt_config_lt_args --quiet" exec AS_MESSAGE_LOG_FD>/dev/null $SHELL "$CONFIG_LT" $lt_config_lt_args || lt_cl_success=false exec AS_MESSAGE_LOG_FD>>config.log $lt_cl_success || AS_EXIT(1) ])# LT_OUTPUT # _LT_CONFIG(TAG) # --------------- # If TAG is the built-in tag, create an initial libtool script with a # default configuration from the untagged config vars. Otherwise add code # to config.status for appending the configuration named by TAG from the # matching tagged config vars. m4_defun([_LT_CONFIG], [m4_require([_LT_FILEUTILS_DEFAULTS])dnl _LT_CONFIG_SAVE_COMMANDS([ m4_define([_LT_TAG], m4_if([$1], [], [C], [$1]))dnl m4_if(_LT_TAG, [C], [ # See if we are running on zsh, and set the options which allow our # commands through without removal of \ escapes. if test -n "${ZSH_VERSION+set}" ; then setopt NO_GLOB_SUBST fi cfgfile="${ofile}T" trap "$RM \"$cfgfile\"; exit 1" 1 2 15 $RM "$cfgfile" cat <<_LT_EOF >> "$cfgfile" #! $SHELL # `$ECHO "$ofile" | sed 's%^.*/%%'` - Provide generalized library-building support services. # Generated automatically by $as_me ($PACKAGE$TIMESTAMP) $VERSION # Libtool was configured on host `(hostname || uname -n) 2>/dev/null | sed 1q`: # NOTE: Changes made to this file will be lost: look at ltmain.sh. # _LT_COPYING _LT_LIBTOOL_TAGS # ### BEGIN LIBTOOL CONFIG _LT_LIBTOOL_CONFIG_VARS _LT_LIBTOOL_TAG_VARS # ### END LIBTOOL CONFIG _LT_EOF case $host_os in aix3*) cat <<\_LT_EOF >> "$cfgfile" # AIX sometimes has problems with the GCC collect2 program. For some # reason, if we set the COLLECT_NAMES environment variable, the problems # vanish in a puff of smoke. if test "X${COLLECT_NAMES+set}" != Xset; then COLLECT_NAMES= export COLLECT_NAMES fi _LT_EOF ;; esac _LT_PROG_LTMAIN # We use sed instead of cat because bash on DJGPP gets confused if # if finds mixed CR/LF and LF-only lines. Since sed operates in # text mode, it properly converts lines to CR/LF. This bash problem # is reportedly fixed, but why not run on old versions too? sed '$q' "$ltmain" >> "$cfgfile" \ || (rm -f "$cfgfile"; exit 1) _LT_PROG_REPLACE_SHELLFNS mv -f "$cfgfile" "$ofile" || (rm -f "$ofile" && cp "$cfgfile" "$ofile" && rm -f "$cfgfile") chmod +x "$ofile" ], [cat <<_LT_EOF >> "$ofile" dnl Unfortunately we have to use $1 here, since _LT_TAG is not expanded dnl in a comment (ie after a #). # ### BEGIN LIBTOOL TAG CONFIG: $1 _LT_LIBTOOL_TAG_VARS(_LT_TAG) # ### END LIBTOOL TAG CONFIG: $1 _LT_EOF ])dnl /m4_if ], [m4_if([$1], [], [ PACKAGE='$PACKAGE' VERSION='$VERSION' TIMESTAMP='$TIMESTAMP' RM='$RM' ofile='$ofile'], []) ])dnl /_LT_CONFIG_SAVE_COMMANDS ])# _LT_CONFIG # LT_SUPPORTED_TAG(TAG) # --------------------- # Trace this macro to discover what tags are supported by the libtool # --tag option, using: # autoconf --trace 'LT_SUPPORTED_TAG:$1' AC_DEFUN([LT_SUPPORTED_TAG], []) # C support is built-in for now m4_define([_LT_LANG_C_enabled], []) m4_define([_LT_TAGS], []) # LT_LANG(LANG) # ------------- # Enable libtool support for the given language if not already enabled. AC_DEFUN([LT_LANG], [AC_BEFORE([$0], [LT_OUTPUT])dnl m4_case([$1], [C], [_LT_LANG(C)], [C++], [_LT_LANG(CXX)], [Java], [_LT_LANG(GCJ)], [Fortran 77], [_LT_LANG(F77)], [Fortran], [_LT_LANG(FC)], [Windows Resource], [_LT_LANG(RC)], [m4_ifdef([_LT_LANG_]$1[_CONFIG], [_LT_LANG($1)], [m4_fatal([$0: unsupported language: "$1"])])])dnl ])# LT_LANG # _LT_LANG(LANGNAME) # ------------------ m4_defun([_LT_LANG], [m4_ifdef([_LT_LANG_]$1[_enabled], [], [LT_SUPPORTED_TAG([$1])dnl m4_append([_LT_TAGS], [$1 ])dnl m4_define([_LT_LANG_]$1[_enabled], [])dnl _LT_LANG_$1_CONFIG($1)])dnl ])# _LT_LANG # _LT_LANG_DEFAULT_CONFIG # ----------------------- m4_defun([_LT_LANG_DEFAULT_CONFIG], [AC_PROVIDE_IFELSE([AC_PROG_CXX], [LT_LANG(CXX)], [m4_define([AC_PROG_CXX], defn([AC_PROG_CXX])[LT_LANG(CXX)])]) AC_PROVIDE_IFELSE([AC_PROG_F77], [LT_LANG(F77)], [m4_define([AC_PROG_F77], defn([AC_PROG_F77])[LT_LANG(F77)])]) AC_PROVIDE_IFELSE([AC_PROG_FC], [LT_LANG(FC)], [m4_define([AC_PROG_FC], defn([AC_PROG_FC])[LT_LANG(FC)])]) dnl The call to [A][M_PROG_GCJ] is quoted like that to stop aclocal dnl pulling things in needlessly. AC_PROVIDE_IFELSE([AC_PROG_GCJ], [LT_LANG(GCJ)], [AC_PROVIDE_IFELSE([A][M_PROG_GCJ], [LT_LANG(GCJ)], [AC_PROVIDE_IFELSE([LT_PROG_GCJ], [LT_LANG(GCJ)], [m4_ifdef([AC_PROG_GCJ], [m4_define([AC_PROG_GCJ], defn([AC_PROG_GCJ])[LT_LANG(GCJ)])]) m4_ifdef([A][M_PROG_GCJ], [m4_define([A][M_PROG_GCJ], defn([A][M_PROG_GCJ])[LT_LANG(GCJ)])]) m4_ifdef([LT_PROG_GCJ], [m4_define([LT_PROG_GCJ], defn([LT_PROG_GCJ])[LT_LANG(GCJ)])])])])]) AC_PROVIDE_IFELSE([LT_PROG_RC], [LT_LANG(RC)], [m4_define([LT_PROG_RC], defn([LT_PROG_RC])[LT_LANG(RC)])]) ])# _LT_LANG_DEFAULT_CONFIG # Obsolete macros: AU_DEFUN([AC_LIBTOOL_CXX], [LT_LANG(C++)]) AU_DEFUN([AC_LIBTOOL_F77], [LT_LANG(Fortran 77)]) AU_DEFUN([AC_LIBTOOL_FC], [LT_LANG(Fortran)]) AU_DEFUN([AC_LIBTOOL_GCJ], [LT_LANG(Java)]) AU_DEFUN([AC_LIBTOOL_RC], [LT_LANG(Windows Resource)]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AC_LIBTOOL_CXX], []) dnl AC_DEFUN([AC_LIBTOOL_F77], []) dnl AC_DEFUN([AC_LIBTOOL_FC], []) dnl AC_DEFUN([AC_LIBTOOL_GCJ], []) dnl AC_DEFUN([AC_LIBTOOL_RC], []) # _LT_TAG_COMPILER # ---------------- m4_defun([_LT_TAG_COMPILER], [AC_REQUIRE([AC_PROG_CC])dnl _LT_DECL([LTCC], [CC], [1], [A C compiler])dnl _LT_DECL([LTCFLAGS], [CFLAGS], [1], [LTCC compiler flags])dnl _LT_TAGDECL([CC], [compiler], [1], [A language specific compiler])dnl _LT_TAGDECL([with_gcc], [GCC], [0], [Is the compiler the GNU compiler?])dnl # If no C compiler was specified, use CC. LTCC=${LTCC-"$CC"} # If no C compiler flags were specified, use CFLAGS. LTCFLAGS=${LTCFLAGS-"$CFLAGS"} # Allow CC to be a program name with arguments. compiler=$CC ])# _LT_TAG_COMPILER # _LT_COMPILER_BOILERPLATE # ------------------------ # Check for compiler boilerplate output or warnings with # the simple compiler test code. m4_defun([_LT_COMPILER_BOILERPLATE], [m4_require([_LT_DECL_SED])dnl ac_outfile=conftest.$ac_objext echo "$lt_simple_compile_test_code" >conftest.$ac_ext eval "$ac_compile" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err _lt_compiler_boilerplate=`cat conftest.err` $RM conftest* ])# _LT_COMPILER_BOILERPLATE # _LT_LINKER_BOILERPLATE # ---------------------- # Check for linker boilerplate output or warnings with # the simple link test code. m4_defun([_LT_LINKER_BOILERPLATE], [m4_require([_LT_DECL_SED])dnl ac_outfile=conftest.$ac_objext echo "$lt_simple_link_test_code" >conftest.$ac_ext eval "$ac_link" 2>&1 >/dev/null | $SED '/^$/d; /^ *+/d' >conftest.err _lt_linker_boilerplate=`cat conftest.err` $RM -r conftest* ])# _LT_LINKER_BOILERPLATE # _LT_REQUIRED_DARWIN_CHECKS # ------------------------- m4_defun_once([_LT_REQUIRED_DARWIN_CHECKS],[ case $host_os in rhapsody* | darwin*) AC_CHECK_TOOL([DSYMUTIL], [dsymutil], [:]) AC_CHECK_TOOL([NMEDIT], [nmedit], [:]) AC_CHECK_TOOL([LIPO], [lipo], [:]) AC_CHECK_TOOL([OTOOL], [otool], [:]) AC_CHECK_TOOL([OTOOL64], [otool64], [:]) _LT_DECL([], [DSYMUTIL], [1], [Tool to manipulate archived DWARF debug symbol files on Mac OS X]) _LT_DECL([], [NMEDIT], [1], [Tool to change global to local symbols on Mac OS X]) _LT_DECL([], [LIPO], [1], [Tool to manipulate fat objects and archives on Mac OS X]) _LT_DECL([], [OTOOL], [1], [ldd/readelf like tool for Mach-O binaries on Mac OS X]) _LT_DECL([], [OTOOL64], [1], [ldd/readelf like tool for 64 bit Mach-O binaries on Mac OS X 10.4]) AC_CACHE_CHECK([for -single_module linker flag],[lt_cv_apple_cc_single_mod], [lt_cv_apple_cc_single_mod=no if test -z "${LT_MULTI_MODULE}"; then # By default we will add the -single_module flag. You can override # by either setting the environment variable LT_MULTI_MODULE # non-empty at configure time, or by adding -multi_module to the # link flags. rm -rf libconftest.dylib* echo "int foo(void){return 1;}" > conftest.c echo "$LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \ -dynamiclib -Wl,-single_module conftest.c" >&AS_MESSAGE_LOG_FD $LTCC $LTCFLAGS $LDFLAGS -o libconftest.dylib \ -dynamiclib -Wl,-single_module conftest.c 2>conftest.err _lt_result=$? if test -f libconftest.dylib && test ! -s conftest.err && test $_lt_result = 0; then lt_cv_apple_cc_single_mod=yes else cat conftest.err >&AS_MESSAGE_LOG_FD fi rm -rf libconftest.dylib* rm -f conftest.* fi]) AC_CACHE_CHECK([for -exported_symbols_list linker flag], [lt_cv_ld_exported_symbols_list], [lt_cv_ld_exported_symbols_list=no save_LDFLAGS=$LDFLAGS echo "_main" > conftest.sym LDFLAGS="$LDFLAGS -Wl,-exported_symbols_list,conftest.sym" AC_LINK_IFELSE([AC_LANG_PROGRAM([],[])], [lt_cv_ld_exported_symbols_list=yes], [lt_cv_ld_exported_symbols_list=no]) LDFLAGS="$save_LDFLAGS" ]) AC_CACHE_CHECK([for -force_load linker flag],[lt_cv_ld_force_load], [lt_cv_ld_force_load=no cat > conftest.c << _LT_EOF int forced_loaded() { return 2;} _LT_EOF echo "$LTCC $LTCFLAGS -c -o conftest.o conftest.c" >&AS_MESSAGE_LOG_FD $LTCC $LTCFLAGS -c -o conftest.o conftest.c 2>&AS_MESSAGE_LOG_FD echo "$AR cru libconftest.a conftest.o" >&AS_MESSAGE_LOG_FD $AR cru libconftest.a conftest.o 2>&AS_MESSAGE_LOG_FD echo "$RANLIB libconftest.a" >&AS_MESSAGE_LOG_FD $RANLIB libconftest.a 2>&AS_MESSAGE_LOG_FD cat > conftest.c << _LT_EOF int main() { return 0;} _LT_EOF echo "$LTCC $LTCFLAGS $LDFLAGS -o conftest conftest.c -Wl,-force_load,./libconftest.a" >&AS_MESSAGE_LOG_FD $LTCC $LTCFLAGS $LDFLAGS -o conftest conftest.c -Wl,-force_load,./libconftest.a 2>conftest.err _lt_result=$? if test -f conftest && test ! -s conftest.err && test $_lt_result = 0 && $GREP forced_load conftest 2>&1 >/dev/null; then lt_cv_ld_force_load=yes else cat conftest.err >&AS_MESSAGE_LOG_FD fi rm -f conftest.err libconftest.a conftest conftest.c rm -rf conftest.dSYM ]) case $host_os in rhapsody* | darwin1.[[012]]) _lt_dar_allow_undefined='${wl}-undefined ${wl}suppress' ;; darwin1.*) _lt_dar_allow_undefined='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;; darwin*) # darwin 5.x on # if running on 10.5 or later, the deployment target defaults # to the OS version, if on x86, and 10.4, the deployment # target defaults to 10.4. Don't you love it? case ${MACOSX_DEPLOYMENT_TARGET-10.0},$host in 10.0,*86*-darwin8*|10.0,*-darwin[[91]]*) _lt_dar_allow_undefined='${wl}-undefined ${wl}dynamic_lookup' ;; 10.[[012]]*) _lt_dar_allow_undefined='${wl}-flat_namespace ${wl}-undefined ${wl}suppress' ;; 10.*) _lt_dar_allow_undefined='${wl}-undefined ${wl}dynamic_lookup' ;; esac ;; esac if test "$lt_cv_apple_cc_single_mod" = "yes"; then _lt_dar_single_mod='$single_module' fi if test "$lt_cv_ld_exported_symbols_list" = "yes"; then _lt_dar_export_syms=' ${wl}-exported_symbols_list,$output_objdir/${libname}-symbols.expsym' else _lt_dar_export_syms='~$NMEDIT -s $output_objdir/${libname}-symbols.expsym ${lib}' fi if test "$DSYMUTIL" != ":" && test "$lt_cv_ld_force_load" = "no"; then _lt_dsymutil='~$DSYMUTIL $lib || :' else _lt_dsymutil= fi ;; esac ]) # _LT_DARWIN_LINKER_FEATURES # -------------------------- # Checks for linker and compiler features on darwin m4_defun([_LT_DARWIN_LINKER_FEATURES], [ m4_require([_LT_REQUIRED_DARWIN_CHECKS]) _LT_TAGVAR(archive_cmds_need_lc, $1)=no _LT_TAGVAR(hardcode_direct, $1)=no _LT_TAGVAR(hardcode_automatic, $1)=yes _LT_TAGVAR(hardcode_shlibpath_var, $1)=unsupported if test "$lt_cv_ld_force_load" = "yes"; then _LT_TAGVAR(whole_archive_flag_spec, $1)='`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience ${wl}-force_load,$conv\"; done; func_echo_all \"$new_convenience\"`' else _LT_TAGVAR(whole_archive_flag_spec, $1)='' fi _LT_TAGVAR(link_all_deplibs, $1)=yes _LT_TAGVAR(allow_undefined_flag, $1)="$_lt_dar_allow_undefined" case $cc_basename in ifort*) _lt_dar_can_shared=yes ;; *) _lt_dar_can_shared=$GCC ;; esac if test "$_lt_dar_can_shared" = "yes"; then output_verbose_link_cmd=func_echo_all _LT_TAGVAR(archive_cmds, $1)="\$CC -dynamiclib \$allow_undefined_flag -o \$lib \$libobjs \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring $_lt_dar_single_mod${_lt_dsymutil}" _LT_TAGVAR(module_cmds, $1)="\$CC \$allow_undefined_flag -o \$lib -bundle \$libobjs \$deplibs \$compiler_flags${_lt_dsymutil}" _LT_TAGVAR(archive_expsym_cmds, $1)="sed 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC -dynamiclib \$allow_undefined_flag -o \$lib \$libobjs \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring ${_lt_dar_single_mod}${_lt_dar_export_syms}${_lt_dsymutil}" _LT_TAGVAR(module_expsym_cmds, $1)="sed -e 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC \$allow_undefined_flag -o \$lib -bundle \$libobjs \$deplibs \$compiler_flags${_lt_dar_export_syms}${_lt_dsymutil}" m4_if([$1], [CXX], [ if test "$lt_cv_apple_cc_single_mod" != "yes"; then _LT_TAGVAR(archive_cmds, $1)="\$CC -r -keep_private_externs -nostdlib -o \${lib}-master.o \$libobjs~\$CC -dynamiclib \$allow_undefined_flag -o \$lib \${lib}-master.o \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring${_lt_dsymutil}" _LT_TAGVAR(archive_expsym_cmds, $1)="sed 's,^,_,' < \$export_symbols > \$output_objdir/\${libname}-symbols.expsym~\$CC -r -keep_private_externs -nostdlib -o \${lib}-master.o \$libobjs~\$CC -dynamiclib \$allow_undefined_flag -o \$lib \${lib}-master.o \$deplibs \$compiler_flags -install_name \$rpath/\$soname \$verstring${_lt_dar_export_syms}${_lt_dsymutil}" fi ],[]) else _LT_TAGVAR(ld_shlibs, $1)=no fi ]) # _LT_SYS_MODULE_PATH_AIX([TAGNAME]) # ---------------------------------- # Links a minimal program and checks the executable # for the system default hardcoded library path. In most cases, # this is /usr/lib:/lib, but when the MPI compilers are used # the location of the communication and MPI libs are included too. # If we don't find anything, use the default library path according # to the aix ld manual. # Store the results from the different compilers for each TAGNAME. # Allow to override them for all tags through lt_cv_aix_libpath. m4_defun([_LT_SYS_MODULE_PATH_AIX], [m4_require([_LT_DECL_SED])dnl if test "${lt_cv_aix_libpath+set}" = set; then aix_libpath=$lt_cv_aix_libpath else AC_CACHE_VAL([_LT_TAGVAR([lt_cv_aix_libpath_], [$1])], [AC_LINK_IFELSE([AC_LANG_PROGRAM],[ lt_aix_libpath_sed='[ /Import File Strings/,/^$/ { /^0/ { s/^0 *\([^ ]*\) *$/\1/ p } }]' _LT_TAGVAR([lt_cv_aix_libpath_], [$1])=`dump -H conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` # Check for a 64-bit object if we didn't find anything. if test -z "$_LT_TAGVAR([lt_cv_aix_libpath_], [$1])"; then _LT_TAGVAR([lt_cv_aix_libpath_], [$1])=`dump -HX64 conftest$ac_exeext 2>/dev/null | $SED -n -e "$lt_aix_libpath_sed"` fi],[]) if test -z "$_LT_TAGVAR([lt_cv_aix_libpath_], [$1])"; then _LT_TAGVAR([lt_cv_aix_libpath_], [$1])="/usr/lib:/lib" fi ]) aix_libpath=$_LT_TAGVAR([lt_cv_aix_libpath_], [$1]) fi ])# _LT_SYS_MODULE_PATH_AIX # _LT_SHELL_INIT(ARG) # ------------------- m4_define([_LT_SHELL_INIT], [m4_divert_text([M4SH-INIT], [$1 ])])# _LT_SHELL_INIT # _LT_PROG_ECHO_BACKSLASH # ----------------------- # Find how we can fake an echo command that does not interpret backslash. # In particular, with Autoconf 2.60 or later we add some code to the start # of the generated configure script which will find a shell with a builtin # printf (which we can use as an echo command). m4_defun([_LT_PROG_ECHO_BACKSLASH], [ECHO='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO$ECHO AC_MSG_CHECKING([how to print strings]) # Test print first, because it will be a builtin if present. if test "X`( print -r -- -n ) 2>/dev/null`" = X-n && \ test "X`print -r -- $ECHO 2>/dev/null`" = "X$ECHO"; then ECHO='print -r --' elif test "X`printf %s $ECHO 2>/dev/null`" = "X$ECHO"; then ECHO='printf %s\n' else # Use this function as a fallback that always works. func_fallback_echo () { eval 'cat <<_LTECHO_EOF $[]1 _LTECHO_EOF' } ECHO='func_fallback_echo' fi # func_echo_all arg... # Invoke $ECHO with all args, space-separated. func_echo_all () { $ECHO "$*" } case "$ECHO" in printf*) AC_MSG_RESULT([printf]) ;; print*) AC_MSG_RESULT([print -r]) ;; *) AC_MSG_RESULT([cat]) ;; esac m4_ifdef([_AS_DETECT_SUGGESTED], [_AS_DETECT_SUGGESTED([ test -n "${ZSH_VERSION+set}${BASH_VERSION+set}" || ( ECHO='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO ECHO=$ECHO$ECHO$ECHO$ECHO$ECHO$ECHO PATH=/empty FPATH=/empty; export PATH FPATH test "X`printf %s $ECHO`" = "X$ECHO" \ || test "X`print -r -- $ECHO`" = "X$ECHO" )])]) _LT_DECL([], [SHELL], [1], [Shell to use when invoking shell scripts]) _LT_DECL([], [ECHO], [1], [An echo program that protects backslashes]) ])# _LT_PROG_ECHO_BACKSLASH # _LT_WITH_SYSROOT # ---------------- AC_DEFUN([_LT_WITH_SYSROOT], [AC_MSG_CHECKING([for sysroot]) AC_ARG_WITH([sysroot], [ --with-sysroot[=DIR] Search for dependent libraries within DIR (or the compiler's sysroot if not specified).], [], [with_sysroot=no]) dnl lt_sysroot will always be passed unquoted. We quote it here dnl in case the user passed a directory name. lt_sysroot= case ${with_sysroot} in #( yes) if test "$GCC" = yes; then lt_sysroot=`$CC --print-sysroot 2>/dev/null` fi ;; #( /*) lt_sysroot=`echo "$with_sysroot" | sed -e "$sed_quote_subst"` ;; #( no|'') ;; #( *) AC_MSG_RESULT([${with_sysroot}]) AC_MSG_ERROR([The sysroot must be an absolute path.]) ;; esac AC_MSG_RESULT([${lt_sysroot:-no}]) _LT_DECL([], [lt_sysroot], [0], [The root where to search for ]dnl [dependent libraries, and in which our libraries should be installed.])]) # _LT_ENABLE_LOCK # --------------- m4_defun([_LT_ENABLE_LOCK], [AC_ARG_ENABLE([libtool-lock], [AS_HELP_STRING([--disable-libtool-lock], [avoid locking (might break parallel builds)])]) test "x$enable_libtool_lock" != xno && enable_libtool_lock=yes # Some flags need to be propagated to the compiler or linker for good # libtool support. case $host in ia64-*-hpux*) # Find out which ABI we are using. echo 'int i;' > conftest.$ac_ext if AC_TRY_EVAL(ac_compile); then case `/usr/bin/file conftest.$ac_objext` in *ELF-32*) HPUX_IA64_MODE="32" ;; *ELF-64*) HPUX_IA64_MODE="64" ;; esac fi rm -rf conftest* ;; *-*-irix6*) # Find out which ABI we are using. echo '[#]line '$LINENO' "configure"' > conftest.$ac_ext if AC_TRY_EVAL(ac_compile); then if test "$lt_cv_prog_gnu_ld" = yes; then case `/usr/bin/file conftest.$ac_objext` in *32-bit*) LD="${LD-ld} -melf32bsmip" ;; *N32*) LD="${LD-ld} -melf32bmipn32" ;; *64-bit*) LD="${LD-ld} -melf64bmip" ;; esac else case `/usr/bin/file conftest.$ac_objext` in *32-bit*) LD="${LD-ld} -32" ;; *N32*) LD="${LD-ld} -n32" ;; *64-bit*) LD="${LD-ld} -64" ;; esac fi fi rm -rf conftest* ;; x86_64-*kfreebsd*-gnu|x86_64-*linux*|ppc*-*linux*|powerpc*-*linux*| \ s390*-*linux*|s390*-*tpf*|sparc*-*linux*) # Find out which ABI we are using. echo 'int i;' > conftest.$ac_ext if AC_TRY_EVAL(ac_compile); then case `/usr/bin/file conftest.o` in *32-bit*) case $host in x86_64-*kfreebsd*-gnu) LD="${LD-ld} -m elf_i386_fbsd" ;; x86_64-*linux*) LD="${LD-ld} -m elf_i386" ;; ppc64-*linux*|powerpc64-*linux*) LD="${LD-ld} -m elf32ppclinux" ;; s390x-*linux*) LD="${LD-ld} -m elf_s390" ;; sparc64-*linux*) LD="${LD-ld} -m elf32_sparc" ;; esac ;; *64-bit*) case $host in x86_64-*kfreebsd*-gnu) LD="${LD-ld} -m elf_x86_64_fbsd" ;; x86_64-*linux*) LD="${LD-ld} -m elf_x86_64" ;; ppc*-*linux*|powerpc*-*linux*) LD="${LD-ld} -m elf64ppc" ;; s390*-*linux*|s390*-*tpf*) LD="${LD-ld} -m elf64_s390" ;; sparc*-*linux*) LD="${LD-ld} -m elf64_sparc" ;; esac ;; esac fi rm -rf conftest* ;; *-*-sco3.2v5*) # On SCO OpenServer 5, we need -belf to get full-featured binaries. SAVE_CFLAGS="$CFLAGS" CFLAGS="$CFLAGS -belf" AC_CACHE_CHECK([whether the C compiler needs -belf], lt_cv_cc_needs_belf, [AC_LANG_PUSH(C) AC_LINK_IFELSE([AC_LANG_PROGRAM([[]],[[]])],[lt_cv_cc_needs_belf=yes],[lt_cv_cc_needs_belf=no]) AC_LANG_POP]) if test x"$lt_cv_cc_needs_belf" != x"yes"; then # this is probably gcc 2.8.0, egcs 1.0 or newer; no need for -belf CFLAGS="$SAVE_CFLAGS" fi ;; sparc*-*solaris*) # Find out which ABI we are using. echo 'int i;' > conftest.$ac_ext if AC_TRY_EVAL(ac_compile); then case `/usr/bin/file conftest.o` in *64-bit*) case $lt_cv_prog_gnu_ld in yes*) LD="${LD-ld} -m elf64_sparc" ;; *) if ${LD-ld} -64 -r -o conftest2.o conftest.o >/dev/null 2>&1; then LD="${LD-ld} -64" fi ;; esac ;; esac fi rm -rf conftest* ;; esac need_locks="$enable_libtool_lock" ])# _LT_ENABLE_LOCK # _LT_PROG_AR # ----------- m4_defun([_LT_PROG_AR], [AC_CHECK_TOOLS(AR, [ar], false) : ${AR=ar} : ${AR_FLAGS=cru} _LT_DECL([], [AR], [1], [The archiver]) _LT_DECL([], [AR_FLAGS], [1], [Flags to create an archive]) AC_CACHE_CHECK([for archiver @FILE support], [lt_cv_ar_at_file], [lt_cv_ar_at_file=no AC_COMPILE_IFELSE([AC_LANG_PROGRAM], [echo conftest.$ac_objext > conftest.lst lt_ar_try='$AR $AR_FLAGS libconftest.a @conftest.lst >&AS_MESSAGE_LOG_FD' AC_TRY_EVAL([lt_ar_try]) if test "$ac_status" -eq 0; then # Ensure the archiver fails upon bogus file names. rm -f conftest.$ac_objext libconftest.a AC_TRY_EVAL([lt_ar_try]) if test "$ac_status" -ne 0; then lt_cv_ar_at_file=@ fi fi rm -f conftest.* libconftest.a ]) ]) if test "x$lt_cv_ar_at_file" = xno; then archiver_list_spec= else archiver_list_spec=$lt_cv_ar_at_file fi _LT_DECL([], [archiver_list_spec], [1], [How to feed a file listing to the archiver]) ])# _LT_PROG_AR # _LT_CMD_OLD_ARCHIVE # ------------------- m4_defun([_LT_CMD_OLD_ARCHIVE], [_LT_PROG_AR AC_CHECK_TOOL(STRIP, strip, :) test -z "$STRIP" && STRIP=: _LT_DECL([], [STRIP], [1], [A symbol stripping program]) AC_CHECK_TOOL(RANLIB, ranlib, :) test -z "$RANLIB" && RANLIB=: _LT_DECL([], [RANLIB], [1], [Commands used to install an old-style archive]) # Determine commands to create old-style static archives. old_archive_cmds='$AR $AR_FLAGS $oldlib$oldobjs' old_postinstall_cmds='chmod 644 $oldlib' old_postuninstall_cmds= if test -n "$RANLIB"; then case $host_os in openbsd*) old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB -t \$oldlib" ;; *) old_postinstall_cmds="$old_postinstall_cmds~\$RANLIB \$oldlib" ;; esac old_archive_cmds="$old_archive_cmds~\$RANLIB \$oldlib" fi case $host_os in darwin*) lock_old_archive_extraction=yes ;; *) lock_old_archive_extraction=no ;; esac _LT_DECL([], [old_postinstall_cmds], [2]) _LT_DECL([], [old_postuninstall_cmds], [2]) _LT_TAGDECL([], [old_archive_cmds], [2], [Commands used to build an old-style archive]) _LT_DECL([], [lock_old_archive_extraction], [0], [Whether to use a lock for old archive extraction]) ])# _LT_CMD_OLD_ARCHIVE # _LT_COMPILER_OPTION(MESSAGE, VARIABLE-NAME, FLAGS, # [OUTPUT-FILE], [ACTION-SUCCESS], [ACTION-FAILURE]) # ---------------------------------------------------------------- # Check whether the given compiler option works AC_DEFUN([_LT_COMPILER_OPTION], [m4_require([_LT_FILEUTILS_DEFAULTS])dnl m4_require([_LT_DECL_SED])dnl AC_CACHE_CHECK([$1], [$2], [$2=no m4_if([$4], , [ac_outfile=conftest.$ac_objext], [ac_outfile=$4]) echo "$lt_simple_compile_test_code" > conftest.$ac_ext lt_compiler_flag="$3" # Insert the option either (1) after the last *FLAGS variable, or # (2) before a word containing "conftest.", or (3) at the end. # Note that $ac_compile itself does not contain backslashes and begins # with a dollar sign (not a hyphen), so the echo should work correctly. # The option is referenced via a variable to avoid confusing sed. lt_compile=`echo "$ac_compile" | $SED \ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [[^ ]]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&AS_MESSAGE_LOG_FD) (eval "$lt_compile" 2>conftest.err) ac_status=$? cat conftest.err >&AS_MESSAGE_LOG_FD echo "$as_me:$LINENO: \$? = $ac_status" >&AS_MESSAGE_LOG_FD if (exit $ac_status) && test -s "$ac_outfile"; then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings other than the usual output. $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' >conftest.exp $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 if test ! -s conftest.er2 || diff conftest.exp conftest.er2 >/dev/null; then $2=yes fi fi $RM conftest* ]) if test x"[$]$2" = xyes; then m4_if([$5], , :, [$5]) else m4_if([$6], , :, [$6]) fi ])# _LT_COMPILER_OPTION # Old name: AU_ALIAS([AC_LIBTOOL_COMPILER_OPTION], [_LT_COMPILER_OPTION]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AC_LIBTOOL_COMPILER_OPTION], []) # _LT_LINKER_OPTION(MESSAGE, VARIABLE-NAME, FLAGS, # [ACTION-SUCCESS], [ACTION-FAILURE]) # ---------------------------------------------------- # Check whether the given linker option works AC_DEFUN([_LT_LINKER_OPTION], [m4_require([_LT_FILEUTILS_DEFAULTS])dnl m4_require([_LT_DECL_SED])dnl AC_CACHE_CHECK([$1], [$2], [$2=no save_LDFLAGS="$LDFLAGS" LDFLAGS="$LDFLAGS $3" echo "$lt_simple_link_test_code" > conftest.$ac_ext if (eval $ac_link 2>conftest.err) && test -s conftest$ac_exeext; then # The linker can only warn and ignore the option if not recognized # So say no if there are warnings if test -s conftest.err; then # Append any errors to the config.log. cat conftest.err 1>&AS_MESSAGE_LOG_FD $ECHO "$_lt_linker_boilerplate" | $SED '/^$/d' > conftest.exp $SED '/^$/d; /^ *+/d' conftest.err >conftest.er2 if diff conftest.exp conftest.er2 >/dev/null; then $2=yes fi else $2=yes fi fi $RM -r conftest* LDFLAGS="$save_LDFLAGS" ]) if test x"[$]$2" = xyes; then m4_if([$4], , :, [$4]) else m4_if([$5], , :, [$5]) fi ])# _LT_LINKER_OPTION # Old name: AU_ALIAS([AC_LIBTOOL_LINKER_OPTION], [_LT_LINKER_OPTION]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AC_LIBTOOL_LINKER_OPTION], []) # LT_CMD_MAX_LEN #--------------- AC_DEFUN([LT_CMD_MAX_LEN], [AC_REQUIRE([AC_CANONICAL_HOST])dnl # find the maximum length of command line arguments AC_MSG_CHECKING([the maximum length of command line arguments]) AC_CACHE_VAL([lt_cv_sys_max_cmd_len], [dnl i=0 teststring="ABCD" case $build_os in msdosdjgpp*) # On DJGPP, this test can blow up pretty badly due to problems in libc # (any single argument exceeding 2000 bytes causes a buffer overrun # during glob expansion). Even if it were fixed, the result of this # check would be larger than it should be. lt_cv_sys_max_cmd_len=12288; # 12K is about right ;; gnu*) # Under GNU Hurd, this test is not required because there is # no limit to the length of command line arguments. # Libtool will interpret -1 as no limit whatsoever lt_cv_sys_max_cmd_len=-1; ;; cygwin* | mingw* | cegcc*) # On Win9x/ME, this test blows up -- it succeeds, but takes # about 5 minutes as the teststring grows exponentially. # Worse, since 9x/ME are not pre-emptively multitasking, # you end up with a "frozen" computer, even though with patience # the test eventually succeeds (with a max line length of 256k). # Instead, let's just punt: use the minimum linelength reported by # all of the supported platforms: 8192 (on NT/2K/XP). lt_cv_sys_max_cmd_len=8192; ;; mint*) # On MiNT this can take a long time and run out of memory. lt_cv_sys_max_cmd_len=8192; ;; amigaos*) # On AmigaOS with pdksh, this test takes hours, literally. # So we just punt and use a minimum line length of 8192. lt_cv_sys_max_cmd_len=8192; ;; netbsd* | freebsd* | openbsd* | darwin* | dragonfly*) # This has been around since 386BSD, at least. Likely further. if test -x /sbin/sysctl; then lt_cv_sys_max_cmd_len=`/sbin/sysctl -n kern.argmax` elif test -x /usr/sbin/sysctl; then lt_cv_sys_max_cmd_len=`/usr/sbin/sysctl -n kern.argmax` else lt_cv_sys_max_cmd_len=65536 # usable default for all BSDs fi # And add a safety zone lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4` lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3` ;; interix*) # We know the value 262144 and hardcode it with a safety zone (like BSD) lt_cv_sys_max_cmd_len=196608 ;; osf*) # Dr. Hans Ekkehard Plesser reports seeing a kernel panic running configure # due to this test when exec_disable_arg_limit is 1 on Tru64. It is not # nice to cause kernel panics so lets avoid the loop below. # First set a reasonable default. lt_cv_sys_max_cmd_len=16384 # if test -x /sbin/sysconfig; then case `/sbin/sysconfig -q proc exec_disable_arg_limit` in *1*) lt_cv_sys_max_cmd_len=-1 ;; esac fi ;; sco3.2v5*) lt_cv_sys_max_cmd_len=102400 ;; sysv5* | sco5v6* | sysv4.2uw2*) kargmax=`grep ARG_MAX /etc/conf/cf.d/stune 2>/dev/null` if test -n "$kargmax"; then lt_cv_sys_max_cmd_len=`echo $kargmax | sed 's/.*[[ ]]//'` else lt_cv_sys_max_cmd_len=32768 fi ;; *) lt_cv_sys_max_cmd_len=`(getconf ARG_MAX) 2> /dev/null` if test -n "$lt_cv_sys_max_cmd_len"; then lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 4` lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \* 3` else # Make teststring a little bigger before we do anything with it. # a 1K string should be a reasonable start. for i in 1 2 3 4 5 6 7 8 ; do teststring=$teststring$teststring done SHELL=${SHELL-${CONFIG_SHELL-/bin/sh}} # If test is not a shell built-in, we'll probably end up computing a # maximum length that is only half of the actual maximum length, but # we can't tell. while { test "X"`func_fallback_echo "$teststring$teststring" 2>/dev/null` \ = "X$teststring$teststring"; } >/dev/null 2>&1 && test $i != 17 # 1/2 MB should be enough do i=`expr $i + 1` teststring=$teststring$teststring done # Only check the string length outside the loop. lt_cv_sys_max_cmd_len=`expr "X$teststring" : ".*" 2>&1` teststring= # Add a significant safety factor because C++ compilers can tack on # massive amounts of additional arguments before passing them to the # linker. It appears as though 1/2 is a usable value. lt_cv_sys_max_cmd_len=`expr $lt_cv_sys_max_cmd_len \/ 2` fi ;; esac ]) if test -n $lt_cv_sys_max_cmd_len ; then AC_MSG_RESULT($lt_cv_sys_max_cmd_len) else AC_MSG_RESULT(none) fi max_cmd_len=$lt_cv_sys_max_cmd_len _LT_DECL([], [max_cmd_len], [0], [What is the maximum length of a command?]) ])# LT_CMD_MAX_LEN # Old name: AU_ALIAS([AC_LIBTOOL_SYS_MAX_CMD_LEN], [LT_CMD_MAX_LEN]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AC_LIBTOOL_SYS_MAX_CMD_LEN], []) # _LT_HEADER_DLFCN # ---------------- m4_defun([_LT_HEADER_DLFCN], [AC_CHECK_HEADERS([dlfcn.h], [], [], [AC_INCLUDES_DEFAULT])dnl ])# _LT_HEADER_DLFCN # _LT_TRY_DLOPEN_SELF (ACTION-IF-TRUE, ACTION-IF-TRUE-W-USCORE, # ACTION-IF-FALSE, ACTION-IF-CROSS-COMPILING) # ---------------------------------------------------------------- m4_defun([_LT_TRY_DLOPEN_SELF], [m4_require([_LT_HEADER_DLFCN])dnl if test "$cross_compiling" = yes; then : [$4] else lt_dlunknown=0; lt_dlno_uscore=1; lt_dlneed_uscore=2 lt_status=$lt_dlunknown cat > conftest.$ac_ext <<_LT_EOF [#line $LINENO "configure" #include "confdefs.h" #if HAVE_DLFCN_H #include #endif #include #ifdef RTLD_GLOBAL # define LT_DLGLOBAL RTLD_GLOBAL #else # ifdef DL_GLOBAL # define LT_DLGLOBAL DL_GLOBAL # else # define LT_DLGLOBAL 0 # endif #endif /* We may have to define LT_DLLAZY_OR_NOW in the command line if we find out it does not work in some platform. */ #ifndef LT_DLLAZY_OR_NOW # ifdef RTLD_LAZY # define LT_DLLAZY_OR_NOW RTLD_LAZY # else # ifdef DL_LAZY # define LT_DLLAZY_OR_NOW DL_LAZY # else # ifdef RTLD_NOW # define LT_DLLAZY_OR_NOW RTLD_NOW # else # ifdef DL_NOW # define LT_DLLAZY_OR_NOW DL_NOW # else # define LT_DLLAZY_OR_NOW 0 # endif # endif # endif # endif #endif /* When -fvisbility=hidden is used, assume the code has been annotated correspondingly for the symbols needed. */ #if defined(__GNUC__) && (((__GNUC__ == 3) && (__GNUC_MINOR__ >= 3)) || (__GNUC__ > 3)) int fnord () __attribute__((visibility("default"))); #endif int fnord () { return 42; } int main () { void *self = dlopen (0, LT_DLGLOBAL|LT_DLLAZY_OR_NOW); int status = $lt_dlunknown; if (self) { if (dlsym (self,"fnord")) status = $lt_dlno_uscore; else { if (dlsym( self,"_fnord")) status = $lt_dlneed_uscore; else puts (dlerror ()); } /* dlclose (self); */ } else puts (dlerror ()); return status; }] _LT_EOF if AC_TRY_EVAL(ac_link) && test -s conftest${ac_exeext} 2>/dev/null; then (./conftest; exit; ) >&AS_MESSAGE_LOG_FD 2>/dev/null lt_status=$? case x$lt_status in x$lt_dlno_uscore) $1 ;; x$lt_dlneed_uscore) $2 ;; x$lt_dlunknown|x*) $3 ;; esac else : # compilation failed $3 fi fi rm -fr conftest* ])# _LT_TRY_DLOPEN_SELF # LT_SYS_DLOPEN_SELF # ------------------ AC_DEFUN([LT_SYS_DLOPEN_SELF], [m4_require([_LT_HEADER_DLFCN])dnl if test "x$enable_dlopen" != xyes; then enable_dlopen=unknown enable_dlopen_self=unknown enable_dlopen_self_static=unknown else lt_cv_dlopen=no lt_cv_dlopen_libs= case $host_os in beos*) lt_cv_dlopen="load_add_on" lt_cv_dlopen_libs= lt_cv_dlopen_self=yes ;; mingw* | pw32* | cegcc*) lt_cv_dlopen="LoadLibrary" lt_cv_dlopen_libs= ;; cygwin*) lt_cv_dlopen="dlopen" lt_cv_dlopen_libs= ;; darwin*) # if libdl is installed we need to link against it AC_CHECK_LIB([dl], [dlopen], [lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl"],[ lt_cv_dlopen="dyld" lt_cv_dlopen_libs= lt_cv_dlopen_self=yes ]) ;; *) AC_CHECK_FUNC([shl_load], [lt_cv_dlopen="shl_load"], [AC_CHECK_LIB([dld], [shl_load], [lt_cv_dlopen="shl_load" lt_cv_dlopen_libs="-ldld"], [AC_CHECK_FUNC([dlopen], [lt_cv_dlopen="dlopen"], [AC_CHECK_LIB([dl], [dlopen], [lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-ldl"], [AC_CHECK_LIB([svld], [dlopen], [lt_cv_dlopen="dlopen" lt_cv_dlopen_libs="-lsvld"], [AC_CHECK_LIB([dld], [dld_link], [lt_cv_dlopen="dld_link" lt_cv_dlopen_libs="-ldld"]) ]) ]) ]) ]) ]) ;; esac if test "x$lt_cv_dlopen" != xno; then enable_dlopen=yes else enable_dlopen=no fi case $lt_cv_dlopen in dlopen) save_CPPFLAGS="$CPPFLAGS" test "x$ac_cv_header_dlfcn_h" = xyes && CPPFLAGS="$CPPFLAGS -DHAVE_DLFCN_H" save_LDFLAGS="$LDFLAGS" wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $export_dynamic_flag_spec\" save_LIBS="$LIBS" LIBS="$lt_cv_dlopen_libs $LIBS" AC_CACHE_CHECK([whether a program can dlopen itself], lt_cv_dlopen_self, [dnl _LT_TRY_DLOPEN_SELF( lt_cv_dlopen_self=yes, lt_cv_dlopen_self=yes, lt_cv_dlopen_self=no, lt_cv_dlopen_self=cross) ]) if test "x$lt_cv_dlopen_self" = xyes; then wl=$lt_prog_compiler_wl eval LDFLAGS=\"\$LDFLAGS $lt_prog_compiler_static\" AC_CACHE_CHECK([whether a statically linked program can dlopen itself], lt_cv_dlopen_self_static, [dnl _LT_TRY_DLOPEN_SELF( lt_cv_dlopen_self_static=yes, lt_cv_dlopen_self_static=yes, lt_cv_dlopen_self_static=no, lt_cv_dlopen_self_static=cross) ]) fi CPPFLAGS="$save_CPPFLAGS" LDFLAGS="$save_LDFLAGS" LIBS="$save_LIBS" ;; esac case $lt_cv_dlopen_self in yes|no) enable_dlopen_self=$lt_cv_dlopen_self ;; *) enable_dlopen_self=unknown ;; esac case $lt_cv_dlopen_self_static in yes|no) enable_dlopen_self_static=$lt_cv_dlopen_self_static ;; *) enable_dlopen_self_static=unknown ;; esac fi _LT_DECL([dlopen_support], [enable_dlopen], [0], [Whether dlopen is supported]) _LT_DECL([dlopen_self], [enable_dlopen_self], [0], [Whether dlopen of programs is supported]) _LT_DECL([dlopen_self_static], [enable_dlopen_self_static], [0], [Whether dlopen of statically linked programs is supported]) ])# LT_SYS_DLOPEN_SELF # Old name: AU_ALIAS([AC_LIBTOOL_DLOPEN_SELF], [LT_SYS_DLOPEN_SELF]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AC_LIBTOOL_DLOPEN_SELF], []) # _LT_COMPILER_C_O([TAGNAME]) # --------------------------- # Check to see if options -c and -o are simultaneously supported by compiler. # This macro does not hard code the compiler like AC_PROG_CC_C_O. m4_defun([_LT_COMPILER_C_O], [m4_require([_LT_DECL_SED])dnl m4_require([_LT_FILEUTILS_DEFAULTS])dnl m4_require([_LT_TAG_COMPILER])dnl AC_CACHE_CHECK([if $compiler supports -c -o file.$ac_objext], [_LT_TAGVAR(lt_cv_prog_compiler_c_o, $1)], [_LT_TAGVAR(lt_cv_prog_compiler_c_o, $1)=no $RM -r conftest 2>/dev/null mkdir conftest cd conftest mkdir out echo "$lt_simple_compile_test_code" > conftest.$ac_ext lt_compiler_flag="-o out/conftest2.$ac_objext" # Insert the option either (1) after the last *FLAGS variable, or # (2) before a word containing "conftest.", or (3) at the end. # Note that $ac_compile itself does not contain backslashes and begins # with a dollar sign (not a hyphen), so the echo should work correctly. lt_compile=`echo "$ac_compile" | $SED \ -e 's:.*FLAGS}\{0,1\} :&$lt_compiler_flag :; t' \ -e 's: [[^ ]]*conftest\.: $lt_compiler_flag&:; t' \ -e 's:$: $lt_compiler_flag:'` (eval echo "\"\$as_me:$LINENO: $lt_compile\"" >&AS_MESSAGE_LOG_FD) (eval "$lt_compile" 2>out/conftest.err) ac_status=$? cat out/conftest.err >&AS_MESSAGE_LOG_FD echo "$as_me:$LINENO: \$? = $ac_status" >&AS_MESSAGE_LOG_FD if (exit $ac_status) && test -s out/conftest2.$ac_objext then # The compiler can only warn and ignore the option if not recognized # So say no if there are warnings $ECHO "$_lt_compiler_boilerplate" | $SED '/^$/d' > out/conftest.exp $SED '/^$/d; /^ *+/d' out/conftest.err >out/conftest.er2 if test ! -s out/conftest.er2 || diff out/conftest.exp out/conftest.er2 >/dev/null; then _LT_TAGVAR(lt_cv_prog_compiler_c_o, $1)=yes fi fi chmod u+w . 2>&AS_MESSAGE_LOG_FD $RM conftest* # SGI C++ compiler will create directory out/ii_files/ for # template instantiation test -d out/ii_files && $RM out/ii_files/* && rmdir out/ii_files $RM out/* && rmdir out cd .. $RM -r conftest $RM conftest* ]) _LT_TAGDECL([compiler_c_o], [lt_cv_prog_compiler_c_o], [1], [Does compiler simultaneously support -c and -o options?]) ])# _LT_COMPILER_C_O # _LT_COMPILER_FILE_LOCKS([TAGNAME]) # ---------------------------------- # Check to see if we can do hard links to lock some files if needed m4_defun([_LT_COMPILER_FILE_LOCKS], [m4_require([_LT_ENABLE_LOCK])dnl m4_require([_LT_FILEUTILS_DEFAULTS])dnl _LT_COMPILER_C_O([$1]) hard_links="nottested" if test "$_LT_TAGVAR(lt_cv_prog_compiler_c_o, $1)" = no && test "$need_locks" != no; then # do not overwrite the value of need_locks provided by the user AC_MSG_CHECKING([if we can lock with hard links]) hard_links=yes $RM conftest* ln conftest.a conftest.b 2>/dev/null && hard_links=no touch conftest.a ln conftest.a conftest.b 2>&5 || hard_links=no ln conftest.a conftest.b 2>/dev/null && hard_links=no AC_MSG_RESULT([$hard_links]) if test "$hard_links" = no; then AC_MSG_WARN([`$CC' does not support `-c -o', so `make -j' may be unsafe]) need_locks=warn fi else need_locks=no fi _LT_DECL([], [need_locks], [1], [Must we lock files when doing compilation?]) ])# _LT_COMPILER_FILE_LOCKS # _LT_CHECK_OBJDIR # ---------------- m4_defun([_LT_CHECK_OBJDIR], [AC_CACHE_CHECK([for objdir], [lt_cv_objdir], [rm -f .libs 2>/dev/null mkdir .libs 2>/dev/null if test -d .libs; then lt_cv_objdir=.libs else # MS-DOS does not allow filenames that begin with a dot. lt_cv_objdir=_libs fi rmdir .libs 2>/dev/null]) objdir=$lt_cv_objdir _LT_DECL([], [objdir], [0], [The name of the directory that contains temporary libtool files])dnl m4_pattern_allow([LT_OBJDIR])dnl AC_DEFINE_UNQUOTED(LT_OBJDIR, "$lt_cv_objdir/", [Define to the sub-directory in which libtool stores uninstalled libraries.]) ])# _LT_CHECK_OBJDIR # _LT_LINKER_HARDCODE_LIBPATH([TAGNAME]) # -------------------------------------- # Check hardcoding attributes. m4_defun([_LT_LINKER_HARDCODE_LIBPATH], [AC_MSG_CHECKING([how to hardcode library paths into programs]) _LT_TAGVAR(hardcode_action, $1)= if test -n "$_LT_TAGVAR(hardcode_libdir_flag_spec, $1)" || test -n "$_LT_TAGVAR(runpath_var, $1)" || test "X$_LT_TAGVAR(hardcode_automatic, $1)" = "Xyes" ; then # We can hardcode non-existent directories. if test "$_LT_TAGVAR(hardcode_direct, $1)" != no && # If the only mechanism to avoid hardcoding is shlibpath_var, we # have to relink, otherwise we might link with an installed library # when we should be linking with a yet-to-be-installed one ## test "$_LT_TAGVAR(hardcode_shlibpath_var, $1)" != no && test "$_LT_TAGVAR(hardcode_minus_L, $1)" != no; then # Linking always hardcodes the temporary library directory. _LT_TAGVAR(hardcode_action, $1)=relink else # We can link without hardcoding, and we can hardcode nonexisting dirs. _LT_TAGVAR(hardcode_action, $1)=immediate fi else # We cannot hardcode anything, or else we can only hardcode existing # directories. _LT_TAGVAR(hardcode_action, $1)=unsupported fi AC_MSG_RESULT([$_LT_TAGVAR(hardcode_action, $1)]) if test "$_LT_TAGVAR(hardcode_action, $1)" = relink || test "$_LT_TAGVAR(inherit_rpath, $1)" = yes; then # Fast installation is not supported enable_fast_install=no elif test "$shlibpath_overrides_runpath" = yes || test "$enable_shared" = no; then # Fast installation is not necessary enable_fast_install=needless fi _LT_TAGDECL([], [hardcode_action], [0], [How to hardcode a shared library path into an executable]) ])# _LT_LINKER_HARDCODE_LIBPATH # _LT_CMD_STRIPLIB # ---------------- m4_defun([_LT_CMD_STRIPLIB], [m4_require([_LT_DECL_EGREP]) striplib= old_striplib= AC_MSG_CHECKING([whether stripping libraries is possible]) if test -n "$STRIP" && $STRIP -V 2>&1 | $GREP "GNU strip" >/dev/null; then test -z "$old_striplib" && old_striplib="$STRIP --strip-debug" test -z "$striplib" && striplib="$STRIP --strip-unneeded" AC_MSG_RESULT([yes]) else # FIXME - insert some real tests, host_os isn't really good enough case $host_os in darwin*) if test -n "$STRIP" ; then striplib="$STRIP -x" old_striplib="$STRIP -S" AC_MSG_RESULT([yes]) else AC_MSG_RESULT([no]) fi ;; *) AC_MSG_RESULT([no]) ;; esac fi _LT_DECL([], [old_striplib], [1], [Commands to strip libraries]) _LT_DECL([], [striplib], [1]) ])# _LT_CMD_STRIPLIB # _LT_SYS_DYNAMIC_LINKER([TAG]) # ----------------------------- # PORTME Fill in your ld.so characteristics m4_defun([_LT_SYS_DYNAMIC_LINKER], [AC_REQUIRE([AC_CANONICAL_HOST])dnl m4_require([_LT_DECL_EGREP])dnl m4_require([_LT_FILEUTILS_DEFAULTS])dnl m4_require([_LT_DECL_OBJDUMP])dnl m4_require([_LT_DECL_SED])dnl m4_require([_LT_CHECK_SHELL_FEATURES])dnl AC_MSG_CHECKING([dynamic linker characteristics]) m4_if([$1], [], [ if test "$GCC" = yes; then case $host_os in darwin*) lt_awk_arg="/^libraries:/,/LR/" ;; *) lt_awk_arg="/^libraries:/" ;; esac case $host_os in mingw* | cegcc*) lt_sed_strip_eq="s,=\([[A-Za-z]]:\),\1,g" ;; *) lt_sed_strip_eq="s,=/,/,g" ;; esac lt_search_path_spec=`$CC -print-search-dirs | awk $lt_awk_arg | $SED -e "s/^libraries://" -e $lt_sed_strip_eq` case $lt_search_path_spec in *\;*) # if the path contains ";" then we assume it to be the separator # otherwise default to the standard path separator (i.e. ":") - it is # assumed that no part of a normal pathname contains ";" but that should # okay in the real world where ";" in dirpaths is itself problematic. lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED 's/;/ /g'` ;; *) lt_search_path_spec=`$ECHO "$lt_search_path_spec" | $SED "s/$PATH_SEPARATOR/ /g"` ;; esac # Ok, now we have the path, separated by spaces, we can step through it # and add multilib dir if necessary. lt_tmp_lt_search_path_spec= lt_multi_os_dir=`$CC $CPPFLAGS $CFLAGS $LDFLAGS -print-multi-os-directory 2>/dev/null` for lt_sys_path in $lt_search_path_spec; do if test -d "$lt_sys_path/$lt_multi_os_dir"; then lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path/$lt_multi_os_dir" else test -d "$lt_sys_path" && \ lt_tmp_lt_search_path_spec="$lt_tmp_lt_search_path_spec $lt_sys_path" fi done lt_search_path_spec=`$ECHO "$lt_tmp_lt_search_path_spec" | awk ' BEGIN {RS=" "; FS="/|\n";} { lt_foo=""; lt_count=0; for (lt_i = NF; lt_i > 0; lt_i--) { if ($lt_i != "" && $lt_i != ".") { if ($lt_i == "..") { lt_count++; } else { if (lt_count == 0) { lt_foo="/" $lt_i lt_foo; } else { lt_count--; } } } } if (lt_foo != "") { lt_freq[[lt_foo]]++; } if (lt_freq[[lt_foo]] == 1) { print lt_foo; } }'` # AWK program above erroneously prepends '/' to C:/dos/paths # for these hosts. case $host_os in mingw* | cegcc*) lt_search_path_spec=`$ECHO "$lt_search_path_spec" |\ $SED 's,/\([[A-Za-z]]:\),\1,g'` ;; esac sys_lib_search_path_spec=`$ECHO "$lt_search_path_spec" | $lt_NL2SP` else sys_lib_search_path_spec="/lib /usr/lib /usr/local/lib" fi]) library_names_spec= libname_spec='lib$name' soname_spec= shrext_cmds=".so" postinstall_cmds= postuninstall_cmds= finish_cmds= finish_eval= shlibpath_var= shlibpath_overrides_runpath=unknown version_type=none dynamic_linker="$host_os ld.so" sys_lib_dlsearch_path_spec="/lib /usr/lib" need_lib_prefix=unknown hardcode_into_libs=no # when you set need_version to no, make sure it does not cause -set_version # flags to be left without arguments need_version=unknown case $host_os in aix3*) version_type=linux library_names_spec='${libname}${release}${shared_ext}$versuffix $libname.a' shlibpath_var=LIBPATH # AIX 3 has no versioning support, so we append a major version to the name. soname_spec='${libname}${release}${shared_ext}$major' ;; aix[[4-9]]*) version_type=linux need_lib_prefix=no need_version=no hardcode_into_libs=yes if test "$host_cpu" = ia64; then # AIX 5 supports IA64 library_names_spec='${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext}$versuffix $libname${shared_ext}' shlibpath_var=LD_LIBRARY_PATH else # With GCC up to 2.95.x, collect2 would create an import file # for dependence libraries. The import file would start with # the line `#! .'. This would cause the generated library to # depend on `.', always an invalid library. This was fixed in # development snapshots of GCC prior to 3.0. case $host_os in aix4 | aix4.[[01]] | aix4.[[01]].*) if { echo '#if __GNUC__ > 2 || (__GNUC__ == 2 && __GNUC_MINOR__ >= 97)' echo ' yes ' echo '#endif'; } | ${CC} -E - | $GREP yes > /dev/null; then : else can_build_shared=no fi ;; esac # AIX (on Power*) has no versioning support, so currently we can not hardcode correct # soname into executable. Probably we can add versioning support to # collect2, so additional links can be useful in future. if test "$aix_use_runtimelinking" = yes; then # If using run time linking (on AIX 4.2 or later) use lib.so # instead of lib.a to let people know that these are not # typical AIX shared libraries. library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' else # We preserve .a as extension for shared libraries through AIX4.2 # and later when we are not doing run time linking. library_names_spec='${libname}${release}.a $libname.a' soname_spec='${libname}${release}${shared_ext}$major' fi shlibpath_var=LIBPATH fi ;; amigaos*) case $host_cpu in powerpc) # Since July 2007 AmigaOS4 officially supports .so libraries. # When compiling the executable, add -use-dynld -Lsobjs: to the compileline. library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' ;; m68k) library_names_spec='$libname.ixlibrary $libname.a' # Create ${libname}_ixlibrary.a entries in /sys/libs. finish_eval='for lib in `ls $libdir/*.ixlibrary 2>/dev/null`; do libname=`func_echo_all "$lib" | $SED '\''s%^.*/\([[^/]]*\)\.ixlibrary$%\1%'\''`; test $RM /sys/libs/${libname}_ixlibrary.a; $show "cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a"; cd /sys/libs && $LN_S $lib ${libname}_ixlibrary.a || exit 1; done' ;; esac ;; beos*) library_names_spec='${libname}${shared_ext}' dynamic_linker="$host_os ld.so" shlibpath_var=LIBRARY_PATH ;; bsdi[[45]]*) version_type=linux need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' finish_cmds='PATH="\$PATH:/sbin" ldconfig $libdir' shlibpath_var=LD_LIBRARY_PATH sys_lib_search_path_spec="/shlib /usr/lib /usr/X11/lib /usr/contrib/lib /lib /usr/local/lib" sys_lib_dlsearch_path_spec="/shlib /usr/lib /usr/local/lib" # the default ld.so.conf also contains /usr/contrib/lib and # /usr/X11R6/lib (/usr/X11 is a link to /usr/X11R6), but let us allow # libtool to hard-code these into programs ;; cygwin* | mingw* | pw32* | cegcc*) version_type=windows shrext_cmds=".dll" need_version=no need_lib_prefix=no case $GCC,$cc_basename in yes,*) # gcc library_names_spec='$libname.dll.a' # DLL is installed to $(libdir)/../bin by postinstall_cmds postinstall_cmds='base_file=`basename \${file}`~ dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~ dldir=$destdir/`dirname \$dlpath`~ test -d \$dldir || mkdir -p \$dldir~ $install_prog $dir/$dlname \$dldir/$dlname~ chmod a+x \$dldir/$dlname~ if test -n '\''$stripme'\'' && test -n '\''$striplib'\''; then eval '\''$striplib \$dldir/$dlname'\'' || exit \$?; fi' postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~ dlpath=$dir/\$dldll~ $RM \$dlpath' shlibpath_overrides_runpath=yes case $host_os in cygwin*) # Cygwin DLLs use 'cyg' prefix rather than 'lib' soname_spec='`echo ${libname} | sed -e 's/^lib/cyg/'``echo ${release} | $SED -e 's/[[.]]/-/g'`${versuffix}${shared_ext}' m4_if([$1], [],[ sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/lib/w32api"]) ;; mingw* | cegcc*) # MinGW DLLs use traditional 'lib' prefix soname_spec='${libname}`echo ${release} | $SED -e 's/[[.]]/-/g'`${versuffix}${shared_ext}' ;; pw32*) # pw32 DLLs use 'pw' prefix rather than 'lib' library_names_spec='`echo ${libname} | sed -e 's/^lib/pw/'``echo ${release} | $SED -e 's/[[.]]/-/g'`${versuffix}${shared_ext}' ;; esac dynamic_linker='Win32 ld.exe' ;; *,cl*) # Native MSVC libname_spec='$name' soname_spec='${libname}`echo ${release} | $SED -e 's/[[.]]/-/g'`${versuffix}${shared_ext}' library_names_spec='${libname}.dll.lib' case $build_os in mingw*) sys_lib_search_path_spec= lt_save_ifs=$IFS IFS=';' for lt_path in $LIB do IFS=$lt_save_ifs # Let DOS variable expansion print the short 8.3 style file name. lt_path=`cd "$lt_path" 2>/dev/null && cmd //C "for %i in (".") do @echo %~si"` sys_lib_search_path_spec="$sys_lib_search_path_spec $lt_path" done IFS=$lt_save_ifs # Convert to MSYS style. sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | sed -e 's|\\\\|/|g' -e 's| \\([[a-zA-Z]]\\):| /\\1|g' -e 's|^ ||'` ;; cygwin*) # Convert to unix form, then to dos form, then back to unix form # but this time dos style (no spaces!) so that the unix form looks # like /cygdrive/c/PROGRA~1:/cygdr... sys_lib_search_path_spec=`cygpath --path --unix "$LIB"` sys_lib_search_path_spec=`cygpath --path --dos "$sys_lib_search_path_spec" 2>/dev/null` sys_lib_search_path_spec=`cygpath --path --unix "$sys_lib_search_path_spec" | $SED -e "s/$PATH_SEPARATOR/ /g"` ;; *) sys_lib_search_path_spec="$LIB" if $ECHO "$sys_lib_search_path_spec" | [$GREP ';[c-zC-Z]:/' >/dev/null]; then # It is most probably a Windows format PATH. sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED -e 's/;/ /g'` else sys_lib_search_path_spec=`$ECHO "$sys_lib_search_path_spec" | $SED -e "s/$PATH_SEPARATOR/ /g"` fi # FIXME: find the short name or the path components, as spaces are # common. (e.g. "Program Files" -> "PROGRA~1") ;; esac # DLL is installed to $(libdir)/../bin by postinstall_cmds postinstall_cmds='base_file=`basename \${file}`~ dlpath=`$SHELL 2>&1 -c '\''. $dir/'\''\${base_file}'\''i; echo \$dlname'\''`~ dldir=$destdir/`dirname \$dlpath`~ test -d \$dldir || mkdir -p \$dldir~ $install_prog $dir/$dlname \$dldir/$dlname' postuninstall_cmds='dldll=`$SHELL 2>&1 -c '\''. $file; echo \$dlname'\''`~ dlpath=$dir/\$dldll~ $RM \$dlpath' shlibpath_overrides_runpath=yes dynamic_linker='Win32 link.exe' ;; *) # Assume MSVC wrapper library_names_spec='${libname}`echo ${release} | $SED -e 's/[[.]]/-/g'`${versuffix}${shared_ext} $libname.lib' dynamic_linker='Win32 ld.exe' ;; esac # FIXME: first we should search . and the directory the executable is in shlibpath_var=PATH ;; darwin* | rhapsody*) dynamic_linker="$host_os dyld" version_type=darwin need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${major}$shared_ext ${libname}$shared_ext' soname_spec='${libname}${release}${major}$shared_ext' shlibpath_overrides_runpath=yes shlibpath_var=DYLD_LIBRARY_PATH shrext_cmds='`test .$module = .yes && echo .so || echo .dylib`' m4_if([$1], [],[ sys_lib_search_path_spec="$sys_lib_search_path_spec /usr/local/lib"]) sys_lib_dlsearch_path_spec='/usr/local/lib /lib /usr/lib' ;; dgux*) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname$shared_ext' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH ;; freebsd1*) dynamic_linker=no ;; freebsd* | dragonfly*) # DragonFly does not have aout. When/if they implement a new # versioning mechanism, adjust this. if test -x /usr/bin/objformat; then objformat=`/usr/bin/objformat` else case $host_os in freebsd[[123]]*) objformat=aout ;; *) objformat=elf ;; esac fi version_type=freebsd-$objformat case $version_type in freebsd-elf*) library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}' need_version=no need_lib_prefix=no ;; freebsd-*) library_names_spec='${libname}${release}${shared_ext}$versuffix $libname${shared_ext}$versuffix' need_version=yes ;; esac shlibpath_var=LD_LIBRARY_PATH case $host_os in freebsd2*) shlibpath_overrides_runpath=yes ;; freebsd3.[[01]]* | freebsdelf3.[[01]]*) shlibpath_overrides_runpath=yes hardcode_into_libs=yes ;; freebsd3.[[2-9]]* | freebsdelf3.[[2-9]]* | \ freebsd4.[[0-5]] | freebsdelf4.[[0-5]] | freebsd4.1.1 | freebsdelf4.1.1) shlibpath_overrides_runpath=no hardcode_into_libs=yes ;; *) # from 4.6 on, and DragonFly shlibpath_overrides_runpath=yes hardcode_into_libs=yes ;; esac ;; gnu*) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=no hardcode_into_libs=yes ;; haiku*) version_type=linux need_lib_prefix=no need_version=no dynamic_linker="$host_os runtime_loader" library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}${major} ${libname}${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LIBRARY_PATH shlibpath_overrides_runpath=yes sys_lib_dlsearch_path_spec='/boot/home/config/lib /boot/common/lib /boot/system/lib' hardcode_into_libs=yes ;; hpux9* | hpux10* | hpux11*) # Give a soname corresponding to the major version so that dld.sl refuses to # link against other versions. version_type=sunos need_lib_prefix=no need_version=no case $host_cpu in ia64*) shrext_cmds='.so' hardcode_into_libs=yes dynamic_linker="$host_os dld.so" shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=yes # Unless +noenvvar is specified. library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' if test "X$HPUX_IA64_MODE" = X32; then sys_lib_search_path_spec="/usr/lib/hpux32 /usr/local/lib/hpux32 /usr/local/lib" else sys_lib_search_path_spec="/usr/lib/hpux64 /usr/local/lib/hpux64" fi sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec ;; hppa*64*) shrext_cmds='.sl' hardcode_into_libs=yes dynamic_linker="$host_os dld.sl" shlibpath_var=LD_LIBRARY_PATH # How should we handle SHLIB_PATH shlibpath_overrides_runpath=yes # Unless +noenvvar is specified. library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' sys_lib_search_path_spec="/usr/lib/pa20_64 /usr/ccs/lib/pa20_64" sys_lib_dlsearch_path_spec=$sys_lib_search_path_spec ;; *) shrext_cmds='.sl' dynamic_linker="$host_os dld.sl" shlibpath_var=SHLIB_PATH shlibpath_overrides_runpath=no # +s is required to enable SHLIB_PATH library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' ;; esac # HP-UX runs *really* slowly unless shared libraries are mode 555, ... postinstall_cmds='chmod 555 $lib' # or fails outright, so override atomically: install_override_mode=555 ;; interix[[3-9]]*) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' dynamic_linker='Interix 3.x ld.so.1 (PE, like ELF)' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=no hardcode_into_libs=yes ;; irix5* | irix6* | nonstopux*) case $host_os in nonstopux*) version_type=nonstopux ;; *) if test "$lt_cv_prog_gnu_ld" = yes; then version_type=linux else version_type=irix fi ;; esac need_lib_prefix=no need_version=no soname_spec='${libname}${release}${shared_ext}$major' library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${release}${shared_ext} $libname${shared_ext}' case $host_os in irix5* | nonstopux*) libsuff= shlibsuff= ;; *) case $LD in # libtool.m4 will add one of these switches to LD *-32|*"-32 "|*-melf32bsmip|*"-melf32bsmip ") libsuff= shlibsuff= libmagic=32-bit;; *-n32|*"-n32 "|*-melf32bmipn32|*"-melf32bmipn32 ") libsuff=32 shlibsuff=N32 libmagic=N32;; *-64|*"-64 "|*-melf64bmip|*"-melf64bmip ") libsuff=64 shlibsuff=64 libmagic=64-bit;; *) libsuff= shlibsuff= libmagic=never-match;; esac ;; esac shlibpath_var=LD_LIBRARY${shlibsuff}_PATH shlibpath_overrides_runpath=no sys_lib_search_path_spec="/usr/lib${libsuff} /lib${libsuff} /usr/local/lib${libsuff}" sys_lib_dlsearch_path_spec="/usr/lib${libsuff} /lib${libsuff}" hardcode_into_libs=yes ;; # No shared lib support for Linux oldld, aout, or coff. linux*oldld* | linux*aout* | linux*coff*) dynamic_linker=no ;; # This must be Linux ELF. linux* | k*bsd*-gnu | kopensolaris*-gnu) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' finish_cmds='PATH="\$PATH:/sbin" ldconfig -n $libdir' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=no # Some binutils ld are patched to set DT_RUNPATH AC_CACHE_VAL([lt_cv_shlibpath_overrides_runpath], [lt_cv_shlibpath_overrides_runpath=no save_LDFLAGS=$LDFLAGS save_libdir=$libdir eval "libdir=/foo; wl=\"$_LT_TAGVAR(lt_prog_compiler_wl, $1)\"; \ LDFLAGS=\"\$LDFLAGS $_LT_TAGVAR(hardcode_libdir_flag_spec, $1)\"" AC_LINK_IFELSE([AC_LANG_PROGRAM([],[])], [AS_IF([ ($OBJDUMP -p conftest$ac_exeext) 2>/dev/null | grep "RUNPATH.*$libdir" >/dev/null], [lt_cv_shlibpath_overrides_runpath=yes])]) LDFLAGS=$save_LDFLAGS libdir=$save_libdir ]) shlibpath_overrides_runpath=$lt_cv_shlibpath_overrides_runpath # This implies no fast_install, which is unacceptable. # Some rework will be needed to allow for fast_install # before this can be enabled. hardcode_into_libs=yes # Append ld.so.conf contents to the search path if test -f /etc/ld.so.conf; then lt_ld_extra=`awk '/^include / { system(sprintf("cd /etc; cat %s 2>/dev/null", \[$]2)); skip = 1; } { if (!skip) print \[$]0; skip = 0; }' < /etc/ld.so.conf | $SED -e 's/#.*//;/^[ ]*hwcap[ ]/d;s/[:, ]/ /g;s/=[^=]*$//;s/=[^= ]* / /g;s/"//g;/^$/d' | tr '\n' ' '` sys_lib_dlsearch_path_spec="/lib /usr/lib $lt_ld_extra" fi # We used to test for /lib/ld.so.1 and disable shared libraries on # powerpc, because MkLinux only supported shared libraries with the # GNU dynamic linker. Since this was broken with cross compilers, # most powerpc-linux boxes support dynamic linking these days and # people can always --disable-shared, the test was removed, and we # assume the GNU/Linux dynamic linker is in use. dynamic_linker='GNU/Linux ld.so' ;; netbsdelf*-gnu) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=no hardcode_into_libs=yes dynamic_linker='NetBSD ld.elf_so' ;; netbsd*) version_type=sunos need_lib_prefix=no need_version=no if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir' dynamic_linker='NetBSD (a.out) ld.so' else library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major ${libname}${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' dynamic_linker='NetBSD ld.elf_so' fi shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=yes hardcode_into_libs=yes ;; newsos6) version_type=linux library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=yes ;; *nto* | *qnx*) version_type=qnx need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=no hardcode_into_libs=yes dynamic_linker='ldqnx.so' ;; openbsd*) version_type=sunos sys_lib_dlsearch_path_spec="/usr/lib" need_lib_prefix=no # Some older versions of OpenBSD (3.3 at least) *do* need versioned libs. case $host_os in openbsd3.3 | openbsd3.3.*) need_version=yes ;; *) need_version=no ;; esac library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' finish_cmds='PATH="\$PATH:/sbin" ldconfig -m $libdir' shlibpath_var=LD_LIBRARY_PATH if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then case $host_os in openbsd2.[[89]] | openbsd2.[[89]].*) shlibpath_overrides_runpath=no ;; *) shlibpath_overrides_runpath=yes ;; esac else shlibpath_overrides_runpath=yes fi ;; os2*) libname_spec='$name' shrext_cmds=".dll" need_lib_prefix=no library_names_spec='$libname${shared_ext} $libname.a' dynamic_linker='OS/2 ld.exe' shlibpath_var=LIBPATH ;; osf3* | osf4* | osf5*) version_type=osf need_lib_prefix=no need_version=no soname_spec='${libname}${release}${shared_ext}$major' library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' shlibpath_var=LD_LIBRARY_PATH sys_lib_search_path_spec="/usr/shlib /usr/ccs/lib /usr/lib/cmplrs/cc /usr/lib /usr/local/lib /var/shlib" sys_lib_dlsearch_path_spec="$sys_lib_search_path_spec" ;; rdos*) dynamic_linker=no ;; solaris*) version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=yes hardcode_into_libs=yes # ldd complains unless libraries are executable postinstall_cmds='chmod +x $lib' ;; sunos4*) version_type=sunos library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${shared_ext}$versuffix' finish_cmds='PATH="\$PATH:/usr/etc" ldconfig $libdir' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=yes if test "$with_gnu_ld" = yes; then need_lib_prefix=no fi need_version=yes ;; sysv4 | sysv4.3*) version_type=linux library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH case $host_vendor in sni) shlibpath_overrides_runpath=no need_lib_prefix=no runpath_var=LD_RUN_PATH ;; siemens) need_lib_prefix=no ;; motorola) need_lib_prefix=no need_version=no shlibpath_overrides_runpath=no sys_lib_search_path_spec='/lib /usr/lib /usr/ccs/lib' ;; esac ;; sysv4*MP*) if test -d /usr/nec ;then version_type=linux library_names_spec='$libname${shared_ext}.$versuffix $libname${shared_ext}.$major $libname${shared_ext}' soname_spec='$libname${shared_ext}.$major' shlibpath_var=LD_LIBRARY_PATH fi ;; sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*) version_type=freebsd-elf need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext} $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=yes hardcode_into_libs=yes if test "$with_gnu_ld" = yes; then sys_lib_search_path_spec='/usr/local/lib /usr/gnu/lib /usr/ccs/lib /usr/lib /lib' else sys_lib_search_path_spec='/usr/ccs/lib /usr/lib' case $host_os in sco3.2v5*) sys_lib_search_path_spec="$sys_lib_search_path_spec /lib" ;; esac fi sys_lib_dlsearch_path_spec='/usr/lib' ;; tpf*) # TPF is a cross-target only. Preferred cross-host = GNU/Linux. version_type=linux need_lib_prefix=no need_version=no library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' shlibpath_var=LD_LIBRARY_PATH shlibpath_overrides_runpath=no hardcode_into_libs=yes ;; uts4*) version_type=linux library_names_spec='${libname}${release}${shared_ext}$versuffix ${libname}${release}${shared_ext}$major $libname${shared_ext}' soname_spec='${libname}${release}${shared_ext}$major' shlibpath_var=LD_LIBRARY_PATH ;; *) dynamic_linker=no ;; esac AC_MSG_RESULT([$dynamic_linker]) test "$dynamic_linker" = no && can_build_shared=no variables_saved_for_relink="PATH $shlibpath_var $runpath_var" if test "$GCC" = yes; then variables_saved_for_relink="$variables_saved_for_relink GCC_EXEC_PREFIX COMPILER_PATH LIBRARY_PATH" fi if test "${lt_cv_sys_lib_search_path_spec+set}" = set; then sys_lib_search_path_spec="$lt_cv_sys_lib_search_path_spec" fi if test "${lt_cv_sys_lib_dlsearch_path_spec+set}" = set; then sys_lib_dlsearch_path_spec="$lt_cv_sys_lib_dlsearch_path_spec" fi _LT_DECL([], [variables_saved_for_relink], [1], [Variables whose values should be saved in libtool wrapper scripts and restored at link time]) _LT_DECL([], [need_lib_prefix], [0], [Do we need the "lib" prefix for modules?]) _LT_DECL([], [need_version], [0], [Do we need a version for libraries?]) _LT_DECL([], [version_type], [0], [Library versioning type]) _LT_DECL([], [runpath_var], [0], [Shared library runtime path variable]) _LT_DECL([], [shlibpath_var], [0],[Shared library path variable]) _LT_DECL([], [shlibpath_overrides_runpath], [0], [Is shlibpath searched before the hard-coded library search path?]) _LT_DECL([], [libname_spec], [1], [Format of library name prefix]) _LT_DECL([], [library_names_spec], [1], [[List of archive names. First name is the real one, the rest are links. The last name is the one that the linker finds with -lNAME]]) _LT_DECL([], [soname_spec], [1], [[The coded name of the library, if different from the real name]]) _LT_DECL([], [install_override_mode], [1], [Permission mode override for installation of shared libraries]) _LT_DECL([], [postinstall_cmds], [2], [Command to use after installation of a shared archive]) _LT_DECL([], [postuninstall_cmds], [2], [Command to use after uninstallation of a shared archive]) _LT_DECL([], [finish_cmds], [2], [Commands used to finish a libtool library installation in a directory]) _LT_DECL([], [finish_eval], [1], [[As "finish_cmds", except a single script fragment to be evaled but not shown]]) _LT_DECL([], [hardcode_into_libs], [0], [Whether we should hardcode library paths into libraries]) _LT_DECL([], [sys_lib_search_path_spec], [2], [Compile-time system search path for libraries]) _LT_DECL([], [sys_lib_dlsearch_path_spec], [2], [Run-time system search path for libraries]) ])# _LT_SYS_DYNAMIC_LINKER # _LT_PATH_TOOL_PREFIX(TOOL) # -------------------------- # find a file program which can recognize shared library AC_DEFUN([_LT_PATH_TOOL_PREFIX], [m4_require([_LT_DECL_EGREP])dnl AC_MSG_CHECKING([for $1]) AC_CACHE_VAL(lt_cv_path_MAGIC_CMD, [case $MAGIC_CMD in [[\\/*] | ?:[\\/]*]) lt_cv_path_MAGIC_CMD="$MAGIC_CMD" # Let the user override the test with a path. ;; *) lt_save_MAGIC_CMD="$MAGIC_CMD" lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR dnl $ac_dummy forces splitting on constant user-supplied paths. dnl POSIX.2 word splitting is done only on the output of word expansions, dnl not every word. This closes a longstanding sh security hole. ac_dummy="m4_if([$2], , $PATH, [$2])" for ac_dir in $ac_dummy; do IFS="$lt_save_ifs" test -z "$ac_dir" && ac_dir=. if test -f $ac_dir/$1; then lt_cv_path_MAGIC_CMD="$ac_dir/$1" if test -n "$file_magic_test_file"; then case $deplibs_check_method in "file_magic "*) file_magic_regex=`expr "$deplibs_check_method" : "file_magic \(.*\)"` MAGIC_CMD="$lt_cv_path_MAGIC_CMD" if eval $file_magic_cmd \$file_magic_test_file 2> /dev/null | $EGREP "$file_magic_regex" > /dev/null; then : else cat <<_LT_EOF 1>&2 *** Warning: the command libtool uses to detect shared libraries, *** $file_magic_cmd, produces output that libtool cannot recognize. *** The result is that libtool may fail to recognize shared libraries *** as such. This will affect the creation of libtool libraries that *** depend on shared libraries, but programs linked with such libtool *** libraries will work regardless of this problem. Nevertheless, you *** may want to report the problem to your system manager and/or to *** bug-libtool@gnu.org _LT_EOF fi ;; esac fi break fi done IFS="$lt_save_ifs" MAGIC_CMD="$lt_save_MAGIC_CMD" ;; esac]) MAGIC_CMD="$lt_cv_path_MAGIC_CMD" if test -n "$MAGIC_CMD"; then AC_MSG_RESULT($MAGIC_CMD) else AC_MSG_RESULT(no) fi _LT_DECL([], [MAGIC_CMD], [0], [Used to examine libraries when file_magic_cmd begins with "file"])dnl ])# _LT_PATH_TOOL_PREFIX # Old name: AU_ALIAS([AC_PATH_TOOL_PREFIX], [_LT_PATH_TOOL_PREFIX]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AC_PATH_TOOL_PREFIX], []) # _LT_PATH_MAGIC # -------------- # find a file program which can recognize a shared library m4_defun([_LT_PATH_MAGIC], [_LT_PATH_TOOL_PREFIX(${ac_tool_prefix}file, /usr/bin$PATH_SEPARATOR$PATH) if test -z "$lt_cv_path_MAGIC_CMD"; then if test -n "$ac_tool_prefix"; then _LT_PATH_TOOL_PREFIX(file, /usr/bin$PATH_SEPARATOR$PATH) else MAGIC_CMD=: fi fi ])# _LT_PATH_MAGIC # LT_PATH_LD # ---------- # find the pathname to the GNU or non-GNU linker AC_DEFUN([LT_PATH_LD], [AC_REQUIRE([AC_PROG_CC])dnl AC_REQUIRE([AC_CANONICAL_HOST])dnl AC_REQUIRE([AC_CANONICAL_BUILD])dnl m4_require([_LT_DECL_SED])dnl m4_require([_LT_DECL_EGREP])dnl m4_require([_LT_PROG_ECHO_BACKSLASH])dnl AC_ARG_WITH([gnu-ld], [AS_HELP_STRING([--with-gnu-ld], [assume the C compiler uses GNU ld @<:@default=no@:>@])], [test "$withval" = no || with_gnu_ld=yes], [with_gnu_ld=no])dnl ac_prog=ld if test "$GCC" = yes; then # Check if gcc -print-prog-name=ld gives a path. AC_MSG_CHECKING([for ld used by $CC]) case $host in *-*-mingw*) # gcc leaves a trailing carriage return which upsets mingw ac_prog=`($CC -print-prog-name=ld) 2>&5 | tr -d '\015'` ;; *) ac_prog=`($CC -print-prog-name=ld) 2>&5` ;; esac case $ac_prog in # Accept absolute paths. [[\\/]]* | ?:[[\\/]]*) re_direlt='/[[^/]][[^/]]*/\.\./' # Canonicalize the pathname of ld ac_prog=`$ECHO "$ac_prog"| $SED 's%\\\\%/%g'` while $ECHO "$ac_prog" | $GREP "$re_direlt" > /dev/null 2>&1; do ac_prog=`$ECHO $ac_prog| $SED "s%$re_direlt%/%"` done test -z "$LD" && LD="$ac_prog" ;; "") # If it fails, then pretend we aren't using GCC. ac_prog=ld ;; *) # If it is relative, then search for the first ld in PATH. with_gnu_ld=unknown ;; esac elif test "$with_gnu_ld" = yes; then AC_MSG_CHECKING([for GNU ld]) else AC_MSG_CHECKING([for non-GNU ld]) fi AC_CACHE_VAL(lt_cv_path_LD, [if test -z "$LD"; then lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR for ac_dir in $PATH; do IFS="$lt_save_ifs" test -z "$ac_dir" && ac_dir=. if test -f "$ac_dir/$ac_prog" || test -f "$ac_dir/$ac_prog$ac_exeext"; then lt_cv_path_LD="$ac_dir/$ac_prog" # Check to see if the program is GNU ld. I'd rather use --version, # but apparently some variants of GNU ld only accept -v. # Break only if it was the GNU/non-GNU ld that we prefer. case `"$lt_cv_path_LD" -v 2>&1 &1 /dev/null 2>&1; then lt_cv_deplibs_check_method='file_magic ^x86 archive import|^x86 DLL' lt_cv_file_magic_cmd='func_win32_libid' else # Keep this pattern in sync with the one in func_win32_libid. lt_cv_deplibs_check_method='file_magic file format (pei*-i386(.*architecture: i386)?|pe-arm-wince|pe-x86-64)' lt_cv_file_magic_cmd='$OBJDUMP -f' fi ;; cegcc*) # use the weaker test based on 'objdump'. See mingw*. lt_cv_deplibs_check_method='file_magic file format pe-arm-.*little(.*architecture: arm)?' lt_cv_file_magic_cmd='$OBJDUMP -f' ;; darwin* | rhapsody*) lt_cv_deplibs_check_method=pass_all ;; freebsd* | dragonfly*) if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then case $host_cpu in i*86 ) # Not sure whether the presence of OpenBSD here was a mistake. # Let's accept both of them until this is cleared up. lt_cv_deplibs_check_method='file_magic (FreeBSD|OpenBSD|DragonFly)/i[[3-9]]86 (compact )?demand paged shared library' lt_cv_file_magic_cmd=/usr/bin/file lt_cv_file_magic_test_file=`echo /usr/lib/libc.so.*` ;; esac else lt_cv_deplibs_check_method=pass_all fi ;; gnu*) lt_cv_deplibs_check_method=pass_all ;; haiku*) lt_cv_deplibs_check_method=pass_all ;; hpux10.20* | hpux11*) lt_cv_file_magic_cmd=/usr/bin/file case $host_cpu in ia64*) lt_cv_deplibs_check_method='file_magic (s[[0-9]][[0-9]][[0-9]]|ELF-[[0-9]][[0-9]]) shared object file - IA64' lt_cv_file_magic_test_file=/usr/lib/hpux32/libc.so ;; hppa*64*) [lt_cv_deplibs_check_method='file_magic (s[0-9][0-9][0-9]|ELF[ -][0-9][0-9])(-bit)?( [LM]SB)? shared object( file)?[, -]* PA-RISC [0-9]\.[0-9]'] lt_cv_file_magic_test_file=/usr/lib/pa20_64/libc.sl ;; *) lt_cv_deplibs_check_method='file_magic (s[[0-9]][[0-9]][[0-9]]|PA-RISC[[0-9]]\.[[0-9]]) shared library' lt_cv_file_magic_test_file=/usr/lib/libc.sl ;; esac ;; interix[[3-9]]*) # PIC code is broken on Interix 3.x, that's why |\.a not |_pic\.a here lt_cv_deplibs_check_method='match_pattern /lib[[^/]]+(\.so|\.a)$' ;; irix5* | irix6* | nonstopux*) case $LD in *-32|*"-32 ") libmagic=32-bit;; *-n32|*"-n32 ") libmagic=N32;; *-64|*"-64 ") libmagic=64-bit;; *) libmagic=never-match;; esac lt_cv_deplibs_check_method=pass_all ;; # This must be Linux ELF. linux* | k*bsd*-gnu | kopensolaris*-gnu) lt_cv_deplibs_check_method=pass_all ;; netbsd* | netbsdelf*-gnu) if echo __ELF__ | $CC -E - | $GREP __ELF__ > /dev/null; then lt_cv_deplibs_check_method='match_pattern /lib[[^/]]+(\.so\.[[0-9]]+\.[[0-9]]+|_pic\.a)$' else lt_cv_deplibs_check_method='match_pattern /lib[[^/]]+(\.so|_pic\.a)$' fi ;; newos6*) lt_cv_deplibs_check_method='file_magic ELF [[0-9]][[0-9]]*-bit [[ML]]SB (executable|dynamic lib)' lt_cv_file_magic_cmd=/usr/bin/file lt_cv_file_magic_test_file=/usr/lib/libnls.so ;; *nto* | *qnx*) lt_cv_deplibs_check_method=pass_all ;; openbsd*) if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then lt_cv_deplibs_check_method='match_pattern /lib[[^/]]+(\.so\.[[0-9]]+\.[[0-9]]+|\.so|_pic\.a)$' else lt_cv_deplibs_check_method='match_pattern /lib[[^/]]+(\.so\.[[0-9]]+\.[[0-9]]+|_pic\.a)$' fi ;; osf3* | osf4* | osf5*) lt_cv_deplibs_check_method=pass_all ;; rdos*) lt_cv_deplibs_check_method=pass_all ;; solaris*) lt_cv_deplibs_check_method=pass_all ;; sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX* | sysv4*uw2*) lt_cv_deplibs_check_method=pass_all ;; sysv4 | sysv4.3*) case $host_vendor in motorola) lt_cv_deplibs_check_method='file_magic ELF [[0-9]][[0-9]]*-bit [[ML]]SB (shared object|dynamic lib) M[[0-9]][[0-9]]* Version [[0-9]]' lt_cv_file_magic_test_file=`echo /usr/lib/libc.so*` ;; ncr) lt_cv_deplibs_check_method=pass_all ;; sequent) lt_cv_file_magic_cmd='/bin/file' lt_cv_deplibs_check_method='file_magic ELF [[0-9]][[0-9]]*-bit [[LM]]SB (shared object|dynamic lib )' ;; sni) lt_cv_file_magic_cmd='/bin/file' lt_cv_deplibs_check_method="file_magic ELF [[0-9]][[0-9]]*-bit [[LM]]SB dynamic lib" lt_cv_file_magic_test_file=/lib/libc.so ;; siemens) lt_cv_deplibs_check_method=pass_all ;; pc) lt_cv_deplibs_check_method=pass_all ;; esac ;; tpf*) lt_cv_deplibs_check_method=pass_all ;; esac ]) file_magic_glob= want_nocaseglob=no if test "$build" = "$host"; then case $host_os in mingw* | pw32*) if ( shopt | grep nocaseglob ) >/dev/null 2>&1; then want_nocaseglob=yes else file_magic_glob=`echo aAbBcCdDeEfFgGhHiIjJkKlLmMnNoOpPqQrRsStTuUvVwWxXyYzZ | $SED -e "s/\(..\)/s\/[[\1]]\/[[\1]]\/g;/g"` fi ;; esac fi file_magic_cmd=$lt_cv_file_magic_cmd deplibs_check_method=$lt_cv_deplibs_check_method test -z "$deplibs_check_method" && deplibs_check_method=unknown _LT_DECL([], [deplibs_check_method], [1], [Method to check whether dependent libraries are shared objects]) _LT_DECL([], [file_magic_cmd], [1], [Command to use when deplibs_check_method = "file_magic"]) _LT_DECL([], [file_magic_glob], [1], [How to find potential files when deplibs_check_method = "file_magic"]) _LT_DECL([], [want_nocaseglob], [1], [Find potential files using nocaseglob when deplibs_check_method = "file_magic"]) ])# _LT_CHECK_MAGIC_METHOD # LT_PATH_NM # ---------- # find the pathname to a BSD- or MS-compatible name lister AC_DEFUN([LT_PATH_NM], [AC_REQUIRE([AC_PROG_CC])dnl AC_CACHE_CHECK([for BSD- or MS-compatible name lister (nm)], lt_cv_path_NM, [if test -n "$NM"; then # Let the user override the test. lt_cv_path_NM="$NM" else lt_nm_to_check="${ac_tool_prefix}nm" if test -n "$ac_tool_prefix" && test "$build" = "$host"; then lt_nm_to_check="$lt_nm_to_check nm" fi for lt_tmp_nm in $lt_nm_to_check; do lt_save_ifs="$IFS"; IFS=$PATH_SEPARATOR for ac_dir in $PATH /usr/ccs/bin/elf /usr/ccs/bin /usr/ucb /bin; do IFS="$lt_save_ifs" test -z "$ac_dir" && ac_dir=. tmp_nm="$ac_dir/$lt_tmp_nm" if test -f "$tmp_nm" || test -f "$tmp_nm$ac_exeext" ; then # Check to see if the nm accepts a BSD-compat flag. # Adding the `sed 1q' prevents false positives on HP-UX, which says: # nm: unknown option "B" ignored # Tru64's nm complains that /dev/null is an invalid object file case `"$tmp_nm" -B /dev/null 2>&1 | sed '1q'` in */dev/null* | *'Invalid file or object type'*) lt_cv_path_NM="$tmp_nm -B" break ;; *) case `"$tmp_nm" -p /dev/null 2>&1 | sed '1q'` in */dev/null*) lt_cv_path_NM="$tmp_nm -p" break ;; *) lt_cv_path_NM=${lt_cv_path_NM="$tmp_nm"} # keep the first match, but continue # so that we can try to find one that supports BSD flags ;; esac ;; esac fi done IFS="$lt_save_ifs" done : ${lt_cv_path_NM=no} fi]) if test "$lt_cv_path_NM" != "no"; then NM="$lt_cv_path_NM" else # Didn't find any BSD compatible name lister, look for dumpbin. if test -n "$DUMPBIN"; then : # Let the user override the test. else AC_CHECK_TOOLS(DUMPBIN, [dumpbin "link -dump"], :) case `$DUMPBIN -symbols /dev/null 2>&1 | sed '1q'` in *COFF*) DUMPBIN="$DUMPBIN -symbols" ;; *) DUMPBIN=: ;; esac fi AC_SUBST([DUMPBIN]) if test "$DUMPBIN" != ":"; then NM="$DUMPBIN" fi fi test -z "$NM" && NM=nm AC_SUBST([NM]) _LT_DECL([], [NM], [1], [A BSD- or MS-compatible name lister])dnl AC_CACHE_CHECK([the name lister ($NM) interface], [lt_cv_nm_interface], [lt_cv_nm_interface="BSD nm" echo "int some_variable = 0;" > conftest.$ac_ext (eval echo "\"\$as_me:$LINENO: $ac_compile\"" >&AS_MESSAGE_LOG_FD) (eval "$ac_compile" 2>conftest.err) cat conftest.err >&AS_MESSAGE_LOG_FD (eval echo "\"\$as_me:$LINENO: $NM \\\"conftest.$ac_objext\\\"\"" >&AS_MESSAGE_LOG_FD) (eval "$NM \"conftest.$ac_objext\"" 2>conftest.err > conftest.out) cat conftest.err >&AS_MESSAGE_LOG_FD (eval echo "\"\$as_me:$LINENO: output\"" >&AS_MESSAGE_LOG_FD) cat conftest.out >&AS_MESSAGE_LOG_FD if $GREP 'External.*some_variable' conftest.out > /dev/null; then lt_cv_nm_interface="MS dumpbin" fi rm -f conftest*]) ])# LT_PATH_NM # Old names: AU_ALIAS([AM_PROG_NM], [LT_PATH_NM]) AU_ALIAS([AC_PROG_NM], [LT_PATH_NM]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AM_PROG_NM], []) dnl AC_DEFUN([AC_PROG_NM], []) # _LT_CHECK_SHAREDLIB_FROM_LINKLIB # -------------------------------- # how to determine the name of the shared library # associated with a specific link library. # -- PORTME fill in with the dynamic library characteristics m4_defun([_LT_CHECK_SHAREDLIB_FROM_LINKLIB], [m4_require([_LT_DECL_EGREP]) m4_require([_LT_DECL_OBJDUMP]) m4_require([_LT_DECL_DLLTOOL]) AC_CACHE_CHECK([how to associate runtime and link libraries], lt_cv_sharedlib_from_linklib_cmd, [lt_cv_sharedlib_from_linklib_cmd='unknown' case $host_os in cygwin* | mingw* | pw32* | cegcc*) # two different shell functions defined in ltmain.sh # decide which to use based on capabilities of $DLLTOOL case `$DLLTOOL --help 2>&1` in *--identify-strict*) lt_cv_sharedlib_from_linklib_cmd=func_cygming_dll_for_implib ;; *) lt_cv_sharedlib_from_linklib_cmd=func_cygming_dll_for_implib_fallback ;; esac ;; *) # fallback: assume linklib IS sharedlib lt_cv_sharedlib_from_linklib_cmd="$ECHO" ;; esac ]) sharedlib_from_linklib_cmd=$lt_cv_sharedlib_from_linklib_cmd test -z "$sharedlib_from_linklib_cmd" && sharedlib_from_linklib_cmd=$ECHO _LT_DECL([], [sharedlib_from_linklib_cmd], [1], [Command to associate shared and link libraries]) ])# _LT_CHECK_SHAREDLIB_FROM_LINKLIB # _LT_PATH_MANIFEST_TOOL # ---------------------- # locate the manifest tool m4_defun([_LT_PATH_MANIFEST_TOOL], [AC_CHECK_TOOL(MANIFEST_TOOL, mt, :) test -z "$MANIFEST_TOOL" && MANIFEST_TOOL=mt AC_CACHE_CHECK([if $MANIFEST_TOOL is a manifest tool], [lt_cv_path_mainfest_tool], [lt_cv_path_mainfest_tool=no echo "$as_me:$LINENO: $MANIFEST_TOOL '-?'" >&AS_MESSAGE_LOG_FD $MANIFEST_TOOL '-?' 2>conftest.err > conftest.out cat conftest.err >&AS_MESSAGE_LOG_FD if $GREP 'Manifest Tool' conftest.out > /dev/null; then lt_cv_path_mainfest_tool=yes fi rm -f conftest*]) if test "x$lt_cv_path_mainfest_tool" != xyes; then MANIFEST_TOOL=: fi _LT_DECL([], [MANIFEST_TOOL], [1], [Manifest tool])dnl ])# _LT_PATH_MANIFEST_TOOL # LT_LIB_M # -------- # check for math library AC_DEFUN([LT_LIB_M], [AC_REQUIRE([AC_CANONICAL_HOST])dnl LIBM= case $host in *-*-beos* | *-*-cegcc* | *-*-cygwin* | *-*-haiku* | *-*-pw32* | *-*-darwin*) # These system don't have libm, or don't need it ;; *-ncr-sysv4.3*) AC_CHECK_LIB(mw, _mwvalidcheckl, LIBM="-lmw") AC_CHECK_LIB(m, cos, LIBM="$LIBM -lm") ;; *) AC_CHECK_LIB(m, cos, LIBM="-lm") ;; esac AC_SUBST([LIBM]) ])# LT_LIB_M # Old name: AU_ALIAS([AC_CHECK_LIBM], [LT_LIB_M]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AC_CHECK_LIBM], []) # _LT_COMPILER_NO_RTTI([TAGNAME]) # ------------------------------- m4_defun([_LT_COMPILER_NO_RTTI], [m4_require([_LT_TAG_COMPILER])dnl _LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)= if test "$GCC" = yes; then case $cc_basename in nvcc*) _LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)=' -Xcompiler -fno-builtin' ;; *) _LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)=' -fno-builtin' ;; esac _LT_COMPILER_OPTION([if $compiler supports -fno-rtti -fno-exceptions], lt_cv_prog_compiler_rtti_exceptions, [-fno-rtti -fno-exceptions], [], [_LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)="$_LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1) -fno-rtti -fno-exceptions"]) fi _LT_TAGDECL([no_builtin_flag], [lt_prog_compiler_no_builtin_flag], [1], [Compiler flag to turn off builtin functions]) ])# _LT_COMPILER_NO_RTTI # _LT_CMD_GLOBAL_SYMBOLS # ---------------------- m4_defun([_LT_CMD_GLOBAL_SYMBOLS], [AC_REQUIRE([AC_CANONICAL_HOST])dnl AC_REQUIRE([AC_PROG_CC])dnl AC_REQUIRE([AC_PROG_AWK])dnl AC_REQUIRE([LT_PATH_NM])dnl AC_REQUIRE([LT_PATH_LD])dnl m4_require([_LT_DECL_SED])dnl m4_require([_LT_DECL_EGREP])dnl m4_require([_LT_TAG_COMPILER])dnl # Check for command to grab the raw symbol name followed by C symbol from nm. AC_MSG_CHECKING([command to parse $NM output from $compiler object]) AC_CACHE_VAL([lt_cv_sys_global_symbol_pipe], [ # These are sane defaults that work on at least a few old systems. # [They come from Ultrix. What could be older than Ultrix?!! ;)] # Character class describing NM global symbol codes. symcode='[[BCDEGRST]]' # Regexp to match symbols that can be accessed directly from C. sympat='\([[_A-Za-z]][[_A-Za-z0-9]]*\)' # Define system-specific variables. case $host_os in aix*) symcode='[[BCDT]]' ;; cygwin* | mingw* | pw32* | cegcc*) symcode='[[ABCDGISTW]]' ;; hpux*) if test "$host_cpu" = ia64; then symcode='[[ABCDEGRST]]' fi ;; irix* | nonstopux*) symcode='[[BCDEGRST]]' ;; osf*) symcode='[[BCDEGQRST]]' ;; solaris*) symcode='[[BDRT]]' ;; sco3.2v5*) symcode='[[DT]]' ;; sysv4.2uw2*) symcode='[[DT]]' ;; sysv5* | sco5v6* | unixware* | OpenUNIX*) symcode='[[ABDT]]' ;; sysv4) symcode='[[DFNSTU]]' ;; esac # If we're using GNU nm, then use its standard symbol codes. case `$NM -V 2>&1` in *GNU* | *'with BFD'*) symcode='[[ABCDGIRSTW]]' ;; esac # Transform an extracted symbol line into a proper C declaration. # Some systems (esp. on ia64) link data and code symbols differently, # so use this general approach. lt_cv_sys_global_symbol_to_cdecl="sed -n -e 's/^T .* \(.*\)$/extern int \1();/p' -e 's/^$symcode* .* \(.*\)$/extern char \1;/p'" # Transform an extracted symbol line into symbol name and symbol address lt_cv_sys_global_symbol_to_c_name_address="sed -n -e 's/^: \([[^ ]]*\)[[ ]]*$/ {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([[^ ]]*\) \([[^ ]]*\)$/ {\"\2\", (void *) \&\2},/p'" lt_cv_sys_global_symbol_to_c_name_address_lib_prefix="sed -n -e 's/^: \([[^ ]]*\)[[ ]]*$/ {\\\"\1\\\", (void *) 0},/p' -e 's/^$symcode* \([[^ ]]*\) \(lib[[^ ]]*\)$/ {\"\2\", (void *) \&\2},/p' -e 's/^$symcode* \([[^ ]]*\) \([[^ ]]*\)$/ {\"lib\2\", (void *) \&\2},/p'" # Handle CRLF in mingw tool chain opt_cr= case $build_os in mingw*) opt_cr=`$ECHO 'x\{0,1\}' | tr x '\015'` # option cr in regexp ;; esac # Try without a prefix underscore, then with it. for ac_symprfx in "" "_"; do # Transform symcode, sympat, and symprfx into a raw symbol and a C symbol. symxfrm="\\1 $ac_symprfx\\2 \\2" # Write the raw and C identifiers. if test "$lt_cv_nm_interface" = "MS dumpbin"; then # Fake it for dumpbin and say T for any non-static function # and D for any global variable. # Also find C++ and __fastcall symbols from MSVC++, # which start with @ or ?. lt_cv_sys_global_symbol_pipe="$AWK ['"\ " {last_section=section; section=\$ 3};"\ " /Section length .*#relocs.*(pick any)/{hide[last_section]=1};"\ " \$ 0!~/External *\|/{next};"\ " / 0+ UNDEF /{next}; / UNDEF \([^|]\)*()/{next};"\ " {if(hide[section]) next};"\ " {f=0}; \$ 0~/\(\).*\|/{f=1}; {printf f ? \"T \" : \"D \"};"\ " {split(\$ 0, a, /\||\r/); split(a[2], s)};"\ " s[1]~/^[@?]/{print s[1], s[1]; next};"\ " s[1]~prfx {split(s[1],t,\"@\"); print t[1], substr(t[1],length(prfx))}"\ " ' prfx=^$ac_symprfx]" else lt_cv_sys_global_symbol_pipe="sed -n -e 's/^.*[[ ]]\($symcode$symcode*\)[[ ]][[ ]]*$ac_symprfx$sympat$opt_cr$/$symxfrm/p'" fi lt_cv_sys_global_symbol_pipe="$lt_cv_sys_global_symbol_pipe | sed '/ __gnu_lto/d'" # Check to see that the pipe works correctly. pipe_works=no rm -f conftest* cat > conftest.$ac_ext <<_LT_EOF #ifdef __cplusplus extern "C" { #endif char nm_test_var; void nm_test_func(void); void nm_test_func(void){} #ifdef __cplusplus } #endif int main(){nm_test_var='a';nm_test_func();return(0);} _LT_EOF if AC_TRY_EVAL(ac_compile); then # Now try to grab the symbols. nlist=conftest.nm if AC_TRY_EVAL(NM conftest.$ac_objext \| "$lt_cv_sys_global_symbol_pipe" \> $nlist) && test -s "$nlist"; then # Try sorting and uniquifying the output. if sort "$nlist" | uniq > "$nlist"T; then mv -f "$nlist"T "$nlist" else rm -f "$nlist"T fi # Make sure that we snagged all the symbols we need. if $GREP ' nm_test_var$' "$nlist" >/dev/null; then if $GREP ' nm_test_func$' "$nlist" >/dev/null; then cat <<_LT_EOF > conftest.$ac_ext /* Keep this code in sync between libtool.m4, ltmain, lt_system.h, and tests. */ #if defined(_WIN32) || defined(__CYGWIN__) || defined(_WIN32_WCE) /* DATA imports from DLLs on WIN32 con't be const, because runtime relocations are performed -- see ld's documentation on pseudo-relocs. */ # define LT@&t@_DLSYM_CONST #elif defined(__osf__) /* This system does not cope well with relocations in const data. */ # define LT@&t@_DLSYM_CONST #else # define LT@&t@_DLSYM_CONST const #endif #ifdef __cplusplus extern "C" { #endif _LT_EOF # Now generate the symbol file. eval "$lt_cv_sys_global_symbol_to_cdecl"' < "$nlist" | $GREP -v main >> conftest.$ac_ext' cat <<_LT_EOF >> conftest.$ac_ext /* The mapping between symbol names and symbols. */ LT@&t@_DLSYM_CONST struct { const char *name; void *address; } lt__PROGRAM__LTX_preloaded_symbols[[]] = { { "@PROGRAM@", (void *) 0 }, _LT_EOF $SED "s/^$symcode$symcode* \(.*\) \(.*\)$/ {\"\2\", (void *) \&\2},/" < "$nlist" | $GREP -v main >> conftest.$ac_ext cat <<\_LT_EOF >> conftest.$ac_ext {0, (void *) 0} }; /* This works around a problem in FreeBSD linker */ #ifdef FREEBSD_WORKAROUND static const void *lt_preloaded_setup() { return lt__PROGRAM__LTX_preloaded_symbols; } #endif #ifdef __cplusplus } #endif _LT_EOF # Now try linking the two files. mv conftest.$ac_objext conftstm.$ac_objext lt_globsym_save_LIBS=$LIBS lt_globsym_save_CFLAGS=$CFLAGS LIBS="conftstm.$ac_objext" CFLAGS="$CFLAGS$_LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)" if AC_TRY_EVAL(ac_link) && test -s conftest${ac_exeext}; then pipe_works=yes fi LIBS=$lt_globsym_save_LIBS CFLAGS=$lt_globsym_save_CFLAGS else echo "cannot find nm_test_func in $nlist" >&AS_MESSAGE_LOG_FD fi else echo "cannot find nm_test_var in $nlist" >&AS_MESSAGE_LOG_FD fi else echo "cannot run $lt_cv_sys_global_symbol_pipe" >&AS_MESSAGE_LOG_FD fi else echo "$progname: failed program was:" >&AS_MESSAGE_LOG_FD cat conftest.$ac_ext >&5 fi rm -rf conftest* conftst* # Do not use the global_symbol_pipe unless it works. if test "$pipe_works" = yes; then break else lt_cv_sys_global_symbol_pipe= fi done ]) if test -z "$lt_cv_sys_global_symbol_pipe"; then lt_cv_sys_global_symbol_to_cdecl= fi if test -z "$lt_cv_sys_global_symbol_pipe$lt_cv_sys_global_symbol_to_cdecl"; then AC_MSG_RESULT(failed) else AC_MSG_RESULT(ok) fi # Response file support. if test "$lt_cv_nm_interface" = "MS dumpbin"; then nm_file_list_spec='@' elif $NM --help 2>/dev/null | grep '[[@]]FILE' >/dev/null; then nm_file_list_spec='@' fi _LT_DECL([global_symbol_pipe], [lt_cv_sys_global_symbol_pipe], [1], [Take the output of nm and produce a listing of raw symbols and C names]) _LT_DECL([global_symbol_to_cdecl], [lt_cv_sys_global_symbol_to_cdecl], [1], [Transform the output of nm in a proper C declaration]) _LT_DECL([global_symbol_to_c_name_address], [lt_cv_sys_global_symbol_to_c_name_address], [1], [Transform the output of nm in a C name address pair]) _LT_DECL([global_symbol_to_c_name_address_lib_prefix], [lt_cv_sys_global_symbol_to_c_name_address_lib_prefix], [1], [Transform the output of nm in a C name address pair when lib prefix is needed]) _LT_DECL([], [nm_file_list_spec], [1], [Specify filename containing input files for $NM]) ]) # _LT_CMD_GLOBAL_SYMBOLS # _LT_COMPILER_PIC([TAGNAME]) # --------------------------- m4_defun([_LT_COMPILER_PIC], [m4_require([_LT_TAG_COMPILER])dnl _LT_TAGVAR(lt_prog_compiler_wl, $1)= _LT_TAGVAR(lt_prog_compiler_pic, $1)= _LT_TAGVAR(lt_prog_compiler_static, $1)= m4_if([$1], [CXX], [ # C++ specific cases for pic, static, wl, etc. if test "$GXX" = yes; then _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_static, $1)='-static' case $host_os in aix*) # All AIX code is PIC. if test "$host_cpu" = ia64; then # AIX 5 now supports IA64 processor _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' fi ;; amigaos*) case $host_cpu in powerpc) # see comment about AmigaOS4 .so support _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' ;; m68k) # FIXME: we need at least 68020 code to build shared libraries, but # adding the `-m68020' flag to GCC prevents building anything better, # like `-m68040'. _LT_TAGVAR(lt_prog_compiler_pic, $1)='-m68020 -resident32 -malways-restore-a4' ;; esac ;; beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*) # PIC is the default for these OSes. ;; mingw* | cygwin* | os2* | pw32* | cegcc*) # This hack is so that the source file can tell whether it is being # built for inclusion in a dll (and should export symbols for example). # Although the cygwin gcc ignores -fPIC, still need this for old-style # (--disable-auto-import) libraries m4_if([$1], [GCJ], [], [_LT_TAGVAR(lt_prog_compiler_pic, $1)='-DDLL_EXPORT']) ;; darwin* | rhapsody*) # PIC is the default on this platform # Common symbols not allowed in MH_DYLIB files _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fno-common' ;; *djgpp*) # DJGPP does not support shared libraries at all _LT_TAGVAR(lt_prog_compiler_pic, $1)= ;; haiku*) # PIC is the default for Haiku. # The "-static" flag exists, but is broken. _LT_TAGVAR(lt_prog_compiler_static, $1)= ;; interix[[3-9]]*) # Interix 3.x gcc -fpic/-fPIC options generate broken code. # Instead, we relocate shared libraries at runtime. ;; sysv4*MP*) if test -d /usr/nec; then _LT_TAGVAR(lt_prog_compiler_pic, $1)=-Kconform_pic fi ;; hpux*) # PIC is the default for 64-bit PA HP-UX, but not for 32-bit # PA HP-UX. On IA64 HP-UX, PIC is the default but the pic flag # sets the default TLS model and affects inlining. case $host_cpu in hppa*64*) ;; *) _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' ;; esac ;; *qnx* | *nto*) # QNX uses GNU C++, but need to define -shared option too, otherwise # it will coredump. _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC -shared' ;; *) _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' ;; esac else case $host_os in aix[[4-9]]*) # All AIX code is PIC. if test "$host_cpu" = ia64; then # AIX 5 now supports IA64 processor _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' else _LT_TAGVAR(lt_prog_compiler_static, $1)='-bnso -bI:/lib/syscalls.exp' fi ;; chorus*) case $cc_basename in cxch68*) # Green Hills C++ Compiler # _LT_TAGVAR(lt_prog_compiler_static, $1)="--no_auto_instantiation -u __main -u __premain -u _abort -r $COOL_DIR/lib/libOrb.a $MVME_DIR/lib/CC/libC.a $MVME_DIR/lib/classix/libcx.s.a" ;; esac ;; mingw* | cygwin* | os2* | pw32* | cegcc*) # This hack is so that the source file can tell whether it is being # built for inclusion in a dll (and should export symbols for example). m4_if([$1], [GCJ], [], [_LT_TAGVAR(lt_prog_compiler_pic, $1)='-DDLL_EXPORT']) ;; dgux*) case $cc_basename in ec++*) _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' ;; ghcx*) # Green Hills C++ Compiler _LT_TAGVAR(lt_prog_compiler_pic, $1)='-pic' ;; *) ;; esac ;; freebsd* | dragonfly*) # FreeBSD uses GNU C++ ;; hpux9* | hpux10* | hpux11*) case $cc_basename in CC*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_static, $1)='${wl}-a ${wl}archive' if test "$host_cpu" != ia64; then _LT_TAGVAR(lt_prog_compiler_pic, $1)='+Z' fi ;; aCC*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_static, $1)='${wl}-a ${wl}archive' case $host_cpu in hppa*64*|ia64*) # +Z the default ;; *) _LT_TAGVAR(lt_prog_compiler_pic, $1)='+Z' ;; esac ;; *) ;; esac ;; interix*) # This is c89, which is MS Visual C++ (no shared libs) # Anyone wants to do a port? ;; irix5* | irix6* | nonstopux*) case $cc_basename in CC*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared' # CC pic flag -KPIC is the default. ;; *) ;; esac ;; linux* | k*bsd*-gnu | kopensolaris*-gnu) case $cc_basename in KCC*) # KAI C++ Compiler _LT_TAGVAR(lt_prog_compiler_wl, $1)='--backend -Wl,' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' ;; ecpc* ) # old Intel C++ for x86_64 which still supported -KPIC. _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-static' ;; icpc* ) # Intel C++, used to be incompatible with GCC. # ICC 10 doesn't accept -KPIC any more. _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-static' ;; pgCC* | pgcpp*) # Portland Group C++ compiler _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fpic' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; cxx*) # Compaq C++ # Make sure the PIC flag is empty. It appears that all Alpha # Linux and Compaq Tru64 Unix objects are PIC. _LT_TAGVAR(lt_prog_compiler_pic, $1)= _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared' ;; xlc* | xlC* | bgxl[[cC]]* | mpixl[[cC]]*) # IBM XL 8.0, 9.0 on PPC and BlueGene _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-qpic' _LT_TAGVAR(lt_prog_compiler_static, $1)='-qstaticlink' ;; *) case `$CC -V 2>&1 | sed 5q` in *Sun\ C*) # Sun C++ 5.9 _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Qoption ld ' ;; esac ;; esac ;; lynxos*) ;; m88k*) ;; mvs*) case $cc_basename in cxx*) _LT_TAGVAR(lt_prog_compiler_pic, $1)='-W c,exportall' ;; *) ;; esac ;; netbsd* | netbsdelf*-gnu) ;; *qnx* | *nto*) # QNX uses GNU C++, but need to define -shared option too, otherwise # it will coredump. _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC -shared' ;; osf3* | osf4* | osf5*) case $cc_basename in KCC*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='--backend -Wl,' ;; RCC*) # Rational C++ 2.4.1 _LT_TAGVAR(lt_prog_compiler_pic, $1)='-pic' ;; cxx*) # Digital/Compaq C++ _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' # Make sure the PIC flag is empty. It appears that all Alpha # Linux and Compaq Tru64 Unix objects are PIC. _LT_TAGVAR(lt_prog_compiler_pic, $1)= _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared' ;; *) ;; esac ;; psos*) ;; solaris*) case $cc_basename in CC* | sunCC*) # Sun C++ 4.2, 5.x and Centerline C++ _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Qoption ld ' ;; gcx*) # Green Hills C++ Compiler _LT_TAGVAR(lt_prog_compiler_pic, $1)='-PIC' ;; *) ;; esac ;; sunos4*) case $cc_basename in CC*) # Sun C++ 4.x _LT_TAGVAR(lt_prog_compiler_pic, $1)='-pic' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; lcc*) # Lucid _LT_TAGVAR(lt_prog_compiler_pic, $1)='-pic' ;; *) ;; esac ;; sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*) case $cc_basename in CC*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; esac ;; tandem*) case $cc_basename in NCC*) # NonStop-UX NCC 3.20 _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' ;; *) ;; esac ;; vxworks*) ;; *) _LT_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no ;; esac fi ], [ if test "$GCC" = yes; then _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_static, $1)='-static' case $host_os in aix*) # All AIX code is PIC. if test "$host_cpu" = ia64; then # AIX 5 now supports IA64 processor _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' fi ;; amigaos*) case $host_cpu in powerpc) # see comment about AmigaOS4 .so support _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' ;; m68k) # FIXME: we need at least 68020 code to build shared libraries, but # adding the `-m68020' flag to GCC prevents building anything better, # like `-m68040'. _LT_TAGVAR(lt_prog_compiler_pic, $1)='-m68020 -resident32 -malways-restore-a4' ;; esac ;; beos* | irix5* | irix6* | nonstopux* | osf3* | osf4* | osf5*) # PIC is the default for these OSes. ;; mingw* | cygwin* | pw32* | os2* | cegcc*) # This hack is so that the source file can tell whether it is being # built for inclusion in a dll (and should export symbols for example). # Although the cygwin gcc ignores -fPIC, still need this for old-style # (--disable-auto-import) libraries m4_if([$1], [GCJ], [], [_LT_TAGVAR(lt_prog_compiler_pic, $1)='-DDLL_EXPORT']) ;; darwin* | rhapsody*) # PIC is the default on this platform # Common symbols not allowed in MH_DYLIB files _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fno-common' ;; haiku*) # PIC is the default for Haiku. # The "-static" flag exists, but is broken. _LT_TAGVAR(lt_prog_compiler_static, $1)= ;; hpux*) # PIC is the default for 64-bit PA HP-UX, but not for 32-bit # PA HP-UX. On IA64 HP-UX, PIC is the default but the pic flag # sets the default TLS model and affects inlining. case $host_cpu in hppa*64*) # +Z the default ;; *) _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' ;; esac ;; interix[[3-9]]*) # Interix 3.x gcc -fpic/-fPIC options generate broken code. # Instead, we relocate shared libraries at runtime. ;; msdosdjgpp*) # Just because we use GCC doesn't mean we suddenly get shared libraries # on systems that don't support them. _LT_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no enable_shared=no ;; *nto* | *qnx*) # QNX uses GNU C++, but need to define -shared option too, otherwise # it will coredump. _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC -shared' ;; sysv4*MP*) if test -d /usr/nec; then _LT_TAGVAR(lt_prog_compiler_pic, $1)=-Kconform_pic fi ;; *) _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' ;; esac case $cc_basename in nvcc*) # Cuda Compiler Driver 2.2 _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Xlinker ' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-Xcompiler -fPIC' ;; esac else # PORTME Check for flag to pass linker flags through the system compiler. case $host_os in aix*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' if test "$host_cpu" = ia64; then # AIX 5 now supports IA64 processor _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' else _LT_TAGVAR(lt_prog_compiler_static, $1)='-bnso -bI:/lib/syscalls.exp' fi ;; mingw* | cygwin* | pw32* | os2* | cegcc*) # This hack is so that the source file can tell whether it is being # built for inclusion in a dll (and should export symbols for example). m4_if([$1], [GCJ], [], [_LT_TAGVAR(lt_prog_compiler_pic, $1)='-DDLL_EXPORT']) ;; hpux9* | hpux10* | hpux11*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' # PIC is the default for IA64 HP-UX and 64-bit HP-UX, but # not for PA HP-UX. case $host_cpu in hppa*64*|ia64*) # +Z the default ;; *) _LT_TAGVAR(lt_prog_compiler_pic, $1)='+Z' ;; esac # Is there a better lt_prog_compiler_static that works with the bundled CC? _LT_TAGVAR(lt_prog_compiler_static, $1)='${wl}-a ${wl}archive' ;; irix5* | irix6* | nonstopux*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' # PIC (with -KPIC) is the default. _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared' ;; linux* | k*bsd*-gnu | kopensolaris*-gnu) case $cc_basename in # old Intel for x86_64 which still supported -KPIC. ecc*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-static' ;; # icc used to be incompatible with GCC. # ICC 10 doesn't accept -KPIC any more. icc* | ifort*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-static' ;; # Lahey Fortran 8.1. lf95*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_pic, $1)='--shared' _LT_TAGVAR(lt_prog_compiler_static, $1)='--static' ;; nagfor*) # NAG Fortran compiler _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,-Wl,,' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-PIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; pgcc* | pgf77* | pgf90* | pgf95* | pgfortran*) # Portland Group compilers (*not* the Pentium gcc compiler, # which looks to be a dead project) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fpic' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; ccc*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' # All Alpha code is PIC. _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared' ;; xl* | bgxl* | bgf* | mpixl*) # IBM XL C 8.0/Fortran 10.1, 11.1 on PPC and BlueGene _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-qpic' _LT_TAGVAR(lt_prog_compiler_static, $1)='-qstaticlink' ;; *) case `$CC -V 2>&1 | sed 5q` in *Sun\ F* | *Sun*Fortran*) # Sun Fortran 8.3 passes all unrecognized flags to the linker _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' _LT_TAGVAR(lt_prog_compiler_wl, $1)='' ;; *Sun\ C*) # Sun C 5.9 _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' ;; esac ;; esac ;; newsos6) _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; *nto* | *qnx*) # QNX uses GNU C++, but need to define -shared option too, otherwise # it will coredump. _LT_TAGVAR(lt_prog_compiler_pic, $1)='-fPIC -shared' ;; osf3* | osf4* | osf5*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' # All OSF/1 code is PIC. _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared' ;; rdos*) _LT_TAGVAR(lt_prog_compiler_static, $1)='-non_shared' ;; solaris*) _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' case $cc_basename in f77* | f90* | f95* | sunf77* | sunf90* | sunf95*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Qoption ld ';; *) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,';; esac ;; sunos4*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Qoption ld ' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-PIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; sysv4 | sysv4.2uw2* | sysv4.3*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; sysv4*MP*) if test -d /usr/nec ;then _LT_TAGVAR(lt_prog_compiler_pic, $1)='-Kconform_pic' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' fi ;; sysv5* | unixware* | sco3.2v5* | sco5v6* | OpenUNIX*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_pic, $1)='-KPIC' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; unicos*) _LT_TAGVAR(lt_prog_compiler_wl, $1)='-Wl,' _LT_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no ;; uts4*) _LT_TAGVAR(lt_prog_compiler_pic, $1)='-pic' _LT_TAGVAR(lt_prog_compiler_static, $1)='-Bstatic' ;; *) _LT_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no ;; esac fi ]) case $host_os in # For platforms which do not support PIC, -DPIC is meaningless: *djgpp*) _LT_TAGVAR(lt_prog_compiler_pic, $1)= ;; *) _LT_TAGVAR(lt_prog_compiler_pic, $1)="$_LT_TAGVAR(lt_prog_compiler_pic, $1)@&t@m4_if([$1],[],[ -DPIC],[m4_if([$1],[CXX],[ -DPIC],[])])" ;; esac AC_CACHE_CHECK([for $compiler option to produce PIC], [_LT_TAGVAR(lt_cv_prog_compiler_pic, $1)], [_LT_TAGVAR(lt_cv_prog_compiler_pic, $1)=$_LT_TAGVAR(lt_prog_compiler_pic, $1)]) _LT_TAGVAR(lt_prog_compiler_pic, $1)=$_LT_TAGVAR(lt_cv_prog_compiler_pic, $1) # # Check to make sure the PIC flag actually works. # if test -n "$_LT_TAGVAR(lt_prog_compiler_pic, $1)"; then _LT_COMPILER_OPTION([if $compiler PIC flag $_LT_TAGVAR(lt_prog_compiler_pic, $1) works], [_LT_TAGVAR(lt_cv_prog_compiler_pic_works, $1)], [$_LT_TAGVAR(lt_prog_compiler_pic, $1)@&t@m4_if([$1],[],[ -DPIC],[m4_if([$1],[CXX],[ -DPIC],[])])], [], [case $_LT_TAGVAR(lt_prog_compiler_pic, $1) in "" | " "*) ;; *) _LT_TAGVAR(lt_prog_compiler_pic, $1)=" $_LT_TAGVAR(lt_prog_compiler_pic, $1)" ;; esac], [_LT_TAGVAR(lt_prog_compiler_pic, $1)= _LT_TAGVAR(lt_prog_compiler_can_build_shared, $1)=no]) fi _LT_TAGDECL([pic_flag], [lt_prog_compiler_pic], [1], [Additional compiler flags for building library objects]) _LT_TAGDECL([wl], [lt_prog_compiler_wl], [1], [How to pass a linker flag through the compiler]) # # Check to make sure the static flag actually works. # wl=$_LT_TAGVAR(lt_prog_compiler_wl, $1) eval lt_tmp_static_flag=\"$_LT_TAGVAR(lt_prog_compiler_static, $1)\" _LT_LINKER_OPTION([if $compiler static flag $lt_tmp_static_flag works], _LT_TAGVAR(lt_cv_prog_compiler_static_works, $1), $lt_tmp_static_flag, [], [_LT_TAGVAR(lt_prog_compiler_static, $1)=]) _LT_TAGDECL([link_static_flag], [lt_prog_compiler_static], [1], [Compiler flag to prevent dynamic linking]) ])# _LT_COMPILER_PIC # _LT_LINKER_SHLIBS([TAGNAME]) # ---------------------------- # See if the linker supports building shared libraries. m4_defun([_LT_LINKER_SHLIBS], [AC_REQUIRE([LT_PATH_LD])dnl AC_REQUIRE([LT_PATH_NM])dnl m4_require([_LT_PATH_MANIFEST_TOOL])dnl m4_require([_LT_FILEUTILS_DEFAULTS])dnl m4_require([_LT_DECL_EGREP])dnl m4_require([_LT_DECL_SED])dnl m4_require([_LT_CMD_GLOBAL_SYMBOLS])dnl m4_require([_LT_TAG_COMPILER])dnl AC_MSG_CHECKING([whether the $compiler linker ($LD) supports shared libraries]) m4_if([$1], [CXX], [ _LT_TAGVAR(export_symbols_cmds, $1)='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols' _LT_TAGVAR(exclude_expsyms, $1)=['_GLOBAL_OFFSET_TABLE_|_GLOBAL__F[ID]_.*'] case $host_os in aix[[4-9]]*) # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global defined # symbols, whereas GNU nm marks them as "W". if $NM -V 2>&1 | $GREP 'GNU' > /dev/null; then _LT_TAGVAR(export_symbols_cmds, $1)='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B") || (\$ 2 == "W")) && ([substr](\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols' else _LT_TAGVAR(export_symbols_cmds, $1)='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && ([substr](\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols' fi ;; pw32*) _LT_TAGVAR(export_symbols_cmds, $1)="$ltdll_cmds" ;; cygwin* | mingw* | cegcc*) case $cc_basename in cl*) ;; *) _LT_TAGVAR(export_symbols_cmds, $1)='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[[BCDGRS]][[ ]]/s/.*[[ ]]\([[^ ]]*\)/\1 DATA/;s/^.*[[ ]]__nm__\([[^ ]]*\)[[ ]][[^ ]]*/\1 DATA/;/^I[[ ]]/d;/^[[AITW]][[ ]]/s/.* //'\'' | sort | uniq > $export_symbols' _LT_TAGVAR(exclude_expsyms, $1)=['[_]+GLOBAL_OFFSET_TABLE_|[_]+GLOBAL__[FID]_.*|[_]+head_[A-Za-z0-9_]+_dll|[A-Za-z0-9_]+_dll_iname'] ;; esac ;; linux* | k*bsd*-gnu | gnu*) _LT_TAGVAR(link_all_deplibs, $1)=no ;; *) _LT_TAGVAR(export_symbols_cmds, $1)='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols' ;; esac ], [ runpath_var= _LT_TAGVAR(allow_undefined_flag, $1)= _LT_TAGVAR(always_export_symbols, $1)=no _LT_TAGVAR(archive_cmds, $1)= _LT_TAGVAR(archive_expsym_cmds, $1)= _LT_TAGVAR(compiler_needs_object, $1)=no _LT_TAGVAR(enable_shared_with_static_runtimes, $1)=no _LT_TAGVAR(export_dynamic_flag_spec, $1)= _LT_TAGVAR(export_symbols_cmds, $1)='$NM $libobjs $convenience | $global_symbol_pipe | $SED '\''s/.* //'\'' | sort | uniq > $export_symbols' _LT_TAGVAR(hardcode_automatic, $1)=no _LT_TAGVAR(hardcode_direct, $1)=no _LT_TAGVAR(hardcode_direct_absolute, $1)=no _LT_TAGVAR(hardcode_libdir_flag_spec, $1)= _LT_TAGVAR(hardcode_libdir_flag_spec_ld, $1)= _LT_TAGVAR(hardcode_libdir_separator, $1)= _LT_TAGVAR(hardcode_minus_L, $1)=no _LT_TAGVAR(hardcode_shlibpath_var, $1)=unsupported _LT_TAGVAR(inherit_rpath, $1)=no _LT_TAGVAR(link_all_deplibs, $1)=unknown _LT_TAGVAR(module_cmds, $1)= _LT_TAGVAR(module_expsym_cmds, $1)= _LT_TAGVAR(old_archive_from_new_cmds, $1)= _LT_TAGVAR(old_archive_from_expsyms_cmds, $1)= _LT_TAGVAR(thread_safe_flag_spec, $1)= _LT_TAGVAR(whole_archive_flag_spec, $1)= # include_expsyms should be a list of space-separated symbols to be *always* # included in the symbol list _LT_TAGVAR(include_expsyms, $1)= # exclude_expsyms can be an extended regexp of symbols to exclude # it will be wrapped by ` (' and `)$', so one must not match beginning or # end of line. Example: `a|bc|.*d.*' will exclude the symbols `a' and `bc', # as well as any symbol that contains `d'. _LT_TAGVAR(exclude_expsyms, $1)=['_GLOBAL_OFFSET_TABLE_|_GLOBAL__F[ID]_.*'] # Although _GLOBAL_OFFSET_TABLE_ is a valid symbol C name, most a.out # platforms (ab)use it in PIC code, but their linkers get confused if # the symbol is explicitly referenced. Since portable code cannot # rely on this symbol name, it's probably fine to never include it in # preloaded symbol tables. # Exclude shared library initialization/finalization symbols. dnl Note also adjust exclude_expsyms for C++ above. extract_expsyms_cmds= case $host_os in cygwin* | mingw* | pw32* | cegcc*) # FIXME: the MSVC++ port hasn't been tested in a loooong time # When not using gcc, we currently assume that we are using # Microsoft Visual C++. if test "$GCC" != yes; then with_gnu_ld=no fi ;; interix*) # we just hope/assume this is gcc and not c89 (= MSVC++) with_gnu_ld=yes ;; openbsd*) with_gnu_ld=no ;; linux* | k*bsd*-gnu | gnu*) _LT_TAGVAR(link_all_deplibs, $1)=no ;; esac _LT_TAGVAR(ld_shlibs, $1)=yes # On some targets, GNU ld is compatible enough with the native linker # that we're better off using the native interface for both. lt_use_gnu_ld_interface=no if test "$with_gnu_ld" = yes; then case $host_os in aix*) # The AIX port of GNU ld has always aspired to compatibility # with the native linker. However, as the warning in the GNU ld # block says, versions before 2.19.5* couldn't really create working # shared libraries, regardless of the interface used. case `$LD -v 2>&1` in *\ \(GNU\ Binutils\)\ 2.19.5*) ;; *\ \(GNU\ Binutils\)\ 2.[[2-9]]*) ;; *\ \(GNU\ Binutils\)\ [[3-9]]*) ;; *) lt_use_gnu_ld_interface=yes ;; esac ;; *) lt_use_gnu_ld_interface=yes ;; esac fi if test "$lt_use_gnu_ld_interface" = yes; then # If archive_cmds runs LD, not CC, wlarc should be empty wlarc='${wl}' # Set some defaults for GNU ld with shared library support. These # are reset later if shared libraries are not supported. Putting them # here allows them to be overridden if necessary. runpath_var=LD_RUN_PATH _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir' _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-dynamic' # ancient GNU ld didn't support --whole-archive et. al. if $LD --help 2>&1 | $GREP 'no-whole-archive' > /dev/null; then _LT_TAGVAR(whole_archive_flag_spec, $1)="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive' else _LT_TAGVAR(whole_archive_flag_spec, $1)= fi supports_anon_versioning=no case `$LD -v 2>&1` in *GNU\ gold*) supports_anon_versioning=yes ;; *\ [[01]].* | *\ 2.[[0-9]].* | *\ 2.10.*) ;; # catch versions < 2.11 *\ 2.11.93.0.2\ *) supports_anon_versioning=yes ;; # RH7.3 ... *\ 2.11.92.0.12\ *) supports_anon_versioning=yes ;; # Mandrake 8.2 ... *\ 2.11.*) ;; # other 2.11 versions *) supports_anon_versioning=yes ;; esac # See if GNU ld supports shared libraries. case $host_os in aix[[3-9]]*) # On AIX/PPC, the GNU linker is very broken if test "$host_cpu" != ia64; then _LT_TAGVAR(ld_shlibs, $1)=no cat <<_LT_EOF 1>&2 *** Warning: the GNU linker, at least up to release 2.19, is reported *** to be unable to reliably create shared libraries on AIX. *** Therefore, libtool is disabling shared libraries support. If you *** really care for shared libraries, you may want to install binutils *** 2.20 or above, or modify your PATH so that a non-GNU linker is found. *** You will then need to restart the configuration process. _LT_EOF fi ;; amigaos*) case $host_cpu in powerpc) # see comment about AmigaOS4 .so support _LT_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='' ;; m68k) _LT_TAGVAR(archive_cmds, $1)='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir' _LT_TAGVAR(hardcode_minus_L, $1)=yes ;; esac ;; beos*) if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then _LT_TAGVAR(allow_undefined_flag, $1)=unsupported # Joseph Beckenbach says some releases of gcc # support --undefined. This deserves some investigation. FIXME _LT_TAGVAR(archive_cmds, $1)='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' else _LT_TAGVAR(ld_shlibs, $1)=no fi ;; cygwin* | mingw* | pw32* | cegcc*) # _LT_TAGVAR(hardcode_libdir_flag_spec, $1) is actually meaningless, # as there is no search path for DLLs. _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir' _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-all-symbols' _LT_TAGVAR(allow_undefined_flag, $1)=unsupported _LT_TAGVAR(always_export_symbols, $1)=no _LT_TAGVAR(enable_shared_with_static_runtimes, $1)=yes _LT_TAGVAR(export_symbols_cmds, $1)='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[[BCDGRS]][[ ]]/s/.*[[ ]]\([[^ ]]*\)/\1 DATA/;s/^.*[[ ]]__nm__\([[^ ]]*\)[[ ]][[^ ]]*/\1 DATA/;/^I[[ ]]/d;/^[[AITW]][[ ]]/s/.* //'\'' | sort | uniq > $export_symbols' _LT_TAGVAR(exclude_expsyms, $1)=['[_]+GLOBAL_OFFSET_TABLE_|[_]+GLOBAL__[FID]_.*|[_]+head_[A-Za-z0-9_]+_dll|[A-Za-z0-9_]+_dll_iname'] if $LD --help 2>&1 | $GREP 'auto-import' > /dev/null; then _LT_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' # If the export-symbols file already is a .def file (1st line # is EXPORTS), use it as is; otherwise, prepend... _LT_TAGVAR(archive_expsym_cmds, $1)='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then cp $export_symbols $output_objdir/$soname.def; else echo EXPORTS > $output_objdir/$soname.def; cat $export_symbols >> $output_objdir/$soname.def; fi~ $CC -shared $output_objdir/$soname.def $libobjs $deplibs $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' else _LT_TAGVAR(ld_shlibs, $1)=no fi ;; haiku*) _LT_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_TAGVAR(link_all_deplibs, $1)=yes ;; interix[[3-9]]*) _LT_TAGVAR(hardcode_direct, $1)=no _LT_TAGVAR(hardcode_shlibpath_var, $1)=no _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir' _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E' # Hack: On Interix 3.x, we cannot compile PIC because of a broken gcc. # Instead, shared libraries are loaded at an image base (0x10000000 by # default) and relocated if they conflict, which is a slow very memory # consuming and fragmenting process. To avoid this, we pick a random, # 256 KiB-aligned image base between 0x50000000 and 0x6FFC0000 at link # time. Moving up from 0x10000000 also allows more sbrk(2) space. _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='sed "s,^,_," $export_symbols >$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--retain-symbols-file,$output_objdir/$soname.expsym ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' ;; gnu* | linux* | tpf* | k*bsd*-gnu | kopensolaris*-gnu) tmp_diet=no if test "$host_os" = linux-dietlibc; then case $cc_basename in diet\ *) tmp_diet=yes;; # linux-dietlibc with static linking (!diet-dyn) esac fi if $LD --help 2>&1 | $EGREP ': supported targets:.* elf' > /dev/null \ && test "$tmp_diet" = no then tmp_addflag=' $pic_flag' tmp_sharedflag='-shared' case $cc_basename,$host_cpu in pgcc*) # Portland Group C compiler _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=' $pic_flag' ;; pgf77* | pgf90* | pgf95* | pgfortran*) # Portland Group f77 and f90 compilers _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' tmp_addflag=' $pic_flag -Mnomain' ;; ecc*,ia64* | icc*,ia64*) # Intel C compiler on ia64 tmp_addflag=' -i_dynamic' ;; efc*,ia64* | ifort*,ia64*) # Intel Fortran compiler on ia64 tmp_addflag=' -i_dynamic -nofor_main' ;; ifc* | ifort*) # Intel Fortran compiler tmp_addflag=' -nofor_main' ;; lf95*) # Lahey Fortran 8.1 _LT_TAGVAR(whole_archive_flag_spec, $1)= tmp_sharedflag='--shared' ;; xl[[cC]]* | bgxl[[cC]]* | mpixl[[cC]]*) # IBM XL C 8.0 on PPC (deal with xlf below) tmp_sharedflag='-qmkshrobj' tmp_addflag= ;; nvcc*) # Cuda Compiler Driver 2.2 _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' _LT_TAGVAR(compiler_needs_object, $1)=yes ;; esac case `$CC -V 2>&1 | sed 5q` in *Sun\ C*) # Sun C 5.9 _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`new_convenience=; for conv in $convenience\"\"; do test -z \"$conv\" || new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' _LT_TAGVAR(compiler_needs_object, $1)=yes tmp_sharedflag='-G' ;; *Sun\ F*) # Sun Fortran 8.3 tmp_sharedflag='-G' ;; esac _LT_TAGVAR(archive_cmds, $1)='$CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' if test "x$supports_anon_versioning" = xyes; then _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $output_objdir/$libname.ver~ cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~ echo "local: *; };" >> $output_objdir/$libname.ver~ $CC '"$tmp_sharedflag""$tmp_addflag"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-version-script ${wl}$output_objdir/$libname.ver -o $lib' fi case $cc_basename in xlf* | bgf* | bgxlf* | mpixlf*) # IBM XL Fortran 10.1 on PPC cannot create shared libs itself _LT_TAGVAR(whole_archive_flag_spec, $1)='--whole-archive$convenience --no-whole-archive' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)= _LT_TAGVAR(hardcode_libdir_flag_spec_ld, $1)='-rpath $libdir' _LT_TAGVAR(archive_cmds, $1)='$LD -shared $libobjs $deplibs $linker_flags -soname $soname -o $lib' if test "x$supports_anon_versioning" = xyes; then _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $output_objdir/$libname.ver~ cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~ echo "local: *; };" >> $output_objdir/$libname.ver~ $LD -shared $libobjs $deplibs $linker_flags -soname $soname -version-script $output_objdir/$libname.ver -o $lib' fi ;; esac else _LT_TAGVAR(ld_shlibs, $1)=no fi ;; netbsd* | netbsdelf*-gnu) if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then _LT_TAGVAR(archive_cmds, $1)='$LD -Bshareable $libobjs $deplibs $linker_flags -o $lib' wlarc= else _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' fi ;; solaris*) if $LD -v 2>&1 | $GREP 'BFD 2\.8' > /dev/null; then _LT_TAGVAR(ld_shlibs, $1)=no cat <<_LT_EOF 1>&2 *** Warning: The releases 2.8.* of the GNU linker cannot reliably *** create shared libraries on Solaris systems. Therefore, libtool *** is disabling shared libraries support. We urge you to upgrade GNU *** binutils to release 2.9.1 or newer. Another option is to modify *** your PATH or compiler configuration so that the native linker is *** used, and then restart. _LT_EOF elif $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' else _LT_TAGVAR(ld_shlibs, $1)=no fi ;; sysv5* | sco3.2v5* | sco5v6* | unixware* | OpenUNIX*) case `$LD -v 2>&1` in *\ [[01]].* | *\ 2.[[0-9]].* | *\ 2.1[[0-5]].*) _LT_TAGVAR(ld_shlibs, $1)=no cat <<_LT_EOF 1>&2 *** Warning: Releases of the GNU linker prior to 2.16.91.0.3 can not *** reliably create shared libraries on SCO systems. Therefore, libtool *** is disabling shared libraries support. We urge you to upgrade GNU *** binutils to release 2.16.91.0.3 or newer. Another option is to modify *** your PATH or compiler configuration so that the native linker is *** used, and then restart. _LT_EOF ;; *) # For security reasons, it is highly recommended that you always # use absolute paths for naming shared libraries, and exclude the # DT_RUNPATH tag from executables and libraries. But doing so # requires that you compile everything twice, which is a pain. if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir' _LT_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' else _LT_TAGVAR(ld_shlibs, $1)=no fi ;; esac ;; sunos4*) _LT_TAGVAR(archive_cmds, $1)='$LD -assert pure-text -Bshareable -o $lib $libobjs $deplibs $linker_flags' wlarc= _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_shlibpath_var, $1)=no ;; *) if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' else _LT_TAGVAR(ld_shlibs, $1)=no fi ;; esac if test "$_LT_TAGVAR(ld_shlibs, $1)" = no; then runpath_var= _LT_TAGVAR(hardcode_libdir_flag_spec, $1)= _LT_TAGVAR(export_dynamic_flag_spec, $1)= _LT_TAGVAR(whole_archive_flag_spec, $1)= fi else # PORTME fill in a description of your system's linker (not GNU ld) case $host_os in aix3*) _LT_TAGVAR(allow_undefined_flag, $1)=unsupported _LT_TAGVAR(always_export_symbols, $1)=yes _LT_TAGVAR(archive_expsym_cmds, $1)='$LD -o $output_objdir/$soname $libobjs $deplibs $linker_flags -bE:$export_symbols -T512 -H512 -bM:SRE~$AR $AR_FLAGS $lib $output_objdir/$soname' # Note: this linker hardcodes the directories in LIBPATH if there # are no directories specified by -L. _LT_TAGVAR(hardcode_minus_L, $1)=yes if test "$GCC" = yes && test -z "$lt_prog_compiler_static"; then # Neither direct hardcoding nor static linking is supported with a # broken collect2. _LT_TAGVAR(hardcode_direct, $1)=unsupported fi ;; aix[[4-9]]*) if test "$host_cpu" = ia64; then # On IA64, the linker does run time linking by default, so we don't # have to do anything special. aix_use_runtimelinking=no exp_sym_flag='-Bexport' no_entry_flag="" else # If we're using GNU nm, then we don't want the "-C" option. # -C means demangle to AIX nm, but means don't demangle with GNU nm # Also, AIX nm treats weak defined symbols like other global # defined symbols, whereas GNU nm marks them as "W". if $NM -V 2>&1 | $GREP 'GNU' > /dev/null; then _LT_TAGVAR(export_symbols_cmds, $1)='$NM -Bpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B") || (\$ 2 == "W")) && ([substr](\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols' else _LT_TAGVAR(export_symbols_cmds, $1)='$NM -BCpg $libobjs $convenience | awk '\''{ if (((\$ 2 == "T") || (\$ 2 == "D") || (\$ 2 == "B")) && ([substr](\$ 3,1,1) != ".")) { print \$ 3 } }'\'' | sort -u > $export_symbols' fi aix_use_runtimelinking=no # Test if we are trying to use run time linking or normal # AIX style linking. If -brtl is somewhere in LDFLAGS, we # need to do runtime linking. case $host_os in aix4.[[23]]|aix4.[[23]].*|aix[[5-9]]*) for ld_flag in $LDFLAGS; do if (test $ld_flag = "-brtl" || test $ld_flag = "-Wl,-brtl"); then aix_use_runtimelinking=yes break fi done ;; esac exp_sym_flag='-bexport' no_entry_flag='-bnoentry' fi # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library # or program results in "error TOC overflow" add -mminimal-toc to # CXXFLAGS/CFLAGS for g++/gcc. In the cases where that is not # enough to fix the problem, add -Wl,-bbigtoc to LDFLAGS. _LT_TAGVAR(archive_cmds, $1)='' _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_direct_absolute, $1)=yes _LT_TAGVAR(hardcode_libdir_separator, $1)=':' _LT_TAGVAR(link_all_deplibs, $1)=yes _LT_TAGVAR(file_list_spec, $1)='${wl}-f,' if test "$GCC" = yes; then case $host_os in aix4.[[012]]|aix4.[[012]].*) # We only want to do this on AIX 4.2 and lower, the check # below for broken collect2 doesn't work under 4.3+ collect2name=`${CC} -print-prog-name=collect2` if test -f "$collect2name" && strings "$collect2name" | $GREP resolve_lib_name >/dev/null then # We have reworked collect2 : else # We have old collect2 _LT_TAGVAR(hardcode_direct, $1)=unsupported # It fails to find uninstalled libraries when the uninstalled # path is not listed in the libpath. Setting hardcode_minus_L # to unsupported forces relinking _LT_TAGVAR(hardcode_minus_L, $1)=yes _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)= fi ;; esac shared_flag='-shared' if test "$aix_use_runtimelinking" = yes; then shared_flag="$shared_flag "'${wl}-G' fi _LT_TAGVAR(link_all_deplibs, $1)=no else # not using gcc if test "$host_cpu" = ia64; then # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release # chokes on -Wl,-G. The following line is correct: shared_flag='-G' else if test "$aix_use_runtimelinking" = yes; then shared_flag='${wl}-G' else shared_flag='${wl}-bM:SRE' fi fi fi _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-bexpall' # It seems that -bexpall does not export symbols beginning with # underscore (_), so it is better to generate a list of symbols to export. _LT_TAGVAR(always_export_symbols, $1)=yes if test "$aix_use_runtimelinking" = yes; then # Warning - without using the other runtime loading flags (-brtl), # -berok will link without error, but may produce a broken library. _LT_TAGVAR(allow_undefined_flag, $1)='-berok' # Determine the default libpath from the value encoded in an # empty executable. _LT_SYS_MODULE_PATH_AIX([$1]) _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-blibpath:$libdir:'"$aix_libpath" _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else if test "$host_cpu" = ia64; then _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-R $libdir:/usr/lib:/lib' _LT_TAGVAR(allow_undefined_flag, $1)="-z nodefs" _LT_TAGVAR(archive_expsym_cmds, $1)="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" else # Determine the default libpath from the value encoded in an # empty executable. _LT_SYS_MODULE_PATH_AIX([$1]) _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-blibpath:$libdir:'"$aix_libpath" # Warning - without using the other run time loading flags, # -berok will link without error, but may produce a broken library. _LT_TAGVAR(no_undefined_flag, $1)=' ${wl}-bernotok' _LT_TAGVAR(allow_undefined_flag, $1)=' ${wl}-berok' if test "$with_gnu_ld" = yes; then # We only use this code for GNU lds that support --whole-archive. _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive$convenience ${wl}--no-whole-archive' else # Exported symbols can be pulled into shared objects from archives _LT_TAGVAR(whole_archive_flag_spec, $1)='$convenience' fi _LT_TAGVAR(archive_cmds_need_lc, $1)=yes # This is similar to how AIX traditionally builds its shared libraries. _LT_TAGVAR(archive_expsym_cmds, $1)="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname' fi fi ;; amigaos*) case $host_cpu in powerpc) # see comment about AmigaOS4 .so support _LT_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='' ;; m68k) _LT_TAGVAR(archive_cmds, $1)='$RM $output_objdir/a2ixlibrary.data~$ECHO "#define NAME $libname" > $output_objdir/a2ixlibrary.data~$ECHO "#define LIBRARY_ID 1" >> $output_objdir/a2ixlibrary.data~$ECHO "#define VERSION $major" >> $output_objdir/a2ixlibrary.data~$ECHO "#define REVISION $revision" >> $output_objdir/a2ixlibrary.data~$AR $AR_FLAGS $lib $libobjs~$RANLIB $lib~(cd $output_objdir && a2ixlibrary -32)' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir' _LT_TAGVAR(hardcode_minus_L, $1)=yes ;; esac ;; bsdi[[45]]*) _LT_TAGVAR(export_dynamic_flag_spec, $1)=-rdynamic ;; cygwin* | mingw* | pw32* | cegcc*) # When not using gcc, we currently assume that we are using # Microsoft Visual C++. # hardcode_libdir_flag_spec is actually meaningless, as there is # no search path for DLLs. case $cc_basename in cl*) # Native MSVC _LT_TAGVAR(hardcode_libdir_flag_spec, $1)=' ' _LT_TAGVAR(allow_undefined_flag, $1)=unsupported _LT_TAGVAR(always_export_symbols, $1)=yes _LT_TAGVAR(file_list_spec, $1)='@' # Tell ltmain to make .lib files, not .a files. libext=lib # Tell ltmain to make .dll files, not .so files. shrext_cmds=".dll" # FIXME: Setting linknames here is a bad hack. _LT_TAGVAR(archive_cmds, $1)='$CC -o $output_objdir/$soname $libobjs $compiler_flags $deplibs -Wl,-dll~linknames=' _LT_TAGVAR(archive_expsym_cmds, $1)='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then sed -n -e 's/\\\\\\\(.*\\\\\\\)/-link\\\ -EXPORT:\\\\\\\1/' -e '1\\\!p' < $export_symbols > $output_objdir/$soname.exp; else sed -e 's/\\\\\\\(.*\\\\\\\)/-link\\\ -EXPORT:\\\\\\\1/' < $export_symbols > $output_objdir/$soname.exp; fi~ $CC -o $tool_output_objdir$soname $libobjs $compiler_flags $deplibs "@$tool_output_objdir$soname.exp" -Wl,-DLL,-IMPLIB:"$tool_output_objdir$libname.dll.lib"~ linknames=' # The linker will not automatically build a static lib if we build a DLL. # _LT_TAGVAR(old_archive_from_new_cmds, $1)='true' _LT_TAGVAR(enable_shared_with_static_runtimes, $1)=yes _LT_TAGVAR(export_symbols_cmds, $1)='$NM $libobjs $convenience | $global_symbol_pipe | $SED -e '\''/^[[BCDGRS]][[ ]]/s/.*[[ ]]\([[^ ]]*\)/\1,DATA/'\'' | $SED -e '\''/^[[AITW]][[ ]]/s/.*[[ ]]//'\'' | sort | uniq > $export_symbols' # Don't use ranlib _LT_TAGVAR(old_postinstall_cmds, $1)='chmod 644 $oldlib' _LT_TAGVAR(postlink_cmds, $1)='lt_outputfile="@OUTPUT@"~ lt_tool_outputfile="@TOOL_OUTPUT@"~ case $lt_outputfile in *.exe|*.EXE) ;; *) lt_outputfile="$lt_outputfile.exe" lt_tool_outputfile="$lt_tool_outputfile.exe" ;; esac~ if test "$MANIFEST_TOOL" != ":" && test -f "$lt_outputfile.manifest"; then $MANIFEST_TOOL -manifest "$lt_tool_outputfile.manifest" -outputresource:"$lt_tool_outputfile" || exit 1; $RM "$lt_outputfile.manifest"; fi' ;; *) # Assume MSVC wrapper _LT_TAGVAR(hardcode_libdir_flag_spec, $1)=' ' _LT_TAGVAR(allow_undefined_flag, $1)=unsupported # Tell ltmain to make .lib files, not .a files. libext=lib # Tell ltmain to make .dll files, not .so files. shrext_cmds=".dll" # FIXME: Setting linknames here is a bad hack. _LT_TAGVAR(archive_cmds, $1)='$CC -o $lib $libobjs $compiler_flags `func_echo_all "$deplibs" | $SED '\''s/ -lc$//'\''` -link -dll~linknames=' # The linker will automatically build a .lib file if we build a DLL. _LT_TAGVAR(old_archive_from_new_cmds, $1)='true' # FIXME: Should let the user specify the lib program. _LT_TAGVAR(old_archive_cmds, $1)='lib -OUT:$oldlib$oldobjs$old_deplibs' _LT_TAGVAR(enable_shared_with_static_runtimes, $1)=yes ;; esac ;; darwin* | rhapsody*) _LT_DARWIN_LINKER_FEATURES($1) ;; dgux*) _LT_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir' _LT_TAGVAR(hardcode_shlibpath_var, $1)=no ;; freebsd1*) _LT_TAGVAR(ld_shlibs, $1)=no ;; # FreeBSD 2.2.[012] allows us to include c++rt0.o to get C++ constructor # support. Future versions do this automatically, but an explicit c++rt0.o # does not break anything, and helps significantly (at the cost of a little # extra space). freebsd2.2*) _LT_TAGVAR(archive_cmds, $1)='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags /usr/lib/c++rt0.o' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir' _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_shlibpath_var, $1)=no ;; # Unfortunately, older versions of FreeBSD 2 do not have this feature. freebsd2*) _LT_TAGVAR(archive_cmds, $1)='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_minus_L, $1)=yes _LT_TAGVAR(hardcode_shlibpath_var, $1)=no ;; # FreeBSD 3 and greater uses gcc -shared to do shared libraries. freebsd* | dragonfly*) _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir' _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_shlibpath_var, $1)=no ;; hpux9*) if test "$GCC" = yes; then _LT_TAGVAR(archive_cmds, $1)='$RM $output_objdir/$soname~$CC -shared $pic_flag ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $libobjs $deplibs $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' else _LT_TAGVAR(archive_cmds, $1)='$RM $output_objdir/$soname~$LD -b +b $install_libdir -o $output_objdir/$soname $libobjs $deplibs $linker_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' fi _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}+b ${wl}$libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)=: _LT_TAGVAR(hardcode_direct, $1)=yes # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. _LT_TAGVAR(hardcode_minus_L, $1)=yes _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E' ;; hpux10*) if test "$GCC" = yes && test "$with_gnu_ld" = no; then _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' else _LT_TAGVAR(archive_cmds, $1)='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags' fi if test "$with_gnu_ld" = no; then _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}+b ${wl}$libdir' _LT_TAGVAR(hardcode_libdir_flag_spec_ld, $1)='+b $libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)=: _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_direct_absolute, $1)=yes _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E' # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. _LT_TAGVAR(hardcode_minus_L, $1)=yes fi ;; hpux11*) if test "$GCC" = yes && test "$with_gnu_ld" = no; then case $host_cpu in hppa*64*) _LT_TAGVAR(archive_cmds, $1)='$CC -shared ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' ;; ia64*) _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' ;; *) _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags' ;; esac else case $host_cpu in hppa*64*) _LT_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' ;; ia64*) _LT_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $libobjs $deplibs $compiler_flags' ;; *) m4_if($1, [], [ # Older versions of the 11.00 compiler do not understand -b yet # (HP92453-01 A.11.01.20 doesn't, HP92453-01 B.11.X.35175-35176.GP does) _LT_LINKER_OPTION([if $CC understands -b], _LT_TAGVAR(lt_cv_prog_compiler__b, $1), [-b], [_LT_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags'], [_LT_TAGVAR(archive_cmds, $1)='$LD -b +h $soname +b $install_libdir -o $lib $libobjs $deplibs $linker_flags'])], [_LT_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $libobjs $deplibs $compiler_flags']) ;; esac fi if test "$with_gnu_ld" = no; then _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}+b ${wl}$libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)=: case $host_cpu in hppa*64*|ia64*) _LT_TAGVAR(hardcode_direct, $1)=no _LT_TAGVAR(hardcode_shlibpath_var, $1)=no ;; *) _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_direct_absolute, $1)=yes _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E' # hardcode_minus_L: Not really in the search PATH, # but as the default location of the library. _LT_TAGVAR(hardcode_minus_L, $1)=yes ;; esac fi ;; irix5* | irix6* | nonstopux*) if test "$GCC" = yes; then _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' # Try to use the -exported_symbol ld option, if it does not # work, assume that -exports_file does not work either and # implicitly export all symbols. # This should be the same for all languages, so no per-tag cache variable. AC_CACHE_CHECK([whether the $host_os linker accepts -exported_symbol], [lt_cv_irix_exported_symbol], [save_LDFLAGS="$LDFLAGS" LDFLAGS="$LDFLAGS -shared ${wl}-exported_symbol ${wl}foo ${wl}-update_registry ${wl}/dev/null" AC_LINK_IFELSE( [AC_LANG_SOURCE( [AC_LANG_CASE([C], [[int foo (void) { return 0; }]], [C++], [[int foo (void) { return 0; }]], [Fortran 77], [[ subroutine foo end]], [Fortran], [[ subroutine foo end]])])], [lt_cv_irix_exported_symbol=yes], [lt_cv_irix_exported_symbol=no]) LDFLAGS="$save_LDFLAGS"]) if test "$lt_cv_irix_exported_symbol" = yes; then _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations ${wl}-exports_file ${wl}$export_symbols -o $lib' fi else _LT_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -exports_file $export_symbols -o $lib' fi _LT_TAGVAR(archive_cmds_need_lc, $1)='no' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)=: _LT_TAGVAR(inherit_rpath, $1)=yes _LT_TAGVAR(link_all_deplibs, $1)=yes ;; netbsd* | netbsdelf*-gnu) if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then _LT_TAGVAR(archive_cmds, $1)='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' # a.out else _LT_TAGVAR(archive_cmds, $1)='$LD -shared -o $lib $libobjs $deplibs $linker_flags' # ELF fi _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir' _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_shlibpath_var, $1)=no ;; newsos6) _LT_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)=: _LT_TAGVAR(hardcode_shlibpath_var, $1)=no ;; *nto* | *qnx*) ;; openbsd*) if test -f /usr/libexec/ld.so; then _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_shlibpath_var, $1)=no _LT_TAGVAR(hardcode_direct_absolute, $1)=yes if test -z "`echo __ELF__ | $CC -E - | $GREP __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags ${wl}-retain-symbols-file,$export_symbols' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir' _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E' else case $host_os in openbsd[[01]].* | openbsd2.[[0-7]] | openbsd2.[[0-7]].*) _LT_TAGVAR(archive_cmds, $1)='$LD -Bshareable -o $lib $libobjs $deplibs $linker_flags' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir' ;; *) _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag -o $lib $libobjs $deplibs $compiler_flags' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir' ;; esac fi else _LT_TAGVAR(ld_shlibs, $1)=no fi ;; os2*) _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir' _LT_TAGVAR(hardcode_minus_L, $1)=yes _LT_TAGVAR(allow_undefined_flag, $1)=unsupported _LT_TAGVAR(archive_cmds, $1)='$ECHO "LIBRARY $libname INITINSTANCE" > $output_objdir/$libname.def~$ECHO "DESCRIPTION \"$libname\"" >> $output_objdir/$libname.def~echo DATA >> $output_objdir/$libname.def~echo " SINGLE NONSHARED" >> $output_objdir/$libname.def~echo EXPORTS >> $output_objdir/$libname.def~emxexp $libobjs >> $output_objdir/$libname.def~$CC -Zdll -Zcrtdll -o $lib $libobjs $deplibs $compiler_flags $output_objdir/$libname.def' _LT_TAGVAR(old_archive_from_new_cmds, $1)='emximp -o $output_objdir/$libname.a $output_objdir/$libname.def' ;; osf3*) if test "$GCC" = yes; then _LT_TAGVAR(allow_undefined_flag, $1)=' ${wl}-expect_unresolved ${wl}\*' _LT_TAGVAR(archive_cmds, $1)='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' else _LT_TAGVAR(allow_undefined_flag, $1)=' -expect_unresolved \*' _LT_TAGVAR(archive_cmds, $1)='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' fi _LT_TAGVAR(archive_cmds_need_lc, $1)='no' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)=: ;; osf4* | osf5*) # as osf3* with the addition of -msym flag if test "$GCC" = yes; then _LT_TAGVAR(allow_undefined_flag, $1)=' ${wl}-expect_unresolved ${wl}\*' _LT_TAGVAR(archive_cmds, $1)='$CC -shared${allow_undefined_flag} $pic_flag $libobjs $deplibs $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir' else _LT_TAGVAR(allow_undefined_flag, $1)=' -expect_unresolved \*' _LT_TAGVAR(archive_cmds, $1)='$CC -shared${allow_undefined_flag} $libobjs $deplibs $compiler_flags -msym -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done; printf "%s\\n" "-hidden">> $lib.exp~ $CC -shared${allow_undefined_flag} ${wl}-input ${wl}$lib.exp $compiler_flags $libobjs $deplibs -soname $soname `test -n "$verstring" && $ECHO "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib~$RM $lib.exp' # Both c and cxx compiler support -rpath directly _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-rpath $libdir' fi _LT_TAGVAR(archive_cmds_need_lc, $1)='no' _LT_TAGVAR(hardcode_libdir_separator, $1)=: ;; solaris*) _LT_TAGVAR(no_undefined_flag, $1)=' -z defs' if test "$GCC" = yes; then wlarc='${wl}' _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag ${wl}-z ${wl}text ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags' _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ $CC -shared $pic_flag ${wl}-z ${wl}text ${wl}-M ${wl}$lib.exp ${wl}-h ${wl}$soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp' else case `$CC -V 2>&1` in *"Compilers 5.0"*) wlarc='' _LT_TAGVAR(archive_cmds, $1)='$LD -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $linker_flags' _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ $LD -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $linker_flags~$RM $lib.exp' ;; *) wlarc='${wl}' _LT_TAGVAR(archive_cmds, $1)='$CC -G${allow_undefined_flag} -h $soname -o $lib $libobjs $deplibs $compiler_flags' _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ $CC -G${allow_undefined_flag} -M $lib.exp -h $soname -o $lib $libobjs $deplibs $compiler_flags~$RM $lib.exp' ;; esac fi _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir' _LT_TAGVAR(hardcode_shlibpath_var, $1)=no case $host_os in solaris2.[[0-5]] | solaris2.[[0-5]].*) ;; *) # The compiler driver will combine and reorder linker options, # but understands `-z linker_flag'. GCC discards it without `$wl', # but is careful enough not to reorder. # Supported since Solaris 2.6 (maybe 2.5.1?) if test "$GCC" = yes; then _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract' else _LT_TAGVAR(whole_archive_flag_spec, $1)='-z allextract$convenience -z defaultextract' fi ;; esac _LT_TAGVAR(link_all_deplibs, $1)=yes ;; sunos4*) if test "x$host_vendor" = xsequent; then # Use $CC to link under sequent, because it throws in some extra .o # files that make .init and .fini sections work. _LT_TAGVAR(archive_cmds, $1)='$CC -G ${wl}-h $soname -o $lib $libobjs $deplibs $compiler_flags' else _LT_TAGVAR(archive_cmds, $1)='$LD -assert pure-text -Bstatic -o $lib $libobjs $deplibs $linker_flags' fi _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir' _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_minus_L, $1)=yes _LT_TAGVAR(hardcode_shlibpath_var, $1)=no ;; sysv4) case $host_vendor in sni) _LT_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' _LT_TAGVAR(hardcode_direct, $1)=yes # is this really true??? ;; siemens) ## LD is ld it makes a PLAMLIB ## CC just makes a GrossModule. _LT_TAGVAR(archive_cmds, $1)='$LD -G -o $lib $libobjs $deplibs $linker_flags' _LT_TAGVAR(reload_cmds, $1)='$CC -r -o $output$reload_objs' _LT_TAGVAR(hardcode_direct, $1)=no ;; motorola) _LT_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' _LT_TAGVAR(hardcode_direct, $1)=no #Motorola manual says yes, but my tests say they lie ;; esac runpath_var='LD_RUN_PATH' _LT_TAGVAR(hardcode_shlibpath_var, $1)=no ;; sysv4.3*) _LT_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' _LT_TAGVAR(hardcode_shlibpath_var, $1)=no _LT_TAGVAR(export_dynamic_flag_spec, $1)='-Bexport' ;; sysv4*MP*) if test -d /usr/nec; then _LT_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' _LT_TAGVAR(hardcode_shlibpath_var, $1)=no runpath_var=LD_RUN_PATH hardcode_runpath_var=yes _LT_TAGVAR(ld_shlibs, $1)=yes fi ;; sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[[01]].[[10]]* | unixware7* | sco3.2v5.0.[[024]]*) _LT_TAGVAR(no_undefined_flag, $1)='${wl}-z,text' _LT_TAGVAR(archive_cmds_need_lc, $1)=no _LT_TAGVAR(hardcode_shlibpath_var, $1)=no runpath_var='LD_RUN_PATH' if test "$GCC" = yes; then _LT_TAGVAR(archive_cmds, $1)='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' else _LT_TAGVAR(archive_cmds, $1)='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' fi ;; sysv5* | sco3.2v5* | sco5v6*) # Note: We can NOT use -z defs as we might desire, because we do not # link with -lc, and that would cause any symbols used from libc to # always be unresolved, which means just about no library would # ever link correctly. If we're not using GNU ld we use -z text # though, which does catch some bad symbols but isn't as heavy-handed # as -z defs. _LT_TAGVAR(no_undefined_flag, $1)='${wl}-z,text' _LT_TAGVAR(allow_undefined_flag, $1)='${wl}-z,nodefs' _LT_TAGVAR(archive_cmds_need_lc, $1)=no _LT_TAGVAR(hardcode_shlibpath_var, $1)=no _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-R,$libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)=':' _LT_TAGVAR(link_all_deplibs, $1)=yes _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-Bexport' runpath_var='LD_RUN_PATH' if test "$GCC" = yes; then _LT_TAGVAR(archive_cmds, $1)='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' else _LT_TAGVAR(archive_cmds, $1)='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' fi ;; uts4*) _LT_TAGVAR(archive_cmds, $1)='$LD -G -h $soname -o $lib $libobjs $deplibs $linker_flags' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir' _LT_TAGVAR(hardcode_shlibpath_var, $1)=no ;; *) _LT_TAGVAR(ld_shlibs, $1)=no ;; esac if test x$host_vendor = xsni; then case $host in sysv4 | sysv4.2uw2* | sysv4.3* | sysv5*) _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-Blargedynsym' ;; esac fi fi ]) AC_MSG_RESULT([$_LT_TAGVAR(ld_shlibs, $1)]) test "$_LT_TAGVAR(ld_shlibs, $1)" = no && can_build_shared=no _LT_TAGVAR(with_gnu_ld, $1)=$with_gnu_ld _LT_DECL([], [libext], [0], [Old archive suffix (normally "a")])dnl _LT_DECL([], [shrext_cmds], [1], [Shared library suffix (normally ".so")])dnl _LT_DECL([], [extract_expsyms_cmds], [2], [The commands to extract the exported symbol list from a shared archive]) # # Do we need to explicitly link libc? # case "x$_LT_TAGVAR(archive_cmds_need_lc, $1)" in x|xyes) # Assume -lc should be added _LT_TAGVAR(archive_cmds_need_lc, $1)=yes if test "$enable_shared" = yes && test "$GCC" = yes; then case $_LT_TAGVAR(archive_cmds, $1) in *'~'*) # FIXME: we may have to deal with multi-command sequences. ;; '$CC '*) # Test whether the compiler implicitly links with -lc since on some # systems, -lgcc has to come before -lc. If gcc already passes -lc # to ld, don't add -lc before -lgcc. AC_CACHE_CHECK([whether -lc should be explicitly linked in], [lt_cv_]_LT_TAGVAR(archive_cmds_need_lc, $1), [$RM conftest* echo "$lt_simple_compile_test_code" > conftest.$ac_ext if AC_TRY_EVAL(ac_compile) 2>conftest.err; then soname=conftest lib=conftest libobjs=conftest.$ac_objext deplibs= wl=$_LT_TAGVAR(lt_prog_compiler_wl, $1) pic_flag=$_LT_TAGVAR(lt_prog_compiler_pic, $1) compiler_flags=-v linker_flags=-v verstring= output_objdir=. libname=conftest lt_save_allow_undefined_flag=$_LT_TAGVAR(allow_undefined_flag, $1) _LT_TAGVAR(allow_undefined_flag, $1)= if AC_TRY_EVAL(_LT_TAGVAR(archive_cmds, $1) 2\>\&1 \| $GREP \" -lc \" \>/dev/null 2\>\&1) then lt_cv_[]_LT_TAGVAR(archive_cmds_need_lc, $1)=no else lt_cv_[]_LT_TAGVAR(archive_cmds_need_lc, $1)=yes fi _LT_TAGVAR(allow_undefined_flag, $1)=$lt_save_allow_undefined_flag else cat conftest.err 1>&5 fi $RM conftest* ]) _LT_TAGVAR(archive_cmds_need_lc, $1)=$lt_cv_[]_LT_TAGVAR(archive_cmds_need_lc, $1) ;; esac fi ;; esac _LT_TAGDECL([build_libtool_need_lc], [archive_cmds_need_lc], [0], [Whether or not to add -lc for building shared libraries]) _LT_TAGDECL([allow_libtool_libs_with_static_runtimes], [enable_shared_with_static_runtimes], [0], [Whether or not to disallow shared libs when runtime libs are static]) _LT_TAGDECL([], [export_dynamic_flag_spec], [1], [Compiler flag to allow reflexive dlopens]) _LT_TAGDECL([], [whole_archive_flag_spec], [1], [Compiler flag to generate shared objects directly from archives]) _LT_TAGDECL([], [compiler_needs_object], [1], [Whether the compiler copes with passing no objects directly]) _LT_TAGDECL([], [old_archive_from_new_cmds], [2], [Create an old-style archive from a shared archive]) _LT_TAGDECL([], [old_archive_from_expsyms_cmds], [2], [Create a temporary old-style archive to link instead of a shared archive]) _LT_TAGDECL([], [archive_cmds], [2], [Commands used to build a shared archive]) _LT_TAGDECL([], [archive_expsym_cmds], [2]) _LT_TAGDECL([], [module_cmds], [2], [Commands used to build a loadable module if different from building a shared archive.]) _LT_TAGDECL([], [module_expsym_cmds], [2]) _LT_TAGDECL([], [with_gnu_ld], [1], [Whether we are building with GNU ld or not]) _LT_TAGDECL([], [allow_undefined_flag], [1], [Flag that allows shared libraries with undefined symbols to be built]) _LT_TAGDECL([], [no_undefined_flag], [1], [Flag that enforces no undefined symbols]) _LT_TAGDECL([], [hardcode_libdir_flag_spec], [1], [Flag to hardcode $libdir into a binary during linking. This must work even if $libdir does not exist]) _LT_TAGDECL([], [hardcode_libdir_flag_spec_ld], [1], [[If ld is used when linking, flag to hardcode $libdir into a binary during linking. This must work even if $libdir does not exist]]) _LT_TAGDECL([], [hardcode_libdir_separator], [1], [Whether we need a single "-rpath" flag with a separated argument]) _LT_TAGDECL([], [hardcode_direct], [0], [Set to "yes" if using DIR/libNAME${shared_ext} during linking hardcodes DIR into the resulting binary]) _LT_TAGDECL([], [hardcode_direct_absolute], [0], [Set to "yes" if using DIR/libNAME${shared_ext} during linking hardcodes DIR into the resulting binary and the resulting library dependency is "absolute", i.e impossible to change by setting ${shlibpath_var} if the library is relocated]) _LT_TAGDECL([], [hardcode_minus_L], [0], [Set to "yes" if using the -LDIR flag during linking hardcodes DIR into the resulting binary]) _LT_TAGDECL([], [hardcode_shlibpath_var], [0], [Set to "yes" if using SHLIBPATH_VAR=DIR during linking hardcodes DIR into the resulting binary]) _LT_TAGDECL([], [hardcode_automatic], [0], [Set to "yes" if building a shared library automatically hardcodes DIR into the library and all subsequent libraries and executables linked against it]) _LT_TAGDECL([], [inherit_rpath], [0], [Set to yes if linker adds runtime paths of dependent libraries to runtime path list]) _LT_TAGDECL([], [link_all_deplibs], [0], [Whether libtool must link a program against all its dependency libraries]) _LT_TAGDECL([], [always_export_symbols], [0], [Set to "yes" if exported symbols are required]) _LT_TAGDECL([], [export_symbols_cmds], [2], [The commands to list exported symbols]) _LT_TAGDECL([], [exclude_expsyms], [1], [Symbols that should not be listed in the preloaded symbols]) _LT_TAGDECL([], [include_expsyms], [1], [Symbols that must always be exported]) _LT_TAGDECL([], [prelink_cmds], [2], [Commands necessary for linking programs (against libraries) with templates]) _LT_TAGDECL([], [postlink_cmds], [2], [Commands necessary for finishing linking programs]) _LT_TAGDECL([], [file_list_spec], [1], [Specify filename containing input files]) dnl FIXME: Not yet implemented dnl _LT_TAGDECL([], [thread_safe_flag_spec], [1], dnl [Compiler flag to generate thread safe objects]) ])# _LT_LINKER_SHLIBS # _LT_LANG_C_CONFIG([TAG]) # ------------------------ # Ensure that the configuration variables for a C compiler are suitably # defined. These variables are subsequently used by _LT_CONFIG to write # the compiler configuration to `libtool'. m4_defun([_LT_LANG_C_CONFIG], [m4_require([_LT_DECL_EGREP])dnl lt_save_CC="$CC" AC_LANG_PUSH(C) # Source file extension for C test sources. ac_ext=c # Object file extension for compiled C test sources. objext=o _LT_TAGVAR(objext, $1)=$objext # Code to be used in simple compile tests lt_simple_compile_test_code="int some_variable = 0;" # Code to be used in simple link tests lt_simple_link_test_code='int main(){return(0);}' _LT_TAG_COMPILER # Save the default compiler, since it gets overwritten when the other # tags are being tested, and _LT_TAGVAR(compiler, []) is a NOP. compiler_DEFAULT=$CC # save warnings/boilerplate of simple test code _LT_COMPILER_BOILERPLATE _LT_LINKER_BOILERPLATE if test -n "$compiler"; then _LT_COMPILER_NO_RTTI($1) _LT_COMPILER_PIC($1) _LT_COMPILER_C_O($1) _LT_COMPILER_FILE_LOCKS($1) _LT_LINKER_SHLIBS($1) _LT_SYS_DYNAMIC_LINKER($1) _LT_LINKER_HARDCODE_LIBPATH($1) LT_SYS_DLOPEN_SELF _LT_CMD_STRIPLIB # Report which library types will actually be built AC_MSG_CHECKING([if libtool supports shared libraries]) AC_MSG_RESULT([$can_build_shared]) AC_MSG_CHECKING([whether to build shared libraries]) test "$can_build_shared" = "no" && enable_shared=no # On AIX, shared libraries and static libraries use the same namespace, and # are all built from PIC. case $host_os in aix3*) test "$enable_shared" = yes && enable_static=no if test -n "$RANLIB"; then archive_cmds="$archive_cmds~\$RANLIB \$lib" postinstall_cmds='$RANLIB $lib' fi ;; aix[[4-9]]*) if test "$host_cpu" != ia64 && test "$aix_use_runtimelinking" = no ; then test "$enable_shared" = yes && enable_static=no fi ;; esac AC_MSG_RESULT([$enable_shared]) AC_MSG_CHECKING([whether to build static libraries]) # Make sure either enable_shared or enable_static is yes. test "$enable_shared" = yes || enable_static=yes AC_MSG_RESULT([$enable_static]) _LT_CONFIG($1) fi AC_LANG_POP CC="$lt_save_CC" ])# _LT_LANG_C_CONFIG # _LT_LANG_CXX_CONFIG([TAG]) # -------------------------- # Ensure that the configuration variables for a C++ compiler are suitably # defined. These variables are subsequently used by _LT_CONFIG to write # the compiler configuration to `libtool'. m4_defun([_LT_LANG_CXX_CONFIG], [m4_require([_LT_FILEUTILS_DEFAULTS])dnl m4_require([_LT_DECL_EGREP])dnl m4_require([_LT_PATH_MANIFEST_TOOL])dnl if test -n "$CXX" && ( test "X$CXX" != "Xno" && ( (test "X$CXX" = "Xg++" && `g++ -v >/dev/null 2>&1` ) || (test "X$CXX" != "Xg++"))) ; then AC_PROG_CXXCPP else _lt_caught_CXX_error=yes fi AC_LANG_PUSH(C++) _LT_TAGVAR(archive_cmds_need_lc, $1)=no _LT_TAGVAR(allow_undefined_flag, $1)= _LT_TAGVAR(always_export_symbols, $1)=no _LT_TAGVAR(archive_expsym_cmds, $1)= _LT_TAGVAR(compiler_needs_object, $1)=no _LT_TAGVAR(export_dynamic_flag_spec, $1)= _LT_TAGVAR(hardcode_direct, $1)=no _LT_TAGVAR(hardcode_direct_absolute, $1)=no _LT_TAGVAR(hardcode_libdir_flag_spec, $1)= _LT_TAGVAR(hardcode_libdir_flag_spec_ld, $1)= _LT_TAGVAR(hardcode_libdir_separator, $1)= _LT_TAGVAR(hardcode_minus_L, $1)=no _LT_TAGVAR(hardcode_shlibpath_var, $1)=unsupported _LT_TAGVAR(hardcode_automatic, $1)=no _LT_TAGVAR(inherit_rpath, $1)=no _LT_TAGVAR(module_cmds, $1)= _LT_TAGVAR(module_expsym_cmds, $1)= _LT_TAGVAR(link_all_deplibs, $1)=unknown _LT_TAGVAR(old_archive_cmds, $1)=$old_archive_cmds _LT_TAGVAR(reload_flag, $1)=$reload_flag _LT_TAGVAR(reload_cmds, $1)=$reload_cmds _LT_TAGVAR(no_undefined_flag, $1)= _LT_TAGVAR(whole_archive_flag_spec, $1)= _LT_TAGVAR(enable_shared_with_static_runtimes, $1)=no # Source file extension for C++ test sources. ac_ext=cpp # Object file extension for compiled C++ test sources. objext=o _LT_TAGVAR(objext, $1)=$objext # No sense in running all these tests if we already determined that # the CXX compiler isn't working. Some variables (like enable_shared) # are currently assumed to apply to all compilers on this platform, # and will be corrupted by setting them based on a non-working compiler. if test "$_lt_caught_CXX_error" != yes; then # Code to be used in simple compile tests lt_simple_compile_test_code="int some_variable = 0;" # Code to be used in simple link tests lt_simple_link_test_code='int main(int, char *[[]]) { return(0); }' # ltmain only uses $CC for tagged configurations so make sure $CC is set. _LT_TAG_COMPILER # save warnings/boilerplate of simple test code _LT_COMPILER_BOILERPLATE _LT_LINKER_BOILERPLATE # Allow CC to be a program name with arguments. lt_save_CC=$CC lt_save_CFLAGS=$CFLAGS lt_save_LD=$LD lt_save_GCC=$GCC GCC=$GXX lt_save_with_gnu_ld=$with_gnu_ld lt_save_path_LD=$lt_cv_path_LD if test -n "${lt_cv_prog_gnu_ldcxx+set}"; then lt_cv_prog_gnu_ld=$lt_cv_prog_gnu_ldcxx else $as_unset lt_cv_prog_gnu_ld fi if test -n "${lt_cv_path_LDCXX+set}"; then lt_cv_path_LD=$lt_cv_path_LDCXX else $as_unset lt_cv_path_LD fi test -z "${LDCXX+set}" || LD=$LDCXX CC=${CXX-"c++"} CFLAGS=$CXXFLAGS compiler=$CC _LT_TAGVAR(compiler, $1)=$CC _LT_CC_BASENAME([$compiler]) if test -n "$compiler"; then # We don't want -fno-exception when compiling C++ code, so set the # no_builtin_flag separately if test "$GXX" = yes; then _LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)=' -fno-builtin' else _LT_TAGVAR(lt_prog_compiler_no_builtin_flag, $1)= fi if test "$GXX" = yes; then # Set up default GNU C++ configuration LT_PATH_LD # Check if GNU C++ uses GNU ld as the underlying linker, since the # archiving commands below assume that GNU ld is being used. if test "$with_gnu_ld" = yes; then _LT_TAGVAR(archive_cmds, $1)='$CC $pic_flag -shared -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC $pic_flag -shared -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir' _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-dynamic' # If archive_cmds runs LD, not CC, wlarc should be empty # XXX I think wlarc can be eliminated in ltcf-cxx, but I need to # investigate it a little bit more. (MM) wlarc='${wl}' # ancient GNU ld didn't support --whole-archive et. al. if eval "`$CC -print-prog-name=ld` --help 2>&1" | $GREP 'no-whole-archive' > /dev/null; then _LT_TAGVAR(whole_archive_flag_spec, $1)="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive' else _LT_TAGVAR(whole_archive_flag_spec, $1)= fi else with_gnu_ld=no wlarc= # A generic and very simple default shared library creation # command for GNU C++ for the case where it uses the native # linker, instead of GNU ld. If possible, this setting should # overridden to take advantage of the native linker features on # the platform it is being used on. _LT_TAGVAR(archive_cmds, $1)='$CC -shared -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -o $lib' fi # Commands to make compiler produce verbose output that lists # what "hidden" libraries, object files and flags are used when # linking a shared library. output_verbose_link_cmd='$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP -v "^Configured with:" | $GREP "\-L"' else GXX=no with_gnu_ld=no wlarc= fi # PORTME: fill in a description of your system's C++ link characteristics AC_MSG_CHECKING([whether the $compiler linker ($LD) supports shared libraries]) _LT_TAGVAR(ld_shlibs, $1)=yes case $host_os in aix3*) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; aix[[4-9]]*) if test "$host_cpu" = ia64; then # On IA64, the linker does run time linking by default, so we don't # have to do anything special. aix_use_runtimelinking=no exp_sym_flag='-Bexport' no_entry_flag="" else aix_use_runtimelinking=no # Test if we are trying to use run time linking or normal # AIX style linking. If -brtl is somewhere in LDFLAGS, we # need to do runtime linking. case $host_os in aix4.[[23]]|aix4.[[23]].*|aix[[5-9]]*) for ld_flag in $LDFLAGS; do case $ld_flag in *-brtl*) aix_use_runtimelinking=yes break ;; esac done ;; esac exp_sym_flag='-bexport' no_entry_flag='-bnoentry' fi # When large executables or shared objects are built, AIX ld can # have problems creating the table of contents. If linking a library # or program results in "error TOC overflow" add -mminimal-toc to # CXXFLAGS/CFLAGS for g++/gcc. In the cases where that is not # enough to fix the problem, add -Wl,-bbigtoc to LDFLAGS. _LT_TAGVAR(archive_cmds, $1)='' _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_direct_absolute, $1)=yes _LT_TAGVAR(hardcode_libdir_separator, $1)=':' _LT_TAGVAR(link_all_deplibs, $1)=yes _LT_TAGVAR(file_list_spec, $1)='${wl}-f,' if test "$GXX" = yes; then case $host_os in aix4.[[012]]|aix4.[[012]].*) # We only want to do this on AIX 4.2 and lower, the check # below for broken collect2 doesn't work under 4.3+ collect2name=`${CC} -print-prog-name=collect2` if test -f "$collect2name" && strings "$collect2name" | $GREP resolve_lib_name >/dev/null then # We have reworked collect2 : else # We have old collect2 _LT_TAGVAR(hardcode_direct, $1)=unsupported # It fails to find uninstalled libraries when the uninstalled # path is not listed in the libpath. Setting hardcode_minus_L # to unsupported forces relinking _LT_TAGVAR(hardcode_minus_L, $1)=yes _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)= fi esac shared_flag='-shared' if test "$aix_use_runtimelinking" = yes; then shared_flag="$shared_flag "'${wl}-G' fi else # not using gcc if test "$host_cpu" = ia64; then # VisualAge C++, Version 5.5 for AIX 5L for IA-64, Beta 3 Release # chokes on -Wl,-G. The following line is correct: shared_flag='-G' else if test "$aix_use_runtimelinking" = yes; then shared_flag='${wl}-G' else shared_flag='${wl}-bM:SRE' fi fi fi _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-bexpall' # It seems that -bexpall does not export symbols beginning with # underscore (_), so it is better to generate a list of symbols to # export. _LT_TAGVAR(always_export_symbols, $1)=yes if test "$aix_use_runtimelinking" = yes; then # Warning - without using the other runtime loading flags (-brtl), # -berok will link without error, but may produce a broken library. _LT_TAGVAR(allow_undefined_flag, $1)='-berok' # Determine the default libpath from the value encoded in an empty # executable. _LT_SYS_MODULE_PATH_AIX([$1]) _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-blibpath:$libdir:'"$aix_libpath" _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags `if test "x${allow_undefined_flag}" != "x"; then func_echo_all "${wl}${allow_undefined_flag}"; else :; fi` '"\${wl}$exp_sym_flag:\$export_symbols $shared_flag" else if test "$host_cpu" = ia64; then _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-R $libdir:/usr/lib:/lib' _LT_TAGVAR(allow_undefined_flag, $1)="-z nodefs" _LT_TAGVAR(archive_expsym_cmds, $1)="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs '"\${wl}$no_entry_flag"' $compiler_flags ${wl}${allow_undefined_flag} '"\${wl}$exp_sym_flag:\$export_symbols" else # Determine the default libpath from the value encoded in an # empty executable. _LT_SYS_MODULE_PATH_AIX([$1]) _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-blibpath:$libdir:'"$aix_libpath" # Warning - without using the other run time loading flags, # -berok will link without error, but may produce a broken library. _LT_TAGVAR(no_undefined_flag, $1)=' ${wl}-bernotok' _LT_TAGVAR(allow_undefined_flag, $1)=' ${wl}-berok' if test "$with_gnu_ld" = yes; then # We only use this code for GNU lds that support --whole-archive. _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive$convenience ${wl}--no-whole-archive' else # Exported symbols can be pulled into shared objects from archives _LT_TAGVAR(whole_archive_flag_spec, $1)='$convenience' fi _LT_TAGVAR(archive_cmds_need_lc, $1)=yes # This is similar to how AIX traditionally builds its shared # libraries. _LT_TAGVAR(archive_expsym_cmds, $1)="\$CC $shared_flag"' -o $output_objdir/$soname $libobjs $deplibs ${wl}-bnoentry $compiler_flags ${wl}-bE:$export_symbols${allow_undefined_flag}~$AR $AR_FLAGS $output_objdir/$libname$release.a $output_objdir/$soname' fi fi ;; beos*) if $LD --help 2>&1 | $GREP ': supported targets:.* elf' > /dev/null; then _LT_TAGVAR(allow_undefined_flag, $1)=unsupported # Joseph Beckenbach says some releases of gcc # support --undefined. This deserves some investigation. FIXME _LT_TAGVAR(archive_cmds, $1)='$CC -nostart $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' else _LT_TAGVAR(ld_shlibs, $1)=no fi ;; chorus*) case $cc_basename in *) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; esac ;; cygwin* | mingw* | pw32* | cegcc*) case $GXX,$cc_basename in ,cl* | no,cl*) # Native MSVC # hardcode_libdir_flag_spec is actually meaningless, as there is # no search path for DLLs. _LT_TAGVAR(hardcode_libdir_flag_spec, $1)=' ' _LT_TAGVAR(allow_undefined_flag, $1)=unsupported _LT_TAGVAR(always_export_symbols, $1)=yes _LT_TAGVAR(file_list_spec, $1)='@' # Tell ltmain to make .lib files, not .a files. libext=lib # Tell ltmain to make .dll files, not .so files. shrext_cmds=".dll" # FIXME: Setting linknames here is a bad hack. _LT_TAGVAR(archive_cmds, $1)='$CC -o $output_objdir/$soname $libobjs $compiler_flags $deplibs -Wl,-dll~linknames=' _LT_TAGVAR(archive_expsym_cmds, $1)='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then $SED -n -e 's/\\\\\\\(.*\\\\\\\)/-link\\\ -EXPORT:\\\\\\\1/' -e '1\\\!p' < $export_symbols > $output_objdir/$soname.exp; else $SED -e 's/\\\\\\\(.*\\\\\\\)/-link\\\ -EXPORT:\\\\\\\1/' < $export_symbols > $output_objdir/$soname.exp; fi~ $CC -o $tool_output_objdir$soname $libobjs $compiler_flags $deplibs "@$tool_output_objdir$soname.exp" -Wl,-DLL,-IMPLIB:"$tool_output_objdir$libname.dll.lib"~ linknames=' # The linker will not automatically build a static lib if we build a DLL. # _LT_TAGVAR(old_archive_from_new_cmds, $1)='true' _LT_TAGVAR(enable_shared_with_static_runtimes, $1)=yes # Don't use ranlib _LT_TAGVAR(old_postinstall_cmds, $1)='chmod 644 $oldlib' _LT_TAGVAR(postlink_cmds, $1)='lt_outputfile="@OUTPUT@"~ lt_tool_outputfile="@TOOL_OUTPUT@"~ case $lt_outputfile in *.exe|*.EXE) ;; *) lt_outputfile="$lt_outputfile.exe" lt_tool_outputfile="$lt_tool_outputfile.exe" ;; esac~ func_to_tool_file "$lt_outputfile"~ if test "$MANIFEST_TOOL" != ":" && test -f "$lt_outputfile.manifest"; then $MANIFEST_TOOL -manifest "$lt_tool_outputfile.manifest" -outputresource:"$lt_tool_outputfile" || exit 1; $RM "$lt_outputfile.manifest"; fi' ;; *) # g++ # _LT_TAGVAR(hardcode_libdir_flag_spec, $1) is actually meaningless, # as there is no search path for DLLs. _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-L$libdir' _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-all-symbols' _LT_TAGVAR(allow_undefined_flag, $1)=unsupported _LT_TAGVAR(always_export_symbols, $1)=no _LT_TAGVAR(enable_shared_with_static_runtimes, $1)=yes if $LD --help 2>&1 | $GREP 'auto-import' > /dev/null; then _LT_TAGVAR(archive_cmds, $1)='$CC -shared -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' # If the export-symbols file already is a .def file (1st line # is EXPORTS), use it as is; otherwise, prepend... _LT_TAGVAR(archive_expsym_cmds, $1)='if test "x`$SED 1q $export_symbols`" = xEXPORTS; then cp $export_symbols $output_objdir/$soname.def; else echo EXPORTS > $output_objdir/$soname.def; cat $export_symbols >> $output_objdir/$soname.def; fi~ $CC -shared -nostdlib $output_objdir/$soname.def $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -o $output_objdir/$soname ${wl}--enable-auto-image-base -Xlinker --out-implib -Xlinker $lib' else _LT_TAGVAR(ld_shlibs, $1)=no fi ;; esac ;; darwin* | rhapsody*) _LT_DARWIN_LINKER_FEATURES($1) ;; dgux*) case $cc_basename in ec++*) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; ghcx*) # Green Hills C++ Compiler # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; *) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; esac ;; freebsd[[12]]*) # C++ shared libraries reported to be fairly broken before # switch to ELF _LT_TAGVAR(ld_shlibs, $1)=no ;; freebsd-elf*) _LT_TAGVAR(archive_cmds_need_lc, $1)=no ;; freebsd* | dragonfly*) # FreeBSD 3 and later use GNU C++ and GNU ld with standard ELF # conventions _LT_TAGVAR(ld_shlibs, $1)=yes ;; gnu*) ;; haiku*) _LT_TAGVAR(archive_cmds, $1)='$CC -shared $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_TAGVAR(link_all_deplibs, $1)=yes ;; hpux9*) _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}+b ${wl}$libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)=: _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E' _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_minus_L, $1)=yes # Not in the search PATH, # but as the default # location of the library. case $cc_basename in CC*) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; aCC*) _LT_TAGVAR(archive_cmds, $1)='$RM $output_objdir/$soname~$CC -b ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' # Commands to make compiler produce verbose output that lists # what "hidden" libraries, object files and flags are used when # linking a shared library. # # There doesn't appear to be a way to prevent this compiler from # explicitly linking system object files so we need to strip them # from the output so that they don't get included in the library # dependencies. output_verbose_link_cmd='templist=`($CC -b $CFLAGS -v conftest.$objext 2>&1) | $EGREP "\-L"`; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "$list"' ;; *) if test "$GXX" = yes; then _LT_TAGVAR(archive_cmds, $1)='$RM $output_objdir/$soname~$CC -shared -nostdlib $pic_flag ${wl}+b ${wl}$install_libdir -o $output_objdir/$soname $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~test $output_objdir/$soname = $lib || mv $output_objdir/$soname $lib' else # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no fi ;; esac ;; hpux10*|hpux11*) if test $with_gnu_ld = no; then _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}+b ${wl}$libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)=: case $host_cpu in hppa*64*|ia64*) ;; *) _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E' ;; esac fi case $host_cpu in hppa*64*|ia64*) _LT_TAGVAR(hardcode_direct, $1)=no _LT_TAGVAR(hardcode_shlibpath_var, $1)=no ;; *) _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_direct_absolute, $1)=yes _LT_TAGVAR(hardcode_minus_L, $1)=yes # Not in the search PATH, # but as the default # location of the library. ;; esac case $cc_basename in CC*) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; aCC*) case $host_cpu in hppa*64*) _LT_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' ;; ia64*) _LT_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' ;; *) _LT_TAGVAR(archive_cmds, $1)='$CC -b ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' ;; esac # Commands to make compiler produce verbose output that lists # what "hidden" libraries, object files and flags are used when # linking a shared library. # # There doesn't appear to be a way to prevent this compiler from # explicitly linking system object files so we need to strip them # from the output so that they don't get included in the library # dependencies. output_verbose_link_cmd='templist=`($CC -b $CFLAGS -v conftest.$objext 2>&1) | $GREP "\-L"`; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "$list"' ;; *) if test "$GXX" = yes; then if test $with_gnu_ld = no; then case $host_cpu in hppa*64*) _LT_TAGVAR(archive_cmds, $1)='$CC -shared -nostdlib -fPIC ${wl}+h ${wl}$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' ;; ia64*) _LT_TAGVAR(archive_cmds, $1)='$CC -shared -nostdlib $pic_flag ${wl}+h ${wl}$soname ${wl}+nodefaultrpath -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' ;; *) _LT_TAGVAR(archive_cmds, $1)='$CC -shared -nostdlib $pic_flag ${wl}+h ${wl}$soname ${wl}+b ${wl}$install_libdir -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' ;; esac fi else # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no fi ;; esac ;; interix[[3-9]]*) _LT_TAGVAR(hardcode_direct, $1)=no _LT_TAGVAR(hardcode_shlibpath_var, $1)=no _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir' _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E' # Hack: On Interix 3.x, we cannot compile PIC because of a broken gcc. # Instead, shared libraries are loaded at an image base (0x10000000 by # default) and relocated if they conflict, which is a slow very memory # consuming and fragmenting process. To avoid this, we pick a random, # 256 KiB-aligned image base between 0x50000000 and 0x6FFC0000 at link # time. Moving up from 0x10000000 also allows more sbrk(2) space. _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='sed "s,^,_," $export_symbols >$output_objdir/$soname.expsym~$CC -shared $pic_flag $libobjs $deplibs $compiler_flags ${wl}-h,$soname ${wl}--retain-symbols-file,$output_objdir/$soname.expsym ${wl}--image-base,`expr ${RANDOM-$$} % 4096 / 2 \* 262144 + 1342177280` -o $lib' ;; irix5* | irix6*) case $cc_basename in CC*) # SGI C++ _LT_TAGVAR(archive_cmds, $1)='$CC -shared -all -multigot $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' # Archives containing C++ object files must be created using # "CC -ar", where "CC" is the IRIX C++ compiler. This is # necessary to make sure instantiated templates are included # in the archive. _LT_TAGVAR(old_archive_cmds, $1)='$CC -ar -WR,-u -o $oldlib $oldobjs' ;; *) if test "$GXX" = yes; then if test "$with_gnu_ld" = no; then _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' else _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag -nostdlib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` -o $lib' fi fi _LT_TAGVAR(link_all_deplibs, $1)=yes ;; esac _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)=: _LT_TAGVAR(inherit_rpath, $1)=yes ;; linux* | k*bsd*-gnu | kopensolaris*-gnu) case $cc_basename in KCC*) # Kuck and Associates, Inc. (KAI) C++ Compiler # KCC will only create a shared library if the output file # ends with ".so" (or ".sl" for HP-UX), so rename the library # to its proper name (with version) after linking. _LT_TAGVAR(archive_cmds, $1)='tempext=`echo $shared_ext | $SED -e '\''s/\([[^()0-9A-Za-z{}]]\)/\\\\\1/g'\''`; templib=`echo $lib | $SED -e "s/\${tempext}\..*/.so/"`; $CC $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags --soname $soname -o \$templib; mv \$templib $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='tempext=`echo $shared_ext | $SED -e '\''s/\([[^()0-9A-Za-z{}]]\)/\\\\\1/g'\''`; templib=`echo $lib | $SED -e "s/\${tempext}\..*/.so/"`; $CC $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags --soname $soname -o \$templib ${wl}-retain-symbols-file,$export_symbols; mv \$templib $lib' # Commands to make compiler produce verbose output that lists # what "hidden" libraries, object files and flags are used when # linking a shared library. # # There doesn't appear to be a way to prevent this compiler from # explicitly linking system object files so we need to strip them # from the output so that they don't get included in the library # dependencies. output_verbose_link_cmd='templist=`$CC $CFLAGS -v conftest.$objext -o libconftest$shared_ext 2>&1 | $GREP "ld"`; rm -f libconftest$shared_ext; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "$list"' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir' _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-dynamic' # Archives containing C++ object files must be created using # "CC -Bstatic", where "CC" is the KAI C++ compiler. _LT_TAGVAR(old_archive_cmds, $1)='$CC -Bstatic -o $oldlib $oldobjs' ;; icpc* | ecpc* ) # Intel C++ with_gnu_ld=yes # version 8.0 and above of icpc choke on multiply defined symbols # if we add $predep_objects and $postdep_objects, however 7.1 and # earlier do not add the objects themselves. case `$CC -V 2>&1` in *"Version 7."*) _LT_TAGVAR(archive_cmds, $1)='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' ;; *) # Version 8.0 or newer tmp_idyn= case $host_cpu in ia64*) tmp_idyn=' -i_dynamic';; esac _LT_TAGVAR(archive_cmds, $1)='$CC -shared'"$tmp_idyn"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared'"$tmp_idyn"' $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-retain-symbols-file $wl$export_symbols -o $lib' ;; esac _LT_TAGVAR(archive_cmds_need_lc, $1)=no _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir' _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-dynamic' _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive$convenience ${wl}--no-whole-archive' ;; pgCC* | pgcpp*) # Portland Group C++ compiler case `$CC -V` in *pgCC\ [[1-5]].* | *pgcpp\ [[1-5]].*) _LT_TAGVAR(prelink_cmds, $1)='tpldir=Template.dir~ rm -rf $tpldir~ $CC --prelink_objects --instantiation_dir $tpldir $objs $libobjs $compile_deplibs~ compile_command="$compile_command `find $tpldir -name \*.o | sort | $NL2SP`"' _LT_TAGVAR(old_archive_cmds, $1)='tpldir=Template.dir~ rm -rf $tpldir~ $CC --prelink_objects --instantiation_dir $tpldir $oldobjs$old_deplibs~ $AR $AR_FLAGS $oldlib$oldobjs$old_deplibs `find $tpldir -name \*.o | sort | $NL2SP`~ $RANLIB $oldlib' _LT_TAGVAR(archive_cmds, $1)='tpldir=Template.dir~ rm -rf $tpldir~ $CC --prelink_objects --instantiation_dir $tpldir $predep_objects $libobjs $deplibs $convenience $postdep_objects~ $CC -shared $pic_flag $predep_objects $libobjs $deplibs `find $tpldir -name \*.o | sort | $NL2SP` $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='tpldir=Template.dir~ rm -rf $tpldir~ $CC --prelink_objects --instantiation_dir $tpldir $predep_objects $libobjs $deplibs $convenience $postdep_objects~ $CC -shared $pic_flag $predep_objects $libobjs $deplibs `find $tpldir -name \*.o | sort | $NL2SP` $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname ${wl}-retain-symbols-file ${wl}$export_symbols -o $lib' ;; *) # Version 6 and above use weak symbols _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $pic_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname ${wl}-retain-symbols-file ${wl}$export_symbols -o $lib' ;; esac _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}--rpath ${wl}$libdir' _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-dynamic' _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`for conv in $convenience\"\"; do test -n \"$conv\" && new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' ;; cxx*) # Compaq C++ _LT_TAGVAR(archive_cmds, $1)='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $wl$soname -o $lib ${wl}-retain-symbols-file $wl$export_symbols' runpath_var=LD_RUN_PATH _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-rpath $libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)=: # Commands to make compiler produce verbose output that lists # what "hidden" libraries, object files and flags are used when # linking a shared library. # # There doesn't appear to be a way to prevent this compiler from # explicitly linking system object files so we need to strip them # from the output so that they don't get included in the library # dependencies. output_verbose_link_cmd='templist=`$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP "ld"`; templist=`func_echo_all "$templist" | $SED "s/\(^.*ld.*\)\( .*ld .*$\)/\1/"`; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "X$list" | $Xsed' ;; xl* | mpixl* | bgxl*) # IBM XL 8.0 on PPC, with GNU ld _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir' _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}--export-dynamic' _LT_TAGVAR(archive_cmds, $1)='$CC -qmkshrobj $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname -o $lib' if test "x$supports_anon_versioning" = xyes; then _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $output_objdir/$libname.ver~ cat $export_symbols | sed -e "s/\(.*\)/\1;/" >> $output_objdir/$libname.ver~ echo "local: *; };" >> $output_objdir/$libname.ver~ $CC -qmkshrobj $libobjs $deplibs $compiler_flags ${wl}-soname $wl$soname ${wl}-version-script ${wl}$output_objdir/$libname.ver -o $lib' fi ;; *) case `$CC -V 2>&1 | sed 5q` in *Sun\ C*) # Sun C++ 5.9 _LT_TAGVAR(no_undefined_flag, $1)=' -zdefs' _LT_TAGVAR(archive_cmds, $1)='$CC -G${allow_undefined_flag} -h$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -G${allow_undefined_flag} -h$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-retain-symbols-file ${wl}$export_symbols' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir' _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}--whole-archive`new_convenience=; for conv in $convenience\"\"; do test -z \"$conv\" || new_convenience=\"$new_convenience,$conv\"; done; func_echo_all \"$new_convenience\"` ${wl}--no-whole-archive' _LT_TAGVAR(compiler_needs_object, $1)=yes # Not sure whether something based on # $CC $CFLAGS -v conftest.$objext -o libconftest$shared_ext 2>&1 # would be better. output_verbose_link_cmd='func_echo_all' # Archives containing C++ object files must be created using # "CC -xar", where "CC" is the Sun C++ compiler. This is # necessary to make sure instantiated templates are included # in the archive. _LT_TAGVAR(old_archive_cmds, $1)='$CC -xar -o $oldlib $oldobjs' ;; esac ;; esac ;; lynxos*) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; m88k*) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; mvs*) case $cc_basename in cxx*) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; *) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; esac ;; netbsd*) if echo __ELF__ | $CC -E - | $GREP __ELF__ >/dev/null; then _LT_TAGVAR(archive_cmds, $1)='$LD -Bshareable -o $lib $predep_objects $libobjs $deplibs $postdep_objects $linker_flags' wlarc= _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir' _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_shlibpath_var, $1)=no fi # Workaround some broken pre-1.5 toolchains output_verbose_link_cmd='$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP conftest.$objext | $SED -e "s:-lgcc -lc -lgcc::"' ;; *nto* | *qnx*) _LT_TAGVAR(ld_shlibs, $1)=yes ;; openbsd2*) # C++ shared libraries are fairly broken _LT_TAGVAR(ld_shlibs, $1)=no ;; openbsd*) if test -f /usr/libexec/ld.so; then _LT_TAGVAR(hardcode_direct, $1)=yes _LT_TAGVAR(hardcode_shlibpath_var, $1)=no _LT_TAGVAR(hardcode_direct_absolute, $1)=yes _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -o $lib' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir' if test -z "`echo __ELF__ | $CC -E - | grep __ELF__`" || test "$host_os-$host_cpu" = "openbsd2.8-powerpc"; then _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared $pic_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-retain-symbols-file,$export_symbols -o $lib' _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-E' _LT_TAGVAR(whole_archive_flag_spec, $1)="$wlarc"'--whole-archive$convenience '"$wlarc"'--no-whole-archive' fi output_verbose_link_cmd=func_echo_all else _LT_TAGVAR(ld_shlibs, $1)=no fi ;; osf3* | osf4* | osf5*) case $cc_basename in KCC*) # Kuck and Associates, Inc. (KAI) C++ Compiler # KCC will only create a shared library if the output file # ends with ".so" (or ".sl" for HP-UX), so rename the library # to its proper name (with version) after linking. _LT_TAGVAR(archive_cmds, $1)='tempext=`echo $shared_ext | $SED -e '\''s/\([[^()0-9A-Za-z{}]]\)/\\\\\1/g'\''`; templib=`echo "$lib" | $SED -e "s/\${tempext}\..*/.so/"`; $CC $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags --soname $soname -o \$templib; mv \$templib $lib' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath,$libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)=: # Archives containing C++ object files must be created using # the KAI C++ compiler. case $host in osf3*) _LT_TAGVAR(old_archive_cmds, $1)='$CC -Bstatic -o $oldlib $oldobjs' ;; *) _LT_TAGVAR(old_archive_cmds, $1)='$CC -o $oldlib $oldobjs' ;; esac ;; RCC*) # Rational C++ 2.4.1 # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; cxx*) case $host in osf3*) _LT_TAGVAR(allow_undefined_flag, $1)=' ${wl}-expect_unresolved ${wl}\*' _LT_TAGVAR(archive_cmds, $1)='$CC -shared${allow_undefined_flag} $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname $soname `test -n "$verstring" && func_echo_all "${wl}-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir' ;; *) _LT_TAGVAR(allow_undefined_flag, $1)=' -expect_unresolved \*' _LT_TAGVAR(archive_cmds, $1)='$CC -shared${allow_undefined_flag} $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -msym -soname $soname `test -n "$verstring" && func_echo_all "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='for i in `cat $export_symbols`; do printf "%s %s\\n" -exported_symbol "\$i" >> $lib.exp; done~ echo "-hidden">> $lib.exp~ $CC -shared$allow_undefined_flag $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags -msym -soname $soname ${wl}-input ${wl}$lib.exp `test -n "$verstring" && $ECHO "-set_version $verstring"` -update_registry ${output_objdir}/so_locations -o $lib~ $RM $lib.exp' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-rpath $libdir' ;; esac _LT_TAGVAR(hardcode_libdir_separator, $1)=: # Commands to make compiler produce verbose output that lists # what "hidden" libraries, object files and flags are used when # linking a shared library. # # There doesn't appear to be a way to prevent this compiler from # explicitly linking system object files so we need to strip them # from the output so that they don't get included in the library # dependencies. output_verbose_link_cmd='templist=`$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP "ld" | $GREP -v "ld:"`; templist=`func_echo_all "$templist" | $SED "s/\(^.*ld.*\)\( .*ld.*$\)/\1/"`; list=""; for z in $templist; do case $z in conftest.$objext) list="$list $z";; *.$objext);; *) list="$list $z";;esac; done; func_echo_all "$list"' ;; *) if test "$GXX" = yes && test "$with_gnu_ld" = no; then _LT_TAGVAR(allow_undefined_flag, $1)=' ${wl}-expect_unresolved ${wl}\*' case $host in osf3*) _LT_TAGVAR(archive_cmds, $1)='$CC -shared -nostdlib ${allow_undefined_flag} $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' ;; *) _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag -nostdlib ${allow_undefined_flag} $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-msym ${wl}-soname ${wl}$soname `test -n "$verstring" && func_echo_all "${wl}-set_version ${wl}$verstring"` ${wl}-update_registry ${wl}${output_objdir}/so_locations -o $lib' ;; esac _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-rpath ${wl}$libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)=: # Commands to make compiler produce verbose output that lists # what "hidden" libraries, object files and flags are used when # linking a shared library. output_verbose_link_cmd='$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP -v "^Configured with:" | $GREP "\-L"' else # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no fi ;; esac ;; psos*) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; sunos4*) case $cc_basename in CC*) # Sun C++ 4.x # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; lcc*) # Lucid # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; *) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; esac ;; solaris*) case $cc_basename in CC* | sunCC*) # Sun C++ 4.2, 5.x and Centerline C++ _LT_TAGVAR(archive_cmds_need_lc,$1)=yes _LT_TAGVAR(no_undefined_flag, $1)=' -zdefs' _LT_TAGVAR(archive_cmds, $1)='$CC -G${allow_undefined_flag} -h$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags' _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ $CC -G${allow_undefined_flag} ${wl}-M ${wl}$lib.exp -h$soname -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~$RM $lib.exp' _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='-R$libdir' _LT_TAGVAR(hardcode_shlibpath_var, $1)=no case $host_os in solaris2.[[0-5]] | solaris2.[[0-5]].*) ;; *) # The compiler driver will combine and reorder linker options, # but understands `-z linker_flag'. # Supported since Solaris 2.6 (maybe 2.5.1?) _LT_TAGVAR(whole_archive_flag_spec, $1)='-z allextract$convenience -z defaultextract' ;; esac _LT_TAGVAR(link_all_deplibs, $1)=yes output_verbose_link_cmd='func_echo_all' # Archives containing C++ object files must be created using # "CC -xar", where "CC" is the Sun C++ compiler. This is # necessary to make sure instantiated templates are included # in the archive. _LT_TAGVAR(old_archive_cmds, $1)='$CC -xar -o $oldlib $oldobjs' ;; gcx*) # Green Hills C++ Compiler _LT_TAGVAR(archive_cmds, $1)='$CC -shared $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-h $wl$soname -o $lib' # The C++ compiler must be used to create the archive. _LT_TAGVAR(old_archive_cmds, $1)='$CC $LDFLAGS -archive -o $oldlib $oldobjs' ;; *) # GNU C++ compiler with Solaris linker if test "$GXX" = yes && test "$with_gnu_ld" = no; then _LT_TAGVAR(no_undefined_flag, $1)=' ${wl}-z ${wl}defs' if $CC --version | $GREP -v '^2\.7' > /dev/null; then _LT_TAGVAR(archive_cmds, $1)='$CC -shared $pic_flag -nostdlib $LDFLAGS $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-h $wl$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ $CC -shared $pic_flag -nostdlib ${wl}-M $wl$lib.exp -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~$RM $lib.exp' # Commands to make compiler produce verbose output that lists # what "hidden" libraries, object files and flags are used when # linking a shared library. output_verbose_link_cmd='$CC -shared $CFLAGS -v conftest.$objext 2>&1 | $GREP -v "^Configured with:" | $GREP "\-L"' else # g++ 2.7 appears to require `-G' NOT `-shared' on this # platform. _LT_TAGVAR(archive_cmds, $1)='$CC -G -nostdlib $LDFLAGS $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags ${wl}-h $wl$soname -o $lib' _LT_TAGVAR(archive_expsym_cmds, $1)='echo "{ global:" > $lib.exp~cat $export_symbols | $SED -e "s/\(.*\)/\1;/" >> $lib.exp~echo "local: *; };" >> $lib.exp~ $CC -G -nostdlib ${wl}-M $wl$lib.exp -o $lib $predep_objects $libobjs $deplibs $postdep_objects $compiler_flags~$RM $lib.exp' # Commands to make compiler produce verbose output that lists # what "hidden" libraries, object files and flags are used when # linking a shared library. output_verbose_link_cmd='$CC -G $CFLAGS -v conftest.$objext 2>&1 | $GREP -v "^Configured with:" | $GREP "\-L"' fi _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-R $wl$libdir' case $host_os in solaris2.[[0-5]] | solaris2.[[0-5]].*) ;; *) _LT_TAGVAR(whole_archive_flag_spec, $1)='${wl}-z ${wl}allextract$convenience ${wl}-z ${wl}defaultextract' ;; esac fi ;; esac ;; sysv4*uw2* | sysv5OpenUNIX* | sysv5UnixWare7.[[01]].[[10]]* | unixware7* | sco3.2v5.0.[[024]]*) _LT_TAGVAR(no_undefined_flag, $1)='${wl}-z,text' _LT_TAGVAR(archive_cmds_need_lc, $1)=no _LT_TAGVAR(hardcode_shlibpath_var, $1)=no runpath_var='LD_RUN_PATH' case $cc_basename in CC*) _LT_TAGVAR(archive_cmds, $1)='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' ;; *) _LT_TAGVAR(archive_cmds, $1)='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' ;; esac ;; sysv5* | sco3.2v5* | sco5v6*) # Note: We can NOT use -z defs as we might desire, because we do not # link with -lc, and that would cause any symbols used from libc to # always be unresolved, which means just about no library would # ever link correctly. If we're not using GNU ld we use -z text # though, which does catch some bad symbols but isn't as heavy-handed # as -z defs. _LT_TAGVAR(no_undefined_flag, $1)='${wl}-z,text' _LT_TAGVAR(allow_undefined_flag, $1)='${wl}-z,nodefs' _LT_TAGVAR(archive_cmds_need_lc, $1)=no _LT_TAGVAR(hardcode_shlibpath_var, $1)=no _LT_TAGVAR(hardcode_libdir_flag_spec, $1)='${wl}-R,$libdir' _LT_TAGVAR(hardcode_libdir_separator, $1)=':' _LT_TAGVAR(link_all_deplibs, $1)=yes _LT_TAGVAR(export_dynamic_flag_spec, $1)='${wl}-Bexport' runpath_var='LD_RUN_PATH' case $cc_basename in CC*) _LT_TAGVAR(archive_cmds, $1)='$CC -G ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -G ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' _LT_TAGVAR(old_archive_cmds, $1)='$CC -Tprelink_objects $oldobjs~ '"$_LT_TAGVAR(old_archive_cmds, $1)" _LT_TAGVAR(reload_cmds, $1)='$CC -Tprelink_objects $reload_objs~ '"$_LT_TAGVAR(reload_cmds, $1)" ;; *) _LT_TAGVAR(archive_cmds, $1)='$CC -shared ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' _LT_TAGVAR(archive_expsym_cmds, $1)='$CC -shared ${wl}-Bexport:$export_symbols ${wl}-h,$soname -o $lib $libobjs $deplibs $compiler_flags' ;; esac ;; tandem*) case $cc_basename in NCC*) # NonStop-UX NCC 3.20 # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; *) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; esac ;; vxworks*) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; *) # FIXME: insert proper C++ library support _LT_TAGVAR(ld_shlibs, $1)=no ;; esac AC_MSG_RESULT([$_LT_TAGVAR(ld_shlibs, $1)]) test "$_LT_TAGVAR(ld_shlibs, $1)" = no && can_build_shared=no _LT_TAGVAR(GCC, $1)="$GXX" _LT_TAGVAR(LD, $1)="$LD" ## CAVEAT EMPTOR: ## There is no encapsulation within the following macros, do not change ## the running order or otherwise move them around unless you know exactly ## what you are doing... _LT_SYS_HIDDEN_LIBDEPS($1) _LT_COMPILER_PIC($1) _LT_COMPILER_C_O($1) _LT_COMPILER_FILE_LOCKS($1) _LT_LINKER_SHLIBS($1) _LT_SYS_DYNAMIC_LINKER($1) _LT_LINKER_HARDCODE_LIBPATH($1) _LT_CONFIG($1) fi # test -n "$compiler" CC=$lt_save_CC CFLAGS=$lt_save_CFLAGS LDCXX=$LD LD=$lt_save_LD GCC=$lt_save_GCC with_gnu_ld=$lt_save_with_gnu_ld lt_cv_path_LDCXX=$lt_cv_path_LD lt_cv_path_LD=$lt_save_path_LD lt_cv_prog_gnu_ldcxx=$lt_cv_prog_gnu_ld lt_cv_prog_gnu_ld=$lt_save_with_gnu_ld fi # test "$_lt_caught_CXX_error" != yes AC_LANG_POP ])# _LT_LANG_CXX_CONFIG # _LT_FUNC_STRIPNAME_CNF # ---------------------- # func_stripname_cnf prefix suffix name # strip PREFIX and SUFFIX off of NAME. # PREFIX and SUFFIX must not contain globbing or regex special # characters, hashes, percent signs, but SUFFIX may contain a leading # dot (in which case that matches only a dot). # # This function is identical to the (non-XSI) version of func_stripname, # except this one can be used by m4 code that may be executed by configure, # rather than the libtool script. m4_defun([_LT_FUNC_STRIPNAME_CNF],[dnl AC_REQUIRE([_LT_DECL_SED]) AC_REQUIRE([_LT_PROG_ECHO_BACKSLASH]) func_stripname_cnf () { case ${2} in .*) func_stripname_result=`$ECHO "${3}" | $SED "s%^${1}%%; s%\\\\${2}\$%%"`;; *) func_stripname_result=`$ECHO "${3}" | $SED "s%^${1}%%; s%${2}\$%%"`;; esac } # func_stripname_cnf ])# _LT_FUNC_STRIPNAME_CNF # _LT_SYS_HIDDEN_LIBDEPS([TAGNAME]) # --------------------------------- # Figure out "hidden" library dependencies from verbose # compiler output when linking a shared library. # Parse the compiler output and extract the necessary # objects, libraries and library flags. m4_defun([_LT_SYS_HIDDEN_LIBDEPS], [m4_require([_LT_FILEUTILS_DEFAULTS])dnl AC_REQUIRE([_LT_FUNC_STRIPNAME_CNF])dnl # Dependencies to place before and after the object being linked: _LT_TAGVAR(predep_objects, $1)= _LT_TAGVAR(postdep_objects, $1)= _LT_TAGVAR(predeps, $1)= _LT_TAGVAR(postdeps, $1)= _LT_TAGVAR(compiler_lib_search_path, $1)= dnl we can't use the lt_simple_compile_test_code here, dnl because it contains code intended for an executable, dnl not a library. It's possible we should let each dnl tag define a new lt_????_link_test_code variable, dnl but it's only used here... m4_if([$1], [], [cat > conftest.$ac_ext <<_LT_EOF int a; void foo (void) { a = 0; } _LT_EOF ], [$1], [CXX], [cat > conftest.$ac_ext <<_LT_EOF class Foo { public: Foo (void) { a = 0; } private: int a; }; _LT_EOF ], [$1], [F77], [cat > conftest.$ac_ext <<_LT_EOF subroutine foo implicit none integer*4 a a=0 return end _LT_EOF ], [$1], [FC], [cat > conftest.$ac_ext <<_LT_EOF subroutine foo implicit none integer a a=0 return end _LT_EOF ], [$1], [GCJ], [cat > conftest.$ac_ext <<_LT_EOF public class foo { private int a; public void bar (void) { a = 0; } }; _LT_EOF ]) _lt_libdeps_save_CFLAGS=$CFLAGS case "$CC $CFLAGS " in #( *\ -flto*\ *) CFLAGS="$CFLAGS -fno-lto" ;; *\ -fwhopr*\ *) CFLAGS="$CFLAGS -fno-whopr" ;; esac dnl Parse the compiler output and extract the necessary dnl objects, libraries and library flags. if AC_TRY_EVAL(ac_compile); then # Parse the compiler output and extract the necessary # objects, libraries and library flags. # Sentinel used to keep track of whether or not we are before # the conftest object file. pre_test_object_deps_done=no for p in `eval "$output_verbose_link_cmd"`; do case ${prev}${p} in -L* | -R* | -l*) # Some compilers place space between "-{L,R}" and the path. # Remove the space. if test $p = "-L" || test $p = "-R"; then prev=$p continue fi # Expand the sysroot to ease extracting the directories later. if test -z "$prev"; then case $p in -L*) func_stripname_cnf '-L' '' "$p"; prev=-L; p=$func_stripname_result ;; -R*) func_stripname_cnf '-R' '' "$p"; prev=-R; p=$func_stripname_result ;; -l*) func_stripname_cnf '-l' '' "$p"; prev=-l; p=$func_stripname_result ;; esac fi case $p in =*) func_stripname_cnf '=' '' "$p"; p=$lt_sysroot$func_stripname_result ;; esac if test "$pre_test_object_deps_done" = no; then case ${prev} in -L | -R) # Internal compiler library paths should come after those # provided the user. The postdeps already come after the # user supplied libs so there is no need to process them. if test -z "$_LT_TAGVAR(compiler_lib_search_path, $1)"; then _LT_TAGVAR(compiler_lib_search_path, $1)="${prev}${p}" else _LT_TAGVAR(compiler_lib_search_path, $1)="${_LT_TAGVAR(compiler_lib_search_path, $1)} ${prev}${p}" fi ;; # The "-l" case would never come before the object being # linked, so don't bother handling this case. esac else if test -z "$_LT_TAGVAR(postdeps, $1)"; then _LT_TAGVAR(postdeps, $1)="${prev}${p}" else _LT_TAGVAR(postdeps, $1)="${_LT_TAGVAR(postdeps, $1)} ${prev}${p}" fi fi prev= ;; *.lto.$objext) ;; # Ignore GCC LTO objects *.$objext) # This assumes that the test object file only shows up # once in the compiler output. if test "$p" = "conftest.$objext"; then pre_test_object_deps_done=yes continue fi if test "$pre_test_object_deps_done" = no; then if test -z "$_LT_TAGVAR(predep_objects, $1)"; then _LT_TAGVAR(predep_objects, $1)="$p" else _LT_TAGVAR(predep_objects, $1)="$_LT_TAGVAR(predep_objects, $1) $p" fi else if test -z "$_LT_TAGVAR(postdep_objects, $1)"; then _LT_TAGVAR(postdep_objects, $1)="$p" else _LT_TAGVAR(postdep_objects, $1)="$_LT_TAGVAR(postdep_objects, $1) $p" fi fi ;; *) ;; # Ignore the rest. esac done # Clean up. rm -f a.out a.exe else echo "libtool.m4: error: problem compiling $1 test program" fi $RM -f confest.$objext CFLAGS=$_lt_libdeps_save_CFLAGS # PORTME: override above test on systems where it is broken m4_if([$1], [CXX], [case $host_os in interix[[3-9]]*) # Interix 3.5 installs completely hosed .la files for C++, so rather than # hack all around it, let's just trust "g++" to DTRT. _LT_TAGVAR(predep_objects,$1)= _LT_TAGVAR(postdep_objects,$1)= _LT_TAGVAR(postdeps,$1)= ;; linux*) case `$CC -V 2>&1 | sed 5q` in *Sun\ C*) # Sun C++ 5.9 # The more standards-conforming stlport4 library is # incompatible with the Cstd library. Avoid specifying # it if it's in CXXFLAGS. Ignore libCrun as # -library=stlport4 depends on it. case " $CXX $CXXFLAGS " in *" -library=stlport4 "*) solaris_use_stlport4=yes ;; esac if test "$solaris_use_stlport4" != yes; then _LT_TAGVAR(postdeps,$1)='-library=Cstd -library=Crun' fi ;; esac ;; solaris*) case $cc_basename in CC* | sunCC*) # The more standards-conforming stlport4 library is # incompatible with the Cstd library. Avoid specifying # it if it's in CXXFLAGS. Ignore libCrun as # -library=stlport4 depends on it. case " $CXX $CXXFLAGS " in *" -library=stlport4 "*) solaris_use_stlport4=yes ;; esac # Adding this requires a known-good setup of shared libraries for # Sun compiler versions before 5.6, else PIC objects from an old # archive will be linked into the output, leading to subtle bugs. if test "$solaris_use_stlport4" != yes; then _LT_TAGVAR(postdeps,$1)='-library=Cstd -library=Crun' fi ;; esac ;; esac ]) case " $_LT_TAGVAR(postdeps, $1) " in *" -lc "*) _LT_TAGVAR(archive_cmds_need_lc, $1)=no ;; esac _LT_TAGVAR(compiler_lib_search_dirs, $1)= if test -n "${_LT_TAGVAR(compiler_lib_search_path, $1)}"; then _LT_TAGVAR(compiler_lib_search_dirs, $1)=`echo " ${_LT_TAGVAR(compiler_lib_search_path, $1)}" | ${SED} -e 's! -L! !g' -e 's!^ !!'` fi _LT_TAGDECL([], [compiler_lib_search_dirs], [1], [The directories searched by this compiler when creating a shared library]) _LT_TAGDECL([], [predep_objects], [1], [Dependencies to place before and after the objects being linked to create a shared library]) _LT_TAGDECL([], [postdep_objects], [1]) _LT_TAGDECL([], [predeps], [1]) _LT_TAGDECL([], [postdeps], [1]) _LT_TAGDECL([], [compiler_lib_search_path], [1], [The library search path used internally by the compiler when linking a shared library]) ])# _LT_SYS_HIDDEN_LIBDEPS # _LT_LANG_F77_CONFIG([TAG]) # -------------------------- # Ensure that the configuration variables for a Fortran 77 compiler are # suitably defined. These variables are subsequently used by _LT_CONFIG # to write the compiler configuration to `libtool'. m4_defun([_LT_LANG_F77_CONFIG], [AC_LANG_PUSH(Fortran 77) if test -z "$F77" || test "X$F77" = "Xno"; then _lt_disable_F77=yes fi _LT_TAGVAR(archive_cmds_need_lc, $1)=no _LT_TAGVAR(allow_undefined_flag, $1)= _LT_TAGVAR(always_export_symbols, $1)=no _LT_TAGVAR(archive_expsym_cmds, $1)= _LT_TAGVAR(export_dynamic_flag_spec, $1)= _LT_TAGVAR(hardcode_direct, $1)=no _LT_TAGVAR(hardcode_direct_absolute, $1)=no _LT_TAGVAR(hardcode_libdir_flag_spec, $1)= _LT_TAGVAR(hardcode_libdir_flag_spec_ld, $1)= _LT_TAGVAR(hardcode_libdir_separator, $1)= _LT_TAGVAR(hardcode_minus_L, $1)=no _LT_TAGVAR(hardcode_automatic, $1)=no _LT_TAGVAR(inherit_rpath, $1)=no _LT_TAGVAR(module_cmds, $1)= _LT_TAGVAR(module_expsym_cmds, $1)= _LT_TAGVAR(link_all_deplibs, $1)=unknown _LT_TAGVAR(old_archive_cmds, $1)=$old_archive_cmds _LT_TAGVAR(reload_flag, $1)=$reload_flag _LT_TAGVAR(reload_cmds, $1)=$reload_cmds _LT_TAGVAR(no_undefined_flag, $1)= _LT_TAGVAR(whole_archive_flag_spec, $1)= _LT_TAGVAR(enable_shared_with_static_runtimes, $1)=no # Source file extension for f77 test sources. ac_ext=f # Object file extension for compiled f77 test sources. objext=o _LT_TAGVAR(objext, $1)=$objext # No sense in running all these tests if we already determined that # the F77 compiler isn't working. Some variables (like enable_shared) # are currently assumed to apply to all compilers on this platform, # and will be corrupted by setting them based on a non-working compiler. if test "$_lt_disable_F77" != yes; then # Code to be used in simple compile tests lt_simple_compile_test_code="\ subroutine t return end " # Code to be used in simple link tests lt_simple_link_test_code="\ program t end " # ltmain only uses $CC for tagged configurations so make sure $CC is set. _LT_TAG_COMPILER # save warnings/boilerplate of simple test code _LT_COMPILER_BOILERPLATE _LT_LINKER_BOILERPLATE # Allow CC to be a program name with arguments. lt_save_CC="$CC" lt_save_GCC=$GCC lt_save_CFLAGS=$CFLAGS CC=${F77-"f77"} CFLAGS=$FFLAGS compiler=$CC _LT_TAGVAR(compiler, $1)=$CC _LT_CC_BASENAME([$compiler]) GCC=$G77 if test -n "$compiler"; then AC_MSG_CHECKING([if libtool supports shared libraries]) AC_MSG_RESULT([$can_build_shared]) AC_MSG_CHECKING([whether to build shared libraries]) test "$can_build_shared" = "no" && enable_shared=no # On AIX, shared libraries and static libraries use the same namespace, and # are all built from PIC. case $host_os in aix3*) test "$enable_shared" = yes && enable_static=no if test -n "$RANLIB"; then archive_cmds="$archive_cmds~\$RANLIB \$lib" postinstall_cmds='$RANLIB $lib' fi ;; aix[[4-9]]*) if test "$host_cpu" != ia64 && test "$aix_use_runtimelinking" = no ; then test "$enable_shared" = yes && enable_static=no fi ;; esac AC_MSG_RESULT([$enable_shared]) AC_MSG_CHECKING([whether to build static libraries]) # Make sure either enable_shared or enable_static is yes. test "$enable_shared" = yes || enable_static=yes AC_MSG_RESULT([$enable_static]) _LT_TAGVAR(GCC, $1)="$G77" _LT_TAGVAR(LD, $1)="$LD" ## CAVEAT EMPTOR: ## There is no encapsulation within the following macros, do not change ## the running order or otherwise move them around unless you know exactly ## what you are doing... _LT_COMPILER_PIC($1) _LT_COMPILER_C_O($1) _LT_COMPILER_FILE_LOCKS($1) _LT_LINKER_SHLIBS($1) _LT_SYS_DYNAMIC_LINKER($1) _LT_LINKER_HARDCODE_LIBPATH($1) _LT_CONFIG($1) fi # test -n "$compiler" GCC=$lt_save_GCC CC="$lt_save_CC" CFLAGS="$lt_save_CFLAGS" fi # test "$_lt_disable_F77" != yes AC_LANG_POP ])# _LT_LANG_F77_CONFIG # _LT_LANG_FC_CONFIG([TAG]) # ------------------------- # Ensure that the configuration variables for a Fortran compiler are # suitably defined. These variables are subsequently used by _LT_CONFIG # to write the compiler configuration to `libtool'. m4_defun([_LT_LANG_FC_CONFIG], [AC_LANG_PUSH(Fortran) if test -z "$FC" || test "X$FC" = "Xno"; then _lt_disable_FC=yes fi _LT_TAGVAR(archive_cmds_need_lc, $1)=no _LT_TAGVAR(allow_undefined_flag, $1)= _LT_TAGVAR(always_export_symbols, $1)=no _LT_TAGVAR(archive_expsym_cmds, $1)= _LT_TAGVAR(export_dynamic_flag_spec, $1)= _LT_TAGVAR(hardcode_direct, $1)=no _LT_TAGVAR(hardcode_direct_absolute, $1)=no _LT_TAGVAR(hardcode_libdir_flag_spec, $1)= _LT_TAGVAR(hardcode_libdir_flag_spec_ld, $1)= _LT_TAGVAR(hardcode_libdir_separator, $1)= _LT_TAGVAR(hardcode_minus_L, $1)=no _LT_TAGVAR(hardcode_automatic, $1)=no _LT_TAGVAR(inherit_rpath, $1)=no _LT_TAGVAR(module_cmds, $1)= _LT_TAGVAR(module_expsym_cmds, $1)= _LT_TAGVAR(link_all_deplibs, $1)=unknown _LT_TAGVAR(old_archive_cmds, $1)=$old_archive_cmds _LT_TAGVAR(reload_flag, $1)=$reload_flag _LT_TAGVAR(reload_cmds, $1)=$reload_cmds _LT_TAGVAR(no_undefined_flag, $1)= _LT_TAGVAR(whole_archive_flag_spec, $1)= _LT_TAGVAR(enable_shared_with_static_runtimes, $1)=no # Source file extension for fc test sources. ac_ext=${ac_fc_srcext-f} # Object file extension for compiled fc test sources. objext=o _LT_TAGVAR(objext, $1)=$objext # No sense in running all these tests if we already determined that # the FC compiler isn't working. Some variables (like enable_shared) # are currently assumed to apply to all compilers on this platform, # and will be corrupted by setting them based on a non-working compiler. if test "$_lt_disable_FC" != yes; then # Code to be used in simple compile tests lt_simple_compile_test_code="\ subroutine t return end " # Code to be used in simple link tests lt_simple_link_test_code="\ program t end " # ltmain only uses $CC for tagged configurations so make sure $CC is set. _LT_TAG_COMPILER # save warnings/boilerplate of simple test code _LT_COMPILER_BOILERPLATE _LT_LINKER_BOILERPLATE # Allow CC to be a program name with arguments. lt_save_CC="$CC" lt_save_GCC=$GCC lt_save_CFLAGS=$CFLAGS CC=${FC-"f95"} CFLAGS=$FCFLAGS compiler=$CC GCC=$ac_cv_fc_compiler_gnu _LT_TAGVAR(compiler, $1)=$CC _LT_CC_BASENAME([$compiler]) if test -n "$compiler"; then AC_MSG_CHECKING([if libtool supports shared libraries]) AC_MSG_RESULT([$can_build_shared]) AC_MSG_CHECKING([whether to build shared libraries]) test "$can_build_shared" = "no" && enable_shared=no # On AIX, shared libraries and static libraries use the same namespace, and # are all built from PIC. case $host_os in aix3*) test "$enable_shared" = yes && enable_static=no if test -n "$RANLIB"; then archive_cmds="$archive_cmds~\$RANLIB \$lib" postinstall_cmds='$RANLIB $lib' fi ;; aix[[4-9]]*) if test "$host_cpu" != ia64 && test "$aix_use_runtimelinking" = no ; then test "$enable_shared" = yes && enable_static=no fi ;; esac AC_MSG_RESULT([$enable_shared]) AC_MSG_CHECKING([whether to build static libraries]) # Make sure either enable_shared or enable_static is yes. test "$enable_shared" = yes || enable_static=yes AC_MSG_RESULT([$enable_static]) _LT_TAGVAR(GCC, $1)="$ac_cv_fc_compiler_gnu" _LT_TAGVAR(LD, $1)="$LD" ## CAVEAT EMPTOR: ## There is no encapsulation within the following macros, do not change ## the running order or otherwise move them around unless you know exactly ## what you are doing... _LT_SYS_HIDDEN_LIBDEPS($1) _LT_COMPILER_PIC($1) _LT_COMPILER_C_O($1) _LT_COMPILER_FILE_LOCKS($1) _LT_LINKER_SHLIBS($1) _LT_SYS_DYNAMIC_LINKER($1) _LT_LINKER_HARDCODE_LIBPATH($1) _LT_CONFIG($1) fi # test -n "$compiler" GCC=$lt_save_GCC CC=$lt_save_CC CFLAGS=$lt_save_CFLAGS fi # test "$_lt_disable_FC" != yes AC_LANG_POP ])# _LT_LANG_FC_CONFIG # _LT_LANG_GCJ_CONFIG([TAG]) # -------------------------- # Ensure that the configuration variables for the GNU Java Compiler compiler # are suitably defined. These variables are subsequently used by _LT_CONFIG # to write the compiler configuration to `libtool'. m4_defun([_LT_LANG_GCJ_CONFIG], [AC_REQUIRE([LT_PROG_GCJ])dnl AC_LANG_SAVE # Source file extension for Java test sources. ac_ext=java # Object file extension for compiled Java test sources. objext=o _LT_TAGVAR(objext, $1)=$objext # Code to be used in simple compile tests lt_simple_compile_test_code="class foo {}" # Code to be used in simple link tests lt_simple_link_test_code='public class conftest { public static void main(String[[]] argv) {}; }' # ltmain only uses $CC for tagged configurations so make sure $CC is set. _LT_TAG_COMPILER # save warnings/boilerplate of simple test code _LT_COMPILER_BOILERPLATE _LT_LINKER_BOILERPLATE # Allow CC to be a program name with arguments. lt_save_CC=$CC lt_save_CFLAGS=$CFLAGS lt_save_GCC=$GCC GCC=yes CC=${GCJ-"gcj"} CFLAGS=$GCJFLAGS compiler=$CC _LT_TAGVAR(compiler, $1)=$CC _LT_TAGVAR(LD, $1)="$LD" _LT_CC_BASENAME([$compiler]) # GCJ did not exist at the time GCC didn't implicitly link libc in. _LT_TAGVAR(archive_cmds_need_lc, $1)=no _LT_TAGVAR(old_archive_cmds, $1)=$old_archive_cmds _LT_TAGVAR(reload_flag, $1)=$reload_flag _LT_TAGVAR(reload_cmds, $1)=$reload_cmds if test -n "$compiler"; then _LT_COMPILER_NO_RTTI($1) _LT_COMPILER_PIC($1) _LT_COMPILER_C_O($1) _LT_COMPILER_FILE_LOCKS($1) _LT_LINKER_SHLIBS($1) _LT_LINKER_HARDCODE_LIBPATH($1) _LT_CONFIG($1) fi AC_LANG_RESTORE GCC=$lt_save_GCC CC=$lt_save_CC CFLAGS=$lt_save_CFLAGS ])# _LT_LANG_GCJ_CONFIG # _LT_LANG_RC_CONFIG([TAG]) # ------------------------- # Ensure that the configuration variables for the Windows resource compiler # are suitably defined. These variables are subsequently used by _LT_CONFIG # to write the compiler configuration to `libtool'. m4_defun([_LT_LANG_RC_CONFIG], [AC_REQUIRE([LT_PROG_RC])dnl AC_LANG_SAVE # Source file extension for RC test sources. ac_ext=rc # Object file extension for compiled RC test sources. objext=o _LT_TAGVAR(objext, $1)=$objext # Code to be used in simple compile tests lt_simple_compile_test_code='sample MENU { MENUITEM "&Soup", 100, CHECKED }' # Code to be used in simple link tests lt_simple_link_test_code="$lt_simple_compile_test_code" # ltmain only uses $CC for tagged configurations so make sure $CC is set. _LT_TAG_COMPILER # save warnings/boilerplate of simple test code _LT_COMPILER_BOILERPLATE _LT_LINKER_BOILERPLATE # Allow CC to be a program name with arguments. lt_save_CC="$CC" lt_save_CFLAGS=$CFLAGS lt_save_GCC=$GCC GCC= CC=${RC-"windres"} CFLAGS= compiler=$CC _LT_TAGVAR(compiler, $1)=$CC _LT_CC_BASENAME([$compiler]) _LT_TAGVAR(lt_cv_prog_compiler_c_o, $1)=yes if test -n "$compiler"; then : _LT_CONFIG($1) fi GCC=$lt_save_GCC AC_LANG_RESTORE CC=$lt_save_CC CFLAGS=$lt_save_CFLAGS ])# _LT_LANG_RC_CONFIG # LT_PROG_GCJ # ----------- AC_DEFUN([LT_PROG_GCJ], [m4_ifdef([AC_PROG_GCJ], [AC_PROG_GCJ], [m4_ifdef([A][M_PROG_GCJ], [A][M_PROG_GCJ], [AC_CHECK_TOOL(GCJ, gcj,) test "x${GCJFLAGS+set}" = xset || GCJFLAGS="-g -O2" AC_SUBST(GCJFLAGS)])])[]dnl ]) # Old name: AU_ALIAS([LT_AC_PROG_GCJ], [LT_PROG_GCJ]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([LT_AC_PROG_GCJ], []) # LT_PROG_RC # ---------- AC_DEFUN([LT_PROG_RC], [AC_CHECK_TOOL(RC, windres,) ]) # Old name: AU_ALIAS([LT_AC_PROG_RC], [LT_PROG_RC]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([LT_AC_PROG_RC], []) # _LT_DECL_EGREP # -------------- # If we don't have a new enough Autoconf to choose the best grep # available, choose the one first in the user's PATH. m4_defun([_LT_DECL_EGREP], [AC_REQUIRE([AC_PROG_EGREP])dnl AC_REQUIRE([AC_PROG_FGREP])dnl test -z "$GREP" && GREP=grep _LT_DECL([], [GREP], [1], [A grep program that handles long lines]) _LT_DECL([], [EGREP], [1], [An ERE matcher]) _LT_DECL([], [FGREP], [1], [A literal string matcher]) dnl Non-bleeding-edge autoconf doesn't subst GREP, so do it here too AC_SUBST([GREP]) ]) # _LT_DECL_OBJDUMP # -------------- # If we don't have a new enough Autoconf to choose the best objdump # available, choose the one first in the user's PATH. m4_defun([_LT_DECL_OBJDUMP], [AC_CHECK_TOOL(OBJDUMP, objdump, false) test -z "$OBJDUMP" && OBJDUMP=objdump _LT_DECL([], [OBJDUMP], [1], [An object symbol dumper]) AC_SUBST([OBJDUMP]) ]) # _LT_DECL_DLLTOOL # ---------------- # Ensure DLLTOOL variable is set. m4_defun([_LT_DECL_DLLTOOL], [AC_CHECK_TOOL(DLLTOOL, dlltool, false) test -z "$DLLTOOL" && DLLTOOL=dlltool _LT_DECL([], [DLLTOOL], [1], [DLL creation program]) AC_SUBST([DLLTOOL]) ]) # _LT_DECL_SED # ------------ # Check for a fully-functional sed program, that truncates # as few characters as possible. Prefer GNU sed if found. m4_defun([_LT_DECL_SED], [AC_PROG_SED test -z "$SED" && SED=sed Xsed="$SED -e 1s/^X//" _LT_DECL([], [SED], [1], [A sed program that does not truncate output]) _LT_DECL([], [Xsed], ["\$SED -e 1s/^X//"], [Sed that helps us avoid accidentally triggering echo(1) options like -n]) ])# _LT_DECL_SED m4_ifndef([AC_PROG_SED], [ # NOTE: This macro has been submitted for inclusion into # # GNU Autoconf as AC_PROG_SED. When it is available in # # a released version of Autoconf we should remove this # # macro and use it instead. # m4_defun([AC_PROG_SED], [AC_MSG_CHECKING([for a sed that does not truncate output]) AC_CACHE_VAL(lt_cv_path_SED, [# Loop through the user's path and test for sed and gsed. # Then use that list of sed's as ones to test for truncation. as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for lt_ac_prog in sed gsed; do for ac_exec_ext in '' $ac_executable_extensions; do if $as_executable_p "$as_dir/$lt_ac_prog$ac_exec_ext"; then lt_ac_sed_list="$lt_ac_sed_list $as_dir/$lt_ac_prog$ac_exec_ext" fi done done done IFS=$as_save_IFS lt_ac_max=0 lt_ac_count=0 # Add /usr/xpg4/bin/sed as it is typically found on Solaris # along with /bin/sed that truncates output. for lt_ac_sed in $lt_ac_sed_list /usr/xpg4/bin/sed; do test ! -f $lt_ac_sed && continue cat /dev/null > conftest.in lt_ac_count=0 echo $ECHO_N "0123456789$ECHO_C" >conftest.in # Check for GNU sed and select it if it is found. if "$lt_ac_sed" --version 2>&1 < /dev/null | grep 'GNU' > /dev/null; then lt_cv_path_SED=$lt_ac_sed break fi while true; do cat conftest.in conftest.in >conftest.tmp mv conftest.tmp conftest.in cp conftest.in conftest.nl echo >>conftest.nl $lt_ac_sed -e 's/a$//' < conftest.nl >conftest.out || break cmp -s conftest.out conftest.nl || break # 10000 chars as input seems more than enough test $lt_ac_count -gt 10 && break lt_ac_count=`expr $lt_ac_count + 1` if test $lt_ac_count -gt $lt_ac_max; then lt_ac_max=$lt_ac_count lt_cv_path_SED=$lt_ac_sed fi done done ]) SED=$lt_cv_path_SED AC_SUBST([SED]) AC_MSG_RESULT([$SED]) ])#AC_PROG_SED ])#m4_ifndef # Old name: AU_ALIAS([LT_AC_PROG_SED], [AC_PROG_SED]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([LT_AC_PROG_SED], []) # _LT_CHECK_SHELL_FEATURES # ------------------------ # Find out whether the shell is Bourne or XSI compatible, # or has some other useful features. m4_defun([_LT_CHECK_SHELL_FEATURES], [AC_MSG_CHECKING([whether the shell understands some XSI constructs]) # Try some XSI features xsi_shell=no ( _lt_dummy="a/b/c" test "${_lt_dummy##*/},${_lt_dummy%/*},${_lt_dummy#??}"${_lt_dummy%"$_lt_dummy"}, \ = c,a/b,b/c, \ && eval 'test $(( 1 + 1 )) -eq 2 \ && test "${#_lt_dummy}" -eq 5' ) >/dev/null 2>&1 \ && xsi_shell=yes AC_MSG_RESULT([$xsi_shell]) _LT_CONFIG_LIBTOOL_INIT([xsi_shell='$xsi_shell']) AC_MSG_CHECKING([whether the shell understands "+="]) lt_shell_append=no ( foo=bar; set foo baz; eval "$[1]+=\$[2]" && test "$foo" = barbaz ) \ >/dev/null 2>&1 \ && lt_shell_append=yes AC_MSG_RESULT([$lt_shell_append]) _LT_CONFIG_LIBTOOL_INIT([lt_shell_append='$lt_shell_append']) if ( (MAIL=60; unset MAIL) || exit) >/dev/null 2>&1; then lt_unset=unset else lt_unset=false fi _LT_DECL([], [lt_unset], [0], [whether the shell understands "unset"])dnl # test EBCDIC or ASCII case `echo X|tr X '\101'` in A) # ASCII based system # \n is not interpreted correctly by Solaris 8 /usr/ucb/tr lt_SP2NL='tr \040 \012' lt_NL2SP='tr \015\012 \040\040' ;; *) # EBCDIC based system lt_SP2NL='tr \100 \n' lt_NL2SP='tr \r\n \100\100' ;; esac _LT_DECL([SP2NL], [lt_SP2NL], [1], [turn spaces into newlines])dnl _LT_DECL([NL2SP], [lt_NL2SP], [1], [turn newlines into spaces])dnl ])# _LT_CHECK_SHELL_FEATURES # _LT_PROG_FUNCTION_REPLACE (FUNCNAME, REPLACEMENT-BODY) # ------------------------------------------------------ # In `$cfgfile', look for function FUNCNAME delimited by `^FUNCNAME ()$' and # '^} FUNCNAME ', and replace its body with REPLACEMENT-BODY. m4_defun([_LT_PROG_FUNCTION_REPLACE], [dnl { sed -e '/^$1 ()$/,/^} # $1 /c\ $1 ()\ {\ m4_bpatsubsts([$2], [$], [\\], [^\([ ]\)], [\\\1]) } # Extended-shell $1 implementation' "$cfgfile" > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: ]) # _LT_PROG_REPLACE_SHELLFNS # ------------------------- # Replace existing portable implementations of several shell functions with # equivalent extended shell implementations where those features are available.. m4_defun([_LT_PROG_REPLACE_SHELLFNS], [if test x"$xsi_shell" = xyes; then _LT_PROG_FUNCTION_REPLACE([func_dirname], [dnl case ${1} in */*) func_dirname_result="${1%/*}${2}" ;; * ) func_dirname_result="${3}" ;; esac]) _LT_PROG_FUNCTION_REPLACE([func_basename], [dnl func_basename_result="${1##*/}"]) _LT_PROG_FUNCTION_REPLACE([func_dirname_and_basename], [dnl case ${1} in */*) func_dirname_result="${1%/*}${2}" ;; * ) func_dirname_result="${3}" ;; esac func_basename_result="${1##*/}"]) _LT_PROG_FUNCTION_REPLACE([func_stripname], [dnl # pdksh 5.2.14 does not do ${X%$Y} correctly if both X and Y are # positional parameters, so assign one to ordinary parameter first. func_stripname_result=${3} func_stripname_result=${func_stripname_result#"${1}"} func_stripname_result=${func_stripname_result%"${2}"}]) _LT_PROG_FUNCTION_REPLACE([func_split_long_opt], [dnl func_split_long_opt_name=${1%%=*} func_split_long_opt_arg=${1#*=}]) _LT_PROG_FUNCTION_REPLACE([func_split_short_opt], [dnl func_split_short_opt_arg=${1#??} func_split_short_opt_name=${1%"$func_split_short_opt_arg"}]) _LT_PROG_FUNCTION_REPLACE([func_lo2o], [dnl case ${1} in *.lo) func_lo2o_result=${1%.lo}.${objext} ;; *) func_lo2o_result=${1} ;; esac]) _LT_PROG_FUNCTION_REPLACE([func_xform], [ func_xform_result=${1%.*}.lo]) _LT_PROG_FUNCTION_REPLACE([func_arith], [ func_arith_result=$(( $[*] ))]) _LT_PROG_FUNCTION_REPLACE([func_len], [ func_len_result=${#1}]) fi if test x"$lt_shell_append" = xyes; then _LT_PROG_FUNCTION_REPLACE([func_append], [ eval "${1}+=\\${2}"]) _LT_PROG_FUNCTION_REPLACE([func_append_quoted], [dnl func_quote_for_eval "${2}" dnl m4 expansion turns \\\\ into \\, and then the shell eval turns that into \ eval "${1}+=\\\\ \\$func_quote_for_eval_result"]) # Save a `func_append' function call where possible by direct use of '+=' sed -e 's%func_append \([[a-zA-Z_]]\{1,\}\) "%\1+="%g' $cfgfile > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: else # Save a `func_append' function call even when '+=' is not available sed -e 's%func_append \([[a-zA-Z_]]\{1,\}\) "%\1="$\1%g' $cfgfile > $cfgfile.tmp \ && mv -f "$cfgfile.tmp" "$cfgfile" \ || (rm -f "$cfgfile" && cp "$cfgfile.tmp" "$cfgfile" && rm -f "$cfgfile.tmp") test 0 -eq $? || _lt_function_replace_fail=: fi if test x"$_lt_function_replace_fail" = x":"; then AC_MSG_WARN([Unable to substitute extended shell functions in $ofile]) fi ]) # _LT_PATH_CONVERSION_FUNCTIONS # ----------------------------- # Determine which file name conversion functions should be used by # func_to_host_file (and, implicitly, by func_to_host_path). These are needed # for certain cross-compile configurations and native mingw. m4_defun([_LT_PATH_CONVERSION_FUNCTIONS], [AC_REQUIRE([AC_CANONICAL_HOST])dnl AC_REQUIRE([AC_CANONICAL_BUILD])dnl AC_MSG_CHECKING([how to convert $build file names to $host format]) AC_CACHE_VAL(lt_cv_to_host_file_cmd, [case $host in *-*-mingw* ) case $build in *-*-mingw* ) # actually msys lt_cv_to_host_file_cmd=func_convert_file_msys_to_w32 ;; *-*-cygwin* ) lt_cv_to_host_file_cmd=func_convert_file_cygwin_to_w32 ;; * ) # otherwise, assume *nix lt_cv_to_host_file_cmd=func_convert_file_nix_to_w32 ;; esac ;; *-*-cygwin* ) case $build in *-*-mingw* ) # actually msys lt_cv_to_host_file_cmd=func_convert_file_msys_to_cygwin ;; *-*-cygwin* ) lt_cv_to_host_file_cmd=func_convert_file_noop ;; * ) # otherwise, assume *nix lt_cv_to_host_file_cmd=func_convert_file_nix_to_cygwin ;; esac ;; * ) # unhandled hosts (and "normal" native builds) lt_cv_to_host_file_cmd=func_convert_file_noop ;; esac ]) to_host_file_cmd=$lt_cv_to_host_file_cmd AC_MSG_RESULT([$lt_cv_to_host_file_cmd]) _LT_DECL([to_host_file_cmd], [lt_cv_to_host_file_cmd], [0], [convert $build file names to $host format])dnl AC_MSG_CHECKING([how to convert $build file names to toolchain format]) AC_CACHE_VAL(lt_cv_to_tool_file_cmd, [#assume ordinary cross tools, or native build. lt_cv_to_tool_file_cmd=func_convert_file_noop case $host in *-*-mingw* ) case $build in *-*-mingw* ) # actually msys lt_cv_to_tool_file_cmd=func_convert_file_msys_to_w32 ;; esac ;; esac ]) to_tool_file_cmd=$lt_cv_to_tool_file_cmd AC_MSG_RESULT([$lt_cv_to_tool_file_cmd]) _LT_DECL([to_tool_file_cmd], [lt_cv_to_tool_file_cmd], [0], [convert $build files to toolchain format])dnl ])# _LT_PATH_CONVERSION_FUNCTIONS # Helper functions for option handling. -*- Autoconf -*- # # Copyright (C) 2004, 2005, 2007, 2008, 2009 Free Software Foundation, # Inc. # Written by Gary V. Vaughan, 2004 # # This file is free software; the Free Software Foundation gives # unlimited permission to copy and/or distribute it, with or without # modifications, as long as this notice is preserved. # serial 7 ltoptions.m4 # This is to help aclocal find these macros, as it can't see m4_define. AC_DEFUN([LTOPTIONS_VERSION], [m4_if([1])]) # _LT_MANGLE_OPTION(MACRO-NAME, OPTION-NAME) # ------------------------------------------ m4_define([_LT_MANGLE_OPTION], [[_LT_OPTION_]m4_bpatsubst($1__$2, [[^a-zA-Z0-9_]], [_])]) # _LT_SET_OPTION(MACRO-NAME, OPTION-NAME) # --------------------------------------- # Set option OPTION-NAME for macro MACRO-NAME, and if there is a # matching handler defined, dispatch to it. Other OPTION-NAMEs are # saved as a flag. m4_define([_LT_SET_OPTION], [m4_define(_LT_MANGLE_OPTION([$1], [$2]))dnl m4_ifdef(_LT_MANGLE_DEFUN([$1], [$2]), _LT_MANGLE_DEFUN([$1], [$2]), [m4_warning([Unknown $1 option `$2'])])[]dnl ]) # _LT_IF_OPTION(MACRO-NAME, OPTION-NAME, IF-SET, [IF-NOT-SET]) # ------------------------------------------------------------ # Execute IF-SET if OPTION is set, IF-NOT-SET otherwise. m4_define([_LT_IF_OPTION], [m4_ifdef(_LT_MANGLE_OPTION([$1], [$2]), [$3], [$4])]) # _LT_UNLESS_OPTIONS(MACRO-NAME, OPTION-LIST, IF-NOT-SET) # ------------------------------------------------------- # Execute IF-NOT-SET unless all options in OPTION-LIST for MACRO-NAME # are set. m4_define([_LT_UNLESS_OPTIONS], [m4_foreach([_LT_Option], m4_split(m4_normalize([$2])), [m4_ifdef(_LT_MANGLE_OPTION([$1], _LT_Option), [m4_define([$0_found])])])[]dnl m4_ifdef([$0_found], [m4_undefine([$0_found])], [$3 ])[]dnl ]) # _LT_SET_OPTIONS(MACRO-NAME, OPTION-LIST) # ---------------------------------------- # OPTION-LIST is a space-separated list of Libtool options associated # with MACRO-NAME. If any OPTION has a matching handler declared with # LT_OPTION_DEFINE, dispatch to that macro; otherwise complain about # the unknown option and exit. m4_defun([_LT_SET_OPTIONS], [# Set options m4_foreach([_LT_Option], m4_split(m4_normalize([$2])), [_LT_SET_OPTION([$1], _LT_Option)]) m4_if([$1],[LT_INIT],[ dnl dnl Simply set some default values (i.e off) if boolean options were not dnl specified: _LT_UNLESS_OPTIONS([LT_INIT], [dlopen], [enable_dlopen=no ]) _LT_UNLESS_OPTIONS([LT_INIT], [win32-dll], [enable_win32_dll=no ]) dnl dnl If no reference was made to various pairs of opposing options, then dnl we run the default mode handler for the pair. For example, if neither dnl `shared' nor `disable-shared' was passed, we enable building of shared dnl archives by default: _LT_UNLESS_OPTIONS([LT_INIT], [shared disable-shared], [_LT_ENABLE_SHARED]) _LT_UNLESS_OPTIONS([LT_INIT], [static disable-static], [_LT_ENABLE_STATIC]) _LT_UNLESS_OPTIONS([LT_INIT], [pic-only no-pic], [_LT_WITH_PIC]) _LT_UNLESS_OPTIONS([LT_INIT], [fast-install disable-fast-install], [_LT_ENABLE_FAST_INSTALL]) ]) ])# _LT_SET_OPTIONS # _LT_MANGLE_DEFUN(MACRO-NAME, OPTION-NAME) # ----------------------------------------- m4_define([_LT_MANGLE_DEFUN], [[_LT_OPTION_DEFUN_]m4_bpatsubst(m4_toupper([$1__$2]), [[^A-Z0-9_]], [_])]) # LT_OPTION_DEFINE(MACRO-NAME, OPTION-NAME, CODE) # ----------------------------------------------- m4_define([LT_OPTION_DEFINE], [m4_define(_LT_MANGLE_DEFUN([$1], [$2]), [$3])[]dnl ])# LT_OPTION_DEFINE # dlopen # ------ LT_OPTION_DEFINE([LT_INIT], [dlopen], [enable_dlopen=yes ]) AU_DEFUN([AC_LIBTOOL_DLOPEN], [_LT_SET_OPTION([LT_INIT], [dlopen]) AC_DIAGNOSE([obsolete], [$0: Remove this warning and the call to _LT_SET_OPTION when you put the `dlopen' option into LT_INIT's first parameter.]) ]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AC_LIBTOOL_DLOPEN], []) # win32-dll # --------- # Declare package support for building win32 dll's. LT_OPTION_DEFINE([LT_INIT], [win32-dll], [enable_win32_dll=yes case $host in *-*-cygwin* | *-*-mingw* | *-*-pw32* | *-*-cegcc*) AC_CHECK_TOOL(AS, as, false) AC_CHECK_TOOL(DLLTOOL, dlltool, false) AC_CHECK_TOOL(OBJDUMP, objdump, false) ;; esac test -z "$AS" && AS=as _LT_DECL([], [AS], [1], [Assembler program])dnl test -z "$DLLTOOL" && DLLTOOL=dlltool _LT_DECL([], [DLLTOOL], [1], [DLL creation program])dnl test -z "$OBJDUMP" && OBJDUMP=objdump _LT_DECL([], [OBJDUMP], [1], [Object dumper program])dnl ])# win32-dll AU_DEFUN([AC_LIBTOOL_WIN32_DLL], [AC_REQUIRE([AC_CANONICAL_HOST])dnl _LT_SET_OPTION([LT_INIT], [win32-dll]) AC_DIAGNOSE([obsolete], [$0: Remove this warning and the call to _LT_SET_OPTION when you put the `win32-dll' option into LT_INIT's first parameter.]) ]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AC_LIBTOOL_WIN32_DLL], []) # _LT_ENABLE_SHARED([DEFAULT]) # ---------------------------- # implement the --enable-shared flag, and supports the `shared' and # `disable-shared' LT_INIT options. # DEFAULT is either `yes' or `no'. If omitted, it defaults to `yes'. m4_define([_LT_ENABLE_SHARED], [m4_define([_LT_ENABLE_SHARED_DEFAULT], [m4_if($1, no, no, yes)])dnl AC_ARG_ENABLE([shared], [AS_HELP_STRING([--enable-shared@<:@=PKGS@:>@], [build shared libraries @<:@default=]_LT_ENABLE_SHARED_DEFAULT[@:>@])], [p=${PACKAGE-default} case $enableval in yes) enable_shared=yes ;; no) enable_shared=no ;; *) enable_shared=no # Look at the argument we got. We use all the common list separators. lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," for pkg in $enableval; do IFS="$lt_save_ifs" if test "X$pkg" = "X$p"; then enable_shared=yes fi done IFS="$lt_save_ifs" ;; esac], [enable_shared=]_LT_ENABLE_SHARED_DEFAULT) _LT_DECL([build_libtool_libs], [enable_shared], [0], [Whether or not to build shared libraries]) ])# _LT_ENABLE_SHARED LT_OPTION_DEFINE([LT_INIT], [shared], [_LT_ENABLE_SHARED([yes])]) LT_OPTION_DEFINE([LT_INIT], [disable-shared], [_LT_ENABLE_SHARED([no])]) # Old names: AC_DEFUN([AC_ENABLE_SHARED], [_LT_SET_OPTION([LT_INIT], m4_if([$1], [no], [disable-])[shared]) ]) AC_DEFUN([AC_DISABLE_SHARED], [_LT_SET_OPTION([LT_INIT], [disable-shared]) ]) AU_DEFUN([AM_ENABLE_SHARED], [AC_ENABLE_SHARED($@)]) AU_DEFUN([AM_DISABLE_SHARED], [AC_DISABLE_SHARED($@)]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AM_ENABLE_SHARED], []) dnl AC_DEFUN([AM_DISABLE_SHARED], []) # _LT_ENABLE_STATIC([DEFAULT]) # ---------------------------- # implement the --enable-static flag, and support the `static' and # `disable-static' LT_INIT options. # DEFAULT is either `yes' or `no'. If omitted, it defaults to `yes'. m4_define([_LT_ENABLE_STATIC], [m4_define([_LT_ENABLE_STATIC_DEFAULT], [m4_if($1, no, no, yes)])dnl AC_ARG_ENABLE([static], [AS_HELP_STRING([--enable-static@<:@=PKGS@:>@], [build static libraries @<:@default=]_LT_ENABLE_STATIC_DEFAULT[@:>@])], [p=${PACKAGE-default} case $enableval in yes) enable_static=yes ;; no) enable_static=no ;; *) enable_static=no # Look at the argument we got. We use all the common list separators. lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," for pkg in $enableval; do IFS="$lt_save_ifs" if test "X$pkg" = "X$p"; then enable_static=yes fi done IFS="$lt_save_ifs" ;; esac], [enable_static=]_LT_ENABLE_STATIC_DEFAULT) _LT_DECL([build_old_libs], [enable_static], [0], [Whether or not to build static libraries]) ])# _LT_ENABLE_STATIC LT_OPTION_DEFINE([LT_INIT], [static], [_LT_ENABLE_STATIC([yes])]) LT_OPTION_DEFINE([LT_INIT], [disable-static], [_LT_ENABLE_STATIC([no])]) # Old names: AC_DEFUN([AC_ENABLE_STATIC], [_LT_SET_OPTION([LT_INIT], m4_if([$1], [no], [disable-])[static]) ]) AC_DEFUN([AC_DISABLE_STATIC], [_LT_SET_OPTION([LT_INIT], [disable-static]) ]) AU_DEFUN([AM_ENABLE_STATIC], [AC_ENABLE_STATIC($@)]) AU_DEFUN([AM_DISABLE_STATIC], [AC_DISABLE_STATIC($@)]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AM_ENABLE_STATIC], []) dnl AC_DEFUN([AM_DISABLE_STATIC], []) # _LT_ENABLE_FAST_INSTALL([DEFAULT]) # ---------------------------------- # implement the --enable-fast-install flag, and support the `fast-install' # and `disable-fast-install' LT_INIT options. # DEFAULT is either `yes' or `no'. If omitted, it defaults to `yes'. m4_define([_LT_ENABLE_FAST_INSTALL], [m4_define([_LT_ENABLE_FAST_INSTALL_DEFAULT], [m4_if($1, no, no, yes)])dnl AC_ARG_ENABLE([fast-install], [AS_HELP_STRING([--enable-fast-install@<:@=PKGS@:>@], [optimize for fast installation @<:@default=]_LT_ENABLE_FAST_INSTALL_DEFAULT[@:>@])], [p=${PACKAGE-default} case $enableval in yes) enable_fast_install=yes ;; no) enable_fast_install=no ;; *) enable_fast_install=no # Look at the argument we got. We use all the common list separators. lt_save_ifs="$IFS"; IFS="${IFS}$PATH_SEPARATOR," for pkg in $enableval; do IFS="$lt_save_ifs" if test "X$pkg" = "X$p"; then enable_fast_install=yes fi done IFS="$lt_save_ifs" ;; esac], [enable_fast_install=]_LT_ENABLE_FAST_INSTALL_DEFAULT) _LT_DECL([fast_install], [enable_fast_install], [0], [Whether or not to optimize for fast installation])dnl ])# _LT_ENABLE_FAST_INSTALL LT_OPTION_DEFINE([LT_INIT], [fast-install], [_LT_ENABLE_FAST_INSTALL([yes])]) LT_OPTION_DEFINE([LT_INIT], [disable-fast-install], [_LT_ENABLE_FAST_INSTALL([no])]) # Old names: AU_DEFUN([AC_ENABLE_FAST_INSTALL], [_LT_SET_OPTION([LT_INIT], m4_if([$1], [no], [disable-])[fast-install]) AC_DIAGNOSE([obsolete], [$0: Remove this warning and the call to _LT_SET_OPTION when you put the `fast-install' option into LT_INIT's first parameter.]) ]) AU_DEFUN([AC_DISABLE_FAST_INSTALL], [_LT_SET_OPTION([LT_INIT], [disable-fast-install]) AC_DIAGNOSE([obsolete], [$0: Remove this warning and the call to _LT_SET_OPTION when you put the `disable-fast-install' option into LT_INIT's first parameter.]) ]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AC_ENABLE_FAST_INSTALL], []) dnl AC_DEFUN([AM_DISABLE_FAST_INSTALL], []) # _LT_WITH_PIC([MODE]) # -------------------- # implement the --with-pic flag, and support the `pic-only' and `no-pic' # LT_INIT options. # MODE is either `yes' or `no'. If omitted, it defaults to `both'. m4_define([_LT_WITH_PIC], [AC_ARG_WITH([pic], [AS_HELP_STRING([--with-pic], [try to use only PIC/non-PIC objects @<:@default=use both@:>@])], [pic_mode="$withval"], [pic_mode=default]) test -z "$pic_mode" && pic_mode=m4_default([$1], [default]) _LT_DECL([], [pic_mode], [0], [What type of objects to build])dnl ])# _LT_WITH_PIC LT_OPTION_DEFINE([LT_INIT], [pic-only], [_LT_WITH_PIC([yes])]) LT_OPTION_DEFINE([LT_INIT], [no-pic], [_LT_WITH_PIC([no])]) # Old name: AU_DEFUN([AC_LIBTOOL_PICMODE], [_LT_SET_OPTION([LT_INIT], [pic-only]) AC_DIAGNOSE([obsolete], [$0: Remove this warning and the call to _LT_SET_OPTION when you put the `pic-only' option into LT_INIT's first parameter.]) ]) dnl aclocal-1.4 backwards compatibility: dnl AC_DEFUN([AC_LIBTOOL_PICMODE], []) m4_define([_LTDL_MODE], []) LT_OPTION_DEFINE([LTDL_INIT], [nonrecursive], [m4_define([_LTDL_MODE], [nonrecursive])]) LT_OPTION_DEFINE([LTDL_INIT], [recursive], [m4_define([_LTDL_MODE], [recursive])]) LT_OPTION_DEFINE([LTDL_INIT], [subproject], [m4_define([_LTDL_MODE], [subproject])]) m4_define([_LTDL_TYPE], []) LT_OPTION_DEFINE([LTDL_INIT], [installable], [m4_define([_LTDL_TYPE], [installable])]) LT_OPTION_DEFINE([LTDL_INIT], [convenience], [m4_define([_LTDL_TYPE], [convenience])]) # ltsugar.m4 -- libtool m4 base layer. -*-Autoconf-*- # # Copyright (C) 2004, 2005, 2007, 2008 Free Software Foundation, Inc. # Written by Gary V. Vaughan, 2004 # # This file is free software; the Free Software Foundation gives # unlimited permission to copy and/or distribute it, with or without # modifications, as long as this notice is preserved. # serial 6 ltsugar.m4 # This is to help aclocal find these macros, as it can't see m4_define. AC_DEFUN([LTSUGAR_VERSION], [m4_if([0.1])]) # lt_join(SEP, ARG1, [ARG2...]) # ----------------------------- # Produce ARG1SEPARG2...SEPARGn, omitting [] arguments and their # associated separator. # Needed until we can rely on m4_join from Autoconf 2.62, since all earlier # versions in m4sugar had bugs. m4_define([lt_join], [m4_if([$#], [1], [], [$#], [2], [[$2]], [m4_if([$2], [], [], [[$2]_])$0([$1], m4_shift(m4_shift($@)))])]) m4_define([_lt_join], [m4_if([$#$2], [2], [], [m4_if([$2], [], [], [[$1$2]])$0([$1], m4_shift(m4_shift($@)))])]) # lt_car(LIST) # lt_cdr(LIST) # ------------ # Manipulate m4 lists. # These macros are necessary as long as will still need to support # Autoconf-2.59 which quotes differently. m4_define([lt_car], [[$1]]) m4_define([lt_cdr], [m4_if([$#], 0, [m4_fatal([$0: cannot be called without arguments])], [$#], 1, [], [m4_dquote(m4_shift($@))])]) m4_define([lt_unquote], $1) # lt_append(MACRO-NAME, STRING, [SEPARATOR]) # ------------------------------------------ # Redefine MACRO-NAME to hold its former content plus `SEPARATOR'`STRING'. # Note that neither SEPARATOR nor STRING are expanded; they are appended # to MACRO-NAME as is (leaving the expansion for when MACRO-NAME is invoked). # No SEPARATOR is output if MACRO-NAME was previously undefined (different # than defined and empty). # # This macro is needed until we can rely on Autoconf 2.62, since earlier # versions of m4sugar mistakenly expanded SEPARATOR but not STRING. m4_define([lt_append], [m4_define([$1], m4_ifdef([$1], [m4_defn([$1])[$3]])[$2])]) # lt_combine(SEP, PREFIX-LIST, INFIX, SUFFIX1, [SUFFIX2...]) # ---------------------------------------------------------- # Produce a SEP delimited list of all paired combinations of elements of # PREFIX-LIST with SUFFIX1 through SUFFIXn. Each element of the list # has the form PREFIXmINFIXSUFFIXn. # Needed until we can rely on m4_combine added in Autoconf 2.62. m4_define([lt_combine], [m4_if(m4_eval([$# > 3]), [1], [m4_pushdef([_Lt_sep], [m4_define([_Lt_sep], m4_defn([lt_car]))])]]dnl [[m4_foreach([_Lt_prefix], [$2], [m4_foreach([_Lt_suffix], ]m4_dquote(m4_dquote(m4_shift(m4_shift(m4_shift($@)))))[, [_Lt_sep([$1])[]m4_defn([_Lt_prefix])[$3]m4_defn([_Lt_suffix])])])])]) # lt_if_append_uniq(MACRO-NAME, VARNAME, [SEPARATOR], [UNIQ], [NOT-UNIQ]) # ----------------------------------------------------------------------- # Iff MACRO-NAME does not yet contain VARNAME, then append it (delimited # by SEPARATOR if supplied) and expand UNIQ, else NOT-UNIQ. m4_define([lt_if_append_uniq], [m4_ifdef([$1], [m4_if(m4_index([$3]m4_defn([$1])[$3], [$3$2$3]), [-1], [lt_append([$1], [$2], [$3])$4], [$5])], [lt_append([$1], [$2], [$3])$4])]) # lt_dict_add(DICT, KEY, VALUE) # ----------------------------- m4_define([lt_dict_add], [m4_define([$1($2)], [$3])]) # lt_dict_add_subkey(DICT, KEY, SUBKEY, VALUE) # -------------------------------------------- m4_define([lt_dict_add_subkey], [m4_define([$1($2:$3)], [$4])]) # lt_dict_fetch(DICT, KEY, [SUBKEY]) # ---------------------------------- m4_define([lt_dict_fetch], [m4_ifval([$3], m4_ifdef([$1($2:$3)], [m4_defn([$1($2:$3)])]), m4_ifdef([$1($2)], [m4_defn([$1($2)])]))]) # lt_if_dict_fetch(DICT, KEY, [SUBKEY], VALUE, IF-TRUE, [IF-FALSE]) # ----------------------------------------------------------------- m4_define([lt_if_dict_fetch], [m4_if(lt_dict_fetch([$1], [$2], [$3]), [$4], [$5], [$6])]) # lt_dict_filter(DICT, [SUBKEY], VALUE, [SEPARATOR], KEY, [...]) # -------------------------------------------------------------- m4_define([lt_dict_filter], [m4_if([$5], [], [], [lt_join(m4_quote(m4_default([$4], [[, ]])), lt_unquote(m4_split(m4_normalize(m4_foreach(_Lt_key, lt_car([m4_shiftn(4, $@)]), [lt_if_dict_fetch([$1], _Lt_key, [$2], [$3], [_Lt_key ])])))))])[]dnl ]) # ltversion.m4 -- version numbers -*- Autoconf -*- # # Copyright (C) 2004 Free Software Foundation, Inc. # Written by Scott James Remnant, 2004 # # This file is free software; the Free Software Foundation gives # unlimited permission to copy and/or distribute it, with or without # modifications, as long as this notice is preserved. # @configure_input@ # serial 3293 ltversion.m4 # This file is part of GNU Libtool m4_define([LT_PACKAGE_VERSION], [2.4]) m4_define([LT_PACKAGE_REVISION], [1.3293]) AC_DEFUN([LTVERSION_VERSION], [macro_version='2.4' macro_revision='1.3293' _LT_DECL(, macro_version, 0, [Which release of libtool.m4 was used?]) _LT_DECL(, macro_revision, 0) ]) # lt~obsolete.m4 -- aclocal satisfying obsolete definitions. -*-Autoconf-*- # # Copyright (C) 2004, 2005, 2007, 2009 Free Software Foundation, Inc. # Written by Scott James Remnant, 2004. # # This file is free software; the Free Software Foundation gives # unlimited permission to copy and/or distribute it, with or without # modifications, as long as this notice is preserved. # serial 5 lt~obsolete.m4 # These exist entirely to fool aclocal when bootstrapping libtool. # # In the past libtool.m4 has provided macros via AC_DEFUN (or AU_DEFUN) # which have later been changed to m4_define as they aren't part of the # exported API, or moved to Autoconf or Automake where they belong. # # The trouble is, aclocal is a bit thick. It'll see the old AC_DEFUN # in /usr/share/aclocal/libtool.m4 and remember it, then when it sees us # using a macro with the same name in our local m4/libtool.m4 it'll # pull the old libtool.m4 in (it doesn't see our shiny new m4_define # and doesn't know about Autoconf macros at all.) # # So we provide this file, which has a silly filename so it's always # included after everything else. This provides aclocal with the # AC_DEFUNs it wants, but when m4 processes it, it doesn't do anything # because those macros already exist, or will be overwritten later. # We use AC_DEFUN over AU_DEFUN for compatibility with aclocal-1.6. # # Anytime we withdraw an AC_DEFUN or AU_DEFUN, remember to add it here. # Yes, that means every name once taken will need to remain here until # we give up compatibility with versions before 1.7, at which point # we need to keep only those names which we still refer to. # This is to help aclocal find these macros, as it can't see m4_define. AC_DEFUN([LTOBSOLETE_VERSION], [m4_if([1])]) m4_ifndef([AC_LIBTOOL_LINKER_OPTION], [AC_DEFUN([AC_LIBTOOL_LINKER_OPTION])]) m4_ifndef([AC_PROG_EGREP], [AC_DEFUN([AC_PROG_EGREP])]) m4_ifndef([_LT_AC_PROG_ECHO_BACKSLASH], [AC_DEFUN([_LT_AC_PROG_ECHO_BACKSLASH])]) m4_ifndef([_LT_AC_SHELL_INIT], [AC_DEFUN([_LT_AC_SHELL_INIT])]) m4_ifndef([_LT_AC_SYS_LIBPATH_AIX], [AC_DEFUN([_LT_AC_SYS_LIBPATH_AIX])]) m4_ifndef([_LT_PROG_LTMAIN], [AC_DEFUN([_LT_PROG_LTMAIN])]) m4_ifndef([_LT_AC_TAGVAR], [AC_DEFUN([_LT_AC_TAGVAR])]) m4_ifndef([AC_LTDL_ENABLE_INSTALL], [AC_DEFUN([AC_LTDL_ENABLE_INSTALL])]) m4_ifndef([AC_LTDL_PREOPEN], [AC_DEFUN([AC_LTDL_PREOPEN])]) m4_ifndef([_LT_AC_SYS_COMPILER], [AC_DEFUN([_LT_AC_SYS_COMPILER])]) m4_ifndef([_LT_AC_LOCK], [AC_DEFUN([_LT_AC_LOCK])]) m4_ifndef([AC_LIBTOOL_SYS_OLD_ARCHIVE], [AC_DEFUN([AC_LIBTOOL_SYS_OLD_ARCHIVE])]) m4_ifndef([_LT_AC_TRY_DLOPEN_SELF], [AC_DEFUN([_LT_AC_TRY_DLOPEN_SELF])]) m4_ifndef([AC_LIBTOOL_PROG_CC_C_O], [AC_DEFUN([AC_LIBTOOL_PROG_CC_C_O])]) m4_ifndef([AC_LIBTOOL_SYS_HARD_LINK_LOCKS], [AC_DEFUN([AC_LIBTOOL_SYS_HARD_LINK_LOCKS])]) m4_ifndef([AC_LIBTOOL_OBJDIR], [AC_DEFUN([AC_LIBTOOL_OBJDIR])]) m4_ifndef([AC_LTDL_OBJDIR], [AC_DEFUN([AC_LTDL_OBJDIR])]) m4_ifndef([AC_LIBTOOL_PROG_LD_HARDCODE_LIBPATH], [AC_DEFUN([AC_LIBTOOL_PROG_LD_HARDCODE_LIBPATH])]) m4_ifndef([AC_LIBTOOL_SYS_LIB_STRIP], [AC_DEFUN([AC_LIBTOOL_SYS_LIB_STRIP])]) m4_ifndef([AC_PATH_MAGIC], [AC_DEFUN([AC_PATH_MAGIC])]) m4_ifndef([AC_PROG_LD_GNU], [AC_DEFUN([AC_PROG_LD_GNU])]) m4_ifndef([AC_PROG_LD_RELOAD_FLAG], [AC_DEFUN([AC_PROG_LD_RELOAD_FLAG])]) m4_ifndef([AC_DEPLIBS_CHECK_METHOD], [AC_DEFUN([AC_DEPLIBS_CHECK_METHOD])]) m4_ifndef([AC_LIBTOOL_PROG_COMPILER_NO_RTTI], [AC_DEFUN([AC_LIBTOOL_PROG_COMPILER_NO_RTTI])]) m4_ifndef([AC_LIBTOOL_SYS_GLOBAL_SYMBOL_PIPE], [AC_DEFUN([AC_LIBTOOL_SYS_GLOBAL_SYMBOL_PIPE])]) m4_ifndef([AC_LIBTOOL_PROG_COMPILER_PIC], [AC_DEFUN([AC_LIBTOOL_PROG_COMPILER_PIC])]) m4_ifndef([AC_LIBTOOL_PROG_LD_SHLIBS], [AC_DEFUN([AC_LIBTOOL_PROG_LD_SHLIBS])]) m4_ifndef([AC_LIBTOOL_POSTDEP_PREDEP], [AC_DEFUN([AC_LIBTOOL_POSTDEP_PREDEP])]) m4_ifndef([LT_AC_PROG_EGREP], [AC_DEFUN([LT_AC_PROG_EGREP])]) m4_ifndef([LT_AC_PROG_SED], [AC_DEFUN([LT_AC_PROG_SED])]) m4_ifndef([_LT_CC_BASENAME], [AC_DEFUN([_LT_CC_BASENAME])]) m4_ifndef([_LT_COMPILER_BOILERPLATE], [AC_DEFUN([_LT_COMPILER_BOILERPLATE])]) m4_ifndef([_LT_LINKER_BOILERPLATE], [AC_DEFUN([_LT_LINKER_BOILERPLATE])]) m4_ifndef([_AC_PROG_LIBTOOL], [AC_DEFUN([_AC_PROG_LIBTOOL])]) m4_ifndef([AC_LIBTOOL_SETUP], [AC_DEFUN([AC_LIBTOOL_SETUP])]) m4_ifndef([_LT_AC_CHECK_DLFCN], [AC_DEFUN([_LT_AC_CHECK_DLFCN])]) m4_ifndef([AC_LIBTOOL_SYS_DYNAMIC_LINKER], [AC_DEFUN([AC_LIBTOOL_SYS_DYNAMIC_LINKER])]) m4_ifndef([_LT_AC_TAGCONFIG], [AC_DEFUN([_LT_AC_TAGCONFIG])]) m4_ifndef([AC_DISABLE_FAST_INSTALL], [AC_DEFUN([AC_DISABLE_FAST_INSTALL])]) m4_ifndef([_LT_AC_LANG_CXX], [AC_DEFUN([_LT_AC_LANG_CXX])]) m4_ifndef([_LT_AC_LANG_F77], [AC_DEFUN([_LT_AC_LANG_F77])]) m4_ifndef([_LT_AC_LANG_GCJ], [AC_DEFUN([_LT_AC_LANG_GCJ])]) m4_ifndef([AC_LIBTOOL_LANG_C_CONFIG], [AC_DEFUN([AC_LIBTOOL_LANG_C_CONFIG])]) m4_ifndef([_LT_AC_LANG_C_CONFIG], [AC_DEFUN([_LT_AC_LANG_C_CONFIG])]) m4_ifndef([AC_LIBTOOL_LANG_CXX_CONFIG], [AC_DEFUN([AC_LIBTOOL_LANG_CXX_CONFIG])]) m4_ifndef([_LT_AC_LANG_CXX_CONFIG], [AC_DEFUN([_LT_AC_LANG_CXX_CONFIG])]) m4_ifndef([AC_LIBTOOL_LANG_F77_CONFIG], [AC_DEFUN([AC_LIBTOOL_LANG_F77_CONFIG])]) m4_ifndef([_LT_AC_LANG_F77_CONFIG], [AC_DEFUN([_LT_AC_LANG_F77_CONFIG])]) m4_ifndef([AC_LIBTOOL_LANG_GCJ_CONFIG], [AC_DEFUN([AC_LIBTOOL_LANG_GCJ_CONFIG])]) m4_ifndef([_LT_AC_LANG_GCJ_CONFIG], [AC_DEFUN([_LT_AC_LANG_GCJ_CONFIG])]) m4_ifndef([AC_LIBTOOL_LANG_RC_CONFIG], [AC_DEFUN([AC_LIBTOOL_LANG_RC_CONFIG])]) m4_ifndef([_LT_AC_LANG_RC_CONFIG], [AC_DEFUN([_LT_AC_LANG_RC_CONFIG])]) m4_ifndef([AC_LIBTOOL_CONFIG], [AC_DEFUN([AC_LIBTOOL_CONFIG])]) m4_ifndef([_LT_AC_FILE_LTDLL_C], [AC_DEFUN([_LT_AC_FILE_LTDLL_C])]) m4_ifndef([_LT_REQUIRED_DARWIN_CHECKS], [AC_DEFUN([_LT_REQUIRED_DARWIN_CHECKS])]) m4_ifndef([_LT_AC_PROG_CXXCPP], [AC_DEFUN([_LT_AC_PROG_CXXCPP])]) m4_ifndef([_LT_PREPARE_SED_QUOTE_VARS], [AC_DEFUN([_LT_PREPARE_SED_QUOTE_VARS])]) m4_ifndef([_LT_PROG_ECHO_BACKSLASH], [AC_DEFUN([_LT_PROG_ECHO_BACKSLASH])]) m4_ifndef([_LT_PROG_F77], [AC_DEFUN([_LT_PROG_F77])]) m4_ifndef([_LT_PROG_FC], [AC_DEFUN([_LT_PROG_FC])]) m4_ifndef([_LT_PROG_CXX], [AC_DEFUN([_LT_PROG_CXX])]) # pkg.m4 - Macros to locate and utilise pkg-config. -*- Autoconf -*- # serial 1 (pkg-config-0.24) # # Copyright © 2004 Scott James Remnant . # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by # the Free Software Foundation; either version 2 of the License, or # (at your option) any later version. # # This program is distributed in the hope that it will be useful, but # WITHOUT ANY WARRANTY; without even the implied warranty of # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU # General Public License for more details. # # You should have received a copy of the GNU General Public License # along with this program; if not, write to the Free Software # Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA. # # As a special exception to the GNU General Public License, if you # distribute this file as part of a program that contains a # configuration script generated by Autoconf, you may include it under # the same distribution terms that you use for the rest of that program. # PKG_PROG_PKG_CONFIG([MIN-VERSION]) # ---------------------------------- AC_DEFUN([PKG_PROG_PKG_CONFIG], [m4_pattern_forbid([^_?PKG_[A-Z_]+$]) m4_pattern_allow([^PKG_CONFIG(_(PATH|LIBDIR|SYSROOT_DIR|ALLOW_SYSTEM_(CFLAGS|LIBS)))?$]) m4_pattern_allow([^PKG_CONFIG_(DISABLE_UNINSTALLED|TOP_BUILD_DIR|DEBUG_SPEW)$]) AC_ARG_VAR([PKG_CONFIG], [path to pkg-config utility]) AC_ARG_VAR([PKG_CONFIG_PATH], [directories to add to pkg-config's search path]) AC_ARG_VAR([PKG_CONFIG_LIBDIR], [path overriding pkg-config's built-in search path]) if test "x$ac_cv_env_PKG_CONFIG_set" != "xset"; then AC_PATH_TOOL([PKG_CONFIG], [pkg-config]) fi if test -n "$PKG_CONFIG"; then _pkg_min_version=m4_default([$1], [0.9.0]) AC_MSG_CHECKING([pkg-config is at least version $_pkg_min_version]) if $PKG_CONFIG --atleast-pkgconfig-version $_pkg_min_version; then AC_MSG_RESULT([yes]) else AC_MSG_RESULT([no]) PKG_CONFIG="" fi fi[]dnl ])# PKG_PROG_PKG_CONFIG # PKG_CHECK_EXISTS(MODULES, [ACTION-IF-FOUND], [ACTION-IF-NOT-FOUND]) # # Check to see whether a particular set of modules exists. Similar # to PKG_CHECK_MODULES(), but does not set variables or print errors. # # Please remember that m4 expands AC_REQUIRE([PKG_PROG_PKG_CONFIG]) # only at the first occurence in configure.ac, so if the first place # it's called might be skipped (such as if it is within an "if", you # have to call PKG_CHECK_EXISTS manually # -------------------------------------------------------------- AC_DEFUN([PKG_CHECK_EXISTS], [AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl if test -n "$PKG_CONFIG" && \ AC_RUN_LOG([$PKG_CONFIG --exists --print-errors "$1"]); then m4_default([$2], [:]) m4_ifvaln([$3], [else $3])dnl fi]) # _PKG_CONFIG([VARIABLE], [COMMAND], [MODULES]) # --------------------------------------------- m4_define([_PKG_CONFIG], [if test -n "$$1"; then pkg_cv_[]$1="$$1" elif test -n "$PKG_CONFIG"; then PKG_CHECK_EXISTS([$3], [pkg_cv_[]$1=`$PKG_CONFIG --[]$2 "$3" 2>/dev/null` test "x$?" != "x0" && pkg_failed=yes ], [pkg_failed=yes]) else pkg_failed=untried fi[]dnl ])# _PKG_CONFIG # _PKG_SHORT_ERRORS_SUPPORTED # ----------------------------- AC_DEFUN([_PKG_SHORT_ERRORS_SUPPORTED], [AC_REQUIRE([PKG_PROG_PKG_CONFIG]) if $PKG_CONFIG --atleast-pkgconfig-version 0.20; then _pkg_short_errors_supported=yes else _pkg_short_errors_supported=no fi[]dnl ])# _PKG_SHORT_ERRORS_SUPPORTED # PKG_CHECK_MODULES(VARIABLE-PREFIX, MODULES, [ACTION-IF-FOUND], # [ACTION-IF-NOT-FOUND]) # # # Note that if there is a possibility the first call to # PKG_CHECK_MODULES might not happen, you should be sure to include an # explicit call to PKG_PROG_PKG_CONFIG in your configure.ac # # # -------------------------------------------------------------- AC_DEFUN([PKG_CHECK_MODULES], [AC_REQUIRE([PKG_PROG_PKG_CONFIG])dnl AC_ARG_VAR([$1][_CFLAGS], [C compiler flags for $1, overriding pkg-config])dnl AC_ARG_VAR([$1][_LIBS], [linker flags for $1, overriding pkg-config])dnl pkg_failed=no AC_MSG_CHECKING([for $1]) _PKG_CONFIG([$1][_CFLAGS], [cflags], [$2]) _PKG_CONFIG([$1][_LIBS], [libs], [$2]) m4_define([_PKG_TEXT], [Alternatively, you may set the environment variables $1[]_CFLAGS and $1[]_LIBS to avoid the need to call pkg-config. See the pkg-config man page for more details.]) if test $pkg_failed = yes; then AC_MSG_RESULT([no]) _PKG_SHORT_ERRORS_SUPPORTED if test $_pkg_short_errors_supported = yes; then $1[]_PKG_ERRORS=`$PKG_CONFIG --short-errors --print-errors --cflags --libs "$2" 2>&1` else $1[]_PKG_ERRORS=`$PKG_CONFIG --print-errors --cflags --libs "$2" 2>&1` fi # Put the nasty error message in config.log where it belongs echo "$$1[]_PKG_ERRORS" >&AS_MESSAGE_LOG_FD m4_default([$4], [AC_MSG_ERROR( [Package requirements ($2) were not met: $$1_PKG_ERRORS Consider adjusting the PKG_CONFIG_PATH environment variable if you installed software in a non-standard prefix. _PKG_TEXT])[]dnl ]) elif test $pkg_failed = untried; then AC_MSG_RESULT([no]) m4_default([$4], [AC_MSG_FAILURE( [The pkg-config script could not be found or is too old. Make sure it is in your PATH or set the PKG_CONFIG environment variable to the full path to pkg-config. _PKG_TEXT To get pkg-config, see .])[]dnl ]) else $1[]_CFLAGS=$pkg_cv_[]$1[]_CFLAGS $1[]_LIBS=$pkg_cv_[]$1[]_LIBS AC_MSG_RESULT([yes]) $3 fi[]dnl ])# PKG_CHECK_MODULES # Copyright (C) 2002, 2003, 2005, 2006, 2007, 2008 Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # AM_AUTOMAKE_VERSION(VERSION) # ---------------------------- # Automake X.Y traces this macro to ensure aclocal.m4 has been # generated from the m4 files accompanying Automake X.Y. # (This private macro should not be called outside this file.) AC_DEFUN([AM_AUTOMAKE_VERSION], [am__api_version='1.11' dnl Some users find AM_AUTOMAKE_VERSION and mistake it for a way to dnl require some minimum version. Point them to the right macro. m4_if([$1], [1.11.1], [], [AC_FATAL([Do not call $0, use AM_INIT_AUTOMAKE([$1]).])])dnl ]) # _AM_AUTOCONF_VERSION(VERSION) # ----------------------------- # aclocal traces this macro to find the Autoconf version. # This is a private macro too. Using m4_define simplifies # the logic in aclocal, which can simply ignore this definition. m4_define([_AM_AUTOCONF_VERSION], []) # AM_SET_CURRENT_AUTOMAKE_VERSION # ------------------------------- # Call AM_AUTOMAKE_VERSION and AM_AUTOMAKE_VERSION so they can be traced. # This function is AC_REQUIREd by AM_INIT_AUTOMAKE. AC_DEFUN([AM_SET_CURRENT_AUTOMAKE_VERSION], [AM_AUTOMAKE_VERSION([1.11.1])dnl m4_ifndef([AC_AUTOCONF_VERSION], [m4_copy([m4_PACKAGE_VERSION], [AC_AUTOCONF_VERSION])])dnl _AM_AUTOCONF_VERSION(m4_defn([AC_AUTOCONF_VERSION]))]) # AM_AUX_DIR_EXPAND -*- Autoconf -*- # Copyright (C) 2001, 2003, 2005 Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # For projects using AC_CONFIG_AUX_DIR([foo]), Autoconf sets # $ac_aux_dir to `$srcdir/foo'. In other projects, it is set to # `$srcdir', `$srcdir/..', or `$srcdir/../..'. # # Of course, Automake must honor this variable whenever it calls a # tool from the auxiliary directory. The problem is that $srcdir (and # therefore $ac_aux_dir as well) can be either absolute or relative, # depending on how configure is run. This is pretty annoying, since # it makes $ac_aux_dir quite unusable in subdirectories: in the top # source directory, any form will work fine, but in subdirectories a # relative path needs to be adjusted first. # # $ac_aux_dir/missing # fails when called from a subdirectory if $ac_aux_dir is relative # $top_srcdir/$ac_aux_dir/missing # fails if $ac_aux_dir is absolute, # fails when called from a subdirectory in a VPATH build with # a relative $ac_aux_dir # # The reason of the latter failure is that $top_srcdir and $ac_aux_dir # are both prefixed by $srcdir. In an in-source build this is usually # harmless because $srcdir is `.', but things will broke when you # start a VPATH build or use an absolute $srcdir. # # So we could use something similar to $top_srcdir/$ac_aux_dir/missing, # iff we strip the leading $srcdir from $ac_aux_dir. That would be: # am_aux_dir='\$(top_srcdir)/'`expr "$ac_aux_dir" : "$srcdir//*\(.*\)"` # and then we would define $MISSING as # MISSING="\${SHELL} $am_aux_dir/missing" # This will work as long as MISSING is not called from configure, because # unfortunately $(top_srcdir) has no meaning in configure. # However there are other variables, like CC, which are often used in # configure, and could therefore not use this "fixed" $ac_aux_dir. # # Another solution, used here, is to always expand $ac_aux_dir to an # absolute PATH. The drawback is that using absolute paths prevent a # configured tree to be moved without reconfiguration. AC_DEFUN([AM_AUX_DIR_EXPAND], [dnl Rely on autoconf to set up CDPATH properly. AC_PREREQ([2.50])dnl # expand $ac_aux_dir to an absolute path am_aux_dir=`cd $ac_aux_dir && pwd` ]) # AM_CONDITIONAL -*- Autoconf -*- # Copyright (C) 1997, 2000, 2001, 2003, 2004, 2005, 2006, 2008 # Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # serial 9 # AM_CONDITIONAL(NAME, SHELL-CONDITION) # ------------------------------------- # Define a conditional. AC_DEFUN([AM_CONDITIONAL], [AC_PREREQ(2.52)dnl ifelse([$1], [TRUE], [AC_FATAL([$0: invalid condition: $1])], [$1], [FALSE], [AC_FATAL([$0: invalid condition: $1])])dnl AC_SUBST([$1_TRUE])dnl AC_SUBST([$1_FALSE])dnl _AM_SUBST_NOTMAKE([$1_TRUE])dnl _AM_SUBST_NOTMAKE([$1_FALSE])dnl m4_define([_AM_COND_VALUE_$1], [$2])dnl if $2; then $1_TRUE= $1_FALSE='#' else $1_TRUE='#' $1_FALSE= fi AC_CONFIG_COMMANDS_PRE( [if test -z "${$1_TRUE}" && test -z "${$1_FALSE}"; then AC_MSG_ERROR([[conditional "$1" was never defined. Usually this means the macro was only invoked conditionally.]]) fi])]) # Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2006, 2009 # Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # serial 10 # There are a few dirty hacks below to avoid letting `AC_PROG_CC' be # written in clear, in which case automake, when reading aclocal.m4, # will think it sees a *use*, and therefore will trigger all it's # C support machinery. Also note that it means that autoscan, seeing # CC etc. in the Makefile, will ask for an AC_PROG_CC use... # _AM_DEPENDENCIES(NAME) # ---------------------- # See how the compiler implements dependency checking. # NAME is "CC", "CXX", "GCJ", or "OBJC". # We try a few techniques and use that to set a single cache variable. # # We don't AC_REQUIRE the corresponding AC_PROG_CC since the latter was # modified to invoke _AM_DEPENDENCIES(CC); we would have a circular # dependency, and given that the user is not expected to run this macro, # just rely on AC_PROG_CC. AC_DEFUN([_AM_DEPENDENCIES], [AC_REQUIRE([AM_SET_DEPDIR])dnl AC_REQUIRE([AM_OUTPUT_DEPENDENCY_COMMANDS])dnl AC_REQUIRE([AM_MAKE_INCLUDE])dnl AC_REQUIRE([AM_DEP_TRACK])dnl ifelse([$1], CC, [depcc="$CC" am_compiler_list=], [$1], CXX, [depcc="$CXX" am_compiler_list=], [$1], OBJC, [depcc="$OBJC" am_compiler_list='gcc3 gcc'], [$1], UPC, [depcc="$UPC" am_compiler_list=], [$1], GCJ, [depcc="$GCJ" am_compiler_list='gcc3 gcc'], [depcc="$$1" am_compiler_list=]) AC_CACHE_CHECK([dependency style of $depcc], [am_cv_$1_dependencies_compiler_type], [if test -z "$AMDEP_TRUE" && test -f "$am_depcomp"; then # We make a subdir and do the tests there. Otherwise we can end up # making bogus files that we don't know about and never remove. For # instance it was reported that on HP-UX the gcc test will end up # making a dummy file named `D' -- because `-MD' means `put the output # in D'. mkdir conftest.dir # Copy depcomp to subdir because otherwise we won't find it if we're # using a relative directory. cp "$am_depcomp" conftest.dir cd conftest.dir # We will build objects and dependencies in a subdirectory because # it helps to detect inapplicable dependency modes. For instance # both Tru64's cc and ICC support -MD to output dependencies as a # side effect of compilation, but ICC will put the dependencies in # the current directory while Tru64 will put them in the object # directory. mkdir sub am_cv_$1_dependencies_compiler_type=none if test "$am_compiler_list" = ""; then am_compiler_list=`sed -n ['s/^#*\([a-zA-Z0-9]*\))$/\1/p'] < ./depcomp` fi am__universal=false m4_case([$1], [CC], [case " $depcc " in #( *\ -arch\ *\ -arch\ *) am__universal=true ;; esac], [CXX], [case " $depcc " in #( *\ -arch\ *\ -arch\ *) am__universal=true ;; esac]) for depmode in $am_compiler_list; do # Setup a source with many dependencies, because some compilers # like to wrap large dependency lists on column 80 (with \), and # we should not choose a depcomp mode which is confused by this. # # We need to recreate these files for each test, as the compiler may # overwrite some of them when testing with obscure command lines. # This happens at least with the AIX C compiler. : > sub/conftest.c for i in 1 2 3 4 5 6; do echo '#include "conftst'$i'.h"' >> sub/conftest.c # Using `: > sub/conftst$i.h' creates only sub/conftst1.h with # Solaris 8's {/usr,}/bin/sh. touch sub/conftst$i.h done echo "${am__include} ${am__quote}sub/conftest.Po${am__quote}" > confmf # We check with `-c' and `-o' for the sake of the "dashmstdout" # mode. It turns out that the SunPro C++ compiler does not properly # handle `-M -o', and we need to detect this. Also, some Intel # versions had trouble with output in subdirs am__obj=sub/conftest.${OBJEXT-o} am__minus_obj="-o $am__obj" case $depmode in gcc) # This depmode causes a compiler race in universal mode. test "$am__universal" = false || continue ;; nosideeffect) # after this tag, mechanisms are not by side-effect, so they'll # only be used when explicitly requested if test "x$enable_dependency_tracking" = xyes; then continue else break fi ;; msvisualcpp | msvcmsys) # This compiler won't grok `-c -o', but also, the minuso test has # not run yet. These depmodes are late enough in the game, and # so weak that their functioning should not be impacted. am__obj=conftest.${OBJEXT-o} am__minus_obj= ;; none) break ;; esac if depmode=$depmode \ source=sub/conftest.c object=$am__obj \ depfile=sub/conftest.Po tmpdepfile=sub/conftest.TPo \ $SHELL ./depcomp $depcc -c $am__minus_obj sub/conftest.c \ >/dev/null 2>conftest.err && grep sub/conftst1.h sub/conftest.Po > /dev/null 2>&1 && grep sub/conftst6.h sub/conftest.Po > /dev/null 2>&1 && grep $am__obj sub/conftest.Po > /dev/null 2>&1 && ${MAKE-make} -s -f confmf > /dev/null 2>&1; then # icc doesn't choke on unknown options, it will just issue warnings # or remarks (even with -Werror). So we grep stderr for any message # that says an option was ignored or not supported. # When given -MP, icc 7.0 and 7.1 complain thusly: # icc: Command line warning: ignoring option '-M'; no argument required # The diagnosis changed in icc 8.0: # icc: Command line remark: option '-MP' not supported if (grep 'ignoring option' conftest.err || grep 'not supported' conftest.err) >/dev/null 2>&1; then :; else am_cv_$1_dependencies_compiler_type=$depmode break fi fi done cd .. rm -rf conftest.dir else am_cv_$1_dependencies_compiler_type=none fi ]) AC_SUBST([$1DEPMODE], [depmode=$am_cv_$1_dependencies_compiler_type]) AM_CONDITIONAL([am__fastdep$1], [ test "x$enable_dependency_tracking" != xno \ && test "$am_cv_$1_dependencies_compiler_type" = gcc3]) ]) # AM_SET_DEPDIR # ------------- # Choose a directory name for dependency files. # This macro is AC_REQUIREd in _AM_DEPENDENCIES AC_DEFUN([AM_SET_DEPDIR], [AC_REQUIRE([AM_SET_LEADING_DOT])dnl AC_SUBST([DEPDIR], ["${am__leading_dot}deps"])dnl ]) # AM_DEP_TRACK # ------------ AC_DEFUN([AM_DEP_TRACK], [AC_ARG_ENABLE(dependency-tracking, [ --disable-dependency-tracking speeds up one-time build --enable-dependency-tracking do not reject slow dependency extractors]) if test "x$enable_dependency_tracking" != xno; then am_depcomp="$ac_aux_dir/depcomp" AMDEPBACKSLASH='\' fi AM_CONDITIONAL([AMDEP], [test "x$enable_dependency_tracking" != xno]) AC_SUBST([AMDEPBACKSLASH])dnl _AM_SUBST_NOTMAKE([AMDEPBACKSLASH])dnl ]) # Generate code to set up dependency tracking. -*- Autoconf -*- # Copyright (C) 1999, 2000, 2001, 2002, 2003, 2004, 2005, 2008 # Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. #serial 5 # _AM_OUTPUT_DEPENDENCY_COMMANDS # ------------------------------ AC_DEFUN([_AM_OUTPUT_DEPENDENCY_COMMANDS], [{ # Autoconf 2.62 quotes --file arguments for eval, but not when files # are listed without --file. Let's play safe and only enable the eval # if we detect the quoting. case $CONFIG_FILES in *\'*) eval set x "$CONFIG_FILES" ;; *) set x $CONFIG_FILES ;; esac shift for mf do # Strip MF so we end up with the name of the file. mf=`echo "$mf" | sed -e 's/:.*$//'` # Check whether this is an Automake generated Makefile or not. # We used to match only the files named `Makefile.in', but # some people rename them; so instead we look at the file content. # Grep'ing the first line is not enough: some people post-process # each Makefile.in and add a new line on top of each file to say so. # Grep'ing the whole file is not good either: AIX grep has a line # limit of 2048, but all sed's we know have understand at least 4000. if sed -n 's,^#.*generated by automake.*,X,p' "$mf" | grep X >/dev/null 2>&1; then dirpart=`AS_DIRNAME("$mf")` else continue fi # Extract the definition of DEPDIR, am__include, and am__quote # from the Makefile without running `make'. DEPDIR=`sed -n 's/^DEPDIR = //p' < "$mf"` test -z "$DEPDIR" && continue am__include=`sed -n 's/^am__include = //p' < "$mf"` test -z "am__include" && continue am__quote=`sed -n 's/^am__quote = //p' < "$mf"` # When using ansi2knr, U may be empty or an underscore; expand it U=`sed -n 's/^U = //p' < "$mf"` # Find all dependency output files, they are included files with # $(DEPDIR) in their names. We invoke sed twice because it is the # simplest approach to changing $(DEPDIR) to its actual value in the # expansion. for file in `sed -n " s/^$am__include $am__quote\(.*(DEPDIR).*\)$am__quote"'$/\1/p' <"$mf" | \ sed -e 's/\$(DEPDIR)/'"$DEPDIR"'/g' -e 's/\$U/'"$U"'/g'`; do # Make sure the directory exists. test -f "$dirpart/$file" && continue fdir=`AS_DIRNAME(["$file"])` AS_MKDIR_P([$dirpart/$fdir]) # echo "creating $dirpart/$file" echo '# dummy' > "$dirpart/$file" done done } ])# _AM_OUTPUT_DEPENDENCY_COMMANDS # AM_OUTPUT_DEPENDENCY_COMMANDS # ----------------------------- # This macro should only be invoked once -- use via AC_REQUIRE. # # This code is only required when automatic dependency tracking # is enabled. FIXME. This creates each `.P' file that we will # need in order to bootstrap the dependency handling code. AC_DEFUN([AM_OUTPUT_DEPENDENCY_COMMANDS], [AC_CONFIG_COMMANDS([depfiles], [test x"$AMDEP_TRUE" != x"" || _AM_OUTPUT_DEPENDENCY_COMMANDS], [AMDEP_TRUE="$AMDEP_TRUE" ac_aux_dir="$ac_aux_dir"]) ]) # Copyright (C) 1996, 1997, 2000, 2001, 2003, 2005 # Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # serial 8 # AM_CONFIG_HEADER is obsolete. It has been replaced by AC_CONFIG_HEADERS. AU_DEFUN([AM_CONFIG_HEADER], [AC_CONFIG_HEADERS($@)]) # Do all the work for Automake. -*- Autoconf -*- # Copyright (C) 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003, 2004, # 2005, 2006, 2008, 2009 Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # serial 16 # This macro actually does too much. Some checks are only needed if # your package does certain things. But this isn't really a big deal. # AM_INIT_AUTOMAKE(PACKAGE, VERSION, [NO-DEFINE]) # AM_INIT_AUTOMAKE([OPTIONS]) # ----------------------------------------------- # The call with PACKAGE and VERSION arguments is the old style # call (pre autoconf-2.50), which is being phased out. PACKAGE # and VERSION should now be passed to AC_INIT and removed from # the call to AM_INIT_AUTOMAKE. # We support both call styles for the transition. After # the next Automake release, Autoconf can make the AC_INIT # arguments mandatory, and then we can depend on a new Autoconf # release and drop the old call support. AC_DEFUN([AM_INIT_AUTOMAKE], [AC_PREREQ([2.62])dnl dnl Autoconf wants to disallow AM_ names. We explicitly allow dnl the ones we care about. m4_pattern_allow([^AM_[A-Z]+FLAGS$])dnl AC_REQUIRE([AM_SET_CURRENT_AUTOMAKE_VERSION])dnl AC_REQUIRE([AC_PROG_INSTALL])dnl if test "`cd $srcdir && pwd`" != "`pwd`"; then # Use -I$(srcdir) only when $(srcdir) != ., so that make's output # is not polluted with repeated "-I." AC_SUBST([am__isrc], [' -I$(srcdir)'])_AM_SUBST_NOTMAKE([am__isrc])dnl # test to see if srcdir already configured if test -f $srcdir/config.status; then AC_MSG_ERROR([source directory already configured; run "make distclean" there first]) fi fi # test whether we have cygpath if test -z "$CYGPATH_W"; then if (cygpath --version) >/dev/null 2>/dev/null; then CYGPATH_W='cygpath -w' else CYGPATH_W=echo fi fi AC_SUBST([CYGPATH_W]) # Define the identity of the package. dnl Distinguish between old-style and new-style calls. m4_ifval([$2], [m4_ifval([$3], [_AM_SET_OPTION([no-define])])dnl AC_SUBST([PACKAGE], [$1])dnl AC_SUBST([VERSION], [$2])], [_AM_SET_OPTIONS([$1])dnl dnl Diagnose old-style AC_INIT with new-style AM_AUTOMAKE_INIT. m4_if(m4_ifdef([AC_PACKAGE_NAME], 1)m4_ifdef([AC_PACKAGE_VERSION], 1), 11,, [m4_fatal([AC_INIT should be called with package and version arguments])])dnl AC_SUBST([PACKAGE], ['AC_PACKAGE_TARNAME'])dnl AC_SUBST([VERSION], ['AC_PACKAGE_VERSION'])])dnl _AM_IF_OPTION([no-define],, [AC_DEFINE_UNQUOTED(PACKAGE, "$PACKAGE", [Name of package]) AC_DEFINE_UNQUOTED(VERSION, "$VERSION", [Version number of package])])dnl # Some tools Automake needs. AC_REQUIRE([AM_SANITY_CHECK])dnl AC_REQUIRE([AC_ARG_PROGRAM])dnl AM_MISSING_PROG(ACLOCAL, aclocal-${am__api_version}) AM_MISSING_PROG(AUTOCONF, autoconf) AM_MISSING_PROG(AUTOMAKE, automake-${am__api_version}) AM_MISSING_PROG(AUTOHEADER, autoheader) AM_MISSING_PROG(MAKEINFO, makeinfo) AC_REQUIRE([AM_PROG_INSTALL_SH])dnl AC_REQUIRE([AM_PROG_INSTALL_STRIP])dnl AC_REQUIRE([AM_PROG_MKDIR_P])dnl # We need awk for the "check" target. The system "awk" is bad on # some platforms. AC_REQUIRE([AC_PROG_AWK])dnl AC_REQUIRE([AC_PROG_MAKE_SET])dnl AC_REQUIRE([AM_SET_LEADING_DOT])dnl _AM_IF_OPTION([tar-ustar], [_AM_PROG_TAR([ustar])], [_AM_IF_OPTION([tar-pax], [_AM_PROG_TAR([pax])], [_AM_PROG_TAR([v7])])]) _AM_IF_OPTION([no-dependencies],, [AC_PROVIDE_IFELSE([AC_PROG_CC], [_AM_DEPENDENCIES(CC)], [define([AC_PROG_CC], defn([AC_PROG_CC])[_AM_DEPENDENCIES(CC)])])dnl AC_PROVIDE_IFELSE([AC_PROG_CXX], [_AM_DEPENDENCIES(CXX)], [define([AC_PROG_CXX], defn([AC_PROG_CXX])[_AM_DEPENDENCIES(CXX)])])dnl AC_PROVIDE_IFELSE([AC_PROG_OBJC], [_AM_DEPENDENCIES(OBJC)], [define([AC_PROG_OBJC], defn([AC_PROG_OBJC])[_AM_DEPENDENCIES(OBJC)])])dnl ]) _AM_IF_OPTION([silent-rules], [AC_REQUIRE([AM_SILENT_RULES])])dnl dnl The `parallel-tests' driver may need to know about EXEEXT, so add the dnl `am__EXEEXT' conditional if _AM_COMPILER_EXEEXT was seen. This macro dnl is hooked onto _AC_COMPILER_EXEEXT early, see below. AC_CONFIG_COMMANDS_PRE(dnl [m4_provide_if([_AM_COMPILER_EXEEXT], [AM_CONDITIONAL([am__EXEEXT], [test -n "$EXEEXT"])])])dnl ]) dnl Hook into `_AC_COMPILER_EXEEXT' early to learn its expansion. Do not dnl add the conditional right here, as _AC_COMPILER_EXEEXT may be further dnl mangled by Autoconf and run in a shell conditional statement. m4_define([_AC_COMPILER_EXEEXT], m4_defn([_AC_COMPILER_EXEEXT])[m4_provide([_AM_COMPILER_EXEEXT])]) # When config.status generates a header, we must update the stamp-h file. # This file resides in the same directory as the config header # that is generated. The stamp files are numbered to have different names. # Autoconf calls _AC_AM_CONFIG_HEADER_HOOK (when defined) in the # loop where config.status creates the headers, so we can generate # our stamp files there. AC_DEFUN([_AC_AM_CONFIG_HEADER_HOOK], [# Compute $1's index in $config_headers. _am_arg=$1 _am_stamp_count=1 for _am_header in $config_headers :; do case $_am_header in $_am_arg | $_am_arg:* ) break ;; * ) _am_stamp_count=`expr $_am_stamp_count + 1` ;; esac done echo "timestamp for $_am_arg" >`AS_DIRNAME(["$_am_arg"])`/stamp-h[]$_am_stamp_count]) # Copyright (C) 2001, 2003, 2005, 2008 Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # AM_PROG_INSTALL_SH # ------------------ # Define $install_sh. AC_DEFUN([AM_PROG_INSTALL_SH], [AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl if test x"${install_sh}" != xset; then case $am_aux_dir in *\ * | *\ *) install_sh="\${SHELL} '$am_aux_dir/install-sh'" ;; *) install_sh="\${SHELL} $am_aux_dir/install-sh" esac fi AC_SUBST(install_sh)]) # Copyright (C) 2003, 2005 Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # serial 2 # Check whether the underlying file-system supports filenames # with a leading dot. For instance MS-DOS doesn't. AC_DEFUN([AM_SET_LEADING_DOT], [rm -rf .tst 2>/dev/null mkdir .tst 2>/dev/null if test -d .tst; then am__leading_dot=. else am__leading_dot=_ fi rmdir .tst 2>/dev/null AC_SUBST([am__leading_dot])]) # Add --enable-maintainer-mode option to configure. -*- Autoconf -*- # From Jim Meyering # Copyright (C) 1996, 1998, 2000, 2001, 2002, 2003, 2004, 2005, 2008 # Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # serial 5 # AM_MAINTAINER_MODE([DEFAULT-MODE]) # ---------------------------------- # Control maintainer-specific portions of Makefiles. # Default is to disable them, unless `enable' is passed literally. # For symmetry, `disable' may be passed as well. Anyway, the user # can override the default with the --enable/--disable switch. AC_DEFUN([AM_MAINTAINER_MODE], [m4_case(m4_default([$1], [disable]), [enable], [m4_define([am_maintainer_other], [disable])], [disable], [m4_define([am_maintainer_other], [enable])], [m4_define([am_maintainer_other], [enable]) m4_warn([syntax], [unexpected argument to AM@&t@_MAINTAINER_MODE: $1])]) AC_MSG_CHECKING([whether to am_maintainer_other maintainer-specific portions of Makefiles]) dnl maintainer-mode's default is 'disable' unless 'enable' is passed AC_ARG_ENABLE([maintainer-mode], [ --][am_maintainer_other][-maintainer-mode am_maintainer_other make rules and dependencies not useful (and sometimes confusing) to the casual installer], [USE_MAINTAINER_MODE=$enableval], [USE_MAINTAINER_MODE=]m4_if(am_maintainer_other, [enable], [no], [yes])) AC_MSG_RESULT([$USE_MAINTAINER_MODE]) AM_CONDITIONAL([MAINTAINER_MODE], [test $USE_MAINTAINER_MODE = yes]) MAINT=$MAINTAINER_MODE_TRUE AC_SUBST([MAINT])dnl ] ) AU_DEFUN([jm_MAINTAINER_MODE], [AM_MAINTAINER_MODE]) # Check to see how 'make' treats includes. -*- Autoconf -*- # Copyright (C) 2001, 2002, 2003, 2005, 2009 Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # serial 4 # AM_MAKE_INCLUDE() # ----------------- # Check to see how make treats includes. AC_DEFUN([AM_MAKE_INCLUDE], [am_make=${MAKE-make} cat > confinc << 'END' am__doit: @echo this is the am__doit target .PHONY: am__doit END # If we don't find an include directive, just comment out the code. AC_MSG_CHECKING([for style of include used by $am_make]) am__include="#" am__quote= _am_result=none # First try GNU make style include. echo "include confinc" > confmf # Ignore all kinds of additional output from `make'. case `$am_make -s -f confmf 2> /dev/null` in #( *the\ am__doit\ target*) am__include=include am__quote= _am_result=GNU ;; esac # Now try BSD make style include. if test "$am__include" = "#"; then echo '.include "confinc"' > confmf case `$am_make -s -f confmf 2> /dev/null` in #( *the\ am__doit\ target*) am__include=.include am__quote="\"" _am_result=BSD ;; esac fi AC_SUBST([am__include]) AC_SUBST([am__quote]) AC_MSG_RESULT([$_am_result]) rm -f confinc confmf ]) # Fake the existence of programs that GNU maintainers use. -*- Autoconf -*- # Copyright (C) 1997, 1999, 2000, 2001, 2003, 2004, 2005, 2008 # Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # serial 6 # AM_MISSING_PROG(NAME, PROGRAM) # ------------------------------ AC_DEFUN([AM_MISSING_PROG], [AC_REQUIRE([AM_MISSING_HAS_RUN]) $1=${$1-"${am_missing_run}$2"} AC_SUBST($1)]) # AM_MISSING_HAS_RUN # ------------------ # Define MISSING if not defined so far and test if it supports --run. # If it does, set am_missing_run to use it, otherwise, to nothing. AC_DEFUN([AM_MISSING_HAS_RUN], [AC_REQUIRE([AM_AUX_DIR_EXPAND])dnl AC_REQUIRE_AUX_FILE([missing])dnl if test x"${MISSING+set}" != xset; then case $am_aux_dir in *\ * | *\ *) MISSING="\${SHELL} \"$am_aux_dir/missing\"" ;; *) MISSING="\${SHELL} $am_aux_dir/missing" ;; esac fi # Use eval to expand $SHELL if eval "$MISSING --run true"; then am_missing_run="$MISSING --run " else am_missing_run= AC_MSG_WARN([`missing' script is too old or missing]) fi ]) # Copyright (C) 2003, 2004, 2005, 2006 Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # AM_PROG_MKDIR_P # --------------- # Check for `mkdir -p'. AC_DEFUN([AM_PROG_MKDIR_P], [AC_PREREQ([2.60])dnl AC_REQUIRE([AC_PROG_MKDIR_P])dnl dnl Automake 1.8 to 1.9.6 used to define mkdir_p. We now use MKDIR_P, dnl while keeping a definition of mkdir_p for backward compatibility. dnl @MKDIR_P@ is magic: AC_OUTPUT adjusts its value for each Makefile. dnl However we cannot define mkdir_p as $(MKDIR_P) for the sake of dnl Makefile.ins that do not define MKDIR_P, so we do our own dnl adjustment using top_builddir (which is defined more often than dnl MKDIR_P). AC_SUBST([mkdir_p], ["$MKDIR_P"])dnl case $mkdir_p in [[\\/$]]* | ?:[[\\/]]*) ;; */*) mkdir_p="\$(top_builddir)/$mkdir_p" ;; esac ]) # Helper functions for option handling. -*- Autoconf -*- # Copyright (C) 2001, 2002, 2003, 2005, 2008 Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # serial 4 # _AM_MANGLE_OPTION(NAME) # ----------------------- AC_DEFUN([_AM_MANGLE_OPTION], [[_AM_OPTION_]m4_bpatsubst($1, [[^a-zA-Z0-9_]], [_])]) # _AM_SET_OPTION(NAME) # ------------------------------ # Set option NAME. Presently that only means defining a flag for this option. AC_DEFUN([_AM_SET_OPTION], [m4_define(_AM_MANGLE_OPTION([$1]), 1)]) # _AM_SET_OPTIONS(OPTIONS) # ---------------------------------- # OPTIONS is a space-separated list of Automake options. AC_DEFUN([_AM_SET_OPTIONS], [m4_foreach_w([_AM_Option], [$1], [_AM_SET_OPTION(_AM_Option)])]) # _AM_IF_OPTION(OPTION, IF-SET, [IF-NOT-SET]) # ------------------------------------------- # Execute IF-SET if OPTION is set, IF-NOT-SET otherwise. AC_DEFUN([_AM_IF_OPTION], [m4_ifset(_AM_MANGLE_OPTION([$1]), [$2], [$3])]) # Check to make sure that the build environment is sane. -*- Autoconf -*- # Copyright (C) 1996, 1997, 2000, 2001, 2003, 2005, 2008 # Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # serial 5 # AM_SANITY_CHECK # --------------- AC_DEFUN([AM_SANITY_CHECK], [AC_MSG_CHECKING([whether build environment is sane]) # Just in case sleep 1 echo timestamp > conftest.file # Reject unsafe characters in $srcdir or the absolute working directory # name. Accept space and tab only in the latter. am_lf=' ' case `pwd` in *[[\\\"\#\$\&\'\`$am_lf]]*) AC_MSG_ERROR([unsafe absolute working directory name]);; esac case $srcdir in *[[\\\"\#\$\&\'\`$am_lf\ \ ]]*) AC_MSG_ERROR([unsafe srcdir value: `$srcdir']);; esac # Do `set' in a subshell so we don't clobber the current shell's # arguments. Must try -L first in case configure is actually a # symlink; some systems play weird games with the mod time of symlinks # (eg FreeBSD returns the mod time of the symlink's containing # directory). if ( set X `ls -Lt "$srcdir/configure" conftest.file 2> /dev/null` if test "$[*]" = "X"; then # -L didn't work. set X `ls -t "$srcdir/configure" conftest.file` fi rm -f conftest.file if test "$[*]" != "X $srcdir/configure conftest.file" \ && test "$[*]" != "X conftest.file $srcdir/configure"; then # If neither matched, then we have a broken ls. This can happen # if, for instance, CONFIG_SHELL is bash and it inherits a # broken ls alias from the environment. This has actually # happened. Such a system could not be considered "sane". AC_MSG_ERROR([ls -t appears to fail. Make sure there is not a broken alias in your environment]) fi test "$[2]" = conftest.file ) then # Ok. : else AC_MSG_ERROR([newly created file is older than distributed files! Check your system clock]) fi AC_MSG_RESULT(yes)]) # Copyright (C) 2001, 2003, 2005 Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # AM_PROG_INSTALL_STRIP # --------------------- # One issue with vendor `install' (even GNU) is that you can't # specify the program used to strip binaries. This is especially # annoying in cross-compiling environments, where the build's strip # is unlikely to handle the host's binaries. # Fortunately install-sh will honor a STRIPPROG variable, so we # always use install-sh in `make install-strip', and initialize # STRIPPROG with the value of the STRIP variable (set by the user). AC_DEFUN([AM_PROG_INSTALL_STRIP], [AC_REQUIRE([AM_PROG_INSTALL_SH])dnl # Installed binaries are usually stripped using `strip' when the user # run `make install-strip'. However `strip' might not be the right # tool to use in cross-compilation environments, therefore Automake # will honor the `STRIP' environment variable to overrule this program. dnl Don't test for $cross_compiling = yes, because it might be `maybe'. if test "$cross_compiling" != no; then AC_CHECK_TOOL([STRIP], [strip], :) fi INSTALL_STRIP_PROGRAM="\$(install_sh) -c -s" AC_SUBST([INSTALL_STRIP_PROGRAM])]) # Copyright (C) 2006, 2008 Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # serial 2 # _AM_SUBST_NOTMAKE(VARIABLE) # --------------------------- # Prevent Automake from outputting VARIABLE = @VARIABLE@ in Makefile.in. # This macro is traced by Automake. AC_DEFUN([_AM_SUBST_NOTMAKE]) # AM_SUBST_NOTMAKE(VARIABLE) # --------------------------- # Public sister of _AM_SUBST_NOTMAKE. AC_DEFUN([AM_SUBST_NOTMAKE], [_AM_SUBST_NOTMAKE($@)]) # Check how to create a tarball. -*- Autoconf -*- # Copyright (C) 2004, 2005 Free Software Foundation, Inc. # # This file is free software; the Free Software Foundation # gives unlimited permission to copy and/or distribute it, # with or without modifications, as long as this notice is preserved. # serial 2 # _AM_PROG_TAR(FORMAT) # -------------------- # Check how to create a tarball in format FORMAT. # FORMAT should be one of `v7', `ustar', or `pax'. # # Substitute a variable $(am__tar) that is a command # writing to stdout a FORMAT-tarball containing the directory # $tardir. # tardir=directory && $(am__tar) > result.tar # # Substitute a variable $(am__untar) that extract such # a tarball read from stdin. # $(am__untar) < result.tar AC_DEFUN([_AM_PROG_TAR], [# Always define AMTAR for backward compatibility. AM_MISSING_PROG([AMTAR], [tar]) m4_if([$1], [v7], [am__tar='${AMTAR} chof - "$$tardir"'; am__untar='${AMTAR} xf -'], [m4_case([$1], [ustar],, [pax],, [m4_fatal([Unknown tar format])]) AC_MSG_CHECKING([how to create a $1 tar archive]) # Loop over all known methods to create a tar archive until one works. _am_tools='gnutar m4_if([$1], [ustar], [plaintar]) pax cpio none' _am_tools=${am_cv_prog_tar_$1-$_am_tools} # Do not fold the above two line into one, because Tru64 sh and # Solaris sh will not grok spaces in the rhs of `-'. for _am_tool in $_am_tools do case $_am_tool in gnutar) for _am_tar in tar gnutar gtar; do AM_RUN_LOG([$_am_tar --version]) && break done am__tar="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$$tardir"' am__tar_="$_am_tar --format=m4_if([$1], [pax], [posix], [$1]) -chf - "'"$tardir"' am__untar="$_am_tar -xf -" ;; plaintar) # Must skip GNU tar: if it does not support --format= it doesn't create # ustar tarball either. (tar --version) >/dev/null 2>&1 && continue am__tar='tar chf - "$$tardir"' am__tar_='tar chf - "$tardir"' am__untar='tar xf -' ;; pax) am__tar='pax -L -x $1 -w "$$tardir"' am__tar_='pax -L -x $1 -w "$tardir"' am__untar='pax -r' ;; cpio) am__tar='find "$$tardir" -print | cpio -o -H $1 -L' am__tar_='find "$tardir" -print | cpio -o -H $1 -L' am__untar='cpio -i -H $1 -d' ;; none) am__tar=false am__tar_=false am__untar=false ;; esac # If the value was cached, stop now. We just wanted to have am__tar # and am__untar set. test -n "${am_cv_prog_tar_$1}" && break # tar/untar a dummy directory, and stop if the command works rm -rf conftest.dir mkdir conftest.dir echo GrepMe > conftest.dir/file AM_RUN_LOG([tardir=conftest.dir && eval $am__tar_ >conftest.tar]) rm -rf conftest.dir if test -s conftest.tar; then AM_RUN_LOG([$am__untar /dev/null 2>&1 && break fi done rm -rf conftest.dir AC_CACHE_VAL([am_cv_prog_tar_$1], [am_cv_prog_tar_$1=$_am_tool]) AC_MSG_RESULT([$am_cv_prog_tar_$1])]) AC_SUBST([am__tar]) AC_SUBST([am__untar]) ]) # _AM_PROG_TAR m4_include([m4/as-compiler-flag.m4]) m4_include([m4/as-version.m4]) crystalhd-0.0~git20110715.fdd2f19/filters/gst/gst-plugin/README0000644000175000017500000000010411610313111022736 0ustar andresandresPlease refer to the release notes for all comments and instructions.crystalhd-0.0~git20110715.fdd2f19/examples/0000755000175000017500000000000011610313111017343 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/examples/hellobcm.cpp0000644000175000017500000002220511610313111021635 0ustar andresandres#include #include #include #include #include #include "bc_dts_types.h" #include "libcrystalhd_if.h" #include #include #include #define TRY_CALL_1(func, p1, errmsg) \ if (BC_STS_SUCCESS != func(p1)) \ throw errmsg; #define TRY_CALL_2(func, p1, p2, errmsg) \ if (BC_STS_SUCCESS != func(p1, p2)) \ throw errmsg; #define TRY_CALL_5(func, p1, p2, p3, p4, p5, errmsg) \ if (BC_STS_SUCCESS != func(p1, p2, p3, p4, p5)) \ throw errmsg; #define TRY_CALL_6(func, p1, p2, p3, p4, p5, p6, errmsg) \ if (BC_STS_SUCCESS != func(p1, p2, p3, p4, p5, p6)) \ throw errmsg; #define OUTPUT_PROC_TIMEOUT 2000 int main() { BC_STATUS ret; HANDLE device = 0; std::fstream inFile; try { printf("starting up\n"); // Initialize the Link and Decoder devices uint32_t mode = DTS_PLAYBACK_MODE | DTS_LOAD_FILE_PLAY_FW | DTS_SKIP_TX_CHK_CPB | DTS_DFLT_RESOLUTION(vdecRESOLUTION_720p29_97); ret = DtsDeviceOpen(&device, mode); if (ret != BC_STS_SUCCESS) { printf("crap, DtsDeviceOpen failed\n"); throw "Failed to open device"; } ret = DtsOpenDecoder(device, BC_STREAM_TYPE_ES); if (ret != BC_STS_SUCCESS) { printf("crap, DtsOpenDecoder failed\n"); throw "Failed to open decoder"; } ret = DtsSetVideoParams(device, BC_VID_ALGO_H264, FALSE, FALSE, TRUE, 0x80000000 | vdecFrameRate23_97); if (ret != BC_STS_SUCCESS) { printf("crap, DtsSetVideoParams failed\n"); throw "Failed to set video params"; } ret = DtsSetColorSpace(device, MODE422_YUY2); if (ret != BC_STS_SUCCESS) { printf("crap, DtsSetColorSpace failed\n"); throw "Failed to set colorspace mode"; } ret = DtsStartDecoder(device); if (ret != BC_STS_SUCCESS) { printf("crap, DtsStartDecoder failed\n"); throw "Failed to start decoder"; } ret = DtsStartCapture(device); if (ret != BC_STS_SUCCESS) { printf("crap, DtsStartCapture failed\n"); throw "Failed to start capture"; } printf("try calls done\n"); // Open the input stream inFile.open("/tmp/test_video.264", std::ios::in | std::ios::binary); if (!inFile.is_open()) throw "Unable to open input file"; else printf("file opened successfully\n"); // Create a 4-byte aligned input buffer uint8_t oddBytes = 0; uint32_t inputLen = 32768; uint8_t* input = (uint8_t*)malloc(inputLen+4); printf("Input Buffer: %p\n", input); if(((uintptr_t)input)%4) oddBytes = 4 - ((uint8_t)((uintptr_t)input % 4)); uint8_t* input_aligned = input + oddBytes; printf("Aligned Input Buffer: %p, Offset = %d\n", input_aligned, oddBytes); // Create a 4-byte aligned output buffer uint32_t ysize = 4147200; // 1920 x 1080 uint32_t uvsize = 0; uint8_t* rawBuf = (uint8_t*)malloc(ysize + uvsize + 4); uint8_t* alignedBuf = rawBuf; if(((uintptr_t)rawBuf)%4) { oddBytes = 4 - ((uint8_t)((uintptr_t)rawBuf % 4)); alignedBuf = rawBuf + oddBytes; printf("Aligned Buffer: %p, Offset = %d\n", alignedBuf, oddBytes); } // If UV is in use, it's data immediately follows Y uint8_t* ybuf = alignedBuf; printf("Y Buffer: %p\n", ybuf); uint8_t* uvbuf = NULL; if (uvsize) { uvbuf = alignedBuf + ysize; printf("UV Buffer: %p\n", ybuf); } bool needData = true; uint32_t bytesRead = 0; bool formatChanged = false; // Open the output stream //std::fstream outFile; //outFile.open("/home/davilla/dozer/dump.yuv", std::ios::binary | std::ios::out); uint32_t chunksSent = 0; uint32_t bytesSent = 0; uint32_t picsDecoded = 0; uint32_t lastDecoded = 0xFF; for (;;) { for (int i = 0; i < 6; i++) { // Read from input file if previously-read data was sent successfully if (needData) { inFile.read((char*)input, inputLen); if (inFile.fail()) { printf("Read %d pictures\n", picsDecoded); throw "Unable to read input file"; } else if (inFile.eof()) throw "Reached end of input file"; bytesRead += inputLen; } // Push input data to driver ret = DtsProcInput(device, input, inputLen, 0, 0); if (ret == BC_STS_SUCCESS) { chunksSent++; bytesSent += inputLen; } else printf("DtsProcInput returned %d\n", ret); usleep(1000); needData = (ret == BC_STS_SUCCESS); // Only need more data if the send succeeded } // Prepare output structure BC_DTS_PROC_OUT output; memset(&output, 0, sizeof(BC_DTS_PROC_OUT)); output.PicInfo.width = 1920; output.PicInfo.height = 1080; output.Ybuff = ybuf; output.YbuffSz = ysize/4; output.UVbuff = uvbuf; output.UVbuffSz = uvsize/4; output.PoutFlags = BC_POUT_FLAGS_SIZE; // Request decoded data from the driver ret = DtsProcOutput(device, OUTPUT_PROC_TIMEOUT, &output); if (ret == BC_STS_SUCCESS) { if (!(output.PoutFlags & BC_POUT_FLAGS_PIB_VALID)) { printf("Invalid PIB received. Skipping picture. Flags: 0x%08x\n", output.PoutFlags); continue; } picsDecoded++; if (output.PicInfo.picture_number == lastDecoded) { /*BC_DTS_STATUS stat; if (BC_STS_SUCCESS == DtsGetDriverStatus(device, &stat)) { printf("Driver Status\n-------------------\n", stat.ReadyListCount); printf("ReadyListCount: %u\n", stat.ReadyListCount); printf("FreeListCount: %u\n", stat.FreeListCount); printf("FramesDropped: %u\n", stat.FramesDropped); printf("FramesCaptured: %u\n", stat.FramesCaptured); printf("FramesRepeated: %u\n", stat.FramesRepeated); printf("InputCount: %u (ChunksSent: %u)\n", stat.ReadyListCount, chunksSent); printf("InputTotalSize: %llu (BytesSent: %u)\n", stat.InputTotalSize, bytesSent); printf("InputBusyCount: %u\n", stat.InputBusyCount); printf("PIBMissCount: %u\n", stat.PIBMissCount); }*/ continue; } lastDecoded = output.PicInfo.picture_number; printf("Received Output. Bytes In: %d, Y: %d, UV: %d, Number: %d, H: %d, W: %d, Flags: 0x%08x\n", bytesSent, output.YBuffDoneSz, output.UVBuffDoneSz, output.PicInfo.picture_number, output.PicInfo.height, output.PicInfo.width, output.PoutFlags); /* std::fstream picFile; char picName[255]; sprintf(picName, "/home/davilla/dozer/frames/picture_%d.yuv", picsDecoded); picFile.open(picName, std::ios::binary | std::ios::out); picFile.write((const char*)output.Ybuff, ysize); output.PicInfo.picture_number -= 3; // Adjust for start-up pictures picFile.close(); //outFile.write((const char*)output.Ybuff, ysize); */ } else if (ret == BC_STS_FMT_CHANGE) { printf("Format Change Detected. Flags: 0x%08x\n", output.PoutFlags); if ((output.PoutFlags & BC_POUT_FLAGS_PIB_VALID) && (output.PoutFlags & BC_POUT_FLAGS_FMT_CHANGE)) { // Read format data from driver printf("New Format\n----------------------------------\n"); printf("\tTimeStamp: %llu\n", output.PicInfo.timeStamp); printf("\tPicture Number: %u\n", output.PicInfo.picture_number); printf("\tWidth: %u\n", output.PicInfo.width); printf("\tHeight: %u\n", output.PicInfo.height); printf("\tChroma: 0x%03x\n", output.PicInfo.chroma_format); printf("\tPulldown: %u\n", output.PicInfo.pulldown); printf("\tFlags: 0x%08x\n", output.PicInfo.flags); printf("\tFrame Rate/Res: %u\n", output.PicInfo.frame_rate); printf("\tAspect Ratio: %u\n", output.PicInfo.aspect_ratio); printf("\tColor Primaries: %u\n", output.PicInfo.colour_primaries); printf("\tMetaData: %u\n", output.PicInfo.picture_meta_payload); printf("\tSession Number: %u\n", output.PicInfo.sess_num); printf("\tTimeStamp: %u\n", output.PicInfo.ycom); printf("\tCustom Aspect: %u\n", output.PicInfo.custom_aspect_ratio_width_height); printf("\tFrames to Drop: %u\n", output.PicInfo.n_drop); printf("\tH264 Valid Fields: 0x%08x\n", output.PicInfo.other.h264.valid); } // TODO: Handle change } else if (ret == BC_STS_TIMEOUT) { printf("Timeout in DtsProcOutput. Accum Bytes: %d\n", bytesRead); } else if (ret == BC_STS_IO_XFR_ERROR) { printf("I/O Transfer Error.\n"); } else if (ret == BC_STS_IO_ERROR) { printf("I/O Error.\n"); } else if (ret == BC_STS_BUSY) { printf("Busy.\n"); } else { printf("DtsProcOutput return an unknown status: %d.\n", ret); return 0; } } } catch(const char* msg) { printf("%s\n", msg); } catch (...) { printf("An unknown exception was thrown\n"); } inFile.close(); DtsStopDecoder(device); DtsCloseDecoder(device); DtsDeviceClose(device); return 0; } crystalhd-0.0~git20110715.fdd2f19/examples/mpeg2test.cpp0000644000175000017500000002237111610313111021766 0ustar andresandres#include #include #include #include #include #include #include #include #include #include #include #define TRY_CALL_1(func, p1, errmsg) \ if (BC_STS_SUCCESS != func(p1)) \ throw errmsg; #define TRY_CALL_2(func, p1, p2, errmsg) \ if (BC_STS_SUCCESS != func(p1, p2)) \ throw errmsg; #define TRY_CALL_5(func, p1, p2, p3, p4, p5, errmsg) \ if (BC_STS_SUCCESS != func(p1, p2, p3, p4, p5)) \ throw errmsg; #define TRY_CALL_6(func, p1, p2, p3, p4, p5, p6, errmsg) \ if (BC_STS_SUCCESS != func(p1, p2, p3, p4, p5, p6)) \ throw errmsg; #define OUTPUT_PROC_TIMEOUT 2000 int main() { BC_STATUS ret; HANDLE device = 0; std::fstream inFile; try { printf("starting up\n"); // Initialize the Link and Decoder devices uint32_t mode = DTS_PLAYBACK_MODE | DTS_LOAD_FILE_PLAY_FW | DTS_SKIP_TX_CHK_CPB | DTS_DFLT_RESOLUTION(vdecRESOLUTION_1080i29_97); ret = DtsDeviceOpen(&device, mode); if (ret != BC_STS_SUCCESS) { printf("crap, DtsDeviceOpen failed\n"); throw "Failed to open device"; } ret = DtsOpenDecoder(device, BC_STREAM_TYPE_PES); if (ret != BC_STS_SUCCESS) { printf("crap, DtsOpenDecoder failed\n"); throw "Failed to open decoder"; } ret = DtsSetVideoParams(device, BC_VID_ALGO_MPEG2, FALSE, FALSE, TRUE, 0); if (ret != BC_STS_SUCCESS) { printf("crap, DtsSetVideoParams failed\n"); throw "Failed to set video params"; } ret = DtsSetColorSpace(device, MODE422_YUY2); if (ret != BC_STS_SUCCESS) { printf("crap, DtsSetColorSpace failed\n"); throw "Failed to set colorspace mode"; } ret = DtsStartDecoder(device); if (ret != BC_STS_SUCCESS) { printf("crap, DtsStartDecoder failed\n"); throw "Failed to start decoder"; } ret = DtsStartCapture(device); if (ret != BC_STS_SUCCESS) { printf("crap, DtsStartCapture failed\n"); throw "Failed to start capture"; } printf("try calls done\n"); // Open the input stream inFile.open("/tmp/test.mpeg2", std::ios::in | std::ios::binary); if (!inFile.is_open()) throw "Unable to open input file"; else printf("file opened successfully\n"); // Create a 4-byte aligned input buffer uint8_t oddBytes = 0; uint32_t inputLen = 32768; uint8_t* input = (uint8_t*)malloc(inputLen+4); printf("Input Buffer: %p\n", input); if(((uintptr_t)input)%4) oddBytes = 4 - ((uint8_t)((uintptr_t)input % 4)); uint8_t* input_aligned = input + oddBytes; printf("Aligned Input Buffer: %p, Offset = %d\n", input_aligned, oddBytes); // Create a 4-byte aligned output buffer uint32_t ysize = 4147200; // 1920 x 1080 uint32_t uvsize = 0; uint8_t* rawBuf = (uint8_t*)malloc(ysize + uvsize + 4); uint8_t* alignedBuf = rawBuf; if(((uintptr_t)rawBuf)%4) { oddBytes = 4 - ((uint8_t)((uintptr_t)rawBuf % 4)); alignedBuf = rawBuf + oddBytes; printf("Aligned Buffer: %p, Offset = %d\n", alignedBuf, oddBytes); } // If UV is in use, it's data immediately follows Y uint8_t* ybuf = alignedBuf; printf("Y Buffer: %p\n", ybuf); uint8_t* uvbuf = NULL; if (uvsize) { uvbuf = alignedBuf + ysize; printf("UV Buffer: %p\n", ybuf); } bool needData = true; uint32_t bytesRead = 0; bool formatChanged = false; // Open the output stream //std::fstream outFile; //outFile.open("/home/davilla/dozer/dump.yuv", std::ios::binary | std::ios::out); uint32_t chunksSent = 0; uint32_t bytesSent = 0; uint32_t picsDecoded = 0; uint32_t lastDecoded = 0xFF; for (;;) { for (int i = 0; i < 2; i++) { // Read from input file if previously-read data was sent successfully if (needData) { inFile.read((char*)input, inputLen); if (inFile.fail()) { printf("Read %d pictures\n", picsDecoded); throw "Unable to read input file"; } else if (inFile.eof()) throw "Reached end of input file"; bytesRead += inputLen; } // Push input data to driver ret = DtsProcInput(device, input, inputLen, 0, 0); if (ret == BC_STS_SUCCESS) { chunksSent++; bytesSent += inputLen; } else printf("DtsProcInput returned %d\n", ret); usleep(1000); needData = (ret == BC_STS_SUCCESS); // Only need more data if the send succeeded } // Prepare output structure BC_DTS_PROC_OUT output; memset(&output, 0, sizeof(BC_DTS_PROC_OUT)); output.PicInfo.width = 1920; output.PicInfo.height = 1080; output.Ybuff = ybuf; output.YbuffSz = ysize/4; output.UVbuff = uvbuf; output.UVbuffSz = uvsize/4; output.PoutFlags = BC_POUT_FLAGS_SIZE; // Request decoded data from the driver ret = DtsProcOutput(device, OUTPUT_PROC_TIMEOUT, &output); if (ret == BC_STS_SUCCESS) { if (!(output.PoutFlags & BC_POUT_FLAGS_PIB_VALID)) { printf("Invalid PIB received. Skipping picture. Flags: 0x%08x\n", output.PoutFlags); continue; } picsDecoded++; if (output.PicInfo.picture_number == lastDecoded) { /*BC_DTS_STATUS stat; if (BC_STS_SUCCESS == DtsGetDriverStatus(device, &stat)) { printf("Driver Status\n-------------------\n", stat.ReadyListCount); printf("ReadyListCount: %u\n", stat.ReadyListCount); printf("FreeListCount: %u\n", stat.FreeListCount); printf("FramesDropped: %u\n", stat.FramesDropped); printf("FramesCaptured: %u\n", stat.FramesCaptured); printf("FramesRepeated: %u\n", stat.FramesRepeated); printf("InputCount: %u (ChunksSent: %u)\n", stat.ReadyListCount, chunksSent); printf("InputTotalSize: %llu (BytesSent: %u)\n", stat.InputTotalSize, bytesSent); printf("InputBusyCount: %u\n", stat.InputBusyCount); printf("PIBMissCount: %u\n", stat.PIBMissCount); }*/ continue; } lastDecoded = output.PicInfo.picture_number; printf("Received Output. Bytes In: %d, Y: %d, UV: %d, Number: %d, H: %d, W: %d, Flags: 0x%08x\n", bytesSent, output.YBuffDoneSz, output.UVBuffDoneSz, output.PicInfo.picture_number, output.PicInfo.height, output.PicInfo.width, output.PoutFlags); /* std::fstream picFile; char picName[255]; sprintf(picName, "/home/davilla/dozer/frames/picture_%d.yuv", picsDecoded); picFile.open(picName, std::ios::binary | std::ios::out); picFile.write((const char*)output.Ybuff, ysize); output.PicInfo.picture_number -= 3; // Adjust for start-up pictures picFile.close(); //outFile.write((const char*)output.Ybuff, ysize); */ } else if (ret == BC_STS_FMT_CHANGE) { printf("Format Change Detected. Flags: 0x%08x\n", output.PoutFlags); if ((output.PoutFlags & BC_POUT_FLAGS_PIB_VALID) && (output.PoutFlags & BC_POUT_FLAGS_FMT_CHANGE)) { // Read format data from driver printf("New Format\n----------------------------------\n"); printf("\tTimeStamp: %llu\n", output.PicInfo.timeStamp); printf("\tPicture Number: %u\n", output.PicInfo.picture_number); printf("\tWidth: %u\n", output.PicInfo.width); printf("\tHeight: %u\n", output.PicInfo.height); printf("\tChroma: 0x%03x\n", output.PicInfo.chroma_format); printf("\tPulldown: %u\n", output.PicInfo.pulldown); printf("\tFlags: 0x%08x\n", output.PicInfo.flags); printf("\tFrame Rate/Res: %u\n", output.PicInfo.frame_rate); printf("\tAspect Ratio: %u\n", output.PicInfo.aspect_ratio); printf("\tColor Primaries: %u\n", output.PicInfo.colour_primaries); printf("\tMetaData: %u\n", output.PicInfo.picture_meta_payload); printf("\tSession Number: %u\n", output.PicInfo.sess_num); printf("\tTimeStamp: %u\n", output.PicInfo.ycom); printf("\tCustom Aspect: %u\n", output.PicInfo.custom_aspect_ratio_width_height); printf("\tFrames to Drop: %u\n", output.PicInfo.n_drop); printf("\tH264 Valid Fields: 0x%08x\n", output.PicInfo.other.h264.valid); } // TODO: Handle change } else if (ret == BC_STS_TIMEOUT) { printf("Timeout in DtsProcOutput. Accum Bytes: %d\n", bytesRead); } else if (ret == BC_STS_IO_XFR_ERROR) { printf("I/O Transfer Error.\n"); } else if (ret == BC_STS_IO_ERROR) { printf("I/O Error.\n"); } else if (ret == BC_STS_BUSY) { printf("Busy.\n"); } else { printf("DtsProcOutput return an unknown status: %d.\n", ret); return 0; } } } catch(const char* msg) { printf("%s\n", msg); } catch (...) { printf("An unknown exception was thrown\n"); } inFile.close(); DtsStopDecoder(device); DtsCloseDecoder(device); DtsDeviceClose(device); return 0; } crystalhd-0.0~git20110715.fdd2f19/examples/Makefile0000644000175000017500000000036711610313111021011 0ustar andresandresCPP := g++ CPPFLAGS += -D__LINUX_USER__ LDFLAGS += -lcrystalhd -lpthread INCLUDES += -I../include/ -I../linux_lib/libcrystalhd/ % : %.cpp $(CPP) $(INCLUDES) $(CPPFLAGS) $(LDFLAGS) -o $@ $< all: hellobcm mpeg2test clean: rm hellobcm mpeg2test crystalhd-0.0~git20110715.fdd2f19/linux_lib/0000755000175000017500000000000011610313111017512 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/0000755000175000017500000000000011610313111022176 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/libcrystalhd_fwload_if.h0000644000175000017500000000337411610313111027054 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_fwload_if.h * * Description: Driver Interface library Internal. * * AU * * HISTORY: * ******************************************************************** * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #ifndef _libcrystalhd_FWLOAD_IF_ #define _libcrystalhd_FWLOAD_IF_ #ifndef __APPLE__ #include "bc_dts_glob_lnx.h" #else #include "bc_dts_glob_osx.h" #endif #include "libcrystalhd_if.h" #define BC_FWIMG_ST_ADDR 0x00000000 #define MAX_BIN_FILE_SZ 0x300000 /* BOOTLOADER IMPLEMENTATION */ DRVIFLIB_INT_API BC_STATUS fwbinPushToLINK(HANDLE hDevice, char *FwBinFile, uint32_t *bytesDnld); DRVIFLIB_INT_API BC_STATUS DtsPushAuthFwToLink(HANDLE hDevice, char *FwBinFile); DRVIFLIB_INT_API BC_STATUS fwbinPushToFLEA(HANDLE hDevice, char *FwBinFile, uint32_t *bytesDnld); DRVIFLIB_INT_API BC_STATUS DtsPushFwToFlea(HANDLE hDevice, char *FwBinFile); DRVIFLIB_INT_API BC_STATUS dec_write_fw_Sig(HANDLE hndl,uint32_t* Sig); #endif crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/libcrystalhd_fwcmds.h0000644000175000017500000000702611610313111026403 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_fwdcmds.h * * Description: Driver Interface library Internal. * * AU * * HISTORY: * ******************************************************************** * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #ifndef _BCM_FWCMDS_H_ #define _BCM_FWCMDS_H_ #include "libcrystalhd_priv.h" DRVIFLIB_INT_API BC_STATUS DtsFWInitialize( HANDLE hDevice, uint32_t resrv1 ); DRVIFLIB_INT_API BC_STATUS DtsFWOpenChannel( HANDLE hDevice, uint32_t StreamType, uint32_t reserved ); DRVIFLIB_INT_API BC_STATUS DtsFWActivateDecoder( HANDLE hDevice ); DRVIFLIB_INT_API BC_STATUS DtsFWSetSingleField( HANDLE hDevice, bool bSingleField ); DRVIFLIB_INT_API BC_STATUS DtsFWHwSelfTest( HANDLE hDevice, uint32_t testID ); DRVIFLIB_INT_API BC_STATUS DtsFWVersion( HANDLE hDevice, uint32_t *Stream, uint32_t *DecCore, uint32_t *HwNumber ); DRVIFLIB_INT_API BC_STATUS DtsFWFifoStatus( HANDLE hDevice, uint32_t *CpbSize, uint32_t *CpbFullness ); DRVIFLIB_INT_API BC_STATUS DtsFWCloseChannel( HANDLE hDevice, uint32_t ChannelID ); DRVIFLIB_INT_API BC_STATUS DtsFWSetVideoInput( HANDLE hDevice ); DRVIFLIB_INT_API BC_STATUS DtsFWSetVideoPID( HANDLE hDevice, uint32_t pid ); DRVIFLIB_INT_API BC_STATUS DtsFWFlushDecoder( HANDLE hDevice, uint32_t rsrv ); DRVIFLIB_INT_API BC_STATUS DtsFWStartVideo( HANDLE hDevice, uint32_t videoAlg, uint32_t FGTEnable, uint32_t MetaDataEnable, uint32_t Progressive, uint32_t OptFlags ); DRVIFLIB_INT_API BC_STATUS DtsFWStopVideo( HANDLE hDevice, uint32_t ChannelId, bool ForceStop ); DRVIFLIB_INT_API BC_STATUS DtsFWDecFlushChannel( HANDLE hDevice, uint32_t Operation ); DRVIFLIB_INT_API BC_STATUS DtsFWPauseVideo( HANDLE hDevice, uint32_t Operation ); DRVIFLIB_INT_API BC_STATUS DtsFWSetTrickPlay( HANDLE hDevice, uint32_t trickMode, uint8_t direction ); DRVIFLIB_INT_API BC_STATUS DtsFWSetHostTrickMode( HANDLE hDevice, uint32_t enable ); DRVIFLIB_INT_API BC_STATUS DtsFWSetFFRate( HANDLE hDevice, uint32_t Rate ); DRVIFLIB_INT_API BC_STATUS DtsFWSetSlowMotionRate( HANDLE hDevice, uint32_t Rate ); DRVIFLIB_INT_API BC_STATUS DtsFWSetSkipPictureMode( HANDLE hDevice, uint32_t SkipMode ); DRVIFLIB_INT_API BC_STATUS DtsFWFrameAdvance( HANDLE hDevice ); DRVIFLIB_INT_API BC_STATUS DtsFWSetContentKeys( HANDLE hDevice, uint8_t *buffer, uint32_t dwLength, uint32_t flags ); DRVIFLIB_INT_API BC_STATUS DtsFWSetSessionKeys( HANDLE hDevice, uint8_t *buffer, uint32_t Length, uint32_t flags ); BC_STATUS DtsFormatChangeAck( HANDLE hDevice, uint32_t flags ); DRVIFLIB_INT_API BC_STATUS DtsFWDrop( HANDLE hDevice, uint32_t Pictures ); #endif //_BCM_FWCMDS_H crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/libcrystalhd_fwdiag_if.cpp0000644000175000017500000001701211610313111027366 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_fwdiag_if.cpp * * Description: Firmware diagnostics * * AU * * HISTORY: * ******************************************************************** * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #include "7411d.h" #include "bc_defines.h" #include "libcrystalhd_int_if.h" #include "libcrystalhd_if.h" #include "libcrystalhd_priv.h" #include "libcrystalhd_fwdiag_if.h" #include "libcrystalhd_fwload_if.h" /* BOOTLOADER IMPLEMENTATION */ /* Functions */ DRVIFLIB_INT_API BC_STATUS DtsSendFWDiagCmd(HANDLE hDevice,BC_HOST_CMD_BLOCK_ST hostMsg) { BC_STATUS status=BC_STS_ERROR; /* Checksum of Message Block */ hostMsg.chk_sum = ~(hostMsg.done+hostMsg.cmd+hostMsg.start+hostMsg.size+ hostMsg.cmdargs[0]+hostMsg.cmdargs[1]+hostMsg.cmdargs[2]); /* Loading of Message Block */ hostMsg.done &= (~BC_HOST_CMD_POSTED); status = DtsDevMemWr(hDevice,(uint32_t *)&hostMsg,sizeof(hostMsg),BC_HOST_CMD_ADDR); if(BC_STS_ERROR == status) { DebugLog_Trace(LDIL_DBG,"Writing register failed status:%x\n",status); return status; } /* Issue done */ hostMsg.done = BC_HOST_CMD_POSTED; status = DtsDevMemWr(hDevice,&(hostMsg.done),4,BC_HOST_CMD_ADDR); if(BC_STS_ERROR == status) { DebugLog_Trace(LDIL_DBG,"Writing register failed status:%x\n",status); return status; } return status; } DRVIFLIB_INT_API BC_STATUS DtsClearFWDiagCommBlock(HANDLE hDevice) { BC_STATUS status=BC_STS_ERROR; BC_HOST_CMD_BLOCK_ST hostMsg; BC_FWDIAG_RES_BLOCK_ST blMsg; memset(&hostMsg, 0, sizeof(BC_HOST_CMD_BLOCK_ST)); memset(&blMsg, 0, sizeof(BC_FWDIAG_RES_BLOCK_ST)); status = DtsDevMemWr(hDevice,(uint32_t *)&hostMsg,sizeof(BC_HOST_CMD_BLOCK_ST),BC_HOST_CMD_ADDR); if(BC_STS_ERROR == status) { DebugLog_Trace(LDIL_DBG,"Clearing Host Message Block failed, status:%x\n",status); return status; } status = DtsDevMemWr(hDevice,(uint32_t *)&blMsg,sizeof(BC_FWDIAG_RES_BLOCK_ST),BC_FWDIAG_RES_ADDR); if(BC_STS_ERROR == status) { DebugLog_Trace(LDIL_DBG,"Clearing Host Message Block failed, status:%x\n",status); return status; } return status; } DRVIFLIB_INT_API BC_STATUS DtsReceiveFWDiagRes(HANDLE hDevice, PBC_FWDIAG_RES_BLOCK_ST pBlMsg,uint32_t wait) { BC_STATUS status = BC_STS_ERROR; uint32_t chkSum = 0; uint32_t cnt=1000; while(--cnt) { status = DtsDevMemRd(hDevice,(uint32_t *)(pBlMsg),sizeof(BC_FWDIAG_RES_BLOCK_ST),BC_FWDIAG_RES_ADDR); if(BC_STS_SUCCESS != status){ DebugLog_Trace(LDIL_DBG,"Command Failure From DIL status:%x\n",status); return (status); } if(pBlMsg->done&BC_FWDIAG_RES_POSTED) { chkSum = ~(pBlMsg->done+pBlMsg->status+pBlMsg->detail[0]+\ pBlMsg->detail[1]+pBlMsg->detail[2]+pBlMsg->detail[3]+pBlMsg->detail[4]); if(chkSum != pBlMsg->chk_sum) { DebugLog_Trace(LDIL_DBG,"Recv. Message Checksum failed\n"); return BC_STS_ERROR; } /* Success */ break; } /* Wait */ bc_sleep_ms(wait); } /* Clear the Message */ DtsClearFWDiagCommBlock(hDevice); if(!cnt){ DebugLog_Trace(LDIL_DBG,"Message Receive Timed-out\n"); return BC_STS_TIMEOUT; } return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsDownloadFWDIAGToLINK(HANDLE hDevice,char *FwBinFile) { BC_STATUS status = BC_STS_ERROR; uint32_t byesDnld=0; //char *fwfile=NULL; char fwfile[MAX_PATH+1]; DTS_LIB_CONTEXT *Ctx = NULL; uint32_t RegVal =0; BC_FWDIAG_RES_BLOCK_ST blMsg; DebugLog_Trace(LDIL_DBG,"0. fwfile is %s\n",FwBinFile); /* Clear Host Message Area */ status = DtsClearFWDiagCommBlock(hDevice); if(status != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsDownloadFWDIAGToLINK: Failed to clear the message area\n"); return status; } DTS_GET_CTX(hDevice,Ctx); /* Get the firmware file to download */ status = DtsGetDILPath(hDevice, fwfile, sizeof(fwfile)); if(status != BC_STS_SUCCESS){ return status; } if(FwBinFile!=NULL){ strncat(fwfile,(const char*)FwBinFile,sizeof(fwfile)); DebugLog_Trace(LDIL_DBG,"1. fwfile is %s\n",FwBinFile); }else{ strncat(fwfile,"/",sizeof(fwfile)); strncat(fwfile,"bcmFWDiag.bin",sizeof(fwfile)); DebugLog_Trace(LDIL_DBG,"2. fwfile is %s\n",fwfile); } //Read OTP_CMD registers to see if Keys are already programmed in OTP RegVal =0; status = DtsFPGARegisterRead(hDevice, OTP_CMD, &RegVal); if(status != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"Error Reading DCI_STATUS register\n"); return status; } status = fwbinPushToLINK(hDevice, fwfile, &byesDnld); if(status != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsDownloadAuthFwToLINK: Failed to download firmware\n"); return status; } /* Check for firmware authentication result */ //look for SIGNATURE_MATCHED or SIGNATURE_MISMATCH in DCI status Register. RegVal =0; status = DtsFPGARegisterRead(hDevice, DCI_STATUS, &RegVal); if(status != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"Error Reading DCI_STATUS register\n"); return status; } if ((RegVal & DCI_SIGNATURE_MATCHED) == DCI_SIGNATURE_MATCHED) { //if SIGNATURE_MATCHED Wait for FW_VALIDATED bit to be set. DebugLog_Trace(LDIL_DBG,"Signature Matched\n"); uint32_t cnt = 1000; while((RegVal & DCI_FIRMWARE_VALIDATED) != DCI_FIRMWARE_VALIDATED) { status = DtsFPGARegisterRead(hDevice, DCI_STATUS, &RegVal); if(status != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"Error Reading DCI_STATUS register\n"); return status; } RegVal &= DCI_FIRMWARE_VALIDATED; if(!(--cnt)) break; bc_sleep_ms(1); } //uart status = DtsDevRegisterWr(hDevice, 0x00100300, 0x03); if(status != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"Error Writing UART register\n"); } else DebugLog_Trace(LDIL_DBG,"Uart Set Sucessfully\n"); //START_PROCESSOR bit in DCI_CMD. RegVal = 0; status = DtsFPGARegisterRead(hDevice, DCI_CMD, &RegVal); if(status != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"Error Reading DCI_CMD register\n"); return status; } RegVal |= DCI_START_PROCESSOR; //DebugLog_Trace(LDIL_DBG,"DCICMD RegVal:%x\n",RegVal); status = DtsFPGARegisterWr(hDevice, DCI_CMD, RegVal); if(status != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"Error Writing DCI_CMD register\n"); return status; } } else if ((RegVal & DCI_SIGNATURE_MISMATCH)==DCI_SIGNATURE_MISMATCH) { DebugLog_Trace(LDIL_DBG,"FW AUthentication failed. Signature Mismatch\n"); return BC_STS_FW_AUTH_FAILED; } /* Check bootloader Status */ status = DtsReceiveFWDiagRes(hDevice, &blMsg, 10); if(status != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsDownloadFWDIAGToLINK: Receive message for FWDiag booting failed, status=%d\n", status); return BC_STS_BOOTLOADER_FAILED; //status; } if(blMsg.status != BC_FWDIAG_BOOTUP_DONE) { DebugLog_Trace(LDIL_DBG,"DtsDownloadFWDIAGToLINK: Failed to boot the FWDiag\n"); return BC_STS_BOOTLOADER_FAILED; //BC_STS_ERROR; } return BC_STS_SUCCESS; } crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/libcrystalhd_parser.cpp0000644000175000017500000010761211610313111026751 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_parser.h * * Description: Driver Interface library Internal. * * AU * * HISTORY: * ******************************************************************** * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #include #include "7411d.h" #include "libcrystalhd_if.h" #include "libcrystalhd_priv.h" #include "libcrystalhd_parser.h" //Check Number of Reference //NAL Unit //#include "NALUnit.h" //Advanced Profile static const uint8_t b_asf_vc1_frame_scode[4]={0x00, 0x00, 0x01, 0x0D}; //Simple / Main Profile //SP/MP Code-In Magic Word static const uint8_t b_asf_vc1_sm_codein_scode[4] = {0x5a, 0x5a, 0x5a, 0x5a}; static const uint8_t b_asf_vc1_sm_codein_data_suffix[1] = {0x0D}; static const uint8_t b_asf_vc1_sm_codein_sl_suffix[1] = {0x0F}; static const uint8_t b_asf_vc1_sm_codein_pts_suffix[1] = {0xBD}; static const uint8_t b_asf_vc1_sm_seqheader_scode[4] = {0x00, 0x00, 0x01, 0x0F}; static const uint8_t b_asf_vc1_sm_picheader_scode[4] = {0x00, 0x00, 0x01, 0x0D}; static const uint8_t b_asf_vc1_sm_codein_header[16] = {0x5a, 0x5a, 0x5a, 0x5a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x5a, 0x5a, 0x5a, 0x5a}; static const uint8_t b_asf_vc1_sm_codein_seqhdr[32] = {0x5a, 0x5a, 0x5a, 0x5a, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x07, 0x5a, 0x5a, 0x5a, 0x5a, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; static const uint8_t b_asf_vc1_sm_seqhdr[12] = {0x00, 0x00, 0x01, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; //Swap Data uint32_t DWORD_SWAP(uint32_t x) { return ((uint32_t)(((x) << 24) | ((x) >> 24) | (((x) & 0xFF00) << 8) | (((x) & 0xFF0000) >> 8))); } uint16_t WORD_SWAP(uint16_t x) { return ((uint16_t)(((x) << 8) | ((x) >> 8))); } uint64_t ULONGLONG_SWAP(uint64_t x) { return ((uint64_t)(((x) << 56) | ((x) >> 56) | (((x) & 0xFF00LL) << 40) | (((x) & 0xFF000000000000LL) >> 40) | (((x) & 0xFF0000LL) << 24) | (((x) & 0xFF0000000000LL) >> 24) | (((x) & 0xFF000000LL) << 8) | (((x) & 0xFF00000000LL) >> 8))); } void PTS2MakerBit5Bytes(uint8_t* pMakerBit, int64_t llPTS) { //4 Bits: '0010' //3 Bits: PTS[32:30] //1 Bit: '1' //15 Bits: PTS[29:15] //1 Bit: '1' //15 Bits: PTS[14:0] //1 Bit : '1' //0010 xxx1 xxxx xxxx xxxx xxx1 xxxx xxxx xxxx xxx1 //Swap uint64_t ullSwap = ULONGLONG_SWAP(llPTS); uint8_t *pPTS = (uint8_t *)(&ullSwap); //Reserved the last 5 bytes, using the last 33 bits of PTS //0000 000x xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx pPTS = pPTS + 3; //1st Byte: 0010 xxx1 *(pMakerBit) = 0x21 | ((*(pPTS) & 0x01) << 3) | ((*(pPTS + 1) & 0xC0) >> 5); //2nd Byte: xxxx xxxx *(pMakerBit + 1) = ((*(pPTS + 1) & 0x3F) << 2) | ((*(pPTS + 2) & 0xC0) >> 6); //3rd Byte: xxxx xxx1 *(pMakerBit + 2) = 0x01 | ((*(pPTS + 2) & 0x3F) << 2) | ((*(pPTS + 3) & 0x80) >> 6); //4th Byte: xxxx xxxx *(pMakerBit + 3) = ((*(pPTS + 3) & 0x7F) << 1) | ((*(pPTS + 4) & 0x80) >> 7); //5th Byte: xxxx xxx1 *(pMakerBit + 4) = 0x01 | ((*(pPTS + 4) & 0x7F) << 1); } /* void PESHeaderPTSInsert(uint8_t *pPESHdr, uint64_t llPTS) { //Swap uint64_t ullSwap = ULONGLONG_SWAP(llPTS); uint8_t *pPTS = (uint8_t *)(&ullSwap); //PES Header Bit[8~12] PTS 5Bytes Field //0010 xxx1 xxxx xxxx //xxxx xxx1 xxxx xxxx //xxxx xxx1 } */ BC_STATUS DtsReleasePESConverter(HANDLE hDevice) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if (Ctx->PESConvParams.m_pSpsPpsBuf) free(Ctx->PESConvParams.m_pSpsPpsBuf); Ctx->PESConvParams.m_pSpsPpsBuf = NULL; if (Ctx->PESConvParams.pStartcodePendBuff) free(Ctx->PESConvParams.pStartcodePendBuff); Ctx->PESConvParams.pStartcodePendBuff = NULL; return BC_STS_SUCCESS; } BC_STATUS DtsInitPESConverter(HANDLE hDevice) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); Ctx->PESConvParams.m_bIsFirstByteStreamNALU = true; Ctx->PESConvParams.m_pSpsPpsBuf = NULL; Ctx->PESConvParams.m_iSpsPpsLen = 0; Ctx->PESConvParams.m_lStartCodeDataSize = 0; Ctx->PESConvParams.pStartcodePendBuff = NULL; Ctx->PESConvParams.lPendBufferSize = 0; Ctx->PESConvParams.m_SymbInt.m_nSize = 0; Ctx->PESConvParams.m_SymbInt.m_nUsed = 0; Ctx->PESConvParams.m_SymbInt.m_pCurrent = NULL; Ctx->PESConvParams.m_SymbInt.m_pInputBuffer = NULL; Ctx->PESConvParams.m_SymbInt.m_pInputBufferEnd = NULL; Ctx->PESConvParams.m_SymbInt.m_ulMask = 0; Ctx->PESConvParams.m_SymbInt.m_ulOffset = 0; Ctx->PESConvParams.m_SymbInt.m_ulZero = 0; Ctx->PESConvParams.m_bAddSpsPps = true; Ctx->PESConvParams.m_bIsAdd_SCode_CodeIn = false; Ctx->PESConvParams.m_bRangered = false; Ctx->PESConvParams.m_bFinterpFlag = false; Ctx->PESConvParams.m_bMaxbFrames = false; return BC_STS_SUCCESS; } BC_STATUS DtsSetVC1SH(HANDLE hDevice) { DTS_LIB_CONTEXT *Ctx = NULL; int sts = 0; DTS_GET_CTX(hDevice,Ctx); //Send SPS and PPS //unused uint8_t *pSrc = NULL; //unused uint8_t *pDes = NULL; if((Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WVC1) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMVA)) { Ctx->PESConvParams.m_iSpsPpsLen = Ctx->VidParams.MetaDataSz; sts = posix_memalign((void**)&Ctx->PESConvParams.m_pSpsPpsBuf, 8, Ctx->PESConvParams.m_iSpsPpsLen); if(sts) return BC_STS_INSUFF_RES; memcpy(Ctx->PESConvParams.m_pSpsPpsBuf, Ctx->VidParams.pMetaData, Ctx->PESConvParams.m_iSpsPpsLen); } else { if (Ctx->DevId == BC_PCI_DEVID_LINK) { if (Ctx->PESConvParams.m_pSpsPpsBuf) free(Ctx->PESConvParams.m_pSpsPpsBuf); Ctx->PESConvParams.m_iSpsPpsLen = 32; sts = posix_memalign((void**)&Ctx->PESConvParams.m_pSpsPpsBuf, 8, Ctx->PESConvParams.m_iSpsPpsLen); if(sts) return BC_STS_INSUFF_RES; memcpy(Ctx->PESConvParams.m_pSpsPpsBuf, b_asf_vc1_sm_codein_seqhdr, Ctx->PESConvParams.m_iSpsPpsLen); *((uint16_t*)(Ctx->PESConvParams.m_pSpsPpsBuf + 17)) = WORD_SWAP((uint16_t)Ctx->VidParams.WidthInPixels); *((uint16_t*)(Ctx->PESConvParams.m_pSpsPpsBuf + 19)) = WORD_SWAP((uint16_t)Ctx->VidParams.HeightInPixels); memcpy(Ctx->PESConvParams.m_pSpsPpsBuf + 21, Ctx->VidParams.pMetaData, 4); } else if (Ctx->DevId == BC_PCI_DEVID_FLEA) { if (Ctx->PESConvParams.m_pSpsPpsBuf) free(Ctx->PESConvParams.m_pSpsPpsBuf); Ctx->PESConvParams.m_iSpsPpsLen = 12; sts = posix_memalign((void**)&Ctx->PESConvParams.m_pSpsPpsBuf, 8, Ctx->PESConvParams.m_iSpsPpsLen); if(sts) return BC_STS_INSUFF_RES; memcpy(Ctx->PESConvParams.m_pSpsPpsBuf, b_asf_vc1_sm_seqhdr, Ctx->PESConvParams.m_iSpsPpsLen); *((uint16_t*)(Ctx->PESConvParams.m_pSpsPpsBuf + 4)) = WORD_SWAP((uint16_t)Ctx->VidParams.WidthInPixels); *((uint16_t*)(Ctx->PESConvParams.m_pSpsPpsBuf + 6)) = WORD_SWAP((uint16_t)Ctx->VidParams.HeightInPixels); memcpy(Ctx->PESConvParams.m_pSpsPpsBuf + 8, Ctx->VidParams.pMetaData, 4); } } return BC_STS_SUCCESS; } BC_STATUS DtsSetSpsPps(HANDLE hDevice) { DTS_LIB_CONTEXT *Ctx = NULL; //Send SPS and PPS uint8_t *pSrc = NULL; uint8_t *pDes = NULL; uint8_t NALtype = 0; int iSHStart[40]; int iSHStop[40]; int iPktIdx = 0; int i = 0; int j = 0; unsigned int iSize = 0; int iStartSize = 2; DTS_GET_CTX(hDevice,Ctx); // if ((Ctx->VidParams.MediaSubType != BC_MSUBTYPE_AVC1) && // (Ctx->VidParams.MediaSubType != BC_MSUBTYPE_H264) && // (Ctx->VidParams.MediaSubType != BC_MSUBTYPE_DIVX) ) // return BC_STS_SUCCESS; // MSUBTYPE_H264 does not have codec_type to generate separate SPS/PPS if ((Ctx->VidParams.MediaSubType != BC_MSUBTYPE_AVC1) && (Ctx->VidParams.MediaSubType != BC_MSUBTYPE_DIVX) ) return BC_STS_SUCCESS; int iSHSize = Ctx->VidParams.MetaDataSz; pSrc = Ctx->VidParams.pMetaData; if((iSHSize > 0) && (pSrc)) { if (pSrc[0]==0x00 && pSrc[1]==0x00 && pSrc[2]==0x01) { iStartSize = 3; iSHStart[iPktIdx] = 3; for (i = 3; i < iSHSize; i ++) { if (pSrc[i-2]==0x00 && pSrc[i-1]==0x00 && pSrc[i]==0x01) { iSHStop[iPktIdx] = i - 3; if (i < iSHSize) { iPktIdx++; iSHStart[iPktIdx] = i + 1; } } } iSHStop[iPktIdx++] = i-1; } else if (pSrc[0]==0x00 && pSrc[1]==0x00 && pSrc[2]==0x00 && pSrc[3]==0x01) { iStartSize = 4; iSHStart[iPktIdx] = 4; for (i = 4; i < iSHSize; i ++) { if (pSrc[i-3] == 0x00 && pSrc[i-2]==0x00 && pSrc[i-1]==0x00 && pSrc[i]==0x01) { iSHStop[iPktIdx] = i - 4; if (i < iSHSize) { iPktIdx++; iSHStart[iPktIdx] = i + 1; } } } iSHStop[iPktIdx++] = i-1; } else { while (i < iSHSize) { iSize = (pSrc[i] << 8) + pSrc[i+1]; iSHStart[iPktIdx] = i + 2; iSHStop[iPktIdx] = iSHStart[iPktIdx] + iSize - 1; iPktIdx++; i += (2 + iSize); } } Ctx->PESConvParams.m_iSpsPpsLen = iSHSize + (BRCM_START_CODE_SIZE - iStartSize) * (iPktIdx); if(Ctx->PESConvParams.m_pSpsPpsBuf) free(Ctx->PESConvParams.m_pSpsPpsBuf); if(!posix_memalign((void**)&Ctx->PESConvParams.m_pSpsPpsBuf, 8, Ctx->PESConvParams.m_iSpsPpsLen)) { memset(Ctx->PESConvParams.m_pSpsPpsBuf, 0, Ctx->PESConvParams.m_iSpsPpsLen); pDes = Ctx->PESConvParams.m_pSpsPpsBuf; pSrc = Ctx->VidParams.pMetaData; for(i=0;iVidParams.pMetaData[iSHStart[i]] & 0x1F; if((((NALtype == 0x7) || (NALtype == 0x8)) && (Ctx->VidParams.MediaSubType != BC_MSUBTYPE_DIVX)) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_DIVX)) { //Start Code //Add to Pending Buffer for(j=0; j (Ctx->PESConvParams.m_iSpsPpsLen - (pDes - Ctx->PESConvParams.m_pSpsPpsBuf))) return BC_STS_ERROR; memcpy(pDes, pSrc, iSize); //Update pDes += iSize; } pSrc += iSize; } } else return BC_STS_INSUFF_RES; } return BC_STS_SUCCESS; } BC_STATUS DtsSetPESConverter( HANDLE hDevice) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); DtsInitPESConverter(hDevice); uint8_t* pSeqHeader = Ctx->VidParams.pMetaData; //SoftRave (VC-1 S/M and Divx) if ((Ctx->DevId == BC_PCI_DEVID_FLEA) && ((Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMV3) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_DIVX) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_DIVX311) )) { Ctx->PESConvParams.m_bSoftRave = true; } else { Ctx->PESConvParams.m_bSoftRave = false; } if ((Ctx->VidParams.MediaSubType == BC_MSUBTYPE_AVC1) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_H264) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_DIVX)) { DtsSetSpsPps(hDevice); if (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_AVC1) Ctx->PESConvParams.m_bIsAdd_SCode_CodeIn = true; } if((Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WVC1) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMV3) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMVA)) { Ctx->PESConvParams.m_bIsAdd_SCode_CodeIn = true; if (pSeqHeader) { if (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMV3) { DWORD dwSH = DWORD_SWAP(*(DWORD *)pSeqHeader); Ctx->PESConvParams.m_bRangered = (0x00000080 & dwSH) == 0x00000080; Ctx->PESConvParams.m_bMaxbFrames = (0x00000070 & dwSH) == 0x00000070; Ctx->PESConvParams.m_bFinterpFlag = (0x00000002 & dwSH) == 0x00000002; } } DtsSetVC1SH(hDevice); } return BC_STS_SUCCESS; } BC_STATUS DtsCheckProfile(HANDLE hDevice) { /* DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); uint8_t* pSequenceHeader = Ctx->VidParams.pMetaData; LONG lSize = Ctx->VidParams.MetaDataSz; Ctx->VidParams.NumOfRefFrames = 0; Ctx->VidParams.LevelIDC = 0; if (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_DIVX && Ctx->DevId != BC_PCI_DEVID_FLEA) return BC_STS_ERROR; if((Ctx->VidParams.MediaSubType != BC_MSUBTYPE_AVC1) && (Ctx->VidParams.MediaSubType != BC_MSUBTYPE_H264)) return BC_STS_SUCCESS; if (pSequenceHeader == NULL || lSize <= 0) return BC_STS_SUCCESS; //Get SPS Size int iSPSSize = (pSequenceHeader[0] << 8) + pSequenceHeader[1]; uint8_t *pSPS = &pSequenceHeader[2]; if (iSPSSize <=0) return BC_STS_SUCCESS; NALUnit nalu(pSPS, iSPSSize); if(nalu.Type() == NALUnit::NAL_Sequence_Params) { SeqParamSet sq; if(sq.Parse(&nalu)) { int cx = sq.EncodedWidth(); int cy = sq.EncodedHeight(); bool bInterlace = sq.Interlaced(); unsigned int iNumRefFrames = sq.NumRefFrames(); // In Link we allocated 12 HD buffers for VDEC processing. This implies 12 * 1920 * 1088 bytes of memory storage. // The actual number of reference pictures allowed will be 2 less than the number of buffers allocated. // 2 is the number of pictures for processing overhead. // For various resolutions the amount of memory required per buffer is as follows - // 288x352 - 172032 // 144x176 - 65536 // 1088x1920 - 3194880 // 576x720 - 688128 // 320x352 - 196608 // 160x176 - 65536 // 720x1280 - 1474560 // Use these values to determine the number of reference pictures we can support without errors in the HW unsigned int iNumRefPicturesSupported; // Just handle the two large cases. Assume that no clips exist with greater than 24 reference pictures // since no valid Profile/Level exists for that case. However x264 allows crazy things to happen. So change if needed. if(cy > 720) iNumRefPicturesSupported = ((12 * 3194880) / 3194880) - 2; else iNumRefPicturesSupported = ((12 * 3194880) / 1474560) - 2; if(iNumRefFrames > iNumRefPicturesSupported) { //Reject return BC_STS_ERROR; } Ctx->VidParams.NumOfRefFrames = iNumRefFrames; Ctx->VidParams.LevelIDC = sq.LevelIDC(); } } */ return BC_STS_SUCCESS; } BOOL DtsChkAVCSps(HANDLE hDevice, uint8_t *pBuffer, uint32_t ulSize) { NALU_t Nalu; int ret = 0; uint32_t Pos = 0; while (1) { ret=DtsGetNaluType(hDevice, pBuffer + Pos,ulSize - Pos,&Nalu, false); if (ret <= 0) { return FALSE; } Pos += ret; if (Nalu.NalUnitType == NALU_TYPE_SPS) return TRUE; } return FALSE; } BOOL DtsCheckSpsPps(HANDLE hDevice, uint8_t *pBuffer, uint32_t ulSize) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if((Ctx->VidParams.MediaSubType == BC_MSUBTYPE_H264) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_AVC1) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_DIVX) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_DIVX311)) return DtsChkAVCSps(hDevice, pBuffer, ulSize); else return FALSE; } BC_STATUS DtsAddH264SCode(HANDLE hDevice, uint8_t **ppBuffer, uint32_t *pUlDataSize, uint64_t *pTimeStamp) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); uint32_t lPendActualSize = 0; uint8_t *pPendCurrentPos = NULL; uint8_t *pStart = NULL; uint32_t lDataRemained = 0; //unused uint64_t timestamp = *pTimeStamp; uint8_t *pNALU = NULL; uint32_t ulNalSize = 0; int sts; if(Ctx->PESConvParams.lPendBufferSize < (*pUlDataSize*2)) { if (Ctx->PESConvParams.pStartcodePendBuff) free(Ctx->PESConvParams.pStartcodePendBuff); Ctx->PESConvParams.lPendBufferSize = *pUlDataSize * 2; if (Ctx->PESConvParams.lPendBufferSize < 1024) Ctx->PESConvParams.lPendBufferSize = 1024; // minimum 8 byte aligned since posix_memalign needs to have min of size of (void *) and on 64-bit this is 8 bytes sts = posix_memalign((void**)&Ctx->PESConvParams.pStartcodePendBuff, 8, Ctx->PESConvParams.lPendBufferSize); if(sts != 0) return BC_STS_INSUFF_RES; } //Replace Start Code lDataRemained = *pUlDataSize; pStart = *ppBuffer; lPendActualSize = 0; pPendCurrentPos = Ctx->PESConvParams.pStartcodePendBuff; while(1) { if(Ctx->PESConvParams.m_lStartCodeDataSize != 0) { //Remained if(Ctx->PESConvParams.m_lStartCodeDataSize >= lDataRemained) { //Pre-Update Size lPendActualSize = lPendActualSize + lDataRemained; //Check Copy Size if(lPendActualSize > Ctx->PESConvParams.lPendBufferSize) { //Error Ctx->PESConvParams.m_lStartCodeDataSize = 0; return BC_STS_ERROR; } //Copy to Pend Buffer memcpy(pPendCurrentPos, pStart, lDataRemained); //Update Pending Buffer pPendCurrentPos = pPendCurrentPos + lDataRemained; //Update Source Buffer pStart = pStart + lDataRemained; Ctx->PESConvParams.m_lStartCodeDataSize = Ctx->PESConvParams.m_lStartCodeDataSize - lDataRemained; lDataRemained = 0; //Done break; } else { //Get Start Code Position //Pre-Update Size lPendActualSize = lPendActualSize + Ctx->PESConvParams.m_lStartCodeDataSize; //Check Copy Size if(lPendActualSize > Ctx->PESConvParams.lPendBufferSize) { //Error Ctx->PESConvParams.m_lStartCodeDataSize = 0; return BC_STS_ERROR; } //Copy to Pend Buffer memcpy(pPendCurrentPos, pStart, Ctx->PESConvParams.m_lStartCodeDataSize); //Update Pending Buffer pPendCurrentPos = pPendCurrentPos + Ctx->PESConvParams.m_lStartCodeDataSize; //Update Source Buffer pStart = pStart + Ctx->PESConvParams.m_lStartCodeDataSize; lDataRemained = lDataRemained - Ctx->PESConvParams.m_lStartCodeDataSize; Ctx->PESConvParams.m_lStartCodeDataSize = 0; } } //Get Start Code uint8_t *StartCode = pStart; if(lDataRemained > Ctx->VidParams.StartCodeSz) { //Get Size for(uint32_t i = 0;i < Ctx->VidParams.StartCodeSz;i++) { Ctx->PESConvParams.m_lStartCodeDataSize <<= 8; Ctx->PESConvParams.m_lStartCodeDataSize += StartCode[i]; } if(Ctx->PESConvParams.m_lStartCodeDataSize < 0) { //Error Ctx->PESConvParams.m_lStartCodeDataSize = 0; return BC_STS_ERROR; } else if(Ctx->PESConvParams.m_lStartCodeDataSize == 1) { //Could be Alreay a Start Code Ctx->PESConvParams.m_lStartCodeDataSize = 0; Ctx->PESConvParams.m_bIsAdd_SCode_CodeIn = false; if (Ctx->PESConvParams.pStartcodePendBuff) free(Ctx->PESConvParams.pStartcodePendBuff); Ctx->PESConvParams.lPendBufferSize = 0; Ctx->PESConvParams.pStartcodePendBuff = NULL; return BC_STS_SUCCESS; } else if(Ctx->PESConvParams.m_lStartCodeDataSize < *pUlDataSize) { //Succeeded //Check NAL Unit Type pNALU = pStart + Ctx->VidParams.StartCodeSz; ulNalSize = Ctx->PESConvParams.m_lStartCodeDataSize; //BRCM Start Code //Pre-Update Size lPendActualSize = lPendActualSize + BRCM_START_CODE_SIZE; //Check Copy Size if(lPendActualSize >Ctx->PESConvParams.lPendBufferSize) { //Error Ctx->PESConvParams.m_lStartCodeDataSize = 0; return BC_STS_ERROR; } //Add to Pending Buffer for(int i=0;iVidParams.StartCodeSz; lDataRemained = lDataRemained - Ctx->VidParams.StartCodeSz; } } else { //Error return BC_STS_IO_XFR_ERROR; } }//While //Use Pending Buffer Directly *ppBuffer = Ctx->PESConvParams.pStartcodePendBuff; *pUlDataSize = lPendActualSize; return BC_STS_SUCCESS; } BC_STATUS DtsAddVC1SCode(HANDLE hDevice, uint8_t **ppBuffer, uint32_t *pUlDataSize, uint64_t *pTimeStamp) { uint32_t iCount = 0; int sts = 0; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); uint64_t timestamp = *pTimeStamp; //Check Start Code for AP and SP/MP if(((*ppBuffer)[0] == 0x00) && ((*ppBuffer)[1] == 0x00) && ((*ppBuffer)[2] == 0x01) && (((*ppBuffer)[3] == 0x0F) || ((*ppBuffer)[3] == 0x0D) || ((*ppBuffer)[3] == 0xE0))) { Ctx->PESConvParams.m_bIsAdd_SCode_CodeIn = false; if (Ctx->PESConvParams.pStartcodePendBuff) free(Ctx->PESConvParams.pStartcodePendBuff); Ctx->PESConvParams.lPendBufferSize = 0; Ctx->PESConvParams.pStartcodePendBuff = NULL; return BC_STS_SUCCESS; } if(Ctx->PESConvParams.lPendBufferSize < (*pUlDataSize*2)) { if (Ctx->PESConvParams.pStartcodePendBuff) free(Ctx->PESConvParams.pStartcodePendBuff); Ctx->PESConvParams.lPendBufferSize = *pUlDataSize * 2; if (Ctx->PESConvParams.lPendBufferSize < 1024) Ctx->PESConvParams.lPendBufferSize = 1024; sts = posix_memalign((void**)&Ctx->PESConvParams.pStartcodePendBuff, 8, Ctx->PESConvParams.lPendBufferSize); if(sts) return BC_STS_INSUFF_RES; } //unused uint8_t* pSequenceHeader = Ctx->VidParams.pMetaData; //unused LONG iSHSize = Ctx->VidParams.MetaDataSz; if((Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WVC1) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMVA)) { //Copy Start Code LONG lStartCodeSize = 4; memcpy(Ctx->PESConvParams.pStartcodePendBuff + iCount, (uint8_t *)b_asf_vc1_frame_scode, lStartCodeSize); iCount += lStartCodeSize; //Copy Data memcpy(Ctx->PESConvParams.pStartcodePendBuff + iCount, (uint8_t *)*ppBuffer, *pUlDataSize); iCount +=*pUlDataSize; *pTimeStamp = timestamp; } else { //SP / MP uint8_t* pData = *ppBuffer; uint8_t* pDst = Ctx->PESConvParams.pStartcodePendBuff; if (Ctx->DevId == BC_PCI_DEVID_LINK) { LONG lCIHeaderSize = 17; LONG lCIPacketSize = 0; LONG lCIZeroPaddingSize = 0; LONG lCILastDataLoc = *pUlDataSize - 1; if ((lCIHeaderSize + *pUlDataSize) & 0x1F) lCIPacketSize = (((lCIHeaderSize + *pUlDataSize) / 32) + 1) * 32; else lCIPacketSize = (lCIHeaderSize + *pUlDataSize); //Code-In Zero Padding lCIZeroPaddingSize = lCIPacketSize - (lCIHeaderSize + *pUlDataSize); memcpy(pDst, b_asf_vc1_sm_codein_header, 16); *((uint32_t *)(pDst + 4)) = DWORD_SWAP((uint32_t)lCIPacketSize); *((uint32_t *)(pDst + 8)) = DWORD_SWAP((uint32_t)lCILastDataLoc); memcpy(pDst + 16, (uint8_t *)b_asf_vc1_sm_codein_data_suffix, 1); memcpy(pDst + 17, pData, *pUlDataSize); memset(pDst + 17 + *pUlDataSize, 0, lCIZeroPaddingSize); iCount = lCIPacketSize; } else if (Ctx->DevId == BC_PCI_DEVID_FLEA) { memcpy(pDst, b_asf_vc1_sm_picheader_scode, 4); memcpy(pDst + 4, pData, *pUlDataSize); iCount = *pUlDataSize + 4; } } *ppBuffer = Ctx->PESConvParams.pStartcodePendBuff; *pUlDataSize = iCount; return BC_STS_SUCCESS; } BC_STATUS DtsCheckKeyFrame(HANDLE hDevice, uint8_t *pBuffer) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); //unused BC_STATUS sts = BC_STS_SUCCESS; bool bKeyFrame = false; int iType = 0; if((Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WVC1) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMVA)) { //Advanced Profile //0: P Type //1: B Type //2: I Type //3: BI Type //Interlaced Check if(!Ctx->VidParams.Progressive) { //Interlaced //Skip FCM with 2 bits //Get Type //--xx xxxx //--? if((pBuffer[0] & 0x20) == 0) { iType = 0; } //--1? else if((pBuffer[0] & 0x10) == 0) { iType = 1; } //--11 ? else if((pBuffer[0] & 0x08) == 0) { iType = 2; } //--11 1? else if((pBuffer[0] & 0x04) == 0) { iType = 3; } } else { //Progress //Get Type //xxxx xxxx //? if((pBuffer[0] & 0x80) == 0) { iType = 0; } //1? else if((pBuffer[0] & 0x40) == 0) { iType = 1; } //11? else if((pBuffer[0] & 0x20) == 0) { iType = 2; } //111? else if((pBuffer[0] & 0x10) == 0) { iType = 3; } } //Check Key Frame if(iType == 2) { bKeyFrame = true; } } else { //SP / MP //0: P Type //1: B Type //2: I Type //3: BI Type int iCurrentBit = 0; //Check Finterpflag if(Ctx->PESConvParams.m_bFinterpFlag) { iCurrentBit = iCurrentBit + 1; } //Drop 2 bits iCurrentBit = iCurrentBit + 2; //Check Rangered if(Ctx->PESConvParams.m_bRangered) { iCurrentBit = iCurrentBit + 1; } //Check Bit uint8_t bFirstCheck = 0; uint8_t bSecondCheck = 0; if(iCurrentBit == 2) { bFirstCheck = 0x20; bSecondCheck = 0x10; } else if(iCurrentBit == 3) { bFirstCheck = 0x10; bSecondCheck = 0x08; } else if(iCurrentBit == 4) { bFirstCheck = 0x08; bSecondCheck = 0x04; } if(pBuffer[0] & bFirstCheck) { iType = 0; } else if(!Ctx->PESConvParams.m_bMaxbFrames) { iType = 2; } else if(pBuffer[0] & bSecondCheck) { iType = 2; } else { iType = 1; } //Check Key Frame if(iType == 2) { bKeyFrame = true; } } if (bKeyFrame) { Ctx->PESConvParams.m_bAddSpsPps = true; } return BC_STS_SUCCESS; } BC_STATUS DtsAddStartCode(HANDLE hDevice, uint8_t **ppBuffer, uint32_t *pUlDataSize, uint64_t * pTimeStamp) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); //unused BC_STATUS sts = BC_STS_SUCCESS; if (!Ctx->PESConvParams.m_bIsAdd_SCode_CodeIn) return BC_STS_SUCCESS; if(Ctx->VidParams.MediaSubType == BC_MSUBTYPE_AVC1 || Ctx->VidParams.MediaSubType == BC_MSUBTYPE_DIVX) return DtsAddH264SCode(hDevice, ppBuffer, pUlDataSize, pTimeStamp); if((Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WVC1) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMV3) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMVA) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_VC1)) return DtsAddVC1SCode(hDevice, ppBuffer, pUlDataSize, pTimeStamp); return BC_STS_SUCCESS; } int DtsFindBSStartCode (unsigned char *Buf, int ZerosInStartcode) { BOOL bStartCode = TRUE; int i; for (i = 0; i < ZerosInStartcode; i++) if(Buf[i] != 0) bStartCode = FALSE; if(Buf[i] != 1) bStartCode = FALSE; return bStartCode; } int DtsGetNaluType(HANDLE hDevice, uint8_t* pInputBuf, uint32_t ulSize, NALU_t* pNalu, bool bSkipSyncMarker) { DTS_LIB_CONTEXT *Ctx = NULL; int b20sInSC, b30sInSC ; int bStartCodeFound, Rewind; int nLeadingZero8BitsCount=0, TrailingZero8Bits=0; //unused bool bSetIDR = true; //unused static BOOL fOne = TRUE; uint32_t Pos = 0; DTS_GET_CTX(hDevice,Ctx); if (bSkipSyncMarker) { pNalu->NalUnitType = (pInputBuf[0]) & 0x1f; pNalu->Len = ulSize; return 1; } while(Pos <= ulSize) { if( (pInputBuf[Pos++]) == 0) continue; else break; } if(pInputBuf[Pos-1] != 1) { return -1; } if(Pos < 3) { return -1; } else if(Pos == 3) { pNalu->StartcodePrefixLen = 3; nLeadingZero8BitsCount = 0; } else { nLeadingZero8BitsCount = Pos-4; pNalu->StartcodePrefixLen = 4; } //the 1st byte stream NAL unit can has nLeadingZero8BitsCount, but subsequent ones are not //allowed to contain it since these zeros(if any) are considered trailing_zero_8bits //of the previous byte stream NAL unit. if(!Ctx->PESConvParams.m_bIsFirstByteStreamNALU && nLeadingZero8BitsCount>0) { // DbgLog((LOG_TRACE, 1, TEXT("GetNaluType : ret 3\n"))); return -1; } Ctx->PESConvParams.m_bIsFirstByteStreamNALU = false; bStartCodeFound = 0; b20sInSC = 0; b30sInSC = 0; while( (!bStartCodeFound) && (Pos < ulSize)) { Pos++; if(Pos > ulSize) { // DbgLog((LOG_TRACE, 1, TEXT("GetNaluType : Pos > size = %d\n"),ulSize)); } b30sInSC = DtsFindBSStartCode( (pInputBuf + Pos- 4), 3); if(b30sInSC != 1) b20sInSC = DtsFindBSStartCode( (pInputBuf + Pos -3), 2); bStartCodeFound = (b20sInSC || b30sInSC); } Rewind = 0; if(!bStartCodeFound) { // DbgLog((LOG_TRACE, 1, TEXT("GetNaluType : ret 4 Pos = %d size = %d\n"),Pos,ulSize)); //even if next start code is not found pprocess this NAL. #if 0 return -1; #endif } if(bStartCodeFound) { //Count the trailing_zero_8bits //TrailingZero8Bits is present only for start code 00 00 00 01 if(b30sInSC) { while(pInputBuf[Pos-5-TrailingZero8Bits]==0) TrailingZero8Bits++; } // Here, we have found another start code (and read length of startcode bytes more than we should // have. Hence, go back in the file if(b30sInSC) Rewind = -4; else if (b20sInSC) Rewind = -3; } // Here the leading zeros(if any), Start code, the complete NALU, trailing zeros(if any) // until the next start code . // Total size traversed is Pos, Pos+rewind are the number of bytes excluding the next // start code, and (Pos+rewind)-StartcodePrefixLen-LeadingZero8BitsCount-TrailingZero8Bits // is the size of the NALU. pNalu->Len = (Pos+Rewind)-pNalu->StartcodePrefixLen-nLeadingZero8BitsCount-TrailingZero8Bits; pNalu->NalUnitType = (pInputBuf[nLeadingZero8BitsCount+pNalu->StartcodePrefixLen]) & 0x1f; return (Pos+Rewind); } BC_STATUS DtsParseAVC(HANDLE hDevice, uint8_t* pInputBuf, ULONG ulSize, uint32_t* Offset, bool bIDR, int *pNalType) { NALU_t Nalu; int ret = 0; uint32_t Pos = 0; bool bResult = false; *pNalType = -1; while (1) { ret=DtsGetNaluType(hDevice, pInputBuf + Pos,ulSize - Pos,&Nalu, false); if (ret <= 0) { return BC_STS_ERROR; } Pos += ret; switch (Nalu.NalUnitType) { case NALU_TYPE_SLICE: case NALU_TYPE_IDR: bResult = true; break; case NALU_TYPE_SEI: case NALU_TYPE_PPS: case NALU_TYPE_SPS: if(!bIDR) bResult = true; break; case NALU_TYPE_DPA: case NALU_TYPE_DPC: case NALU_TYPE_AUD: case NALU_TYPE_EOSEQ: case NALU_TYPE_EOSTREAM: case NALU_TYPE_FILL: default: break; } if(bResult) { *Offset = Pos; break; } } *pNalType = Nalu.NalUnitType; return BC_STS_SUCCESS; } BC_STATUS DtsFindIDR(HANDLE hDevice, uint8_t* pInputBuffer, uint32_t ulSizeInBytes, uint32_t* pOffset) { int nNalType = 0; uint32_t ulPos = 0; DtsParseAVC(hDevice, pInputBuffer, ulSizeInBytes, &ulPos, true, &nNalType); if( (nNalType == NALU_TYPE_SLICE) | (nNalType == NALU_TYPE_IDR)) { *pOffset = ulPos; return BC_STS_SUCCESS; } return BC_STS_ERROR; } BC_STATUS DtsFindStartCode(HANDLE hDevice, uint8_t* pInputBuffer, uint32_t ulSizeInBytes, uint32_t* pOffset) { DTS_LIB_CONTEXT *Ctx = NULL; uint32_t i=0; uint8_t Suffix1 = 0; uint8_t Suffix2 = 0; *pOffset = 0; DTS_GET_CTX(hDevice,Ctx); if (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WVC1 || Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMVA || Ctx->VidParams.MediaSubType == BC_MSUBTYPE_VC1) { Suffix1 = VC1_FRM_SUFFIX; Suffix2 = VC1_SEQ_SUFFIX; } else if (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_MPEG2VIDEO) { Suffix1 = MPEG2_FRM_SUFFIX; Suffix2 = MPEG2_SEQ_SUFFIX; } else if (Ctx->VidParams.MediaSubType ==BC_MSUBTYPE_WMV3) //For VC-1 SP/MP { Suffix1 = VC1_SM_FRM_SUFFIX; } if((Ctx->VidParams.MediaSubType == BC_MSUBTYPE_H264) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_AVC1) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_DIVX)) { int nNalType = 0; uint32_t ulPos = 0; if (DtsParseAVC(hDevice, pInputBuffer,ulSizeInBytes,&ulPos,false, &nNalType) != BC_STS_SUCCESS) return BC_STS_ERROR; if( (nNalType == NALU_TYPE_SEI) || (nNalType == NALU_TYPE_PPS) || (nNalType == NALU_TYPE_SPS)) { *pOffset = ulPos; return BC_STS_SUCCESS; } else if( (nNalType == NALU_TYPE_SLICE) | (nNalType == NALU_TYPE_IDR)) { *pOffset = 0; return BC_STS_SUCCESS; } return BC_STS_ERROR; } else if((Ctx->VidParams.MediaSubType == BC_MSUBTYPE_MPEG2VIDEO) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WVC1) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMVA) || (Ctx->VidParams.MediaSubType ==BC_MSUBTYPE_WMV3) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_VC1)) { while(i < ulSizeInBytes) { if( (*(pInputBuffer +i) == Suffix1) || (*(pInputBuffer +i) == Suffix2)) { if(i >= 3) { if( (*(pInputBuffer+(i-3)) == 0x00) && (*(pInputBuffer+(i-2)) == 0x00) && (*(pInputBuffer+(i-1)) == 0x01)) { *pOffset = i-3; return BC_STS_SUCCESS; } } } i++; } return BC_STS_ERROR; } return BC_STS_SUCCESS; } BOOL DtsFindPTSInfoCode(HANDLE hDevice, uint8_t* pInputBuffer, uint32_t ulSizeInBytes) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if((Ctx->VidParams.MediaSubType != BC_MSUBTYPE_WMV3) && (Ctx->VidParams.MediaSubType != BC_MSUBTYPE_WMVA)) return FALSE; //Move PES Header uint32_t ulCurrent = 8; uint8_t bPESHeaderLen = pInputBuffer[ulCurrent]; ulCurrent = ulCurrent + bPESHeaderLen + 1; //Check PES Payload for PTS Info if((ulSizeInBytes - ulCurrent) == 32) { DWORD dwFirstCode = *(DWORD *)&pInputBuffer[ulCurrent]; ulCurrent = ulCurrent + 12; DWORD dwSecondCode = *(DWORD *)&pInputBuffer[ulCurrent]; ulCurrent = ulCurrent + 4; if((dwFirstCode == VC1_SM_MAGIC_WORD) && (dwSecondCode == VC1_SM_MAGIC_WORD) && (pInputBuffer[ulCurrent] == VC1_SM_PTS_INFO_START_CODE)) { return TRUE; } } return FALSE; } BC_STATUS DtsSymbIntSiBuffer (HANDLE hDevice, uint8_t* pInputBuffer, ULONG ulSize) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); SYMBINT *pSymbint = &(Ctx->PESConvParams.m_SymbInt); pSymbint->m_pCurrent = pSymbint->m_pInputBuffer = (uint8_t*) pInputBuffer; pSymbint->m_nSize = ulSize; pSymbint->m_pInputBufferEnd = pSymbint->m_pInputBuffer + ulSize; pSymbint->m_nUsed = 1; pSymbint->m_ulOffset = 0; pSymbint->m_ulMask = 0x80; return BC_STS_SUCCESS; } BC_STATUS DtsSymbIntSiUe (HANDLE hDevice, ULONG* pCode) { uint32_t ulSuffix; int nLeadingZeros; int nBit; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); SYMBINT *pSymbint = &(Ctx->PESConvParams.m_SymbInt); nLeadingZeros = -1; for (nBit = 0; nBit == 0; nLeadingZeros++) { nBit = DtsSymbIntNextBit(hDevice); if(pSymbint->m_nUsed >= pSymbint->m_nSize) return BC_STS_ERROR; } *pCode = (1 << nLeadingZeros) - 1; ulSuffix = 0; while (nLeadingZeros-- > 0 ) { ulSuffix = (ulSuffix << 1) | DtsSymbIntNextBit(hDevice); if(pSymbint->m_nUsed >= pSymbint->m_nSize) return BC_STS_ERROR; } *pCode += ulSuffix; return BC_STS_SUCCESS; } inline int DtsSymbIntNextBit ( HANDLE hDevice ) { int nBit; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); SYMBINT *pSymbint = &(Ctx->PESConvParams.m_SymbInt); nBit = (pSymbint->m_pCurrent[0] & pSymbint->m_ulMask) ? 1 : 0; if ((pSymbint->m_ulMask >>= 1) == 0) { pSymbint->m_ulMask = 0x80; if ( pSymbint->m_nUsed == pSymbint->m_nSize ) pSymbint->m_pCurrent = pSymbint->m_pInputBuffer;//reset look again else { if ( ++pSymbint->m_pCurrent == pSymbint->m_pInputBufferEnd ) pSymbint->m_pCurrent = pSymbint->m_pInputBuffer; pSymbint->m_nUsed++; } } pSymbint->m_ulOffset++; return nBit; } #if 0 void *DtsAlignedMalloc(size_t size, size_t alignment) { void *p1 ,*p2; // basic pointer needed for computation. if((p1 =(void *) malloc(size + alignment + sizeof(size_t)))==NULL) return NULL; size_t addr = (size_t)p1 + alignment + sizeof(size_t); p2 = (void *)(addr - (addr%alignment)); *((size_t *)p2-1) = (size_t)p1; return p2; } void DtsAlignedFree(void *ptr) { if (ptr) free((void *)(*((size_t *) ptr-1))); } #endif crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/libcrystalhd_parser.h0000644000175000017500000001153511610313111026414 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_parser.h * * Description: Driver Interface library Internal. * * AU * * HISTORY: * ******************************************************************** * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #ifndef CPARSE #define CPARSE #include //VC1 prefix 000001 #define VC1_FRM_SUFFIX 0x0D #define VC1_SEQ_SUFFIX 0x0F //VC1 SM Profile prefix 000001 #define VC1_SM_FRM_SUFFIX 0xE0 //Check WMV SP/MP PES Payload for PTS Info #define VC1_SM_MAGIC_WORD 0x5A5A5A5A #define VC1_SM_PTS_INFO_START_CODE 0xBD //MPEG2 prefix 000001 #define MPEG2_FRM_SUFFIX 0x00 #define MPEG2_SEQ_SUFFIX 0xB3 #define BRCM_START_CODE_SIZE 4 //Packetized PES #define MAX_RE_PES_BOUND (LONG)0xFFF0 static const uint8_t b_pes_header[9]={0x00, 0x00, 0x01, 0xE0, 0x00, 0x00, 0x81, 0x00, 0x00}; typedef enum { P_SLICE = 0, B_SLICE, I_SLICE, SP_SLICE, SI_SLICE } SliceType; typedef enum { NALU_TYPE_SLICE = 1, NALU_TYPE_DPA, NALU_TYPE_DPB, NALU_TYPE_DPC, NALU_TYPE_IDR, NALU_TYPE_SEI, NALU_TYPE_SPS, NALU_TYPE_PPS, NALU_TYPE_AUD, NALU_TYPE_EOSEQ, NALU_TYPE_EOSTREAM, NALU_TYPE_FILL }NALuType; typedef struct { int32_t StartcodePrefixLen; //! 4 for parameter sets and first slice in picture, 3 for everything else (suggested) uint32_t Len; //! Length of the NAL unit (Excluding the start code, which does not belong to the NALU) uint32_t MaxSize; //! Nal Unit Buffer size int32_t NalUnitType; //! NALU_TYPE_xxxx int32_t ForbiddenBit; //! should be always FALSE uint8_t* pNalBuf; } NALU_t; typedef struct stSYMBINT { uint8_t* m_pInputBuffer; uint8_t* m_pInputBufferEnd; uint8_t* m_pCurrent; uint32_t m_ulMask; uint32_t m_ulOffset; uint32_t m_nSize; uint32_t m_nUsed; uint32_t m_ulZero; } SYMBINT; typedef struct stPES_CONVERT_PARAMS { bool m_bIsFirstByteStreamNALU; SYMBINT m_SymbInt; uint8_t* m_pSpsPpsBuf; uint32_t m_iSpsPpsLen; uint32_t m_lStartCodeDataSize; uint8_t *pStartcodePendBuff; uint32_t lPendBufferSize; //Get Sequence Header Info (Sequence Layer Bitestream for Simple and Main Profile) bool m_bRangered; bool m_bFinterpFlag; bool m_bMaxbFrames; bool m_bIsAdd_SCode_CodeIn; bool m_bAddSpsPps; //PES header parameter bool m_bPESPrivData; bool m_bPESExtField; uint32_t m_nPESExtLen; bool m_bStuffing; uint32_t m_nStuffingBytes; uint8_t *m_pPESPrivData; uint8_t *m_pPESExtField; //SoftRave (VC-1 S/M and Divx) EOS Timing Marker bool m_bSoftRave; }PES_CONVERT_PARAMS; BC_STATUS DtsSetPESConverter( HANDLE hDevice); BC_STATUS DtsInitPESConverter(HANDLE hDevice); BC_STATUS DtsReleasePESConverter(HANDLE hDevice); BC_STATUS DtsCheckProfile(HANDLE hDevice); BC_STATUS DtsCheckKeyFrame(HANDLE hDevice, uint8_t *pBuffer); BC_STATUS DtsSetSpsPps(HANDLE hDevice); BOOL DtsCheckSpsPps(HANDLE hDevice, uint8_t *pBuffer, uint32_t ulSize); BC_STATUS DtsSetVC1SH(HANDLE hDevice); BC_STATUS DtsAddH264SCode(HANDLE hDevice, uint8_t **ppBuffer, uint32_t *pUlDataSize, uint64_t *timeStamp); BC_STATUS DtsAddVC1SCode(HANDLE hDevice, uint8_t **ppBuffer, uint32_t *pUlDataSize, uint64_t *timeStamp); BC_STATUS DtsAddStartCode(HANDLE hDevice, uint8_t **ppBuffer, uint32_t *pUlDataSize, uint64_t *timeStamp); int32_t DtsFindBSStartCode (uint8_t *Buf, int ZerosInStartcode); int32_t DtsGetNaluType(HANDLE hDevice, uint8_t* pInputBuf, uint32_t ulSize, NALU_t* pNalu, bool bSkipSyncMarker); BC_STATUS DtsParseAVC(HANDLE hDevice, uint8_t* pInputBuf, uint32_t ulSize, uint32_t* Offset, bool bIDR, int32_t *pNalType); BC_STATUS DtsFindIDR(HANDLE hDevice, uint8_t* pInputBuffer, uint32_t ulSizeInBytes, uint32_t* pOffset); BC_STATUS DtsFindStartCode(HANDLE hDevice, uint8_t* pInputBuffer, uint32_t ulSizeInBytes, uint32_t* pOffset); BOOL DtsFindPTSInfoCode(HANDLE hDevice, uint8_t* pInputBuffer, uint32_t ulSizeInBytes); inline int32_t DtsSymbIntNextBit ( HANDLE hDevice ); BC_STATUS DtsSymbIntSiUe (HANDLE hDevice, uint32_t* pCode); BC_STATUS DtsSymbIntSiBuffer (HANDLE hDevice, uint8_t* pInputBuffer, uint32_t ulSize); void PTS2MakerBit5Bytes(uint8_t *pMakerBit, int64_t llPTS); uint16_t WORD_SWAP(uint16_t x); #endif crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/libcrystalhd_int_if.h0000644000175000017500000001256211610313111026371 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_int_if.h * * Description: Driver Internal functions. * * AU * * HISTORY: * ******************************************************************** * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #ifndef _BCM_DRV_INT_H_ #define _BCM_DRV_INT_H_ #include "bc_dts_glob_lnx.h" #ifdef __cplusplus extern "C" { #endif #define BSVS_UART_DEC_NONE 0x00 #define BSVS_UART_DEC_OUTER 0x01 #define BSVS_UART_DEC_INNER 0x02 #define BSVS_UART_STREAM 0x03 #define STREAM_VERSION_ADDR 0x001c5f00 typedef uint32_t BC_DTS_CFG; DRVIFLIB_INT_API BC_STATUS DtsGetHwType( HANDLE hDevice, uint32_t *DeviceID, uint32_t *VendorID, uint32_t *HWRev ); DRVIFLIB_INT_API VOID DtsHwReset( HANDLE hDevice ); DRVIFLIB_INT_API BC_STATUS DtsSetLinkIn422Mode(HANDLE hDevice); DRVIFLIB_INT_API BC_STATUS DtsSetFleaIn422Mode(HANDLE hDevice); DRVIFLIB_INT_API BC_STATUS DtsSoftReset( HANDLE hDevice ); DRVIFLIB_INT_API BC_STATUS DtsGetConfig( HANDLE hDevice, BC_DTS_CFG *cfg ); DRVIFLIB_INT_API BC_STATUS DtsSetCoreClock( HANDLE hDevice, uint32_t freq ); DRVIFLIB_INT_API BC_STATUS DtsSetTSMode( HANDLE hDevice, uint32_t resrv1 ); DRVIFLIB_INT_API BC_STATUS DtsSetProgressive( HANDLE hDevice, uint32_t resrv1 ); BC_STATUS DtsRstVidClkDLL( HANDLE hDevice ); DRVIFLIB_INT_API BC_STATUS DtsSetVideoClock( HANDLE hDevice, uint32_t freq ); DRVIFLIB_INT_API BOOL DtsIsVideoClockSet(HANDLE hDevice); DRVIFLIB_INT_API BC_STATUS DtsGetPciConfigSpace( HANDLE hDevice, uint8_t *info ); DRVIFLIB_INT_API BC_STATUS DtsReadPciConfigSpace( HANDLE hDevice, uint32_t offset, uint32_t *Value, uint32_t Size ); DRVIFLIB_INT_API BC_STATUS DtsWritePciConfigSpace( HANDLE hDevice, uint32_t Offset, uint32_t Value, uint32_t Size ); DRVIFLIB_INT_API BC_STATUS DtsDevRegisterRead( HANDLE hDevice, uint32_t offset, uint32_t *Value ); DRVIFLIB_INT_API BC_STATUS DtsDevRegisterWr( HANDLE hDevice, uint32_t offset, uint32_t Value ); DRVIFLIB_INT_API BC_STATUS DtsFPGARegisterRead( HANDLE hDevice, uint32_t offset, uint32_t *Value ); DRVIFLIB_INT_API BC_STATUS DtsFPGARegisterWr( HANDLE hDevice, uint32_t offset, uint32_t Value ); DRVIFLIB_INT_API BC_STATUS DtsDevMemRd( HANDLE hDevice, uint32_t *Buffer, uint32_t BuffSz, uint32_t Offset ); DRVIFLIB_INT_API BC_STATUS DtsDevMemWr( HANDLE hDevice, uint32_t *Buffer, uint32_t BuffSz, uint32_t Offset ); DRVIFLIB_INT_API BC_STATUS DtsTxDmaText( HANDLE hDevice , uint8_t *pUserData, uint32_t ulSizeInBytes, uint32_t *dramOff, uint8_t Encrypted ); DRVIFLIB_INT_API BC_STATUS DtsGetDrvStat( HANDLE hDevice, BC_DTS_STATS *pDrvStat ); DRVIFLIB_INT_API BC_STATUS DtsSendData( HANDLE hDevice , uint8_t *pUserData, uint32_t ulSizeInBytes, uint64_t timeStamp, BOOL encrypted ); DRVIFLIB_INT_API BC_STATUS DtsSetTemperatureMeasure( HANDLE hDevice, BOOL bTurnOn ); DRVIFLIB_INT_API BC_STATUS DtsGetCoreTemperature( HANDLE hDevice, float *pTemperature ); DRVIFLIB_INT_API BC_STATUS DtsRstDrvStat( HANDLE hDevice ); DRVIFLIB_INT_API BC_STATUS DtsGetFWFiles( HANDLE hDevice, char *StreamFName, char *VDecOuter, char *VDecInner ); DRVIFLIB_INT_API BC_STATUS DtsDownloadFWBin( HANDLE hDevice, uint8_t *binBuff, uint32_t buffsize, uint32_t sig ); DRVIFLIB_INT_API BC_STATUS DtsCancelProcOutput( HANDLE hDevice, PVOID Context); DRVIFLIB_INT_API BC_STATUS DtsChkYUVSizes( struct _DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *Vout, BC_DTS_PROC_OUT *Vin); BC_STATUS DtsCopyRawDataToOutBuff( struct _DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *Vout, BC_DTS_PROC_OUT *Vin); BC_STATUS DtsCopyNV12ToYV12( struct _DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *Vout, BC_DTS_PROC_OUT *Vin); BC_STATUS DtsCopyNV12( struct _DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *Vout, BC_DTS_PROC_OUT *Vin); BC_STATUS DtsCopyFormat( struct _DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *Vout, BC_DTS_PROC_OUT *Vin); BC_STATUS DtsSendEOS( HANDLE hDevice, uint32_t Op ); extern DRVIFLIB_INT_API BC_STATUS DtsPushFwBinToLink(HANDLE hDevice, uint32_t *FwBinFile, uint32_t bytesDnld); /*================ Debug/Test Routines ===================*/ DRVIFLIB_INT_API void DumpDataToFile( FILE *fp, char *header, uint32_t off, uint8_t *buff, uint32_t dwcount ); void DumpInputSampleToFile(uint8_t *buff, uint32_t buffsize); #ifdef __cplusplus } #endif #endif crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/ln-libcrystalhd.sh0000644000175000017500000000035411610313111025627 0ustar andresandres#!/bin/bash # # Author: Prasad Bolisetty # # Script to create symlink for crystalhd soname. # # TBD:: Add install option. For now ==> ${PWD} # ln -sf libcrystalhd.so.1.0 libcrystalhd.so ln -sf libcrystalhd.so.1.0 libcrystalhd.so.1 crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/libcrystalhd_fwload_if.cpp0000644000175000017500000001330311610313111027400 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_fwload_if.cpp * * Description: Firmware diagnostics * * AU * * HISTORY: * ******************************************************************** * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #include "7411d.h" #include "bc_defines.h" #include "bcm_70012_regs.h" /* Link Register defs */ #include "libcrystalhd_fwload_if.h" #include "libcrystalhd_int_if.h" #include "libcrystalhd_priv.h" DRVIFLIB_INT_API BC_STATUS DtsPushAuthFwToLink(HANDLE hDevice, char *FwBinFile) { BC_STATUS status=BC_STS_ERROR; uint32_t byesDnld=0; char *fwfile=NULL; DTS_LIB_CONTEXT *Ctx=NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->OpMode == DTS_DIAG_MODE){ /* In command line case, we don't get a close * between successive devinit commands. */ Ctx->FixFlags &= ~DTS_LOAD_FILE_PLAY_FW; if(FwBinFile){ if(!strncmp(FwBinFile,"FILE_PLAY_BACK",14)){ Ctx->FixFlags |=DTS_LOAD_FILE_PLAY_FW; FwBinFile=NULL; } } } /* Get the firmware file to download */ if (!FwBinFile) { status = DtsGetFirmwareFiles(Ctx); if (status == BC_STS_SUCCESS) fwfile = Ctx->FwBinFile; else return status; } else { fwfile = FwBinFile; } //DebugLog_Trace(LDIL_DBG,"Firmware File is :%s\n",fwfile); /* Push the F/W bin file to the driver */ status = fwbinPushToLINK(hDevice, fwfile, &byesDnld); if (status != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsPushAuthFwToLink: Failed to download firmware\n"); return status; } return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsPushFwToFlea(HANDLE hDevice, char *FwBinFile) { BC_STATUS status=BC_STS_ERROR; uint32_t byesDnld=0; char *fwfile=NULL; DTS_LIB_CONTEXT *Ctx=NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->OpMode == DTS_DIAG_MODE){ /* In command line case, we don't get a close * between successive devinit commands. */ Ctx->FixFlags &= ~DTS_LOAD_FILE_PLAY_FW; if(FwBinFile){ if(!strncmp(FwBinFile,"FILE_PLAY_BACK",14)){ Ctx->FixFlags |=DTS_LOAD_FILE_PLAY_FW; FwBinFile=NULL; } } } /* Get the firmware file to download */ if (!FwBinFile) { status = DtsGetFirmwareFiles(Ctx); if (status == BC_STS_SUCCESS) fwfile = Ctx->FwBinFile; else return status; } else { fwfile = FwBinFile; } //DebugLog_Trace(LDIL_DBG,"Firmware File is :%s\n",fwfile); /* Push the F/W bin file to the driver */ status = fwbinPushToFLEA(hDevice, fwfile, &byesDnld); if (status != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsPushFwToFlea: Failed to download firmware\n"); return status; } return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS fwbinPushToLINK(HANDLE hDevice, char *FwBinFile, uint32_t *bytesDnld) { BC_STATUS status=BC_STS_ERROR; uint32_t FileSz=0; char *buff=NULL; FILE *fp=NULL; if( (!FwBinFile) || (!hDevice) || (!bytesDnld)) { DebugLog_Trace(LDIL_DBG,"Invalid Arguments\n"); return BC_STS_INV_ARG; } fp = fopen(FwBinFile,"rb"); if(!fp) { DebugLog_Trace(LDIL_DBG,"Failed to Open FW file. %s\n", FwBinFile); perror("LINK FW"); return BC_STS_ERROR; } fseek(fp,0,SEEK_END); FileSz = ftell(fp); fseek(fp,0,SEEK_SET); buff = (char*)malloc(FileSz); if (!buff) { DebugLog_Trace(LDIL_DBG,"Failed to allocate memory\n"); return BC_STS_INSUFF_RES; } *bytesDnld = fread(buff,1,FileSz,fp); if(0 == *bytesDnld) { DebugLog_Trace(LDIL_DBG,"Failed to Read The File\n"); return BC_STS_IO_ERROR; } status = DtsPushFwBinToLink(hDevice, (uint32_t*)buff, *bytesDnld); if(buff) free(buff); if(fp) fclose(fp); return status; } DRVIFLIB_INT_API BC_STATUS fwbinPushToFLEA(HANDLE hDevice, char *FwBinFile, uint32_t *bytesDnld) { BC_STATUS status=BC_STS_ERROR; uint32_t FileSz=0; char *buff=NULL; FILE *fp=NULL; if( (!FwBinFile) || (!hDevice) || (!bytesDnld)) { DebugLog_Trace(LDIL_DBG,"Invalid Arguments\n"); return BC_STS_INV_ARG; } fp = fopen(FwBinFile,"rb"); if(!fp) { DebugLog_Trace(LDIL_DBG,"Failed to Open FW file. %s\n", FwBinFile); perror("FLEA FW"); return BC_STS_ERROR; } fseek(fp,0,SEEK_END); FileSz = ftell(fp); fseek(fp,0,SEEK_SET); buff = (char*)malloc(FileSz); if (!buff) { DebugLog_Trace(LDIL_DBG,"Failed to allocate memory\n"); return BC_STS_INSUFF_RES; } *bytesDnld = fread(buff,1,FileSz,fp); if(0 == *bytesDnld) { DebugLog_Trace(LDIL_DBG,"Failed to Read The File\n"); return BC_STS_IO_ERROR; } status = DtsPushFwBinToLink(hDevice, (uint32_t*)buff, *bytesDnld); if(buff) free(buff); if(fp) fclose(fp); return status; } BC_STATUS dec_write_fw_Sig(HANDLE hndl, uint32_t* Sig) { unsigned int *ptr = Sig; unsigned int DciSigDataReg = (unsigned int)DCI_SIGNATURE_DATA_7; BC_STATUS sts = BC_STS_ERROR; for (int reg_cnt=0;reg_cnt<8;reg_cnt++) { sts = DtsFPGARegisterWr(hndl, DciSigDataReg, bswap_32_1(*ptr)); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"Error Wrinting Fw Sig data register\n"); return sts; } DciSigDataReg-=4; ptr++; } return sts; } crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/libcrystalhd_fwcmds.cpp0000644000175000017500000010762211610313111026741 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_fwdcmds.cpp * * Description: Driver Interface library Internal. * * AU * * HISTORY: * ******************************************************************** * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ /******************************************************************* FIRMWARE BINARIES ARE DISTRIBUTED UNDER THE FOLLOWING LICENSE - BINARIES COVERED WITH THIS LICENSE ARE bcm70015fw.bin and bcm70012fw.bin Copyright 2007-2010 Broadcom Corporation Redistribution and use in binary forms of this software, without modification, are permitted provided that the following conditions are met: Redistributions must reproduce the above copyright notice, this list of conditions and the following disclaimer in the documentation and/or other materials provided with the distribution. Neither the name of Broadcom nor the names of its contributors may be used to endorse or promote products derived from this software without specific prior written permission. THIS SOFTWARE IS PROVIDED “AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL BROADCOM BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. *********************************************************************/ #include "7411d.h" #include "libcrystalhd_fwcmds.h" #include "libcrystalhd_priv.h" DRVIFLIB_INT_API BC_STATUS DtsFWInitialize( HANDLE hDevice, uint32_t resrv1 ) { BC_STATUS sts = BC_STS_SUCCESS; C011CmdInit *vi=NULL; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; vi = (C011CmdInit*)&pIocData->u.fwCmd.cmd; vi->command = eCMD_C011_INIT; vi->sequence = ++Ctx->fwcmdseq; vi->memSizeMBytes = 0x00000040; // 64MB vi->inputClkFreq = 200000000; // 200 MHz vi->uartBaudRate = 38400; vi->initArcs = C011_STREAM_ARC|C011_VDEC_ARC; vi->interrupt = eC011_INT_ENABLE; vi->brcmMode = eC011_BRCM_ECG_MODE_ON; vi->fgtEnable = 0x00000001; vi->openMode = Ctx->FixFlags; if(Ctx->DevId == BC_PCI_DEVID_LINK) vi->rsaDecrypt = 0x00000001; if( (sts=DtsDrvCmd(Ctx, BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DtsRelIoctlData(Ctx,pIocData); DebugLog_Trace(LDIL_DBG,"DtsInitialize: Ioctl failed: %d\n",sts); return sts; } if(pIocData->u.fwCmd.rsp[2]){ DtsRelIoctlData(Ctx,pIocData); DebugLog_Trace(LDIL_DBG,"DtsInitialize: Failed %d\n",pIocData->u.fwCmd.rsp[2]); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWOpenChannel( HANDLE hDevice, uint32_t StreamType, uint32_t reserved ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; uint32_t ScaledWidth=0; DTS_GET_CTX(hDevice,Ctx); if(Ctx->State != BC_DEC_STATE_CLOSE) { DebugLog_Trace(LDIL_DBG,"DtsFWOpenChannel: No Active Decoder\n"); return BC_STS_ERR_USAGE; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; if (Ctx->DevId != BC_PCI_DEVID_FLEA) { DecCmdChannelStreamOpen *pOpen; DecRspChannelStreamOpen *pRsp; pOpen = (DecCmdChannelStreamOpen *)&pIocData->u.fwCmd.cmd; pOpen->command = eCMD_C011_DEC_CHAN_STREAM_OPEN; pOpen->sequence = ++Ctx->fwcmdseq; pOpen->inPort = eC011_IN_PORT0; //CSI pOpen->streamType = (eC011_STREAM_TYPE)StreamType; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DtsRelIoctlData(Ctx,pIocData); DebugLog_Trace(LDIL_DBG,"DtsOpenDecoder: Ioctl failed: %d\n",sts); return sts; } pRsp = (DecRspChannelStreamOpen*)&pIocData->u.fwCmd.rsp; if(pRsp->status){ DebugLog_Trace(LDIL_DBG,"DtsOpenDecoder: Failed %d\n",pRsp->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } memcpy(&Ctx->OpenRsp,pRsp,sizeof(Ctx->OpenRsp)); }else{ DecCmdChannelChannelOpen *pOpen; DecRspChannelChannelOpen *pRsp; pOpen = (DecCmdChannelChannelOpen *) &pIocData->u.fwCmd.cmd; pOpen->command = eCMD_C011_DEC_CHAN_OPEN; pOpen->sequence = ++Ctx->fwcmdseq; pOpen->videoAlg = (eC011_VIDEO_ALG) Ctx->VidParams.VideoAlgo; pOpen->streamType = (eC011_STREAM_TYPE)StreamType; pOpen->reservedWord8 =0; if (Ctx->EnableScaling & 0x00000001){ ScaledWidth = (Ctx->EnableScaling>>20)& 0xFFF; if((ScaledWidth>=1920)||(ScaledWidth<128)) ScaledWidth = 960; if(ScaledWidth%2) ScaledWidth+=1; pOpen->reservedWord8 |= ScaledWidth<<20; ScaledWidth=(Ctx->EnableScaling>>8)& 0xFFF; if((ScaledWidth>=1920)||(ScaledWidth<128)) ScaledWidth = 1280; if(ScaledWidth%2) ScaledWidth+=1; pOpen->reservedWord8 |= ScaledWidth<<8; pOpen->reservedWord8 |=1; } DebugLog_Trace(LDIL_DBG,"Scaling command param 0x%x,ctx_scal:0x%x\n",pOpen->reservedWord8,Ctx->EnableScaling); if (Ctx->bEnable720pDropHalf) pOpen->reservedWord14 = 1; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DtsRelIoctlData(Ctx,pIocData); DebugLog_Trace(LDIL_DBG,"DtsOpenDecoder: Ioctl failed: %d\n",sts); return sts; } pRsp = (DecRspChannelChannelOpen*) &pIocData->u.fwCmd.rsp; if(pRsp->status){ DebugLog_Trace(LDIL_DBG,"DtsOpenDecoder: Failed %d\n",pRsp->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } Ctx->OpenRsp.channelId = pRsp->ChannelID; } // For deconf backward compatibility only... Ctx->State = BC_DEC_STATE_STOP; DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWActivateDecoder( HANDLE hDevice ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelActivate *pAct; DecRspChannelActivate *pActRsp; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->State == BC_DEC_STATE_CLOSE) { DebugLog_Trace(LDIL_DBG,"DtsActChannel: Channel is NOT Opened\n"); return BC_STS_DEC_NOT_OPEN; } if(Ctx->State == BC_DEC_STATE_START) { DebugLog_Trace(LDIL_DBG,"DtsActChannel: Channel is already Opened\n"); return BC_STS_SUCCESS; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; pAct = (DecCmdChannelActivate *)&pIocData->u.fwCmd.cmd; pAct->command = eCMD_C011_DEC_CHAN_ACTIVATE; pAct->sequence = ++Ctx->fwcmdseq; pAct->channelId = Ctx->OpenRsp.channelId; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsActChannel: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } pActRsp = (DecRspChannelActivate*)&pIocData->u.fwCmd.rsp; if(pActRsp->status){ DebugLog_Trace(LDIL_DBG,"DtsActChannel: ChannelActivate Failed %d\n",pActRsp->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWSetSingleField( HANDLE hDevice, bool bSingleField ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelSingleField *pAct; DecRspChannelSingleField *pActRsp; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->State == BC_DEC_STATE_CLOSE) { DebugLog_Trace(LDIL_DBG,"DtsFWSetSingleField: Channel Not Opened\n"); return BC_STS_DEC_NOT_OPEN; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; pAct = (DecCmdChannelSingleField *)&pIocData->u.fwCmd.cmd; pAct->command = eCMD_C011_DEC_CHAN_SET_SINGLE_FIELD; pAct->sequence = ++Ctx->fwcmdseq; pAct->channelId = Ctx->OpenRsp.channelId; pAct->SingleField = bSingleField; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFWSetSingleField: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } pActRsp = (DecRspChannelSingleField*)&pIocData->u.fwCmd.rsp; if(pActRsp->status){ DebugLog_Trace(LDIL_DBG,"DtsFWSetSingleField: Set Single Field Failed %d\n",pActRsp->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWHwSelfTest( HANDLE hDevice, uint32_t testID ) { BC_STATUS sts = BC_STS_SUCCESS; C011CmdSelfTest *stest=NULL; C011RspSelfTest *pRsp = NULL; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; stest = (C011CmdSelfTest *)&pIocData->u.fwCmd.cmd; stest->command = eCMD_C011_SELF_TEST; stest->sequence = ++Ctx->fwcmdseq; stest->testId = (eC011_TEST_ID)testID; if(Ctx->DevId==BC_PCI_DEVID_FLEA) { if (testID>3 || testID<6){ stest->mode = testID; stest->height = Ctx->HWOutPicHeight; stest->width = Ctx->HWOutPicWidth; } } if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsHwSelfTest: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } pRsp = (C011RspSelfTest*)&pIocData->u.fwCmd.rsp; if(pRsp->status){ DebugLog_Trace(LDIL_DBG,"DtsHwSelfTest: SetVideoOut Failed %d\n",pRsp->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWVersion( HANDLE hDevice, uint32_t *Stream, uint32_t *DecCore, uint32_t *HwNumber ) { BC_STATUS sts = BC_STS_SUCCESS; C011CmdGetVersion *ver=NULL; C011RspGetVersion *pRsp = NULL; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(!Stream || !DecCore || !HwNumber) { DebugLog_Trace(LDIL_DBG,"DtsFWVersion: Invalid Handle\n"); return BC_STS_INV_ARG; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; ver = (C011CmdGetVersion *)&pIocData->u.fwCmd.cmd; ver->command = eCMD_C011_GET_VERSION; ver->sequence = ++Ctx->fwcmdseq; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFWVersion: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } pRsp = (C011RspGetVersion*)&pIocData->u.fwCmd.rsp; if(pRsp->status){ DebugLog_Trace(LDIL_DBG,"DtsHwSelfTest: SetVideoOut Failed %d\n",pRsp->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } *Stream = pRsp->streamSwVersion; *DecCore = pRsp->decoderSwVersion; *HwNumber = pRsp->chipHwVersion; DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWFifoStatus( HANDLE hDevice, uint32_t *CpbSize, uint32_t *CpbFullness ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelStatus *pCmd=NULL; DecRspChannelStatus *pRsp = NULL; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->State == BC_DEC_STATE_CLOSE){ DebugLog_Trace(LDIL_DBG,"DtsFifoStatus: No Open Decoder\n"); return BC_STS_DEC_NOT_OPEN; } if(!CpbSize || !CpbFullness) { DebugLog_Trace(LDIL_DBG,"DtsFifoStatus: Invalid Args\n"); return BC_STS_INV_ARG; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; pCmd = (DecCmdChannelStatus *)&pIocData->u.fwCmd.cmd; pCmd->command = eCMD_C011_DEC_CHAN_STATUS; pCmd->sequence = ++Ctx->fwcmdseq; pCmd->channelId = Ctx->OpenRsp.channelId; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1, pIocData, FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsChannelStatus: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } pRsp = (DecRspChannelStatus*)&pIocData->u.fwCmd.rsp; if(pRsp->status){ DebugLog_Trace(LDIL_DBG,"DtsChannelStatus: Failed %d\n",pRsp->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } *CpbSize = pRsp->cpbSize; *CpbFullness = pRsp->cpbFullness; DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWCloseChannel( HANDLE hDevice, uint32_t ChannelID ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelClose *pCmd; DecRspChannelClose *pRsp; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->State == BC_DEC_STATE_CLOSE) { DebugLog_Trace(LDIL_DBG,"DtsCloseDecoder: Channel is not Open\n"); return BC_STS_SUCCESS; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; pCmd = ((DecCmdChannelClose*)&pIocData->u.fwCmd.cmd); pCmd->command = eCMD_C011_DEC_CHAN_CLOSE; pCmd->sequence = ++Ctx->fwcmdseq; //pCmd->channelId = Ctx->OpenRsp.channelId; pCmd->channelId = ChannelID; pCmd->pictureRelease = eC011_PIC_REL_INTERNAL; pCmd->lastPicDisplay = eC011_LASTPIC_DISPLAY_ON; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsCloseDecoder: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } pRsp = (DecRspChannelClose*)&pIocData->u.fwCmd.rsp; if(pRsp->status){ DebugLog_Trace(LDIL_DBG,"DtsCloseDecoder: Failed %d\n",pRsp->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } memset(&Ctx->OpenRsp,0,sizeof(Ctx->OpenRsp)); DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWSetVideoInput( HANDLE hDevice ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelSetInputParams *vi=NULL; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if((Ctx->State == BC_DEC_STATE_CLOSE)){ DebugLog_Trace(LDIL_DBG,"DtsSetVideoInput: Channel not opened\n"); return BC_STS_DEC_NOT_OPEN; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; vi = (DecCmdChannelSetInputParams*)&pIocData->u.fwCmd.cmd; vi->command = eCMD_C011_DEC_CHAN_INPUT_PARAMS; vi->sequence = ++Ctx->fwcmdseq; vi->syncMode = eC011_SYNC_MODE_SYNCPIN; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsSetVideoInput: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } if(pIocData->u.fwCmd.rsp[2]){ DebugLog_Trace(LDIL_DBG,"DtsSetVideoInput: SetInputParameters Failed %d\n",pIocData->u.fwCmd.rsp[2]); sts = BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return sts; } DRVIFLIB_INT_API BC_STATUS DtsFWSetVideoPID( HANDLE hDevice, uint32_t pid ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelSetTSPIDs *spid=NULL; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if((Ctx->State == BC_DEC_STATE_CLOSE)) { DebugLog_Trace(LDIL_DBG,"DtsFWSetVideoPID: Channel not opened\n"); return BC_STS_DEC_NOT_OPEN; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; spid = (DecCmdChannelSetTSPIDs*)&pIocData->u.fwCmd.cmd; spid->command = eCMD_C011_DEC_CHAN_TS_PIDS; spid->sequence = ++Ctx->fwcmdseq; spid->channelId = Ctx->OpenRsp.channelId; spid->videoPid = pid; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFWSetVideoPID: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } if(pIocData->u.fwCmd.rsp[2]){ DebugLog_Trace(LDIL_DBG,"DtsFWSetVideoPID: Failed %d\n",pIocData->u.fwCmd.rsp[2]); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWFlushDecoder( HANDLE hDevice, uint32_t rsrv ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelFlush *fl; DecRspChannelFlush *flRsp; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->State == BC_DEC_STATE_CLOSE) { DebugLog_Trace(LDIL_DBG,"DtsFlushDecoder: Channel Not Opened\n"); return BC_STS_DEC_NOT_OPEN; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; fl = (DecCmdChannelFlush *)&pIocData->u.fwCmd.cmd; fl->command = eCMD_C011_DEC_CHAN_FLUSH; fl->sequence = ++Ctx->fwcmdseq; fl->channelId = Ctx->OpenRsp.channelId; fl->flushMode = eC011_FLUSH_PROC_POINT_RESET_TS; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFlushDecoder: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } flRsp = (DecRspChannelFlush*)&pIocData->u.fwCmd.rsp; if(flRsp->status){ DebugLog_Trace(LDIL_DBG,"DtsFlushDecoder: Flush Decoder Failed %d\n",flRsp->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWStartVideo( HANDLE hDevice, uint32_t videoAlg, uint32_t FGTEnable, uint32_t MetaDataEnable, uint32_t Progressive, uint32_t OptFlags ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelStartVideo *sVid; DecRspChannelStartVideo *sVidRsp; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->State == BC_DEC_STATE_CLOSE) { DebugLog_Trace(LDIL_DBG,"DtsStartVideo: Channel Not Opened\n"); return BC_STS_DEC_NOT_OPEN; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; sVid = (DecCmdChannelStartVideo *)&pIocData->u.fwCmd.cmd; sVid->command = eCMD_C011_DEC_CHAN_START_VIDEO; sVid->sequence = ++Ctx->fwcmdseq; sVid->channelId = Ctx->OpenRsp.channelId; sVid->outVidPort = eC011_OUT_PORT0; sVid->maxPicSize = eC011_MAX_PICSIZE_HD; sVid->outCtrlMode = eC011_OUTCTRL_VIDEO_TIMING; sVid->chanType = eC011_CHANNEL_PLAYBACK; sVid->videoAlg = (eC011_VIDEO_ALG)videoAlg; sVid->sourceMode = eC011_VIDSRC_DEFAULT_PROGRESSIVE; sVid->pulldown = eC011_PULLDOWN_DEFAULT_32; if(Ctx->RegCfg.DbgOptions & BC_BIT(6) ){ /* PIB in regular DEL/RELQ scheme. */ sVid->picInfo = eC011_PICTURE_INFO_ON; }else { /* PIB embedded with in the frame */ sVid->picInfo = eC011_PICTURE_INFO_OFF; } sVid->displayOrder = eC011_DISPLAY_ORDER_DISPLAY; sVid->streamId = 0; sVid->vcxoControl = eC011_EXTERNAL_VCXO_OFF; sVid->enableFgt = FGTEnable; sVid->enable23_297FrameRateOutput = Progressive; sVid->displayTiming = eC011_DISPLAY_TIMING_IGNORE_PTS; //Line 21 Closed Caption sVid->userDataMode = eC011_USER_DATA_MODE_ON; sVid->defaultFrameRate = (OptFlags&0x0f); sVid->decOperationMode = (OptFlags&0x30)>>4; sVid->MaxFrameRateMode = (OptFlags&0x40)>>6 | (OptFlags&0x80)>>6; // Bit 1 is used to indicate to ignore pulldown in the firmware. if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsStartVideo: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } sVidRsp = (DecRspChannelStartVideo*)&pIocData->u.fwCmd.rsp; if(sVidRsp->status){ DebugLog_Trace(LDIL_DBG,"DtsStartVideo: StartVideo Failed %d\n",sVidRsp->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } memcpy(&Ctx->sVidRsp,sVidRsp,sizeof(Ctx->sVidRsp)); Ctx->State = BC_DEC_STATE_START; DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWStopVideo( HANDLE hDevice, uint32_t ChannelId, bool ForceStop ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelStopVideo *sVid; DecRspChannelStopVideo *sVidRsp; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(!(ForceStop) && (Ctx->State != BC_DEC_STATE_START) && (Ctx->State != BC_DEC_STATE_PAUSE) && (Ctx->State != BC_DEC_STATE_FLUSH)) { DebugLog_Trace(LDIL_DBG,"DtsStopVideo: Channel Not Opened\n"); return BC_STS_DEC_NOT_STARTED; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; sVid = (DecCmdChannelStopVideo *)&pIocData->u.fwCmd.cmd; sVid->command = eCMD_C011_DEC_CHAN_STOP_VIDEO; sVid->sequence = ++Ctx->fwcmdseq; //sVid->channelId = Ctx->OpenRsp.channelId; sVid->channelId = ChannelId; sVid->pictureRelease= eC011_PIC_REL_INTERNAL; sVid->lastPicDisplay= eC011_LASTPIC_DISPLAY_ON; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsStopVideo: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } sVidRsp = (DecRspChannelStopVideo*)&pIocData->u.fwCmd.rsp; if(sVidRsp->status){ DebugLog_Trace(LDIL_DBG,"DtsStopVideo: StopVideo Failed %d\n",sVidRsp->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } Ctx->State = BC_DEC_STATE_STOP; DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWDecFlushChannel( HANDLE hDevice, uint32_t Operation ) { BC_STATUS sts = BC_STS_SUCCESS; uint32_t i = 10; DecCmdChannelFlush *cFlush; DecRspChannelFlush *rspFlush; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if (Ctx->State == BC_DEC_STATE_CLOSE) { return BC_STS_DEC_NOT_OPEN; } if( (Operation <0) || (Operation > 2) ) return BC_STS_INV_ARG; if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; cFlush = (DecCmdChannelFlush *)&pIocData->u.fwCmd.cmd; cFlush->command = eCMD_C011_DEC_CHAN_FLUSH; cFlush->sequence = ++Ctx->fwcmdseq; cFlush->channelId = Ctx->OpenRsp.channelId; cFlush->flushMode = (eC011_FLUSH_MODE)Operation; do { if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFWDecFlushChannel: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } rspFlush = (DecRspChannelFlush*)&pIocData->u.fwCmd.rsp; if (Ctx->State != BC_DEC_STATE_START && Ctx->State != BC_DEC_STATE_PAUSE) break; bc_sleep_ms(5); if(0 == i--) break; // Only try to FLUSH the decoder 10 times. Not hang infinitely if the FW is stuck } while (rspFlush->status == BC_FW_CMD_TIMEOUT); if(rspFlush->status){ DebugLog_Trace(LDIL_DBG,"DtsFWDecFlushChannel: FlushChannel Failed %d\n",rspFlush->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWPauseVideo( HANDLE hDevice, uint32_t Operation ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelPause *cPause; DecRspChannelPause *rspPause; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->State == BC_DEC_STATE_CLOSE) { DebugLog_Trace(LDIL_DBG,"DtsFWPauseVideo: Channel is NOT Opened\n"); return BC_STS_DEC_NOT_OPEN; } if(Ctx->State == BC_DEC_STATE_STOP) { DebugLog_Trace(LDIL_DBG,"DtsFWPauseVideo: Channel is already Opened\n"); return BC_STS_DEC_NOT_STARTED; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; cPause = (DecCmdChannelPause *)&pIocData->u.fwCmd.cmd; cPause->command = eCMD_C011_DEC_CHAN_PAUSE; cPause->sequence = ++Ctx->fwcmdseq; cPause->channelId = Ctx->OpenRsp.channelId; cPause->enableState = (eC011_PAUSE_MODE)Operation; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFWPauseVideo: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } rspPause = (DecRspChannelPause*)&pIocData->u.fwCmd.rsp; if(rspPause->status){ DebugLog_Trace(LDIL_DBG,"DtsFWPauseVideo: PauseChannel Failed %d\n",rspPause->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWSetTrickPlay( HANDLE hDevice, uint32_t trickMode, uint8_t direction ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelTrickPlay *cTrickPlay; DecRspChannelTrickPlay *rspTrickPlay; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; cTrickPlay = (DecCmdChannelTrickPlay *)&pIocData->u.fwCmd.cmd; cTrickPlay->command = eCMD_C011_DEC_CHAN_TRICK_PLAY; cTrickPlay->sequence = ++Ctx->fwcmdseq; cTrickPlay->channelId = Ctx->OpenRsp.channelId; cTrickPlay->direction = (eC011_DIR)direction; cTrickPlay->speed = (eC011_SPEED)trickMode; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFWSetTrickPlay: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } rspTrickPlay = (DecRspChannelTrickPlay*)&pIocData->u.fwCmd.rsp; if(rspTrickPlay->status){ DebugLog_Trace(LDIL_DBG,"DtsFWSetTrickPlay: TrickPlay Failed %d\n",rspTrickPlay->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWSetHostTrickMode( HANDLE hDevice, uint32_t enable ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelSetHostTrickMode *cHostTrickMode; DecRspChannelSetHostTrickMode *rspHostTrickMode; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if (Ctx->DevId == BC_PCI_DEVID_FLEA) return BC_STS_SUCCESS; if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; cHostTrickMode = (DecCmdChannelSetHostTrickMode *)&pIocData->u.fwCmd.cmd; cHostTrickMode->command = eCMD_C011_DEC_CHAN_SET_HOST_TRICK_MODE; cHostTrickMode->sequence = ++Ctx->fwcmdseq; cHostTrickMode->channelId = Ctx->OpenRsp.channelId; cHostTrickMode->enable = enable; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFWSetHostTrickMode: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } rspHostTrickMode = (DecRspChannelSetHostTrickMode*)&pIocData->u.fwCmd.rsp; if(rspHostTrickMode->status){ DebugLog_Trace(LDIL_DBG,"DtsFWSetHostTrickMode: Failed %d\n",rspHostTrickMode->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWSetFFRate( HANDLE hDevice, uint32_t Rate ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelSetFFRate *cFFRate; DecRspChannelSetFFRate *rspFFRate; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; cFFRate = (DecCmdChannelSetFFRate *)&pIocData->u.fwCmd.cmd; cFFRate->command = eCMD_C011_DEC_CHAN_SET_FF_RATE; cFFRate->sequence = ++Ctx->fwcmdseq; cFFRate->channelId = Ctx->OpenRsp.channelId; cFFRate->rate = Rate; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFWSetFFRate: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } rspFFRate = (DecRspChannelSetFFRate*)&pIocData->u.fwCmd.rsp; if(rspFFRate->status){ DebugLog_Trace(LDIL_DBG,"DtsFWSetFFRate: SetFFRate Failed %d\n",rspFFRate->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWSetSlowMotionRate( HANDLE hDevice, uint32_t Rate ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelSetSlowMotionRate *cSMRate; DecRspChannelSetSlowMotionRate *rspSMRate; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if (Ctx->DevId == BC_PCI_DEVID_FLEA) return BC_STS_SUCCESS; if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; cSMRate = (DecCmdChannelSetSlowMotionRate *)&pIocData->u.fwCmd.cmd; cSMRate->command = eCMD_C011_DEC_CHAN_SET_SLOWM_RATE; cSMRate->sequence = ++Ctx->fwcmdseq; cSMRate->channelId = Ctx->OpenRsp.channelId; cSMRate->rate = Rate; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFWSetFFRate: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } rspSMRate = (DecRspChannelSetSlowMotionRate*)&pIocData->u.fwCmd.rsp; if(rspSMRate->status){ DebugLog_Trace(LDIL_DBG,"DtsFWSetFFRate: SetSMRate Failed %d\n",rspSMRate->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWSetSkipPictureMode( HANDLE hDevice, uint32_t SkipMode ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelSetSkipPictureMode *cSkipPictureMode; DecRspChannelSetSkipPictureMode *rspSkipPictureMode; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; cSkipPictureMode = (DecCmdChannelSetSkipPictureMode *)&pIocData->u.fwCmd.cmd; cSkipPictureMode->command = eCMD_C011_DEC_CHAN_SET_SKIP_PIC_MODE; cSkipPictureMode->sequence = ++Ctx->fwcmdseq; cSkipPictureMode->channelId = Ctx->OpenRsp.channelId; cSkipPictureMode->skipMode = (eC011_SKIP_PIC_MODE)SkipMode; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFWSetSkipPictureMode: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } rspSkipPictureMode = (DecRspChannelSetSkipPictureMode*)&pIocData->u.fwCmd.rsp; if(rspSkipPictureMode->status){ DebugLog_Trace(LDIL_DBG,"DtsFWSetSkipPictureMode: SkipPictureMode Failed %d\n",rspSkipPictureMode->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWFrameAdvance( HANDLE hDevice ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelFrameAdvance *cFrameAdvance; DecRspChannelFrameAdvance *rspFrameAdvance; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; cFrameAdvance = (DecCmdChannelFrameAdvance *)&pIocData->u.fwCmd.cmd; cFrameAdvance->command = eCMD_C011_DEC_CHAN_FRAME_ADVANCE; cFrameAdvance->sequence = ++Ctx->fwcmdseq; cFrameAdvance->channelId = Ctx->OpenRsp.channelId; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFWFrameAdvance: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } rspFrameAdvance = (DecRspChannelFrameAdvance*)&pIocData->u.fwCmd.rsp; if(rspFrameAdvance->status){ DebugLog_Trace(LDIL_DBG,"DtsFWFrameAdvance: Failed %d\n",rspFrameAdvance->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWSetContentKeys( HANDLE hDevice, uint8_t *buffer, uint32_t Length, uint32_t flags ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdSetContentKey *cKeys; DecRspSetContentKey *rspcKeys; uint8_t *temp=NULL; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(!buffer || (Length > ((BC_MAX_FW_CMD_BUFF_SZ*sizeof(uint32_t)) - 16) ) ){ return BC_STS_INV_ARG; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; cKeys = (DecCmdSetContentKey *)&pIocData->u.fwCmd.cmd; cKeys->command = eCMD_C011_DEC_CHAN_SET_CONTENT_KEY; cKeys->sequence = ++Ctx->fwcmdseq; cKeys->channelId = Ctx->OpenRsp.channelId; cKeys->flags = flags; if(Ctx->FixFlags & DTS_ADAPTIVE_OUTPUT_PER) cKeys->flags |= BC_BIT(17); temp = ((uint8_t *)cKeys) + 16; memcpy(temp, buffer, Length); if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFWSetFFRate: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } rspcKeys = (DecRspSetContentKey*)&pIocData->u.fwCmd.rsp; if(rspcKeys->status){ DebugLog_Trace(LDIL_DBG,"DtsFWSetContentKeys: Failed %d\n",rspcKeys->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWSetSessionKeys( HANDLE hDevice, uint8_t *buffer, uint32_t Length, uint32_t flags ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdSetSessionKey *sKey; DecRspSetSessionKey *rspsKey; uint8_t *temp=NULL; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(!buffer || (Length > ((BC_MAX_FW_CMD_BUFF_SZ*sizeof(uint32_t)) - 16) ) ){ return BC_STS_INV_ARG; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; sKey = (DecCmdSetSessionKey *)&pIocData->u.fwCmd.cmd; sKey->command = eCMD_C011_DEC_CHAN_SET_SESSION_KEY; sKey->sequence = ++Ctx->fwcmdseq; sKey->channelId = Ctx->OpenRsp.channelId; sKey->flags = flags; temp = ((uint8_t *)sKey) + 16; memcpy(temp, buffer, Length); if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFWSetFFRate: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } rspsKey = (DecRspSetSessionKey*)&pIocData->u.fwCmd.rsp; if(rspsKey->status){ DebugLog_Trace(LDIL_DBG,"DtsFWSetSessionKey: Failed %d\n",rspsKey->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } BC_STATUS DtsFormatChangeAck(HANDLE hDevice, uint32_t flags) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdFormatChangeAck *Ack; DecRspFormatChangeAck *rspAck; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if (!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; Ack = (DecCmdFormatChangeAck *) &pIocData->u.fwCmd.cmd; Ack->command = eCMD_C011_DEC_CHAN_FMT_CHANGE_ACK; Ack->sequence = ++Ctx->fwcmdseq; Ack->channelId = Ctx->OpenRsp.channelId; Ack->flags = flags; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFormatChangeAck: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } rspAck = (DecRspFormatChangeAck*) &pIocData->u.fwCmd.rsp; if(rspAck->status){ DebugLog_Trace(LDIL_DBG,"DtsFormatChangeAck: Failed %d\n",rspAck->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFWDrop( HANDLE hDevice, uint32_t Pictures ) { BC_STATUS sts = BC_STS_SUCCESS; DecCmdChannelDrop *cDrop; DecRspChannelDrop *rspDrop; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->State == BC_DEC_STATE_CLOSE) { DebugLog_Trace(LDIL_DBG,"DtsFWDrop: Channel is not Open\n"); return BC_STS_DEC_NOT_OPEN; } if(Ctx->State == BC_DEC_STATE_STOP) { DebugLog_Trace(LDIL_DBG,"DtsFWDrop: Channel is not Start\n"); return BC_STS_DEC_NOT_STARTED; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; cDrop = (DecCmdChannelDrop *)&pIocData->u.fwCmd.cmd; cDrop->command = eCMD_C011_DEC_CHAN_DROP; cDrop->sequence = ++Ctx->fwcmdseq; cDrop->channelId = Ctx->OpenRsp.channelId; cDrop->numPicDrop = Pictures; cDrop->dropType = eC011_DROP_TYPE_DECODER; // Do not skip reference types. if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FW_CMD,1,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFWDrop: Ioctl failed: %d\n",sts); DtsRelIoctlData(Ctx,pIocData); return sts; } rspDrop = (DecRspChannelDrop*)&pIocData->u.fwCmd.rsp; if(rspDrop->status){ DebugLog_Trace(LDIL_DBG,"DtsFWDrop: Drop Failed %d\n",rspDrop->status); DtsRelIoctlData(Ctx,pIocData); return BC_STS_FW_CMD_ERR; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/libcrystalhd_if.cpp0000644000175000017500000022273211610313111026054 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_if.cpp * * Description: Driver Interface API. * * AU * * HISTORY: * ******************************************************************** * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #include #include #include #include #include #include #include "7411d.h" #include "libcrystalhd_version.h" #include "bc_decoder_regs.h" #include "libcrystalhd_if.h" #include "libcrystalhd_priv.h" #include "libcrystalhd_int_if.h" #include "libcrystalhd_fwcmds.h" #include "libcrystalhd_fwload_if.h" #if (!__STDC_WANT_SECURE_LIB__) inline bool memcpy_s(void *dest, size_t sizeInBytes, void *src, size_t count) { bool status = false; if (count > sizeInBytes) { DebugLog_Trace(LDIL_DBG,"memcpy_s: buffer overflow\n"); } else { memcpy(dest, src, count); status = true; } return(status); } inline bool memmove_s(void *dest, size_t sizeInBytes, void *src, size_t count) { bool status = false; if (count > sizeInBytes) { DebugLog_Trace(LDIL_DBG,"memmove_s: buffer overflow\n"); } else { memmove(dest, src, count); status = true; } return(status); } #endif // Full TS packet of EOS static __attribute__((aligned(4))) uint8_t eos_mpeg[184] = { 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7, 0x00, 0x00, 0x01, 0xb7 }; static __attribute__((aligned(4))) uint8_t eos_avc_vc1[184] = { 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a, 0x00, 0x00, 0x01, 0x0a }; static __attribute__((aligned(4))) uint8_t eos_vc1_spmp_link[32] = { 0x5a, 0x5a, 0x5a, 0x5a, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x05, 0x5a, 0x5a, 0x5a, 0x5a, 0x0d, 0x00, 0x00, 0x01, 0x0a, 0xe0, 0x55, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 }; static __attribute__((aligned(4))) uint8_t eos_divx[184] = { 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x01, 0xb1 }; static __attribute__((aligned(4))) uint8_t btp_video_done_es_private[] = { /* 0x81, 0x01, 0x14, 0x80,*/ 0x42, 0x52, 0x43, 0x4D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 /*, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00,*/ }; static __attribute__((aligned(4))) uint8_t btp_video_done_es[] = { /*0x81, 0x01, 0x14, 0x80, 0x42, 0x52, 0x43, 0x4D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF,*/ 0x00, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAA, 0xBB, 0xCC, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xBC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; #if 0 static __attribute__((aligned(4))) uint8_t btp_video_plunge_es[] = { /*0x81, 0x01, 0x14, 0x80, 0x42, 0x52, 0x43, 0x4D, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF,*/ 0x00, 0x00, 0x00, 0x00, 0x0A, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xAA, 0xBB, 0xCC, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xBC, 0xAA, 0xBB, 0xCC, 0xDD, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF }; #endif static __attribute__((aligned(4))) uint8_t ExtData[] = { 0x00, 0x00}; BC_STATUS DtsSetupHardware(HANDLE hDevice, BOOL IgnClkChk) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx; DTS_GET_CTX(hDevice,Ctx); if( !IgnClkChk){ if(Ctx->DevId == BC_PCI_DEVID_LINK || Ctx->DevId == BC_PCI_DEVID_FLEA){ if(DtsGetHwInitSts() != BC_DIL_HWINIT_NOT_YET){ DebugLog_Trace(LDIL_DBG," HW init already?\n"); return BC_STS_SUCCESS; } } } DtsSetHwInitSts(BC_DIL_HWINIT_IN_PROGRESS); if (Ctx->DevId == BC_PCI_DEVID_LINK) sts = DtsPushAuthFwToLink(hDevice,NULL); else if (Ctx->DevId == BC_PCI_DEVID_FLEA) sts = DtsPushFwToFlea(hDevice,NULL); else { DebugLog_Trace(LDIL_DBG,"HW Type not found\n"); return BC_STS_ERROR; } if(sts != BC_STS_SUCCESS){ return sts; } /* Initialize Firmware interface */ sts = DtsFWInitialize(hDevice,0); if (sts == BC_STS_SUCCESS) DtsSetHwInitSts(BC_DIL_HWINIT_DONE); else DtsSetHwInitSts(BC_DIL_HWINIT_NOT_YET); return sts; } static BC_STATUS DtsReleaseChannel(HANDLE hDevice, uint32_t ChannelID, bool Stop) { BC_STATUS sts = BC_STS_SUCCESS; if(Stop){ sts = DtsFWStopVideo(hDevice, ChannelID, true); if(sts != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsReleaseChannel: StopVideoFailed Ignoring error\n"); } } sts = DtsFWCloseChannel(hDevice, ChannelID); if(sts != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsReleaseChannel: DtsFWCloseChannel Failed\n"); } return sts; } static BC_STATUS DtsRecoverableDecOpen(HANDLE hDevice,uint32_t StreamType) { BC_STATUS sts = BC_STS_SUCCESS; uint32_t retry = 3; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; if (Ctx->DevId == BC_PCI_DEVID_FLEA) { sts = DtsFWOpenChannel(hDevice, StreamType, 0); if(sts == BC_STS_SUCCESS) { /*For Multiapplication support this will change.*/ if(Ctx->OpenRsp.channelId != 0) sts = BC_STS_FW_CMD_ERR; } return sts; } while(retry--){ sts = DtsFWOpenChannel(hDevice, StreamType, 0); if(sts == BC_STS_SUCCESS){ if(Ctx->OpenRsp.channelId == 0){ break; }else{ DebugLog_Trace(LDIL_DBG,"DtsFWOpenChannel: ChannelID leakage..\n"); /* First Release the Current Channel.*/ DtsReleaseChannel(hDevice,Ctx->OpenRsp.channelId, FALSE); /* Fall through to release the previous Channel */ sts = BC_STS_FW_CMD_ERR; } } if((sts == BC_STS_TIMEOUT) || (retry == 1) ){ /* Do Full initialization */ sts = DtsSetupHardware(hDevice,TRUE); if(sts != BC_STS_SUCCESS) break; /* Setup The Clock Again */ sts = DtsSetVideoClock(hDevice,0); if(sts != BC_STS_SUCCESS ) break; }else{ sts = DtsReleaseChannel(hDevice,0,TRUE); if(sts != BC_STS_SUCCESS) break; } } return sts; } //===================================Externs ============================================ extern BOOL glob_mode_valid; DRVIFLIB_API BC_STATUS DtsDeviceOpen( HANDLE *hDevice, uint32_t mode ) { int drvHandle=1; BC_STATUS Sts=BC_STS_SUCCESS; uint32_t globMode = 0; uint8_t nTry=1; uint32_t VendorID, DeviceID, RevID, FixFlags, drvMode; uint32_t drvVer, dilVer; uint32_t fwVer, decVer, hwVer; pid_t processID; int shmid=0; DebugLog_Trace(LDIL_DBG,"Running DIL (%d.%d.%d) Version\n", DIL_MAJOR_VERSION,DIL_MINOR_VERSION,DIL_REVISION ); processID = getpid(); FixFlags = mode; mode &= 0xFF; Sts = DtsCreateShMem(&shmid); if(BC_STS_SUCCESS !=Sts) return Sts; if (mode != DTS_MONITOR_MODE && DtsIsDecOpened(processID)) { DebugLog_Trace(LDIL_DBG, "DtsDeviceOpen: Decoder is already opened\n"); DtsDelDilShMem(); return BC_STS_DEC_EXIST_OPEN; } DebugLog_Trace(LDIL_DBG,"DtsDeviceOpen: Opening HW in mode %x\n", mode); /* For External API case, we support only Plyaback mode. */ if( !(BC_DTS_DEF_CFG & BC_EN_DIAG_MODE) && (mode != DTS_PLAYBACK_MODE) ){ DebugLog_Trace(LDIL_ERR,"DtsDeviceOpen: mode %d not supported\n",mode); DtsDelDilShMem(); return BC_STS_INV_ARG; } if(!glob_mode_valid) { globMode = DtsGetOPMode(); if(globMode&4) { globMode&=4; } DebugLog_Trace(LDIL_DBG,"DtsDeviceOpen: New globmode is %d \n",globMode); } else{ globMode = DtsGetOPMode(); } if (mode == DTS_HWINIT_MODE) DtsSetHwInitSts(BC_DIL_HWINIT_IN_PROGRESS); drvHandle =open(CRYSTALHD_API_DEV_NAME, O_RDWR); if(drvHandle < 0) { DebugLog_Trace(LDIL_ERR,"DtsDeviceOpen: Create File Failed\n"); DtsDelDilShMem(); return BC_STS_ERROR; } /* Initialize Internal Driver interfaces.. */ if( (Sts = DtsInitInterface(drvHandle,hDevice, mode)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_ERR,"DtsDeviceOpen: Interface Init Failed:%x\n",Sts); DtsReleaseInterface(DtsGetContext(*hDevice)); DtsDelDilShMem(); return Sts; } if( (Sts = DtsGetHwType(*hDevice,&DeviceID,&VendorID,&RevID))!=BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"Get Hardware Type Failed\n"); DtsReleaseInterface(DtsGetContext(*hDevice)); DtsDelDilShMem(); return Sts; } // set Ctx->DevId early, other depend on it DtsGetContext(*hDevice)->DevId = DeviceID; DtsSetgDevID(DeviceID); /* * Old layout link cards have issues w/a core clock of 200, so we use * 180 for all link cards, as we have no way to tell old layout from * new layout cards. */ DtsSetCoreClock(*hDevice, 180); /* * We have to specify the mode to the driver. * So the driver can cleanup only in case of * playback/Diag mode application close. */ if ((Sts = DtsGetVersion(*hDevice, &drvVer, &dilVer)) != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"Get drv ver failed\n"); DtsReleaseInterface(DtsGetContext(*hDevice)); DtsDelDilShMem(); return Sts; } /* If driver minor version is more than 13, enable DTS_SKIP_TX_CHK_CPB feature */ if (FixFlags & DTS_SKIP_TX_CHK_CPB) { if (((drvVer >> 16) & 0xFF) > 13) FixFlags |= DTS_SKIP_TX_CHK_CPB; } if (FixFlags & DTS_ADAPTIVE_OUTPUT_PER) { if(DtsGetContext(*hDevice)->DevId == BC_PCI_DEVID_FLEA) Sts = DtsGetFWVersion(*hDevice, &fwVer, &decVer, &hwVer, (char*)FWBINFILE_70015, 0); else Sts = DtsGetFWVersion(*hDevice, &fwVer, &decVer, &hwVer, (char*)FWBINFILE_70012, 0); if(Sts == BC_STS_SUCCESS) { if (fwVer >= ((14 << 16) | (8 << 8) | (1))) // 2.14.8.1 (ignore 2) FixFlags |= DTS_ADAPTIVE_OUTPUT_PER; else FixFlags &= (~DTS_ADAPTIVE_OUTPUT_PER); } } /* only enable dropping of repeated pictures for Adobe mode and MFT mode */ /* since we see corrupted video is some cases for non Adobe usage */ /* NAREN - This is a major hack since we have not root caused the corrupted video */ if(((FixFlags & DTS_SINGLE_THREADED_MODE) || (FixFlags & DTS_MFT_MODE)) && !(FixFlags & DTS_DIAG_TEST_MODE)) FixFlags |= DTS_PLAYBACK_DROP_RPT_MODE; /* If driver minor version is newer (for major == 2), send the fullMode */ if (((drvVer >> 24) & 0xFF) == 2) { if (((drvVer >> 16) & 0xFF) > 10) drvMode = FixFlags; else drvMode = mode; } else drvMode = FixFlags; if( (Sts = DtsNotifyOperatingMode(*hDevice,drvMode)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"Notify Operating Mode Failed\n"); DtsReleaseInterface(DtsGetContext(*hDevice)); DtsDelDilShMem(); return Sts; } /* Setup Hardware Specific Configuration */ DtsSetupConfig(DtsGetContext(*hDevice), DeviceID, RevID, FixFlags); /* Enable single threaded mode in the context */ if (FixFlags & DTS_SINGLE_THREADED_MODE) { DebugLog_Trace(LDIL_DBG,"Enable single threaded mode\n"); DtsGetContext(*hDevice)->SingleThreadedAppMode = 1; } if(mode == DTS_PLAYBACK_MODE){ globMode |= 0x1; } else if(mode == DTS_DIAG_MODE){ globMode |= 0x2; } else if(mode == DTS_MONITOR_MODE) { globMode |= 0x4; } else if(mode == DTS_HWINIT_MODE) { globMode |= 0x8; } else { globMode = 0; } DtsSetOPMode(globMode); if (DeviceID == BC_PCI_DEVID_LINK || DeviceID == BC_PCI_DEVID_FLEA) nTry = HARDWARE_INIT_RETRY_LINK_CNT; else nTry = HARDWARE_INIT_RETRY_CNT; if((mode == DTS_PLAYBACK_MODE)||(mode == DTS_HWINIT_MODE)) { while(nTry--) { Sts = DtsSetupHardware(*hDevice, FALSE); if(Sts == BC_STS_SUCCESS) { break; } else { DebugLog_Trace(LDIL_DBG,"DtsSetupHardware: Failed from Open\n"); bc_sleep_ms(100); } } if(Sts != BC_STS_SUCCESS ) { DtsReleaseInterface(DtsGetContext(*hDevice)); DtsDelDilShMem(); goto exit; } } if(mode == DTS_HWINIT_MODE){ DtsSetHwInitSts(0); } // Clear all stats before we start play back if(mode == DTS_PLAYBACK_MODE) { DtsRstDrvStat(*hDevice); } DtsGetContext(*hDevice)->ProcessID = processID; //DtsDevRegisterWr( hDevice,UartSelectA, 3); exit: return Sts; } DRVIFLIB_API BC_STATUS DtsDeviceClose( HANDLE hDevice ) { DTS_LIB_CONTEXT *Ctx; uint32_t globMode = 0; if(hDevice == NULL) return BC_STS_SUCCESS; DTS_GET_CTX(hDevice,Ctx); if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; if(Ctx->State != BC_DEC_STATE_CLOSE){ DtsCloseDecoder(hDevice); } DtsCancelFetchOutInt(Ctx); /* Unmask the mode */ globMode = DtsGetOPMode( ); // Make sure we are in playback mode before freeing up playback resources if(Ctx->OpMode == DTS_PLAYBACK_MODE) { DtsFlushRxCapture(hDevice,false); // Make sure that all buffers and DMA engines are freed up } if(Ctx->OpMode == DTS_PLAYBACK_MODE){ globMode &= (~0x1); } else if(Ctx->OpMode == DTS_DIAG_MODE){ globMode &= (~0x2); } else if(Ctx->OpMode == DTS_MONITOR_MODE) { globMode &= (~0x4); } else if(Ctx->OpMode == DTS_HWINIT_MODE) { globMode &= (~0x8); } else { globMode = 0; } DtsSetOPMode(globMode); DtsReleasePESConverter(hDevice); return DtsReleaseInterface(Ctx); } DRVIFLIB_API BC_STATUS DtsGetVersion( HANDLE hDevice, uint32_t *DrVer, uint32_t *DilVer ) { BC_VERSION_INFO *pVerInfo; BC_IOCTL_DATA *pIocData = NULL; DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_SUCCESS; DTS_GET_CTX(hDevice,Ctx); if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; pVerInfo = &pIocData->u.VerInfo; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_GET_VERSION,0,pIocData,FALSE)) != BC_STS_SUCCESS){ DtsRelIoctlData(Ctx,pIocData); DebugLog_Trace(LDIL_DBG,"DtsGetVersion: Ioctl failed: %d\n",sts); return sts; } *DrVer = (pVerInfo->DriverMajor << 24) | (pVerInfo->DriverMinor<<16) | pVerInfo->DriverRevision; *DilVer = (DIL_MAJOR_VERSION <<24)| (DIL_MINOR_VERSION<<16) | DIL_REVISION; DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } #define MAX_BIN_FILE_SZ 0x300000 DRVIFLIB_API BC_STATUS DtsGetFWVersionFromFile( HANDLE hDevice, uint32_t *StreamVer, uint32_t *DecVer, char *fname ) { BC_STATUS sts = BC_STS_SUCCESS; uint8_t *buf; //uint32_t buflen=0; uint32_t sizeRead=0; uint32_t err=0; FILE *fhnd =NULL; char fwfile[MAX_PATH+1]; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); sts = DtsGetDILPath(hDevice, fwfile, sizeof(fwfile)); if(sts != BC_STS_SUCCESS){ return sts; } if(fname){ strncat(fwfile,(const char*)fname,sizeof(fwfile)); }else{ if(Ctx->DevId == BC_PCI_DEVID_FLEA) strncat(fwfile,FWBINFILE_70015,sizeof(FWBINFILE_70015)); else strncat(fwfile,FWBINFILE_70012,sizeof(FWBINFILE_70012)); } if(!StreamVer){ DebugLog_Trace(LDIL_DBG,"\nDtsGetFWVersionFromFile: Null Pointer argument"); return BC_STS_INSUFF_RES; } fhnd = fopen((const char *)fwfile, "rb"); if(fhnd == NULL ){ DebugLog_Trace(LDIL_DBG,"DtsGetFWVersionFromFile:Failed to Open file Err\n"); return BC_STS_INSUFF_RES; } buf=(uint8_t *)malloc(MAX_BIN_FILE_SZ); if(buf==NULL) { DebugLog_Trace(LDIL_DBG,"DtsGetFWVersionFromFile:Failed to allocate memory\n"); return BC_STS_INSUFF_RES; } /* Read the FW bin file */ err = fread(buf, sizeof(uint8_t), MAX_BIN_FILE_SZ, fhnd); if(!err) { sizeRead = err; } if((err==0)&&(errno!=0)) { DebugLog_Trace(LDIL_DBG,"DtsGetFWVersionFromFile:Failed to read bin file %d\n",errno); if(buf)free(buf); fclose(fhnd); return BC_STS_ERROR; } //There is 16k hole in the FW binary. Hnece start searching from 16k in the bin file uint8_t *pSearchStr = &buf[0x4000]; *StreamVer =0; for(uint32_t i=0; i <(sizeRead-0x4000);i++){ if(NULL != strstr((char *)pSearchStr,(const char *)"Media_PC_FW_Rev")){ //The actual FW versions are at searchstring - 4 bytes. *StreamVer = ((*(pSearchStr-4)) << 16) | ((*(pSearchStr-3))<<8) | (*(pSearchStr-2)); break; } pSearchStr++; } if(buf) free(buf); if(fhnd) fhnd=NULL; if(*StreamVer ==0) return BC_STS_ERROR; else return BC_STS_SUCCESS; } DRVIFLIB_API BC_STATUS DtsGetFWVersion( HANDLE hDevice, uint32_t *StreamVer, uint32_t *DecVer, uint32_t *HwVer, char *fname, uint32_t flag ) { BC_STATUS sts; if(flag) //get runtime version by issuing a FWcmd { sts = DtsFWVersion(hDevice,StreamVer,DecVer,HwVer); if(sts == BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"FW Version: Stream: %x, Dec: %x, HW:%x\n",*StreamVer,*DecVer,*HwVer); } else { DebugLog_Trace(LDIL_DBG,"DtsGetFWVersion: failed to get version fromFW at runtime: %d\n",sts); return sts; } } else //read the stream arc version from binary { sts = DtsGetFWVersionFromFile(hDevice,StreamVer,DecVer,fname); if(sts == BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"FW Version: Stream: %x",*StreamVer); if(DecVer !=NULL) DebugLog_Trace(LDIL_DBG," Dec: %x\n",*DecVer); } else { DebugLog_Trace(LDIL_DBG,"DtsGetFWVersion: failed to get version from FW bin file: %d\n",sts); return sts; } } return BC_STS_SUCCESS; } DRVIFLIB_API BC_STATUS DtsOpenDecoder( HANDLE hDevice, uint32_t StreamType) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->State != BC_DEC_STATE_CLOSE) { if((sts = DtsCloseDecoder(hDevice)) != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG, "DtsOpenDecoder: DtsCloseDecoder Failed (sts:%d)\n", sts); return sts; } } Ctx->LastPicNum = -1; Ctx->LastSessNum = -1; Ctx->EOSCnt = 0; Ctx->DrvStatusEOSCnt = 0; Ctx->bEOSCheck = false; Ctx->bEOS = false; Ctx->CapState = 0; Ctx->hw_paused = false; Ctx->fw_cmd_issued = false; sts = DtsSetVideoClock(hDevice,0); if (sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"Failed to Set Video Clock:%x\n",sts); return sts; } if(Ctx->DevId == BC_PCI_DEVID_LINK) { // FIX_ME to support other stream types. sts = DtsSetTSMode(hDevice,0); if(sts != BC_STS_SUCCESS ) { return sts; } } if (Ctx->VidParams.MediaSubType != BC_MSUBTYPE_INVALID) StreamType = Ctx->VidParams.StreamType; else if (Ctx->DevId == BC_PCI_DEVID_FLEA) StreamType = BC_STREAM_TYPE_PES; sts = DtsRecoverableDecOpen(hDevice,StreamType); if(sts != BC_STS_SUCCESS ) { DebugLog_Trace(LDIL_DBG,"Dts Recoverable Open Failed:%x\n",sts); return sts; } sts = DtsFWSetVideoInput(hDevice); if(sts != BC_STS_SUCCESS ) { DebugLog_Trace(LDIL_DBG,"DtsFWSetVideoInput Failed:%x\n",sts); return sts; } Ctx->State = BC_DEC_STATE_STOP; DtsSetDecStat(true, Ctx->ProcessID); return BC_STS_SUCCESS; } DRVIFLIB_API BC_STATUS DtsStartDecoder( HANDLE hDevice ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; if (Ctx->State == BC_DEC_STATE_CLOSE) { DebugLog_Trace(LDIL_DBG,"DtsStartDecoder: Decoder is not opened\n"); return BC_STS_DEC_NOT_OPEN; } if( Ctx->State == BC_DEC_STATE_START) { if ((sts = DtsStopDecoder(hDevice)) != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG, "DtsStartDecoder: DtsStopDecoder FAILED (sts:%d)\n", sts); return sts; } } if(Ctx->VidParams.Progressive){ sts = DtsSetProgressive(hDevice,0); if(sts != BC_STS_SUCCESS ) { DebugLog_Trace(LDIL_DBG,"DtsSetProgressive: Failed [%x]\n",sts); return sts; } } sts = DtsFWActivateDecoder(hDevice); if(sts != BC_STS_SUCCESS ) { DebugLog_Trace(LDIL_DBG,"DtsFWActivateDecoder: Failed [%x]\n",sts); return sts; } sts = DtsFWStartVideo(hDevice, Ctx->VidParams.VideoAlgo, Ctx->VidParams.FGTEnable, Ctx->VidParams.MetaDataEnable, Ctx->VidParams.Progressive, Ctx->VidParams.OptFlags); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsFWStartVideo: Failed [%x]\n",sts); return sts; } Ctx->State = BC_DEC_STATE_START; return sts; } DRVIFLIB_API BC_STATUS DtsCloseDecoder( HANDLE hDevice ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; if(Ctx->State == BC_DEC_STATE_CLOSE) { return BC_STS_SUCCESS; } if (Ctx->State != BC_DEC_STATE_STOP) { DtsStopDecoder(hDevice); } sts = DtsFWCloseChannel(hDevice,Ctx->OpenRsp.channelId); /*if(sts != BC_STS_SUCCESS ) { return sts; }*/ DtsSetDecStat(false, Ctx->ProcessID); Ctx->State = BC_DEC_STATE_CLOSE; Ctx->LastPicNum = -1; Ctx->LastSessNum = -1; Ctx->EOSCnt = 0; Ctx->DrvStatusEOSCnt = 0; Ctx->bEOSCheck = false; Ctx->bEOS = false; // Ctx->InSampleCount = 0; /* Clear all pending lists.. */ DtsClrPendMdataList(Ctx); /* Close the Input dump File */ DumpInputSampleToFile(NULL,0); return sts; } DRVIFLIB_API BC_STATUS DtsSetVideoParams( HANDLE hDevice, uint32_t videoAlg, BOOL FGTEnable, BOOL MetaDataEnable, BOOL Progressive, uint32_t OptFlags ) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); Ctx->VidParams.VideoAlgo = videoAlg; Ctx->VidParams.FGTEnable = FGTEnable; Ctx->VidParams.MetaDataEnable = MetaDataEnable; Ctx->VidParams.Progressive = Progressive; //Ctx->VidParams.Reserved = rsrv; //Ctx->VidParams.FrameRate = FrameRate; Ctx->VidParams.OptFlags = OptFlags; // SingleThreadedAppMode is bit 7 of OptFlags if(OptFlags & 0x80) { Ctx->SingleThreadedAppMode = 1; // Hard code BD mode as well as max frame rate mode for Link Ctx->VidParams.OptFlags |= 0xD1; } else Ctx->SingleThreadedAppMode = 0; if (Ctx->DevId == BC_PCI_DEVID_FLEA || Ctx->VidParams.VideoAlgo == BC_VID_ALGO_VC1MP) Ctx->VidParams.StreamType = BC_STREAM_TYPE_PES; else Ctx->VidParams.StreamType = BC_STREAM_TYPE_ES; return BC_STS_SUCCESS; } DRVIFLIB_API BC_STATUS DtsSetInputFormat( HANDLE hDevice, BC_INPUT_FORMAT *pInputFormat ) { DTS_LIB_CONTEXT *Ctx = NULL; uint32_t videoAlgo = BC_VID_ALGO_H264; uint32_t ScaledWidth = 0; DTS_GET_CTX(hDevice,Ctx); Ctx->VidParams.MediaSubType = pInputFormat->mSubtype; Ctx->VidParams.WidthInPixels = pInputFormat->width; Ctx->VidParams.HeightInPixels = pInputFormat->height; if (pInputFormat->startCodeSz) Ctx->VidParams.StartCodeSz = pInputFormat->startCodeSz; else Ctx->VidParams.StartCodeSz = BRCM_START_CODE_SIZE; if (pInputFormat->metaDataSz) { if(Ctx->VidParams.pMetaData){ DebugLog_Trace(LDIL_DBG,"deleting buffer\n"); free(Ctx->VidParams.pMetaData); } Ctx->VidParams.pMetaData = (uint8_t*)malloc(pInputFormat->metaDataSz); memcpy(Ctx->VidParams.pMetaData, pInputFormat->pMetaData, pInputFormat->metaDataSz); Ctx->VidParams.MetaDataSz = pInputFormat->metaDataSz; } if(Ctx->VidParams.MediaSubType == BC_MSUBTYPE_H264 || Ctx->VidParams.MediaSubType== BC_MSUBTYPE_AVC1) { videoAlgo = BC_VID_ALGO_H264; } else if (Ctx->VidParams.MediaSubType==BC_MSUBTYPE_DIVX) { videoAlgo = BC_VID_ALGO_DIVX; } else if(Ctx->VidParams.MediaSubType == BC_MSUBTYPE_MPEG2VIDEO ) { videoAlgo = BC_VID_ALGO_MPEG2; } else if(Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WVC1 || Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMVA ||Ctx->VidParams.MediaSubType == BC_MSUBTYPE_VC1) { videoAlgo = BC_VID_ALGO_VC1; } else if (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMV3) { videoAlgo = BC_VID_ALGO_VC1MP; // Main Profile } if (Ctx->DevId == BC_PCI_DEVID_FLEA || Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMV3) Ctx->VidParams.StreamType = BC_STREAM_TYPE_PES; else Ctx->VidParams.StreamType = BC_STREAM_TYPE_ES; DtsSetVideoParams(hDevice, videoAlgo, pInputFormat->FGTEnable, pInputFormat->MetaDataEnable, pInputFormat->Progressive, pInputFormat->OptFlags); DtsSetPESConverter(hDevice); if(Ctx->DevId == BC_PCI_DEVID_FLEA) { if(Ctx->SingleThreadedAppMode) { pInputFormat->bEnableScaling = true; pInputFormat->ScalingParams.sWidth = 1280; } if(pInputFormat->bEnableScaling) { if((pInputFormat->ScalingParams.sWidth > 1920)|| (pInputFormat->ScalingParams.sWidth < 128)) ScaledWidth = 1280; else ScaledWidth = pInputFormat->ScalingParams.sWidth; Ctx->EnableScaling = (ScaledWidth << 20) | (ScaledWidth << 8) | pInputFormat->bEnableScaling; } else { Ctx->EnableScaling = 0; } Ctx->bEnable720pDropHalf = 0; } return DtsCheckProfile(hDevice); } DRVIFLIB_API BC_STATUS DtsGetVideoParams( HANDLE hDevice, uint32_t *videoAlg, BOOL *FGTEnable, BOOL *MetaDataEnable, BOOL *Progressive, uint32_t rsrv ) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if(!videoAlg || !FGTEnable || !MetaDataEnable || !Progressive) return BC_STS_INV_ARG; *videoAlg = Ctx->VidParams.VideoAlgo; *FGTEnable = Ctx->VidParams.FGTEnable; *MetaDataEnable = Ctx->VidParams.MetaDataEnable; *Progressive = Ctx->VidParams.Progressive; return BC_STS_SUCCESS; } DRVIFLIB_API BC_STATUS DtsFormatChange( HANDLE hDevice, uint32_t videoAlg, BOOL FGTEnable, BOOL MetaDataEnable, BOOL Progressive, uint32_t rsrv ) { return BC_STS_NOT_IMPL; } DRVIFLIB_API BC_STATUS DtsStopDecoder( HANDLE hDevice ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; if (Ctx->State == BC_DEC_STATE_CLOSE || Ctx->State == BC_DEC_STATE_STOP) { return BC_STS_SUCCESS; } // On LINK if the decoder is paused due to the RLL being full, un pause it before flush if(Ctx->DevId == BC_PCI_DEVID_LINK && Ctx->hw_paused) { DtsFWPauseVideo(hDevice,eC011_PAUSE_MODE_OFF); Ctx->hw_paused = false; } DtsCancelFetchOutInt(Ctx); sts = DtsFWStopVideo(hDevice,Ctx->OpenRsp.channelId, FALSE); sts = DtsFlushRxCapture(hDevice, false); Ctx->State = BC_DEC_STATE_STOP; return sts; } DRVIFLIB_API BC_STATUS DtsPauseDecoder( HANDLE hDevice ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; if (Ctx->State == BC_DEC_STATE_CLOSE) { DebugLog_Trace(LDIL_DBG, "DtsPauseDecoder: Decoder is not opened\n"); return BC_STS_DEC_NOT_OPEN; } if (Ctx->State == BC_DEC_STATE_STOP) { DebugLog_Trace(LDIL_DBG, "DtsPauseDecoder: Decoder is not started\n"); return BC_STS_DEC_NOT_STARTED; } if( Ctx->State == BC_DEC_STATE_PAUSE || Ctx->DevId == BC_PCI_DEVID_FLEA) { Ctx->State = BC_DEC_STATE_PAUSE; return BC_STS_SUCCESS; } sts = DtsFWPauseVideo(hDevice,eC011_PAUSE_MODE_ON); if(sts != BC_STS_SUCCESS ) { DebugLog_Trace(LDIL_DBG,"DtsPauseDecoder: Failed\n"); return sts; } Ctx->State = BC_DEC_STATE_PAUSE; return sts; } DRVIFLIB_API BC_STATUS DtsResumeDecoder( HANDLE hDevice ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; if (Ctx->State == BC_DEC_STATE_CLOSE) { DebugLog_Trace(LDIL_DBG, "DtsResumeDecoder: Decoder is not opened\n"); return BC_STS_DEC_NOT_OPEN; } if (Ctx->State == BC_DEC_STATE_STOP) { DebugLog_Trace(LDIL_DBG, "DtsResumeDecoder: Decoder is not started\n"); return BC_STS_DEC_NOT_STARTED; } if(Ctx->State == BC_DEC_STATE_START || Ctx->DevId == BC_PCI_DEVID_FLEA) { Ctx->State = BC_DEC_STATE_START; return BC_STS_SUCCESS; } sts = DtsFWPauseVideo(hDevice,eC011_PAUSE_MODE_OFF); if(sts != BC_STS_SUCCESS ) { return sts; } Ctx->State = BC_DEC_STATE_START; return sts; } DRVIFLIB_API BC_STATUS DtsSetVideoPID( HANDLE hDevice, uint32_t pid ) { return BC_STS_NOT_IMPL; } DRVIFLIB_API BC_STATUS DtsStartCaptureImmidiate(HANDLE hDevice, uint32_t Reserved) { DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; BC_STATUS sts = BC_STS_SUCCESS; //unused uint32_t Sz=0; DTS_GET_CTX(hDevice,Ctx); if(Ctx->State != BC_DEC_STATE_START) { DebugLog_Trace(LDIL_DBG, "DtsStartCaptureImmidiate: Decoder is not started\n"); return BC_STS_DEC_NOT_STARTED; } if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; if(Ctx->CfgFlags & BC_ADDBUFF_MOVE){ sts = DtsMapYUVBuffs(Ctx); if(sts != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsMapYUVBuffs failed Sts:%d\n",sts); return sts; } } // DebugLog_Trace(LDIL_DBG,"DbgOptions=%x\n", Ctx->RegCfg.DbgOptions); pIocData->u.RxCap.Rsrd = ST_CAP_IMMIDIATE; pIocData->u.RxCap.StartDeliveryThsh = RX_START_DELIVERY_THRESHOLD; pIocData->u.RxCap.PauseThsh = PAUSE_DECODER_THRESHOLD; pIocData->u.RxCap.ResumeThsh = RESUME_DECODER_THRESHOLD; // NAREN for Flea change the values dynamically for pause and resume if(Ctx->DevId == BC_PCI_DEVID_FLEA) { pIocData->u.RxCap.PauseThsh = Ctx->MpoolCnt - 2; pIocData->u.RxCap.ResumeThsh = FLEA_RT_PU_THRESHOLD; } if( (sts=DtsDrvCmd(Ctx,BCM_IOC_START_RX_CAP,0,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsStartCapture: Failed: %d\n",sts); } DtsRelIoctlData(Ctx,pIocData); return sts; } DRVIFLIB_API BC_STATUS DtsStartCapture(HANDLE hDevice) { DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; BC_STATUS sts = BC_STS_SUCCESS; //unused uint32_t Sz=0; DTS_GET_CTX(hDevice,Ctx); if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; if (Ctx->State != BC_DEC_STATE_START) { DebugLog_Trace(LDIL_DBG, "DtsStartCapture: Decoder is not started\n"); return BC_STS_DEC_NOT_STARTED; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; if(Ctx->CfgFlags & BC_ADDBUFF_MOVE){ sts = DtsMapYUVBuffs(Ctx); if(sts != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsMapYUVBuffs failed Sts:%d\n",sts); return sts; } } // DebugLog_Trace(LDIL_DBG,"DbgOptions=%x\n", Ctx->RegCfg.DbgOptions); pIocData->u.RxCap.Rsrd = NO_PARAM; pIocData->u.RxCap.StartDeliveryThsh = RX_START_DELIVERY_THRESHOLD; pIocData->u.RxCap.PauseThsh = PAUSE_DECODER_THRESHOLD; pIocData->u.RxCap.ResumeThsh = RESUME_DECODER_THRESHOLD; // NAREN for Flea change the values dynamically for pause and resume if(Ctx->DevId == BC_PCI_DEVID_FLEA) { pIocData->u.RxCap.PauseThsh = Ctx->MpoolCnt - 2; pIocData->u.RxCap.ResumeThsh = FLEA_RT_PU_THRESHOLD; } if( (sts=DtsDrvCmd(Ctx,BCM_IOC_START_RX_CAP,0,pIocData,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsStartCapture: Failed: %d\n",sts); } DtsRelIoctlData(Ctx,pIocData); return sts; } DRVIFLIB_API BC_STATUS DtsFlushRxCapture( HANDLE hDevice, BOOL bDiscardOnly) { DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS Sts; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if (!Ctx->bMapOutBufDone) { return BC_STS_SUCCESS; } if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; if (Ctx->State == BC_DEC_STATE_CLOSE) { return BC_STS_DEC_NOT_OPEN; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; pIocData->u.FlushRxCap.bDiscardOnly = bDiscardOnly; Sts = DtsDrvCmd(Ctx,BCM_IOC_FLUSH_RX_CAP, 0, pIocData, TRUE); //If it is not Discard Only, RX Buffer will be un-mapped if(bDiscardOnly == false) { Ctx->bMapOutBufDone = false; } return Sts; } DRVIFLIB_INT_API BC_STATUS DtsCancelTxRequest( HANDLE hDevice, uint32_t Operation) { return BC_STS_SUCCESS; // Since we always check before TX, there can never be a TX holding in the Driver. FIXME } DRVIFLIB_API BC_STATUS DtsProcOutput( HANDLE hDevice, uint32_t milliSecWait, BC_DTS_PROC_OUT *pOut) { BC_STATUS stRel,sts = BC_STS_SUCCESS; BC_DTS_PROC_OUT OutBuffs; uint32_t width=0, savFlags=0; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if (Ctx->State == BC_DEC_STATE_CLOSE) { return BC_STS_DEC_NOT_OPEN; } if (Ctx->State == BC_DEC_STATE_STOP || Ctx->State == BC_DEC_STATE_FLUSH) { return BC_STS_DEC_NOT_STARTED; } if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; if(!pOut){ DebugLog_Trace(LDIL_DBG,"DtsProcOutput: Invalid Arg!!\n"); return BC_STS_INV_ARG; } if(!(Ctx->FixFlags & DTS_LOAD_FILE_PLAY_FW)){ if(!(Ctx->RegCfg.DbgOptions & BC_BIT(6))){ DebugLog_Trace(LDIL_DBG,"DtsProcOutput: Use NoCopy Interface for PIB encryption scheme\n"); return BC_STS_ERR_USAGE; } } savFlags = pOut->PoutFlags; pOut->discCnt = 0; do { memset(&OutBuffs,0,sizeof(OutBuffs)); sts = DtsFetchOutInterruptible(Ctx,&OutBuffs,milliSecWait); if(sts != BC_STS_SUCCESS) { if(sts == BC_STS_TIMEOUT) { if (Ctx->bEOSCheck == true && Ctx->bEOS == false) { if(milliSecWait) Ctx->EOSCnt = BC_EOS_PIC_COUNT; else Ctx->EOSCnt ++; if(Ctx->EOSCnt >= BC_EOS_PIC_COUNT) { /* Mark this picture as end of stream..*/ pOut->PicInfo.flags |= VDEC_FLAG_LAST_PICTURE; Ctx->bEOS = TRUE; DebugLog_Trace(LDIL_DBG,"HIT EOS with counter\n"); } } sts = BC_STS_NO_DATA; } // Have to make sure EOS is returned correctly for FLEA // In case of Flea the EOS picture has no data and hence the status will be STS_NO_DATA if(OutBuffs.PicInfo.flags & VDEC_FLAG_EOS) pOut->PicInfo.flags |= (VDEC_FLAG_EOS|VDEC_FLAG_LAST_PICTURE); DtsRelRxBuff(Ctx,&Ctx->pOutData->u.RxBuffs,TRUE); return sts; } Ctx->bEOS = FALSE; pOut->PoutFlags |= OutBuffs.PoutFlags; /* Copying the discontinuity count */ if(OutBuffs.discCnt) pOut->discCnt = OutBuffs.discCnt; if(pOut->PoutFlags & BC_POUT_FLAGS_FMT_CHANGE){ if(pOut->PoutFlags & BC_POUT_FLAGS_PIB_VALID){ pOut->PicInfo = OutBuffs.PicInfo; } /* Update Counters */ DtsUpdateOutStats(Ctx,pOut); DtsUpdateVidParams(Ctx, pOut); DtsRelRxBuff(Ctx,&Ctx->pOutData->u.RxBuffs,true); return BC_STS_FMT_CHANGE; } if (Ctx->DevId == BC_PCI_DEVID_FLEA) { if (Ctx->bEOSCheck == true && Ctx->bEOS == true && (OutBuffs.PicInfo.flags & VDEC_FLAG_EOS)) { Ctx->bEOS = true; pOut->PicInfo.flags |= (VDEC_FLAG_LAST_PICTURE|VDEC_FLAG_EOS); DebugLog_Trace(LDIL_DBG,"HIT EOS with PIB tag\n"); } } else { if (DtsCheckRptPic(Ctx, &OutBuffs) == true) { DtsRelRxBuff(Ctx,&Ctx->pOutData->u.RxBuffs,FALSE); return BC_STS_NO_DATA; } } if(pOut->DropFrames) { /* We need to release the buffers even if we fail to copy..*/ stRel = DtsRelRxBuff(Ctx,&Ctx->pOutData->u.RxBuffs,FALSE); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsProcOutput: Failed to copy out buffs.. %x\n", sts); return sts; } pOut->DropFrames--; /* Get back the original flags */ pOut->PoutFlags = savFlags; // Added support for dropping of single pictures by Adobe FP if(Ctx->SingleThreadedAppMode && (pOut->DropFrames == 0)) { pOut->PicInfo.timeStamp = 0; pOut->PicInfo.picture_number = OutBuffs.PicInfo.picture_number; if(OutBuffs.PicInfo.flags & VDEC_FLAG_EOS) pOut->PicInfo.flags |= (VDEC_FLAG_EOS|VDEC_FLAG_LAST_PICTURE); return BC_STS_SUCCESS; } } else break; // this can't be right, DropFrames is a uint8_t so it will always be greater than or equal to zero. //} while((pOut->DropFrames >= 0)); } while((pOut->DropFrames > 0)); if(pOut->AppCallBack && pOut->hnd && (OutBuffs.PoutFlags & BC_POUT_FLAGS_PIB_VALID)) { /* Merge in and out flags */ OutBuffs.PoutFlags |= pOut->PoutFlags; width = Ctx->HWOutPicWidth; OutBuffs.b422Mode = Ctx->b422Mode; pOut->AppCallBack(pOut->hnd, width, OutBuffs.PicInfo.height, 0, &OutBuffs); } if (pOut->PoutFlags & BC_POUT_FLAGS_MODE) { sts = DtsCopyFormat(Ctx,pOut,&OutBuffs); } else { pOut->b422Mode = Ctx->b422Mode; if(Ctx->b422Mode) { sts = DtsCopyRawDataToOutBuff(Ctx,pOut,&OutBuffs); }else{ if(pOut->PoutFlags & BC_POUT_FLAGS_YV12){ sts = DtsCopyNV12ToYV12(Ctx,pOut,&OutBuffs); }else { sts = DtsCopyNV12(Ctx,pOut,&OutBuffs); } } } if(pOut->PoutFlags & BC_POUT_FLAGS_PIB_VALID){ pOut->PicInfo = OutBuffs.PicInfo; } /* Update Counters */ DtsUpdateOutStats(Ctx,pOut); /* We need to release the buffers even if we fail to copy..*/ stRel = DtsRelRxBuff(Ctx,&Ctx->pOutData->u.RxBuffs,FALSE); if(sts != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsProcOutput: Failed to copy out buffs.. %x\n", sts); return sts; } return stRel; } #ifdef _ENABLE_CODE_INSTRUMENTATION_ static void dts_swap_buffer(uint32_t *dst, uint32_t *src, uint32_t cnt) { uint32_t i=0; for (i=0; i < cnt; i++){ dst[i] = BC_SWAP32(src[i]); } } #endif DRVIFLIB_API BC_STATUS DtsProcOutputNoCopy( HANDLE hDevice, uint32_t milliSecWait, BC_DTS_PROC_OUT *pOut ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; if (Ctx->State == BC_DEC_STATE_CLOSE) { return BC_STS_DEC_NOT_OPEN; } if (Ctx->State == BC_DEC_STATE_STOP || Ctx->State == BC_DEC_STATE_FLUSH) { return BC_STS_DEC_NOT_STARTED; } if(!pOut){ return BC_STS_INV_ARG; } /* Init device params */ if(Ctx->DevId == BC_PCI_DEVID_LINK){ pOut->bPibEnc = TRUE; }else{ pOut->bPibEnc = FALSE; } pOut->b422Mode = Ctx->b422Mode; while(Ctx->State == BC_DEC_STATE_START || Ctx->State == BC_DEC_STATE_PAUSE){ if( (sts = DtsFetchOutInterruptible(Ctx,pOut,milliSecWait)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsProcOutput: No Active Channels\n"); /* In case of a peek..*/ if((sts == BC_STS_TIMEOUT) && !(milliSecWait) ){ sts = BC_STS_NO_DATA; break; } } /* * If the PIB is not encrypted then we can direclty go * to the PIB and get the information weather the Picture * is encrypted or not. */ /* Update Counters.. */ DtsUpdateOutStats(Ctx,pOut); if( (sts == BC_STS_SUCCESS) && (pOut->PoutFlags & BC_POUT_FLAGS_FMT_CHANGE) ){ DtsRelRxBuff(Ctx,&Ctx->pOutData->u.RxBuffs,TRUE); sts = BC_STS_FMT_CHANGE; break; } if(pOut->DropFrames){ /* We need to release the buffers even if we fail to copy..*/ sts = DtsRelRxBuff(Ctx,&Ctx->pOutData->u.RxBuffs,FALSE); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsProcOutput: Failed to release buffs.. %x\n", sts); return sts; } pOut->DropFrames--; } else break; } return sts; } DRVIFLIB_API BC_STATUS DtsReleaseOutputBuffs( HANDLE hDevice, PVOID Reserved, BOOL fChange) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if(fChange) return BC_STS_SUCCESS; return DtsRelRxBuff(Ctx, &Ctx->pOutData->u.RxBuffs, FALSE); } DRVIFLIB_INT_API BC_STATUS DtsSendData( HANDLE hDevice , uint8_t *pUserData, uint32_t ulSizeInBytes, uint64_t timeStamp, BOOL encrypted ) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); // for now check the sizes here and wait if there is not enough space while(ulSizeInBytes > Ctx->circBuf.freeSize) { usleep(5 * 1000); if (Ctx->State != BC_DEC_STATE_START && Ctx->State != BC_DEC_STATE_PAUSE) return BC_STS_IO_USER_ABORT; } return txBufPush(&Ctx->circBuf, pUserData, ulSizeInBytes); } DRVIFLIB_API uint32_t DtsTxFreeSize( HANDLE hDevice ) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); return Ctx->circBuf.freeSize; } DRVIFLIB_API BC_STATUS DtsSendSPESPkt(HANDLE hDevice , uint64_t timeStamp, BOOL encrypted ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_INPUT_MDATA *im = NULL; //unused uint8_t *temp=NULL; uint32_t ulSize = 0; uint8_t* pSPESPkt = NULL; uint8_t i = 0; DTS_GET_CTX(hDevice,Ctx); if (Ctx->State == BC_DEC_STATE_CLOSE) { return BC_STS_DEC_NOT_OPEN; } if (Ctx->State == BC_DEC_STATE_STOP || Ctx->State == BC_DEC_STATE_FLUSH) { return BC_STS_DEC_NOT_STARTED; } while (i <20) { sts = DtsPrepareMdata(Ctx, timeStamp, &im, &pSPESPkt, &ulSize); if (sts == BC_STS_SUCCESS) break; i++; bc_sleep_ms(2); } if (sts == BC_STS_SUCCESS) { if(Ctx->VidParams.VideoAlgo == BC_VID_ALGO_VC1MP) { if(posix_memalign((void**)&pSPESPkt, 8, 32+sizeof(BC_PES_HDR_FORMAT))){ DebugLog_Trace(LDIL_DBG, "DtsProcInput: Failed to alloc mem for ASFHdr for SPES:%x\n", sts); return BC_STS_INSUFF_RES; } sts =DtsPrepareMdataASFHdr(Ctx, im, pSPESPkt); if(sts != BC_STS_SUCCESS){ free(pSPESPkt); DebugLog_Trace(LDIL_DBG, "DtsProcInput: Failed to Prepare ASFHdr for SPES:%x\n", sts); return sts; } ulSize = 32+sizeof(BC_PES_HDR_FORMAT); } sts = DtsSendData(hDevice, pSPESPkt, ulSize, 0, encrypted); if(Ctx->VidParams.VideoAlgo == BC_VID_ALGO_VC1MP) free(pSPESPkt); if(sts != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG, "DtsProcInput: Failed to send Spes hdr:%x\n", sts); DtsFreeMdata(Ctx,im,TRUE); return sts; } sts = DtsInsertMdata(Ctx,im); if(sts != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG, "DtsProcInput: DtsInsertMdata failed\n"); } } return sts; } DRVIFLIB_API BC_STATUS DtsAlignSendData( HANDLE hDevice , uint8_t *pUserData, uint32_t ulSizeInBytes, uint64_t timeStamp, BOOL encrypted ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; uint8_t oddBytes = 0; uint8_t* alignBuf; DTS_GET_CTX(hDevice,Ctx); alignBuf = Ctx->alignBuf; uint32_t ulRestBytes = ulSizeInBytes; uint32_t ulDeliverBytes = 0; uint32_t ulPktLength; uint32_t ulPktHeaderSz; uint32_t ulUsedDataBytes = 0; uint8_t* pDeliverBuf = NULL; uint8_t* pRestDataPt = pUserData; uint8_t bAddPTS = 1; uint8_t bPrivData = Ctx->PESConvParams.m_bPESPrivData; uint8_t bExtData = Ctx->PESConvParams.m_bPESExtField; uint8_t bStuffing = Ctx->PESConvParams.m_bStuffing; uint8_t* pPrivData = Ctx->PESConvParams.m_pPESPrivData; uint8_t* pExtData = Ctx->PESConvParams.m_pPESExtField; uint32_t nExtDataLen = Ctx->PESConvParams.m_nPESExtLen; uint32_t nStuffingBytes = Ctx->PESConvParams.m_nStuffingBytes; uint8_t j = 0; uint8_t k = 0; //SoftRave (VC-1 S/M and Divx) EOS Timing Marker if ((timeStamp || Ctx->PESConvParams.m_bSoftRave)) { bAddPTS = 1; } else { bAddPTS = 0; } while ((Ctx->State == BC_DEC_STATE_START || Ctx->State == BC_DEC_STATE_PAUSE) && ulRestBytes ) { sts = BC_STS_SUCCESS; pDeliverBuf = pRestDataPt; if (Ctx->State == BC_DEC_STATE_PAUSE) { sleep(5); continue; } /* Copy the non-DWORD aligned buffer first */ oddBytes = (uint8_t)((uintptr_t)pDeliverBuf % 4); if (Ctx->VidParams.StreamType == BC_STREAM_TYPE_ES) { // SPES Mode ulDeliverBytes = ulRestBytes; if (timeStamp) { sts = DtsSendSPESPkt(hDevice, timeStamp, encrypted); } timeStamp = 0; if(oddBytes) { if (ulRestBytes > ALIGN_BUF_SIZE) ulDeliverBytes = ALIGN_BUF_SIZE - oddBytes; else ulDeliverBytes = ulRestBytes; memcpy(alignBuf, pDeliverBuf, ulDeliverBytes); pDeliverBuf = alignBuf; } ulUsedDataBytes = ulDeliverBytes; } else if (Ctx->VidParams.StreamType == BC_STREAM_TYPE_PES) { if (Ctx->DevId == BC_PCI_DEVID_LINK && timeStamp) { sts = DtsSendSPESPkt(hDevice, timeStamp, encrypted); timeStamp = 0; bAddPTS =0; } if (bAddPTS) ulPktHeaderSz = 5; else ulPktHeaderSz = 0; if (bPrivData || bExtData) ulPktHeaderSz += 1; if (bPrivData) ulPktHeaderSz += 16; if (bExtData) ulPktHeaderSz += nExtDataLen + 1; if (bStuffing) ulPktHeaderSz += nStuffingBytes; ulPktLength = ulRestBytes + 3 + ulPktHeaderSz; if (ulPktLength > MAX_RE_PES_BOUND) { ulPktLength = MAX_RE_PES_BOUND; } ulUsedDataBytes = ulPktLength - ulPktHeaderSz - 3; ulDeliverBytes = ulPktLength + 6; memcpy(alignBuf,(uint8_t *)b_pes_header, 9); *((uint16_t *)(alignBuf + 4)) = WORD_SWAP((uint16_t)ulPktLength); *(alignBuf + 8) = (uint8_t)ulPktHeaderSz; j = 9; if (bAddPTS) { *(alignBuf + 7) = 0x80; PTS2MakerBit5Bytes(alignBuf + j, timeStamp); j += 5; } if (bPrivData || bExtData) { *(alignBuf + 7) |= 0x01; *(alignBuf + j) = 0x00; if (bPrivData) *(alignBuf + j) |= 0x80; if (bExtData) *(alignBuf + j) |= 0x01; j++; } if (bPrivData) { memcpy(alignBuf + j, pPrivData, 16); j += 16; } if (bExtData) { *(alignBuf + j) = 0x80 | nExtDataLen; j++; memcpy(alignBuf + j, pExtData, nExtDataLen); j += nExtDataLen; } if (bStuffing) { for (k = 0; k < nStuffingBytes; k ++, j++) { *(alignBuf + j) = 0xFF; } } memcpy(alignBuf + j, pDeliverBuf, ulUsedDataBytes); pDeliverBuf = alignBuf; } if (ulDeliverBytes) { sts = DtsSendData(hDevice,pDeliverBuf ,ulDeliverBytes, 0, encrypted); if(sts == BC_STS_BUSY ) { if (Ctx->State == BC_DEC_STATE_STOP) { break; } sleep(2); } else if(sts == BC_STS_SUCCESS) { ulRestBytes -= ulUsedDataBytes; pRestDataPt += ulUsedDataBytes; bAddPTS = 0; timeStamp = 0; bPrivData = 0; bExtData = 0; pPrivData = NULL; pExtData = NULL; nExtDataLen = 0; bStuffing = 0; nStuffingBytes = 0; } else if(sts == BC_STS_IO_USER_ABORT) { sts = BC_STS_SUCCESS; break; } else break; // On any other error condition } } return sts; } DRVIFLIB_API BC_STATUS DtsProcInput( HANDLE hDevice , uint8_t *pUserData, uint32_t ulSizeInBytes, uint64_t timeStamp, BOOL encrypted ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; uint32_t Offset = 0; DTS_GET_CTX(hDevice,Ctx); if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; if (Ctx->State == BC_DEC_STATE_FLUSH) Ctx->State = BC_DEC_STATE_START; if (Ctx->State != BC_DEC_STATE_START) { if (!DtsIsDecOpened(0)) { DtsLock(Ctx); sts = DtsOpenDecoder(hDevice, Ctx->VidParams.StreamType); if (sts == BC_STS_SUCCESS) { sts = DtsStartDecoder(hDevice); if (sts == BC_STS_SUCCESS) sts = DtsStartCapture(hDevice); } DtsUnLock(Ctx); if (sts != BC_STS_SUCCESS) return sts; } } Ctx->bEOSCheck = false; Ctx->bEOS = false; // According to ASF spec special timestamps can be 0x1FFFFFFFF or 0x1FFFFFFFE // NAREN - FIXME - should we add support for these pre-roll timestamps if (Ctx->DevId == BC_PCI_DEVID_FLEA && timeStamp != 0xFFFFFFFFFFFFFFFFULL) { timeStamp /= 10000; } if((Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WVC1) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMV3) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMVA)) DtsCheckKeyFrame(hDevice, pUserData); if (Ctx->PESConvParams.m_bAddSpsPps) { if (Ctx->PESConvParams.m_pSpsPpsBuf != NULL && Ctx->PESConvParams.m_iSpsPpsLen != 0) { //Check if SequenceHeader is already delivered within input data. //Unnecessary SpsPps input will cause no timestamp output. if (!Ctx->SingleThreadedAppMode && !DtsCheckSpsPps(hDevice, pUserData, ulSizeInBytes)) { // Used to flag softRAVE special handling of Sequence level information as well as preroll samples if (Ctx->PESConvParams.m_bSoftRave) sts = DtsAlignSendData(hDevice, Ctx->PESConvParams.m_pSpsPpsBuf, Ctx->PESConvParams.m_iSpsPpsLen, 0xFFFFFFFFFFFFFFFFULL, 0); else sts = DtsAlignSendData(hDevice, Ctx->PESConvParams.m_pSpsPpsBuf, Ctx->PESConvParams.m_iSpsPpsLen, 0, 0); if (sts != BC_STS_SUCCESS) return sts; } } Ctx->PESConvParams.m_bAddSpsPps = false; } //Use 0xFFFFFFFD for SoftRave context instead of zero // For pre-roll samples for softRAVE context we send the timestamp as 0 to the softRAVE to handle. // The FW is responsible to add the timestamp back. //Both 0x1FFFFFFFF and 0x1FFFFFFFE when right shifted by XPT become 0xFFFFFFFF which will be treated as special PTS by softrave to replace the PTS entry with Start code entry if (Ctx->PESConvParams.m_bSoftRave && (((timeStamp&0x1FFFFFFFFULL) == 0x1FFFFFFFFULL) || ((timeStamp&0x1FFFFFFFFULL) == 0x1FFFFFFFEULL))) { //timeStamp = 0x0; timeStamp = 0xFFFFFFFDULL; } if ((sts = DtsAddStartCode(hDevice, &pUserData, &ulSizeInBytes, &timeStamp)) != BC_STS_SUCCESS) { if (sts == BC_STS_IO_XFR_ERROR) return BC_STS_SUCCESS; return BC_STS_ERROR; } if (Ctx->VidParams.StreamType == BC_STREAM_TYPE_PES || timeStamp == 0) { return DtsAlignSendData(hDevice, pUserData, ulSizeInBytes, timeStamp, encrypted); } else { if(!Ctx->SingleThreadedAppMode && (DtsFindStartCode(hDevice, pUserData, ulSizeInBytes, &Offset) != BC_STS_SUCCESS)) { timeStamp = 0; Offset = 0; } if(Offset == 0) { return DtsAlignSendData(hDevice, pUserData, ulSizeInBytes, timeStamp, encrypted); } else { if ((sts=DtsAlignSendData(hDevice, pUserData, Offset, 0, encrypted)) != BC_STS_SUCCESS) return sts; if(ulSizeInBytes > Offset) return DtsAlignSendData(hDevice, pUserData+Offset, ulSizeInBytes-Offset, timeStamp, encrypted); } } return BC_STS_ERROR; } DRVIFLIB_API BC_STATUS DtsGetColorPrimaries( HANDLE hDevice , uint32_t *colorPrimaries ) { return BC_STS_NOT_IMPL; } DRVIFLIB_API BC_STATUS DtsSendEOS( HANDLE hDevice, uint32_t Op ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); uint8_t *pEOS; uint32_t nEOSLen; uint32_t nTag; if (Ctx->State == BC_DEC_STATE_CLOSE) { return BC_STS_DEC_NOT_OPEN; } if (Ctx->State == BC_DEC_STATE_STOP || Ctx->State == BC_DEC_STATE_FLUSH) { return BC_STS_DEC_NOT_STARTED; } Ctx->PESConvParams.m_bPESExtField = false; Ctx->PESConvParams.m_bPESPrivData = false; Ctx->PESConvParams.m_pPESExtField = NULL; Ctx->PESConvParams.m_pPESPrivData = NULL; //SoftRave (VC-1 S/M and Divx) EOS Timing Marker if ((Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WVC1) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMV3) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMVA) || (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_VC1) ) { Ctx->PESConvParams.m_bPESExtField = true; Ctx->PESConvParams.m_nPESExtLen = 2; Ctx->PESConvParams.m_pPESExtField = ExtData; } if (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_MPEG1VIDEO || Ctx->VidParams.MediaSubType == BC_MSUBTYPE_MPEG2VIDEO) { pEOS = eos_mpeg; nEOSLen = 4; } else if (Ctx->VidParams.MediaSubType == BC_MSUBTYPE_DIVX || Ctx->VidParams.MediaSubType == BC_MSUBTYPE_DIVX311) { pEOS = eos_divx; nEOSLen = 8; } else if (Ctx->DevId == BC_PCI_DEVID_LINK && Ctx->VidParams.MediaSubType == BC_MSUBTYPE_WMV3) { pEOS = eos_vc1_spmp_link; nEOSLen = 32; } else { pEOS = eos_avc_vc1; nEOSLen = 8; } sts = DtsAlignSendData(hDevice, pEOS, nEOSLen, 0, 0); /* Only send timing marker if this is FLEA */ /* LINK Support LAST_PICTURE and does not need timing marker */ if (Op == 0) { if (Ctx->DevId == BC_PCI_DEVID_FLEA) { Ctx->PESConvParams.m_bPESPrivData = true; Ctx->PESConvParams.m_pPESPrivData = btp_video_done_es_private; if (Ctx->PESConvParams.m_bPESExtField == true) { Ctx->PESConvParams.m_bStuffing = false; Ctx->PESConvParams.m_nStuffingBytes = 0; } else { Ctx->PESConvParams.m_bStuffing = true; Ctx->PESConvParams.m_nStuffingBytes = 3; } nTag = 0xffff0000 | (0xffff & 0x0001); btp_video_done_es[0] = 0x00; btp_video_done_es[13] = (nTag >> 24) & 0xff; btp_video_done_es[14] = (nTag >> 16) & 0xff; btp_video_done_es[15] = (nTag >> 8) & 0xff; btp_video_done_es[16] = nTag & 0xff; sts = DtsAlignSendData(hDevice, btp_video_done_es, sizeof(btp_video_done_es), 0, 0); Ctx->PESConvParams.m_bPESPrivData = false; Ctx->PESConvParams.m_pPESPrivData = NULL; Ctx->PESConvParams.m_bStuffing = false; Ctx->PESConvParams.m_nStuffingBytes = 0; sts = DtsAlignSendData(hDevice, pEOS, nEOSLen, 0, 0); sts = DtsAlignSendData(hDevice, pEOS, nEOSLen, 0, 0); } Ctx->bEOSCheck = true; } //Reset Ctx->PESConvParams.m_bPESExtField = false; Ctx->PESConvParams.m_pPESExtField = NULL; Ctx->PESConvParams.m_bPESPrivData = false; Ctx->PESConvParams.m_pPESPrivData = NULL; Ctx->PESConvParams.m_bStuffing = false; Ctx->PESConvParams.m_nStuffingBytes = 0; //SoftRave (VC-1 S/M and Divx) EOS Timing Marker return sts; } DRVIFLIB_API BC_STATUS DtsFlushInput( HANDLE hDevice , uint32_t Op ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); DebugLog_Trace(LDIL_DBG, "Flush called with opcode %u\n", Op); if (Ctx->State == BC_DEC_STATE_CLOSE) { return BC_STS_DEC_NOT_OPEN; } if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; if(Op == 0 || Op == 5) // DRAIN { DtsSendEOS(hDevice, Op); return BC_STS_SUCCESS; } else { Ctx->PESConvParams.m_bAddSpsPps = true; Ctx->State = BC_DEC_STATE_FLUSH; txBufFlush(&Ctx->circBuf); Ctx->bEOSCheck = false; bc_sleep_ms(30); // For the cancel to take place in case we are looping sts = DtsCancelTxRequest(hDevice, Op); if((Op == 3) || (sts != BC_STS_SUCCESS)) { return sts; } DtsClrPendMdataList(Ctx); } // On LINK if the decoder is paused due to the RLL being full, un pause it before flush if(Ctx->DevId == BC_PCI_DEVID_LINK && Ctx->hw_paused) { DtsFWPauseVideo(hDevice,eC011_PAUSE_MODE_OFF); Ctx->hw_paused = false; } if(Op == 4) sts = DtsFWDecFlushChannel(hDevice,2); else if (Op != 0 && Op != 5) sts = DtsFWDecFlushChannel(hDevice,Op); if(Op != 0 && Op != 5) { if (Ctx->State != BC_DEC_STATE_CLOSE) { DtsLock(Ctx); sts = DtsStopDecoder(hDevice); sts = DtsCloseDecoder(hDevice); DtsUnLock(Ctx); } } Ctx->LastPicNum = -1; Ctx->LastSessNum = -1; Ctx->EOSCnt = 0; Ctx->DrvStatusEOSCnt = 0; Ctx->bEOS = FALSE; // Ctx->InSampleCount = 0; Ctx->PESConvParams.m_lStartCodeDataSize = 0; return BC_STS_SUCCESS; } DRVIFLIB_API BC_STATUS DtsSetRateChange(HANDLE hDevice , uint32_t rate, uint8_t direction ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); //For Rate Change uint32_t mode = 0; uint32_t HostTrickModeEnable = 0; if (Ctx->State == BC_DEC_STATE_CLOSE) { return BC_STS_DEC_NOT_OPEN; } if (Ctx->State == BC_DEC_STATE_STOP || Ctx->State == BC_DEC_STATE_FLUSH) { return BC_STS_DEC_NOT_STARTED; } if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; //Change Rate Value for Version 1.1 //Rate: Specifies the new rate x 10000 //Rate is the inverse of speed. For example, if the playback speed is 2x, the rate is 1/2, so the Rate member is set to 5000. float fRate = float(1) / ((float)rate / (float)10000); //Mode Decision if(fRate < 1) { //Slow LONG Rate = LONG(float(1) / fRate); mode = eC011_SKIP_PIC_IPB_DECODE; HostTrickModeEnable = 1; sts = DtsFWSetHostTrickMode(hDevice,HostTrickModeEnable); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsSetRateChange:DtsFWSetHostTrickMode Failed\n"); return sts; } sts = DtsFWSetSkipPictureMode(hDevice,mode); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsSetRateChange: DtsFWSetSkipPictureMode Failed\n"); return sts; } sts = DtsFWSetSlowMotionRate(hDevice, Rate); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsSetRateChange: Set Slow Forward Failed\n"); return sts; } } else { //Fast LONG Rate = (LONG)fRate; //For I-Frame Only Trick Mode //Direction: 0: Forward, 1: Backward if(Ctx->DevId == BC_PCI_DEVID_FLEA) { //Flea if((Rate <= 2) && (direction == 0)) { DebugLog_Trace(LDIL_DBG,"DtsSetRateChange: Set Normal Speed\n"); mode = eC011_SKIP_PIC_IPB_DECODE; HostTrickModeEnable = 0; } else if((Rate <= 3) && (direction == 0)) { DebugLog_Trace(LDIL_DBG,"DtsSetRateChange: Set Fast Speed for IP-Frame Only\n"); mode = eC011_SKIP_PIC_IP_DECODE; HostTrickModeEnable = 1; } else { //I-Frame Only for Fast Forward and All Speed Backward DebugLog_Trace(LDIL_DBG,"DtsSetRateChange: Set Very Fast Speed for I-Frame Only\n"); mode = eC011_SKIP_PIC_I_DECODE; HostTrickModeEnable = 1; } } else { //Link if((Rate == 1) && (direction == 0)) { DebugLog_Trace(LDIL_DBG,"DtsSetRateChange: Set Normal Speed\n"); mode = eC011_SKIP_PIC_IPB_DECODE; HostTrickModeEnable = 0; if(fRate > 1 && fRate < 2) { //Nav is giving I instead of IBP for 1.4x or 1.6x DebugLog_Trace(LDIL_DBG,"DtsSetRateChange: Set 1.x I only\n"); mode = eC011_SKIP_PIC_I_DECODE; HostTrickModeEnable = 1; } } else { //I-Frame Only for Fast Forward and All Speed Backward DebugLog_Trace(LDIL_DBG,"DtsSetRateChange: Set Very Fast Speed for I-Frame Only\n"); mode = eC011_SKIP_PIC_I_DECODE; HostTrickModeEnable = 1; } } sts = DtsFWSetHostTrickMode(hDevice,HostTrickModeEnable); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsSetRateChange:DtsFWSetHostTrickMode Failed\n"); return sts; } sts = DtsFWSetSkipPictureMode(hDevice,mode); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsSetRateChange: DtsFWSetSkipPictureMode Failed\n"); return sts; } if(Ctx->DevId != BC_PCI_DEVID_FLEA) { sts = DtsFWSetFFRate(hDevice, Rate); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsSetRateChange: Set Fast Forward Failed\n"); return sts; } } } return BC_STS_SUCCESS; } //Set FF Rate for Catching Up DRVIFLIB_API BC_STATUS DtsSetFFRate(HANDLE hDevice , uint32_t rate) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); //For Rate Change uint32_t mode = 0; uint32_t HostTrickModeEnable = 0; if (Ctx->State == BC_DEC_STATE_CLOSE) { return BC_STS_DEC_NOT_OPEN; } if (Ctx->State == BC_DEC_STATE_STOP || Ctx->State == BC_DEC_STATE_FLUSH) { return BC_STS_DEC_NOT_STARTED; } if (!DtsChkPID(Ctx->ProcessID)) return BC_STS_ERROR; //Change Rate Value for Version 1.1 //Rate: Specifies the new rate x 10000 //Rate is the inverse of speed. For example, if the playback speed is 2x, the rate is 1/2, so the Rate member is set to 5000. float fRate = float(1) / ((float)rate / (float)10000); //Mode Decision if(fRate < 1) { //Error //Only for FF DebugLog_Trace(LDIL_DBG,"DtsSetFFRate: NOT Support Slow Motion\n"); return BC_STS_INV_ARG; } else { //Fast LONG Rate = (LONG)fRate; if(Ctx->DevId == BC_PCI_DEVID_FLEA) { if(Rate > FLEA_MAX_TRICK_MODE_SPEED) { Rate = FLEA_MAX_TRICK_MODE_SPEED; } } //IPB Mode for Catching Up mode = eC011_SKIP_PIC_IPB_DECODE; if(Rate == 1) { //Normal Mode DebugLog_Trace(LDIL_DBG,"DtsSetFFRate: Set Normal Speed\n"); HostTrickModeEnable = 0; } else { //Fast Forward DebugLog_Trace(LDIL_DBG,"DtsSetFFRate: Set Fast Forward\n"); HostTrickModeEnable = 1; } sts = DtsFWSetHostTrickMode(hDevice, HostTrickModeEnable); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsSetFFRate:DtsFWSetHostTrickMode Failed\n"); return sts; } sts = DtsFWSetSkipPictureMode(hDevice, mode); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsSetFFRate: DtsFWSetSkipPictureMode Failed\n"); return sts; } sts = DtsFWSetFFRate(hDevice, Rate); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsSetFFRate: Set Fast Forward Failed\n"); return sts; } } return BC_STS_SUCCESS; } DRVIFLIB_API BC_STATUS DtsSetSkipPictureMode( HANDLE hDevice , uint32_t SkipMode ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); sts = DtsFWSetSkipPictureMode(hDevice,SkipMode); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsSetSkipPictureMode: Set Picture Mode Failed, %d\n",SkipMode); return sts; } return BC_STS_SUCCESS; } DRVIFLIB_API BC_STATUS DtsSetIFrameTrickMode( HANDLE hDevice ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); sts = DtsFWSetHostTrickMode(hDevice,1); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsSetIFrameTrickMode: DtsFWSetHostTrickMode Failed\n"); return sts; } sts = DtsFWSetSkipPictureMode(hDevice,eC011_SKIP_PIC_I_DECODE); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsSetIFrameTrickMode: DtsFWSetSkipPictureMode Failed\n"); return sts; } return BC_STS_SUCCESS; } DRVIFLIB_API BC_STATUS DtsStepDecoder( HANDLE hDevice ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if( Ctx->State != BC_DEC_STATE_PAUSE ) { DebugLog_Trace(LDIL_DBG,"DtsStepDecoder: Failed because Decoder is Not Paused\n"); return BC_STS_ERR_USAGE; } sts = DtsFWFrameAdvance(hDevice); if(sts != BC_STS_SUCCESS ) { DebugLog_Trace(LDIL_DBG,"DtsStepDecoder: Failed \n"); return sts; } return sts; } #if 0 DRVIFLIB_API BC_STATUS DtsIs422Supported( HANDLE hDevice, uint8_t* bSupported) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->DevId == BC_PCI_DEVID_LINK || Ctx->DevId == BC_PCI_DEVID_FLEA) { *bSupported = 1; } else { *bSupported = 0; } return sts; } DRVIFLIB_API BC_STATUS DtsSet422Mode(HANDLE hDevice, uint8_t Mode422) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->DevId != BC_PCI_DEVID_LINK) { return sts; } Ctx->b422Mode = (BC_OUTPUT_FORMAT)Mode422; sts = DtsSetLinkIn422Mode(hDevice); return sts; } #endif DRVIFLIB_API BC_STATUS DtsIsEndOfStream( HANDLE hDevice, uint8_t* bEOS ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); *bEOS = Ctx->bEOS; return sts; } DRVIFLIB_API BC_STATUS DtsSetColorSpace( HANDLE hDevice, BC_OUTPUT_FORMAT Mode422 ) { BC_STATUS sts = BC_STS_SUCCESS; //unused uint32_t Val = 0; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->DevId == BC_PCI_DEVID_LINK) { Ctx->b422Mode = Mode422; sts = DtsSetLinkIn422Mode(hDevice); } else if (Ctx->DevId == BC_PCI_DEVID_FLEA) { Ctx->b422Mode = Mode422; sts = DtsSetFleaIn422Mode(hDevice); } return sts; } DRVIFLIB_API BC_STATUS DtsGetDILPath( HANDLE hDevice, char *DilPath, uint32_t size ) { DTS_LIB_CONTEXT *Ctx = NULL; uint32_t *ptemp=NULL; DTS_GET_CTX(hDevice,Ctx); if(!DilPath || (size < sizeof(Ctx->DilPath)) ){ return BC_STS_INV_ARG; } /* if the first 4 bytes are zero, then the dil path in the context is not yet set. Hence go ahead and look at registry and update the context. and then just copy the dil path from context. */ ptemp = (uint32_t*)&Ctx->DilPath[0]; if(!(*ptemp)) DtsGetFirmwareFiles(Ctx); strncpy(DilPath, Ctx->DilPath, sizeof(Ctx->DilPath)); return BC_STS_SUCCESS; } DRVIFLIB_API BC_STATUS DtsDropPictures( HANDLE hDevice , uint32_t Pictures ) { BC_STATUS sts = BC_STS_SUCCESS; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if (Ctx->State == BC_DEC_STATE_CLOSE) { return BC_STS_DEC_NOT_OPEN; } if (Ctx->State == BC_DEC_STATE_STOP || Ctx->State == BC_DEC_STATE_FLUSH) { return BC_STS_DEC_NOT_STARTED; } sts = DtsFWDrop(hDevice,Pictures); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsDropPictures: Set Picture Mode Failed, %d\n",Pictures); return sts; } return BC_STS_SUCCESS; } DRVIFLIB_API BC_STATUS DtsGetDriverStatus( HANDLE hDevice, BC_DTS_STATUS *pStatus) { BC_DTS_STATS temp; BC_STATUS ret; BOOL realHWCPBSize = false; // Always report DIL buffer size unless explicitly asked to report HW size BOOL readTXinfoOnly = false; // Report only TX information uint64_t NextTimeStamp = 0; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); temp.DrvNextMDataPLD = Ctx->HWOutPicWidth | (0x1 << 31); // If bit 31 of the input cpbEmptySize is set, then report the real HW size // Else report the buffered size // If Bit 30 of the input cpbEmptySize is set, then only report TX information // and not probe for anything else // Use Bit 29 to indicate to the driver to read the VC1 fifo status if(pStatus->cpbEmptySize >> 31) realHWCPBSize = true; if((pStatus->cpbEmptySize >> 30) & 0x1) { readTXinfoOnly = true; temp.DrvcpbEmptySize |= (1 << 30); } if(Ctx->VidParams.VideoAlgo == BC_VID_ALGO_VC1MP) temp.DrvcpbEmptySize |= (1 << 29); ret = DtsGetDrvStat(hDevice, &temp); if (ret != BC_STS_SUCCESS) { return ret; } pStatus->FreeListCount = temp.drvFLL; pStatus->ReadyListCount = temp.drvRLL; pStatus->FramesCaptured = temp.opFrameCaptured; pStatus->FramesDropped = temp.opFrameDropped; pStatus->FramesRepeated = temp.reptdFrames; pStatus->PIBMissCount = temp.pibMisses; pStatus->InputCount = temp.ipSampleCnt; pStatus->InputBusyCount = temp.TxFifoBsyCnt; pStatus->InputTotalSize = temp.ipTotalSize; pStatus->cpbEmptySize = temp.DrvcpbEmptySize; pStatus->picNumFlags = temp.picNumFlags; pStatus->PowerStateChange = temp.pwr_state_change; if(temp.eosDetected) { Ctx->bEOS = true; } if (Ctx->bEOSCheck == true && Ctx->bEOS == true) { if (pStatus->ReadyListCount == 0) { Ctx->DrvStatusEOSCnt ++; if(Ctx->DrvStatusEOSCnt >= BC_EOS_PIC_COUNT) { /* Mark this picture as end of stream..*/ Ctx->bEOS = TRUE; } } else Ctx->DrvStatusEOSCnt = 0; } if(!realHWCPBSize) pStatus->cpbEmptySize = Ctx->circBuf.freeSize; if(!readTXinfoOnly) { /* return the timestamp of the next picture to be returned by ProcOutput */ if((pStatus->ReadyListCount > 0) && Ctx->SingleThreadedAppMode) { if(Ctx->DevId == BC_PCI_DEVID_FLEA) { if(temp.DrvNextMDataPLD == 0xFFFFFFFF){ //For Pre-Load pStatus->NextTimeStamp = 0xFFFFFFFFFFFFFFFFLL; }else{ //Normal PTS //Change PTS becuase of Shift PTS Issue in FW and 32-bit (ms) and 64-bit (100 ns) Scaling pStatus->NextTimeStamp = (temp.DrvNextMDataPLD * 2 * 10000); } }else{ DtsFetchTimeStampMdata(Ctx, ((temp.DrvNextMDataPLD & 0xFF) << 8) | ((temp.DrvNextMDataPLD & 0xFF00) >> 8), &NextTimeStamp); pStatus->NextTimeStamp = NextTimeStamp; } } } // For LINK Pause HW if the RLL is too full. Prevent overflows // Hard coded values for now if(Ctx->DevId == BC_PCI_DEVID_LINK && Ctx->SingleThreadedAppMode) { if(pStatus->ReadyListCount > 10 && !Ctx->hw_paused && !Ctx->fw_cmd_issued) { DtsFWPauseVideo(hDevice,eC011_PAUSE_MODE_ON); Ctx->hw_paused = true; } else if (pStatus->ReadyListCount < 6 && Ctx->hw_paused && !Ctx->fw_cmd_issued) { DtsFWPauseVideo(hDevice,eC011_PAUSE_MODE_OFF); Ctx->hw_paused = false; } } return ret; } DRVIFLIB_API BC_STATUS DtsGetCapabilities (HANDLE hDevice, PBC_HW_CAPS pCapsBuffer) { DTS_LIB_CONTEXT *Ctx; BC_STATUS sts = BC_STS_SUCCESS; uint32_t pciids = 0; int shmid = 0; // DebugLog_Trace(LDIL_DBG,"DtsGetCapabilities: Called\n"); if(hDevice != NULL) { DTS_GET_CTX(hDevice,Ctx); // Called after the HW has been opened pciids = Ctx->DevId; } else { // called before HW has been opened // First make sure no one else has the HW open already if(BC_STS_SUCCESS == DtsCreateShMem(&shmid)) { pciids = DtsGetgDevID(); DtsDelDilShMem(); if(pciids == BC_PCI_DEVID_INVALID) { sts = DtsGetHWFeatures(&pciids); pciids >>= 16; if(sts != BC_STS_SUCCESS) return sts; } } else return BC_STS_INSUFF_RES; } if (pciids == BC_PCI_DEVID_INVALID) { return BC_STS_ERROR; } // Should check with driver/FW if current video is supported or not, and output supported format if(pciids == BC_PCI_DEVID_LINK) { pCapsBuffer->flags = PES_CONV_SUPPORT; pCapsBuffer->ColorCaps.Count = 3; pCapsBuffer->ColorCaps.OutFmt[0] = OUTPUT_MODE420; pCapsBuffer->ColorCaps.OutFmt[1] = OUTPUT_MODE422_YUY2; pCapsBuffer->ColorCaps.OutFmt[2] = OUTPUT_MODE422_UYVY; pCapsBuffer->Reserved1 = NULL; //Decoder Capability pCapsBuffer->DecCaps = BC_DEC_FLAGS_H264 | BC_DEC_FLAGS_MPEG2 | BC_DEC_FLAGS_VC1; } if(pciids == BC_PCI_DEVID_FLEA) { pCapsBuffer->flags = PES_CONV_SUPPORT; pCapsBuffer->ColorCaps.Count = 1; pCapsBuffer->ColorCaps.OutFmt[0] = OUTPUT_MODE422_YUY2; pCapsBuffer->ColorCaps.OutFmt[1] = OUTPUT_MODE_INVALID; pCapsBuffer->ColorCaps.OutFmt[2] = OUTPUT_MODE_INVALID; pCapsBuffer->Reserved1 = NULL; //Decoder Capability pCapsBuffer->DecCaps = BC_DEC_FLAGS_H264 | BC_DEC_FLAGS_MPEG2 | BC_DEC_FLAGS_VC1 | BC_DEC_FLAGS_M4P2; } return BC_STS_SUCCESS; } DRVIFLIB_API BC_STATUS DtsSetScaleParams(HANDLE hDevice, PBC_SCALING_PARAMS pScaleParams) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice, Ctx); uint32_t ScaledWidth = 0; if (Ctx->DevId == BC_PCI_DEVID_FLEA) { if ((pScaleParams->sWidth > 1920) || (pScaleParams->sWidth < 128)) ScaledWidth = 1280; else ScaledWidth = pScaleParams->sWidth; Ctx->EnableScaling = (ScaledWidth << 20) | (ScaledWidth << 8) | 1; } else { DebugLog_Trace(LDIL_ERR,"DtsSetScaleParams: not supported\n"); return BC_STS_INV_ARG; } return DtsCheckProfile(hDevice); } DRVIFLIB_API BC_STATUS DtsCrystalHDVersion(HANDLE hDevice, PBC_INFO_CRYSTAL bCrystalInfo) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->DevId == BC_PCI_DEVID_LINK) bCrystalInfo->device = 0; else if(Ctx->DevId == BC_PCI_DEVID_FLEA) bCrystalInfo->device = 1; bCrystalInfo->dilVersion.dilRelease = DIL_MAJOR_VERSION; bCrystalInfo->dilVersion.dilMajor = DIL_MINOR_VERSION; bCrystalInfo->dilVersion.dilMinor = DIL_REVISION; bCrystalInfo->drvVersion.drvRelease = DRIVER_MAJOR_VERSION; bCrystalInfo->drvVersion.drvMajor = DRIVER_MINOR_VERSION; bCrystalInfo->drvVersion.drvMinor = DRIVER_REVISION; bCrystalInfo->fwVersion.fwRelease = FW_MAJOR_VERSION; bCrystalInfo->fwVersion.fwMajor = FW_MINOR_VERSION; bCrystalInfo->fwVersion.fwMinor = FW_REVISION; return BC_STS_SUCCESS; } crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/libcrystalhd_int_if.cpp0000644000175000017500000015436411610313111026733 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_int_if.cpp * * Description: Driver Internal Interfaces * * AU * * HISTORY: * ******************************************************************** * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #include "7411d.h" #include "bc_defines.h" #include "bc_decoder_regs.h" #include "libcrystalhd_priv.h" #include "libcrystalhd_int_if.h" #include "libcrystalhd_fwcmds.h" #include #define SV_MAX_LINE_SZ 128 #define PCI_GLOBAL_CONTROL MISC2_GLOBAL_CTRL #define PCI_INT_STS_REG MISC2_INTERNAL_STATUS // FLEA #define BCHP_MISC2_GLOBAL_CTRL 0x00502100 /* Global Control Register */ #define BCHP_CLK_TEMP_MON_CTRL 0x00070040 /* Temperature monitor control. */ #define BCHP_CLK_TEMP_MON_STATUS 0x00070044 /* Temperature monitor status. */ //===================================Externs =========================================== DRVIFLIB_INT_API BC_STATUS DtsGetHwType( HANDLE hDevice, uint32_t *DeviceID, uint32_t *VendorID, uint32_t *HWRev ) { BC_HW_TYPE *pHWInfo; BC_IOCTL_DATA *pIocData = NULL; DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_SUCCESS; DTS_GET_CTX(hDevice,Ctx); if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; pHWInfo = &pIocData->u.hwType; pHWInfo->PciDevId = 0xffff; pHWInfo->PciVenId = 0xffff; pHWInfo->HwRev = 0xff; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_GET_HWTYPE,0,pIocData,FALSE)) != BC_STS_SUCCESS){ DtsRelIoctlData(Ctx,pIocData); DebugLog_Trace(LDIL_DBG,"DtsGetHwType: Ioctl failed: %d\n",sts); return sts; } *DeviceID = pHWInfo->PciDevId; *VendorID = pHWInfo->PciVenId; *HWRev = pHWInfo->HwRev; // Set these early Ctx->DevId = pHWInfo->PciDevId; Ctx->hwRevId = pHWInfo->HwRev; Ctx->VendorId = pHWInfo->PciVenId; DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API VOID DtsHwReset( HANDLE hDevice ) { return; } DRVIFLIB_INT_API BC_STATUS DtsSoftReset( HANDLE hDevice ) { uint32_t Val = 0; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->DevId == BC_PCI_DEVID_LINK || Ctx->DevId == BC_PCI_DEVID_DOZER) { DtsDevRegisterWr( hDevice, DecHt_HostSwReset, 0x00000001); // Assert c011 soft reset bc_sleep_ms(50); DtsDevRegisterWr( hDevice, DecHt_HostSwReset, 0x00000000 ); // Release c011 soft reset /* Disable Stuffing.. */ DtsFPGARegisterRead(hDevice,PCI_GLOBAL_CONTROL,&Val); Val |= BC_BIT(8); DtsFPGARegisterWr(hDevice,PCI_GLOBAL_CONTROL,Val); //DtsSetCoreClock(hDevice, 0); } else if(Ctx->DevId == BC_PCI_DEVID_FLEA) { // For Link, this is used to bring up 7412 and running. // Since the 70012 was running in low power mode, but the 7412 was not. // In flea there is no need for this. In general most of the chip will be in idle mode, // and should not be needed to reset in order to start up. // In Flea, we can never do full chip reset, because that will reset PCIe as well and // probably cause a BSOD. Individual blocks will have to be reset, either by asserting true resets // (but not from the host) or by re-initializing -like the ARM for example. } return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsSetLinkIn422Mode(HANDLE hDevice) { uint32_t Val = 0; DTS_LIB_CONTEXT *Ctx; uint32_t ModeSelect; DTS_GET_CTX(hDevice,Ctx); ModeSelect = Ctx->b422Mode; DebugLog_Trace(LDIL_DBG,"Setting Color Mode to %u\n", Ctx->b422Mode); /* * EN_WRITE_ALL BIT -Bit 20 * This bit dictates that weather the data will be xferred in * 1 - UYVY Mode. * 0 - YUY2 Mode. */ DtsFPGARegisterRead(hDevice,PCI_GLOBAL_CONTROL,&Val); if (ModeSelect == OUTPUT_MODE420) { Val &= 0xffeeffff; } else { Val |= BC_BIT(16); if(ModeSelect == OUTPUT_MODE422_UYVY) { Val |= BC_BIT(20); } else { Val &= ~BC_BIT(20); } } DtsFPGARegisterWr(hDevice,PCI_GLOBAL_CONTROL,Val); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsSetFleaIn422Mode(HANDLE hDevice) { uint32_t Val = 0; DTS_LIB_CONTEXT *Ctx; uint32_t ModeSelect; DTS_GET_CTX(hDevice,Ctx); ModeSelect = Ctx->b422Mode; // Flea HW only support UYVY/YUY2 if( ModeSelect != OUTPUT_MODE422_UYVY && ModeSelect != OUTPUT_MODE422_YUY2 ) return BC_STS_INV_ARG; DtsDevRegisterRead(hDevice,BCHP_MISC2_GLOBAL_CTRL,&Val); Val &= 0x0000007c; if( ModeSelect == OUTPUT_MODE422_YUY2 ) { Val |= BC_BIT(1); // bit_1 0-> UYVY, 1-> YUY2 } DtsDevRegisterWr(hDevice,BCHP_MISC2_GLOBAL_CTRL,Val); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsGetConfig( HANDLE hDevice, BC_DTS_CFG *cfg ) { DTS_LIB_CONTEXT *Ctx; DTS_GET_CTX(hDevice,Ctx); if(!cfg){ return BC_STS_INV_ARG; } *cfg = Ctx->CfgFlags; return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsSetConfig( HANDLE hDevice, BC_DTS_CFG *cfg ) { DTS_LIB_CONTEXT *Ctx; DTS_GET_CTX(hDevice,Ctx); if(!cfg){ return BC_STS_INV_ARG; } Ctx->CfgFlags = *cfg; return BC_STS_SUCCESS; } BC_STATUS DtsSetCoreClock( HANDLE hDevice, uint32_t freq ) { // uint32_t Val=0,clkRate=0, cnt; DTS_LIB_CONTEXT *Ctx; // uint32_t DevID,VendorID,Revision; uint32_t reg; uint32_t n, i; uint32_t vco_mg; uint32_t refresh_reg; DTS_GET_CTX(hDevice,Ctx); if(Ctx->DevId != BC_PCI_DEVID_LINK) { //DebugLog_Trace(LDIL_DBG,"DtsSetCoreClock is not supported in this device\n"); return BC_STS_ERROR; } #if 0 if(BC_STS_SUCCESS != DtsGetHwType(hDevice,&DevID,&VendorID,&Revision)) { DebugLog_Trace(LDIL_DBG,"Get Hardware Type Failed\n"); return BC_STS_INV_ARG; } if(DevID == BC_PCI_DEVID_LINK) { // Don't set the core clock return BC_STS_SUCCESS; } if(freq){ DebugLog_Trace(LDIL_DBG,"DtsSetCoreClock: Custom pll settings not implemented yet.\n"); return BC_STS_NOT_IMPL; } if(Ctx->CfgFlags & BC_DEC_VCLK_74MHZ){ clkRate = 0x000230f0; }else if(Ctx->CfgFlags & BC_DEC_VCLK_77MHZ){ clkRate = 0x000230f2; }else{ return BC_STS_INV_ARG; } #endif if(freq == 0) return BC_STS_SUCCESS; n = freq/5; //if (n == Ctx->prev_n) // return BC_STS_CLK_NOCHG; if ((n * 27) < 560) vco_mg = 0; else if ((n * 27) < 900) vco_mg = 1; else if ((n * 27) < 1030) vco_mg = 2; else vco_mg = 3; DtsDevRegisterRead(hDevice,DecHt_PllACtl, ®); reg &= 0xFFFFCFC0; reg |= n; reg |= vco_mg << 12; refresh_reg = (7 * freq / 16); DtsDevRegisterWr(hDevice,SDRAM_REF_PARAM,((1 << 12) | refresh_reg)); DtsDevRegisterWr(hDevice, DecHt_PllACtl, reg); DebugLog_Trace(LDIL_DBG,"Clock set to %d\n", freq); i = 0; while (i < 10) { DtsDevRegisterRead(hDevice,DecHt_PllACtl, ®); if (reg & 0x00020000) { //Ctx->prev_n = n; return BC_STS_SUCCESS; } else { bc_sleep_ms(10); } i++; } return BC_STS_ERROR; } DRVIFLIB_INT_API BC_STATUS DtsSetTSMode( HANDLE hDevice, uint32_t resv1 ) { uint32_t RegVal = 0; DTS_LIB_CONTEXT *Ctx; BOOL TsMode = TRUE; DTS_GET_CTX(hDevice,Ctx); if(Ctx->DevId != BC_PCI_DEVID_LINK && Ctx->DevId != BC_PCI_DEVID_DOZER) { DebugLog_Trace(LDIL_DBG,"DtsSetTSMode is not supported in this device\n"); return BC_STS_ERROR; } if(Ctx->FixFlags & DTS_LOAD_FILE_PLAY_FW) TsMode = FALSE; if(TsMode){ DtsFPGARegisterRead(hDevice,PCI_GLOBAL_CONTROL,&RegVal); RegVal &= 0xFFFFFFFE; //Reset Bit 0 DtsFPGARegisterWr(hDevice,PCI_GLOBAL_CONTROL,RegVal); }else{ // Set the FPGA up in non TS mode DtsFPGARegisterRead(hDevice,PCI_GLOBAL_CONTROL,&RegVal); RegVal |= 0x01; //Set Bit 0 DtsFPGARegisterWr(hDevice,PCI_GLOBAL_CONTROL,RegVal); } return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsSetProgressive( HANDLE hDevice, uint32_t resv1 ) { uint32_t RegVal; DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); if(Ctx->DevId != BC_PCI_DEVID_LINK && Ctx->DevId != BC_PCI_DEVID_DOZER) { return BC_STS_SUCCESS; } // Set the FPGA up in Progressive mode - i.e. 1 vsync/frame DtsFPGARegisterRead(hDevice,PCI_GLOBAL_CONTROL,&RegVal); RegVal |= 0x10; //Set Bit 4 DtsFPGARegisterWr(hDevice,PCI_GLOBAL_CONTROL,RegVal); return BC_STS_SUCCESS; } BC_STATUS DtsRstVidClkDLL( HANDLE hDevice) { uint32_t RegVal,Cnt=100; DtsFPGARegisterRead(hDevice,PCI_GLOBAL_CONTROL,&RegVal); RegVal |= 0x08; //Set Bit 3 the Reset Bit DtsFPGARegisterWr(hDevice,PCI_GLOBAL_CONTROL,RegVal); // // Wait for the bit to go low [Unlock] // while(Cnt) { DtsFPGARegisterRead(hDevice,PCI_INT_STS_REG,&RegVal); if(!(RegVal | 0x04) ) { break; }else{ bc_sleep_ms(100); Cnt--; } } bc_sleep_ms(100); DtsFPGARegisterRead(hDevice,PCI_GLOBAL_CONTROL,&RegVal); RegVal &= 0xfffffff7; //reset bit 3 DtsFPGARegisterWr(hDevice,PCI_GLOBAL_CONTROL,RegVal); RegVal=0; Cnt =100; while(Cnt) { DtsFPGARegisterRead(hDevice,PCI_INT_STS_REG,&RegVal); if(RegVal & 0x04) { // // This means that the video clock is locked. // return BC_STS_SUCCESS; }else{ bc_sleep_ms(100); Cnt--; } } DebugLog_Trace(LDIL_DBG,"DtsSetVideoClock: DLL did not lock.\n"); return BC_STS_ERROR; } DRVIFLIB_INT_API BC_STATUS DtsSetVideoClock( HANDLE hDevice, uint32_t freq ) { uint32_t Val=0; uint32_t clkRate = 0; DTS_LIB_CONTEXT *Ctx; uint32_t DevID,VendorID,Revision; DTS_GET_CTX(hDevice,Ctx); if(freq){ DebugLog_Trace(LDIL_DBG,"DtsSetVideoClock: Custom pll settings not implemented yet.\n"); return BC_STS_NOT_IMPL; } if(BC_STS_SUCCESS != DtsGetHwType(hDevice,&DevID,&VendorID,&Revision)) { DebugLog_Trace(LDIL_DBG,"Get Hardware Type Failed\n"); return BC_STS_INV_ARG; } if(DevID == BC_PCI_DEVID_LINK || DevID == BC_PCI_DEVID_FLEA) { // Don't set the video clock return BC_STS_SUCCESS; } if(Ctx->CfgFlags & BC_DEC_VCLK_74MHZ){ // Program PLL-E to 75 MHZ (n = 44, m = 10, vco_rng = 1) clkRate = 0x000012AC; }else if(Ctx->CfgFlags & BC_DEC_VCLK_77MHZ){ // Program PLL-E to 77 MHZ (n = ??, m = ??, vco_rng = ??) clkRate = 0x000012B0; }else{ return BC_STS_INV_ARG; } DtsDevRegisterWr( hDevice, DecHt_PllDCtl, 0x00010000); // Bypass PLL-D bc_sleep_ms(50); DtsDevRegisterRead( hDevice, DecHt_PllDCtl, &Val); if(Val != 0x00030000){ DebugLog_Trace(LDIL_DBG,"DtsSetVideoClock: Failed to change PLL_D_CTL\n"); //FIX_ME //return BC_STS_NO_ACCESS; } DtsDevRegisterWr( hDevice, DecHt_PllECtl, clkRate); bc_sleep_ms(50); DtsDevRegisterRead( hDevice, DecHt_PllECtl, &Val); if(Val != (clkRate | 0x00020000) ){ DebugLog_Trace(LDIL_DBG,"DtsSetVideoClock: Failed to change PLL_E_CTL\n"); //FIX_ME //return BC_STS_NO_ACCESS; } //if(BC_STS_SUCCESS != DtsRstVidClkDLL(hDevice)) //{ // DebugLog_Trace(LDIL_DBG,"DtsSetVideoClock: Vid Clk DLL Failed to Lock\n"); // return BC_STS_ERROR; //} return BC_STS_SUCCESS; } DRVIFLIB_INT_API BOOL DtsIsVideoClockSet(HANDLE hDevice) { uint32_t RegVal=0; DTS_LIB_CONTEXT *Ctx = NULL; uint32_t DevID,VendorID,Revision; DTS_GET_CTX(hDevice,Ctx); if(BC_STS_SUCCESS != DtsGetHwType(hDevice,&DevID,&VendorID,&Revision)) { DebugLog_Trace(LDIL_DBG,"Get Hardware Type Failed\n"); return FALSE; } if(DevID == BC_PCI_DEVID_LINK || DevID == BC_PCI_DEVID_FLEA) { // Don't set the video clock return FALSE; } if((Ctx->RegCfg.DbgOptions & BC_BIT(1)) && (Ctx->OpMode == DTS_PLAYBACK_MODE)) return FALSE; DtsFPGARegisterRead(hDevice,PCI_GLOBAL_CONTROL,&RegVal); if(RegVal & BC_BIT(0)) return TRUE; DtsFPGARegisterRead(hDevice,PCI_INT_STS_REG,&RegVal); return (RegVal & BC_BIT(2)); } DRVIFLIB_INT_API BC_STATUS DtsGetPciConfigSpace( HANDLE hDevice, uint8_t *info ) { BC_IOCTL_DATA *pIocData = NULL; BC_PCI_CFG *pciInfo; DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_SUCCESS; DTS_GET_CTX(hDevice,Ctx); if(!info) { DebugLog_Trace(LDIL_DBG,"DtsGetPciConfigSpace: Invlid Arguments\n"); return BC_STS_ERROR; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; pciInfo = (BC_PCI_CFG *)&pIocData->u.pciCfg; pciInfo->Size = PCI_CFG_SIZE; pciInfo->Offset = 0; memset(info,0, PCI_CFG_SIZE); if( (sts=DtsDrvCmd(Ctx,BCM_IOC_RD_PCI_CFG,0,pIocData,FALSE)) != BC_STS_SUCCESS){ DtsRelIoctlData(Ctx,pIocData); DebugLog_Trace(LDIL_DBG,"DtsGetPciConfigSpace: Ioctl failed: %d\n",sts); return sts; } memcpy(info,pciInfo->pci_cfg_space,PCI_CFG_SIZE); DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsDevRegisterRead( HANDLE hDevice, uint32_t offset, uint32_t *Value ) { BC_IOCTL_DATA *pIocData = NULL; BC_CMD_REG_ACC *reg_acc_read; DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_SUCCESS; DTS_GET_CTX(hDevice,Ctx); if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; reg_acc_read = (BC_CMD_REG_ACC *) &pIocData->u.regAcc; // // Prepare the command here. // reg_acc_read->Offset = offset; reg_acc_read->Value = 0; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_REG_RD,0,pIocData,FALSE)) != BC_STS_SUCCESS){ DtsRelIoctlData(Ctx,pIocData); DebugLog_Trace(LDIL_DBG,"DtsDevRegisterRead: Ioctl failed: %d\n",sts); return sts; } *Value = reg_acc_read->Value; DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsDevRegisterWr( HANDLE hDevice, uint32_t offset, uint32_t Value ) { BC_CMD_REG_ACC *reg_acc_wr; BC_IOCTL_DATA *pIocData = NULL; DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_SUCCESS; DTS_GET_CTX(hDevice, Ctx); if (!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; reg_acc_wr = (BC_CMD_REG_ACC *) &pIocData->u.regAcc; // Prepare the command here. reg_acc_wr->Offset = offset; reg_acc_wr->Value = Value; sts = DtsDrvCmd(Ctx, BCM_IOC_REG_WR, 0, pIocData, FALSE); if (sts != BC_STS_SUCCESS) DebugLog_Trace(LDIL_DBG,"DtsDevRegisterWr: Ioctl failed: %d\n", sts); DtsRelIoctlData(Ctx,pIocData); return sts; } DRVIFLIB_INT_API BC_STATUS DtsFPGARegisterRead( HANDLE hDevice, uint32_t offset, uint32_t *Value ) { BC_IOCTL_DATA *pIocData = NULL; BC_CMD_REG_ACC *reg_acc_read; DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_SUCCESS; DTS_GET_CTX(hDevice,Ctx); if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; reg_acc_read = (BC_CMD_REG_ACC *) &pIocData->u.regAcc; // // Prepare the command here. // reg_acc_read->Offset = offset; reg_acc_read->Value = 0; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FPGA_RD,0,pIocData,FALSE)) != BC_STS_SUCCESS){ DtsRelIoctlData(Ctx,pIocData); DebugLog_Trace(LDIL_DBG,"DtsFPGARegisterRead: Ioctl failed: %d\n",sts); return sts; } *Value = reg_acc_read->Value; DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsFPGARegisterWr( HANDLE hDevice, uint32_t offset, uint32_t Value ) { BC_CMD_REG_ACC *reg_acc_wr; BC_IOCTL_DATA *pIocData = NULL; DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_SUCCESS; DTS_GET_CTX(hDevice,Ctx); if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; reg_acc_wr = (BC_CMD_REG_ACC *) &pIocData->u.regAcc; // // Prepare the command here. // reg_acc_wr->Offset = offset; reg_acc_wr->Value = Value; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_FPGA_WR,0,pIocData,FALSE)) != BC_STS_SUCCESS){ DtsRelIoctlData(Ctx,pIocData); DebugLog_Trace(LDIL_DBG,"DtsFPGARegisterWr: Ioctl failed: %d\n",sts); return sts; } DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsDevMemRd( HANDLE hDevice, uint32_t *Buffer, uint32_t BuffSz, uint32_t Offset ) { uint8_t *pXferBuff; uint32_t IOcCode,size_in_dword; BC_IOCTL_DATA *pIoctlData; BC_CMD_DEV_MEM *pMemAccessRd; uint32_t BytesReturned,AllocSz; if(!hDevice) { DebugLog_Trace(LDIL_DBG,"DtsDevMemRd: Invalid Handle\n"); return BC_STS_INV_ARG; } if(!Buffer) { DebugLog_Trace(LDIL_DBG,"DtsDevMemRd: Null Buffer\n"); return BC_STS_INV_ARG; } if(BuffSz % 4) { DebugLog_Trace(LDIL_DBG,"DtsDevMemRd: Buff Size is not a multiple of DWORD\n"); return BC_STS_ERROR; } AllocSz = sizeof(BC_IOCTL_DATA) + (BuffSz); pIoctlData = (BC_IOCTL_DATA *) malloc(AllocSz); if(!pIoctlData) { DebugLog_Trace(LDIL_DBG,"DtsDevMemRd: Memory Allocation Failed\n"); return BC_STS_ERROR; } pXferBuff = ( ((PUCHAR)pIoctlData) + sizeof(BC_IOCTL_DATA)); pMemAccessRd = &pIoctlData->u.devMem; size_in_dword = BuffSz / 4; pIoctlData->RetSts = BC_STS_ERROR; pIoctlData->IoctlDataSz = sizeof(BC_IOCTL_DATA); pMemAccessRd->StartOff = Offset; memset(pXferBuff,'a',BuffSz); /* The size is passed in Bytes*/ pMemAccessRd->NumDwords = size_in_dword; IOcCode = BCM_IOC_MEM_RD; if(!DtsDrvIoctl(hDevice, BCM_IOC_MEM_RD, pIoctlData, AllocSz, pIoctlData, AllocSz, (LPDWORD)&BytesReturned, 0)) { DebugLog_Trace(LDIL_DBG,"DtsDevMemRd: DeviceIoControl Failed\n"); return BC_STS_ERROR; } if(BC_STS_ERROR == pIoctlData->RetSts) { DebugLog_Trace(LDIL_DBG,"DtsDevMemRd: IOCTL Cmd Failed By Driver\n"); return pIoctlData->RetSts; } memcpy(Buffer,pXferBuff,BuffSz); if(pIoctlData) free(pIoctlData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsDevMemWr( HANDLE hDevice, uint32_t *Buffer, uint32_t BuffSz, uint32_t Offset ) { uint8_t *pXferBuff; uint32_t IOcCode,size_in_dword; BC_IOCTL_DATA *pIoctlData; BC_CMD_DEV_MEM *pMemAccessRd; uint32_t BytesReturned,AllocSz; //pIoctlData = (BC_IOCTL_DATA *)malloc(sizeof(BC_IOCTL_DATA)); if(!hDevice) { DebugLog_Trace(LDIL_DBG,"DtsDevMemWr: Invalid Handle\n"); return BC_STS_INV_ARG; } if(!Buffer) { DebugLog_Trace(LDIL_DBG,"DtsDevMemWr: Null Buffer\n"); return BC_STS_INV_ARG; } if(BuffSz % 4) { DebugLog_Trace(LDIL_DBG,"DtsDevMemWr: Buff Size is not a multiple of DWORD\n"); return BC_STS_ERROR; } AllocSz = sizeof(BC_IOCTL_DATA) + (BuffSz); pIoctlData = (BC_IOCTL_DATA *) malloc(AllocSz); if(!pIoctlData) { DebugLog_Trace(LDIL_DBG,"DtsDevMemWr: Memory Allocation Failed\n"); return BC_STS_ERROR; } pXferBuff = ( ((PUCHAR)pIoctlData) + sizeof(BC_IOCTL_DATA)); pMemAccessRd = &pIoctlData->u.devMem; size_in_dword = BuffSz / 4; pIoctlData->RetSts = BC_STS_ERROR; pIoctlData->IoctlDataSz = sizeof(BC_IOCTL_DATA); pMemAccessRd->StartOff = Offset; memcpy(pXferBuff,Buffer,BuffSz); /* The size is passed in Bytes*/ pMemAccessRd->NumDwords = size_in_dword; IOcCode = BCM_IOC_MEM_WR; if(!DtsDrvIoctl(hDevice, BCM_IOC_MEM_WR, pIoctlData, AllocSz, pIoctlData, AllocSz, (LPDWORD)&BytesReturned, NULL)) { DebugLog_Trace(LDIL_DBG,"DtsDevMemWr: DeviceIoControl Failed\n"); return BC_STS_ERROR; } if(BC_STS_ERROR == pIoctlData->RetSts) { DebugLog_Trace(LDIL_DBG,"DtsDevMemWr: IOCTL Cmd Failed By Driver\n"); return pIoctlData->RetSts; } if(pIoctlData) free(pIoctlData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsTxDmaText( HANDLE hDevice , uint8_t *pUserData, uint32_t ulSizeInBytes, uint32_t *dramOff, uint8_t Encrypted) { BC_STATUS status = BC_STS_SUCCESS; uint32_t ulDmaSz; uint8_t *pDmaBuff; DTS_LIB_CONTEXT *Ctx = NULL; BC_IOCTL_DATA *pIocData = NULL; DTS_GET_CTX(hDevice,Ctx); if( (!pUserData) || (!ulSizeInBytes) || !dramOff) { return BC_STS_INV_ARG; } pDmaBuff = pUserData; ulDmaSz = ulSizeInBytes; if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; pIocData->RetSts = BC_STS_ERROR; pIocData->IoctlDataSz = sizeof(BC_IOCTL_DATA); pIocData->u.ProcInput.DramOffset =0; pIocData->u.ProcInput.pDmaBuff = pDmaBuff; pIocData->u.ProcInput.BuffSz = ulDmaSz; pIocData->u.ProcInput.Mapped = FALSE; pIocData->u.ProcInput.Encrypted = Encrypted; if(Ctx->VidParams.VideoAlgo == BC_VID_ALGO_VC1MP) pIocData->u.ProcInput.Encrypted|=0x2; status = DtsDrvCmd(Ctx,BCM_IOC_PROC_INPUT,1,pIocData,FALSE); *dramOff = pIocData->u.ProcInput.DramOffset; if( BC_STS_SUCCESS != status && BC_STS_IO_USER_ABORT != status) { DebugLog_Trace(LDIL_DBG,"DtsTxDmaText: DeviceIoControl Failed with Sts %d\n", status); } DtsRelIoctlData(Ctx,pIocData); DumpInputSampleToFile(pUserData,ulSizeInBytes); return status; } DRVIFLIB_INT_API BC_STATUS DtsCancelProcOutput( HANDLE hDevice, PVOID Context) { DTS_LIB_CONTEXT *Ctx = NULL; DTS_GET_CTX(hDevice,Ctx); return DtsCancelFetchOutInt(Ctx); } //------------------------------------------------------------------------ // Name: DtsChkYUVSizes // Description: Check Src/Dst buffer sizes with configured resolution. // // Vin: Strtucture received from HW // Vout: Structure got from App (Where data need to be copied) // //------------------------------------------------------------------------ DRVIFLIB_INT_API BC_STATUS DtsChkYUVSizes( DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *Vout, BC_DTS_PROC_OUT *Vin) { if (!Vout || !Vout->Ybuff || !Vin || !Vin->Ybuff){ return BC_STS_INV_ARG; } if((!Ctx->b422Mode) && (!Vout->UVbuff || !Vin->UVbuff)){ return BC_STS_INV_ARG; } /* Pass on size info irrespective of the status (for debug) */ Vout->YBuffDoneSz = Vin->YBuffDoneSz; Vout->UVBuffDoneSz = Vin->UVBuffDoneSz; /* Does Driver qualifies this condition before setting _PIB_VALID flag??..*/ if( !( Vin->YBuffDoneSz) || ((!Ctx->b422Mode) && (!Vin->UVBuffDoneSz)) ){ DebugLog_Trace(LDIL_DBG,"DtsChkYUVSizes: Incomplete Transfer\n"); return BC_STS_IO_XFR_ERROR; } /* Let the upper layer take care of this if(!(Vin->PoutFlags & BC_POUT_FLAGS_PIB_VALID)){ DebugLog_Trace(LDIL_DBG,"DtsChkYUVSizes: PIB not Valid\n"); return BC_STS_IO_XFR_ERROR; }*/ return BC_STS_SUCCESS; } /***/ DRVIFLIB_INT_API BC_STATUS DtsGetDrvStat( HANDLE hDevice, BC_DTS_STATS *pDrvStat ) { BC_IOCTL_DATA *pIocData = NULL; BC_DTS_STATS *pIntDrvStat; DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_SUCCESS; // float fTemperature = 0; DTS_GET_CTX(hDevice,Ctx); if(!pDrvStat) { DebugLog_Trace(LDIL_DBG,"DtsGetDrvStat: Invlid Arguments\n"); return BC_STS_ERROR; } if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; if(Ctx->SingleThreadedAppMode) pIocData->u.drvStat.DrvNextMDataPLD = pDrvStat->DrvNextMDataPLD; if( (sts=DtsDrvCmd(Ctx,BCM_IOC_GET_DRV_STAT,0,pIocData,FALSE)) != BC_STS_SUCCESS){ DtsRelIoctlData(Ctx,pIocData); DebugLog_Trace(LDIL_DBG,"DtsGetDriveStats: Ioctl failed: %d\n",sts); return sts; } /* DIL counters */ pIntDrvStat = DtsGetgStats ( ); //memcpy_s(pDrvStat, 128, pIntDrvStat, 128); memcpy(pDrvStat, pIntDrvStat, 128); /* Driver counters */ pIntDrvStat = (BC_DTS_STATS *)&pIocData->u.drvStat; pDrvStat->drvRLL = pIntDrvStat->drvRLL; pDrvStat->drvFLL = pIntDrvStat->drvFLL; pDrvStat->intCount = pIntDrvStat->intCount; pDrvStat->pauseCount = pIntDrvStat->pauseCount; pDrvStat->DrvIgnIntrCnt = pIntDrvStat->DrvIgnIntrCnt; pDrvStat->DrvTotalFrmDropped = pIntDrvStat->DrvTotalFrmDropped; pDrvStat->DrvTotalHWErrs = pIntDrvStat->DrvTotalHWErrs; pDrvStat->DrvTotalPIBFlushCnt = pIntDrvStat->DrvTotalPIBFlushCnt; pDrvStat->DrvTotalFrmCaptured = pIntDrvStat->DrvTotalFrmCaptured; pDrvStat->DrvPIBMisses = pIntDrvStat->DrvPIBMisses; pDrvStat->DrvPauseTime = pIntDrvStat->DrvPauseTime; pDrvStat->DrvRepeatedFrms = pIntDrvStat->DrvRepeatedFrms; pDrvStat->TxFifoBsyCnt = pIntDrvStat->TxFifoBsyCnt; pDrvStat->pwr_state_change = pIntDrvStat->pwr_state_change; pDrvStat->DrvNextMDataPLD = pIntDrvStat->DrvNextMDataPLD; pDrvStat->DrvcpbEmptySize = pIntDrvStat->DrvcpbEmptySize; pDrvStat->eosDetected = pIntDrvStat->eosDetected; pDrvStat->picNumFlags = pIntDrvStat->picNumFlags; // DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } DRVIFLIB_INT_API BC_STATUS DtsSetTemperatureMeasure( HANDLE hDevice, BOOL bTurnOn ) { DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_SUCCESS; uint32_t Val = 0; DTS_GET_CTX(hDevice,Ctx); if( Ctx->DevId != BC_PCI_DEVID_FLEA ) { DebugLog_Trace(LDIL_DBG,"DtsSetTemperatureMeasure Only support for Flea.\n"); return BC_STS_SUCCESS; } if( bTurnOn ) { Val = 0x3; // sts = DtsDevRegisterWr(hDevice,BCHP_CLK_TEMP_MON_CTRL,Val); bc_sleep_ms(10); Val = 0x203; // sts = DtsDevRegisterWr(hDevice,BCHP_CLK_TEMP_MON_CTRL,Val); bc_sleep_ms(10); } else { Val = 0x103; // sts = DtsDevRegisterWr(hDevice,BCHP_CLK_TEMP_MON_CTRL,Val); bc_sleep_ms(10); } return sts; } DRVIFLIB_INT_API BC_STATUS DtsGetCoreTemperature( HANDLE hDevice, float *pTemperature ) { DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_ERROR; uint32_t Val = 0; *pTemperature = 0; DTS_GET_CTX(hDevice,Ctx); if( Ctx->DevId != BC_PCI_DEVID_FLEA ) { DebugLog_Trace(LDIL_DBG,"DtsSetTemperatureMeasure Only support for Flea.\n"); return BC_STS_SUCCESS; } sts = DtsDevRegisterRead(hDevice,BCHP_CLK_TEMP_MON_STATUS,&Val); if( sts != BC_STS_SUCCESS ) return sts; Val = Val & 0x0000ffff; *pTemperature = 267.2 - 0.7 * (float)Val; return sts; } DRVIFLIB_INT_API BC_STATUS DtsRstDrvStat( HANDLE hDevice ) { BC_IOCTL_DATA *pIocData = NULL; DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_SUCCESS; DTS_GET_CTX(hDevice,Ctx); /* CHECK WHETHER NULL pIocData CAN BE PASSED */ if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; /* Driver related counters */ if( (sts=DtsDrvCmd(Ctx,BCM_IOC_RST_DRV_STAT,0,pIocData,FALSE)) != BC_STS_SUCCESS){ DtsRelIoctlData(Ctx,pIocData); DebugLog_Trace(LDIL_DBG,"DtsRstDrvStats: Ioctl failed: %d\n",sts); return sts; } /* DIL related counters */ DtsRstStats( ); DtsRelIoctlData(Ctx,pIocData); return BC_STS_SUCCESS; } /**/ /* Get firmware files */ DRVIFLIB_INT_API BC_STATUS DtsGetFWFiles( HANDLE hDevice, char *StreamFName, char *VDecOuter, char *VDecInner ) { DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_SUCCESS; DTS_GET_CTX(hDevice,Ctx); sts = DtsGetFirmwareFiles(Ctx); if(sts == BC_STS_SUCCESS){ strncpy(StreamFName, Ctx->StreamFile, MAX_PATH); strncpy(VDecOuter, Ctx->VidOuter, MAX_PATH); strncpy(VDecInner, Ctx->VidInner, MAX_PATH ); }else{ return sts; } return sts; } /**/ DRVIFLIB_INT_API BC_STATUS DtsDownloadFWBin(HANDLE hDevice, uint8_t *binBuff, uint32_t buffsize, uint32_t dramOffset) { BC_STATUS rstatus = BC_STS_SUCCESS; /* Write bootloader vector table section */ rstatus = DtsDevMemWr(hDevice,(uint32_t *)binBuff,buffsize,dramOffset); if (BC_STS_SUCCESS != rstatus) { DebugLog_Trace(LDIL_DBG,"DtsDownloadFWBin: Fw Download Failed\n"); } return rstatus; } BC_STATUS DtsCopyRawDataToOutBuff(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *Vout, BC_DTS_PROC_OUT *Vin) { uint32_t y,lDestStride=0; uint8_t *pSrc = NULL, *pDest=NULL; uint32_t dstWidthInPixels, dstHeightInPixels; uint32_t srcWidthInPixels = 0, srcHeightInPixels; BC_STATUS Sts = BC_STS_SUCCESS; if ( (Sts = DtsChkYUVSizes(Ctx,Vout,Vin)) != BC_STS_SUCCESS) return Sts; if(Vout->PoutFlags & BC_POUT_FLAGS_STRIDE) lDestStride = Vout->StrideSz; if(Vout->PoutFlags & BC_POUT_FLAGS_SIZE) { // Use DShow provided size for now dstWidthInPixels = Vout->PicInfo.width; if(!Ctx->VidParams.Progressive) dstHeightInPixels = Vout->PicInfo.height/2; else dstHeightInPixels = Vout->PicInfo.height; /* Check for Valid data based on the filter information */ /* interlaced frames currently don't get delivered from the library if this check is in place */ #if 0 if(Vout->YBuffDoneSz < (dstWidthInPixels * dstHeightInPixels / 2)) { DebugLog_Trace(LDIL_DBG,"DtsCopy422: XFER ERROR dnsz %u, w %u, h %u\n", Vout->YBuffDoneSz, dstWidthInPixels, dstHeightInPixels); return BC_STS_IO_XFR_ERROR; } #endif srcWidthInPixels = Ctx->HWOutPicWidth; srcHeightInPixels = dstHeightInPixels; } else { dstWidthInPixels = Vin->PicInfo.width; dstHeightInPixels = Vin->PicInfo.height; } lDestStride = lDestStride*2; dstWidthInPixels = dstWidthInPixels*2; srcWidthInPixels = srcWidthInPixels*2; // Do a strided copy only if the stride is non-zero if( (lDestStride != 0)|| (srcWidthInPixels != dstWidthInPixels) ) { // Y plane pDest = Vout->Ybuff; pSrc = Vin->Ybuff; for (y = 0; y < dstHeightInPixels; y++){ memcpy(pDest,pSrc,dstWidthInPixels); //memcpy_fast(pDest,pSrc,dstWidthInPixels*2); pDest += dstWidthInPixels + lDestStride; pSrc += (srcWidthInPixels); } } else { // Y Plane memcpy(Vout->Ybuff, Vin->Ybuff, dstHeightInPixels * dstWidthInPixels); //memcpy_fast(Vout->Ybuff, Vin->Ybuff, dstHeightInPixels * dstWidthInPixels * 2); } return BC_STS_SUCCESS; } /***/ //FIX_ME:: This routine assumes, Y & UV buffs are contiguous.. BC_STATUS DtsCopyNV12ToYV12(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *Vout, BC_DTS_PROC_OUT *Vin) { uint8_t *buff=NULL; uint8_t *yv12buff = NULL; uint32_t uvbase=0; BC_STATUS Sts = BC_STS_SUCCESS; uint32_t x,y,lDestStrideY=0, lDestStrideUV=0; uint8_t *pSrc = NULL, *pDest=NULL; uint32_t dstWidthInPixels, dstHeightInPixels; uint32_t srcWidthInPixels, srcHeightInPixels; if ( (Sts = DtsChkYUVSizes(Ctx,Vout,Vin)) != BC_STS_SUCCESS) return Sts; if(Vout->PoutFlags & BC_POUT_FLAGS_SIZE)// needs to be optimized. { if(Vout->PoutFlags & BC_POUT_FLAGS_STRIDE) lDestStrideUV = (lDestStrideY = Vout->StrideSz)/2; if(Vout->PoutFlags & BC_POUT_FLAGS_STRIDE_UV) lDestStrideUV = Vout->StrideSzUV; // Use DShow provided size for now dstWidthInPixels = Vout->PicInfo.width; if(!Ctx->VidParams.Progressive) dstHeightInPixels = Vout->PicInfo.height/2; else dstHeightInPixels = Vout->PicInfo.height; /* Check for Valid data based on the filter information */ if((Vout->YBuffDoneSz < (dstWidthInPixels * dstHeightInPixels / 4)) || (Vout->UVBuffDoneSz < (dstWidthInPixels * dstHeightInPixels/2 / 4))) { DebugLog_Trace(LDIL_DBG,"DtsCopyYV12: XFER ERROR\n"); return BC_STS_IO_XFR_ERROR; } srcWidthInPixels = Ctx->HWOutPicWidth; srcHeightInPixels = dstHeightInPixels; //copy luma pDest = Vout->Ybuff; pSrc = Vin->Ybuff; for (y = 0; y < dstHeightInPixels; y++) { memcpy(pDest,pSrc,dstWidthInPixels); pDest += dstWidthInPixels + lDestStrideY; pSrc += srcWidthInPixels; } //copy chroma pDest = Vout->UVbuff; pSrc = Vin->UVbuff; uvbase = (dstWidthInPixels + lDestStrideY) * dstHeightInPixels/4 ;//(Vin->UVBuffDoneSz * 4/2); for (y = 0; y < dstHeightInPixels/2; y++) { for(x = 0; x < dstWidthInPixels; x += 2) { pDest[x/2] = pSrc[x+1]; pDest[uvbase + x/2] = pSrc[x]; } pDest += dstWidthInPixels / 2 + lDestStrideUV; pSrc += srcWidthInPixels; } } else { /* Y-Buff loop */ buff = Vin->Ybuff; yv12buff = Vout->Ybuff; for(uint32_t i = 0; i < Vin->YBuffDoneSz*4; i += 2) { yv12buff[i] = buff[i]; yv12buff[i+1] = buff[i+1]; } /* UV-Buff loop */ buff = Vin->UVbuff; yv12buff = Vout->UVbuff; uvbase = (Vin->UVBuffDoneSz * 4/2); for(uint32_t i = 0; i < Vin->UVBuffDoneSz*4; i += 2) { yv12buff[i/2] = buff[i+1]; yv12buff[uvbase + (i/2)] = buff[i]; } } return BC_STS_SUCCESS; } BC_STATUS DtsCopyNV12(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *Vout, BC_DTS_PROC_OUT *Vin) { uint32_t y,lDestStrideY=0,lDestStrideUV=0; uint8_t *pSrc = NULL, *pDest=NULL; uint32_t dstWidthInPixels, dstHeightInPixels; uint32_t srcWidthInPixels=0, srcHeightInPixels; BC_STATUS Sts = BC_STS_SUCCESS; if ( (Sts = DtsChkYUVSizes(Ctx,Vout,Vin)) != BC_STS_SUCCESS) return Sts; if(Vout->PoutFlags & BC_POUT_FLAGS_STRIDE) lDestStrideUV = lDestStrideY = Vout->StrideSz; if(Vout->PoutFlags & BC_POUT_FLAGS_STRIDE_UV) lDestStrideUV = Vout->StrideSzUV; if(Vout->PoutFlags & BC_POUT_FLAGS_SIZE) { // Use DShow provided size for now dstWidthInPixels = Vout->PicInfo.width; if(!Ctx->VidParams.Progressive) dstHeightInPixels = Vout->PicInfo.height/2; else dstHeightInPixels = Vout->PicInfo.height; /* Check for Valid data based on the filter information */ if((Vout->YBuffDoneSz < (dstWidthInPixels * dstHeightInPixels / 4)) || (Vout->UVBuffDoneSz < (dstWidthInPixels * dstHeightInPixels/2 / 4))) return BC_STS_IO_XFR_ERROR; srcWidthInPixels = Ctx->HWOutPicWidth; srcHeightInPixels = dstHeightInPixels; } else { dstWidthInPixels = Vin->PicInfo.width; dstHeightInPixels = Vin->PicInfo.height; } // NV12 is planar: Y plane, followed by packed U-V plane. // Do a strided copy only if the stride is non-zero if((lDestStrideY != 0) || (lDestStrideUV != 0) || (srcWidthInPixels != dstWidthInPixels)) { // Y plane pDest = Vout->Ybuff; pSrc = Vin->Ybuff; for (y = 0; y < dstHeightInPixels; y++){ memcpy(pDest,pSrc,dstWidthInPixels); pDest += dstWidthInPixels + lDestStrideY; pSrc += srcWidthInPixels; } // U-V plane pDest = Vout->UVbuff; pSrc = Vin->UVbuff; for (y = 0; y < dstHeightInPixels/2; y++){ memcpy(pDest,pSrc,dstWidthInPixels); pDest += dstWidthInPixels + lDestStrideUV; pSrc += srcWidthInPixels; } } else { // Y Plane memcpy(Vout->Ybuff, Vin->Ybuff, dstHeightInPixels * dstWidthInPixels); // UV Plane memcpy(Vout->UVbuff, Vin->UVbuff, dstHeightInPixels/2 * dstWidthInPixels); } return BC_STS_SUCCESS; } // TODO: add sse2 detection static bool gSSE2 = true; // most of the platforms will have it anyway: // 64 bits: no test necessary // mac: no test necessary // linux/windows: we might have to do the test. static void fast_memcpy(uint8_t *dst, const uint8_t *src, uint32_t count) { // tested if (gSSE2) { if (((((uintptr_t) dst) & 0xf) == 0) && ((((uintptr_t) src) & 0xf) == 0)) { while (count >= (16*4)) { _mm_stream_si128((__m128i *) (dst+ 0*16), _mm_load_si128((__m128i *) (src+ 0*16))); _mm_stream_si128((__m128i *) (dst+ 1*16), _mm_load_si128((__m128i *) (src+ 1*16))); _mm_stream_si128((__m128i *) (dst+ 2*16), _mm_load_si128((__m128i *) (src+ 2*16))); _mm_stream_si128((__m128i *) (dst+ 3*16), _mm_load_si128((__m128i *) (src+ 3*16))); count -= 16*4; src += 16*4; dst += 16*4; } } else { while (count >= (16*4)) { _mm_storeu_si128((__m128i *) (dst+ 0*16), _mm_loadu_si128((__m128i *) (src+ 0*16))); _mm_storeu_si128((__m128i *) (dst+ 1*16), _mm_loadu_si128((__m128i *) (src+ 1*16))); _mm_storeu_si128((__m128i *) (dst+ 2*16), _mm_loadu_si128((__m128i *) (src+ 2*16))); _mm_storeu_si128((__m128i *) (dst+ 3*16), _mm_loadu_si128((__m128i *) (src+ 3*16))); count -= 16*4; src += 16*4; dst += 16*4; } } } while (count --) *dst++ = *src++; } // this is not good. // if we have 3 buffers, we cannot assume V is after U static BC_STATUS DtsCopy422ToYV12(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) { // copy YUY2 to YV12 // TODO // NOTE: if we want to support this porperly, we will need to add a Vbuffer pointer // if we have 3 destination buffers, there's no guarantee that V buffer is derivable from UV pointer. return BC_STS_INV_ARG; } // this is just a memcpy static BC_STATUS DtsCopy422ToYUY2(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) { // copy YUY2 to YUY2 uint32_t y; // TODO: test this strideY += dstWidth*2; for (y = 0; y < height; y++) { fast_memcpy(dstY, srcY, srcWidth*2); srcY += srcWidth*2; dstY += strideY; } return BC_STS_SUCCESS; } // almost a memcpy, we just need to shuffle YUV's around static BC_STATUS DtsCopy422ToUYVY(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) { // TODO, test this uint32_t x = 0, __y; strideY += dstWidth*2; for (__y = 0; __y < height; __y++) { if (gSSE2) { if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) { while (x < srcWidth-7) { __m128i v = _mm_load_si128((__m128i *)(srcY+x*2)); __m128i v1 = _mm_srli_epi16(v, 8); __m128i v2 = _mm_slli_epi16(v, 8); _mm_stream_si128((__m128i *)(dstY+x*2), _mm_or_si128(v1, v2)); x += 8; } } else { while (x < srcWidth-7) { __m128i v = _mm_loadu_si128((__m128i *)(srcY+x*2)); __m128i v1 = _mm_srli_epi16(v, 8); __m128i v2 = _mm_slli_epi16(v, 8); _mm_storeu_si128((__m128i *)(dstY+x*2), _mm_or_si128(v1, v2)); x += 8; } } } while (x < srcWidth-1) { dstY[x*2+0] = srcY[x+1]; dstY[x*2+1] = srcY[x+0]; dstY[x*2+2] = srcY[x+3]; dstY[x*2+3] = srcY[x+2]; x += 2; } srcY += srcWidth*2; dstY += strideY; } return BC_STS_SUCCESS; } // convert to NV12 static BC_STATUS DtsCopy422ToNV12(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) { // tested uint32_t x, __y; strideY += dstWidth; strideUV += dstWidth; static __m128i mask = _mm_set_epi16(0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff, 0x00ff); for (__y = 0; __y < height; __y += 2) { x = 0; // first line: Y and UV extraction if (gSSE2) { if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0) && ((((uintptr_t) dstUV) & 0xf) == 0)) { while (x < srcWidth-15) { __m128i s1 = _mm_load_si128((__m128i *) (srcY+x*2+ 0)); // load 8 pixels __m128i s2 = _mm_load_si128((__m128i *) (srcY+x*2+16)); // load 8 more __m128i y1 = _mm_and_si128(s1, mask); // mask out uvs __m128i y2 = _mm_and_si128(s2, mask); // mask out uvs __m128i y = _mm_packus_epi16 (y1, y2); // get the y together _mm_stream_si128((__m128i *) (dstY+x), y); // store 16 Y s1 = _mm_srli_epi16(s1, 8); // get rid of Y s2 = _mm_srli_epi16(s2, 8); // get rid of Y __m128i uv = _mm_packus_epi16 (s1, s2); // get the uv together _mm_stream_si128((__m128i *) (dstUV+x), uv); // store 8 UV pairs x += 16; } } else { while (x < srcWidth-15) { __m128i s1 = _mm_loadu_si128((__m128i *) (srcY+x*2+ 0)); // load 8 pixels __m128i s2 = _mm_loadu_si128((__m128i *) (srcY+x*2+16)); // load 8 more __m128i y1 = _mm_and_si128(s1, mask); // mask out uvs __m128i y2 = _mm_and_si128(s2, mask); // mask out uvs __m128i y = _mm_packus_epi16 (y1, y2); // get the y together _mm_storeu_si128((__m128i *) (dstY+x), y); // store 16 Y s1 = _mm_srli_epi16(s1, 8); // get rid of Y s2 = _mm_srli_epi16(s2, 8); // get rid of Y __m128i uv = _mm_packus_epi16 (s1, s2); // get the uv together _mm_storeu_si128((__m128i *) (dstUV+x), uv); // store 8 UV pairs x += 16; } } } while (x < srcWidth-1) { dstY [x+0] = srcY[x*2+0]; // Y dstUV[x+0] = srcY[x*2+1]; // U dstY [x+1] = srcY[x*2+2]; // Y dstUV[x+1] = srcY[x*2+3]; // V x += 2; } srcY += srcWidth*2; dstY += strideY; dstUV += strideUV; // second line: just Y x = 0; if (gSSE2) { if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) { while (x < srcWidth-15) { __m128i s1 = _mm_load_si128((__m128i *) (srcY+x*2+ 0)); // load 8 pixels __m128i s2 = _mm_load_si128((__m128i *) (srcY+x*2+16)); // load 8 more __m128i y1 = _mm_and_si128(s1, mask); // mask out uvs __m128i y2 = _mm_and_si128(s2, mask); // mask out uvs __m128i y = _mm_packus_epi16 (y1, y2); // get the y _mm_stream_si128((__m128i *) (dstY+x), y); // store 16 Y x += 16; } } else { while (x < srcWidth-15) { __m128i s1 = _mm_loadu_si128((__m128i *) (srcY+x*2+ 0)); // load 8 pixels __m128i s2 = _mm_loadu_si128((__m128i *) (srcY+x*2+16)); // load 8 more __m128i y1 = _mm_and_si128(s1, mask); // mask out uvs __m128i y2 = _mm_and_si128(s2, mask); // mask out uvs __m128i y = _mm_packus_epi16 (y1, y2); // get the y _mm_storeu_si128((__m128i *) (dstY+x), y); // store 16 Y x += 16; } } } while (x < srcWidth-1) { dstY [x+0] = srcY[x*2+0]; // Y dstY [x+1] = srcY[x*2+2]; // Y x += 2; } srcY += srcWidth*2; dstY += strideY; } return BC_STS_SUCCESS; } // this is not good. // if we have 3 textures, we cannot assume V is after U static BC_STATUS DtsCopy420ToYV12(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, const uint8_t *srcUV, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) { // TODO // NOTE: if we want to support this porperly, we will need to add a Vbuffer pointer return BC_STS_INV_ARG; } static BC_STATUS DtsCopy420ToYUY2(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, const uint8_t *srcUV, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) { // TODO, test this uint32_t x, __y; strideY += dstWidth*2; __y = 0; while (__y < height-2) { // first line x = 0; if (gSSE2) { if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) { while (x < srcWidth-15) { __m128i y = _mm_load_si128((__m128i *) (srcY+x)); // load 16 Y pixels __m128i uv = _mm_load_si128((__m128i *) (srcUV+x)); // load 8 UV _mm_stream_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(y, uv)); // store 8 pixels _mm_stream_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(y, uv)); // store 8 pixels x += 16; } } else { while (x < srcWidth-15) { __m128i y = _mm_loadu_si128((__m128i *) (srcY+x)); // load 16 Y pixels __m128i uv = _mm_loadu_si128((__m128i *) (srcUV+x)); // load 8 UV _mm_storeu_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(y, uv)); // store 8 pixels _mm_storeu_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(y, uv)); // store 8 pixels x += 16; } } } while (x < srcWidth-1) { dstY[x*2+0] = srcY [x+0]; dstY[x*2+1] = srcUV[x+0]; dstY[x*2+2] = srcY [x+1]; dstY[x*2+3] = srcUV[x+1]; x += 2; } srcY += srcWidth; dstY += strideY; // second line x = 0; if (gSSE2) { if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) { while (x < srcWidth-15) { __m128i y = _mm_load_si128((__m128i *) (srcY+x)); // load 16 Y pixels __m128i uv1 = _mm_load_si128((__m128i *) (srcUV+x)); // load 8 UV __m128i uv2 = _mm_load_si128((__m128i *) (srcUV+x+srcWidth)); // load 8 UV __m128i uv = _mm_avg_epu8(uv1, uv2); _mm_stream_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(y, uv)); // store 8 pixels _mm_stream_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(y, uv)); // store 8 pixels x += 16; } } else { while (x < srcWidth-15) { __m128i y = _mm_loadu_si128((__m128i *) (srcY+x)); // load 16 Y pixels __m128i uv1 = _mm_loadu_si128((__m128i *) (srcUV+x)); // load 8 UV __m128i uv2 = _mm_loadu_si128((__m128i *) (srcUV+x+srcWidth)); // load 8 UV __m128i uv = _mm_avg_epu8(uv1, uv2); _mm_storeu_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(y, uv)); // store 8 pixels _mm_storeu_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(y, uv)); // store 8 pixels x += 16; } } } while (x < srcWidth-1) { dstY[x*2+0] = srcY [x+0]; dstY[x*2+1] = (srcUV[x+0] + srcUV[x+0+srcWidth])/2; dstY[x*2+2] = srcY [x+1]; dstY[x*2+3] = (srcUV[x+1] + srcUV[x+1+srcWidth])/2; x += 2; } srcY += srcWidth; srcUV += srcWidth; dstY += strideY; __y += 2; } // last 2 lines while (__y < height) { x = 0; if (gSSE2) { if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) { while (x < srcWidth-15) { __m128i y = _mm_load_si128((__m128i *) (srcY+x)); // load 16 Y pixels __m128i uv = _mm_load_si128((__m128i *) (srcUV+x)); // load 8 UV _mm_stream_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(y, uv)); // store 8 pixels _mm_stream_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(y, uv)); // store 8 pixels x += 16; } } else { while (x < srcWidth-15) { __m128i y = _mm_loadu_si128((__m128i *) (srcY+x)); // load 16 Y pixels __m128i uv = _mm_loadu_si128((__m128i *) (srcUV+x)); // load 8 UV _mm_storeu_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(y, uv)); // store 8 pixels _mm_storeu_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(y, uv)); // store 8 pixels x += 16; } } } while (x < srcWidth-1) { dstY[x*2+0] = srcY [x+0]; dstY[x*2+1] = srcUV[x+0]; dstY[x*2+2] = srcY [x+1]; dstY[x*2+3] = srcUV[x+1]; x += 2; } srcY += srcWidth; dstY += strideY; __y++; } return BC_STS_SUCCESS; } static BC_STATUS DtsCopy420ToUYVY(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, const uint8_t *srcUV, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) { // TODO, test this uint32_t x, __y; strideY += dstWidth*2; __y = 0; while (__y < height-2) { // first line x = 0; if (gSSE2) { if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) { while (x < srcWidth-15) { __m128i y = _mm_load_si128((__m128i *) (srcY+x)); // load 16 Y pixels __m128i uv = _mm_load_si128((__m128i *) (srcUV+x)); // load 8 UV _mm_stream_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(uv, y)); // store 8 pixels _mm_stream_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(uv, y)); // store 8 pixels x += 16; } } else { while (x < srcWidth-15) { __m128i y = _mm_loadu_si128((__m128i *) (srcY+x)); // load 16 Y pixels __m128i uv = _mm_loadu_si128((__m128i *) (srcUV+x)); // load 8 UV _mm_storeu_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(uv, y)); // store 8 pixels _mm_storeu_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(uv, y)); // store 8 pixels x += 16; } } } while (x < srcWidth-1) { dstY[x*2+1] = srcY [x+0]; dstY[x*2+0] = srcUV[x+0]; dstY[x*2+3] = srcY [x+1]; dstY[x*2+2] = srcUV[x+1]; x += 2; } srcY += srcWidth; dstY += strideY; // second line x = 0; if (gSSE2) { if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) { while (x < srcWidth-15) { __m128i y = _mm_load_si128((__m128i *) (srcY+x)); // load 16 Y pixels __m128i uv1 = _mm_load_si128((__m128i *) (srcUV+x)); // load 8 UV __m128i uv2 = _mm_load_si128((__m128i *) (srcUV+x+srcWidth)); // load 8 UV __m128i uv = _mm_avg_epu8(uv1, uv2); _mm_stream_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(uv, y)); // store 8 pixels _mm_stream_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(uv, y)); // store 8 pixels x += 16; } } else { while (x < srcWidth-15) { __m128i y = _mm_loadu_si128((__m128i *) (srcY+x)); // load 16 Y pixels __m128i uv1 = _mm_loadu_si128((__m128i *) (srcUV+x)); // load 8 UV __m128i uv2 = _mm_loadu_si128((__m128i *) (srcUV+x+srcWidth)); // load 8 UV __m128i uv = _mm_avg_epu8(uv1, uv2); _mm_storeu_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(uv, y)); // store 8 pixels _mm_storeu_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(uv, y)); // store 8 pixels x += 16; } } } while (x < srcWidth-1) { dstY[x*2+1] = srcY [x+0]; dstY[x*2+0] = (srcUV[x+0] + srcUV[x+0+srcWidth])/2; dstY[x*2+3] = srcY [x+1]; dstY[x*2+2] = (srcUV[x+1] + srcUV[x+1+srcWidth])/2; x += 2; } srcY += srcWidth; srcUV += srcWidth; dstY += strideY; } // last 2 lines while (__y < height) { x = 0; if (gSSE2) { if (((((uintptr_t) dstY) & 0xf) == 0) && ((((uintptr_t) srcY) & 0xf) == 0)) { while (x < srcWidth-15) { __m128i y = _mm_load_si128((__m128i *) (srcY+x)); // load 16 Y pixels __m128i uv = _mm_load_si128((__m128i *) (srcUV+x)); // load 8 UV _mm_stream_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(uv, y)); // store 8 pixels _mm_stream_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(uv, y)); // store 8 pixels x += 16; } } else { while (x < srcWidth-15) { __m128i y = _mm_loadu_si128((__m128i *) (srcY+x)); // load 16 Y pixels __m128i uv = _mm_loadu_si128((__m128i *) (srcUV+x)); // load 8 UV _mm_storeu_si128((__m128i *) (dstY+x*2+ 0), _mm_unpacklo_epi8(uv, y)); // store 8 pixels _mm_storeu_si128((__m128i *) (dstY+x*2+16), _mm_unpackhi_epi8(uv, y)); // store 8 pixels x += 16; } } } while (x < srcWidth-1) { dstY[x*2+1] = srcY [x+0]; dstY[x*2+0] = srcUV[x+0]; dstY[x*2+3] = srcY [x+1]; dstY[x*2+2] = srcUV[x+1]; x += 2; } srcY += srcWidth; dstY += strideY; __y++; } return BC_STS_SUCCESS; } static BC_STATUS DtsCopy420ToNV12(uint8_t *dstY, uint8_t *dstUV, const uint8_t *srcY, const uint8_t *srcUV, uint32_t srcWidth, uint32_t dstWidth, uint32_t height, uint32_t strideY, uint32_t strideUV) { // tested uint32_t __y; strideY += dstWidth; strideUV += dstWidth; // first copy Y for (__y = 0; __y < height; __y++) { fast_memcpy(dstY, srcY, srcWidth); dstY += strideY; srcY += srcWidth; } // now copy uvs height /= 2; for (__y = 0; __y < height; __y++) { fast_memcpy(dstUV, srcUV, srcWidth); srcUV += srcWidth; dstUV += strideUV; } return BC_STS_SUCCESS; } // copy 422/420 ( device format to format specified in Vout) BC_STATUS DtsCopyFormat(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *Vout, BC_DTS_PROC_OUT *Vin) { uint32_t lDestStrideY=0, lDestStrideUV=0; uint32_t dstHeightInPixels; BC_STATUS Sts = BC_STS_SUCCESS; if ( (Sts = DtsChkYUVSizes(Ctx,Vout,Vin)) != BC_STS_SUCCESS) return Sts; if(Vout->PoutFlags & BC_POUT_FLAGS_STRIDE) lDestStrideUV = lDestStrideY = Vout->StrideSz; if(Vout->PoutFlags & BC_POUT_FLAGS_STRIDE_UV) lDestStrideUV = Vout->StrideSzUV; if(Vout->PoutFlags & BC_POUT_FLAGS_SIZE) { // Use application provided size for now if(!Ctx->VidParams.Progressive) dstHeightInPixels = Vout->PicInfo.height/2; else dstHeightInPixels = Vout->PicInfo.height; /* Check for Valid data based on the application information */ // we cannot do that any more.size may vary, we have to suppose them // ok // if((Vout->YBuffDoneSz < (dstWidthInPixels * dstHeightInPixels / 4)) || // (Vout->UVBuffDoneSz < (dstWidthInPixels * dstHeightInPixels/2 / 4))) // return BC_STS_IO_XFR_ERROR; } else { dstHeightInPixels = Vin->PicInfo.height; } // check that we can do the copy properly if (Ctx->HWOutPicWidth > Vin->PicInfo.width) return BC_STS_IO_XFR_ERROR; //DebugLog_Trace(LDIL_DBG,"Copying from %d to %d\n", Ctx->b422Mode, Vout->b422Mode); if (Ctx->b422Mode) { // input is 422 (YUY2) switch (Vout->b422Mode) { case OUTPUT_MODE422_YUY2: Sts = DtsCopy422ToYUY2( Vout->Ybuff, Vout->UVbuff, Vin->Ybuff, Ctx->HWOutPicWidth, Vin->PicInfo.width, dstHeightInPixels, lDestStrideY, lDestStrideUV ); break; case OUTPUT_MODE422_UYVY: Sts = DtsCopy422ToUYVY( Vout->Ybuff, Vout->UVbuff, Vin->Ybuff, Ctx->HWOutPicWidth, Vin->PicInfo.width, dstHeightInPixels, lDestStrideY, lDestStrideUV ); break; case OUTPUT_MODE420_NV12: Sts = DtsCopy422ToNV12( Vout->Ybuff, Vout->UVbuff, Vin->Ybuff, Ctx->HWOutPicWidth, Vin->PicInfo.width, dstHeightInPixels, lDestStrideY, lDestStrideUV ); break; default: Sts = BC_STS_INV_ARG; break; } }else{ // input is 420 (NV12) switch (Vout->b422Mode) { case OUTPUT_MODE422_YUY2: Sts = DtsCopy420ToYUY2( Vout->Ybuff, Vout->UVbuff, Vin->Ybuff, Vin->UVbuff, Ctx->HWOutPicWidth, Vin->PicInfo.width, dstHeightInPixels, lDestStrideY, lDestStrideUV ); break; case OUTPUT_MODE422_UYVY: Sts = DtsCopy420ToUYVY( Vout->Ybuff, Vout->UVbuff, Vin->Ybuff, Vin->UVbuff, Ctx->HWOutPicWidth, Vin->PicInfo.width, dstHeightInPixels, lDestStrideY, lDestStrideUV ); break; case OUTPUT_MODE420_NV12: Sts = DtsCopy420ToNV12( Vout->Ybuff, Vout->UVbuff, Vin->Ybuff, Vin->UVbuff, Ctx->HWOutPicWidth, Vin->PicInfo.width, dstHeightInPixels, lDestStrideY, lDestStrideUV ); break; default: Sts = BC_STS_INV_ARG; break; } } return Sts; } DRVIFLIB_INT_API BC_STATUS DtsPushFwBinToLink( HANDLE hDevice, uint32_t *Buffer, uint32_t BuffSz) { uint8_t *pXferBuff; BC_IOCTL_DATA *pIoctlData; BC_CMD_DEV_MEM *pMemAccess; uint32_t BytesReturned, AllocSz; if (!hDevice) { DebugLog_Trace(LDIL_DBG,"DtsPushFwBinToLink: Invalid Handle\n"); return BC_STS_INV_ARG; } if (!Buffer) { DebugLog_Trace(LDIL_DBG,"DtsPushFwBinToLink: Null Buffer\n"); return BC_STS_INV_ARG; } if (BuffSz % 4) { DebugLog_Trace(LDIL_DBG,"DtsPushFwBinToLink: Buff Size is not a multiple of DWORD\n"); return BC_STS_ERROR; } AllocSz = sizeof(BC_IOCTL_DATA) + (BuffSz); pIoctlData = (BC_IOCTL_DATA *) malloc(AllocSz); if(!pIoctlData) { DebugLog_Trace(LDIL_DBG,"DtsPushFwBinToLink: Memory Allocation Failed\n"); return BC_STS_ERROR; } memset(pIoctlData, 0, AllocSz); pXferBuff = ((PUCHAR)pIoctlData) + sizeof(BC_IOCTL_DATA); pMemAccess = &pIoctlData->u.devMem; pIoctlData->RetSts = BC_STS_ERROR; pIoctlData->IoctlDataSz = sizeof(BC_IOCTL_DATA); pMemAccess->StartOff = 0; pMemAccess->NumDwords = BuffSz/4; memcpy(pXferBuff, Buffer, BuffSz); if (!DtsDrvIoctl(hDevice, BCM_IOC_FW_DOWNLOAD, pIoctlData, AllocSz, pIoctlData, AllocSz, (LPDWORD)&BytesReturned, 0)) { DebugLog_Trace(LDIL_DBG,"DtsPushFwBinToLink: DeviceIoControl Failed\n"); return BC_STS_ERROR; } if (BC_STS_ERROR == pIoctlData->RetSts) { DebugLog_Trace(LDIL_DBG,"DtsPushFwBinToLink: IOCTL Cmd Failed By Driver\n"); return pIoctlData->RetSts; } if(pIoctlData) { free(pIoctlData); } return BC_STS_SUCCESS; } /*====================== Debug Routines ========================================*/ void DumpDataToFile(FILE *fp, char *header, uint32_t off, uint8_t *buff, uint32_t dwcount) { uint32_t i, k=1; #ifndef _LIB_EN_FWDUMP_ // Skip FW Download dumping.. return ; #endif if(!fp) return; if(header){ fprintf(fp,"%s\n",header); } for(i = 0; i < dwcount; i++){ if (k == 1) fprintf(fp, "0x%08X : ", off); fprintf(fp," 0x%08X ", *((uint32_t *)buff)); buff += sizeof(uint32_t); off += sizeof(uint32_t); k++; if ((i == dwcount - 1) || (k > 4)){ fprintf(fp,"\n"); k = 1; } } //fprintf(fp,"\n"); fflush(fp); } void DumpInputSampleToFile(uint8_t *buff, uint32_t buffsize) { #ifndef _LIB_EN_INDUMP_ return ; #endif static FILE *pOutputFile=NULL; if(!buff || !buffsize){ if(pOutputFile){ fclose(pOutputFile); pOutputFile = NULL; } return; } if(!pOutputFile){ if(!(pOutputFile = fopen("hdfile_dump.ts","wb")) ) return; } fwrite(buff, sizeof(uint8_t), buffsize, pOutputFile); fflush(pOutputFile); } crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/libcrystalhd_if.h0000644000175000017500000012704011610313111025515 0ustar andresandres/***************************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_if.h * * Description: Device Interface Library API. * * AU * * HISTORY: * ***************************************************************************** * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * ****************************************************************************/ #ifndef _BCM_LDIL_IF_H_ #define _BCM_LDIL_IF_H_ #include "bc_dts_defs.h" #include "bc_dts_types.h" #define FLEA_MAX_TRICK_MODE_SPEED 6 #ifdef __cplusplus extern "C" { #endif /***************************************************************************** ****************************************************************************** Theory of operation The Device Interface Library (DIL) allows application level code, such as a DirectShow filter, to access the Broadcom CrystalHD decoder driver to provide hardware decoding for MPEG-2, H.264 (AVC) and VC-1 streams. In the Microsoft DirectShow system, the overall system graph would look like the following: +--------+ +---------------+ +---------------+ +--------------------+ | Source |->| Demultiplexer |->| Audio decoder |->| DirectSound Device | +--------+ +---------------+ +---------------+ +--------------------+ | | +-------------------------+ +----------------+ +->| Broadcom decoder filter |->| Video Renderer | +-------------------------+ +----------------+ | | +----------------+ | Broadcom DIL | +----------------+ | | +-----------------+ | Broadcom Driver | +-----------------+ From the view of the caller, the DIL will accept compressed video streams and will output decoded video frames or fields to seperate Y and UV buffers. The DIL is responsible solely for decoding video and has no responsibilities for audio nor for rendering, as shown in the above diagram. Audio/video sychronization is assisted by feeding the DIL with timestamps so that it may pass those timestamps along with the decoded video. The timestamped output video will then be presented at the appropriate time by the renderer. A minimal implementation would be: HANDLE hBRCMhandle; uint8_t input_buffer[INPUT_SIZE]; uint8_t y_output_buffer[WIDTH*HEIGHT]; uint8_t uv_output_buffer[WIDTH*HEIGHT]; BC_DTS_PROC_OUT sProcOutData = { fill in your values here }; BC_PIC_INFO_BLOCK sPIB = { fill in your values here }; // Acquire handle for device. DtsDeviceOpen(&hBRCMhandle, 0); // Elemental stream. DtsOpenDecoder(hBRCMhandle, 0); // H.264, Enable FGT SEI, do not parse metadata, no forced progressive out DtsSetVideoParams(hBRCMhandle,0,1,0,0,0); // Tell decoder to wait for input from host. (PC) DtsStartDecoder(hBRCMhandle); // Input buffer address, input buffer size, no timestamp, Unencrypted DtsProcInput(hBRCMhandle,input_buffer,sizeof(input_buffer),0,0); // Tell PC to wait for data from decoder. DtsStartCapture(hBRCMhandle); // 16ms timeout, pass pointer to PIB then get the decoded picture. DtsProcOutput(hBRCMhandle,16,&sPIB); // Stop the decoder. DtsStopDecoder(hBRCMhandle); // Close the decoder DtsCloseDecoder(hBRCMhandle); // Release handle for device. DtsDeviceClose(hBRCMhandle); ****************************************************************************** *****************************************************************************/ #define DRVIFLIB_API /***************************************************************************** Function name: DtsDeviceOpen Description: Opens a handle to the decoder device that will be used to address that unique instance of the decoder for all subsequent operations. Must be called once when the application opens the decoder for use. Parameters: *hDevice Pointer to device handle that will be filled in after the device is successfully opened. [OUTPUT] mode Controls the mode in which the device is opened. Currently only mode 0 (normal playback) is supported. All other values will return BC_STS_INV_ARG. Return: Returns BC_STS_SUCCESS or error codes as appropriate. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsDeviceOpen( HANDLE *hDevice, uint32_t mode ); /***************************************************************************** Function name: DtsDeviceClose Description: Close the handle to the decoder device. Must be called once when the application closes the decoder after use. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen Return: Returns BC_STS_SUCCESS or error codes as appropriate. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsDeviceClose( HANDLE hDevice ); /***************************************************************************** Function name: DtsGetVersion Description: Get version information from the driver as well as API library. Version numbers are maintained in .. format. Example ?01.23.4567 The device must have been previously opened for this call to succeed. The individual components of the revision number are available as follows: o Major (8 Bits) : Bit 31 ?24 o Minor (8 Bits) : Bit 23 ?16 o Revision (16 Bits) : Bits 15 ?Bit 0. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen DrVer Device driver version DilVer Driver interface library version Return: The revision numbers from the currently loaded driver as well as the driver interface API library. BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsGetVersion( HANDLE hDevice, uint32_t *DrVer, uint32_t *DilVer ); /***************************************************************************** Function name: DtsGetFWVersionFromFile Description: Get version information from the Firmware Bin file when FW is not running Version numbers in FW are maintained in .. format. the return value will be of the format: (Major << 16) | (Minor<<8) | Spl_rev ?012345 The individual components of the revision number are available as follows: o Major (8 Bits) : Bit 24 ?16 o Minor (8 Bits) : Bit 16 ?8 o Revision (16 Bits) : Bits 8 ?0. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen StreamVer Stream FW version DecVer VDEC FW version Rsvd Reserved for future use Return: The Stream FW Version umbers from the FW bin file in the install directory BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsGetFWVersionFromFile( HANDLE hDevice, uint32_t *StreamVer, uint32_t *DecVer, char *fname ); /***************************************************************************** Function name: DtsGetFWVersion Description: Get version information from the Firmware. The version information is obtained from Bin file when the flag is not set. When the flag is set, a FW command is issued to get the version numbers. Version numbers in FW are maintained in .. format. Version number will be returned in the following format (Major << 16) | (Minor<<8) | Spl_rev ?012345 The individual components of the revision number are available as follows: o Major (8 Bits) : Bit 24 ?16 o Minor (8 Bits) : Bit 16 ?8 o Revision (16 Bits) : Bits 8 ?Bit 0. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen StreamVer Stream FW version DecVer VDEC FW version HwVer Hardware version Rsvd Reserved for future use flag Reseved for future use Return: The Stream FW Version number, VDEC FW version and Hwrev BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsGetFWVersion( HANDLE hDevice, uint32_t *StreamVer, uint32_t *DecVer, uint32_t *HwVer, char *fname, uint32_t flag ); /***************************************************************************** Function name: DtsOpenDecoder Description: Open the decoder for playback operations and sets appropriate parameters for decode of input video data. The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. StreamType Currently supported streams are: Elementary Streams with no timestamp management (0) Transport Streams (2) Elementary Streams with timestamp management (6) All other values will return BC_STS_INV_ARG. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsOpenDecoder( HANDLE hDevice, uint32_t StreamType ); /***************************************************************************** Function name: DtsCloseDecoder Description: Close the decoder. No further pictures will be produced and all input will be ignored. The device must have been previously opened for this call to succeed. This function closes the decoder and cleans up the state of the driver and the library. All pending pictures will be dropped and all outstanding transfers to and from the decoder will be aborted. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsCloseDecoder( HANDLE hDevice ); /***************************************************************************** Function name: DtsStartDecoder Description: Start the actual processing of input data. Before this command the decoder will ignore all of the presented input data. DtsOpenDecoder must always be followed by a DtsStartDecoder for the decoder to start processing input data. The device must have been previously opened for this call to succeed. In addition the video parameters for codec must have been set via a call to DtsSetVideoParams. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsStartDecoder( HANDLE hDevice ); /***************************************************************************** Function name: DtsSetVideoParams Description: Sets various codec parameters that would be used by a subsequent call to DtsStartDecoder. DtsSetVideoParams must always be called before DtsStartDecoder for the decoder to start processing input data. The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. videoAlg Video Codec to be enabled to decode stream. H.264 (0), VC-1 (4) and MPEG-2 (1) currently supported. All other values will return BC_STS_INV_ARG FGTEnable Enable processing of FGT SEI. MetaDataEnable Enable retrieval of picture metadata to be sent to video pipeline. Progressive Instruct decoder to always try to send back progressive frames. If input content is 1080p, the decoder will ignore pull-down flags and always give 1080p output. If 1080i content is processed, the decoder will return 1080i data. When this flag is not set, the decoder will use pull-down information in the input stream to decide the decoded data format. OptFlags In this field bits 0:3 are used pass default frame rate, bits 4:5 are for operation mode (used to indicate Blu-ray mode to the decoder) and bit 6 is for the flag mpcOutPutMaxFRate which when set tells the FW to output at the max rate for the resolution and ignore the frame rate determined from the stream. Bit 7 is set to indicate that this is single threaded mode and the driver will be peeked to get timestamps ahead of time. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsSetVideoParams( HANDLE hDevice, uint32_t videoAlg, BOOL FGTEnable, BOOL MetaDataEnable, BOOL Progressive, uint32_t OptFlags ); /***************************************************************************** Function name: DtsSetInputFormat Description: Sets input video's various parameters that would be used by a subsequent call to DtsStartDecoder. DtsSetInputFormat must always be called before DtsOpenDecoder for the decoder to start processing input data. The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. pInputFormat Pointer to the BC_INPUT_FORMAT data. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsSetInputFormat( HANDLE hDevice, BC_INPUT_FORMAT *pInputFormat ); /***************************************************************************** Function name: DtsGetVideoParams Description: Returns various codec parameters that would be used by a subsequent call to DtsStartDecoder. These parameters are either default values or were set via a prior call to DtsSetVideoParams The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. *videoAlg See DtsSetVideoParams. [OUTPUT] *FGTEnable See DtsSetVideoParams. [OUTPUT] *MetaDataEnable See DtsSetVideoParams. [OUTPUT] *Progressive See DtsSetVideoParams. [OUTPUT] Reserved This field is reserved for possible future expansion. Set to 0. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsGetVideoParams( HANDLE hDevice, uint32_t *videoAlg, BOOL *FGTEnable, BOOL *MetaDataEnable, BOOL *Progressive, uint32_t Reserved ); /***************************************************************************** Function name: DtsFormatChange Description: Changes codec type and parameters. The device must have been previously opened for this call to succeed. This function should be used only for mid-stream format changes. DtsStartDecoder must have been called before for this function to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. videoAlg Video Codec to be enabled to decode stream. H.264 (0), VC-1 (4) and MPEG-2 (1) currently supported. All other values will return BC_STS_INV_ARG FGTEnable Enable processing of FGT SEI. Progressive Instruct decoder to always try to send back progressive frames. If input content is 1080p, the decoder will ignore pull-down flags and always give 1080p output. If 1080i content is processed, the decoder will return 1080i data. When this flag is not set, the decoder will use pull-down information in the input stream to decide the decoded data format. Reserved This field is reserved for possible future expansion. Set to 0. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsFormatChange( HANDLE hDevice, uint32_t videoAlg, BOOL FGTEnable, BOOL MetaDataEnable, BOOL Progressive, uint32_t Reserved ); /***************************************************************************** Function name: DtsStopDecoder Description: Stop the decoder. The device must have been previously opened for this call to succeed. This function will clean up any pending operations and stop the decoder. Internal state is still maintained and the decoder can be restarted. Any pending pictures will be dropped. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsStopDecoder( HANDLE hDevice ); /***************************************************************************** Function name: DtsPauseDecoder Description: Pause the decoder. The paused picture will be repeated by decoder. The device must have been previously opened for this call to succeed. In addition the decoder must have been started as well. If the decoder is open but not started, this function will return BC_STS_DEC_NOT_STARTED. If the decoder has not been opened this function will return BC_STS_DEC_NOT_OPEN. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsPauseDecoder( HANDLE hDevice ); /***************************************************************************** Function name: DtsResumeDecoder Description: Unpause the decoder from a previous paused condition. The device must have been previously opened for this call to succeed. If the decoder was not paused previously, this function will return without affecting the decoder with a BC_STS_SUCCESS status. If the decoder is open but not started, this function will return BC_STS_DEC_NOT_STARTED. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsResumeDecoder( HANDLE hDevice ); /***************************************************************************** Function name: DtsSetVideoPID Description: Sets the video PID in the input Transport Stream that the decoder needs to process. The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. PID PID value that decoder needs to process. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsSetVideoPID( HANDLE hDevice, uint32_t pid ); /***************************************************************************** Function name: StartCaptureImmidiate Description: Instruct the driver to start capturing decoded frames for output. The device must have been previously opened for this call to succeed. This function must be called before the first call to DtsProcInput. This function instructs the receive path in the driver to start waiting for valid data to be presented from the decoder. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsStartCaptureImmidiate( HANDLE hDevice, uint32_t Reserved ); /***************************************************************************** Function name: StartCapture Description: Instruct the driver to start capturing decoded frames for output. The device must have been previously opened for this call to succeed. This function must be called before the first call to DtsProcInput. This function instructs the receive path in the driver to start waiting for valid data to be presented from the decoder. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsStartCapture( HANDLE hDevice ); /***************************************************************************** Function name: FlushRxCapture Description: ***This function is deprecated and is for temporary use only.*** Flush the driverís queue of pictures and stops the capture process. These functions will be replaced with automatic Stop (End of Sequence) detection. The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsFlushRxCapture( HANDLE hDevice, BOOL bDiscardOnly ); /***************************************************************************** Function name: DtsProcOutput Description: Returns one decoded picture to the caller. The device must have been previously opened for this call to succeed. == NOTE ==== For PIB AND 100% output encryption/scrambling on Bcm LINK hardware use ProcOutputNoCopy() Interace. This interface will not support PIB encryption. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. milliSecWait Timeout parameter. DtsProcOutput will fail is no picture is received in this time. *pOut This is a pointer to the BC_DTS_PROC_OUT structure that is allocated by the caller. The decoded picture is returned in this structure. This structure is described in the data structures section. The actual data buffer to be filled with the decoded data is allocated by the caller. Data is copied from the decoder to the buffers before this function returns. [INPUT/OUTPUT] Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsProcOutput( HANDLE hDevice, uint32_t milliSecWait, BC_DTS_PROC_OUT *pOut ); /***************************************************************************** Function name: DtsProcOutputNoCopy Description: Returns one decoded picture to the caller. Functionality of this API() is very similar to ProcOutPut() API. This API will not copy the video data to caller's buffers but provides the source buffer pointers in pOut structure. This is more secure and preferred method for BCM's Link hardware. The actual format conversion/copy routines are provided as part of the Filter/Security layer source code. Using this method, all the clear data handling will be done by bcmDFilter or bcmSec layers which are expected to be in Player's tamper resistant area. == NOTE ==== 1) DtsReleaseOutputBuffs() interface must be called to release the buffers back to DIL if return Status is BC_STS_SUCCESS. 2) Only this interface supports PIB and full 100% output encryption/Scrambling. The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. milliSecWait Timeout parameter. DtsProcOoutput will fail is no picture is received in this time. *pOut This is a pointer to the BC_DTS_PROC_OUT structure that is allocated by the caller. The decoded picture is returned in this structure. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsProcOutputNoCopy( HANDLE hDevice, uint32_t milliSecWait, BC_DTS_PROC_OUT *pOut ); /***************************************************************************** Function name: DtsReleaseOutputBuffs Description: Release Buffers acquired during ProcOutputNoCopy() interface. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. Reserved Reserved. Set to NULL. fChange FALSE. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsReleaseOutputBuffs( HANDLE hDevice, PVOID Reserved, BOOL fChange ); /***************************************************************************** Function name: DtsProcInput Description: Sends compressed (coded) data to the decoder for processing. The device must have been previously opened for this call to succeed. In addition, suitable keys must have been exchanged for decryption and decode to be successful. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. pUserData Pointer to data buffer that holds the data to be transferred. [INPUT] sizeInBytes Size in Bytes of data available to be sent to the decoder for processing. Timestamp Optional timestamp information attached to the media sample that is available in the buffer. If timestamp is present (i.e. non-zero), then this will be reflected in the output sample (picture) produced from the contents of this buffer. Timestamp should be in units of 100 ns. Encrypted Flag to indicate that the data transfer is not in the clear and that the decoder needs to decrypt before it can decode the data. Note that due to complexity, it is preferred that the application writer uses the higher level dts_pre_proc_input() call if encypted content will be sent. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsProcInput( HANDLE hDevice, uint8_t *pUserData, uint32_t ulSizeInBytes, uint64_t timeStamp, BOOL encrypted ); /***************************************************************************** Function name: DtsGetColorPrimaries Description: Returns color primaries information from the stream being processed. The device must have been previously opened for this call to succeed. In addition at least one picture must have been successfully decoded and returned back from the decoder. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. colorPrimaries Pointer to U32 to receive the color primaries information. The values returned are described in the previous section regarding the picture metadata. [OUTPUT] Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsGetColorPrimaries( HANDLE hDevice, uint32_t *colorPrimaries ); /***************************************************************************** Function name: DtsFlushInput Description: Flushes the current channel and causes the decoder to stop accessing input data. Based on the flush mode parameter, the channel will be flushed from the current point in the input data or from the current processing point. The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. Mode 0 Flush at the current input point. use to drain the input FIFO . All the data that has been received will be decoded. 1 Flush at the current processing point. All the decoded frames will be presented but no more data from the input will be decoded. 2 Flushes all the decoder buffers, input, decoded and to be decoded. 3 Cancels the pending TX Request from the DIL/driver 4 Flushes all the decoder buffers, input, decoded and to be decoded data. Also flushes the drivers buffers Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsFlushInput( HANDLE hDevice, uint32_t Mode ); /***************************************************************************** Function name: DtsSetRateChange Description: Sets the decoder playback speed and direction of playback. The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. rate Inverse of speed x 10000. Examples: 1/2x playback speed = 20000 1x playback speed = 10000 2x playback speed = 5000 direction Playback direction. 0 Forward direction. 1 Reverse direction. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsSetRateChange( HANDLE hDevice, uint32_t rate, uint8_t direction ); //Set FF Rate for Catching Up /***************************************************************************** Function name: DtsSetFFRate Description: Sets the decoder playback FF speed The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. rate Inverse of speed x 10000. Examples: 1/2x playback speed = 20000 1x playback speed = 10000 2x playback speed = 5000 Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsSetFFRate( HANDLE hDevice, uint32_t rate ); /***************************************************************************** Function name: DtsSetSkipPictureMode Description: This command sets the decoder to only decode selected picture types. The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. SkipMode 0 IPB, All pictures are decoded. 1 IP decoding, This mode skips all non reference pictures. 2 I decoding, This mode skips all P/B pictures and only decodes I pictures. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsSetSkipPictureMode( HANDLE hDevice, uint32_t SkipMode ); /***************************************************************************** Function name: DtsSetIFrameTrickMode Description: This command sets the decoder to decode only I Frames for FF and FR. Use this API for I Frame only trick mode play back in either direction. The application/Up stream filter determines the speed of the playback by means of Skip on the input compressed data. The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsSetIFrameTrickMode( HANDLE hDevice ); /***************************************************************************** Function name: DtsStepDecoder Description: This function forwards one frame. The device must have been opened must be in paused state previously for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsStepDecoder( HANDLE hDevice ); /***************************************************************************** Function name: DtsIs422Supported Description: This function returns whether 422 YUV mode is supported or not. The device must have been opened previously for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. bSupported 1 - 422 is supported 0 - 422 is not supported. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsIs422Supported( HANDLE hDevice, uint8_t *bSupported ); /***************************************************************************** Function name: DtsSetColorSpace Description: This function sets the output sample's color space. The device must have been opened previously and must support 422 mode for this call to succeed. Use "DtsIs422Supported" to find whether 422 mode is supported. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. 422Mode Mode is defined by BC_OUTPUT_FORMAT as follows - OUTPUT_MODE420 = 0x0, OUTPUT_MODE422_YUY2 = 0x1, OUTPUT_MODE422_UYVY = 0x2, OUTPUT_MODE_INVALID = 0xFF Valid values for this API are OUTPUT_MODE422_YUY2 and OUTPUT_MODE422_UYVY Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsSetColorSpace( HANDLE hDevice, BC_OUTPUT_FORMAT Mode422 ); /***************************************************************************** Function name: DtsSet422Mode Description: This function sets the 422 mode to either YUY2 or UYVY. The device must have been opened previously and must support 422 mode for this call to succeed. Use "DtsIs422Supported" to find whether 422 mode is supported. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. 422Mode 0 - set the YUV mode to YUY2 1 - set the YUV mode to UYVY Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsSet422Mode( HANDLE hDevice, uint8_t Mode422 ); /***************************************************************************** Function name: DtsGetDILPath Description: This is a helper function to return DIL's Path. The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. DilPath Buffer to hold DIL path info upto 256 bytes. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsGetDILPath( HANDLE hDevice, char *DilPath, uint32_t size ); /***************************************************************************** Function name: DtsDropPictures Description: This command sets the decoder to skip one or more non-reference (B) pictures in the input data stream. This is used for when the audio is ahead of video and the application needs to cause video to move ahead to catch up. Reference pictures are not skipped. The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. Pictures The number of non-reference pictures to drop. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsDropPictures( HANDLE hDevice, uint32_t Pictures ); /***************************************************************************** Function name: DtsGetDriverStatus Description: This command returns various statistics related to the driver and DIL. The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. *pStatus Pointer to BC_DTS_STATUS to receive driver status. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsGetDriverStatus( HANDLE hDevice, BC_DTS_STATUS *pStatus ); /***************************************************************************** Function name: DtsGetCapabilities Description: This command returns output format support and hardware capabilities. The device must have been previously opened for this call to succeed. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. pCapsBuffer Pointer to BC_HW_CAPS to receive HW Output capabilities. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsGetCapabilities ( HANDLE hDevice, PBC_HW_CAPS pCapsBuffer ); /***************************************************************************** Function name: DtsSetScaleParams Description: This command sets hardware scaling parameters. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. pScaleParams Pointer to BC_SCALING_PARAMS to set hardware scaling parameters. Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsSetScaleParams ( HANDLE hDevice, PBC_SCALING_PARAMS pScaleParams ); /***************************************************************************** Function name: DtsIsEndOfStream Description: This command returns whether the end of stream(EOS) is reaching. Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. bEOS Pointer to uint8_t to indicate if EOS of not Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsIsEndOfStream( HANDLE hDevice, uint8_t* bEOS ); /***************************************************************************** Function name: DtsCrystalHDVersion Description: This API returns hw and sw version information for Crystal HD solutions Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. bCrystalInfo Pointer to structure to fill in with information device = 0 for BCM70012, 1 for BCM70015 Return: BC_STS_SUCCESS will be returned on successful completion. *****************************************************************************/ DRVIFLIB_API BC_STATUS DtsCrystalHDVersion( HANDLE hDevice, PBC_INFO_CRYSTAL bCrystalInfo ); /***************************************************************************** Function name: DtsTxFreeSize Description: This API returns the amount of free space in the tx circular buffer Parameters: hDevice Handle to device. This is obtained via a prior call to DtsDeviceOpen. Return: uint32_t value of number of free bytes in the tx circular buffer *****************************************************************************/ DRVIFLIB_API uint32_t DtsTxFreeSize( HANDLE hDevice ); #ifdef __cplusplus } #endif #endif crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/libcrystalhd_priv.cpp0000644000175000017500000021667711610313111026451 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_priv.cpp * * Description: Driver Interface library Internal. * * AU * * HISTORY: * ******************************************************************** * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #include #include #include #include #include #include #include #include #include "7411d.h" #include "libcrystalhd_if.h" #include "libcrystalhd_int_if.h" #include "libcrystalhd_priv.h" #include "libcrystalhd_parser.h" /*============== Global shared area usage ======================*/ /* Global mode settings */ /* Bit 0 (LSB) - Play Back mode Bit 1 - Diag mode Bit 2 - Monitor mode Bit 3 - HwInit mode bit 5 - Hwsetup in progress */ bc_dil_glob_s *bc_dil_glob_ptr=NULL; bool glob_mode_valid=TRUE; BC_STATUS DtsCreateShMem(int *shmem_id) { int shmid=-1; key_t shmkey=BC_DIL_SHMEM_KEY; shmid_ds buf; uint32_t mode=0; if(shmem_id==NULL) { DebugLog_Trace(LDIL_DBG,"Invalid argument ...\n"); return BC_STS_INSUFF_RES; } *shmem_id =shmid; //First Try to create it. if((shmid= shmget(shmkey, 1024, 0644|IPC_CREAT|IPC_EXCL))== -1 ) { if(errno==EEXIST) { //DebugLog_Trace(LDIL_DBG,"DtsCreateShMem:shmem already exists :%d\n",errno); //shmem segment already exists so get the shmid if((shmid= shmget(shmkey, 1024, 0644))== -1 ) { DebugLog_Trace(LDIL_DBG,"DtsCreateShMem:unable to get shmid :%d\n",errno); return BC_STS_INSUFF_RES; } //we got the shmid, see if any process is alreday attached to it if(shmctl(shmid,IPC_STAT,&buf)==-1){ DebugLog_Trace(LDIL_DBG,"DtsCreateShMem:shmctl failed ...\n"); return BC_STS_ERROR; } if(buf.shm_nattch ==0) { //No process is currently attached to the shmem seg. go ahead and delete it as its contents are stale. if(-1!=shmctl(shmid,IPC_RMID,NULL)){ DebugLog_Trace(LDIL_DBG,"DtsCreateShMem:deleted shmem segment and creating a new one ...\n"); //return BC_STS_ERROR; } //create a new shmem if((shmid= shmget(shmkey, 1024, 0644|IPC_CREAT|IPC_EXCL))== -1 ) { DebugLog_Trace(LDIL_DBG,"DtsCreateShMem:unable to get shmid :%d\n",errno); return BC_STS_INSUFF_RES; } //attach to it DtsGetDilShMem(shmid); } else{ //someone is attached to it DtsGetDilShMem(shmid); mode = DtsGetOPMode(); if(! ((mode==1)||(mode==2)||(mode==4))&&(buf.shm_nattch==1) ) { glob_mode_valid=FALSE; DebugLog_Trace(LDIL_DBG,"DtsCreateShMem:globmode %d is invalid\n",mode); } } }else{ DebugLog_Trace(LDIL_DBG,"shmcreate failed with err %d",errno); return BC_STS_ERROR; } }else{ //we created just attach to it DtsGetDilShMem(shmid); } *shmem_id =shmid; return BC_STS_SUCCESS; } BC_STATUS DtsGetDilShMem(uint32_t shmid) { bc_dil_glob_ptr=(bc_dil_glob_s *)shmat(shmid,(void *)0,0); if((long)bc_dil_glob_ptr==-1) { DebugLog_Trace(LDIL_DBG,"Unable to open shared memory ...\n"); return BC_STS_ERROR; } return BC_STS_SUCCESS; } BC_STATUS DtsDelDilShMem() { int shmid =0; shmid_ds buf; //First dettach the shared mem segment if(shmdt(bc_dil_glob_ptr)==-1) { DebugLog_Trace(LDIL_DBG,"Unable to detach from Dil shared memory ...\n"); //return BC_STS_ERROR; } //delete the shared mem segment if there are no other attachments if ((shmid =shmget((key_t)BC_DIL_SHMEM_KEY,0,0))==-1){ DebugLog_Trace(LDIL_DBG,"DtsDelDilShMem:Unable get shmid ...\n"); return BC_STS_ERROR; } if(shmctl(shmid,IPC_STAT,&buf)==-1){ DebugLog_Trace(LDIL_DBG,"DtsDelDilShMem:shmctl failed ...\n"); return BC_STS_ERROR; } if(buf.shm_nattch ==0) { //No process is currently attached to the shmem seg. go ahead and delete it if(-1!=shmctl(shmid,IPC_RMID,NULL)){ // DebugLog_Trace(LDIL_DBG,"DtsDelDilShMem:deleted shmem segment ...\n"); return BC_STS_ERROR; } else{ DebugLog_Trace(LDIL_DBG,"DtsDelDilShMem:unable to delete shmem segment ...\n"); } } return BC_STS_SUCCESS; } uint32_t DtsGetgDevID(void) { if(bc_dil_glob_ptr == NULL) return BC_PCI_DEVID_INVALID; else return bc_dil_glob_ptr->DevID; } void DtsSetgDevID(uint32_t DevID) { bc_dil_glob_ptr->DevID = DevID; } uint32_t DtsGetOPMode( void ) { return bc_dil_glob_ptr->gDilOpMode; } void DtsSetOPMode( uint32_t value ) { bc_dil_glob_ptr->gDilOpMode = value; } uint32_t DtsGetHwInitSts( void ) { return bc_dil_glob_ptr->gHwInitSts; } void DtsSetHwInitSts( uint32_t value ) { bc_dil_glob_ptr->gHwInitSts = value; } void DtsRstStats( void ) { memset(&bc_dil_glob_ptr->stats, 0, sizeof(bc_dil_glob_ptr->stats)); } BC_DTS_STATS * DtsGetgStats ( void ) { return &bc_dil_glob_ptr->stats; } bool DtsIsDecOpened(pid_t nNewPID) { if(bc_dil_glob_ptr == NULL) return false; if (nNewPID == 0) return bc_dil_glob_ptr->g_bDecOpened; if (nNewPID == bc_dil_glob_ptr->g_nProcID) return false; return bc_dil_glob_ptr->g_bDecOpened; } bool DtsChkPID(pid_t nCurPID) { if (bc_dil_glob_ptr->g_nProcID == 0) return true; return (nCurPID == bc_dil_glob_ptr->g_nProcID); } void DtsSetDecStat(bool bDecOpen, pid_t PID) { if (bDecOpen == true) bc_dil_glob_ptr->g_nProcID = PID; else bc_dil_glob_ptr->g_nProcID = 0; bc_dil_glob_ptr->g_bDecOpened = bDecOpen; } /*============== Global shared area usage End.. ======================*/ #define TOP_FIELD_FLAG 0x01 #define BOTTOM_FIELD_FLAG 0x02 #define PROGRESSIVE_FRAME_FLAG 0x03 static void DtsGetMaxYUVSize(DTS_LIB_CONTEXT *Ctx, uint32_t *YbSz, uint32_t *UVbSz) { if (Ctx->b422Mode) { *YbSz = (1920*1090)*2; *UVbSz = 0; } else { *YbSz = 1920*1090; *UVbSz = 1920*1090/2; } } static void DtsGetMaxSize(DTS_LIB_CONTEXT *Ctx, uint32_t *Sz) { *Sz = (1920*1090)*2; } static void DtsInitLock(DTS_LIB_CONTEXT *Ctx) { //Create mutex int ret; pthread_mutexattr_t thLockattr; ret = pthread_mutexattr_init(&thLockattr); if(ret) DebugLog_Trace(LDIL_DBG, "Error initializing attributes\n"); ret = pthread_mutexattr_settype(&thLockattr, PTHREAD_MUTEX_RECURSIVE); if(ret) DebugLog_Trace(LDIL_DBG, "Error setting type of mutex\n"); ret = pthread_mutex_init(&Ctx->thLock, &thLockattr); if(ret) DebugLog_Trace(LDIL_DBG, "Error initializing mutex\n"); } static void DtsDelLock(DTS_LIB_CONTEXT *Ctx) { pthread_mutex_destroy(&Ctx->thLock); } void DtsLock(DTS_LIB_CONTEXT *Ctx) { pthread_mutex_lock(&Ctx->thLock); } void DtsUnLock(DTS_LIB_CONTEXT *Ctx) { pthread_mutex_unlock(&Ctx->thLock); } static void DtsIncPend(DTS_LIB_CONTEXT *Ctx) { DtsLock(Ctx); Ctx->ProcOutPending++; DtsUnLock(Ctx); } static void DtsDecPend(DTS_LIB_CONTEXT *Ctx) { DtsLock(Ctx); if(Ctx->ProcOutPending) Ctx->ProcOutPending--; DtsUnLock(Ctx); } void DtsGetFrameRate(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut) { if (Ctx->VidParams.FrameRate == pOut->PicInfo.frame_rate) { pOut->PicInfo.frame_rate = 0; return; } // DebugLog_Trace(LDIL_DBG,"DtsGetFrameRate: frame_rate:%d (%d)\n", pOut->PicInfo.frame_rate, Ctx->VidParams.FrameRate); Ctx->VidParams.FrameRate = pOut->PicInfo.frame_rate; if (pOut->PicInfo.frame_rate == vdecFrameRate23_97) pOut->PicInfo.frame_rate = 23970; else if (pOut->PicInfo.frame_rate == vdecFrameRate24) pOut->PicInfo.frame_rate = 24000; else if (pOut->PicInfo.frame_rate == vdecFrameRate25) pOut->PicInfo.frame_rate = 25000; else if (pOut->PicInfo.frame_rate == vdecFrameRate29_97) pOut->PicInfo.frame_rate = 29970; else if (pOut->PicInfo.frame_rate == vdecFrameRate30) pOut->PicInfo.frame_rate = 30000; else if (pOut->PicInfo.frame_rate == vdecFrameRate50) pOut->PicInfo.frame_rate = 50000; else if (pOut->PicInfo.frame_rate == vdecFrameRate59_94) pOut->PicInfo.frame_rate = 59940; else if (pOut->PicInfo.frame_rate == vdecFrameRate60) pOut->PicInfo.frame_rate = 60000; else if (pOut->PicInfo.frame_rate == vdecFrameRate14_985) pOut->PicInfo.frame_rate = 14985; else if (pOut->PicInfo.frame_rate == vdecFrameRate7_496) pOut->PicInfo.frame_rate = 7496; else if (pOut->PicInfo.frame_rate == vdecFrameRateUnknown) pOut->PicInfo.frame_rate = 23970; else pOut->PicInfo.frame_rate = 23970; } uint32_t DtsGetHWOutputStride(DTS_LIB_CONTEXT *Ctx, C011_PIB *pPIBInfo) { if (Ctx->DevId == BC_PCI_DEVID_FLEA) { return pPIBInfo->ppb.width; } else { return pPIBInfo->resolution; } } uint32_t DtsGetWidthfromResolution(DTS_LIB_CONTEXT *Ctx, uint32_t Resolution) { uint32_t Width; /* For Flea source width is always equal to video width */ /* For Link translate from format container to actual source width */ if(Ctx->DevId == BC_PCI_DEVID_FLEA) return 0; switch (Resolution) { case vdecRESOLUTION_CUSTOM: Width = 0; break; case vdecRESOLUTION_1080i: case vdecRESOLUTION_1080i25: case vdecRESOLUTION_1080i29_97: case vdecRESOLUTION_1080p29_97: case vdecRESOLUTION_1080p30: case vdecRESOLUTION_1080p24: case vdecRESOLUTION_1080p25: case vdecRESOLUTION_1080p0: case vdecRESOLUTION_1080i0: case vdecRESOLUTION_1080p23_976: Width = 1920; break; case vdecRESOLUTION_240p29_97: case vdecRESOLUTION_240p30: case vdecRESOLUTION_288p25: Width = 1440; break; case vdecRESOLUTION_720p: case vdecRESOLUTION_720p50: case vdecRESOLUTION_720p59_94: case vdecRESOLUTION_720p24: case vdecRESOLUTION_720p29_97: case vdecRESOLUTION_720p0: case vdecRESOLUTION_720p23_976: Width = 1280; break; case vdecRESOLUTION_480i: case vdecRESOLUTION_NTSC: case vdecRESOLUTION_PAL1: case vdecRESOLUTION_SD_DVD: case vdecRESOLUTION_480p656: case vdecRESOLUTION_480p: case vdecRESOLUTION_576p: case vdecRESOLUTION_480p23_976: case vdecRESOLUTION_480p29_97: case vdecRESOLUTION_576p25: case vdecRESOLUTION_480p0: case vdecRESOLUTION_480i0: case vdecRESOLUTION_576p0: Width = 720; break; default: Width = 0; break; } return Width; } static void DtsCopyAppPIB(DTS_LIB_CONTEXT *Ctx, BC_DEC_OUT_BUFF *decOut, BC_DTS_PROC_OUT *pOut) { C011_PIB *srcPib = &decOut->PibInfo; BC_PIC_INFO_BLOCK *dstPib = &pOut->PicInfo; //uint16_t sNum = 0; //BC_STATUS sts = BC_STS_SUCCESS; Ctx->FormatInfo.timeStamp = dstPib->timeStamp = 0; Ctx->FormatInfo.picture_number = dstPib->picture_number = srcPib->ppb.picture_number; Ctx->FormatInfo.width = dstPib->width = srcPib->ppb.width; Ctx->FormatInfo.height = dstPib->height = srcPib->ppb.height; Ctx->FormatInfo.chroma_format = dstPib->chroma_format = srcPib->ppb.chroma_format; Ctx->FormatInfo.pulldown = dstPib->pulldown = srcPib->ppb.pulldown; Ctx->FormatInfo.flags = dstPib->flags = srcPib->ppb.flags; Ctx->FormatInfo.sess_num = dstPib->sess_num = srcPib->ptsStcOffset; Ctx->FormatInfo.aspect_ratio = dstPib->aspect_ratio = srcPib->ppb.aspect_ratio; Ctx->FormatInfo.colour_primaries = dstPib->colour_primaries = srcPib->ppb.colour_primaries; Ctx->FormatInfo.picture_meta_payload= dstPib->picture_meta_payload = srcPib->ppb.picture_meta_payload; /* FIX_ME:: Add extensions part.. */ /* Retrieve Timestamp */ // NAREN - FIXME - We should not copy the timestamp for Format Change since it is a dummy picture with no timestamp #if 0 if(srcPib->ppb.flags & VDEC_FLAG_PICTURE_META_DATA_PRESENT){ sNum = (U16) ( ((srcPib->ppb.picture_meta_payload & 0xFF) << 8) | ((srcPib->ppb.picture_meta_payload& 0xFF00) >> 8) ); DtsFetchMdata(Ctx,sNum,pOut); } #endif } static void dts_swap_buffer(uint32_t *dst, uint32_t *src, uint32_t cnt) { uint32_t i=0; for (i=0; i < cnt; i++){ dst[i] = BC_SWAP32(src[i]); } } static void DtsGetPibFrom422(uint8_t *pibBuff, uint8_t mode422) { uint32_t i; //First stripe has PIB data and second one has Extension PB. so total 256 bytes if (mode422 == OUTPUT_MODE422_YUY2) { for(i=0; i<256; i++) { pibBuff[i] = pibBuff[i*2]; } } else if (mode422 == OUTPUT_MODE422_UYVY) { for(i=0; i<256; i++) { pibBuff[i] = pibBuff[(i*2)+1]; } } } static BC_STATUS DtsGetPictureInfo(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut) { uint16_t sNum = 0; uint8_t* pPicInfoLine = NULL; uint32_t PictureNumber = 0; uint32_t PicInfoLineNum; bool bInterlaced = false; if (Ctx->DevId == BC_PCI_DEVID_FLEA) { PicInfoLineNum = *(uint32_t *)(pOut->Ybuff); } else if (Ctx->b422Mode == OUTPUT_MODE422_YUY2) { PicInfoLineNum = ((uint32_t)(*(pOut->Ybuff + 6)) & 0xff) | (((uint32_t)(*(pOut->Ybuff + 4)) << 8) & 0x0000ff00) | (((uint32_t)(*(pOut->Ybuff + 2)) << 16) & 0x00ff0000) | (((uint32_t)(*(pOut->Ybuff + 0)) << 24) & 0xff000000); } else if (Ctx->b422Mode == OUTPUT_MODE422_UYVY) { PicInfoLineNum = ((uint32_t)(*(pOut->Ybuff + 7)) & 0xff) | (((uint32_t)(*(pOut->Ybuff + 5)) << 8) & 0x0000ff00) | (((uint32_t)(*(pOut->Ybuff + 3)) << 16) & 0x00ff0000) | (((uint32_t)(*(pOut->Ybuff + 1)) << 24) & 0xff000000); } else { PicInfoLineNum = ((uint32_t)(*(pOut->Ybuff + 3)) & 0xff) | (((uint32_t)(*(pOut->Ybuff + 2)) << 8) & 0x0000ff00) | (((uint32_t)(*(pOut->Ybuff + 1)) << 16) & 0x00ff0000) | (((uint32_t)(*(pOut->Ybuff + 0)) << 24) & 0xff000000); } if (PicInfoLineNum == BC_EOS_DETECTED) // EOS { memcpy((uint32_t*)&pOut->PicInfo,(uint32_t*)(pOut->Ybuff + 4), sizeof(BC_PIC_INFO_BLOCK)); if (pOut->PicInfo.flags & VDEC_FLAG_EOS) { Ctx->bEOS = true; Ctx->pOutData->RetSts = BC_STS_NO_DATA; DebugLog_Trace(LDIL_DBG, "Found EOS \n"); return BC_STS_NO_DATA; } } /* -- To take care of 16 byte alignment the firmware might put extra -- line so that the PIB starts with a line boundary. We will need to -- have additional checks for the following condition to take care of -- extra lines. */ if( ( (PicInfoLineNum != Ctx->HWOutPicHeight) && (PicInfoLineNum != (Ctx->HWOutPicHeight+1))) && ( (PicInfoLineNum != Ctx->HWOutPicHeight/2) && (PicInfoLineNum != (Ctx->HWOutPicHeight+1)/2)) ) { return BC_STS_IO_XFR_ERROR; } if (Ctx->b422Mode) { pPicInfoLine = pOut->Ybuff + PicInfoLineNum * Ctx->HWOutPicWidth * 2; } else { pPicInfoLine = pOut->Ybuff + PicInfoLineNum * Ctx->HWOutPicWidth; } if (Ctx->DevId != BC_PCI_DEVID_FLEA) { DtsGetPibFrom422(pPicInfoLine, Ctx->b422Mode); PictureNumber = ((ULONG)(*(pPicInfoLine + 3)) & 0xff) | (((ULONG)(*(pPicInfoLine + 2)) << 8) & 0x0000ff00) | (((ULONG)(*(pPicInfoLine + 1)) << 16) & 0x00ff0000) | (((ULONG)(*(pPicInfoLine + 0)) << 24) & 0xff000000); }else{ /*The Metadata Is Linear in Flea.*/ PictureNumber = ((ULONG)(*(pPicInfoLine + 0)) & 0xff) | (((ULONG)(*(pPicInfoLine + 1)) << 8) & 0x0000ff00) | (((ULONG)(*(pPicInfoLine + 2)) << 16) & 0x00ff0000) | (((ULONG)(*(pPicInfoLine + 3)) << 24) & 0xff000000); } pOut->PoutFlags |= BC_POUT_FLAGS_PIB_VALID; if (Ctx->DevId != BC_PCI_DEVID_FLEA) { dts_swap_buffer((uint32_t*)&pOut->PicInfo,(uint32_t*)(pPicInfoLine + 4), 32); //copy ext PIB dts_swap_buffer((uint32_t*)&pOut->PicInfo.other,(uint32_t*)(pPicInfoLine +128), 32); } else { memcpy((uint32_t*)&pOut->PicInfo,(uint32_t*)(pPicInfoLine + 4), sizeof(BC_PIC_INFO_BLOCK)); } if (Ctx->DevId == BC_PCI_DEVID_FLEA) { if (pOut->PicInfo.flags & VDEC_FLAG_BOTTOMFIELD) bInterlaced = true; } else { if (pOut->PicInfo.flags & VDEC_FLAG_INTERLACED_SRC) bInterlaced = true; } if(bInterlaced) { Ctx->VidParams.Progressive = FALSE; pOut->PicInfo.flags |= VDEC_FLAG_INTERLACED_SRC; if (PictureNumber & 0x40000000) { pOut->PoutFlags |= BC_POUT_FLAGS_FLD_BOT; pOut->PicInfo.flags |= VDEC_FLAG_BOTTOMFIELD; } else { pOut->PicInfo.flags &= ~VDEC_FLAG_BOTTOMFIELD; pOut->PicInfo.flags |= VDEC_FLAG_TOPFIELD; } } else { Ctx->VidParams.Progressive = TRUE; pOut->PicInfo.flags &= ~(VDEC_FLAG_BOTTOMFIELD | VDEC_FLAG_INTERLACED_SRC); } if(PictureNumber & 0x80000000) { pOut->PoutFlags |= BC_POUT_FLAGS_ENCRYPTED; } DtsGetFrameRate(Ctx, pOut); //DILDbg_Trace(BC_DIL_DBG_DETAIL, TEXT("DtsGetPictureInfo: PicInfo (W,H):(%d,%d) FR:%ld Flags:0x%x\n"),pOut->PicInfo.width, pOut->PicInfo.height,pOut->PicInfo.frame_rate, pOut->PicInfo.flags); /* Replace Y Component data*/ if(Ctx->DevId == BC_PCI_DEVID_FLEA) { // In Flea from the HW we are getting Y and UV directly in the y component *((uint32_t *)&pOut->Ybuff[0]) = pOut->PicInfo.ycom; } else { //Replace Data Back by 422 Mode if (Ctx->b422Mode == OUTPUT_MODE422_YUY2) { //For YUY2 *(pOut->Ybuff + 6) = ((char *)&pOut->PicInfo.ycom)[3]; *(pOut->Ybuff + 4) = ((char *)&pOut->PicInfo.ycom)[2]; *(pOut->Ybuff + 2) = ((char *)&pOut->PicInfo.ycom)[1]; *(pOut->Ybuff + 0) = ((char *)&pOut->PicInfo.ycom)[0]; } else if (Ctx->b422Mode == OUTPUT_MODE422_UYVY) { //For UYVY *(pOut->Ybuff + 7) = ((char *)&pOut->PicInfo.ycom)[3]; *(pOut->Ybuff + 5) = ((char *)&pOut->PicInfo.ycom)[2]; *(pOut->Ybuff + 3) = ((char *)&pOut->PicInfo.ycom)[1]; *(pOut->Ybuff + 1) = ((char *)&pOut->PicInfo.ycom)[0]; } else { //For NV12 or YV12 *((uint32_t*)&pOut->Ybuff[0]) = pOut->PicInfo.ycom; } } if(Ctx->DevId == BC_PCI_DEVID_FLEA) { //Flea Mode if(pOut->PicInfo.timeStamp == 0xFFFFFFFF) { //For Pre-Load pOut->PicInfo.timeStamp = 0xFFFFFFFFFFFFFFFFLL; } else { //Normal PTS //Change PTS becuase of Shift PTS Issue in FW and 32-bit (ms) and 64-bit (100 ns) Scaling pOut->PicInfo.timeStamp = pOut->PicInfo.timeStamp * 2 * 10000; } } else { /* Retrieve Timestamp */ if(pOut->PicInfo.flags & VDEC_FLAG_PICTURE_META_DATA_PRESENT) { sNum = (uint16_t) ( ( (pOut->PicInfo.picture_meta_payload & 0xFF) << 8) | ((pOut->PicInfo.picture_meta_payload& 0xFF00) >> 8) ); DtsFetchMdata(Ctx,sNum,pOut); } } return BC_STS_SUCCESS; } BC_STATUS DtsUpdateVidParams(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut) { Ctx->VidParams.WidthInPixels = pOut->PicInfo.width; Ctx->VidParams.HeightInPixels = pOut->PicInfo.height; if (pOut->PicInfo.flags & VDEC_FLAG_INTERLACED_SRC) Ctx->VidParams.Progressive = FALSE; else Ctx->VidParams.Progressive = TRUE; return BC_STS_SUCCESS; } BOOL DtsCheckRptPic(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut) { BOOL bRepeat = FALSE; uint8_t nCheckFlag = TOP_FIELD_FLAG; if (pOut->PicInfo.picture_number <3) return FALSE; if (Ctx->bEOS == TRUE) { pOut->PicInfo.flags |= VDEC_FLAG_LAST_PICTURE; return TRUE; } if (Ctx->LastPicNum == pOut->PicInfo.picture_number && Ctx->LastSessNum == pOut->PicInfo.sess_num) { if (Ctx->VidParams.Progressive) nCheckFlag = PROGRESSIVE_FRAME_FLAG; else if((pOut->PicInfo.flags & VDEC_FLAG_BOTTOMFIELD) == VDEC_FLAG_BOTTOMFIELD) nCheckFlag = BOTTOM_FIELD_FLAG; else nCheckFlag = TOP_FIELD_FLAG; //Discard for PullDown int nShift = 2; uint8_t nFlag = Ctx->PullDownFlag; bool bFound = false; while(nFlag) { if((nFlag & 0x03) == nCheckFlag) { bFound = true; break; } nFlag = nFlag >> 2; nShift += 2; } if(!bFound) bRepeat = true; Ctx->PullDownFlag = Ctx->PullDownFlag >> nShift; } else { if (Ctx->VidParams.Progressive) { switch(pOut->PicInfo.pulldown) { case vdecFrame_X1: Ctx->PullDownFlag = 0x0003; //Frame x 1 ==> 00000011 break; case vdecFrame_X2: Ctx->PullDownFlag = 0x000f; //Frame x 2 ==> 00001111 break; case vdecFrame_X3: Ctx->PullDownFlag = 0x003f; //Frame x 3 ==> 00111111 break; case vdecFrame_X4: Ctx->PullDownFlag = 0x00ff; //Frame x 4 ==> 11111111 break; default: Ctx->PullDownFlag = 0x0003; //Frame x 1 ==> 00000011 break; } } else { switch(pOut->PicInfo.pulldown) { case vdecTop: Ctx->PullDownFlag = 0x0001; //Top ==> 00000001 break; case vdecBottom: Ctx->PullDownFlag = 0x0002; //Bottom ==> 00000010 break; case vdecTopBottom: Ctx->PullDownFlag = 0x0009; //TopBottom ==> 00001001 break; case vdecBottomTop: Ctx->PullDownFlag = 0x0006; //BottomTop ==> 00000110 break; case vdecTopBottomTop: Ctx->PullDownFlag = 0x0019; //TopBottomTop ==> 00011001 break; case vdecBottomTopBottom: Ctx->PullDownFlag = 0x0026; //BottomTopBottom ==> 00100110 break; default: Ctx->PullDownFlag = 0x0009; //TopBottom ==> 00001001 break; } } Ctx->EOSCnt = 0; } if (Ctx->bEOSCheck && !Ctx->bEOS) { if (bRepeat) Ctx->EOSCnt ++; if (Ctx->EOSCnt >= BC_EOS_PIC_COUNT) { Ctx->bEOS = true; pOut->PicInfo.flags |= VDEC_FLAG_LAST_PICTURE; } } Ctx->LastPicNum = pOut->PicInfo.picture_number; Ctx->LastSessNum = pOut->PicInfo.sess_num; return bRepeat; } static void DtsSetupProcOutInfo(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut, BC_IOCTL_DATA *pIo) { if(!pOut || !pIo) return; // This is an internal function should never happen.. if(Ctx->RegCfg.DbgOptions & BC_BIT(6)) { /* Decoder PIC_INFO_ON mode, PIB is NOT embedded in frame */ if(pIo->u.DecOutData.Flags & COMP_FLAG_PIB_VALID) { pOut->PoutFlags |= BC_POUT_FLAGS_PIB_VALID; DtsCopyAppPIB(Ctx, &pIo->u.DecOutData, pOut); } if(pIo->u.DecOutData.Flags & COMP_FLAG_DATA_ENC) pOut->PoutFlags |= BC_POUT_FLAGS_ENCRYPTED; if (pOut->PicInfo.flags & VDEC_FLAG_BOTTOMFIELD) pOut->PicInfo.flags |= VDEC_FLAG_INTERLACED_SRC; if (pOut->PicInfo.flags & VDEC_FLAG_INTERLACED_SRC) Ctx->VidParams.Progressive = FALSE; else Ctx->VidParams.Progressive = TRUE; } /* No change in Format Change method */ if(pIo->u.DecOutData.Flags & COMP_FLAG_FMT_CHANGE) { if(pIo->u.DecOutData.Flags & COMP_FLAG_PIB_VALID) { pOut->PoutFlags |= BC_POUT_FLAGS_PIB_VALID; DtsCopyAppPIB(Ctx, &pIo->u.DecOutData, pOut); }else{ DebugLog_Trace(LDIL_DBG,"Error: Can't handle F/C w/o PIB_VALID \n"); return; } Ctx->HWOutPicHeight = pOut->PicInfo.height; // FW returns output picture's stride in PPB.resolution when Format changes. Ctx->HWOutPicWidth = DtsGetHWOutputStride(Ctx,(C011_PIB *)&(pIo->u.DecOutData.PibInfo)); if (pOut->PicInfo.flags & VDEC_FLAG_BOTTOMFIELD) pOut->PicInfo.flags |= VDEC_FLAG_INTERLACED_SRC; pOut->PoutFlags |= BC_POUT_FLAGS_FMT_CHANGE; if(pIo->u.DecOutData.Flags & COMP_FLAG_DATA_VALID){ DebugLog_Trace(LDIL_DBG,"Error: Data not expected with F/C \n"); return; } } if(pIo->u.DecOutData.Flags & COMP_FLAG_DATA_VALID) { pOut->Ybuff = pIo->u.DecOutData.OutPutBuffs.YuvBuff; pOut->YBuffDoneSz = pIo->u.DecOutData.OutPutBuffs.YBuffDoneSz; pOut->YbuffSz = pIo->u.DecOutData.OutPutBuffs.UVbuffOffset; pOut->UVbuff = pIo->u.DecOutData.OutPutBuffs.YuvBuff + pIo->u.DecOutData.OutPutBuffs.UVbuffOffset; pOut->UVBuffDoneSz = pIo->u.DecOutData.OutPutBuffs.UVBuffDoneSz; pOut->UVbuffSz = (pIo->u.DecOutData.OutPutBuffs.YuvBuffSz - pIo->u.DecOutData.OutPutBuffs.UVbuffOffset); pOut->discCnt = pIo->u.DecOutData.BadFrCnt; if(Ctx->FixFlags & DTS_LOAD_FILE_PLAY_FW){ /* Decoder PIC_INFO_OFF mode, PIB is embedded in frame */ DtsGetPictureInfo(Ctx, pOut); } } } // Input Meta Data related funtions.. static BC_STATUS DtsCreateMdataPool(DTS_LIB_CONTEXT *Ctx) { uint32_t i, mpSz =0; DTS_INPUT_MDATA *temp=NULL; mpSz = BC_INPUT_MDATA_POOL_SZ * sizeof(DTS_INPUT_MDATA); if( (Ctx->MdataPoolPtr = malloc(mpSz)) == NULL){ DebugLog_Trace(LDIL_DBG,"Failed to Alloc mem\n"); return BC_STS_INSUFF_RES; } memset(Ctx->MdataPoolPtr,0,mpSz); temp = (DTS_INPUT_MDATA*)Ctx->MdataPoolPtr; Ctx->MDFreeHead = Ctx->MDPendHead = Ctx->MDPendTail = NULL; for(i=0; iflink = Ctx->MDFreeHead; Ctx->MDFreeHead = temp; temp++; } /* Initialize MData Pending list Params */ Ctx->MDPendHead = DTS_MDATA_PEND_LINK(Ctx); Ctx->MDPendTail = DTS_MDATA_PEND_LINK(Ctx); Ctx->InMdataTag = 0; return BC_STS_SUCCESS; } static void DtsMdataSetIntTag(DTS_LIB_CONTEXT *Ctx, DTS_INPUT_MDATA *temp) { uint16_t stemp=0; DtsLock(Ctx); if(Ctx->InMdataTag == 0xFFFF){ // Skip zero seqNum Ctx->InMdataTag = 0; } temp->IntTag = ++Ctx->InMdataTag & (DTS_MDATA_MAX_TAG|DTS_MDATA_TAG_MASK); stemp = (uint16_t)( temp->IntTag & DTS_MDATA_MAX_TAG ); temp->Spes.SeqNum[0] = (uint8_t)(stemp & 0xFF); temp->Spes.SeqNum[1] = (uint8_t)((stemp & 0xFF00) >> 8); DtsUnLock(Ctx); } static uint32_t DtsMdataGetIntTag(DTS_LIB_CONTEXT *Ctx, uint16_t snum) { uint32_t retTag=0; DtsLock(Ctx); retTag = ((Ctx->InMdataTag & DTS_MDATA_TAG_MASK) | snum) ; DtsUnLock(Ctx); return retTag; } static BC_STATUS DtsDeleteMdataPool(DTS_LIB_CONTEXT *Ctx) { DTS_INPUT_MDATA *temp=NULL; if(!Ctx || !Ctx->MdataPoolPtr){ return BC_STS_INV_ARG; } DtsLock(Ctx); /* Remove all Pending elements */ temp = Ctx->MDPendHead; while(temp && temp != DTS_MDATA_PEND_LINK(Ctx)){ DtsRemoveMdata(Ctx,temp,FALSE); temp = Ctx->MDPendHead; } /* Delete Free Pool */ Ctx->MDFreeHead = NULL; if(Ctx->MdataPoolPtr){ free(Ctx->MdataPoolPtr); Ctx->MdataPoolPtr = NULL; } DtsUnLock(Ctx); return BC_STS_SUCCESS; } /*===================== Externs =================================*/ //----------------------------------------------------------------------- // Name: DtsGetContext // Description: Get internal context structure from user handle. //----------------------------------------------------------------------- DTS_LIB_CONTEXT * DtsGetContext(HANDLE userHnd) { DTS_LIB_CONTEXT *AppCtx = (DTS_LIB_CONTEXT *)userHnd; if(!AppCtx) return NULL; if(AppCtx->Sig != LIB_CTX_SIG) return NULL; return AppCtx; } //----------------------------------------------------------------------- // Name: DtsIsPend // Description: Check for Pending request.. //----------------------------------------------------------------------- BOOL DtsIsPend(DTS_LIB_CONTEXT *Ctx) { BOOL res =FALSE; DtsLock(Ctx); res = (Ctx->ProcOutPending); DtsUnLock(Ctx); return res; } //----------------------------------------------------------------------- // Name: DtsDrvIoctl // Description: Wrapper for windows IOCTL. //----------------------------------------------------------------------- BOOL DtsDrvIoctl ( HANDLE userHandle, DWORD dwIoControlCode, LPVOID lpInBuffer, DWORD nInBufferSize, LPVOID lpOutBuffer, DWORD nOutBufferSize, LPDWORD lpBytesReturned, BOOL Async ) { DTS_LIB_CONTEXT * Ctx = DtsGetContext(userHandle); //unused DWORD dwTimeout = 0; BC_STATUS sts; if( !Ctx ) return FALSE; if(Ctx->Sig != LIB_CTX_SIG) return FALSE; // == FIX ME == // We need to take care of Async ioctl. // WILL need to take care of lb bytes returned. // Check the existing code. // if(BC_STS_SUCCESS != (sts = DtsDrvCmd(Ctx,dwIoControlCode,Async,(BC_IOCTL_DATA *)lpInBuffer,FALSE))) { DebugLog_Trace(LDIL_DBG, "DtsDrvCmd Failed with status %d\n", sts); return FALSE; } return TRUE; } //------------------------------------------------------------------------ // Name: DtsDrvCmd // Description: Wrapper for windows IOCTL using the internal pre-allocated // IOCTL_DATA structure. And waits for the completion incase // Async path. //------------------------------------------------------------------------ BC_STATUS DtsDrvCmd(DTS_LIB_CONTEXT *Ctx, DWORD Code, BOOL Async, BC_IOCTL_DATA *pIoData, BOOL Rel) { int rc; //DWORD BytesReturned=0; BOOL locRel=FALSE;//,bRes=0; //DWORD dwTimeout = 0; BC_IOCTL_DATA *pIo = NULL; BC_STATUS Sts = BC_STS_SUCCESS ; int i = 30; if(!Ctx || !Ctx->DevHandle){ DebugLog_Trace(LDIL_DBG,"Invalid arg..%p \n",Ctx); return BC_STS_INV_ARG; } if(!pIoData){ if(! (pIo = DtsAllocIoctlData(Ctx)) ){ return BC_STS_INSUFF_RES; } locRel = TRUE; }else{ pIo = pIoData; } pIo->RetSts = BC_STS_SUCCESS; // We need to take care of async completion. // == FIX ME == // We allow only one FW command at a time for LINK // prevent additional fw commands from other threads if(Ctx->DevId == BC_PCI_DEVID_LINK && Code == BCM_IOC_FW_CMD) { while(Ctx->fw_cmd_issued && (i > 0)) { usleep(100); i--; } if (i == 0) return BC_STS_ERROR; // cannot issue second FW command while one is pending Ctx->fw_cmd_issued = true; } rc = ioctl(Ctx->DevHandle, Code, pIo); Sts = pIo->RetSts; if(Ctx->DevId == BC_PCI_DEVID_LINK && Code == BCM_IOC_FW_CMD) { Ctx->fw_cmd_issued = false; // FW commands complete synchronously } if (locRel || Rel) DtsRelIoctlData(Ctx, pIo); if (rc < 0) { DebugLog_Trace(LDIL_DBG,"IOCTL Command Failed %d cmd %x sts %d\n", rc, Code, Sts); return BC_STS_ERROR; } return Sts; } //------------------------------------------------------------------------ // Name: DtsRelIoctlData // Description: Release IOCTL_DATA back to the pool. //------------------------------------------------------------------------ void DtsRelIoctlData(DTS_LIB_CONTEXT *Ctx, BC_IOCTL_DATA *pIoData) { DtsLock(Ctx); pIoData->next = Ctx->pIoDataFreeHd; Ctx->pIoDataFreeHd = pIoData; DtsUnLock(Ctx); } //------------------------------------------------------------------------ // Name: DtsAllocIoctlData // Description: Acquire IOCTL_DATA From pool. //------------------------------------------------------------------------ BC_IOCTL_DATA *DtsAllocIoctlData(DTS_LIB_CONTEXT *Ctx) { BC_IOCTL_DATA *temp=NULL; DtsLock(Ctx); if((temp=Ctx->pIoDataFreeHd) != NULL){ Ctx->pIoDataFreeHd = Ctx->pIoDataFreeHd->next; memset(temp,0,sizeof(*temp)); } DtsUnLock(Ctx); if(!temp){ DebugLog_Trace(LDIL_DBG,"DtsAllocIoctlData Error\n"); } return temp; } //------------------------------------------------------------------------ // Name: DtsAllocMemPools // Description: Allocate memory for application specific configs and RxBuffs //------------------------------------------------------------------------ BC_STATUS DtsAllocMemPools(DTS_LIB_CONTEXT *Ctx) { uint32_t i, Sz; DTS_MPOOL_TYPE *mp; BC_IOCTL_DATA *pIoData; BC_STATUS sts = BC_STS_SUCCESS; if(!Ctx){ return BC_STS_INV_ARG; } DtsInitLock(Ctx); for(i=0; i< BC_IOCTL_DATA_POOL_SIZE; i++){ pIoData = (BC_IOCTL_DATA *) malloc(sizeof(BC_IOCTL_DATA)); if(!pIoData){ DebugLog_Trace(LDIL_DBG,"DtsInitMemPools: ioctlData pool Alloc Failed\n"); return BC_STS_INSUFF_RES; } DtsRelIoctlData(Ctx,pIoData); } Ctx->pOutData = (BC_IOCTL_DATA *) malloc(sizeof(BC_IOCTL_DATA)); if(!Ctx->pOutData){ DebugLog_Trace(LDIL_DBG,"DtsInitMemPools: pOutData \n"); return BC_STS_INSUFF_RES; } if((Ctx->OpMode != DTS_PLAYBACK_MODE) && (Ctx->OpMode != DTS_DIAG_MODE)) return BC_STS_SUCCESS; sts = DtsCreateMdataPool(Ctx); if(sts != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"InMdata PoolCreation Failed:%x\n",sts); return sts; } if(!(Ctx->CfgFlags & BC_MPOOL_INCL_YUV_BUFFS)){ return BC_STS_SUCCESS; } Ctx->MpoolCnt = BC_MAX_SW_VOUT_BUFFS; Ctx->Mpools = (DTS_MPOOL_TYPE*)malloc(Ctx->MpoolCnt * sizeof(DTS_MPOOL_TYPE)); if(!Ctx->Mpools){ DebugLog_Trace(LDIL_DBG,"DtsInitMemPools: Mpool alloc failed\n"); return BC_STS_INSUFF_RES; } memset(Ctx->Mpools,0,(Ctx->MpoolCnt * sizeof(DTS_MPOOL_TYPE))); DtsGetMaxSize(Ctx,&Sz); for(i=0; iMpools[i]; mp->type = BC_MEM_DEC_YUVBUFF |BC_MEM_USER_MODE_ALLOC; mp->sz = Sz; mp->buff = (uint8_t *)malloc(mp->sz); if(!mp->buff){ DebugLog_Trace(LDIL_DBG,"DtsInitMemPools: Mpool %x failed\n",mp->type); return BC_STS_INSUFF_RES; } //DebugLog_Trace(LDIL_DBG,"DtsInitMemPools: Alloc Mpool %x Buff:%p\n",mp->type,mp->buff); memset(mp->buff,0,mp->sz); } return BC_STS_SUCCESS; } BC_STATUS DtsAllocMemPools_dbg(DTS_LIB_CONTEXT *Ctx) { uint32_t i; BC_IOCTL_DATA *pIoData; if(!Ctx){ return BC_STS_INV_ARG; } DtsInitLock(Ctx); for(i=0; i< BC_IOCTL_DATA_POOL_SIZE; i++){ pIoData = (BC_IOCTL_DATA *) malloc(sizeof(BC_IOCTL_DATA)); if(!pIoData){ DebugLog_Trace(LDIL_DBG,"DtsInitMemPools: ioctlData pool Alloc Failed\n"); return BC_STS_INSUFF_RES; } DtsRelIoctlData(Ctx,pIoData); } Ctx->pOutData = (BC_IOCTL_DATA *) malloc(sizeof(BC_IOCTL_DATA)); if(!Ctx->pOutData){ DebugLog_Trace(LDIL_DBG,"DtsInitMemPools: pOutData \n"); return BC_STS_INSUFF_RES; } return BC_STS_SUCCESS; } //------------------------------------------------------------------------ // Name: DtsReleaseMemPools // Description: Release application specific allocations. //------------------------------------------------------------------------ void DtsReleaseMemPools(DTS_LIB_CONTEXT *Ctx) { uint32_t i,cnt=0; DTS_MPOOL_TYPE *mp; BC_IOCTL_DATA *pIoData = NULL; if (!Ctx) //vgd return; /* need to release any user buffers mapped in driver * or free(mp->buff) can hang under Linux and Mac OS X */ pIoData = DtsAllocIoctlData(Ctx); if (pIoData) { pIoData->u.FlushRxCap.bDiscardOnly = TRUE; DtsDrvCmd(Ctx, BCM_IOC_FLUSH_RX_CAP, 0, pIoData, TRUE); } if (Ctx->MpoolCnt) { for (i = 0; i < Ctx->MpoolCnt; i++){ mp = &Ctx->Mpools[i]; if (mp->buff){ //DebugLog_Trace(LDIL_DBG,"DtsReleaseMemPools: Free Mpool %x Buff:%p\n",mp->type,mp->buff); free(mp->buff); } } free(Ctx->Mpools); } /* Release IOCTL_DATA pool */ while((pIoData=DtsAllocIoctlData(Ctx))!=NULL){ free(pIoData); cnt++; } if(cnt != BC_IOCTL_DATA_POOL_SIZE){ DebugLog_Trace(LDIL_DBG,"DtsReleaseMemPools: pIoData MemPool Leak: %d..\n",cnt); } if(Ctx->pOutData) free(Ctx->pOutData); if(Ctx->MdataPoolPtr) DtsDeleteMdataPool(Ctx); if (Ctx->VidParams.pMetaData) free(Ctx->VidParams.pMetaData); DtsDelLock(Ctx); } void DtsReleaseMemPools_dbg(DTS_LIB_CONTEXT *Ctx) { uint32_t cnt=0; BC_IOCTL_DATA *pIoData = NULL; if(!Ctx || !Ctx->Mpools){ return; } /* Release IOCTL_DATA pool */ while((pIoData=DtsAllocIoctlData(Ctx))!=NULL){ free(pIoData); cnt++; } if(cnt != BC_IOCTL_DATA_POOL_SIZE){ DebugLog_Trace(LDIL_DBG,"DtsReleaseMemPools: pIoData MemPool Leak: %d..\n",cnt); } if(Ctx->pOutData) free(Ctx->pOutData); } //------------------------------------------------------------------------ // Name: DtsAddOutBuff // Description: Pass on user mode allocated Rx buffs to driver. //------------------------------------------------------------------------ BC_STATUS DtsAddOutBuff(DTS_LIB_CONTEXT *Ctx, uint8_t *buff, uint32_t BuffSz, uint32_t flags) { uint32_t YbSz, UVbSz; BC_IOCTL_DATA *pIocData = NULL; if(!Ctx || !buff) return BC_STS_INV_ARG; if(!(pIocData = DtsAllocIoctlData(Ctx))) { DebugLog_Trace(LDIL_DBG,"Cannot Allocate IOCTL data\n"); return BC_STS_INSUFF_RES; } DtsGetMaxYUVSize(Ctx, &YbSz, &UVbSz); pIocData->u.RxBuffs.YuvBuff = buff; pIocData->u.RxBuffs.YuvBuffSz = YbSz + UVbSz; if(Ctx->b422Mode) { pIocData->u.RxBuffs.b422Mode = Ctx->b422Mode; pIocData->u.RxBuffs.UVbuffOffset = 0; }else{ pIocData->u.RxBuffs.b422Mode = FALSE; pIocData->u.RxBuffs.UVbuffOffset = YbSz; } return DtsDrvCmd(Ctx,BCM_IOC_ADD_RXBUFFS,0, pIocData, TRUE); } //------------------------------------------------------------------------ // Name: DtsRelRxBuff // Description: Release Rx buffers back to driver. //------------------------------------------------------------------------ BC_STATUS DtsRelRxBuff(DTS_LIB_CONTEXT *Ctx, BC_DEC_YUV_BUFFS *buff, BOOL SkipAddBuff) { BC_STATUS sts; if(!Ctx || !buff) { DebugLog_Trace(LDIL_DBG,"DtsRelRxBuff: Invalid Arguments\n"); return BC_STS_INV_ARG; } if(SkipAddBuff){ DtsDecPend(Ctx); return BC_STS_SUCCESS; } Ctx->pOutData->u.RxBuffs.b422Mode = Ctx->b422Mode; Ctx->pOutData->u.RxBuffs.UVBuffDoneSz =0; Ctx->pOutData->u.RxBuffs.YBuffDoneSz=0; sts = DtsDrvCmd(Ctx,BCM_IOC_ADD_RXBUFFS,0, Ctx->pOutData, FALSE); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"DtsRelRxBuff: Failed Sts:%x .. \n",sts); } if(sts == BC_STS_SUCCESS) DtsDecPend(Ctx); return sts; } //------------------------------------------------------------------------ // Name: DtsFetchOutInterruptible // Description: Get uncompressed video data from hardware. // This function is interruptable procOut for // multi-threaded scenerios ONLY.. //------------------------------------------------------------------------ BC_STATUS DtsFetchOutInterruptible(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut, uint32_t dwTimeout) { BC_STATUS sts = BC_STS_SUCCESS; if(!Ctx || !pOut) return BC_STS_INV_ARG; if(DtsIsPend(Ctx)){ DebugLog_Trace(LDIL_DBG,"DtsFetchOutInterruptible: ProcOutput Pending.. \n"); return BC_STS_BUSY; } DtsIncPend(Ctx); memset(Ctx->pOutData,0,sizeof(*Ctx->pOutData)); sts=DtsDrvCmd(Ctx,BCM_IOC_FETCH_RXBUFF,0,Ctx->pOutData,FALSE); if(sts == BC_STS_SUCCESS) { DtsSetupProcOutInfo(Ctx,pOut,Ctx->pOutData); sts = Ctx->pOutData->RetSts; if(sts != BC_STS_SUCCESS) { DtsDecPend(Ctx); } }else{ DebugLog_Trace(LDIL_DBG,"DtsFetchOutInterruptible: Failed:%x\n",sts); DtsDecPend(Ctx); } if(!Ctx->CancelWaiting) return sts; /* Cancel request waiting.. Release Buffer back * to driver and trigger Cancel wait. */ if(sts == BC_STS_SUCCESS){ sts = BC_STS_IO_USER_ABORT; DtsRelRxBuff(Ctx,&Ctx->pOutData->u.RxBuffs,FALSE); } return sts; } //------------------------------------------------------------------------ // Name: DtsCancelFetchOutInt // Description: Cancel Pending ProcOut Request.. //------------------------------------------------------------------------ BC_STATUS DtsCancelFetchOutInt(DTS_LIB_CONTEXT *Ctx) { bool pend = false; uint32_t cnt; if(!(DtsIsPend(Ctx))){ return BC_STS_SUCCESS; } Ctx->CancelWaiting = 1; /* Worst case scenerio the timeout should happen.. */ cnt = BC_PROC_OUTPUT_TIMEOUT / 100; do{ usleep(100 * 1000); pend = DtsIsPend(Ctx); }while( (pend) && (cnt--) ); if(pend){ DebugLog_Trace(LDIL_DBG,"DtsCancelFetchOutInt: TimeOut\n"); Ctx->CancelWaiting = 0; return BC_STS_TIMEOUT; } Ctx->CancelWaiting = 0; return BC_STS_SUCCESS; } //------------------------------------------------------------------------ // Name: DtsMapYUVBuffs // Description: Pass user mode pre-allocated buffers to driver for mapping. //------------------------------------------------------------------------ BC_STATUS DtsMapYUVBuffs(DTS_LIB_CONTEXT *Ctx) { uint32_t i; BC_STATUS sts; DTS_MPOOL_TYPE *mp; if (Ctx->bMapOutBufDone) return BC_STS_SUCCESS; if(!Ctx->Mpools || !(Ctx->CfgFlags & BC_MPOOL_INCL_YUV_BUFFS)){ return BC_STS_SUCCESS; } for(i=0; iMpoolCnt; i++){ mp = &Ctx->Mpools[i]; if(mp->type & BC_MEM_DEC_YUVBUFF){ sts = DtsAddOutBuff(Ctx, mp->buff,mp->sz, mp->type); if(sts != BC_STS_SUCCESS) { DebugLog_Trace(LDIL_DBG,"Map YUV buffs Failed [%x]\n",sts); return sts; } } } Ctx->bMapOutBufDone = true; return BC_STS_SUCCESS; } //------------------------------------------------------------------------ // Name: DtsInitInterface // Description: Do application specific allocation and other initialization. //------------------------------------------------------------------------ BC_STATUS DtsInitInterface(int hDevice, HANDLE *RetCtx, uint32_t mode) { DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_SUCCESS; pthread_attr_t thread_attr; int ret = 0; Ctx = (DTS_LIB_CONTEXT*)malloc(sizeof(*Ctx)); if(!Ctx){ DebugLog_Trace(LDIL_DBG,"DtsInitInterface: Ctx alloc failed\n"); return BC_STS_INSUFF_RES; } memset(Ctx,0,sizeof(*Ctx)); /* Initialize Application specific params. */ Ctx->Sig = LIB_CTX_SIG; Ctx->DevHandle = hDevice; Ctx->OpMode = mode; Ctx->CfgFlags = BC_DTS_DEF_CFG; Ctx->b422Mode = OUTPUT_MODE420; Ctx->VidParams.MediaSubType = BC_MSUBTYPE_INVALID; Ctx->VidParams.StartCodeSz = 0; Ctx->VidParams.StreamType = BC_STREAM_TYPE_ES; // Ctx->InSampleCount = 0; /* Set Pixel height & width */ if(Ctx->CfgFlags & BC_PIX_WID_1080){ Ctx->VidParams.HeightInPixels = 1080; Ctx->VidParams.WidthInPixels = 1920; }else{ Ctx->VidParams.HeightInPixels = 720; Ctx->VidParams.WidthInPixels = 1280; } Ctx->VidParams.pMetaData = NULL; sts = DtsAllocMemPools(Ctx); if(sts != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsAllocMemPools failed Sts:%d\n",sts); *RetCtx = (HANDLE)Ctx; return sts; } if(!(Ctx->CfgFlags & BC_ADDBUFF_MOVE)){ sts = DtsMapYUVBuffs(Ctx); if(sts != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsMapYUVBuffs failed Sts:%d\n",sts); *RetCtx = (HANDLE)Ctx; return sts; } } // Allocate circular buffer if(BC_STS_SUCCESS != txBufInit(&Ctx->circBuf, CIRC_TX_BUF_SIZE)) sts = BC_STS_INSUFF_RES; pthread_attr_init(&thread_attr); pthread_attr_setdetachstate(&thread_attr, PTHREAD_CREATE_JOINABLE); pthread_create(&Ctx->htxThread, &thread_attr, txThreadProc, Ctx); pthread_attr_destroy(&thread_attr); ret = posix_memalign((void**)&Ctx->alignBuf, 128, ALIGN_BUF_SIZE); if(ret) sts = BC_STS_INSUFF_RES; *RetCtx = (HANDLE)Ctx; return sts; } //------------------------------------------------------------------------ // Name: DtsReleaseInterface // Description: Do application specific Release and other initialization. //------------------------------------------------------------------------ BC_STATUS DtsReleaseInterface(DTS_LIB_CONTEXT *Ctx) { if(!Ctx) return BC_STS_INV_ARG; // Exit TX thread Ctx->txThreadExit = true; // wait to make sure the thread exited pthread_join(Ctx->htxThread, NULL); // de-Allocate circular buffer txBufFree(&Ctx->circBuf); Ctx->htxThread = 0; if(Ctx->alignBuf) free(Ctx->alignBuf); DtsReleaseMemPools(Ctx); if(Ctx->DevHandle != 0) //Zero if success { DtsReleaseUserHandle(Ctx); if(0 != close(Ctx->DevHandle)) DebugLog_Trace(LDIL_DBG,"DtsDeviceClose: Close Handle Failed with error %d\n",errno); } DtsSetHwInitSts(BC_DIL_HWINIT_NOT_YET); DtsDelDilShMem(); free(Ctx); return BC_STS_SUCCESS; } //------------------------------------------------------------------------ // Name: DtsReleaseUserHandle // Description: Notfiy the driver to release the user handle // Should be called right before close //------------------------------------------------------------------------ BC_STATUS DtsReleaseUserHandle(DTS_LIB_CONTEXT* Ctx) { BC_IOCTL_DATA pIo; BC_STATUS sts = BC_STS_SUCCESS; memset(&pIo, 0, sizeof(BC_IOCTL_DATA)); if( (sts=DtsDrvCmd(Ctx,BCM_IOC_RELEASE,0,&pIo,FALSE)) != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsReleaseUserHandle: Ioctl failed: %d\n",sts); return sts; } return sts; } //------------------------------------------------------------------------ // Name: DtsNotifyOperatingMode // Description: Notfiy the operating mode to driver. //------------------------------------------------------------------------ BC_STATUS DtsNotifyOperatingMode(HANDLE hDevice,uint32_t Mode) { BC_IOCTL_DATA *pIocData = NULL; DTS_LIB_CONTEXT *Ctx = NULL; BC_STATUS sts = BC_STS_SUCCESS; DTS_GET_CTX(hDevice,Ctx); if(!(pIocData = DtsAllocIoctlData(Ctx))) return BC_STS_INSUFF_RES; pIocData->u.NotifyMode.Mode = Mode ; /* Setting the 31st bit to indicate that this is not the timeout value */ if( (sts=DtsDrvCmd(Ctx,BCM_IOC_NOTIFY_MODE,0,pIocData,FALSE)) != BC_STS_SUCCESS){ DtsRelIoctlData(Ctx,pIocData); DebugLog_Trace(LDIL_DBG,"DtsNotifyMode: Ioctl failed: %d\n",sts); return sts; } DtsRelIoctlData(Ctx,pIocData); return sts; } //------------------------------------------------------------------------ // Name: DtsSetupConfiguration // Description: Setup HW specific Configuration. //------------------------------------------------------------------------ BC_STATUS DtsSetupConfig(DTS_LIB_CONTEXT *Ctx, uint32_t did, uint32_t rid, uint32_t FixFlags) { Ctx->DevId = did; Ctx->hwRevId = rid; Ctx->FixFlags = FixFlags; if(Ctx->DevId == BC_PCI_DEVID_LINK){ Ctx->RegCfg.DbgOptions = BC_DTS_DEF_OPTIONS_LINK; }else{ Ctx->RegCfg.DbgOptions = BC_DTS_DEF_OPTIONS; } DtsGetBCRegConfig(Ctx); //Forcing the use of certificate in case of Link. if( (Ctx->DevId == BC_PCI_DEVID_LINK)&& (!(Ctx->RegCfg.DbgOptions & BC_BIT(5))) ){ Ctx->RegCfg.DbgOptions |= BC_BIT(5); } Ctx->capInfo.ColorCaps.Count = 0; if (Ctx->DevId == BC_PCI_DEVID_LINK) { Ctx->capInfo.ColorCaps.Count =3; Ctx->capInfo.ColorCaps.OutFmt[0] = OUTPUT_MODE420; Ctx->capInfo.ColorCaps.OutFmt[1] = OUTPUT_MODE422_YUY2; Ctx->capInfo.ColorCaps.OutFmt[2] = OUTPUT_MODE422_UYVY; Ctx->capInfo.flags = PES_CONV_SUPPORT; //Decoder Capability Ctx->capInfo.DecCaps = BC_DEC_FLAGS_H264 | BC_DEC_FLAGS_MPEG2 | BC_DEC_FLAGS_VC1; } else if(Ctx->DevId == BC_PCI_DEVID_DOZER) { Ctx->capInfo.ColorCaps.Count =1; Ctx->capInfo.ColorCaps.OutFmt[0] = OUTPUT_MODE420; Ctx->capInfo.flags = PES_CONV_SUPPORT; //Decoder Capability Ctx->capInfo.DecCaps = BC_DEC_FLAGS_H264 | BC_DEC_FLAGS_MPEG2 | BC_DEC_FLAGS_VC1; } Ctx->capInfo.Reserved1 = NULL; return BC_STS_SUCCESS; } //------------------------------------------------------------------------ // Name: DtsGetBCRegConfig // Description: Setup Register Sub-Key values. //------------------------------------------------------------------------ BC_STATUS DtsGetBCRegConfig(DTS_LIB_CONTEXT *Ctx) { return BC_STS_NOT_IMPL; } int dtscallback(struct dl_phdr_info *info, size_t size, void *data) { int ret=0,dilpath_len=0; //char* pSearchStr = (char*)info->dlpi_name; char * temp=NULL; //temp = strstr((char *)pSearchStr,(const char *)"/libdil.so"); if(NULL != (temp= (char *)strstr(info->dlpi_name,(const char *)"/libcrystal.so"))){ /*we found the loaded dil, set teh return value to non-zero so that the callback won't be called anymore*/ ret = 1; } if(ret!=0){ dilpath_len = (temp-info->dlpi_name)+1; //we want the slash also to be copied strncpy((char*)data, info->dlpi_name,dilpath_len); } return dilpath_len; } //------------------------------------------------------------------------ // Name: DtsGetFirmwareFiles // Description: Setup Firmware Filenames. //------------------------------------------------------------------------ BC_STATUS DtsGetFirmwareFiles(DTS_LIB_CONTEXT *Ctx) { int fwfile_len; char fwfile[MAX_PATH + 1]; char fwfilepath[MAX_PATH + 1]; #ifndef __APPLE__ const char fwdir[] = "/lib/firmware/"; #else const char fwdir[] = "/usr/lib/"; #endif if(Ctx->DevId == BC_PCI_DEVID_FLEA) { fwfile_len = strlen(FWBINFILE_70015); strncpy(fwfile, FWBINFILE_70015, fwfile_len); } else { fwfile_len = strlen(FWBINFILE_70012); strncpy(fwfile, FWBINFILE_70012, fwfile_len); } if ((strlen(fwdir) + fwfile_len) > (MAX_PATH + 1)) { DebugLog_Trace(LDIL_DATA,"DtsGetFirmwareFiles:Path is too large ...."); return BC_STS_ERROR; } strncpy(fwfilepath, fwdir, strlen(fwdir) + 1); strncat(fwfilepath, fwfile, fwfile_len); fwfilepath[strlen(fwdir) + fwfile_len] = '\0'; strncpy(Ctx->FwBinFile, fwfilepath, strlen(fwdir) + fwfile_len); return BC_STS_SUCCESS; } //------------------------------------------------------------------------ // Name: DtsAllocMdata // Description: Get Mdata from free pool. //------------------------------------------------------------------------ DTS_INPUT_MDATA *DtsAllocMdata(DTS_LIB_CONTEXT *Ctx) { DTS_INPUT_MDATA *temp = NULL; if(!Ctx) return temp; DtsLock(Ctx); if((temp=Ctx->MDFreeHead) != NULL) { Ctx->MDFreeHead = Ctx->MDFreeHead->flink; memset(temp, 0, sizeof(*temp)); } else { //Use the Last Un-Fetched One DTS_INPUT_MDATA *last = NULL; last = Ctx->MDPendHead; //Check the Last Fetch Tag if((last) && (Ctx->MDLastFetchTag > (last->IntTag + MAX_DISORDER_GAP))) { //Remove DtsRemoveMdata(Ctx, last, FALSE); if((temp = Ctx->MDFreeHead) != NULL) { Ctx->MDFreeHead = Ctx->MDFreeHead->flink; memset(temp, 0, sizeof(*temp)); } } } DtsUnLock(Ctx); return temp; } //------------------------------------------------------------------------ // Name: DtsFreeMdata // Description: Free Mdata from to pool. //------------------------------------------------------------------------ BC_STATUS DtsFreeMdata(DTS_LIB_CONTEXT *Ctx, DTS_INPUT_MDATA *Mdata, BOOL sync) { if(!Ctx || !Mdata){ return BC_STS_INV_ARG; } if(sync) DtsLock(Ctx); Mdata->flink = Ctx->MDFreeHead; Ctx->MDFreeHead = Mdata; if(sync) DtsUnLock(Ctx); return BC_STS_SUCCESS; } //------------------------------------------------------------------------ // Name: DtsClrPendMdataList // Description: Release all pending list back to free pool. //------------------------------------------------------------------------ BC_STATUS DtsClrPendMdataList(DTS_LIB_CONTEXT *Ctx) { DTS_INPUT_MDATA *temp=NULL; int mdata_count = 0; if(!Ctx || !Ctx->MdataPoolPtr){ return BC_STS_INV_ARG; } DtsLock(Ctx); /* Remove all Pending elements */ temp = Ctx->MDPendHead; while(temp && temp != DTS_MDATA_PEND_LINK(Ctx)){ //DebugLog_Trace(LDIL_DBG,"Clearing PendMdata %p %x \n", temp->Spes.SeqNum, temp->IntTag); DtsRemoveMdata(Ctx,temp,FALSE); temp = Ctx->MDPendHead; mdata_count++; } if (mdata_count) DebugLog_Trace(LDIL_DBG,"Clearing %d PendMdata entries \n", mdata_count); DtsUnLock(Ctx); return BC_STS_SUCCESS; } //------------------------------------------------------------------------ // Name: DtsPendMdataGarbageCollect // Description: Garbage Collect Meta Data. This funtion is only called // internel when we run out of Mdata. //------------------------------------------------------------------------ BC_STATUS DtsPendMdataGarbageCollect(DTS_LIB_CONTEXT *Ctx) { DTS_INPUT_MDATA *temp=NULL; int mdata_count = 0; if(!Ctx || !Ctx->MdataPoolPtr){ return BC_STS_INV_ARG; } DtsLock(Ctx); /* Collect garbage it */ temp = Ctx->MDPendHead; while(temp && temp != DTS_MDATA_PEND_LINK(Ctx)){ //DebugLog_Trace(LDIL_DBG,"Clearing PendMdata %p %x \n", temp->Spes.SeqNum, temp->IntTag); if(mdata_count > (BC_INPUT_MDATA_POOL_SZ - BC_INPUT_MDATA_POOL_SZ_COLLECT)) { break; } DtsRemoveMdata(Ctx,temp,FALSE); temp = Ctx->MDPendHead; mdata_count++; } if (mdata_count) DebugLog_Trace(LDIL_DBG,"Clearing %d PendMdata entries \n", mdata_count); DtsUnLock(Ctx); return BC_STS_SUCCESS; } //------------------------------------------------------------------------ // Name: DtsInsertMdata // Description: Insert Meta Data into list. //------------------------------------------------------------------------ BC_STATUS DtsInsertMdata(DTS_LIB_CONTEXT *Ctx, DTS_INPUT_MDATA *Mdata) { if(!Ctx || !Mdata){ return BC_STS_INV_ARG; } DtsLock(Ctx); Mdata->flink = DTS_MDATA_PEND_LINK(Ctx); Mdata->blink = Ctx->MDPendTail; Mdata->flink->blink = Mdata; Mdata->blink->flink = Mdata; DtsUnLock(Ctx); return BC_STS_SUCCESS; } //------------------------------------------------------------------------ // Name: DtsRemoveMdata // Description: Remove Meta Data From List. //------------------------------------------------------------------------ BC_STATUS DtsRemoveMdata(DTS_LIB_CONTEXT *Ctx, DTS_INPUT_MDATA *Mdata, BOOL sync) { if(!Ctx || !Mdata){ return BC_STS_INV_ARG; } if(sync) DtsLock(Ctx); if(Ctx->MDPendHead != DTS_MDATA_PEND_LINK(Ctx)) { Mdata->flink->blink = Mdata->blink; Mdata->blink->flink = Mdata->flink; } if(sync) DtsUnLock(Ctx); return DtsFreeMdata(Ctx,Mdata,sync); } //------------------------------------------------------------------------ // Name: DtsFetchMdata // Description: Get Input Meta Data. // // FIX_ME:: Fill the pout part after FW upgrade with SeqNum feature.. //------------------------------------------------------------------------ BC_STATUS DtsFetchMdata(DTS_LIB_CONTEXT *Ctx, uint16_t snum, BC_DTS_PROC_OUT *pout) { uint32_t InTag; DTS_INPUT_MDATA *temp=NULL; BC_STATUS sts = BC_STS_NO_DATA; int16_t tsnum = 0; uint32_t i = 0; if(!Ctx || !pout){ return BC_STS_INV_ARG; } if(!snum){ // Zero is not a valid SeqNum. pout->PicInfo.timeStamp = 0; DebugLog_Trace(LDIL_DBG,"ZeroSnum \n"); return BC_STS_NO_DATA; } InTag = DtsMdataGetIntTag(Ctx,snum); temp = Ctx->MDPendHead; DtsLock(Ctx); while(temp && temp != DTS_MDATA_PEND_LINK(Ctx)){ if(temp->IntTag == InTag){ pout->PicInfo.timeStamp = temp->appTimeStamp; sts = BC_STS_SUCCESS; DtsRemoveMdata(Ctx, temp, FALSE); //Reserve the Last Fetch Tag Ctx->MDLastFetchTag = InTag; break; } temp = temp->flink; } DtsUnLock(Ctx); // If we found a tag, clear out all the old entries - from (tag - 10) to (tag-110) // This is to work around the issue of lost pictures for which tags will never get freed if(sts == BC_STS_SUCCESS) { for(i = 0; i < 100; i++) { tsnum = snum - (10 + i); if(tsnum < 0) break; InTag = DtsMdataGetIntTag(Ctx, tsnum); temp = Ctx->MDPendHead; DtsLock(Ctx); while(temp && temp != DTS_MDATA_PEND_LINK(Ctx)){ if(temp->IntTag == InTag){ DtsRemoveMdata(Ctx, temp, FALSE); break; } temp = temp->flink; } DtsUnLock(Ctx); } } return sts; } //------------------------------------------------------------------------ // Name: DtsFetchTimeStampMdata // Description: Get the Timestamp from the Meta Data field with the specifc picture number. // Do not change the mdata list in any way. // //------------------------------------------------------------------------ BC_STATUS DtsFetchTimeStampMdata(DTS_LIB_CONTEXT *Ctx, uint16_t snum, uint64_t *TimeStamp) { uint32_t InTag; DTS_INPUT_MDATA *temp=NULL; BC_STATUS sts = BC_STS_NO_DATA; if(!Ctx) { return BC_STS_INV_ARG; } if(!snum) { /* Zero is not a valid SeqNum. */ *TimeStamp = 0; return BC_STS_NO_DATA; } InTag = DtsMdataGetIntTag(Ctx, snum); temp = Ctx->MDPendHead; DtsLock(Ctx); while(temp && temp != DTS_MDATA_PEND_LINK(Ctx)) { if(temp->IntTag == InTag) { *TimeStamp = temp->appTimeStamp; /* DebugLog_Trace(LDIL_DBG, "Found entry for %x %x tstamp: %x\n", */ /* snum, temp->IntTag, pout->PicInfo.timeStamp); */ sts = BC_STS_SUCCESS; break; } temp = temp->flink; } DtsUnLock(Ctx); return sts; } //------------------------------------------------------------------------ // Name: DtsPrepareMdata // Description: Insert Meta Data.. //------------------------------------------------------------------------ BC_STATUS DtsPrepareMdata(DTS_LIB_CONTEXT *Ctx, uint64_t timeStamp, DTS_INPUT_MDATA **mData, uint8_t** ppData, uint32_t *pSize) { DTS_INPUT_MDATA *temp = NULL; BC_STATUS ret; if( !mData || !Ctx) return BC_STS_INV_ARG; /* Alloc clears all fields */ if( (temp = DtsAllocMdata(Ctx)) == NULL) { DebugLog_Trace(LDIL_DBG,"COULD not find free MDATA try again\n"); ret = DtsPendMdataGarbageCollect(Ctx); if(ret != BC_STS_SUCCESS) { return BC_STS_BUSY; } if( (temp = DtsAllocMdata(Ctx)) == NULL) { DebugLog_Trace(LDIL_DBG,"COULD not find free MDATA finaly failed\n"); return BC_STS_BUSY; } } /* Store all app data */ DtsMdataSetIntTag(Ctx,temp); temp->appTimeStamp = timeStamp; /* Fill spes data.. */ temp->Spes.StartCode[0] = 0; temp->Spes.StartCode[1] = 0; temp->Spes.StartCode[2] = 01; temp->Spes.StartCode[3] = 0xBD; temp->Spes.PacketLen = 0x07; temp->Spes.StartCodeEnd = 0x40; temp->Spes.Command = 0x0A; *mData = temp; *ppData = (uint8_t*)(&temp->Spes); *pSize = sizeof(temp->Spes); return BC_STS_SUCCESS; } //------------------------------------------------------------------------ // Name: DtsPrepareMdataASFHdr // Description: Insert Meta Data.. //------------------------------------------------------------------------ BC_STATUS DtsPrepareMdataASFHdr(DTS_LIB_CONTEXT *Ctx, DTS_INPUT_MDATA *mData, uint8_t* buf) { if(buf==NULL) return BC_STS_INSUFF_RES; buf[0]=0; buf[1] = 0; buf[2] = 01; buf[3] = 0xE0; buf[4] = 0x0; buf[5]=35; buf[6] =0x80; buf[7]=0; buf[8]= 0; buf[9]=0x5a;buf[10]=0x5a;buf[11]=0x5a;buf[12]=0x5a; buf[13]=0x0; buf[14]=0x0;buf[15]=0x0;buf[16]=0x20; buf[17]=0x0; buf[18]=0x0;buf[19]=0x0;buf[20]=0x9; buf[21]=0x5a; buf[22]=0x5a;buf[23]=0x5a;buf[24]=0x5a; buf[25]=0xBD; buf[26]=0x40; buf[27]=mData->Spes.SeqNum[0];buf[28]=mData->Spes.SeqNum[1]; buf[29]=mData->Spes.Command; buf[30]=buf[31]=buf[32]=buf[33]=buf[34]=buf[35]=buf[36]=buf[37]=buf[38]=buf[39]=buf[40]=0x0; return BC_STS_SUCCESS; } void DtsUpdateInStats(DTS_LIB_CONTEXT *Ctx, uint32_t size) { BC_DTS_STATS *pDtsStat = DtsGetgStats( ); pDtsStat->ipSampleCnt++; pDtsStat->ipTotalSize += size; pDtsStat->TxFifoBsyCnt = 0; // Ctx->InSampleCount ++; // if (Ctx->InSampleCount > 65530) // Ctx->InSampleCount = 1; return; } void DtsUpdateOutStats(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut) { uint32_t fr23_976 = 0; BOOL rptFrmCheck = TRUE; BC_DTS_STATS *pDtsStat = DtsGetgStats( ); if(pOut->PicInfo.flags & VDEC_FLAG_LAST_PICTURE) { pDtsStat->eosDetected = 1; } if(!Ctx->CapState){ /* Capture did not started yet..*/ memset(pDtsStat,0,sizeof(*pDtsStat)); if(pOut->PoutFlags & BC_POUT_FLAGS_FMT_CHANGE){ /* Get the frame rate from vdecResolution enums */ switch(pOut->PicInfo.frame_rate) { case vdecRESOLUTION_1080p23_976: fr23_976 = 1; break; case vdecRESOLUTION_1080i29_97: fr23_976 = 0; break; case vdecRESOLUTION_1080i25: fr23_976 = 0; break; //For Zero Frame Rate case vdecRESOLUTION_480p0: case vdecRESOLUTION_480i0: case vdecRESOLUTION_576p0: case vdecRESOLUTION_720p0: case vdecRESOLUTION_1080i0: case vdecRESOLUTION_1080p0: fr23_976 = 0; break; case vdecRESOLUTION_1080i: fr23_976 = 0; break; case vdecRESOLUTION_720p59_94: fr23_976 = 0; break; case vdecRESOLUTION_720p50: fr23_976 = 0; break; case vdecRESOLUTION_720p: fr23_976 = 0; break; case vdecRESOLUTION_720p23_976: fr23_976 = 1; break; case vdecRESOLUTION_CUSTOM ://no change in frame rate fr23_976 = Ctx->prevFrameRate; break; default: fr23_976 = 1; break; } /* Get the present frame rate */ Ctx->prevFrameRate = fr23_976; if( ((pOut->PicInfo.flags & VDEC_FLAG_FIELDPAIR) || (pOut->PicInfo.flags & VDEC_FLAG_INTERLACED_SRC)) && (!fr23_976)){ /* Interlaced.*/ Ctx->CapState = 1; }else{ /* Progressive */ Ctx->CapState = 2; } } return; } if((!pOut->UVBuffDoneSz && !pOut->b422Mode) || (!pOut->YBuffDoneSz)) { pDtsStat->opFrameDropped++; }else{ pDtsStat->opFrameCaptured++; } if(pOut->discCnt){ pDtsStat->opFrameDropped += pOut->discCnt; } #ifdef _ENABLE_CODE_INSTRUMENTATION_ /* * For code instrumentation to be enabled * we have to have unencripted PIBs. */ //if(!(Ctx->RegCfg.DbgOptions & BC_BIT(6))){ // /* New Scheme PIB is NOT available to DIL */ // return; //} #else if(!(Ctx->RegCfg.DbgOptions & BC_BIT(6))){ /* New Scheme PIB is NOT available to DIL */ return; } #endif /* PIB is not valid.. */ if(!(pOut->PoutFlags & BC_POUT_FLAGS_PIB_VALID)) { pDtsStat->pibMisses++; return; } /* detect Even Odd field consistancy for interlaced..*/ if(Ctx->CapState == 1){ if( !Ctx->PibIntToggle && !(pOut->PoutFlags & BC_POUT_FLAGS_FLD_BOT)) { // Previous ODD & Current Even --- OK Ctx->PibIntToggle = 1; } else if (Ctx->PibIntToggle && (pOut->PoutFlags & BC_POUT_FLAGS_FLD_BOT)){ //Previous Even and Current ODD --- OK rptFrmCheck = FALSE; Ctx->PibIntToggle = 0; } else if(!Ctx->PibIntToggle && (pOut->PoutFlags & BC_POUT_FLAGS_FLD_BOT)) { // Successive ODD if(!pOut->discCnt){ if(Ctx->prevPicNum == pOut->PicInfo.picture_number) { DebugLog_Trace(LDIL_DBG,"Succesive Odd=%d\n", pOut->PicInfo.picture_number); pDtsStat->reptdFrames++; rptFrmCheck = FALSE; } } } else if(Ctx->PibIntToggle && !(pOut->PoutFlags & BC_POUT_FLAGS_FLD_BOT)) { //Successive EVEN.. if(!pOut->discCnt){ if(Ctx->prevPicNum == pOut->PicInfo.picture_number) { DebugLog_Trace(LDIL_DBG,"Succesive Even=%d\n", pOut->PicInfo.picture_number); pDtsStat->reptdFrames++; rptFrmCheck = FALSE; } } } } if(!rptFrmCheck){ Ctx->prevPicNum = pOut->PicInfo.picture_number; return; } if(Ctx->prevPicNum == pOut->PicInfo.picture_number) { /* Picture Number repetetion..*/ DebugLog_Trace(LDIL_DBG,"Repetition=%d\n", pOut->PicInfo.picture_number); pDtsStat->reptdFrames++; } if(((Ctx->prevPicNum +1) != pOut->PicInfo.picture_number)&& !(pOut->discCnt) ){ /* Discontguous Picture Numbers Frames/PIBs got dropped..*/ pDtsStat->discCounter = pOut->PicInfo.picture_number - Ctx->prevPicNum ; } Ctx->prevPicNum = pOut->PicInfo.picture_number; return; } /********************************************************************************/ /* TX Circular Buffer routines */ // Init the circular buffer to be on 128 byte boundary BC_STATUS txBufInit(pTXBUFFER txBuf, uint32_t sizeInit) { BC_STATUS sts = BC_STS_SUCCESS; int ret = 0; if(txBuf->buffer != NULL) return BC_STS_INV_ARG; ret = posix_memalign((void**)&txBuf->buffer, 128, sizeInit); if(ret) return BC_STS_INSUFF_RES; if(txBuf->buffer != NULL) { txBuf->basePointer = txBuf->buffer; txBuf->endPointer = txBuf->basePointer + sizeInit - 1; txBuf->readPointer = txBuf->writePointer = 0; txBuf->freeSize = txBuf->totalSize = sizeInit; txBuf->busySize = 0; pthread_mutex_init(&txBuf->flushLock, NULL); pthread_mutex_init(&txBuf->pushpopLock, NULL); } else sts = BC_STS_INSUFF_RES; return sts; } // Push the number of bytes specified on to the circular buffer // This routine copies the data so that the orginial buffer can be released // Assume here that Flush of this buffer always happens from the same thread that does procinput // So don't lock pushing of new data against flush BC_STATUS txBufPush(pTXBUFFER txBuf, uint8_t* bufToPush, uint32_t sizeToPush) { uint32_t mcpySz = 0, sizeTop = 0; uint8_t* bufRemain = bufToPush; if(txBuf == NULL || bufToPush == NULL) return BC_STS_INV_ARG; if(txBuf->freeSize < sizeToPush) return BC_STS_INSUFF_RES; // How much will fit before we need to wrap sizeTop = (uint32_t)(txBuf->endPointer - (txBuf->basePointer + txBuf->writePointer) + 1); if(sizeToPush <= sizeTop) mcpySz = sizeToPush; else mcpySz = sizeTop; memcpy(txBuf->basePointer + txBuf->writePointer, bufToPush, mcpySz); txBuf->writePointer = (txBuf->writePointer + mcpySz) % txBuf->totalSize; pthread_mutex_lock(&txBuf->pushpopLock); txBuf->busySize += mcpySz; txBuf->freeSize -= mcpySz; pthread_mutex_unlock(&txBuf->pushpopLock); if((sizeToPush - mcpySz) != 0) { // Can only get here if we wrap at the top // writePointer should be 0 bufRemain += mcpySz; mcpySz = sizeToPush - mcpySz; sizeTop = txBuf->readPointer; memcpy(txBuf->basePointer, bufRemain, mcpySz); txBuf->writePointer = mcpySz; pthread_mutex_lock(&txBuf->pushpopLock); txBuf->busySize += mcpySz; txBuf->freeSize -= mcpySz; pthread_mutex_unlock(&txBuf->pushpopLock); } return BC_STS_SUCCESS; } // Pops data from the circular buffer // Returns the number of bytes popped // We have to do a copy since we require the HW buffer to be 128 byte aligned for Flea BC_STATUS txBufPop(pTXBUFFER txBuf, uint8_t* bufToPop, uint32_t sizeToPop) { uint32_t popSz = 0, sizeTop = 0; uint8_t* bufRemain = bufToPop; if(txBuf == NULL) return BC_STS_INV_ARG; pthread_mutex_lock(&txBuf->flushLock); if(sizeToPop > txBuf->busySize) return BC_STS_INV_ARG; sizeTop = (uint32_t)(txBuf->endPointer - (txBuf->basePointer + txBuf->readPointer) + 1); if(sizeToPop <= sizeTop) popSz = sizeToPop; else popSz = sizeTop; memcpy(bufToPop, txBuf->basePointer + txBuf->readPointer, popSz); txBuf->readPointer = (txBuf->readPointer + popSz) % txBuf->totalSize; pthread_mutex_lock(&txBuf->pushpopLock); txBuf->busySize -= popSz; txBuf->freeSize += popSz; pthread_mutex_unlock(&txBuf->pushpopLock); if((sizeToPop - popSz) != 0) { // Can only get here if we wrap at the top // readPointer should be 0 bufRemain += popSz; popSz = sizeToPop - popSz; sizeTop = txBuf->writePointer; memcpy(bufRemain, txBuf->basePointer, popSz); txBuf->readPointer = popSz; pthread_mutex_lock(&txBuf->pushpopLock); txBuf->busySize -= popSz; txBuf->freeSize += popSz; pthread_mutex_unlock(&txBuf->pushpopLock); } pthread_mutex_unlock(&txBuf->flushLock); return BC_STS_SUCCESS; } // Assume here that Flush of this buffer always happens from the same thread that does procinput // So don't lock pushing of new data against flush BC_STATUS txBufFlush(pTXBUFFER txBuf) { if(txBuf->buffer == NULL) return BC_STS_INV_ARG; pthread_mutex_lock(&txBuf->flushLock); txBuf->readPointer = txBuf->writePointer = 0; txBuf->freeSize = txBuf->totalSize; txBuf->busySize = 0; pthread_mutex_unlock(&txBuf->flushLock); return BC_STS_SUCCESS; } BC_STATUS txBufFree(pTXBUFFER txBuf) { if(txBuf->buffer == NULL) return BC_STS_INV_ARG; txBuf->basePointer = NULL; txBuf->endPointer = NULL; txBuf->readPointer = txBuf->writePointer = 0; txBuf->freeSize = 0; txBuf->busySize = 0; free(txBuf->buffer); pthread_mutex_destroy(&txBuf->flushLock); pthread_mutex_destroy(&txBuf->pushpopLock); return BC_STS_SUCCESS; } // TX Thread // This thread has dual purpose. First is to send TX data. Second is to detect if we have restarted from any suspend/hibernate action // and to restore the HW state void * txThreadProc(void *ctx) { DTS_LIB_CONTEXT* Ctx = (DTS_LIB_CONTEXT*)ctx; uint8_t* localBuffer; uint32_t szDataToSend; BC_STATUS sts; uint32_t dramOff; uint8_t encrypted = 0; HANDLE hDevice = (HANDLE)Ctx; BC_DTS_STATUS pStat; int ret = 0; uint32_t waitForPictCount = 0; uint32_t numPicCaptured = 0; ret = posix_memalign((void**)&localBuffer, 128, CIRC_TX_BUF_SIZE); if(ret) return FALSE; while(!Ctx->txThreadExit) { // First check the status of the HW // Get the real HW free size and also mark as we want TX information only pStat.cpbEmptySize = (0x3 << 31); sts = DtsGetDriverStatus(hDevice, &pStat); if(sts != BC_STS_SUCCESS) { pStat.cpbEmptySize = 0; DebugLog_Trace(LDIL_ERR,"txThreadProc: Got status %d from GetDriverStatus\n", sts); usleep(2 * 1000); continue; } //DebugLog_Trace(LDIL_ERR,"txThreadProc: Got hw size %u and data size %u\n", pStat.cpbEmptySize, Ctx->circBuf.busySize); if(pStat.PowerStateChange == BC_HW_SUSPEND) { // HW is in suspend mode, sleep 30 ms and then try again usleep(30 * 1000); continue; } // hack for indicating EOS when the HW does not signal one // We will check if the HW does not produce a picture for 1s and does not signal EOS either // This way exit maximum in 1s if(Ctx->bEOSCheck) { if(numPicCaptured == pStat.FramesCaptured) waitForPictCount++; if(waitForPictCount >= BC_EOS_PIC_COUNT) Ctx->bEOS = true; usleep(30 * 1000); } else waitForPictCount = 0; if(numPicCaptured != pStat.FramesCaptured) { waitForPictCount = 0; numPicCaptured = pStat.FramesCaptured; } if(pStat.PowerStateChange == BC_HW_RESUME) { DebugLog_Trace(LDIL_ERR,"Trying to resume from S3/S5\n"); // HW is up, but needs to be initialized DtsSetCoreClock(hDevice, 180); // For LINK sts = DtsSetupHardware(hDevice, true); if(sts != BC_STS_SUCCESS) { // At this point we are dead. Can't do much' DebugLog_Trace(LDIL_ERR,"Cannot Recover from S3/S5 RESUME SetupHardware failed %d\n", sts); usleep(1000 * 1000); continue; // Try again and pray for the best } Ctx->State = BC_DEC_STATE_CLOSE; // Because the HW was reset below us sts = DtsOpenDecoder(hDevice, 0); if(sts != BC_STS_SUCCESS) { // At this point we are dead. Can't do much' DebugLog_Trace(LDIL_ERR,"Cannot Recover from S3/S5 RESUME OpenDecoder failed %d\n", sts); usleep(1000 * 1000); continue; // Try again and pray for the best } sts = DtsStartDecoder(hDevice); if(sts != BC_STS_SUCCESS) { // At this point we are dead. Can't do much' DebugLog_Trace(LDIL_ERR,"Cannot Recover from S3/S5 RESUME StartDecoder failed %d\n", sts); usleep(1000 * 1000); continue; // Try again and pray for the best } sts = DtsStartCapture(hDevice); if(sts != BC_STS_SUCCESS) { // At this point we are dead. Can't do much' DebugLog_Trace(LDIL_ERR,"Cannot Recover from S3/S5 RESUME StartCapture failed %d\n", sts); usleep(1000 * 1000); continue; // Try again and pray for the best } // Force sending SPS/PPS previously stored DtsClrPendMdataList(Ctx); Ctx->LastPicNum = -1; Ctx->LastSessNum = -1; Ctx->EOSCnt = 0; Ctx->DrvStatusEOSCnt = 0; Ctx->bEOS = FALSE; Ctx->PESConvParams.m_lStartCodeDataSize = 0; Ctx->PESConvParams.m_bAddSpsPps = true; // Throw away any potential partial data, since we need a complete picture to start decoding txBufFlush(&Ctx->circBuf); // But in case we were already in the mode to be hunting for EOS // and did not send it to HW, resend it so the playback can end gracefully if(Ctx->bEOSCheck) DtsSendEOS(hDevice, 0); DebugLog_Trace(LDIL_ERR,"Resume from S3/S5 Done\n"); } // Check if we have data to send. if(Ctx->circBuf.busySize != 0) { if(pStat.cpbEmptySize == 0) { usleep(3000); continue; } if(Ctx->circBuf.busySize < pStat.cpbEmptySize) szDataToSend = Ctx->circBuf.busySize; else szDataToSend = pStat.cpbEmptySize; if(BC_STS_SUCCESS != txBufPop(&Ctx->circBuf, localBuffer, szDataToSend)) { usleep(5 * 1000); continue; } if(Ctx->VidParams.VideoAlgo == BC_VID_ALGO_VC1MP) encrypted |= 0x2; sts = DtsTxDmaText(hDevice, localBuffer, szDataToSend, &dramOff, encrypted); if(sts == BC_STS_SUCCESS) DtsUpdateInStats(Ctx, szDataToSend); else { // signal error to the next procinput DebugLog_Trace(LDIL_ERR,"txThreadProc: Got status %d from TxDmaText\n", sts); } } else usleep(5 * 1000); } free(localBuffer); localBuffer = NULL; return FALSE; } DRVIFLIB_INT_API BC_STATUS DtsGetHWFeatures(uint32_t *pciids) { int drvHandle = -1; BC_IOCTL_DATA pIo; int rc; memset(&pIo, 0, sizeof(BC_IOCTL_DATA)); drvHandle =open(CRYSTALHD_API_DEV_NAME, O_RDWR); if(drvHandle < 0) { DebugLog_Trace(LDIL_ERR,"DtsGetHWFeatures: Create File Failed\n"); return BC_STS_ERROR; } pIo.u.pciCfg.Offset = 0; pIo.u.pciCfg.Size = 4; rc = ioctl(drvHandle, BCM_IOC_RD_PCI_CFG, &pIo); if(rc < 0){ DebugLog_Trace(LDIL_ERR,"ioctl to get HW features failed\n"); close(drvHandle); return BC_STS_ERROR; } if(pIo.RetSts == BC_STS_SUCCESS) { *pciids = pIo.u.pciCfg.pci_cfg_space[0] | (pIo.u.pciCfg.pci_cfg_space[1] << 8) | (pIo.u.pciCfg.pci_cfg_space[2] << 16) | (pIo.u.pciCfg.pci_cfg_space[3] << 24); //*pciids = *(uint32_t*)pIo.u.pciCfg.pci_cfg_space; close(drvHandle); return BC_STS_SUCCESS; } else { DebugLog_Trace(LDIL_ERR, "error in getting pciids\n"); close(drvHandle); return BC_STS_ERROR; } } /*====================== Debug Routines ========================================*/ // // Test routine to verify mdata functions .. // void DtsTestMdata(DTS_LIB_CONTEXT *gCtx) { uint32_t i; BC_STATUS sts = BC_STS_SUCCESS; DTS_INPUT_MDATA *im = NULL; uint8_t *temp; uint32_t ulSize; //sts = DtsCreateMdataPool(gCtx); //if(sts != BC_STS_SUCCESS){ // DebugLog_Trace(LDIL_DBG,"PoolCreation Failed:%x\n",sts); // return; //} //DebugLog_Trace(LDIL_DBG,"PoolCreation done\n"); DebugLog_Trace(LDIL_DBG,"Inserting Elements for Sequential Fetch..\n"); //gCtx->InMdataTag = 0x11; //for(i=0x11; i < 0x21; i++){ //gCtx->InMdataTag = 0; for(i=0; i < 64; i++){ sts = DtsPrepareMdata(gCtx,i, &im, &temp, &ulSize); if(sts != BC_STS_SUCCESS){ DtsFreeMdata(gCtx,im,TRUE); DebugLog_Trace(LDIL_DBG,"DtsPrepareMdata Failed:%x\n",sts); return; } DtsInsertMdata(gCtx,im); } // DtsFetchMdata(gCtx,10,&gpout); #if 1 BC_DTS_PROC_OUT gpout; DebugLog_Trace(LDIL_DBG,"Fetch Begin\n"); //for(i=0x12; i < 0x22; i++){ for(i=1; i < 64; i++){ sts = DtsFetchMdata(gCtx,i,&gpout); if(sts != BC_STS_SUCCESS){ DebugLog_Trace(LDIL_DBG,"DtsFetchMdata Failed:%x SNum:%x \n",sts,i); //return; } } #endif // DebugLog_Trace(LDIL_DBG,"Deleting Pool...\n"); // DtsDeleteMdataPool(gCtx); } BOOL DtsDbgCheckPointers(DTS_LIB_CONTEXT *Ctx,BC_IOCTL_DATA *pIo) { uint32_t i; BOOL bRet = FALSE; DTS_MPOOL_TYPE *mp; if(!Ctx->Mpools || !(Ctx->CfgFlags & BC_MPOOL_INCL_YUV_BUFFS)){ return FALSE; } for(i=0; iMpoolCnt; i++){ mp = &Ctx->Mpools[i]; if(mp->type & BC_MEM_DEC_YUVBUFF){ if(mp->buff == pIo->u.DecOutData.OutPutBuffs.YuvBuff){ bRet = TRUE; break; } } } return bRet; } crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/libcrystalhd_priv.h0000644000175000017500000003345111610313111026101 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_priv.h * * Description: Driver Interface library Interanl. * * AU * * HISTORY: * ******************************************************************** * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #ifndef _BCM_DRV_IF_PRIV_ #define _BCM_DRV_IF_PRIV_ #include #include "bc_dts_glob_lnx.h" #include "libcrystalhd_parser.h" #ifdef __cplusplus extern "C" { #endif enum _bc_ldil_log_level{ LDIL_ERR = 0x80000000, /* Don't disable this option */ /* Following are allowed only in debug mode */ LDIL_INFO = 0x00000001, /* Generic informational */ LDIL_DBG = 0x00000002, /* First level Debug info */ }; #define LDIL_PRINTS_ON 1 #if LDIL_PRINTS_ON #define DebugLog_Trace(_tl, fmt, args...) printf(fmt, ##args); #else #define DebugLog_Trace(_tl, fmt, args...) #endif #define bc_sleep_ms(x) usleep(1000*x) /* Some of the globals from bc_dts_glob.h. are defined * here that are applicable only to ldil. */ enum _crystalhd_ldil_globals { BC_EOS_PIC_COUNT = 16, /* EOS check counter..*/ BC_INPUT_MDATA_POOL_SZ = 1024, /* Input Meta Data Pool size */ BC_INPUT_MDATA_POOL_SZ_COLLECT = 256, /* Input Meta Data Pool size for collector */ BC_MAX_SW_VOUT_BUFFS = BC_RX_LIST_CNT, /* MAX - pre allocated buffers..*/ RX_START_DELIVERY_THRESHOLD = 0, PAUSE_DECODER_THRESHOLD = 12, RESUME_DECODER_THRESHOLD = 5, FLEA_RT_PD_THRESHOLD = 14, FLEA_RT_PU_THRESHOLD = 3, HARDWARE_INIT_RETRY_CNT = 10, HARDWARE_INIT_RETRY_LINK_CNT = 1, }; enum _DtsRunState { BC_DEC_STATE_CLOSE = 0x00, BC_DEC_STATE_STOP = 0x01, BC_DEC_STATE_START = 0x02, BC_DEC_STATE_PAUSE = 0x03, BC_DEC_STATE_FLUSH = 0x04 }; /* Bit fields */ enum _BCMemTypeFlags { BC_MEM_DEC_YUVBUFF = 0x1, BC_MEM_USER_MODE_ALLOC = 0x80000000, }; enum _STCapParams{ NO_PARAM = 0, ST_CAP_IMMIDIATE = 0x01, }; /* Application specific run-time configurations */ enum _DtsAppSpecificCfgFlags { BC_MPOOL_FLAGS_DEF = 0x000, BC_MPOOL_INCL_YUV_BUFFS = 0x001, /* Include YUV Buffs allocation */ BC_DEC_EN_DUART = 0x002, /* Enable DUART for FW log */ BC_DEC_INIT_MEM = 0x004, /* Initialize Entire DRAM takes about a min */ BC_DEC_VCLK_74MHZ = 0x008, /* Enable Vidoe clock to 75 MHZ */ BC_EN_DIAG_MODE = 0x010, /* Enable Diag Mode application */ BC_PIX_WID_1080 = 0x020, /* FIX_ME: deprecate this after PIB work */ BC_ADDBUFF_MOVE = 0x040, /* FIX_ME: Deleteme after testing.. */ BC_DEC_VCLK_77MHZ = 0x080 /* Enable Vidoe clock to 77 MHZ */ }; #define BC_DTS_DEF_CFG (BC_MPOOL_INCL_YUV_BUFFS | BC_EN_DIAG_MODE | BC_DEC_VCLK_74MHZ | BC_ADDBUFF_MOVE) /* !!!!Note!!!! * Don't forget to change this value * while changing the file names */ #define BC_MAX_FW_FNAME_SIZE 32 #define MAX_PATH 256 #define FWBINFILE_70012 "bcm70012fw.bin" #define FWBINFILE_70015 "bcm70015fw.bin" #define BC_DTS_DEF_OPTIONS 0x0D #define BC_DTS_DEF_OPTIONS_LINK 0xB0000005 #define BC_FW_CMD_TIMEOUT 2 //Use the Last Un-Fetched One #define MAX_DISORDER_GAP 5 #define ALIGN_BUF_SIZE (512*1024) #define CIRC_TX_BUF_SIZE (1024*1024) #define BC_EOS_DETECTED 0xffffffff typedef struct _DTS_MPOOL_TYPE { uint32_t type; uint32_t sz; uint8_t *buff; } DTS_MPOOL_TYPE; #define LIB_CTX_SIG 0x11223344 typedef struct _DTS_VIDEO_PARAMS { uint32_t VideoAlgo; uint32_t WidthInPixels; uint32_t HeightInPixels; BOOL FGTEnable; BOOL MetaDataEnable; BOOL Progressive; uint32_t FrameRate; uint32_t OptFlags; //currently has the DEc_operation_mode in bits 4 and 5, bits 0:3 have the default framerate, Ignore frame rate is bit 6. Bit 7 is SingleThreadedAppMode BC_MEDIA_SUBTYPE MediaSubType; uint32_t StartCodeSz; uint8_t *pMetaData; uint32_t MetaDataSz; uint32_t NumOfRefFrames; uint32_t LevelIDC; uint32_t StreamType; } DTS_VIDEO_PARAMS; /* Input MetaData handling.. */ typedef struct _BC_SEQ_HDR_FORMAT{ uint8_t StartCode[4]; uint8_t PacketLen; uint8_t StartCodeEnd; uint8_t SeqNum[2]; uint8_t Command; uint8_t PicLength[2]; uint8_t Reserved; }BC_SEQ_HDR_FORMAT; typedef struct _BC_PES_HDR_FORMAT{ uint8_t StartCode[4]; uint8_t PacketLen[2]; uint8_t OptPesHdr[2]; uint8_t optPesHdrLen; }BC_PES_HDR_FORMAT; typedef struct _DTS_INPUT_MDATA{ struct _DTS_INPUT_MDATA *flink; struct _DTS_INPUT_MDATA *blink; uint32_t IntTag; uint32_t Reserved; uint64_t appTimeStamp; BC_SEQ_HDR_FORMAT Spes; }DTS_INPUT_MDATA; #define DTS_MDATA_PEND_LINK(_c) ( (DTS_INPUT_MDATA *)&_c->MDPendHead ) #define DTS_MDATA_TAG_MASK (0x00010000) #define DTS_MDATA_MAX_TAG (0x0000FFFF) typedef struct _TXBUFFER{ uint32_t readPointer; // Index into the buffer for next read uint32_t writePointer; // Index into the buffer for next write uint32_t freeSize; uint32_t totalSize; uint32_t busySize; uint8_t *basePointer; // First byte that can be written uint8_t *endPointer; // Last byte that can be written uint8_t *buffer; pthread_mutex_t flushLock; // LOCK used only for flushing pthread_mutex_t pushpopLock; // LOCK for push and pop operations }TXBUFFER, *pTXBUFFER; BC_STATUS txBufPush(pTXBUFFER txBuf, uint8_t* bufToPush, uint32_t sizeToPush); BC_STATUS txBufPop(pTXBUFFER txBuf, uint8_t* bufToPop, uint32_t sizeToPop); BC_STATUS txBufFlush(pTXBUFFER txBuf); BC_STATUS txBufInit(pTXBUFFER txBuf, uint32_t sizeInit); BC_STATUS txBufFree(pTXBUFFER txBuf); // TX Thread function void * txThreadProc(void *ctx); typedef struct _DTS_LIB_CONTEXT{ uint32_t Sig; /* Mazic number */ uint32_t State; /* DIL's Run State */ int DevHandle; /* Driver handle */ BC_IOCTL_DATA *pIoDataFreeHd; /* IOCTL data pool head */ DTS_MPOOL_TYPE *Mpools; /* List of memory pools created */ uint32_t MpoolCnt; /* Number of entries */ uint32_t CfgFlags; /* Application specifi flags */ uint32_t OpMode; /* Mode of operation playback etc..*/ uint32_t DevId; /* HW Device ID */ uint32_t hwRevId; /* HW revision ID */ uint32_t VendorId; /* HW vendor ID - should always be Broadcom 0x14e4 */ uint32_t fwcmdseq; /* FW Cmd Sequence number */ uint32_t FixFlags; /* Flags for conditionally enabling fixes */ pthread_mutex_t thLock; DTS_VIDEO_PARAMS VidParams; /* App specific Video Params */ DecRspChannelStreamOpen OpenRsp;/* Channel Open Response */ DecRspChannelStartVideo sVidRsp;/* Start Video Response */ /* Proc Output Related */ BOOL ProcOutPending; /* To avoid muliple ProcOuts */ BOOL CancelWaiting; /* Notify FetchOut to signal */ /* pOutData is dedicated for ProcOut() use only. Every other * Interface should use the memory from IocData pool. This * is to provide priority for ProcOut() interface due to its * performance criticality. * * !!!!!NOTE!!!! * * Using this data structures for other interfaces, will cause * thread related race conditions. */ BC_IOCTL_DATA *pOutData; /* Current Active Proc Out Buffer */ /* Place Holder for FW file paths */ char StreamFile[MAX_PATH+1]; char VidInner[MAX_PATH+1]; char VidOuter[MAX_PATH+1]; uint32_t InMdataTag; /* InMetaData Tag for TimeStamp */ void *MdataPoolPtr; /* allocated memory PoolPointer */ struct _DTS_INPUT_MDATA *MDFreeHead; /* MetaData Free List Head */ struct _DTS_INPUT_MDATA *MDPendHead; /* MetaData Pending List Head */ struct _DTS_INPUT_MDATA *MDPendTail; /* MetaData Pending List Tail */ //Reserve the Last Fetch Tag uint32_t MDLastFetchTag; /* End Of Stream detection */ BOOL bEOSCheck; /* Flag to start EOS detection */ uint32_t EOSCnt; /* Last picture repetition count */ uint32_t DrvStatusEOSCnt; uint32_t LastPicNum; /* Last picture number */ uint32_t LastSessNum; /* Last session number */ uint8_t PullDownFlag; BOOL bEOS; /* Statistics Related */ uint32_t prevPicNum; /* Previous received frame */ uint32_t CapState; /* 0 = Not started, 1 = Interlaced, 2 = progressive */ uint32_t PibIntToggle; /* Toggle flag to detect PIB miss in Interlaced mode.*/ uint32_t prevFrameRate; /* Previous frame rate */ BC_REG_CONFIG RegCfg; /* Registry Configurable options.*/ char FwBinFile[MAX_PATH+1]; /* Firmware Bin file place holder */ BC_OUTPUT_FORMAT b422Mode; /* 422 Mode Identifier for Link */ uint32_t HWOutPicWidth; uint32_t HWOutPicHeight; char DilPath[MAX_PATH+1]; /* DIL runtime Location.. */ uint8_t SingleThreadedAppMode; /* flag to indicate that we are running in single threaded mode */ bool hw_paused; bool fw_cmd_issued; PES_CONVERT_PARAMS PESConvParams; BC_HW_CAPS capInfo; // uint16_t InSampleCount; uint8_t bMapOutBufDone; BC_PIC_INFO_BLOCK FormatInfo; TXBUFFER circBuf; bool txThreadExit; // Handle to event to indicate to the tx thread to exit pthread_t htxThread; // Handle to TX thread uint8_t *alignBuf; uint32_t EnableScaling; uint8_t bEnable720pDropHalf; pid_t ProcessID; uint32_t nRefNum; uint32_t DrvMode; }DTS_LIB_CONTEXT; /* Helper macro to get lib context from user handle */ #define DTS_GET_CTX(_uh, _c) \ { \ if( !(_c = DtsGetContext(_uh)) ){ \ return BC_STS_INV_ARG; \ } \ } extern DTS_LIB_CONTEXT * DtsGetContext(HANDLE userHnd); BOOL DtsIsPend(DTS_LIB_CONTEXT *Ctx); BOOL DtsDrvIoctl ( HANDLE hDevice, DWORD dwIoControlCode, LPVOID lpInBuffer, DWORD nInBufferSize, LPVOID lpOutBuffer, DWORD nOutBufferSize, LPDWORD lpBytesReturned, BOOL Async ); BC_STATUS DtsDrvCmd(DTS_LIB_CONTEXT *Ctx, DWORD Code, BOOL Async, BC_IOCTL_DATA *pIoData, BOOL Rel); void DtsRelIoctlData(DTS_LIB_CONTEXT *Ctx, BC_IOCTL_DATA *pIoData); BC_IOCTL_DATA *DtsAllocIoctlData(DTS_LIB_CONTEXT *Ctx); BC_STATUS DtsAllocMemPools(DTS_LIB_CONTEXT *Ctx); void DtsReleaseMemPools(DTS_LIB_CONTEXT *Ctx); BC_STATUS DtsAddOutBuff(DTS_LIB_CONTEXT *Ctx, PVOID buff, uint32_t BuffSz, uint32_t flags); BC_STATUS DtsRelRxBuff(DTS_LIB_CONTEXT *Ctx, BC_DEC_YUV_BUFFS *buff,BOOL SkipAddBuff); BC_STATUS DtsFetchOutInterruptible(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *DecOut, uint32_t dwTimeout); BC_STATUS DtsCancelFetchOutInt(DTS_LIB_CONTEXT *Ctx); BC_STATUS DtsMapYUVBuffs(DTS_LIB_CONTEXT *Ctx); BC_STATUS DtsInitInterface(int hDevice,HANDLE *RetCtx, uint32_t mode); BC_STATUS DtsSetupConfig(DTS_LIB_CONTEXT *Ctx, uint32_t did, uint32_t rid, uint32_t FixFlags); BC_STATUS DtsReleaseInterface(DTS_LIB_CONTEXT *Ctx); BC_STATUS DtsGetBCRegConfig(DTS_LIB_CONTEXT *Ctx); BC_STATUS DtsGetFirmwareFiles(DTS_LIB_CONTEXT *Ctx); DTS_INPUT_MDATA *DtsAllocMdata(DTS_LIB_CONTEXT *Ctx); BC_STATUS DtsFreeMdata(DTS_LIB_CONTEXT *Ctx, DTS_INPUT_MDATA *Mdata, BOOL sync); BC_STATUS DtsClrPendMdataList(DTS_LIB_CONTEXT *Ctx); BC_STATUS DtsInsertMdata(DTS_LIB_CONTEXT *Ctx, DTS_INPUT_MDATA *Mdata); BC_STATUS DtsRemoveMdata(DTS_LIB_CONTEXT *Ctx, DTS_INPUT_MDATA *Mdata, BOOL sync); BC_STATUS DtsFetchMdata(DTS_LIB_CONTEXT *Ctx, uint16_t snum, BC_DTS_PROC_OUT *pout); BC_STATUS DtsFetchTimeStampMdata(DTS_LIB_CONTEXT *Ctx, uint16_t snum, uint64_t *TimeStamp); BC_STATUS DtsPrepareMdataASFHdr(DTS_LIB_CONTEXT *Ctx, DTS_INPUT_MDATA *mData, uint8_t* buf); BC_STATUS DtsPrepareMdata(DTS_LIB_CONTEXT *Ctx, uint64_t timeStamp, DTS_INPUT_MDATA **mData, uint8_t** pDataBuf, uint32_t *pSize); BC_STATUS DtsNotifyOperatingMode(HANDLE hDevice, uint32_t Mode); BC_STATUS DtsReleaseUserHandle(DTS_LIB_CONTEXT *Ctx); BC_STATUS DtsGetHWFeatures(uint32_t *pciids); BC_STATUS DtsSetupHardware(HANDLE hDevice, BOOL IgnClkChk); /* Internal helper function */ uint32_t DtsGetWidthfromResolution(DTS_LIB_CONTEXT *Ctx, uint32_t Resolution); /*====================== Performance Counter Routines ============================*/ void DtsUpdateInStats(DTS_LIB_CONTEXT *Ctx, uint32_t size); void DtsUpdateOutStats(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut); /*============== Global shared area usage ======================*/ #define BC_DIL_HWINIT_NOT_YET 0 #define BC_DIL_HWINIT_IN_PROGRESS 1 #define BC_DIL_HWINIT_DONE 2 #define BC_DIL_SHMEM_KEY 0xBABEFACE typedef struct _bc_dil_glob_s{ uint32_t gDilOpMode; uint32_t gHwInitSts; BC_DTS_STATS stats; pid_t g_nProcID; bool g_bDecOpened; uint32_t DevID; } bc_dil_glob_s; BC_STATUS DtsGetDilShMem(uint32_t shmid); BC_STATUS DtsDelDilShMem(void); BC_STATUS DtsCreateShMem(int *shmem_id); /* DTS Global Parameters Utility functions */ uint32_t DtsGetOPMode(void); void DtsSetOPMode(uint32_t value); uint32_t DtsGetHwInitSts(void); void DtsSetHwInitSts(uint32_t value); void DtsRstStats(void); BC_DTS_STATS * DtsGetgStats (void); uint32_t DtsGetgDevID(void); void DtsSetgDevID(uint32_t DevID); BC_STATUS DtsGetDevType(uint32_t *pDevID, uint32_t *pVendID, uint32_t *pRevID); uint32_t DtsGetDevID(); bool DtsIsDecOpened(pid_t nNewPID); void DtsSetDecStat(bool bDecOpen, pid_t PID); bool DtsChkPID(pid_t nCurPID); void DtsLock(DTS_LIB_CONTEXT *Ctx); void DtsUnLock(DTS_LIB_CONTEXT *Ctx); /*====================== Debug Routines ========================================*/ void DtsTestMdata(DTS_LIB_CONTEXT *gCtx); BOOL DtsDbgCheckPointers(DTS_LIB_CONTEXT *Ctx,BC_IOCTL_DATA *pIo); BOOL DtsCheckRptPic(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut); BC_STATUS DtsUpdateVidParams(DTS_LIB_CONTEXT *Ctx, BC_DTS_PROC_OUT *pOut); #ifdef __cplusplus } #endif #endif crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/Makefile0000644000175000017500000000425511610313111023644 0ustar andresandres# # Broadcom "BCM970012/BCM970015" Crystal HD device interface library. # # BCLIB_MINOR=6 BCLIB_MAJOR=3 BCLIB_NAME=libcrystalhd.so BCLIB_SL=$(BCLIB_NAME).$(BCLIB_MAJOR) BCLIB=$(BCLIB_NAME).$(BCLIB_MAJOR).$(BCLIB_MINOR) LIBDIR=/usr/lib AT = @ ECHO = ${AT} echo BCGCC = g++ ROOTDIR = ../.. INCLUDES = -I./ -I/usr/include -I$(ROOTDIR)/include INCLUDES += -I$(ROOTDIR)/include/link CPPFLAGS = -D__LINUX_USER__ # -DLDIL_PRINTS_ON # -D_USE_SHMEM_ CPPFLAGS += ${INCLUDES} CPPFLAGS += -O2 -Wall -fPIC -shared -fstrict-aliasing -msse2 LDFLAGS = -Wl,-soname,${BCLIB_SL} -pthread SRCFILES = libcrystalhd_if.cpp \ libcrystalhd_int_if.cpp \ libcrystalhd_fwcmds.cpp \ libcrystalhd_priv.cpp \ libcrystalhd_fwdiag_if.cpp \ libcrystalhd_fwload_if.cpp \ libcrystalhd_parser.cpp OBJFILES = ${SRCFILES:.cpp=.o} all:help $(OBJFILES) $(BCGCC) $(CPPFLAGS) $(LDFLAGS) -o $(BCLIB) ${OBJFILES} ln -sf $(BCLIB) $(BCLIB_NAME) ln -sf $(BCLIB) $(BCLIB_SL) help: ${ECHO} OBJFILES = ${OBJFILES} ${ECHO} SRCFILES = ${SRCFILES} ${ECHO} LNM = ${BCLIB} ${BCLIB_SL} clean: rm -f ${BCLIB} ${BCLIB_SL} ${BCLIB_NAME} *.o rm -f ${OBJFILES} install: mkdir -p $(DESTDIR)$(LIBDIR) mkdir -p $(DESTDIR)/lib/firmware mkdir -p $(DESTDIR)/usr/include/libcrystalhd cp libcrystalhd_if.h $(DESTDIR)/usr/include/libcrystalhd/ chmod 0644 $(DESTDIR)/usr/include/libcrystalhd/libcrystalhd_if.h cp $(ROOTDIR)/include/bc_dts_defs.h $(DESTDIR)/usr/include/libcrystalhd/ chmod 0644 $(DESTDIR)/usr/include/libcrystalhd/bc_dts_defs.h cp $(ROOTDIR)/include/bc_dts_types.h $(DESTDIR)/usr/include/libcrystalhd/ chmod 0644 $(DESTDIR)/usr/include/libcrystalhd/bc_dts_types.h cp $(ROOTDIR)/include/libcrystalhd_version.h $(DESTDIR)/usr/include/libcrystalhd/ chmod 0644 $(DESTDIR)/usr/include/libcrystalhd/libcrystalhd_version.h cp $(ROOTDIR)/firmware/fwbin/70012/bcm70012fw.bin $(DESTDIR)/lib/firmware/ chmod 0644 $(DESTDIR)/lib/firmware/bcm70012fw.bin cp $(ROOTDIR)/firmware/fwbin/70015/bcm70015fw.bin $(DESTDIR)/lib/firmware/ chmod 0644 $(DESTDIR)/lib/firmware/bcm70015fw.bin install -m 755 $(BCLIB) $(DESTDIR)$(LIBDIR) (cd $(DESTDIR)$(LIBDIR); ln -sf $(BCLIB) $(BCLIB_NAME)) (cd $(DESTDIR)$(LIBDIR); ln -sf $(BCLIB) $(BCLIB_SL)) crystalhd-0.0~git20110715.fdd2f19/linux_lib/libcrystalhd/libcrystalhd_fwdiag_if.h0000644000175000017500000000531411610313111027035 0ustar andresandres/******************************************************************** * Copyright(c) 2006-2009 Broadcom Corporation. * * Name: libcrystalhd_fwdiag_if.h * * Description: Driver Interface library Internal. * * AU * * HISTORY: * ******************************************************************** * * This file is part of libcrystalhd. * * This library is free software: you can redistribute it and/or modify * it under the terms of the GNU Lesser General Public License as published * by the Free Software Foundation, either version 2.1 of the License. * * This library is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU Lesser General Public License for more details. * You should have received a copy of the GNU Lesser General Public License * along with this library. If not, see . * *******************************************************************/ #ifndef _libcrystalhd_FWDIAG_IF_ #define _libcrystalhd_FWDIAG_IF_ #define BC_HOST_CMD_ADDR 0x00000100 /* Host-Bootloader Communication Message Block */ typedef struct _BC_HOST_CMD_BLOCK_ST { uint32_t done; uint32_t cmd; uint32_t start; uint32_t size; uint32_t cmdargs[3]; uint32_t chk_sum; } BC_HOST_CMD_BLOCK_ST, *PBC_HOST_CMD_BLOCK_ST; #define BC_FWDIAG_DONE 0x00000001 /* Bootloader Status */ typedef enum _BC_FWDIAG_STATUS{ BC_FWDIAG_STS_SUCCESS = 0, BC_FWDIAG_BOOTUP_DONE = 1, BC_FWDIAG_TEST_PASS = 2, BC_FWDIAG_TEST_FAIL = 3, BC_FWDIAG_TEST_NOT_IMPL = 4, BC_FWDIAG_INVALID_ARGS = 5, /* Must be the last one.*/ BC_FWDIAG_STS_ERROR = -1 }BC_FWDIAG_STATUS; #define BC_FWDIAG_RES_ADDR 0x00000140 /* Bootloader-Host Communication Message Block */ typedef struct _BC_FWDIAG_RES_BLOCK_ST { uint32_t done; uint32_t status; uint32_t detail[5]; uint32_t chk_sum; }BC_FWDIAG_RES_BLOCK_ST, *PBC_FWDIAG_RES_BLOCK_ST; #define BC_HOST_CMD_POSTED 0x00000001 #define BC_FWDIAG_RES_POSTED 0x00000001 #define BC_FWDIAG_PATTERN_ADDR 0x00000200 /* Bootloader Status */ typedef enum _BC_FWDIAG_CMDS{ BC_FWDIAG_SHORT_MEM_TEST = 0x1, BC_FWDIAG_LONG_MEM_TEST = 0x2, BC_FWDIAG_MEM_READ_TEST = 0x3, BC_FWDIAG_MEM_WRITE_TEST = 0x4, BC_FWDIAG_DMA_READ_TEST = 0x8, BC_FWDIAG_DMA_WRITE_TEST = 0xC, }BC_FWDIAG_CMDS; DRVIFLIB_INT_API BC_STATUS DtsDownloadFWDIAGToLINK(HANDLE hDevice, char *FwBinFile); DRVIFLIB_INT_API BC_STATUS DtsSendFWDiagCmd(HANDLE hDevice, BC_HOST_CMD_BLOCK_ST hostMsg); DRVIFLIB_INT_API BC_STATUS DtsReceiveFWDiagRes(HANDLE hDevice, PBC_FWDIAG_RES_BLOCK_ST pBlMsg, uint32_t wait); DRVIFLIB_INT_API BC_STATUS DtsClearFWDiagCommBlock(HANDLE hDevice); #endif crystalhd-0.0~git20110715.fdd2f19/export-driver-for-staging.sh0000755000175000017500000000206411610313111023116 0ustar andresandres#!/bin/bash # # Crude script to export kernel driver bits to a kernel git tree, # under drivers/staging/crystalhd/ # You still need to edit drivers/staging/{Kconfig,Makefile} by hand # if [ -z "$1" ]; then echo "You need to specify a path to a kernel tree" exit 1 fi kernelsrc=$1 dest=$kernelsrc/drivers/staging/crystalhd me=$PWD if [ ! -e $dest ]; then mkdir $dest fi # Copy files into place in kernel git tree cp -a $me/driver/linux/*.c $dest/ cp -a $me/driver/linux/*.h $dest/ # copy userspace headers cp -a $me/include/bc_dts_defs.h $dest/ cp -a $me/include/bc_dts_glob_lnx.h $dest/ # copy register defines for bcm70012 bcm70015 cp -a $me/include/link/bcm_70012_regs.h $dest/ cp -a $me/include/flea/bcm_70015_regs.h $dest/ # copy random header cp -a $me/include/flea/DriverFwShare.h $dest/ # Now run unifdef over the source to strip out legacy compat pushd $dest perl -pi -e 's|KERNEL_VERSION.*|1|g' *.c *.h for f in *.c *.h do cp $f tmp-$f unifdef -DLINUX_VERSION_CODE=2 tmp-$f > $f rm -f tmp-$f done # Now show diff and diffstat git diff -p --stat crystalhd-0.0~git20110715.fdd2f19/driver/0000755000175000017500000000000011610313111017020 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/driver/linux/0000755000175000017500000000000011610313122020161 5ustar andresandrescrystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_misc.c0000644000175000017500000005545011610313111023344 0ustar andresandres/*************************************************************************** * Copyright (c) 2005-2009, Broadcom Corporation. * * Name: crystalhd_misc . c * * Description: * BCM70012 Linux driver misc routines. * * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ #include #include #include "crystalhd_lnx.h" #include "crystalhd_misc.h" /* Some HW specific code defines */ extern uint32_t link_GetRptDropParam(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, void *); extern uint32_t flea_GetRptDropParam(struct crystalhd_hw *hw, void *); static struct crystalhd_dio_req *crystalhd_alloc_dio(struct crystalhd_adp *adp) { unsigned long flags = 0; struct crystalhd_dio_req *temp = NULL; if (!adp) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return temp; } spin_lock_irqsave(&adp->lock, flags); temp = adp->ua_map_free_head; if (temp) adp->ua_map_free_head = adp->ua_map_free_head->next; spin_unlock_irqrestore(&adp->lock, flags); return temp; } static void crystalhd_free_dio(struct crystalhd_adp *adp, struct crystalhd_dio_req *dio) { unsigned long flags = 0; if (!adp || !dio) return; spin_lock_irqsave(&adp->lock, flags); dio->sig = crystalhd_dio_inv; dio->page_cnt = 0; dio->fb_size = 0; memset(&dio->uinfo, 0, sizeof(dio->uinfo)); dio->next = adp->ua_map_free_head; adp->ua_map_free_head = dio; spin_unlock_irqrestore(&adp->lock, flags); } static struct crystalhd_elem *crystalhd_alloc_elem(struct crystalhd_adp *adp) { unsigned long flags = 0; struct crystalhd_elem *temp = NULL; if (!adp) { printk(KERN_ERR "%s: Invalid args\n", __func__); return temp; } spin_lock_irqsave(&adp->lock, flags); temp = adp->elem_pool_head; if (temp) { adp->elem_pool_head = adp->elem_pool_head->flink; memset(temp, 0, sizeof(*temp)); } spin_unlock_irqrestore(&adp->lock, flags); return temp; } static void crystalhd_free_elem(struct crystalhd_adp *adp, struct crystalhd_elem *elem) { unsigned long flags = 0; if (!adp || !elem) return; spin_lock_irqsave(&adp->lock, flags); elem->flink = adp->elem_pool_head; adp->elem_pool_head = elem; spin_unlock_irqrestore(&adp->lock, flags); } static inline void crystalhd_set_sg(struct scatterlist *sg, struct page *page, unsigned int len, unsigned int offset) { #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 23) sg_set_page(sg, page, len, offset); #else sg->page = page; sg->offset = offset; sg->length = len; #endif #ifdef CONFIG_X86_64 sg->dma_length = len; #endif } static inline void crystalhd_init_sg(struct scatterlist *sg, unsigned int entries) { /* http://lkml.org/lkml/2007/11/27/68 */ #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 23) sg_init_table(sg, entries); #endif } /*========================== Extern ========================================*/ /** * crystalhd_pci_cfg_rd - PCIe config read * @adp: Adapter instance * @off: PCI config space offset. * @len: Size -- Byte, Word & dword. * @val: Value read * * Return: * Status. * * Get value from PCIe config space. */ BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *adp, uint32_t off, uint32_t len, uint32_t *val) { BC_STATUS sts = BC_STS_SUCCESS; int rc = 0; if (!adp || !val) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } switch (len) { case 1: rc = pci_read_config_byte(adp->pdev, off, (u8 *)val); break; case 2: rc = pci_read_config_word(adp->pdev, off, (u16 *)val); break; case 4: rc = pci_read_config_dword(adp->pdev, off, (u32 *)val); break; default: rc = -EINVAL; sts = BC_STS_INV_ARG; dev_err(&adp->pdev->dev, "Invalid len:%d\n", len); }; if (rc && (sts == BC_STS_SUCCESS)) sts = BC_STS_ERROR; return sts; } /** * crystalhd_pci_cfg_wr - PCIe config write * @adp: Adapter instance * @off: PCI config space offset. * @len: Size -- Byte, Word & dword. * @val: Value to be written * * Return: * Status. * * Set value to Link's PCIe config space. */ BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *adp, uint32_t off, uint32_t len, uint32_t val) { BC_STATUS sts = BC_STS_SUCCESS; int rc = 0; if (!adp || !val) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } switch (len) { case 1: rc = pci_write_config_byte(adp->pdev, off, (u8)val); break; case 2: rc = pci_write_config_word(adp->pdev, off, (u16)val); break; case 4: rc = pci_write_config_dword(adp->pdev, off, val); break; default: rc = -EINVAL; sts = BC_STS_INV_ARG; dev_err(&adp->pdev->dev, "Invalid len:%d\n", len); }; if (rc && (sts == BC_STS_SUCCESS)) sts = BC_STS_ERROR; return sts; } /** * bc_kern_dma_alloc - Allocate memory for Dma rings * @adp: Adapter instance * @sz: Size of the memory to allocate. * @phy_addr: Physical address of the memory allocated. * Typedef to system's dma_addr_t (u64) * * Return: * Pointer to allocated memory.. * * Wrapper to Linux kernel interface. * */ void *bc_kern_dma_alloc(struct crystalhd_adp *adp, uint32_t sz, dma_addr_t *phy_addr) { void *temp = NULL; if (!adp || !sz || !phy_addr) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return temp; } temp = pci_alloc_consistent(adp->pdev, sz, phy_addr); if (temp) memset(temp, 0, sz); return temp; } /** * bc_kern_dma_free - Release Dma ring memory. * @adp: Adapter instance * @sz: Size of the memory to allocate. * @ka: Kernel virtual address returned during _dio_alloc() * @phy_addr: Physical address of the memory allocated. * Typedef to system's dma_addr_t (u64) * * Return: * none. */ void bc_kern_dma_free(struct crystalhd_adp *adp, uint32_t sz, void *ka, dma_addr_t phy_addr) { if (!adp || !ka || !sz || !phy_addr) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return; } pci_free_consistent(adp->pdev, sz, ka, phy_addr); } /** * crystalhd_create_dioq - Create Generic DIO queue * @adp: Adapter instance * @dioq_hnd: Handle to the dio queue created * @cb : Optional - Call back To free the element. * @cbctx: Context to pass to callback. * * Return: * status * * Initialize Generic DIO queue to hold any data. Callback * will be used to free elements while deleting the queue. */ BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *adp, struct crystalhd_dioq **dioq_hnd, crystalhd_data_free_cb cb, void *cbctx) { struct crystalhd_dioq *dioq = NULL; if (!adp || !dioq_hnd) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } dioq = kzalloc(sizeof(*dioq), GFP_KERNEL); if (!dioq) return BC_STS_INSUFF_RES; spin_lock_init(&dioq->lock); dioq->sig = BC_LINK_DIOQ_SIG; dioq->head = (struct crystalhd_elem *)&dioq->head; dioq->tail = (struct crystalhd_elem *)&dioq->head; crystalhd_create_event(&dioq->event); dioq->adp = adp; dioq->data_rel_cb = cb; dioq->cb_context = cbctx; *dioq_hnd = dioq; return BC_STS_SUCCESS; } /** * crystalhd_delete_dioq - Delete Generic DIO queue * @adp: Adapter instance * @dioq: DIOQ instance.. * * Return: * None. * * Release Generic DIO queue. This function will remove * all the entries from the Queue and will release data * by calling the call back provided during creation. * */ void crystalhd_delete_dioq(struct crystalhd_adp *adp, struct crystalhd_dioq *dioq) { void *temp; if (!dioq || (dioq->sig != BC_LINK_DIOQ_SIG)) return; do { temp = crystalhd_dioq_fetch(dioq); if (temp && dioq->data_rel_cb) dioq->data_rel_cb(dioq->cb_context, temp); } while (temp); dioq->sig = 0; kfree(dioq); } /** * crystalhd_dioq_add - Add new DIO request element. * @ioq: DIO queue instance * @t: DIO request to be added. * @wake: True - Wake up suspended process. * @tag: Special tag to assign - For search and get. * * Return: * Status. * * Insert new element to Q tail. */ BC_STATUS crystalhd_dioq_add(struct crystalhd_dioq *ioq, void *data, bool wake, uint32_t tag) { unsigned long flags = 0; struct crystalhd_elem *tmp; if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG) || !data) { dev_err(chddev(), "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } tmp = crystalhd_alloc_elem(ioq->adp); if (!tmp) { dev_err(chddev(), "%s: No free elements.\n", __func__); return BC_STS_INSUFF_RES; } tmp->data = data; tmp->tag = tag; spin_lock_irqsave(&ioq->lock, flags); tmp->flink = (struct crystalhd_elem *)&ioq->head; tmp->blink = ioq->tail; tmp->flink->blink = tmp; tmp->blink->flink = tmp; ioq->count++; spin_unlock_irqrestore(&ioq->lock, flags); if (wake) crystalhd_set_event(&ioq->event); return BC_STS_SUCCESS; } /** * crystalhd_dioq_fetch - Fetch element from head. * @ioq: DIO queue instance * * Return: * data element from the head.. * * Remove an element from Queue. */ void *crystalhd_dioq_fetch(struct crystalhd_dioq *ioq) { unsigned long flags = 0; struct crystalhd_elem *tmp; struct crystalhd_elem *ret = NULL; void *data = NULL; if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG)) { dev_err(chddev(), "%s: Invalid arg\n", __func__); if(!ioq) dev_err(chddev(), "ioq not initialized\n"); else dev_err(chddev(), "ioq invalid signature\n"); return data; } spin_lock_irqsave(&ioq->lock, flags); tmp = ioq->head; if (tmp != (struct crystalhd_elem *)&ioq->head) { ret = tmp; tmp->flink->blink = tmp->blink; tmp->blink->flink = tmp->flink; ioq->count--; } spin_unlock_irqrestore(&ioq->lock, flags); if (ret) { data = ret->data; crystalhd_free_elem(ioq->adp, ret); } return data; } /** * crystalhd_dioq_find_and_fetch - Search the tag and Fetch element * @ioq: DIO queue instance * @tag: Tag to search for. * * Return: * element from the head.. * * Search TAG and remove the element. */ void *crystalhd_dioq_find_and_fetch(struct crystalhd_dioq *ioq, uint32_t tag) { unsigned long flags = 0; struct crystalhd_elem *tmp; struct crystalhd_elem *ret = NULL; void *data = NULL; if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG)) { dev_err(chddev(), "%s: Invalid arg\n", __func__); return data; } spin_lock_irqsave(&ioq->lock, flags); tmp = ioq->head; while (tmp != (struct crystalhd_elem *)&ioq->head) { if (tmp->tag == tag) { ret = tmp; tmp->flink->blink = tmp->blink; tmp->blink->flink = tmp->flink; ioq->count--; break; } tmp = tmp->flink; } spin_unlock_irqrestore(&ioq->lock, flags); if (ret) { data = ret->data; crystalhd_free_elem(ioq->adp, ret); } return data; } /** * crystalhd_dioq_fetch_wait - Fetch element from Head. * @ioq: DIO queue instance * @to_secs: Wait timeout in seconds.. * * Return: * element from the head.. * * Return element from head if Q is not empty. Wait for new element * if Q is empty for Timeout seconds. */ void *crystalhd_dioq_fetch_wait(struct crystalhd_hw *hw, uint32_t to_secs, uint32_t *sig_pend) { struct device *dev = chddev(); unsigned long flags = 0; int rc = 0; struct crystalhd_rx_dma_pkt *r_pkt = NULL; struct crystalhd_dioq *ioq = hw->rx_rdyq; uint32_t picYcomp = 0; unsigned long fetchTimeout = jiffies + msecs_to_jiffies(to_secs * 1000); if (!ioq || (ioq->sig != BC_LINK_DIOQ_SIG) || !to_secs || !sig_pend) { dev_err(dev, "%s: Invalid arg\n", __func__); return r_pkt; } spin_lock_irqsave(&ioq->lock, flags); while (!time_after_eq(jiffies, fetchTimeout)) { if(ioq->count == 0) { spin_unlock_irqrestore(&ioq->lock, flags); crystalhd_wait_on_event(&ioq->event, (ioq->count > 0), 250, rc, false); } else spin_unlock_irqrestore(&ioq->lock, flags); if (rc == 0) { /* Found a packet. Check if it is a repeated picture or not */ /* Drop the picture if it is a repeated picture */ /* Lock against checks from get status calls */ if(down_interruptible(&hw->fetch_sem)) goto sem_error; r_pkt = crystalhd_dioq_fetch(ioq); /* If format change packet, then return with out checking anything */ if (r_pkt->flags & (COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE)) goto sem_rel_return; if (hw->adp->pdev->device == BC_PCI_DEVID_LINK) { picYcomp = link_GetRptDropParam(hw, hw->PICHeight, hw->PICWidth, (void *)r_pkt); } else { /* For Flea, we don't have the width and height handy since they */ /* come in the PIB in the picture, so this function will also */ /* populate the width and height */ picYcomp = flea_GetRptDropParam(hw, (void *)r_pkt); /* For flea it is the above function that indicated format change */ if(r_pkt->flags & (COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE)) goto sem_rel_return; } if(!picYcomp || (picYcomp == hw->LastPicNo) || (picYcomp == hw->LastTwoPicNo)) { /*Discard picture */ if(picYcomp != 0) { hw->LastTwoPicNo = hw->LastPicNo; hw->LastPicNo = picYcomp; } crystalhd_dioq_add(hw->rx_freeq, r_pkt, false, r_pkt->pkt_tag); r_pkt = NULL; up(&hw->fetch_sem); } else { if(hw->adp->pdev->device == BC_PCI_DEVID_LINK) { if((picYcomp - hw->LastPicNo) > 1) { dev_info(dev, "MISSING %u PICTURES\n", (picYcomp - hw->LastPicNo)); } } hw->LastTwoPicNo = hw->LastPicNo; hw->LastPicNo = picYcomp; goto sem_rel_return; } } else if (rc == -EINTR) { *sig_pend = 1; return r_pkt; } spin_lock_irqsave(&ioq->lock, flags); } dev_info(dev, "FETCH TIMEOUT\n"); spin_unlock_irqrestore(&ioq->lock, flags); return r_pkt; sem_error: return NULL; sem_rel_return: up(&hw->fetch_sem); return r_pkt; } /** * crystalhd_map_dio - Map user address for DMA * @adp: Adapter instance * @ubuff: User buffer to map. * @ubuff_sz: User buffer size. * @uv_offset: UV buffer offset. * @en_422mode: TRUE:422 FALSE:420 Capture mode. * @dir_tx: TRUE for Tx (To device from host) * @dio_hnd: Handle to mapped DIO request. * * Return: * Status. * * This routine maps user address and lock pages for DMA. * */ BC_STATUS crystalhd_map_dio(struct crystalhd_adp *adp, void *ubuff, uint32_t ubuff_sz, uint32_t uv_offset, bool en_422mode, bool dir_tx, struct crystalhd_dio_req **dio_hnd) { struct device *dev; struct crystalhd_dio_req *dio; uint32_t start = 0, end = 0, count = 0; uint32_t spsz = 0; unsigned long uaddr = 0, uv_start = 0; int i = 0, rw = 0, res = 0, nr_pages = 0, skip_fb_sg = 0; if (!adp || !ubuff || !ubuff_sz || !dio_hnd) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } dev = &adp->pdev->dev; /* Compute pages */ uaddr = (unsigned long)ubuff; count = ubuff_sz; end = (uaddr + count + PAGE_SIZE - 1) >> PAGE_SHIFT; start = uaddr >> PAGE_SHIFT; nr_pages = end - start; if (!count || ((uaddr + count) < uaddr)) { dev_err(dev, "User addr overflow!!\n"); return BC_STS_INV_ARG; } dio = crystalhd_alloc_dio(adp); if (!dio) { dev_err(dev, "dio pool empty..\n"); return BC_STS_INSUFF_RES; } if (dir_tx) { rw = WRITE; dio->direction = DMA_TO_DEVICE; } else { rw = READ; dio->direction = DMA_FROM_DEVICE; } if (nr_pages > dio->max_pages) { dev_err(dev, "max_pages(%d) exceeded(%d)!!\n", dio->max_pages, nr_pages); crystalhd_unmap_dio(adp, dio); return BC_STS_INSUFF_RES; } if (uv_offset) { uv_start = (uaddr + uv_offset) >> PAGE_SHIFT; dio->uinfo.uv_sg_ix = uv_start - start; dio->uinfo.uv_sg_off = ((uaddr + uv_offset) & ~PAGE_MASK); } dio->fb_size = ubuff_sz & 0x03; if (dio->fb_size) { res = copy_from_user(dio->fb_va, (void *)(uaddr + count - dio->fb_size), dio->fb_size); if (res) { dev_err(dev, "failed %d to copy %u fill bytes from %p\n", res, dio->fb_size, (void *)(uaddr + count-dio->fb_size)); crystalhd_unmap_dio(adp, dio); return BC_STS_INSUFF_RES; } } down_read(¤t->mm->mmap_sem); res = get_user_pages(current, current->mm, uaddr, nr_pages, rw == READ, 0, dio->pages, NULL); up_read(¤t->mm->mmap_sem); /* Save for release..*/ dio->sig = crystalhd_dio_locked; if (res < nr_pages) { dev_err(dev, "get pages failed: %d-%d\n", nr_pages, res); dio->page_cnt = res; crystalhd_unmap_dio(adp, dio); return BC_STS_ERROR; } dio->page_cnt = nr_pages; /* Get scatter/gather */ crystalhd_init_sg(dio->sg, dio->page_cnt); crystalhd_set_sg(&dio->sg[0], dio->pages[0], 0, uaddr & ~PAGE_MASK); if (nr_pages > 1) { dio->sg[0].length = PAGE_SIZE - dio->sg[0].offset; #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 23) #ifdef CONFIG_X86_64 dio->sg[0].dma_length = dio->sg[0].length; #endif #endif count -= dio->sg[0].length; for (i = 1; i < nr_pages; i++) { if (count < 4) { spsz = count; skip_fb_sg = 1; } else { spsz = (count < PAGE_SIZE) ? (count & ~0x03) : PAGE_SIZE; } crystalhd_set_sg(&dio->sg[i], dio->pages[i], spsz, 0); count -= spsz; } } else { if (count < 4) { dio->sg[0].length = count; skip_fb_sg = 1; } else { dio->sg[0].length = count - dio->fb_size; } #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 23) #ifdef CONFIG_X86_64 dio->sg[0].dma_length = dio->sg[0].length; #endif #endif } dio->sg_cnt = pci_map_sg(adp->pdev, dio->sg, dio->page_cnt, dio->direction); if (dio->sg_cnt <= 0) { dev_err(dev, "sg map %d-%d\n", dio->sg_cnt, dio->page_cnt); crystalhd_unmap_dio(adp, dio); return BC_STS_ERROR; } if (dio->sg_cnt && skip_fb_sg) dio->sg_cnt -= 1; dio->sig = crystalhd_dio_sg_mapped; /* Fill in User info.. */ dio->uinfo.xfr_len = ubuff_sz; dio->uinfo.xfr_buff = ubuff; dio->uinfo.uv_offset = uv_offset; dio->uinfo.b422mode = en_422mode; dio->uinfo.dir_tx = dir_tx; *dio_hnd = dio; return BC_STS_SUCCESS; } /** * crystalhd_unmap_sgl - Release mapped resources * @adp: Adapter instance * @dio: DIO request instance * * Return: * Status. * * This routine is to unmap the user buffer pages. */ BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *adp, struct crystalhd_dio_req *dio) { struct page *page = NULL; int j = 0; if (!adp || !dio) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } if ((dio->page_cnt > 0) && (dio->sig != crystalhd_dio_inv)) { for (j = 0; j < dio->page_cnt; j++) { page = dio->pages[j]; if (page) { if (!PageReserved(page) && (dio->direction == DMA_FROM_DEVICE)) SetPageDirty(page); page_cache_release(page); } } } if (dio->sig == crystalhd_dio_sg_mapped) pci_unmap_sg(adp->pdev, dio->sg, dio->page_cnt, dio->direction); crystalhd_free_dio(adp, dio); return BC_STS_SUCCESS; } /** * crystalhd_create_dio_pool - Allocate mem pool for DIO management. * @adp: Adapter instance * @max_pages: Max pages for size calculation. * * Return: * system error. * * This routine creates a memory pool to hold dio context for * for HW Direct IO operation. */ int crystalhd_create_dio_pool(struct crystalhd_adp *adp, uint32_t max_pages) { struct device *dev; uint32_t asz = 0, i = 0; uint8_t *temp; struct crystalhd_dio_req *dio; if (!adp || !max_pages) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return -EINVAL; } dev = &adp->pdev->dev; /* Get dma memory for fill byte handling..*/ adp->fill_byte_pool = pci_pool_create("crystalhd_fbyte", adp->pdev, 8, 8, 0); if (!adp->fill_byte_pool) { dev_err(dev, "failed to create fill byte pool\n"); return -ENOMEM; } /* Get the max size from user based on 420/422 modes */ asz = (sizeof(*dio->pages) * max_pages) + (sizeof(*dio->sg) * max_pages) + sizeof(*dio); dev_dbg(dev, "Initializing Dio pool %d %d %x %p\n", BC_LINK_SG_POOL_SZ, max_pages, asz, adp->fill_byte_pool); for (i = 0; i < BC_LINK_SG_POOL_SZ; i++) { temp = kzalloc(asz, GFP_KERNEL); if ((temp) == NULL) { dev_err(dev, "Failed to alloc %d mem\n", asz); return -ENOMEM; } dio = (struct crystalhd_dio_req *)temp; temp += sizeof(*dio); dio->pages = (struct page **)temp; temp += (sizeof(*dio->pages) * max_pages); dio->sg = (struct scatterlist *)temp; dio->max_pages = max_pages; dio->fb_va = pci_pool_alloc(adp->fill_byte_pool, GFP_KERNEL, &dio->fb_pa); if (!dio->fb_va) { dev_err(dev, "fill byte alloc failed.\n"); return -ENOMEM; } crystalhd_free_dio(adp, dio); } return 0; } /** * crystalhd_destroy_dio_pool - Release DIO mem pool. * @adp: Adapter instance * * Return: * none. * * This routine releases dio memory pool during close. */ void crystalhd_destroy_dio_pool(struct crystalhd_adp *adp) { struct crystalhd_dio_req *dio; int count = 0; if (!adp) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return; } do { dio = crystalhd_alloc_dio(adp); if (dio) { if (dio->fb_va) pci_pool_free(adp->fill_byte_pool, dio->fb_va, dio->fb_pa); count++; kfree(dio); } } while (dio); if (adp->fill_byte_pool) { pci_pool_destroy(adp->fill_byte_pool); adp->fill_byte_pool = NULL; } dev_dbg(&adp->pdev->dev, "Released dio pool %d\n", count); } /** * crystalhd_create_elem_pool - List element pool creation. * @adp: Adapter instance * @pool_size: Number of elements in the pool. * * Return: * 0 - success, <0 error * * Create general purpose list element pool to hold pending, * and active requests. */ int crystalhd_create_elem_pool(struct crystalhd_adp *adp, uint32_t pool_size) { uint32_t i; struct crystalhd_elem *temp; if (!adp || !pool_size) return -EINVAL; for (i = 0; i < pool_size; i++) { temp = kzalloc(sizeof(*temp), GFP_KERNEL); if (!temp) { dev_err(&adp->pdev->dev, "kzalloc failed\n"); return -ENOMEM; } crystalhd_free_elem(adp, temp); } dev_dbg(&adp->pdev->dev, "allocated %d elem\n", pool_size); return 0; } /** * crystalhd_delete_elem_pool - List element pool deletion. * @adp: Adapter instance * * Return: * none * * Delete general purpose list element pool. */ void crystalhd_delete_elem_pool(struct crystalhd_adp *adp) { struct crystalhd_elem *temp; int dbg_cnt = 0; if (!adp) return; do { temp = crystalhd_alloc_elem(adp); if (temp) { kfree(temp); dbg_cnt++; } } while (temp); dev_dbg(&adp->pdev->dev, "released %d elem\n", dbg_cnt); } /*================ Debug support routines.. ================================*/ void crystalhd_show_buffer(uint32_t off, uint8_t *buff, uint32_t dwcount) { struct device *dev = chddev(); uint32_t i, k = 1; for (i = 0; i < dwcount; i++) { if (k == 1) dev_dbg(dev, "0x%08X : ", off); dev_dbg(dev, " 0x%08X ", *((uint32_t *)buff)); buff += sizeof(uint32_t); off += sizeof(uint32_t); k++; if ((i == dwcount - 1) || (k > 4)) { dev_dbg(dev, "\n"); k = 1; } } } crystalhd-0.0~git20110715.fdd2f19/driver/linux/20-crystalhd.rules0000644000175000017500000000004111610313111023442 0ustar andresandresKERNEL=="crystalhd", MODE="0666" crystalhd-0.0~git20110715.fdd2f19/driver/linux/bcm_70012_dev.sh0000644000175000017500000000235611610313111022651 0ustar andresandres#!/bin/bash # # Author: Prasad Bolisetty # # Script to load broadcom 70012 module and create device node. # # bcm_dev_bin="bcm70012" bcm_dev_name="crystalhd" bcm_node="/dev/crystalhd" if ! whoami | grep root > /dev/null ; then echo " Login as root and try.." exit 1; fi bcm_pci_id=`lspci -d 14e4:1612` if [ $? -ne 0 -o -z "$bcm_pci_id" ]; then echo "BCM 70012 not installed.." exit 1; fi if lsmod | grep $bcm_dev_bin > /dev/null ; then echo "Stopping Broadcom MediaPC 70012 Module" rmmod $bcm_dev_bin >& /dev/null if [ $? -ne 0 ]; then echo "Failed to stop: Close applications and try again. " exit 1; fi fi bcm_major=`cat /proc/devices | grep "$bcm_dev_name" | cut -c1-3` if [ -z "$bcm_major" ]; then modinfo $bcm_dev_bin >& /dev/null if [ $? -ne 0 ]; then echo "Broadcom MediaPC 70012 Kernel Module not installed" exit 1; fi modprobe $bcm_dev_bin >& /dev/null bcm_major=`cat /proc/devices | grep "$bcm_dev_name" | cut -c1-3` if [ $? -ne 0 -o -z "$bcm_major" ]; then echo "Error($bcm_major): Loading Broadcom MediaPC 70012 Module" rmmod $bcm_dev_bin >& /dev/null exit 1; fi fi if [ -c $bcm_node ]; then rm -f $bcm_node >& /dev/null fi mknod -m 666 $bcm_node c $bcm_major 0 echo "Broadcom MediaPC 70012 Module loaded" crystalhd-0.0~git20110715.fdd2f19/driver/linux/FleaDefs.h0000644000175000017500000001460511610313111022007 0ustar andresandres#ifndef _FLEA_DEFS_ #define _FLEA_DEFS_ /* * Include a whole bunch of RDB files for register definitions */ #include "bcm_70015_regs.h" /* Assume we have 64MB DRam */ #define FLEA_TOTAL_DRAM_SIZE 64*1024*1024 #define FLEA_GISB_DIRECT_BASE 0x50 /*- These definition of the ADDRESS and DATA - Registers are not there in RDB. */ #define FLEA_GISB_INDIRECT_ADDRESS 0xFFF8 #define FLEA_GISB_INDIRECT_DATA 0xFFFC /* * POLL count for Flea. */ #define FLEA_MAX_POLL_CNT 1000 /* -- Flea Firmware Signature length (128 bit) */ #define FLEA_FW_SIG_LEN_IN_BYTES 16 #define LENGTH_FIELD_SIZE 4 #define FLEA_FW_SIG_LEN_IN_DWORD (FLEA_FW_SIG_LEN_IN_BYTES/4) #define FW_DOWNLOAD_START_ADDR 0 /* * Some macros to ease the bit specification from RDB */ #define SCRAM_KEY_DONE_INT_BIT BC_BIT(BCHP_WRAP_MISC_INTR2_CPU_STATUS_SCRM_KEY_DONE_INTR_SHIFT) #define BOOT_VER_DONE_BIT BC_BIT(BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_DONE_INTR_SHIFT) #define BOOT_VER_FAIL_BIT BC_BIT(BCHP_WRAP_MISC_INTR2_CPU_STATUS_BOOT_VER_FAIL_INTR_SHIFT) #define SHARF_ERR_INTR BC_BIT(BCHP_WRAP_MISC_INTR2_CPU_STATUS_SHARF_ERR_INTR_SHIFT) #define SCRUB_ENABLE_BIT BC_BIT(BCHP_SCRUB_CTRL_SCRUB_ENABLE_SCRUB_EN_SHIFT) #define DRAM_SCRAM_ENABLE_BIT BC_BIT(BCHP_SCRUB_CTRL_SCRUB_ENABLE_DSCRAM_EN_SHIFT) #define ARM_RUN_REQ_BIT BC_BIT(BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL_arm_run_request_SHIFT) #define GetScrubEndAddr(_Sz) ((FW_DOWNLOAD_START_ADDR + (_Sz - FLEA_FW_SIG_LEN_IN_BYTES -LENGTH_FIELD_SIZE-1))& (BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_BORCH_END_ADDR_MASK)) /* -- Firmware Command Interface Definitions. -- We use BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI1 as host to FW mailbox. -- We use BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1 as FW to Host mailbox. */ /* Address where the command parameters are written. */ #define DDRADDR_4_FWCMDS 0x100 /* */ /* mailbox used for passing the FW Command address (DDR address) to */ /* firmware. */ /* */ #define FW_CMD_POST_MBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1 /* Once we get a firmware command done interrupt, */ /* we will need to get the address of the response. */ /* This mailbox is written by FW before asserting the */ /* firmware command done interrupt. */ #define FW_CMD_RES_MBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI1 /* -- RxDMA Picture QStatus Mailbox. -- RxDMA Picture Post Mailbox. < Write DDR address to this mailbox > */ #define RX_DMA_PIC_QSTS_MBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_PCI2 #define RX_POST_MAILBOX BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM2 #define RX_POST_CONFIRM_SCRATCH BCHP_ARMCR4_BRIDGE_REG_SCRATCH_5 #define RX_START_SEQ_NUMBER 1 #define INDICATE_TX_DONE_REG BCHP_ARMCR4_BRIDGE_REG_SCRATCH_9 /* -- At the end of the picture frame there is the Link's Y0 data -- and there is Width data. The driver will copy this 32 bit data to Y[0] -- location. This makes the Flea PIB compatible with Link. -- Also note that Flea is capable of putting out the odd size picture widths -- so the PicWidth field is the actual picture width of the picture. In link -- We were only getting 1920,1280 or 720 as picture widths. */ #define PIC_PIB_DATA_OFFSET_FROM_END 4 #define PIC_PIB_DATA_SIZE_IN_BYTES 4 /*The data that use to be in Y[0] component */ #define PIC_WIDTH_OFFSET_FROM_END 8 /*Width information for the driver. */ #define PIC_WIDTH_DATA_SIZE_IN_BYTES 4 /*Width information for the driver. */ /* -- The format change PIB comes in a dummy frame now. -- The Width field has the format change flag (bit-31) which -- the driver uses to detect the format change now. */ #define PIB_FORMAT_CHANGE_BIT BC_BIT(31) #define PIB_EOS_DETECTED_BIT BC_BIT(30) #define FLEA_DECODE_ERROR_FLAG 0x800 /* -- Interrupt Mask, Set and Clear registers are exactly -- same as the interrupt status register. We will -- Use the following union for all the registers. */ union FLEA_INTR_BITS_COMMON { struct { uint32_t L0TxDMADone:1; /* Bit-0 */ uint32_t L0TxDMAErr:1; /* Bit-1 */ uint32_t L0YRxDMADone:1; /* Bit-2 */ uint32_t L0YRxDMAErr:1; /* Bit-3 */ uint32_t L0UVRxDMADone:1; /* Bit-4 */ uint32_t L0UVRxDMAErr:1; /* Bit-5 */ uint32_t Reserved1:2; /* Bit-6-7 */ uint32_t L1TxDMADone:1; /* Bit-8 */ uint32_t L1TxDMAErr:1; /* Bit-9 */ uint32_t L1YRxDMADone:1; /* Bit-10 */ uint32_t L1YRxDMAErr:1; /* Bit-11 */ uint32_t L1UVRxDMADone:1; /* Bit-12 */ uint32_t L1UVRxDMAErr:1; /* Bit-13 */ uint32_t Reserved2:2; /* Bit-14-15 */ uint32_t ArmMbox0Int:1; /* Bit-16 */ uint32_t ArmMbox1Int:1; /* Bit-17 */ uint32_t ArmMbox2Int:1; /* Bit-18 */ uint32_t ArmMbox3Int:1; /* Bit-19 */ uint32_t Reserved3:4; /* Bit-20-23 */ uint32_t PcieTgtUrAttn:1; /* Bit-24 */ uint32_t PcieTgtCaAttn:1; /* Bit-25 */ uint32_t HaltIntr:1; /* Bit-26 */ uint32_t Reserved4:5; /* Bit-27-31 */ }; uint32_t WholeReg; }; /* ================================================================ -- Flea power state machine -- FLEA_PS_NONE -- Enter to this state when system boots up and device is not open. -- FLEA_PS_ACTIVE: -- 1. Set when the device is started and FW downloaded. -- 2. We come to this state from FLEA_PS_LP_COMPLETE when -- 2.a Free list length becomes greater than X. [Same As Internal Pause Sequence] -- 2.b There is a firmware command issued. -- 3. We come to this state from FLEA_PS_LP_PENDING when -- 3.a Free list length becomes greater than X. [Same As Internal Pause Sequence] -- 3.b There is a firmware command Issued. -- FLEA_PS_LP_PENDING -- 1. Enter to this state from FLEA_PS_ACTIVE -- 1.a FLL becomes greater less than Y[Same as Internal Resume]. -- FLEA_PS_LP_COMPLETE -- 1. Enter in to this state from FLEA_PS_LP_PENDING -- 1.a There are no Pending TX, RX, and FW Command. -- 2. Enter to This state when the handle is closed. -- 3. Enter to this state From ACTIVE -- 3.a FLL < Y. -- 3.b There is no TX,RX and FW pending. -- 4. Enter this state when RX is not running, either before it is started or after it is stopped. ================================================================= */ enum FLEA_POWER_STATES { FLEA_PS_NONE=0, FLEA_PS_STOPPED, FLEA_PS_ACTIVE, FLEA_PS_LP_PENDING, FLEA_PS_LP_COMPLETE }; enum FLEA_STATE_CH_EVENT { FLEA_EVT_NONE=0, FLEA_EVT_START_DEVICE, FLEA_EVT_STOP_DEVICE, FLEA_EVT_FLL_CHANGE, FLEA_EVT_FW_CMD_POST, FLEA_EVT_CMD_COMP }; #define TEST_BIT(_value_,_bit_number_) (_value_ & (0x00000001 << _bit_number_)) #define CLEAR_BIT(_value_,_bit_number_)\ {_value_ = _value_ & (~(0x00000001 << _bit_number_));} #define SET_BIT(_value_,_bit_number_)\ {_value_ |= (0x01 << _bit_number_);} #endif crystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_cmds.h0000644000175000017500000000551211610313111023336 0ustar andresandres/*************************************************************************** * Copyright (c) 2005-2009, Broadcom Corporation. * * Name: crystalhd_cmds . h * * Description: * BCM70010 Linux driver user command interfaces. * * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ #ifndef _CRYSTALHD_CMDS_H_ #define _CRYSTALHD_CMDS_H_ /* * NOTE:: This is the main interface file between the Linux layer * and the harware layer. This file will use the definitions * from _dts_glob and dts_defs etc.. which are defined for * windows. */ #include "crystalhd_hw.h" #include "crystalhd_misc.h" extern struct device * chddev(void); enum _crystalhd_state{ BC_LINK_INVALID = 0x00, BC_LINK_INIT = 0x01, BC_LINK_CAP_EN = 0x02, BC_LINK_FMT_CHG = 0x04, BC_LINK_SUSPEND = 0x10, BC_LINK_PAUSED = 0x20, BC_LINK_RESUME = 0x40, BC_LINK_READY = (BC_LINK_INIT | BC_LINK_CAP_EN | BC_LINK_FMT_CHG), }; struct crystalhd_user { uint32_t uid; uint32_t in_use; uint32_t mode; }; #define DTS_MODE_INV (-1) struct crystalhd_cmd { uint32_t state; struct crystalhd_adp *adp; struct crystalhd_user user[BC_LINK_MAX_OPENS]; spinlock_t ctx_lock; uint32_t tx_list_id; uint32_t cin_wait_exit; uint32_t pwr_state_change; /* 0 is running, 1 is going to suspend, 2 is going to resume */ struct crystalhd_hw *hw_ctx; }; typedef BC_STATUS (*crystalhd_cmd_proc)(struct crystalhd_cmd *, crystalhd_ioctl_data *); struct crystalhd_cmd_tbl { uint32_t cmd_id; const crystalhd_cmd_proc cmd_proc; uint32_t block_mon; }; BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata); BC_STATUS crystalhd_resume(struct crystalhd_cmd *ctx); crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, uint32_t cmd, struct crystalhd_user *uc); BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, struct crystalhd_user **user_ctx); BC_STATUS crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, struct crystalhd_adp *adp); BC_STATUS crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx); bool crystalhd_cmd_interrupt(struct crystalhd_cmd *ctx); #endif crystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_hw.c0000644000175000017500000007320411610313111023024 0ustar andresandres/*************************************************************************** * Copyright (c) 2005-2009, Broadcom Corporation. * * Name: crystalhd_hw . c * * Description: * BCM70012/BCM70015 Linux driver hardware layer. * * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ #include #include #include #include #include #include "crystalhd_lnx.h" #include "crystalhd_linkfuncs.h" #include "crystalhd_fleafuncs.h" #define OFFSETOF(_s_, _m_) ((size_t)(unsigned long)&(((_s_ *)0)->_m_)) BC_STATUS crystalhd_hw_open(struct crystalhd_hw *hw, struct crystalhd_adp *adp) { struct device *dev; if (!hw || !adp) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } if (hw->dev_started) return BC_STS_SUCCESS; dev = &adp->pdev->dev; hw->PauseThreshold = BC_RX_LIST_CNT - 2; hw->DefaultPauseThreshold = BC_RX_LIST_CNT - 2; hw->ResumeThreshold = 3; /* Setup HW specific functions appropriately */ if (adp->pdev->device == BC_PCI_DEVID_FLEA) { dev_dbg(dev, "crystalhd_hw_open: setting up functions, device = Flea\n"); hw->pfnStartDevice = crystalhd_flea_start_device; hw->pfnStopDevice = crystalhd_flea_stop_device; hw->pfnFindAndClearIntr = crystalhd_flea_hw_interrupt_handle; hw->pfnReadDevRegister = crystalhd_flea_reg_rd; /* Done */ hw->pfnWriteDevRegister = crystalhd_flea_reg_wr; /* Done */ hw->pfnReadFPGARegister = crystalhd_flea_reg_rd; /* Done */ hw->pfnWriteFPGARegister = crystalhd_flea_reg_wr; /* Done */ hw->pfnCheckInputFIFO = crystalhd_flea_check_input_full; hw->pfnDevDRAMRead = crystalhd_flea_mem_rd; /* Done */ hw->pfnDevDRAMWrite = crystalhd_flea_mem_wr; /* Done */ hw->pfnDoFirmwareCmd = crystalhd_flea_do_fw_cmd; hw->pfnFWDwnld = crystalhd_flea_download_fw; hw->pfnHWGetDoneSize = crystalhd_flea_get_dnsz; hw->pfnIssuePause = crystalhd_flea_hw_pause; hw->pfnPeekNextDeodedFr = crystalhd_flea_peek_next_decoded_frame; hw->pfnPostRxSideBuff = crystalhd_flea_hw_post_cap_buff; hw->pfnStartTxDMA = crystalhd_flea_start_tx_dma_engine; hw->pfnStopTxDMA = crystalhd_flea_stop_tx_dma_engine; hw->pfnStopRXDMAEngines = crystalhd_flea_stop_rx_dma_engine; hw->pfnNotifyFLLChange = crystalhd_flea_notify_fll_change; hw->pfnNotifyHardware = crystalhd_flea_notify_event; } else { dev_dbg(dev, "crystalhd_hw_open: setting up functions, device = Link\n"); hw->pfnStartDevice = crystalhd_link_start_device; hw->pfnStopDevice = crystalhd_link_stop_device; hw->pfnFindAndClearIntr = crystalhd_link_hw_interrupt_handle; hw->pfnReadDevRegister = link_dec_reg_rd; hw->pfnWriteDevRegister = link_dec_reg_wr; hw->pfnReadFPGARegister = crystalhd_link_reg_rd; hw->pfnWriteFPGARegister = crystalhd_link_reg_wr; hw->pfnCheckInputFIFO = crystalhd_link_check_input_full; hw->pfnDevDRAMRead = crystalhd_link_mem_rd; hw->pfnDevDRAMWrite = crystalhd_link_mem_wr; hw->pfnDoFirmwareCmd = crystalhd_link_do_fw_cmd; hw->pfnFWDwnld = crystalhd_link_download_fw; hw->pfnHWGetDoneSize = crystalhd_link_get_dnsz; hw->pfnIssuePause = crystalhd_link_hw_pause; hw->pfnPeekNextDeodedFr = crystalhd_link_peek_next_decoded_frame; hw->pfnPostRxSideBuff = crystalhd_link_hw_post_cap_buff; hw->pfnStartTxDMA = crystalhd_link_start_tx_dma_engine; hw->pfnStopTxDMA = crystalhd_link_stop_tx_dma_engine; hw->pfnStopRXDMAEngines = crystalhd_link_stop_rx_dma_engine; hw->pfnNotifyFLLChange = crystalhd_link_notify_fll_change; hw->pfnNotifyHardware = crystalhd_link_notify_event; } hw->adp = adp; spin_lock_init(&hw->lock); spin_lock_init(&hw->rx_lock); sema_init(&hw->fetch_sem, 1); /* Seed for error checking and debugging. Random numbers */ hw->tx_ioq_tag_seed = 0x70023070; hw->rx_pkt_tag_seed = 0x70029070; hw->stop_pending = 0; hw->pfnStartDevice(hw); hw->dev_started = true; dev_dbg(dev, "Opening HW. hw:0x%lx, hw->adp:0x%lx\n", (uintptr_t)hw, (uintptr_t)(hw->adp)); return BC_STS_SUCCESS; } BC_STATUS crystalhd_hw_close(struct crystalhd_hw *hw, struct crystalhd_adp *adp) { if (!hw) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_SUCCESS; } if (!hw->dev_started) return BC_STS_SUCCESS; /* Stop and DDR sleep will happen in here */ /* Only stop the HW if we are the last user */ if(adp->cfg_users == 1) crystalhd_hw_suspend(hw); hw->dev_started = false; return BC_STS_SUCCESS; } struct crystalhd_rx_dma_pkt *crystalhd_hw_alloc_rx_pkt(struct crystalhd_hw *hw) { unsigned long flags = 0; struct crystalhd_rx_dma_pkt *temp = NULL; if (!hw) return NULL; spin_lock_irqsave(&hw->lock, flags); temp = hw->rx_pkt_pool_head; if (temp) { hw->rx_pkt_pool_head = hw->rx_pkt_pool_head->next; temp->dio_req = NULL; temp->pkt_tag = 0; temp->flags = 0; } spin_unlock_irqrestore(&hw->lock, flags); return temp; } void crystalhd_hw_free_rx_pkt(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *pkt) { unsigned long flags = 0; if (!hw || !pkt) return; spin_lock_irqsave(&hw->lock, flags); pkt->next = hw->rx_pkt_pool_head; hw->rx_pkt_pool_head = pkt; spin_unlock_irqrestore(&hw->lock, flags); } /* * Call back from TX - IOQ deletion. * * This routine will release the TX DMA rings allocated * druing setup_dma rings interface. * * Memory is allocated per DMA ring basis. This is just * a place holder to be able to create the dio queues. */ void crystalhd_tx_desc_rel_call_back(void *context, void *data) { } /* * Rx Packet release callback.. * * Release All user mapped capture buffers and Our DMA packets * back to our free pool. The actual cleanup of the DMA * ring descriptors happen during dma ring release. */ void crystalhd_rx_pkt_rel_call_back(void *context, void *data) { struct crystalhd_hw *hw = (struct crystalhd_hw *)context; struct crystalhd_rx_dma_pkt *pkt = (struct crystalhd_rx_dma_pkt *)data; if (!pkt || !hw) { printk(KERN_ERR "%s: Invalid arg - %p %p\n", __func__, hw, pkt); return; } if (pkt->dio_req) crystalhd_unmap_dio(hw->adp, pkt->dio_req); crystalhd_hw_free_rx_pkt(hw, pkt); } #define crystalhd_hw_delete_ioq(adp, q) \ if (q) { \ crystalhd_delete_dioq(adp, q); \ q = NULL; \ } void crystalhd_hw_delete_ioqs(struct crystalhd_hw *hw) { if (!hw) return; crystalhd_hw_delete_ioq(hw->adp, hw->tx_actq); crystalhd_hw_delete_ioq(hw->adp, hw->tx_freeq); crystalhd_hw_delete_ioq(hw->adp, hw->rx_actq); crystalhd_hw_delete_ioq(hw->adp, hw->rx_freeq); crystalhd_hw_delete_ioq(hw->adp, hw->rx_rdyq); } #define crystalhd_hw_create_ioq(sts, hw, q, cb) \ do { \ sts = crystalhd_create_dioq(hw->adp, &q, cb, hw); \ if (sts != BC_STS_SUCCESS) \ goto hw_create_ioq_err; \ } while (0) /* * Create IOQs.. * * TX - Active & Free * RX - Active, Ready and Free. */ BC_STATUS crystalhd_hw_create_ioqs(struct crystalhd_hw *hw) { BC_STATUS sts = BC_STS_SUCCESS; if (!hw) { printk(KERN_ERR "%s: Invalid Arg!!\n", __func__); return BC_STS_INV_ARG; } crystalhd_hw_create_ioq(sts, hw, hw->tx_freeq, crystalhd_tx_desc_rel_call_back); crystalhd_hw_create_ioq(sts, hw, hw->tx_actq, crystalhd_tx_desc_rel_call_back); crystalhd_hw_create_ioq(sts, hw, hw->rx_freeq, crystalhd_rx_pkt_rel_call_back); crystalhd_hw_create_ioq(sts, hw, hw->rx_rdyq, crystalhd_rx_pkt_rel_call_back); crystalhd_hw_create_ioq(sts, hw, hw->rx_actq, crystalhd_rx_pkt_rel_call_back); return sts; hw_create_ioq_err: crystalhd_hw_delete_ioqs(hw); return sts; } BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *hw) { struct device *dev; unsigned int i; void *mem; size_t mem_len; dma_addr_t phy_addr; BC_STATUS sts = BC_STS_SUCCESS; struct crystalhd_rx_dma_pkt *rpkt; if (!hw || !hw->adp) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } dev = &hw->adp->pdev->dev; sts = crystalhd_hw_create_ioqs(hw); if (sts != BC_STS_SUCCESS) { dev_err(dev, "Failed to create IOQs..\n"); return sts; } mem_len = BC_LINK_MAX_SGLS * sizeof(struct dma_descriptor); for (i = 0; i < BC_TX_LIST_CNT; i++) { mem = bc_kern_dma_alloc(hw->adp, mem_len, &phy_addr); if (mem) { memset(mem, 0, mem_len); } else { dev_err(dev, "Insufficient Memory For TX\n"); crystalhd_hw_free_dma_rings(hw); return BC_STS_INSUFF_RES; } /* rx_pkt_pool -- static memory allocation */ hw->tx_pkt_pool[i].desc_mem.pdma_desc_start = mem; hw->tx_pkt_pool[i].desc_mem.phy_addr = phy_addr; hw->tx_pkt_pool[i].desc_mem.sz = BC_LINK_MAX_SGLS * sizeof(struct dma_descriptor); hw->tx_pkt_pool[i].list_tag = 0; /* Add TX dma requests to Free Queue..*/ sts = crystalhd_dioq_add(hw->tx_freeq, &hw->tx_pkt_pool[i], false, 0); if (sts != BC_STS_SUCCESS) { crystalhd_hw_free_dma_rings(hw); return sts; } } for (i = 0; i < BC_RX_LIST_CNT; i++) { rpkt = kzalloc(sizeof(*rpkt), GFP_KERNEL); if (!rpkt) { dev_err(dev, "Insufficient Memory For RX\n"); crystalhd_hw_free_dma_rings(hw); return BC_STS_INSUFF_RES; } mem = bc_kern_dma_alloc(hw->adp, mem_len, &phy_addr); if (mem) { memset(mem, 0, mem_len); } else { dev_err(dev, "Insufficient Memory For RX\n"); crystalhd_hw_free_dma_rings(hw); return BC_STS_INSUFF_RES; } rpkt->desc_mem.pdma_desc_start = mem; rpkt->desc_mem.phy_addr = phy_addr; rpkt->desc_mem.sz = BC_LINK_MAX_SGLS * sizeof(struct dma_descriptor); rpkt->pkt_tag = hw->rx_pkt_tag_seed + i; crystalhd_hw_free_rx_pkt(hw, rpkt); } return BC_STS_SUCCESS; } BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *hw) { unsigned int i; struct crystalhd_rx_dma_pkt *rpkt = NULL; if (!hw || !hw->adp) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } /* Delete all IOQs.. */ crystalhd_hw_delete_ioqs(hw); for (i = 0; i < BC_TX_LIST_CNT; i++) { if (hw->tx_pkt_pool[i].desc_mem.pdma_desc_start) { bc_kern_dma_free(hw->adp, hw->tx_pkt_pool[i].desc_mem.sz, hw->tx_pkt_pool[i].desc_mem.pdma_desc_start, hw->tx_pkt_pool[i].desc_mem.phy_addr); hw->tx_pkt_pool[i].desc_mem.pdma_desc_start = NULL; } } dev_dbg(&hw->adp->pdev->dev, "Releasing RX Pkt pool\n"); for (i = 0; i < BC_RX_LIST_CNT; i++) { rpkt = crystalhd_hw_alloc_rx_pkt(hw); if (!rpkt) break; bc_kern_dma_free(hw->adp, rpkt->desc_mem.sz, rpkt->desc_mem.pdma_desc_start, rpkt->desc_mem.phy_addr); kfree(rpkt); } return BC_STS_SUCCESS; } BC_STATUS crystalhd_hw_tx_req_complete(struct crystalhd_hw *hw, uint32_t list_id, BC_STATUS cs) { struct tx_dma_pkt *tx_req; if (!hw || !list_id) { printk(KERN_ERR "%s: Invalid Arg!!\n", __func__); return BC_STS_INV_ARG; } tx_req = (struct tx_dma_pkt *)crystalhd_dioq_find_and_fetch(hw->tx_actq, list_id); if (!tx_req) { if (cs != BC_STS_IO_USER_ABORT) dev_err(&hw->adp->pdev->dev, "Find/Fetch: no req!\n"); return BC_STS_NO_DATA; } if (tx_req->call_back) { tx_req->call_back(tx_req->dio_req, tx_req->cb_event, cs); tx_req->dio_req = NULL; tx_req->cb_event = NULL; tx_req->call_back = NULL; } else { dev_dbg(&hw->adp->pdev->dev, "Missing Tx Callback - %X\n", tx_req->list_tag); } /* Now put back the tx_list back in FreeQ */ tx_req->list_tag = 0; return crystalhd_dioq_add(hw->tx_freeq, tx_req, false, 0); } BC_STATUS crystalhd_hw_fill_desc(struct crystalhd_dio_req *ioreq, struct dma_descriptor *desc, dma_addr_t desc_paddr_base, uint32_t sg_cnt, uint32_t sg_st_ix, uint32_t sg_st_off, uint32_t xfr_sz, struct device *dev, uint32_t destDRAMaddr) { uint32_t count = 0, ix = 0, sg_ix = 0, len = 0, last_desc_ix = 0; dma_addr_t desc_phy_addr = desc_paddr_base; addr_64 addr_temp; uint32_t curDRAMaddr = destDRAMaddr; if (!ioreq || !desc || !desc_paddr_base || !xfr_sz || (!sg_cnt && !ioreq->uinfo.dir_tx)) { dev_err(dev, "%s: Invalid Args\n", __func__); return BC_STS_INV_ARG; } for (ix = 0; ix < sg_cnt; ix++) { /* Setup SGLE index. */ sg_ix = ix + sg_st_ix; /* Get SGLE length */ len = crystalhd_get_sgle_len(ioreq, sg_ix); if (len % 4) { dev_err(dev, "unsupported len in sg %d %d %d\n", len, sg_ix, sg_cnt); return BC_STS_NOT_IMPL; } /* Setup DMA desc with Phy addr & Length at current index. */ addr_temp.full_addr = crystalhd_get_sgle_paddr(ioreq, sg_ix); if (sg_ix == sg_st_ix) { addr_temp.full_addr += sg_st_off; len -= sg_st_off; } memset(&desc[ix], 0, sizeof(desc[ix])); desc[ix].buff_addr_low = addr_temp.low_part; desc[ix].buff_addr_high = addr_temp.high_part; desc[ix].dma_dir = ioreq->uinfo.dir_tx; /* RX dma_dir = 0, TX dma_dir = 1 */ /* Chain DMA descriptor. */ addr_temp.full_addr = desc_phy_addr + sizeof(struct dma_descriptor); desc[ix].next_desc_addr_low = addr_temp.low_part; desc[ix].next_desc_addr_high = addr_temp.high_part; if ((count + len) > xfr_sz) len = xfr_sz - count; /* Debug.. */ if ((!len) || (len > crystalhd_get_sgle_len(ioreq, sg_ix))) { dev_err(dev, "inv-len(%x) Ix(%d) count:%x xfr_sz:%x " "sg_cnt:%d\n", len, ix, count, xfr_sz, sg_cnt); return BC_STS_ERROR; } /* Length expects Multiple of 4 */ desc[ix].xfer_size = (len / 4); count += len; /* If TX fill in the destination DRAM address if needed */ if(ioreq->uinfo.dir_tx) { desc[ix].sdram_buff_addr = curDRAMaddr; curDRAMaddr = destDRAMaddr + count; } else desc[ix].sdram_buff_addr = 0; desc_phy_addr += sizeof(struct dma_descriptor); } last_desc_ix = ix - 1; if (ioreq->fb_size) { memset(&desc[ix], 0, sizeof(desc[ix])); addr_temp.full_addr = ioreq->fb_pa; desc[ix].buff_addr_low = addr_temp.low_part; desc[ix].buff_addr_high = addr_temp.high_part; desc[ix].dma_dir = ioreq->uinfo.dir_tx; desc[ix].xfer_size = 1; desc[ix].fill_bytes = 4 - ioreq->fb_size; count += ioreq->fb_size; /* If TX fill in the destination DRAM address if needed */ if(ioreq->uinfo.dir_tx) { desc[ix].sdram_buff_addr = curDRAMaddr; curDRAMaddr = destDRAMaddr + count; } else desc[ix].sdram_buff_addr = 0; last_desc_ix++; } /* setup last descriptor..*/ desc[last_desc_ix].last_rec_indicator = 1; desc[last_desc_ix].next_desc_addr_low = 0; desc[last_desc_ix].next_desc_addr_high = 0; desc[last_desc_ix].intr_enable = 1; if (count != xfr_sz) { dev_err(dev, "interal error sz curr:%x exp:%x\n", count, xfr_sz); return BC_STS_ERROR; } return BC_STS_SUCCESS; } BC_STATUS crystalhd_xlat_sgl_to_dma_desc(struct crystalhd_dio_req *ioreq, struct dma_desc_mem * pdesc_mem, uint32_t *uv_desc_index, struct device *dev, uint32_t destDRAMaddr) { struct dma_descriptor *desc = NULL; dma_addr_t desc_paddr_base = 0; uint32_t sg_cnt = 0, sg_st_ix = 0, sg_st_off = 0; uint32_t xfr_sz = 0; BC_STATUS sts = BC_STS_SUCCESS; /* Check params.. */ if (!ioreq || !pdesc_mem || !uv_desc_index) { dev_err(dev, "%s: Invalid Args\n", __func__); return BC_STS_INV_ARG; } if (!pdesc_mem->sz || !pdesc_mem->pdma_desc_start || !ioreq->sg || (!ioreq->sg_cnt && !ioreq->uinfo.dir_tx)) { dev_err(dev, "%s: Invalid Args\n", __func__); return BC_STS_INV_ARG; } if ((ioreq->uinfo.dir_tx) && (ioreq->uinfo.uv_offset)) { dev_err(dev, "%s: UV offset for TX??\n", __func__); return BC_STS_INV_ARG; } desc = pdesc_mem->pdma_desc_start; desc_paddr_base = pdesc_mem->phy_addr; if (ioreq->uinfo.dir_tx || (ioreq->uinfo.uv_offset == 0)) { sg_cnt = ioreq->sg_cnt; xfr_sz = ioreq->uinfo.xfr_len; } else { sg_cnt = ioreq->uinfo.uv_sg_ix + 1; xfr_sz = ioreq->uinfo.uv_offset; } sts = crystalhd_hw_fill_desc(ioreq, desc, desc_paddr_base, sg_cnt, sg_st_ix, sg_st_off, xfr_sz, dev, destDRAMaddr); if ((sts != BC_STS_SUCCESS) || !ioreq->uinfo.uv_offset) return sts; /* Prepare for UV mapping.. */ desc = &pdesc_mem->pdma_desc_start[sg_cnt]; desc_paddr_base = pdesc_mem->phy_addr + (sg_cnt * sizeof(struct dma_descriptor)); /* Done with desc addr.. now update sg stuff.*/ sg_cnt = ioreq->sg_cnt - ioreq->uinfo.uv_sg_ix; xfr_sz = ioreq->uinfo.xfr_len - ioreq->uinfo.uv_offset; sg_st_ix = ioreq->uinfo.uv_sg_ix; sg_st_off = ioreq->uinfo.uv_sg_off; sts = crystalhd_hw_fill_desc(ioreq, desc, desc_paddr_base, sg_cnt, sg_st_ix, sg_st_off, xfr_sz, dev, destDRAMaddr); if (sts != BC_STS_SUCCESS) return sts; *uv_desc_index = sg_st_ix; return sts; } BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw, uint32_t list_index, BC_STATUS comp_sts) { struct crystalhd_rx_dma_pkt *rx_pkt = NULL; uint32_t y_dw_dnsz, uv_dw_dnsz; BC_STATUS sts = BC_STS_SUCCESS; uint64_t currTick; uint32_t totalTick_Hi; uint32_t TickSpentInPD_Hi; uint64_t temp_64; int32_t totalTick_Hi_f; int32_t TickSpentInPD_Hi_f; if (!hw || list_index >= DMA_ENGINE_CNT) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } rx_pkt = crystalhd_dioq_find_and_fetch(hw->rx_actq, hw->rx_pkt_tag_seed + list_index); if (!rx_pkt) { dev_err(&hw->adp->pdev->dev, "Act-Q: PostIx:%x L0Sts:%x " "L1Sts:%x current L:%x tag:%x comp:%x\n", hw->rx_list_post_index, hw->rx_list_sts[0], hw->rx_list_sts[1], list_index, hw->rx_pkt_tag_seed + list_index, comp_sts); return BC_STS_INV_ARG; } if (comp_sts == BC_STS_SUCCESS) { hw->DrvTotalFrmCaptured++; hw->pfnHWGetDoneSize(hw, list_index, &y_dw_dnsz, &uv_dw_dnsz); rx_pkt->dio_req->uinfo.y_done_sz = y_dw_dnsz; rx_pkt->flags = COMP_FLAG_DATA_VALID; if (rx_pkt->uv_phy_addr) rx_pkt->dio_req->uinfo.uv_done_sz = uv_dw_dnsz; crystalhd_dioq_add(hw->rx_rdyq, rx_pkt, true, hw->rx_pkt_tag_seed + list_index); if( hw->adp->pdev->device == BC_PCI_DEVID_FLEA) { /*printk("pre-PD state %x RLL %x Ptsh %x ratio %d currentPS %d\n", */ /* hw->FleaPowerState, crystalhd_dioq_count(hw->rx_rdyq) , hw->PauseThreshold, hw->PDRatio, hw->FleaPowerState); */ if(hw->FleaPowerState == FLEA_PS_ACTIVE) { if(crystalhd_dioq_count(hw->rx_rdyq) >= hw->PauseThreshold) { hw->pfnIssuePause(hw, true); hw->hw_pause_issued = true; } /* NAREN check if the PD ratio is less than 50. If so, try to reduce the PauseThreshold to improve the ratio */ /* never go lower than 6 pictures */ /* Only do this when we have some data to determine PDRatio */ /* For now assume that if we have captured 100 pictures then we should have enough data for the analysis to start */ if((hw->PDRatio < 50) && (hw->PauseThreshold > 6) && (hw->DrvTotalFrmCaptured > 100)) { /*printk("Current PDRatio:%u, PauseThreshold:%u, DrvTotalFrmCaptured:%u decress PauseThreshold\n", */ /* hw->PDRatio, hw->PauseThreshold, hw->DrvTotalFrmCaptured); */ hw->PauseThreshold--; } else { rdtscll(currTick); temp_64 = (hw->TickSpentInPD)>>24; TickSpentInPD_Hi = (uint32_t)(temp_64); TickSpentInPD_Hi_f = (int32_t)TickSpentInPD_Hi; temp_64 = (currTick - hw->TickCntDecodePU)>>24; totalTick_Hi = (uint32_t)(temp_64); totalTick_Hi_f = (int32_t)totalTick_Hi; if( totalTick_Hi_f <= 0 ) { temp_64 = (hw->TickSpentInPD); TickSpentInPD_Hi = (uint32_t)(temp_64); TickSpentInPD_Hi_f = (int32_t)TickSpentInPD_Hi; temp_64 = (currTick - hw->TickCntDecodePU); totalTick_Hi = (uint32_t)(temp_64); totalTick_Hi_f = (int32_t)totalTick_Hi; } if( totalTick_Hi_f <= 0 ) { printk("totalTick_Hi_f <= 0, set hw->PDRatio = 60\n"); hw->PDRatio = 60; } else hw->PDRatio = (TickSpentInPD_Hi_f * 100) / totalTick_Hi_f; /*printk("Current PDRatio:%u, PauseThreshold:%u, DrvTotalFrmCaptured:%u don't decress PauseThreshold\n", */ /* hw->PDRatio, hw->PauseThreshold, hw->DrvTotalFrmCaptured); */ /*hw->PDRatio = ((uint32_t)(hw->TickSpentInPD))/((uint32_t)(currTick - hw->TickCntDecodePU)/100); */ } } } else if( hw->hw_pause_issued == false ) { #if 0 if(crystalhd_dioq_count(hw->rx_rdyq) > hw->PauseThreshold)/*HW_PAUSE_THRESHOLD */ { dev_info(&hw->adp->pdev->dev, "HW PAUSE\n"); hw->pfnIssuePause(hw, true); hw->hw_pause_issued = true; } #endif } return sts; } /* Check if we can post this DIO again. */ return hw->pfnPostRxSideBuff(hw, rx_pkt); } BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq, hw_comp_callback call_back, wait_queue_head_t *cb_event, uint32_t *list_id, uint8_t data_flags) { struct device *dev; struct tx_dma_pkt *tx_dma_packet = NULL; uint32_t low_addr, high_addr; addr_64 desc_addr; BC_STATUS sts, add_sts; uint32_t dummy_index = 0; unsigned long flags; uint8_t list_posted; uint8_t local_flags = data_flags; bool rc; uint32_t destDRAMaddr = 0; if (!hw || !ioreq || !call_back || !cb_event || !list_id) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } dev = &hw->adp->pdev->dev; /* * Since we hit code in busy condition very frequently, * we will check the code in status first before * checking the availability of free elem. * * This will avoid the Q fetch/add in normal condition. */ rc = hw->pfnCheckInputFIFO(hw, ioreq->uinfo.xfr_len, &dummy_index, false, &local_flags); if (rc) { hw->stats.cin_busy++; return BC_STS_BUSY; } if(local_flags & BC_BIT(7)) destDRAMaddr = hw->TxFwInputBuffInfo.DramBuffAdd; /* Get a list from TxFreeQ */ tx_dma_packet = (struct tx_dma_pkt *)crystalhd_dioq_fetch(hw->tx_freeq); if (!tx_dma_packet) { dev_err(dev, "No empty elements..\n"); return BC_STS_INSUFF_RES; } sts = crystalhd_xlat_sgl_to_dma_desc(ioreq, &tx_dma_packet->desc_mem, &dummy_index, dev, destDRAMaddr); if (sts != BC_STS_SUCCESS) { add_sts = crystalhd_dioq_add(hw->tx_freeq, tx_dma_packet, false, 0); if (add_sts != BC_STS_SUCCESS) dev_err(dev, "double fault..\n"); return sts; } desc_addr.full_addr = tx_dma_packet->desc_mem.phy_addr; low_addr = desc_addr.low_part; high_addr = desc_addr.high_part; tx_dma_packet->call_back = call_back; tx_dma_packet->cb_event = cb_event; tx_dma_packet->dio_req = ioreq; spin_lock_irqsave(&hw->lock, flags); list_posted = hw->tx_list_post_index; *list_id = tx_dma_packet->list_tag = hw->tx_ioq_tag_seed + hw->tx_list_post_index; if( hw->tx_list_post_index % DMA_ENGINE_CNT) { hw->TxList1Sts |= TxListWaitingForIntr; } else { hw->TxList0Sts |= TxListWaitingForIntr; } hw->tx_list_post_index = (hw->tx_list_post_index + 1) % DMA_ENGINE_CNT; /* Insert in Active Q..*/ crystalhd_dioq_add(hw->tx_actq, tx_dma_packet, false, tx_dma_packet->list_tag); /* * Interrupt will come as soon as you write * the valid bit. So be ready for that. All * the initialization should happen before that. */ /* Save the transfer length */ hw->TxFwInputBuffInfo.HostXferSzInBytes = ioreq->uinfo.xfr_len; hw->pfnStartTxDMA(hw, list_posted, desc_addr); spin_unlock_irqrestore(&hw->lock, flags); return BC_STS_SUCCESS; } /* * This is a force cancel and we are racing with ISR. * * Will try to remove the req from ActQ before ISR gets it. * If ISR gets it first then the completion happens in the * normal path and we will return _STS_NO_DATA from here. * * FIX_ME: Not Tested the actual condition.. */ BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id) { unsigned long flags; if (!hw || !list_id) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } spin_lock_irqsave(&hw->lock, flags); hw->pfnStopTxDMA(hw); spin_unlock_irqrestore(&hw->lock, flags); crystalhd_hw_tx_req_complete(hw, list_id, BC_STS_IO_USER_ABORT); return BC_STS_SUCCESS; } BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq, bool en_post) { struct crystalhd_rx_dma_pkt *rpkt; uint32_t tag, uv_desc_ix = 0; BC_STATUS sts; if (!hw || !ioreq) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } rpkt = crystalhd_hw_alloc_rx_pkt(hw); if (!rpkt) { dev_err(&hw->adp->pdev->dev, "Insufficient resources\n"); return BC_STS_INSUFF_RES; } rpkt->dio_req = ioreq; tag = rpkt->pkt_tag; sts = crystalhd_xlat_sgl_to_dma_desc(ioreq, &rpkt->desc_mem, &uv_desc_ix, &hw->adp->pdev->dev, 0); if (sts != BC_STS_SUCCESS) return sts; rpkt->uv_phy_addr = 0; /* Store the address of UV in the rx packet for post*/ if (uv_desc_ix) rpkt->uv_phy_addr = rpkt->desc_mem.phy_addr + (sizeof(struct dma_descriptor) * (uv_desc_ix + 1)); if (en_post && !hw->hw_pause_issued) { sts = hw->pfnPostRxSideBuff(hw, rpkt); } else { sts = crystalhd_dioq_add(hw->rx_freeq, rpkt, false, tag); hw->pfnNotifyFLLChange(hw, false); } return sts; } BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw, struct C011_PIB *pib, struct crystalhd_dio_req **ioreq) { struct crystalhd_rx_dma_pkt *rpkt; uint32_t timeout = BC_PROC_OUTPUT_TIMEOUT / 1000; uint32_t sig_pending = 0; if (!hw || !ioreq || !pib) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } rpkt = crystalhd_dioq_fetch_wait(hw, timeout, &sig_pending); if( hw->adp->pdev->device == BC_PCI_DEVID_FLEA) { /*printk("pre-PU state %x RLL %x Rtsh %x, currentPS %d,\n", */ /* hw->FleaPowerState, crystalhd_dioq_count(hw->rx_rdyq) , hw->ResumeThreshold, hw->FleaPowerState); */ if( (hw->FleaPowerState == FLEA_PS_LP_PENDING) || (hw->FleaPowerState == FLEA_PS_LP_COMPLETE)) { if(crystalhd_dioq_count(hw->rx_rdyq) <= hw->ResumeThreshold) hw->pfnIssuePause(hw, false); /*Need this Notification For Flea*/ hw->hw_pause_issued = false; } } else if( hw->hw_pause_issued) { #if 0 if(crystalhd_dioq_count(hw->rx_rdyq) < hw->PauseThreshold ) /*HW_RESUME_THRESHOLD */ { dev_info(&hw->adp->pdev->dev, "HW RESUME with rdy list %u \n",crystalhd_dioq_count(hw->rx_rdyq)); hw->pfnIssuePause(hw, false); hw->hw_pause_issued = false; } #endif } if (!rpkt) { if (sig_pending) { return BC_STS_IO_USER_ABORT; } else { return BC_STS_TIMEOUT; } } rpkt->dio_req->uinfo.comp_flags = rpkt->flags; if (rpkt->flags & COMP_FLAG_PIB_VALID) { pib->ppb.picture_number = rpkt->pib.picture_number; pib->ppb.width = rpkt->pib.width; pib->ppb.height = rpkt->pib.height; pib->ppb.chroma_format = rpkt->pib.chroma_format; pib->ppb.pulldown = rpkt->pib.pulldown; pib->ppb.flags = rpkt->pib.flags; pib->ptsStcOffset = rpkt->pib.sess_num; pib->ppb.aspect_ratio = rpkt->pib.aspect_ratio; pib->ppb.colour_primaries = rpkt->pib.colour_primaries; pib->ppb.picture_meta_payload = rpkt->pib.picture_meta_payload; pib->resolution = rpkt->pib.frame_rate; } *ioreq = rpkt->dio_req; crystalhd_hw_free_rx_pkt(hw, rpkt); return BC_STS_SUCCESS; } BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw) { struct crystalhd_rx_dma_pkt *rx_pkt; BC_STATUS sts; uint32_t i; if (!hw) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } /* This is start of capture.. Post to both the lists.. */ for (i = 0; i < DMA_ENGINE_CNT; i++) { rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); if (!rx_pkt) return BC_STS_NO_DATA; sts = hw->pfnPostRxSideBuff(hw, rx_pkt); if (BC_STS_SUCCESS != sts) break; } return BC_STS_SUCCESS; } BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw, bool unmap) { void *temp = NULL; if (!hw) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } hw->pfnStopRXDMAEngines(hw); if(!unmap) return BC_STS_SUCCESS; /* Clear up Active, Ready and Free lists one by one and release resources */ do { temp = crystalhd_dioq_fetch(hw->rx_actq); if (temp) crystalhd_rx_pkt_rel_call_back(hw, temp); } while (temp); do { temp = crystalhd_dioq_fetch(hw->rx_rdyq); if (temp) crystalhd_rx_pkt_rel_call_back(hw, temp); } while (temp); do { temp = crystalhd_dioq_fetch(hw->rx_freeq); if (temp) crystalhd_rx_pkt_rel_call_back(hw, temp); } while (temp); return BC_STS_SUCCESS; } BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw) { if (!hw) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } if (!hw->pfnStopDevice(hw)) { dev_info(&hw->adp->pdev->dev, "Failed to Stop Device!!\n"); return BC_STS_ERROR; } return BC_STS_SUCCESS; } BC_STATUS crystalhd_hw_resume(struct crystalhd_hw *hw) { if (!hw) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } // Reset list state hw->rx_list_sts[0] = sts_free; hw->rx_list_sts[1] = sts_free; hw->TxList0Sts = ListStsFree; hw->TxList1Sts = ListStsFree; hw->rx_list_post_index = 0; hw->tx_list_post_index = 0; if (hw->pfnStartDevice(hw)) { dev_info(&hw->adp->pdev->dev, "Failed to Start Device!!\n"); return BC_STS_ERROR; } return BC_STS_SUCCESS; } void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats) { if (!hw) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return; } /* if called w/NULL stats, its a req to zero out the stats */ if (!stats) { hw->DrvTotalFrmCaptured = 0; memset(&hw->stats, 0, sizeof(hw->stats)); return; } hw->stats.freeq_count = crystalhd_dioq_count(hw->rx_freeq); hw->stats.rdyq_count = crystalhd_dioq_count(hw->rx_rdyq); memcpy(stats, &hw->stats, sizeof(*stats)); } crystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_linkfuncs.c0000644000175000017500000016202411610313111024401 0ustar andresandres/*************************************************************************** * Copyright (c) 2005-2009, Broadcom Corporation. * * Name: crystalhd_hw . c * * Description: * BCM70010 Linux driver HW layer. * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ #include #include #include #include #include "crystalhd_hw.h" #include "crystalhd_lnx.h" #include "crystalhd_linkfuncs.h" #define OFFSETOF(_s_, _m_) ((size_t)(unsigned long)&(((_s_ *)0)->_m_)) /** * link_dec_reg_rd - Read 70010's device register. * @adp: Adapter instance * @reg_off: Register offset. * * Return: * 32bit value read * * 70010's device register read routine. This interface use * 70010's device access range mapped from BAR-2 (4M) of PCIe * configuration space. */ uint32_t link_dec_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off) { if (!adp) { printk(KERN_ERR "%s: Invalid args\n", __func__); return 0; } if (reg_off > adp->pci_mem_len) { dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", __func__, reg_off); return 0; } return readl(adp->mem_addr + reg_off); } /** * link_dec_reg_wr - Write 70010's device register * @adp: Adapter instance * @reg_off: Register offset. * @val: Dword value to be written. * * Return: * none. * * 70010's device register write routine. This interface use * 70010's device access range mapped from BAR-2 (4M) of PCIe * configuration space. */ void link_dec_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val) { if (!adp) { printk(KERN_ERR "%s: Invalid args\n", __func__); return; } if (reg_off > adp->pci_mem_len) { dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", __func__, reg_off); return; } writel(val, adp->mem_addr + reg_off); /* the udelay is required for latest 70012, not for others... :( */ udelay(8); } /** * crystalhd_reg_rd - Read 70012's device register. * @adp: Adapter instance * @reg_off: Register offset. * * Return: * 32bit value read * * 70012 device register read routine. This interface use * 70012's device access range mapped from BAR-1 (64K) of PCIe * configuration space. * */ uint32_t crystalhd_link_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off) { if (!adp) { printk(KERN_ERR "%s: Invalid args\n", __func__); return 0; } if (reg_off > adp->pci_i2o_len) { dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", __func__, reg_off); return 0; } return readl(adp->i2o_addr + reg_off); } /** * crystalhd_reg_wr - Write 70012's device register * @adp: Adapter instance * @reg_off: Register offset. * @val: Dword value to be written. * * Return: * none. * * 70012 device register write routine. This interface use * 70012's device access range mapped from BAR-1 (64K) of PCIe * configuration space. * */ void crystalhd_link_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val) { if (!adp) { printk(KERN_ERR "%s: Invalid args\n", __func__); return; } if (reg_off > adp->pci_i2o_len) { dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", __func__, reg_off); return; } writel(val, adp->i2o_addr + reg_off); } inline uint32_t crystalhd_link_dram_rd(struct crystalhd_hw *hw, uint32_t mem_off) { hw->pfnWriteFPGARegister(hw->adp, DCI_DRAM_BASE_ADDR, (mem_off >> 19)); return hw->pfnReadDevRegister(hw->adp, (0x00380000 | (mem_off & 0x0007FFFF))); } inline void crystalhd_link_dram_wr(struct crystalhd_hw *hw, uint32_t mem_off, uint32_t val) { hw->pfnWriteFPGARegister(hw->adp, DCI_DRAM_BASE_ADDR, (mem_off >> 19)); hw->pfnWriteDevRegister(hw->adp, (0x00380000 | (mem_off & 0x0007FFFF)), val); } /** * crystalhd_link_mem_rd - Read data from DRAM area. * @adp: Adapter instance * @start_off: Start offset. * @dw_cnt: Count in dwords. * @rd_buff: Buffer to copy the data from dram. * * Return: * Status. * * Dram read routine. */ BC_STATUS crystalhd_link_mem_rd(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *rd_buff) { uint32_t ix = 0; if (!hw || !rd_buff) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } for (ix = 0; ix < dw_cnt; ix++) rd_buff[ix] = crystalhd_link_dram_rd(hw, (start_off + (ix * 4))); return BC_STS_SUCCESS; } /** * crystalhd_link_mem_wr - Write data to DRAM area. * @adp: Adapter instance * @start_off: Start offset. * @dw_cnt: Count in dwords. * @wr_buff: Data Buffer to be written. * * Return: * Status. * * Dram write routine. */ BC_STATUS crystalhd_link_mem_wr(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *wr_buff) { uint32_t ix = 0; if (!hw || !wr_buff) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } for (ix = 0; ix < dw_cnt; ix++) crystalhd_link_dram_wr(hw, (start_off + (ix * 4)), wr_buff[ix]); return BC_STS_SUCCESS; } void crystalhd_link_enable_uarts(struct crystalhd_hw *hw) { hw->pfnWriteDevRegister(hw->adp, UartSelectA, BSVS_UART_STREAM); hw->pfnWriteDevRegister(hw->adp, UartSelectB, BSVS_UART_DEC_OUTER); } void crystalhd_link_start_dram(struct crystalhd_hw *hw) { hw->pfnWriteDevRegister(hw->adp, SDRAM_PARAM, ((40 / 5 - 1) << 0) | #if 0 tras (40ns tras)/(5ns period) -1 ((15/5 - 1) << 4) | /* trcd */ #endif ((15 / 5 - 1) << 7) | /* trp */ ((10 / 5 - 1) << 10) | /* trrd */ ((15 / 5 + 1) << 12) | /* twr */ ((2 + 1) << 16) | /* twtr */ ((70 / 5 - 2) << 19) | /* trfc */ (0 << 23)); hw->pfnWriteDevRegister(hw->adp, SDRAM_PRECHARGE, 0); hw->pfnWriteDevRegister(hw->adp, SDRAM_EXT_MODE, 2); hw->pfnWriteDevRegister(hw->adp, SDRAM_MODE, 0x132); hw->pfnWriteDevRegister(hw->adp, SDRAM_PRECHARGE, 0); hw->pfnWriteDevRegister(hw->adp, SDRAM_REFRESH, 0); hw->pfnWriteDevRegister(hw->adp, SDRAM_REFRESH, 0); hw->pfnWriteDevRegister(hw->adp, SDRAM_MODE, 0x32); /* setting the refresh rate here */ hw->pfnWriteDevRegister(hw->adp, SDRAM_REF_PARAM, ((1 << 12) | 96)); } bool crystalhd_link_bring_out_of_rst(struct crystalhd_hw *hw) { union link_misc_perst_deco_ctrl rst_deco_cntrl; union link_misc_perst_clk_ctrl rst_clk_cntrl; uint32_t temp; /* * Link clocks: MISC_PERST_CLOCK_CTRL Clear PLL power down bit, * delay to allow PLL to lock Clear alternate clock, stop clock bits */ rst_clk_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL); rst_clk_cntrl.pll_pwr_dn = 0; hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); msleep_interruptible(50); rst_clk_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL); rst_clk_cntrl.stop_core_clk = 0; rst_clk_cntrl.sel_alt_clk = 0; hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); msleep_interruptible(50); /* * Bus Arbiter Timeout: GISB_ARBITER_TIMER * Set internal bus arbiter timeout to 40us based on core clock speed * (63MHz * 40us = 0x9D8) */ hw->pfnWriteFPGARegister(hw->adp, GISB_ARBITER_TIMER, 0x9D8); /* * Decoder clocks: MISC_PERST_DECODER_CTRL * Enable clocks while 7412 reset is asserted, delay * De-assert 7412 reset */ rst_deco_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL); rst_deco_cntrl.stop_bcm_7412_clk = 0; rst_deco_cntrl.bcm7412_rst = 1; hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); msleep_interruptible(50); rst_deco_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL); rst_deco_cntrl.bcm7412_rst = 0; hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); msleep_interruptible(50); /* Disable OTP_CONTENT_MISC to 0 to disable all secure modes */ hw->pfnWriteFPGARegister(hw->adp, OTP_CONTENT_MISC, 0); /* Clear bit 29 of 0x404 */ temp = hw->pfnReadFPGARegister(hw->adp, PCIE_TL_TRANSACTION_CONFIGURATION); temp &= ~BC_BIT(29); hw->pfnWriteFPGARegister(hw->adp, PCIE_TL_TRANSACTION_CONFIGURATION, temp); /* 2.5V regulator must be set to 2.6 volts (+6%) */ hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_VREG_CTRL, 0xF3); return true; } bool crystalhd_link_put_in_reset(struct crystalhd_hw *hw) { union link_misc_perst_deco_ctrl rst_deco_cntrl; union link_misc_perst_clk_ctrl rst_clk_cntrl; uint32_t temp; /* * Decoder clocks: MISC_PERST_DECODER_CTRL * Assert 7412 reset, delay * Assert 7412 stop clock */ rst_deco_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL); rst_deco_cntrl.stop_bcm_7412_clk = 1; hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_deco_cntrl.whole_reg); msleep_interruptible(50); /* Bus Arbiter Timeout: GISB_ARBITER_TIMER * Set internal bus arbiter timeout to 40us based on core clock speed * (6.75MHZ * 40us = 0x10E) */ hw->pfnWriteFPGARegister(hw->adp, GISB_ARBITER_TIMER, 0x10E); /* Link clocks: MISC_PERST_CLOCK_CTRL * Stop core clk, delay * Set alternate clk, delay, set PLL power down */ rst_clk_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL); rst_clk_cntrl.stop_core_clk = 1; rst_clk_cntrl.sel_alt_clk = 1; hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); msleep_interruptible(50); rst_clk_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL); rst_clk_cntrl.pll_pwr_dn = 1; hw->pfnWriteFPGARegister(hw->adp, MISC_PERST_CLOCK_CTRL, rst_clk_cntrl.whole_reg); /* * Read and restore the Transaction Configuration Register * after core reset */ temp = hw->pfnReadFPGARegister(hw->adp, PCIE_TL_TRANSACTION_CONFIGURATION); /* * Link core soft reset: MISC3_RESET_CTRL * - Write BIT[0]=1 and read it back for core reset to take place */ hw->pfnWriteFPGARegister(hw->adp, MISC3_RESET_CTRL, 1); rst_deco_cntrl.whole_reg = hw->pfnReadFPGARegister(hw->adp, MISC3_RESET_CTRL); msleep_interruptible(50); /* restore the transaction configuration register */ hw->pfnWriteFPGARegister(hw->adp, PCIE_TL_TRANSACTION_CONFIGURATION, temp); return true; } void crystalhd_link_disable_interrupts(struct crystalhd_hw *hw) { union intr_mask_reg intr_mask; intr_mask.whole_reg = hw->pfnReadFPGARegister(hw->adp, INTR_INTR_MSK_STS_REG); intr_mask.mask_pcie_err = 1; intr_mask.mask_pcie_rbusmast_err = 1; intr_mask.mask_pcie_rgr_bridge = 1; intr_mask.mask_rx_done = 1; intr_mask.mask_rx_err = 1; intr_mask.mask_tx_done = 1; intr_mask.mask_tx_err = 1; hw->pfnWriteFPGARegister(hw->adp, INTR_INTR_MSK_SET_REG, intr_mask.whole_reg); return; } void crystalhd_link_enable_interrupts(struct crystalhd_hw *hw) { union intr_mask_reg intr_mask; intr_mask.whole_reg = hw->pfnReadFPGARegister(hw->adp, INTR_INTR_MSK_STS_REG); intr_mask.mask_pcie_err = 1; intr_mask.mask_pcie_rbusmast_err = 1; intr_mask.mask_pcie_rgr_bridge = 1; intr_mask.mask_rx_done = 1; intr_mask.mask_rx_err = 1; intr_mask.mask_tx_done = 1; intr_mask.mask_tx_err = 1; hw->pfnWriteFPGARegister(hw->adp, INTR_INTR_MSK_CLR_REG, intr_mask.whole_reg); return; } void crystalhd_link_clear_errors(struct crystalhd_hw *hw) { uint32_t reg; /* Writing a 1 to a set bit clears that bit */ reg = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS); if (reg) hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS, reg); reg = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS); if (reg) hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS, reg); reg = hw->pfnReadFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS); if (reg) hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS, reg); } void crystalhd_link_clear_interrupts(struct crystalhd_hw *hw) { uint32_t intr_sts = hw->pfnReadFPGARegister(hw->adp, INTR_INTR_STATUS); if (intr_sts) { hw->pfnWriteFPGARegister(hw->adp, INTR_INTR_CLR_REG, intr_sts); /* Write End Of Interrupt for PCIE */ hw->pfnWriteFPGARegister(hw->adp, INTR_EOI_CTRL, 1); } } void crystalhd_link_soft_rst(struct crystalhd_hw *hw) { uint32_t val; /* Assert c011 soft reset*/ hw->pfnWriteDevRegister(hw->adp, DecHt_HostSwReset, 0x00000001); msleep_interruptible(50); /* Release c011 soft reset*/ hw->pfnWriteDevRegister(hw->adp, DecHt_HostSwReset, 0x00000000); /* Disable Stuffing..*/ val = hw->pfnReadFPGARegister(hw->adp, MISC2_GLOBAL_CTRL); val |= BC_BIT(8); hw->pfnWriteFPGARegister(hw->adp, MISC2_GLOBAL_CTRL, val); } bool crystalhd_link_load_firmware_config(struct crystalhd_hw *hw) { uint32_t i = 0, reg; hw->pfnWriteFPGARegister(hw->adp, DCI_DRAM_BASE_ADDR, (BC_DRAM_FW_CFG_ADDR >> 19)); hw->pfnWriteFPGARegister(hw->adp, AES_CMD, 0); hw->pfnWriteFPGARegister(hw->adp, AES_CONFIG_INFO, (BC_DRAM_FW_CFG_ADDR & 0x7FFFF)); hw->pfnWriteFPGARegister(hw->adp, AES_CMD, 0x1); for (i = 0; i < 100; ++i) { reg = hw->pfnReadFPGARegister(hw->adp, AES_STATUS); if (reg & 0x1) return true; msleep_interruptible(10); } return false; } bool crystalhd_link_start_device(struct crystalhd_hw *hw) { uint32_t dbg_options, glb_cntrl = 0, reg_pwrmgmt = 0; struct device *dev; if (!hw) return -EINVAL; dev = &hw->adp->pdev->dev; dev_dbg(dev, "Starting Crystal HD BCM70012 Device\n"); if (!crystalhd_link_bring_out_of_rst(hw)) { dev_err(dev, "Failed To Bring BCM70012 Out Of Reset\n"); return false; } crystalhd_link_disable_interrupts(hw); crystalhd_link_clear_errors(hw); crystalhd_link_clear_interrupts(hw); crystalhd_link_enable_interrupts(hw); /* Enable the option for getting the total no. of DWORDS * that have been transfered by the RXDMA engine */ dbg_options = hw->pfnReadFPGARegister(hw->adp, MISC1_DMA_DEBUG_OPTIONS_REG); dbg_options |= 0x10; hw->pfnWriteFPGARegister(hw->adp, MISC1_DMA_DEBUG_OPTIONS_REG, dbg_options); /* Enable PCI Global Control options */ glb_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC2_GLOBAL_CTRL); glb_cntrl |= 0x100; glb_cntrl |= 0x8000; hw->pfnWriteFPGARegister(hw->adp, MISC2_GLOBAL_CTRL, glb_cntrl); crystalhd_link_enable_interrupts(hw); crystalhd_link_soft_rst(hw); crystalhd_link_start_dram(hw); crystalhd_link_enable_uarts(hw); /* Disable L1 ASPM while video is playing as this causes performance problems otherwise */ reg_pwrmgmt = hw->pfnReadFPGARegister(hw->adp, PCIE_DLL_DATA_LINK_CONTROL); reg_pwrmgmt &= ~ASPM_L1_ENABLE; hw->pfnWriteFPGARegister(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, reg_pwrmgmt); return true; } bool crystalhd_link_stop_device(struct crystalhd_hw *hw) { uint32_t reg; BC_STATUS sts; dev_dbg(&hw->adp->pdev->dev, "Stopping Crystal HD BCM70012 Device\n"); sts = crystalhd_link_put_ddr2sleep(hw); if (sts != BC_STS_SUCCESS) { dev_err(&hw->adp->pdev->dev, "Failed to Put DDR To Sleep!!\n"); return BC_STS_ERROR; } /* Clear and disable interrupts */ crystalhd_link_disable_interrupts(hw); crystalhd_link_clear_errors(hw); crystalhd_link_clear_interrupts(hw); if (!crystalhd_link_put_in_reset(hw)) dev_err(&hw->adp->pdev->dev, "Failed to Put Link To Reset State\n"); reg = hw->pfnReadFPGARegister(hw->adp, PCIE_DLL_DATA_LINK_CONTROL); reg |= ASPM_L1_ENABLE; hw->pfnWriteFPGARegister(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, reg); /* Set PCI Clk Req */ reg = hw->pfnReadFPGARegister(hw->adp, PCIE_CLK_REQ_REG); reg |= PCI_CLK_REQ_ENABLE; hw->pfnWriteFPGARegister(hw->adp, PCIE_CLK_REQ_REG, reg); return true; } uint32_t link_GetPicInfoLineNum(struct crystalhd_dio_req *dio, uint8_t *base) { uint32_t PicInfoLineNum = 0; if (dio->uinfo.b422mode == MODE422_YUY2) { PicInfoLineNum = ((uint32_t)(*(base + 6)) & 0xff) | (((uint32_t)(*(base + 4)) << 8) & 0x0000ff00) | (((uint32_t)(*(base + 2)) << 16) & 0x00ff0000) | (((uint32_t)(*(base + 0)) << 24) & 0xff000000); } else if (dio->uinfo.b422mode == MODE422_UYVY) { PicInfoLineNum = ((uint32_t)(*(base + 7)) & 0xff) | (((uint32_t)(*(base + 5)) << 8) & 0x0000ff00) | (((uint32_t)(*(base + 3)) << 16) & 0x00ff0000) | (((uint32_t)(*(base + 1)) << 24) & 0xff000000); } else { PicInfoLineNum = ((uint32_t)(*(base + 3)) & 0xff) | (((uint32_t)(*(base + 2)) << 8) & 0x0000ff00) | (((uint32_t)(*(base + 1)) << 16) & 0x00ff0000) | (((uint32_t)(*(base + 0)) << 24) & 0xff000000); } return PicInfoLineNum; } uint32_t link_GetMode422Data(struct crystalhd_dio_req *dio, PBC_PIC_INFO_BLOCK pPicInfoLine, int type) { int i; uint32_t offset = 0, val = 0; uint8_t *tmp; tmp = (uint8_t *)&val; if (type == 1) offset = OFFSETOF(BC_PIC_INFO_BLOCK, picture_meta_payload); else if (type == 2) offset = OFFSETOF(BC_PIC_INFO_BLOCK, height); else offset = 0; if (dio->uinfo.b422mode == MODE422_YUY2) { for (i = 0; i < 4; i++) ((uint8_t*)tmp)[i] = ((uint8_t*)pPicInfoLine)[(offset + i) * 2]; } else if (dio->uinfo.b422mode == MODE422_UYVY) { for (i = 0; i < 4; i++) ((uint8_t*)tmp)[i] = ((uint8_t*)pPicInfoLine)[(offset + i) * 2 + 1]; } return val; } uint32_t link_GetMetaDataFromPib(struct crystalhd_dio_req *dio, PBC_PIC_INFO_BLOCK pPicInfoLine) { uint32_t picture_meta_payload = 0; if (dio->uinfo.b422mode) picture_meta_payload = link_GetMode422Data(dio, pPicInfoLine, 1); else picture_meta_payload = pPicInfoLine->picture_meta_payload; return BC_SWAP32(picture_meta_payload); } uint32_t link_GetHeightFromPib(struct crystalhd_dio_req *dio, PBC_PIC_INFO_BLOCK pPicInfoLine) { uint32_t height = 0; if (dio->uinfo.b422mode) height = link_GetMode422Data(dio, pPicInfoLine, 2); else height = pPicInfoLine->height; return BC_SWAP32(height); } /* This function cannot be called from ISR context since it uses APIs that can sleep */ bool link_GetPictureInfo(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, struct crystalhd_dio_req *dio, uint32_t *PicNumber, uint64_t *PicMetaData) { uint32_t PicInfoLineNum = 0, HeightInPib = 0, offset = 0, size = 0; PBC_PIC_INFO_BLOCK pPicInfoLine = NULL; uint32_t pic_number = 0; uint8_t *tmp = (uint8_t *)&pic_number; int i; unsigned long res = 0; dev_dbg(&hw->adp->pdev->dev, "getting Picture Info\n"); *PicNumber = 0; *PicMetaData = 0; if (!dio || !picWidth) goto getpictureinfo_err_nosem; /* if(down_interruptible(&hw->fetch_sem)) */ /* goto getpictureinfo_err_nosem; */ dio->pib_va = kmalloc(2 * sizeof(BC_PIC_INFO_BLOCK) + 16, GFP_KERNEL); /* since copy_from_user can sleep anyway */ if(dio->pib_va == NULL) goto getpictureinfo_err; res = copy_from_user(dio->pib_va, (void *)dio->uinfo.xfr_buff, 8); if (res != 0) goto getpictureinfo_err; /* * -- Ajitabh[01-16-2009]: Strictly check against done size. * -- we have seen that the done size sometimes comes less without * -- any error indicated to the driver. So we change the limit * -- to check against the done size rather than the full buffer size * -- this way we will always make sure that the PIB is recieved by * -- the driver. */ /* Limit = Base + pRxDMAReq->RxYDMADesc.RxBuffSz; */ /* Limit = Base + (pRxDMAReq->RxYDoneSzInDword * 4); */ /* Limit = dio->uinfo.xfr_buff + dio->uinfo.xfr_len; */ PicInfoLineNum = link_GetPicInfoLineNum(dio, dio->pib_va); if (PicInfoLineNum > 1092) { dev_dbg(&hw->adp->pdev->dev, "Invalid Line Number[%x]\n", (int)PicInfoLineNum); goto getpictureinfo_err; } /* * -- Ajitabh[01-16-2009]: Added the check for validating the * -- PicInfoLine Number. This function is only called for link so we * -- do not have to check for height+1 or (Height+1)/2 as we are doing * -- in DIL. In DIL we need that because for flea firmware is padding * -- the data to make it 16 byte aligned. This Validates the reception * -- of PIB itself. */ if (picHeight) { if ((PicInfoLineNum != picHeight) && (PicInfoLineNum != picHeight/2)) { dev_dbg(&hw->adp->pdev->dev, "PicInfoLineNum[%d] != PICHeight " "Or PICHeight/2 [%d]\n", (int)PicInfoLineNum, picHeight); goto getpictureinfo_err; } } /* calc pic info line offset */ if (dio->uinfo.b422mode) { size = 2 * sizeof(BC_PIC_INFO_BLOCK); offset = (PicInfoLineNum * picWidth * 2) + 8; } else { size = sizeof(BC_PIC_INFO_BLOCK); offset = (PicInfoLineNum * picWidth) + 4; } res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff+offset), size); if (res != 0) goto getpictureinfo_err; pPicInfoLine = (PBC_PIC_INFO_BLOCK)(dio->pib_va); /* if (((uint8_t *)pPicInfoLine < Base) || */ /* ((uint8_t *)pPicInfoLine > Limit)) { */ /* dev_err(dev, "Base Limit Check Failed for Extracting " */ /* "the PIB\n"); */ /* goto getpictureinfo_err; */ /* } */ /* * -- Ajitabh[01-16-2009]: * We have seen that the data gets shifted for some repeated frames. * To detect those we use PicInfoLineNum and compare it with height. */ HeightInPib = link_GetHeightFromPib(dio, pPicInfoLine); if ((PicInfoLineNum != HeightInPib) && (PicInfoLineNum != HeightInPib / 2)) { printk("Height Match Failed: HeightInPIB[%d] " "PicInfoLineNum[%d]\n", (int)HeightInPib, (int)PicInfoLineNum); goto getpictureinfo_err; } /* get pic meta data from pib */ *PicMetaData = link_GetMetaDataFromPib(dio, pPicInfoLine); /* get pic number from pib */ /* calc pic info line offset */ if (dio->uinfo.b422mode) offset = (PicInfoLineNum * picWidth * 2); else offset = (PicInfoLineNum * picWidth); res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff+offset), 12); if (res != 0) goto getpictureinfo_err; if (dio->uinfo.b422mode == MODE422_YUY2) { for (i = 0; i < 4; i++) ((uint8_t *)tmp)[i] = ((uint8_t *)dio->pib_va)[i * 2]; } else if (dio->uinfo.b422mode == MODE422_UYVY) { for (i = 0; i < 4; i++) ((uint8_t *)tmp)[i] = ((uint8_t *)dio->pib_va)[(i * 2) + 1]; } else pic_number = *(uint32_t *)(dio->pib_va); *PicNumber = BC_SWAP32(pic_number); if(dio->pib_va) kfree(dio->pib_va); /* up(&hw->fetch_sem); */ return true; getpictureinfo_err: /* up(&hw->fetch_sem); */ getpictureinfo_err_nosem: if(dio->pib_va) kfree(dio->pib_va); *PicNumber = 0; *PicMetaData = 0; return false; } uint32_t link_GetRptDropParam(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, void* pRxDMAReq) { uint32_t PicNumber = 0, result = 0; uint64_t PicMetaData = 0; if(link_GetPictureInfo(hw, picHeight, picWidth, ((struct crystalhd_rx_dma_pkt *)pRxDMAReq)->dio_req, &PicNumber, &PicMetaData)) result = PicNumber; return result; } /* * This function gets the next picture metadata payload * from the decoded picture in ReadyQ (if there was any) * and returns it. THIS IS ONLY USED FOR LINK. */ bool crystalhd_link_peek_next_decoded_frame(struct crystalhd_hw *hw, uint64_t *meta_payload, uint32_t *picNumFlags, uint32_t PicWidth) { uint32_t PicNumber = 0; unsigned long flags = 0; struct crystalhd_dioq *ioq; struct crystalhd_elem *tmp; struct crystalhd_rx_dma_pkt *rpkt; *meta_payload = 0; ioq = hw->rx_rdyq; spin_lock_irqsave(&ioq->lock, flags); if ((ioq->count > 0) && (ioq->head != (struct crystalhd_elem *)&ioq->head)) { tmp = ioq->head; spin_unlock_irqrestore(&ioq->lock, flags); rpkt = (struct crystalhd_rx_dma_pkt *)tmp->data; if (rpkt) { /* We are in process context here and have to check if we have repeated pictures */ /* Drop repeated pictures or garbabge pictures here */ /* This is because if we advertize a valid picture here, but later drop it */ /* It will cause single threaded applications to hang, or errors in applications that expect */ /* pictures not to be dropped once we have advertized their availability */ /* If format change packet, then return with out checking anything */ if (!(rpkt->flags & (COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE))) { link_GetPictureInfo(hw, hw->PICHeight, hw->PICWidth, rpkt->dio_req, &PicNumber, meta_payload); if(!PicNumber || (PicNumber == hw->LastPicNo) || (PicNumber == hw->LastTwoPicNo)) { /* discard picture */ if(PicNumber != 0) { hw->LastTwoPicNo = hw->LastPicNo; hw->LastPicNo = PicNumber; } rpkt = crystalhd_dioq_fetch(hw->rx_rdyq); if (rpkt) { crystalhd_dioq_add(hw->rx_freeq, rpkt, false, rpkt->pkt_tag); rpkt = NULL; } *meta_payload = 0; } return true; /* Do not update the picture numbers here since they will be updated on the actual fetch of a valid picture */ } else return false; /* don't use the meta_payload information */ } else return false; } spin_unlock_irqrestore(&ioq->lock, flags); return false; } bool crystalhd_link_check_input_full(struct crystalhd_hw *hw, uint32_t needed_sz, uint32_t *empty_sz, bool b_188_byte_pkts, uint8_t *flags) { uint32_t base, end, writep, readp; uint32_t cpbSize, cpbFullness, fifoSize; if (*flags & 0x02) { /* ASF Bit is set */ base = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsAudCDB2Base); end = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsAudCDB2End); writep = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsAudCDB2Wrptr); readp = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsAudCDB2Rdptr); } else if (b_188_byte_pkts) { /*Encrypted 188 byte packets*/ base = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsUser0Base); end = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsUser0End); writep = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsUser0Wrptr); readp = hw->pfnReadDevRegister(hw->adp, REG_Dec_TsUser0Rdptr); } else { base = hw->pfnReadDevRegister(hw->adp, REG_DecCA_RegCinBase); end = hw->pfnReadDevRegister(hw->adp, REG_DecCA_RegCinEnd); writep = hw->pfnReadDevRegister(hw->adp, REG_DecCA_RegCinWrPtr); readp = hw->pfnReadDevRegister(hw->adp, REG_DecCA_RegCinRdPtr); } cpbSize = end - base; if (writep >= readp) cpbFullness = writep - readp; else cpbFullness = (end - base) - (readp - writep); fifoSize = cpbSize - cpbFullness; if (fifoSize < BC_INFIFO_THRESHOLD) { *empty_sz = 0; return true; } if (needed_sz > (fifoSize - BC_INFIFO_THRESHOLD)) { *empty_sz = 0; return true; } *empty_sz = fifoSize - BC_INFIFO_THRESHOLD; return false; } bool crystalhd_link_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts) { uint32_t err_mask, tmp; err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK | MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK | MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; if (!(err_sts & err_mask)) return false; dev_err(&hw->adp->pdev->dev, "Error on Tx-L0 %x\n", err_sts); tmp = err_mask; if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK) tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; if (tmp) { /* reset list index.*/ hw->tx_list_post_index = 0; } tmp = err_sts & err_mask; hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp); return true; } bool crystalhd_link_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts) { uint32_t err_mask, tmp; err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK | MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK | MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; if (!(err_sts & err_mask)) return false; dev_err(&hw->adp->pdev->dev, "Error on Tx-L1 %x\n", err_sts); tmp = err_mask; if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK) tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; if (tmp) { /* reset list index.*/ hw->tx_list_post_index = 0; } tmp = err_sts & err_mask; hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS, tmp); return true; } void crystalhd_link_tx_isr(struct crystalhd_hw *hw, uint32_t int_sts) { uint32_t err_sts; if (int_sts & INTR_INTR_STATUS_L0_TX_DMA_DONE_INTR_MASK) crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, BC_STS_SUCCESS); if (int_sts & INTR_INTR_STATUS_L1_TX_DMA_DONE_INTR_MASK) crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, BC_STS_SUCCESS); if (!(int_sts & (INTR_INTR_STATUS_L0_TX_DMA_ERR_INTR_MASK | INTR_INTR_STATUS_L1_TX_DMA_ERR_INTR_MASK))) /* No error mask set.. */ return; /* Handle Tx errors. */ err_sts = hw->pfnReadFPGARegister(hw->adp, MISC1_TX_DMA_ERROR_STATUS); if (crystalhd_link_tx_list0_handler(hw, err_sts)) crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, BC_STS_ERROR); if (crystalhd_link_tx_list1_handler(hw, err_sts)) crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, BC_STS_ERROR); hw->stats.tx_errors++; } void crystalhd_link_start_tx_dma_engine(struct crystalhd_hw *hw, uint8_t list_id, addr_64 desc_addr) { uint32_t dma_cntrl; uint32_t first_desc_u_addr, first_desc_l_addr; if (list_id == 0) { first_desc_u_addr = MISC1_TX_FIRST_DESC_U_ADDR_LIST0; first_desc_l_addr = MISC1_TX_FIRST_DESC_L_ADDR_LIST0; } else { first_desc_u_addr = MISC1_TX_FIRST_DESC_U_ADDR_LIST1; first_desc_l_addr = MISC1_TX_FIRST_DESC_L_ADDR_LIST1; } dma_cntrl = hw->pfnReadFPGARegister(hw->adp,MISC1_TX_SW_DESC_LIST_CTRL_STS); if (!(dma_cntrl & DMA_START_BIT)) { dma_cntrl |= DMA_START_BIT; hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS, dma_cntrl); } hw->pfnWriteFPGARegister(hw->adp, first_desc_u_addr, desc_addr.high_part); hw->pfnWriteFPGARegister(hw->adp, first_desc_l_addr, desc_addr.low_part | 0x01); /* Be sure we set the valid bit ^^^^ */ return; } /* _CHECK_THIS_ * * Verify if the Stop generates a completion interrupt or not. * if it does not generate an interrupt, then add polling here. */ BC_STATUS crystalhd_link_stop_tx_dma_engine(struct crystalhd_hw *hw) { struct device *dev; uint32_t dma_cntrl, cnt = 30; uint32_t l1 = 1, l2 = 1; dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS); dev = &hw->adp->pdev->dev; dev_dbg(dev, "Stopping TX DMA Engine..\n"); if (!(dma_cntrl & DMA_START_BIT)) { hw->tx_list_post_index = 0; dev_dbg(dev, "Already Stopped\n"); return BC_STS_SUCCESS; } crystalhd_link_disable_interrupts(hw); /* Issue stop to HW */ dma_cntrl &= ~DMA_START_BIT; hw->pfnWriteFPGARegister(hw->adp, MISC1_TX_SW_DESC_LIST_CTRL_STS, dma_cntrl); dev_dbg(dev, "Cleared the DMA Start bit\n"); /* Poll for 3seconds (30 * 100ms) on both the lists..*/ while ((l1 || l2) && cnt) { if (l1) { l1 = hw->pfnReadFPGARegister(hw->adp, MISC1_TX_FIRST_DESC_L_ADDR_LIST0); l1 &= DMA_START_BIT; } if (l2) { l2 = hw->pfnReadFPGARegister(hw->adp, MISC1_TX_FIRST_DESC_L_ADDR_LIST1); l2 &= DMA_START_BIT; } msleep_interruptible(100); cnt--; } if (!cnt) { dev_err(dev, "Failed to stop TX DMA.. l1 %d, l2 %d\n", l1, l2); crystalhd_link_enable_interrupts(hw); return BC_STS_ERROR; } hw->tx_list_post_index = 0; dev_dbg(dev, "stopped TX DMA..\n"); crystalhd_link_enable_interrupts(hw); return BC_STS_SUCCESS; } uint32_t crystalhd_link_get_pib_avail_cnt(struct crystalhd_hw *hw) { /* * Position of the PIB Entries can be found at * 0th and the 1st location of the Circular list. */ uint32_t Q_addr; uint32_t pib_cnt, r_offset, w_offset; Q_addr = hw->pib_del_Q_addr; /* Get the Read Pointer */ crystalhd_link_mem_rd(hw, Q_addr, 1, &r_offset); /* Get the Write Pointer */ crystalhd_link_mem_rd(hw, Q_addr + sizeof(uint32_t), 1, &w_offset); if (r_offset == w_offset) return 0; /* Queue is empty */ if (w_offset > r_offset) pib_cnt = w_offset - r_offset; else pib_cnt = (w_offset + MAX_PIB_Q_DEPTH) - (r_offset + MIN_PIB_Q_DEPTH); if (pib_cnt > MAX_PIB_Q_DEPTH) { dev_err(&hw->adp->pdev->dev, "Invalid PIB Count (%u)\n", pib_cnt); return 0; } return pib_cnt; } uint32_t crystalhd_link_get_addr_from_pib_Q(struct crystalhd_hw *hw) { uint32_t Q_addr; uint32_t addr_entry, r_offset, w_offset; Q_addr = hw->pib_del_Q_addr; /* Get the Read Pointer 0Th Location is Read Pointer */ crystalhd_link_mem_rd(hw, Q_addr, 1, &r_offset); /* Get the Write Pointer 1st Location is Write pointer */ crystalhd_link_mem_rd(hw, Q_addr + sizeof(uint32_t), 1, &w_offset); /* Queue is empty */ if (r_offset == w_offset) return 0; if ((r_offset < MIN_PIB_Q_DEPTH) || (r_offset >= MAX_PIB_Q_DEPTH)) return 0; /* Get the Actual Address of the PIB */ crystalhd_link_mem_rd(hw, Q_addr + (r_offset * sizeof(uint32_t)), 1, &addr_entry); /* Increment the Read Pointer */ r_offset++; if (MAX_PIB_Q_DEPTH == r_offset) r_offset = MIN_PIB_Q_DEPTH; /* Write back the read pointer to It's Location */ crystalhd_link_mem_wr(hw, Q_addr, 1, &r_offset); return addr_entry; } bool crystalhd_link_rel_addr_to_pib_Q(struct crystalhd_hw *hw, uint32_t addr_to_rel) { uint32_t Q_addr; uint32_t r_offset, w_offset, n_offset; Q_addr = hw->pib_rel_Q_addr; /* Get the Read Pointer */ crystalhd_link_mem_rd(hw, Q_addr, 1, &r_offset); /* Get the Write Pointer */ crystalhd_link_mem_rd(hw, Q_addr + sizeof(uint32_t), 1, &w_offset); if ((r_offset < MIN_PIB_Q_DEPTH) || (r_offset >= MAX_PIB_Q_DEPTH)) return false; n_offset = w_offset + 1; if (MAX_PIB_Q_DEPTH == n_offset) n_offset = MIN_PIB_Q_DEPTH; if (r_offset == n_offset) return false; /* should never happen */ /* Write the DRAM ADDR to the Queue at Next Offset */ crystalhd_link_mem_wr(hw, Q_addr + (w_offset * sizeof(uint32_t)), 1, &addr_to_rel); /* Put the New value of the write pointer in Queue */ crystalhd_link_mem_wr(hw, Q_addr + sizeof(uint32_t), 1, &n_offset); return true; } void link_cpy_pib_to_app(struct C011_PIB *src_pib, BC_PIC_INFO_BLOCK *dst_pib) { if (!src_pib || !dst_pib) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return; } dst_pib->timeStamp = 0; dst_pib->picture_number = src_pib->ppb.picture_number; dst_pib->width = src_pib->ppb.width; dst_pib->height = src_pib->ppb.height; dst_pib->chroma_format = src_pib->ppb.chroma_format; dst_pib->pulldown = src_pib->ppb.pulldown; dst_pib->flags = src_pib->ppb.flags; dst_pib->sess_num = src_pib->ptsStcOffset; dst_pib->aspect_ratio = src_pib->ppb.aspect_ratio; dst_pib->colour_primaries = src_pib->ppb.colour_primaries; dst_pib->picture_meta_payload = src_pib->ppb.picture_meta_payload; dst_pib->frame_rate = src_pib->resolution ; return; } void crystalhd_link_proc_pib(struct crystalhd_hw *hw) { unsigned int cnt; struct C011_PIB src_pib; uint32_t pib_addr, pib_cnt; BC_PIC_INFO_BLOCK *AppPib; struct crystalhd_rx_dma_pkt *rx_pkt = NULL; pib_cnt = crystalhd_link_get_pib_avail_cnt(hw); if (!pib_cnt) return; for (cnt = 0; cnt < pib_cnt; cnt++) { pib_addr = crystalhd_link_get_addr_from_pib_Q(hw); crystalhd_link_mem_rd(hw, pib_addr, sizeof(struct C011_PIB) / 4, (uint32_t *)&src_pib); if (src_pib.bFormatChange) { rx_pkt = (struct crystalhd_rx_dma_pkt *) crystalhd_dioq_fetch(hw->rx_freeq); if (!rx_pkt) return; rx_pkt->flags = 0; rx_pkt->flags |= COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE; AppPib = &rx_pkt->pib; link_cpy_pib_to_app(&src_pib, AppPib); hw->PICHeight = rx_pkt->pib.height; if (rx_pkt->pib.width > 1280) hw->PICWidth = 1920; else if (rx_pkt->pib.width > 720) hw->PICWidth = 1280; else hw->PICWidth = 720; dev_info(&hw->adp->pdev->dev, "[FMT CH] PIB:%x %x %x %x %x %x %x %x %x %x\n", rx_pkt->pib.picture_number, rx_pkt->pib.aspect_ratio, rx_pkt->pib.chroma_format, rx_pkt->pib.colour_primaries, rx_pkt->pib.frame_rate, rx_pkt->pib.height, rx_pkt->pib.width, rx_pkt->pib.n_drop, rx_pkt->pib.pulldown, rx_pkt->pib.ycom); crystalhd_dioq_add(hw->rx_rdyq, (void *)rx_pkt, true, rx_pkt->pkt_tag); } crystalhd_link_rel_addr_to_pib_Q(hw, pib_addr); } } void crystalhd_link_start_rx_dma_engine(struct crystalhd_hw *hw) { uint32_t dma_cntrl; dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); if (!(dma_cntrl & DMA_START_BIT)) { dma_cntrl |= DMA_START_BIT; hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); } dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); if (!(dma_cntrl & DMA_START_BIT)) { dma_cntrl |= DMA_START_BIT; hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); } return; } void crystalhd_link_stop_rx_dma_engine(struct crystalhd_hw *hw) { struct device *dev = &hw->adp->pdev->dev; uint32_t dma_cntrl = 0, count = 30; uint32_t l0y = 1, l0uv = 1, l1y = 1, l1uv = 1; dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); if ((dma_cntrl & DMA_START_BIT)) { dma_cntrl &= ~DMA_START_BIT; hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); } dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); if ((dma_cntrl & DMA_START_BIT)) { dma_cntrl &= ~DMA_START_BIT; hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); } /* Poll for 3seconds (30 * 100ms) on both the lists..*/ while ((l0y || l0uv || l1y || l1uv) && count) { if (l0y) { l0y = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0); l0y &= DMA_START_BIT; if (!l0y) hw->rx_list_sts[0] &= ~rx_waiting_y_intr; } if (l1y) { l1y = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1); l1y &= DMA_START_BIT; if (!l1y) hw->rx_list_sts[1] &= ~rx_waiting_y_intr; } if (l0uv) { l0uv = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0); l0uv &= DMA_START_BIT; if (!l0uv) hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; } if (l1uv) { l1uv = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1); l1uv &= DMA_START_BIT; if (!l1uv) hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; } msleep_interruptible(100); count--; } hw->rx_list_post_index = 0; dev_dbg(dev, "Capture Stop: %d List0:Sts:%x List1:Sts:%x\n", count, hw->rx_list_sts[0], hw->rx_list_sts[1]); } BC_STATUS crystalhd_link_hw_prog_rxdma(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *rx_pkt) { struct device *dev; uint32_t y_low_addr_reg, y_high_addr_reg; uint32_t uv_low_addr_reg, uv_high_addr_reg; addr_64 desc_addr; unsigned long flags; if (!hw || !rx_pkt) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } dev = &hw->adp->pdev->dev; if (hw->rx_list_post_index >= DMA_ENGINE_CNT) { dev_err(dev, "List Out Of bounds %x\n", hw->rx_list_post_index); return BC_STS_INV_ARG; } spin_lock_irqsave(&hw->rx_lock, flags); if (hw->rx_list_sts[hw->rx_list_post_index]) { spin_unlock_irqrestore(&hw->rx_lock, flags); return BC_STS_BUSY; } if (!hw->rx_list_post_index) { y_low_addr_reg = MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST0; y_high_addr_reg = MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST0; uv_low_addr_reg = MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST0; uv_high_addr_reg = MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST0; } else { y_low_addr_reg = MISC1_Y_RX_FIRST_DESC_L_ADDR_LIST1; y_high_addr_reg = MISC1_Y_RX_FIRST_DESC_U_ADDR_LIST1; uv_low_addr_reg = MISC1_UV_RX_FIRST_DESC_L_ADDR_LIST1; uv_high_addr_reg = MISC1_UV_RX_FIRST_DESC_U_ADDR_LIST1; } rx_pkt->pkt_tag = hw->rx_pkt_tag_seed + hw->rx_list_post_index; hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_y_intr; if (rx_pkt->uv_phy_addr) hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_uv_intr; hw->rx_list_post_index = (hw->rx_list_post_index + 1) % DMA_ENGINE_CNT; crystalhd_dioq_add(hw->rx_actq, (void *)rx_pkt, false, rx_pkt->pkt_tag); crystalhd_link_start_rx_dma_engine(hw); /* Program the Y descriptor */ desc_addr.full_addr = rx_pkt->desc_mem.phy_addr; hw->pfnWriteFPGARegister(hw->adp, y_high_addr_reg, desc_addr.high_part); hw->pfnWriteFPGARegister(hw->adp, y_low_addr_reg, desc_addr.low_part | 0x01); if (rx_pkt->uv_phy_addr) { /* Program the UV descriptor */ desc_addr.full_addr = rx_pkt->uv_phy_addr; hw->pfnWriteFPGARegister(hw->adp, uv_high_addr_reg, desc_addr.high_part); hw->pfnWriteFPGARegister(hw->adp, uv_low_addr_reg, desc_addr.low_part | 0x01); } spin_unlock_irqrestore(&hw->rx_lock, flags); return BC_STS_SUCCESS; } BC_STATUS crystalhd_link_hw_post_cap_buff(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *rx_pkt) { BC_STATUS sts = crystalhd_link_hw_prog_rxdma(hw, rx_pkt); if (sts == BC_STS_BUSY) crystalhd_dioq_add(hw->rx_freeq, (void *)rx_pkt, false, rx_pkt->pkt_tag); return sts; } void crystalhd_link_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index, uint32_t *y_dw_dnsz, uint32_t *uv_dw_dnsz) { uint32_t y_dn_sz_reg, uv_dn_sz_reg; if (!list_index) { y_dn_sz_reg = MISC1_Y_RX_LIST0_CUR_BYTE_CNT; uv_dn_sz_reg = MISC1_UV_RX_LIST0_CUR_BYTE_CNT; } else { y_dn_sz_reg = MISC1_Y_RX_LIST1_CUR_BYTE_CNT; uv_dn_sz_reg = MISC1_UV_RX_LIST1_CUR_BYTE_CNT; } *y_dw_dnsz = hw->pfnReadFPGARegister(hw->adp, y_dn_sz_reg); *uv_dw_dnsz = hw->pfnReadFPGARegister(hw->adp, uv_dn_sz_reg); } /* * This function should be called only after making sure that the two DMA * lists are free. This function does not check if DMA's are active, before * turning off the DMA. */ void crystalhd_link_hw_finalize_pause(struct crystalhd_hw *hw) { uint32_t dma_cntrl; hw->stop_pending = 0; dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS); if (dma_cntrl & DMA_START_BIT) { dma_cntrl &= ~DMA_START_BIT; hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); } dma_cntrl = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS); if (dma_cntrl & DMA_START_BIT) { dma_cntrl &= ~DMA_START_BIT; hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_SW_DESC_LIST_CTRL_STS, dma_cntrl); } hw->rx_list_post_index = 0; /* aspm = crystalhd_reg_rd(hw->adp, PCIE_DLL_DATA_LINK_CONTROL); */ /* aspm |= ASPM_L1_ENABLE; */ /* dev_info(&hw->adp->pdev->dev, "aspm on\n"); */ /* crystalhd_reg_wr(hw->adp, PCIE_DLL_DATA_LINK_CONTROL, aspm); */ } bool crystalhd_link_rx_list0_handler(struct crystalhd_hw *hw, uint32_t int_sts, uint32_t y_err_sts, uint32_t uv_err_sts) { uint32_t tmp; enum list_sts tmp_lsts; if (!(y_err_sts & GET_Y0_ERR_MSK) && !(uv_err_sts & GET_UV0_ERR_MSK)) return false; tmp_lsts = hw->rx_list_sts[0]; /* Y0 - DMA */ tmp = y_err_sts & GET_Y0_ERR_MSK; if (int_sts & INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK) hw->rx_list_sts[0] &= ~rx_waiting_y_intr; if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { hw->rx_list_sts[0] &= ~rx_waiting_y_intr; tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; } if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { hw->rx_list_sts[0] &= ~rx_y_mask; hw->rx_list_sts[0] |= rx_y_error; tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; } if (tmp) { hw->rx_list_sts[0] &= ~rx_y_mask; hw->rx_list_sts[0] |= rx_y_error; hw->rx_list_post_index = 0; } /* UV0 - DMA */ tmp = uv_err_sts & GET_UV0_ERR_MSK; if (int_sts & INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK) hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; } if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { hw->rx_list_sts[0] &= ~rx_uv_mask; hw->rx_list_sts[0] |= rx_uv_error; tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; } if (tmp) { hw->rx_list_sts[0] &= ~rx_uv_mask; hw->rx_list_sts[0] |= rx_uv_error; hw->rx_list_post_index = 0; } if (y_err_sts & GET_Y0_ERR_MSK) { tmp = y_err_sts & GET_Y0_ERR_MSK; hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp); } if (uv_err_sts & GET_UV0_ERR_MSK) { tmp = uv_err_sts & GET_UV0_ERR_MSK; hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp); } return (tmp_lsts != hw->rx_list_sts[0]); } bool crystalhd_link_rx_list1_handler(struct crystalhd_hw *hw, uint32_t int_sts, uint32_t y_err_sts, uint32_t uv_err_sts) { uint32_t tmp; enum list_sts tmp_lsts; if (!(y_err_sts & GET_Y1_ERR_MSK) && !(uv_err_sts & GET_UV1_ERR_MSK)) return false; tmp_lsts = hw->rx_list_sts[1]; /* Y1 - DMA */ tmp = y_err_sts & GET_Y1_ERR_MSK; if (int_sts & INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK) hw->rx_list_sts[1] &= ~rx_waiting_y_intr; if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { hw->rx_list_sts[1] &= ~rx_waiting_y_intr; tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; } if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { /* Add retry-support..*/ hw->rx_list_sts[1] &= ~rx_y_mask; hw->rx_list_sts[1] |= rx_y_error; tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; } if (tmp) { hw->rx_list_sts[1] &= ~rx_y_mask; hw->rx_list_sts[1] |= rx_y_error; hw->rx_list_post_index = 0; } /* UV1 - DMA */ tmp = uv_err_sts & GET_UV1_ERR_MSK; if (int_sts & INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK) hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; } if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { /* Add retry-support*/ hw->rx_list_sts[1] &= ~rx_uv_mask; hw->rx_list_sts[1] |= rx_uv_error; tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; } if (tmp) { hw->rx_list_sts[1] &= ~rx_uv_mask; hw->rx_list_sts[1] |= rx_uv_error; hw->rx_list_post_index = 0; } if (y_err_sts & GET_Y1_ERR_MSK) { tmp = y_err_sts & GET_Y1_ERR_MSK; hw->pfnWriteFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS, tmp); } if (uv_err_sts & GET_UV1_ERR_MSK) { tmp = uv_err_sts & GET_UV1_ERR_MSK; hw->pfnWriteFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS, tmp); } return (tmp_lsts != hw->rx_list_sts[1]); } void crystalhd_link_rx_isr(struct crystalhd_hw *hw, uint32_t intr_sts) { unsigned long flags; uint32_t i, list_avail = 0; BC_STATUS comp_sts = BC_STS_NO_DATA; uint32_t y_err_sts, uv_err_sts, y_dn_sz = 0, uv_dn_sz = 0; bool ret = 0; if (!hw) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return; } if (!(intr_sts & GET_RX_INTR_MASK)) return; y_err_sts = hw->pfnReadFPGARegister(hw->adp, MISC1_Y_RX_ERROR_STATUS); uv_err_sts = hw->pfnReadFPGARegister(hw->adp, MISC1_UV_RX_ERROR_STATUS); for (i = 0; i < DMA_ENGINE_CNT; i++) { /* Update States..*/ spin_lock_irqsave(&hw->rx_lock, flags); if (i == 0) ret = crystalhd_link_rx_list0_handler(hw, intr_sts, y_err_sts, uv_err_sts); else ret = crystalhd_link_rx_list1_handler(hw, intr_sts, y_err_sts, uv_err_sts); if (ret) { switch (hw->rx_list_sts[i]) { case sts_free: comp_sts = BC_STS_SUCCESS; list_avail = 1; hw->stats.rx_success++; break; case rx_y_error: case rx_uv_error: case rx_sts_error: /* We got error on both or Y or uv. */ hw->stats.rx_errors++; hw->pfnHWGetDoneSize(hw, i, &y_dn_sz, &uv_dn_sz); dev_info(&hw->adp->pdev->dev, "list_index:%x " "rx[%d] rxtot[%d] Y:%x UV:%x Int:%x YDnSz:%x " "UVDnSz:%x\n", i, hw->stats.rx_errors, hw->stats.rx_errors + hw->stats.rx_success, y_err_sts, uv_err_sts, intr_sts, y_dn_sz, uv_dn_sz); hw->rx_list_sts[i] = sts_free; comp_sts = BC_STS_ERROR; break; default: /* Wait for completion..*/ comp_sts = BC_STS_NO_DATA; break; } } spin_unlock_irqrestore(&hw->rx_lock, flags); /* handle completion...*/ if (comp_sts != BC_STS_NO_DATA) { crystalhd_rx_pkt_done(hw, i, comp_sts); comp_sts = BC_STS_NO_DATA; } } if (list_avail) { if (hw->stop_pending) { if ((hw->rx_list_sts[0] == sts_free) && (hw->rx_list_sts[1] == sts_free)) crystalhd_link_hw_finalize_pause(hw); } else { if(!hw->hw_pause_issued) crystalhd_hw_start_capture(hw); } } } BC_STATUS crystalhd_link_hw_pause(struct crystalhd_hw *hw, bool state) { uint32_t pause = 0; BC_STATUS sts = BC_STS_SUCCESS; if(state) { pause = 1; hw->stats.pause_cnt++; hw->stop_pending = 1; hw->pfnWriteDevRegister(hw->adp, HW_PauseMbx, pause); if ((hw->rx_list_sts[0] == sts_free) && (hw->rx_list_sts[1] == sts_free)) crystalhd_link_hw_finalize_pause(hw); } else { pause = 0; hw->stop_pending = 0; sts = crystalhd_hw_start_capture(hw); hw->pfnWriteDevRegister(hw->adp, HW_PauseMbx, pause); } return sts; } BC_STATUS crystalhd_link_fw_cmd_post_proc(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd) { BC_STATUS sts = BC_STS_SUCCESS; struct DecRspChannelStartVideo *st_rsp = NULL; switch (fw_cmd->cmd[0]) { case eCMD_C011_DEC_CHAN_START_VIDEO: st_rsp = (struct DecRspChannelStartVideo *)fw_cmd->rsp; hw->pib_del_Q_addr = st_rsp->picInfoDeliveryQ; hw->pib_rel_Q_addr = st_rsp->picInfoReleaseQ; dev_dbg(&hw->adp->pdev->dev, "DelQAddr:%x RelQAddr:%x\n", hw->pib_del_Q_addr, hw->pib_rel_Q_addr); break; case eCMD_C011_INIT: if (!(crystalhd_link_load_firmware_config(hw))) { dev_err(&hw->adp->pdev->dev, "Invalid Params\n"); sts = BC_STS_FW_AUTH_FAILED; } break; default: break; } return sts; } BC_STATUS crystalhd_link_put_ddr2sleep(struct crystalhd_hw *hw) { uint32_t reg; union link_misc_perst_decoder_ctrl rst_cntrl_reg; /* Pulse reset pin of 7412 (MISC_PERST_DECODER_CTRL) */ rst_cntrl_reg.whole_reg = hw->pfnReadDevRegister(hw->adp, MISC_PERST_DECODER_CTRL); rst_cntrl_reg.bcm_7412_rst = 1; hw->pfnWriteDevRegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg); msleep_interruptible(50); rst_cntrl_reg.bcm_7412_rst = 0; hw->pfnWriteDevRegister(hw->adp, MISC_PERST_DECODER_CTRL, rst_cntrl_reg.whole_reg); /* Close all banks, put DDR in idle */ hw->pfnWriteDevRegister(hw->adp, SDRAM_PRECHARGE, 0); /* Set bit 25 (drop CKE pin of DDR) */ reg = hw->pfnReadDevRegister(hw->adp, SDRAM_PARAM); reg |= 0x02000000; hw->pfnWriteDevRegister(hw->adp, SDRAM_PARAM, reg); /* Reset the audio block */ hw->pfnWriteDevRegister(hw->adp, AUD_DSP_MISC_SOFT_RESET, 0x1); /* Power down Raptor PLL */ reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllCCtl); reg |= 0x00008000; hw->pfnWriteDevRegister(hw->adp, DecHt_PllCCtl, reg); /* Power down all Audio PLL */ hw->pfnWriteDevRegister(hw->adp, AIO_MISC_PLL_RESET, 0x1); /* Power down video clock (75MHz) */ reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllECtl); reg |= 0x00008000; hw->pfnWriteDevRegister(hw->adp, DecHt_PllECtl, reg); /* Power down video clock (75MHz) */ reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllDCtl); reg |= 0x00008000; hw->pfnWriteDevRegister(hw->adp, DecHt_PllDCtl, reg); /* Power down core clock (200MHz) */ reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllACtl); reg |= 0x00008000; hw->pfnWriteDevRegister(hw->adp, DecHt_PllACtl, reg); /* Power down core clock (200MHz) */ reg = hw->pfnReadDevRegister(hw->adp, DecHt_PllBCtl); reg |= 0x00008000; hw->pfnWriteDevRegister(hw->adp, DecHt_PllBCtl, reg); return BC_STS_SUCCESS; } /************************************************ ** *************************************************/ BC_STATUS crystalhd_link_download_fw(struct crystalhd_hw *hw, uint8_t *buffer, uint32_t sz) { struct device *dev; uint32_t reg_data, cnt, *temp_buff; uint32_t fw_sig_len = 36; uint32_t dram_offset = BC_FWIMG_ST_ADDR, sig_reg; if (!hw || !buffer || !sz) { printk(KERN_ERR "%s: Invalid Params\n", __func__); return BC_STS_INV_ARG; } dev = &hw->adp->pdev->dev; dev_dbg(dev, "%s entered\n", __func__); reg_data = hw->pfnReadFPGARegister(hw->adp, OTP_CMD); if (!(reg_data & 0x02)) { dev_err(dev, "Invalid hw config.. otp not programmed\n"); return BC_STS_ERROR; } reg_data = 0; hw->pfnWriteFPGARegister(hw->adp, DCI_CMD, 0); reg_data |= BC_BIT(0); hw->pfnWriteFPGARegister(hw->adp, DCI_CMD, reg_data); reg_data = 0; cnt = 1000; msleep_interruptible(10); while (reg_data != BC_BIT(4)) { reg_data = hw->pfnReadFPGARegister(hw->adp, DCI_STATUS); reg_data &= BC_BIT(4); if (--cnt == 0) { dev_err(dev, "Firmware Download RDY Timeout.\n"); return BC_STS_TIMEOUT; } } msleep_interruptible(10); /* Load the FW to the FW_ADDR field in the DCI_FIRMWARE_ADDR */ hw->pfnWriteFPGARegister(hw->adp, DCI_FIRMWARE_ADDR, dram_offset); temp_buff = (uint32_t *)buffer; for (cnt = 0; cnt < (sz - fw_sig_len); cnt += 4) { hw->pfnWriteFPGARegister(hw->adp, DCI_DRAM_BASE_ADDR, (dram_offset >> 19)); hw->pfnWriteFPGARegister(hw->adp, DCI_FIRMWARE_DATA, *temp_buff); dram_offset += 4; temp_buff++; } msleep_interruptible(10); temp_buff++; sig_reg = (uint32_t)DCI_SIGNATURE_DATA_7; for (cnt = 0; cnt < 8; cnt++) { uint32_t swapped_data = *temp_buff; swapped_data = cpu_to_be32(swapped_data); hw->pfnWriteFPGARegister(hw->adp, sig_reg, swapped_data); sig_reg -= 4; temp_buff++; } msleep_interruptible(10); reg_data = 0; reg_data |= BC_BIT(1); hw->pfnWriteFPGARegister(hw->adp, DCI_CMD, reg_data); msleep_interruptible(10); reg_data = 0; reg_data = hw->pfnReadFPGARegister(hw->adp, DCI_STATUS); if ((reg_data & BC_BIT(9)) == BC_BIT(9)) { cnt = 1000; while ((reg_data & BC_BIT(0)) != BC_BIT(0)) { reg_data = hw->pfnReadFPGARegister(hw->adp, DCI_STATUS); reg_data &= BC_BIT(0); if (!(--cnt)) break; msleep_interruptible(10); } reg_data = 0; reg_data = hw->pfnReadFPGARegister(hw->adp, DCI_CMD); reg_data |= BC_BIT(4); hw->pfnWriteFPGARegister(hw->adp, DCI_CMD, reg_data); } else { dev_err(dev, "F/w Signature mismatch\n"); return BC_STS_FW_AUTH_FAILED; } dev_dbg(dev, "Firmware Downloaded Successfully\n"); /* Load command response addresses */ hw->fwcmdPostAddr = TS_Host2CpuSnd; hw->fwcmdPostMbox = Hst2CpuMbx1; hw->fwcmdRespMbox = Cpu2HstMbx1; return BC_STS_SUCCESS;; } BC_STATUS crystalhd_link_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd) { struct device *dev; uint32_t cnt = 0, cmd_res_addr; uint32_t *cmd_buff, *res_buff; wait_queue_head_t fw_cmd_event; int rc = 0; BC_STATUS sts; unsigned long flags; crystalhd_create_event(&fw_cmd_event); if (!hw || !fw_cmd) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } dev = &hw->adp->pdev->dev; dev_dbg(dev, "%s entered\n", __func__); cmd_buff = fw_cmd->cmd; res_buff = fw_cmd->rsp; if (!cmd_buff || !res_buff) { dev_err(dev, "Invalid Parameters for F/W Command\n"); return BC_STS_INV_ARG; } hw->fwcmd_evt_sts = 0; hw->pfw_cmd_event = &fw_cmd_event; spin_lock_irqsave(&hw->lock, flags); /*Write the command to the memory*/ hw->pfnDevDRAMWrite(hw, hw->fwcmdPostAddr, FW_CMD_BUFF_SZ, cmd_buff); /*Memory Read for memory arbitrator flush*/ hw->pfnDevDRAMRead(hw, hw->fwcmdPostAddr, 1, &cnt); /* Write the command address to mailbox */ hw->pfnWriteDevRegister(hw->adp, hw->fwcmdPostMbox, hw->fwcmdPostAddr); spin_unlock_irqrestore(&hw->lock, flags); msleep_interruptible(50); /* FW commands should complete even if we got a signal from the upper layer */ crystalhd_wait_on_event(&fw_cmd_event, hw->fwcmd_evt_sts, 20000, rc, true); if (!rc) { sts = BC_STS_SUCCESS; } else if (rc == -EBUSY) { dev_err(dev, "Firmware command T/O\n"); sts = BC_STS_TIMEOUT; } else if (rc == -EINTR) { dev_err(dev, "FwCmd Wait Signal int - Should never happen\n"); sts = BC_STS_IO_USER_ABORT; } else { dev_err(dev, "FwCmd IO Error.\n"); sts = BC_STS_IO_ERROR; } if (sts != BC_STS_SUCCESS) { dev_err(dev, "FwCmd Failed.\n"); return sts; } spin_lock_irqsave(&hw->lock, flags); /*Get the Responce Address*/ cmd_res_addr = hw->pfnReadDevRegister(hw->adp, hw->fwcmdRespMbox); /*Read the Response*/ hw->pfnDevDRAMRead(hw, cmd_res_addr, FW_CMD_BUFF_SZ, res_buff); spin_unlock_irqrestore(&hw->lock, flags); if (res_buff[2] != C011_RET_SUCCESS) { dev_err(dev, "res_buff[2] != C011_RET_SUCCESS\n"); return BC_STS_FW_CMD_ERR; } sts = crystalhd_link_fw_cmd_post_proc(hw, fw_cmd); if (sts != BC_STS_SUCCESS) dev_err(dev, "crystalhd_fw_cmd_post_proc Failed.\n"); return sts; } bool crystalhd_link_hw_interrupt_handle(struct crystalhd_adp *adp, struct crystalhd_hw *hw) { uint32_t intr_sts = 0; uint32_t deco_intr = 0; bool rc = false; if (!adp || !hw->dev_started) return rc; hw->stats.num_interrupts++; deco_intr = hw->pfnReadDevRegister(hw->adp, Stream2Host_Intr_Sts); intr_sts = hw->pfnReadFPGARegister(hw->adp, INTR_INTR_STATUS); if (intr_sts) { /* let system know we processed interrupt..*/ rc = true; hw->stats.dev_interrupts++; } if (deco_intr && (deco_intr != 0xdeaddead)) { if (deco_intr & 0x80000000) { /*Set the Event and the status flag*/ if (hw->pfw_cmd_event) { hw->fwcmd_evt_sts = 1; crystalhd_set_event(hw->pfw_cmd_event); } } if (deco_intr & BC_BIT(1)) crystalhd_link_proc_pib(hw); hw->pfnWriteDevRegister(hw->adp, Stream2Host_Intr_Sts, deco_intr); hw->pfnWriteDevRegister(hw->adp, Stream2Host_Intr_Sts, 0); rc = 1; } /* Rx interrupts */ crystalhd_link_rx_isr(hw, intr_sts); /* Tx interrupts*/ crystalhd_link_tx_isr(hw, intr_sts); /* Clear interrupts */ if (rc) { if (intr_sts) hw->pfnWriteFPGARegister(hw->adp, INTR_INTR_CLR_REG, intr_sts); hw->pfnWriteFPGARegister(hw->adp, INTR_EOI_CTRL, 1); } return rc; } /* Dummy private function */ void crystalhd_link_notify_fll_change(struct crystalhd_hw *hw, bool bCleanupContext) { return; } bool crystalhd_link_notify_event(struct crystalhd_hw *hw, enum BRCM_EVENT EventCode) { return true; } crystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_flea_ddr.h0000644000175000017500000000410711610313111024147 0ustar andresandres/*************************************************************************** * Copyright (c) 2005-2010, Broadcom Corporation. * * Name: crystalhd_flea_ddr . h * * Description: * BCM70015 generic DDR routines * * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ #undef BRCM_ALIGN #define BRCM_ALIGN(c,r,f) 0 #define MEM_SYS_NUM_DDR_PLLS 2; /*extern uint32_t rts_prog_vals[][5]; */ enum eDDR2_SPEED_GRADE { DDR2_400MHZ = 0x0, DDR2_333MHZ = 0x1, DDR2_266MHZ = 0x2, DDR2_200MHZ = 0x3, DDR2_533MHZ = 0x4, DDR2_667MHZ = 0x5 }; enum eSD_COL_SIZE { COL_BITS_9 = 0x0, COL_BITS_10 = 0x1, COL_BITS_11 = 0x2, }; enum eSD_BANK_SIZE { BANK_SIZE_4 = 0x0, BANK_SIZE_8 = 0x1, }; enum eSD_ROW_SIZE { ROW_SIZE_8K = 0x0, ROW_SIZE_16K = 0x1, }; /*DDR PHY PLL init routine */ void crystalhd_flea_ddr_pll_config(struct crystalhd_hw* hw, int32_t *speed_grade, int32_t num_plls, uint32_t tmode); /*DDR controller init routine */ void crystalhd_flea_ddr_ctrl_init(struct crystalhd_hw *hw, int32_t port, int32_t ddr3, int32_t speed_grade, int32_t col, int32_t bank, int32_t row, uint32_t tmode ); /*RTS Init routines */ void crystalhd_flea_ddr_arb_rts_init(struct crystalhd_hw *hw); crystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_fw_if.h0000644000175000017500000003425511610313111023510 0ustar andresandres/*************************************************************************** * Copyright (c) 2005-2009, Broadcom Corporation. * * Name: crystalhd_fw_if . h * * Description: * BCM70012 Firmware interface definitions. * * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ #ifndef _CRYSTALHD_FW_IF_H_ #define _CRYSTALHD_FW_IF_H_ #include /* TBD: Pull in only required defs into this file.. */ /* User Data Header */ struct UD_HDR { struct UD_HDR *next; uint32_t type; uint32_t size; }; /*------------------------------------------------------* * MPEG Extension to the PPB * *------------------------------------------------------*/ struct PPB_MPEG { uint32_t to_be_defined; uint32_t valid; /* Always valid, defaults to picture size if no sequence display extension in the stream. */ uint32_t display_horizontal_size; uint32_t display_vertical_size; /* MPEG_VALID_PANSCAN Offsets are a copy values from the MPEG stream. */ uint32_t offset_count; int32_t horizontal_offset[3]; int32_t vertical_offset[3]; /* MPEG_VALID_USERDATA User data is in the form of a linked list. */ int32_t userDataSize; struct UD_HDR *userData; }; /*------------------------------------------------------* * VC1 Extension to the PPB * *------------------------------------------------------*/ struct PPB_VC1 { uint32_t to_be_defined; uint32_t valid; /* Always valid, defaults to picture size if no sequence display extension in the stream. */ uint32_t display_horizontal_size; uint32_t display_vertical_size; /* VC1 pan scan windows */ uint32_t num_panscan_windows; int32_t ps_horiz_offset[4]; int32_t ps_vert_offset[4]; int32_t ps_width[4]; int32_t ps_height[4]; /* VC1_VALID_USERDATA User data is in the form of a linked list. */ int32_t userDataSize; struct UD_HDR *userData; }; /*------------------------------------------------------* * H.264 Extension to the PPB * *------------------------------------------------------*/ /** * @brief Film grain SEI message. * * Content of the film grain SEI message. */ /* maximum number of model-values as for Thomson spec(standard says 5) */ #define MAX_FGT_MODEL_VALUE (3) /* maximum number of intervals(as many as 256 intervals?) */ #define MAX_FGT_VALUE_INTERVAL (256) struct FGT_SEI { struct FGT_SEI *next; unsigned char model_values[3][MAX_FGT_VALUE_INTERVAL][MAX_FGT_MODEL_VALUE]; unsigned char upper_bound[3][MAX_FGT_VALUE_INTERVAL]; unsigned char lower_bound[3][MAX_FGT_VALUE_INTERVAL]; unsigned char cancel_flag; /* Cancel flag: 1 no film grain. */ unsigned char model_id; /* Model id. */ /* +unused SE based on Thomson spec */ unsigned char color_desc_flag; /* Separate color descrition flag. */ unsigned char bit_depth_luma; /* Bit depth luma minus 8. */ unsigned char bit_depth_chroma; /* Bit depth chroma minus 8. */ unsigned char full_range_flag; /* Full range flag. */ unsigned char color_primaries; /* Color primaries. */ unsigned char transfer_charact; /* Transfer characteristics. */ unsigned char matrix_coeff; /*< Matrix coefficients. */ /* -unused SE based on Thomson spec */ unsigned char blending_mode_id; /* Blending mode. */ unsigned char log2_scale_factor; /* Log2 scale factor (2-7). */ unsigned char comp_flag[3]; /* Components [0,2] parameters present flag. */ unsigned char num_intervals_minus1[3]; /* Number of intensity level intervals. */ unsigned char num_model_values[3]; /* Number of model values. */ uint16_t repetition_period; /* Repetition period (0-16384) */ }; struct PPB_H264 { /* 'valid' specifies which fields (or sets of * fields) below are valid. If the corresponding * bit in 'valid' is NOT set then that field(s) * is (are) not initialized. */ uint32_t valid; int32_t poc_top; /* POC for Top Field/Frame */ int32_t poc_bottom; /* POC for Bottom Field */ uint32_t idr_pic_id; /* H264_VALID_PANSCAN */ uint32_t pan_scan_count; int32_t pan_scan_left[3]; int32_t pan_scan_right[3]; int32_t pan_scan_top[3]; int32_t pan_scan_bottom[3]; /* H264_VALID_CT_TYPE */ uint32_t ct_type_count; uint32_t ct_type[3]; /* H264_VALID_SPS_CROP */ int32_t sps_crop_left; int32_t sps_crop_right; int32_t sps_crop_top; int32_t sps_crop_bottom; /* H264_VALID_VUI */ uint32_t chroma_top; uint32_t chroma_bottom; /* H264_VALID_USER */ uint32_t user_data_size; struct UD_HDR *user_data; /* H264 VALID FGT */ struct FGT_SEI *pfgt; }; struct PPB { /* Common fields. */ uint32_t picture_number; /* Ordinal display number */ uint32_t video_buffer; /* Video (picbuf) number */ uint32_t video_address; /* Address of picbuf Y */ uint32_t video_address_uv; /* Address of picbuf UV */ uint32_t video_stripe; /* Picbuf stripe */ uint32_t video_width; /* Picbuf width */ uint32_t video_height; /* Picbuf height */ uint32_t channel_id; /* Decoder channel ID */ uint32_t status; /* reserved */ uint32_t width; /* pixels */ uint32_t height; /* pixels */ uint32_t chroma_format; /* see above */ uint32_t pulldown; /* see above */ uint32_t flags; /* see above */ uint32_t pts; /* 32 LSBs of PTS */ uint32_t protocol; /* protocolXXX (above) */ uint32_t frame_rate; /* see above */ uint32_t matrix_coeff; /* see above */ uint32_t aspect_ratio; /* see above */ uint32_t colour_primaries; /* see above */ uint32_t transfer_char; /* see above */ uint32_t pcr_offset; /* 45kHz if PCR type; else 27MHz */ uint32_t n_drop; /* Number of pictures to be dropped */ uint32_t custom_aspect_ratio_width_height; /* upper 16-bits is Y and lower 16-bits is X */ uint32_t picture_tag; /* Indexing tag from BUD packets */ uint32_t picture_done_payload; uint32_t picture_meta_payload; uint32_t reserved[1]; /* Protocol-specific extensions. */ union { struct PPB_H264 h264; struct PPB_MPEG mpeg; struct PPB_VC1 vc1; } other; }; struct C011_PIB { uint32_t bFormatChange; uint32_t resolution; uint32_t channelId; uint32_t ppbPtr; int32_t ptsStcOffset; uint32_t zeroPanscanValid; uint32_t dramOutBufAddr; uint32_t yComponent; struct PPB ppb; }; struct C011_TS_CMD { uint32_t eCmd; /* eC011_TS_CMD */ uint32_t ulParams[63]; }; struct DecRspChannelStartVideo { uint32_t command; uint32_t sequence; uint32_t status; uint32_t picBuf; uint32_t picRelBuf; uint32_t picInfoDeliveryQ; uint32_t picInfoReleaseQ; uint32_t channelStatus; uint32_t userDataDeliveryQ; uint32_t userDataReleaseQ; uint32_t transportStreamCaptureAddr; uint32_t asyncEventQ; }; struct DecRspChannelChannelOpen { uint32_t command; uint32_t sequence; uint32_t status; uint32_t ChannelID; uint32_t picBuf; uint32_t picRelBuf; uint32_t picInfoDeliveryQ; uint32_t picInfoReleaseQ; uint32_t channelStatus; uint32_t userDataDeliveryQ; uint32_t userDataReleaseQ; uint32_t transportStreamCaptureAddr; uint32_t asyncEventQ; }; #define eCMD_C011_CMD_BASE (0x73763000) /* host commands */ enum eC011_TS_CMD { eCMD_TS_GET_NEXT_PIC = 0x7376F100, /* debug get next picture */ eCMD_TS_GET_LAST_PIC = 0x7376F102, /* debug get last pic status */ eCMD_TS_READ_WRITE_MEM = 0x7376F104, /* debug read write memory */ /* New API commands */ /* General commands */ eCMD_C011_INIT = eCMD_C011_CMD_BASE + 0x01, eCMD_C011_RESET = eCMD_C011_CMD_BASE + 0x02, eCMD_C011_SELF_TEST = eCMD_C011_CMD_BASE + 0x03, eCMD_C011_GET_VERSION = eCMD_C011_CMD_BASE + 0x04, eCMD_C011_GPIO = eCMD_C011_CMD_BASE + 0x05, eCMD_C011_DEBUG_SETUP = eCMD_C011_CMD_BASE + 0x06, /* Decoding commands */ eCMD_C011_DEC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x100, eCMD_C011_DEC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x101, eCMD_C011_DEC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x102, eCMD_C011_DEC_CHAN_STATUS = eCMD_C011_CMD_BASE + 0x103, eCMD_C011_DEC_CHAN_FLUSH = eCMD_C011_CMD_BASE + 0x104, eCMD_C011_DEC_CHAN_TRICK_PLAY = eCMD_C011_CMD_BASE + 0x105, eCMD_C011_DEC_CHAN_TS_PIDS = eCMD_C011_CMD_BASE + 0x106, eCMD_C011_DEC_CHAN_PS_STREAM_ID = eCMD_C011_CMD_BASE + 0x107, eCMD_C011_DEC_CHAN_INPUT_PARAMS = eCMD_C011_CMD_BASE + 0x108, eCMD_C011_DEC_CHAN_VIDEO_OUTPUT = eCMD_C011_CMD_BASE + 0x109, eCMD_C011_DEC_CHAN_OUTPUT_FORMAT = eCMD_C011_CMD_BASE + 0x10A, eCMD_C011_DEC_CHAN_SCALING_FILTERS = eCMD_C011_CMD_BASE + 0x10B, eCMD_C011_DEC_CHAN_OSD_MODE = eCMD_C011_CMD_BASE + 0x10D, eCMD_C011_DEC_CHAN_DROP = eCMD_C011_CMD_BASE + 0x10E, eCMD_C011_DEC_CHAN_RELEASE = eCMD_C011_CMD_BASE + 0x10F, eCMD_C011_DEC_CHAN_STREAM_SETTINGS = eCMD_C011_CMD_BASE + 0x110, eCMD_C011_DEC_CHAN_PAUSE_OUTPUT = eCMD_C011_CMD_BASE + 0x111, eCMD_C011_DEC_CHAN_CHANGE = eCMD_C011_CMD_BASE + 0x112, eCMD_C011_DEC_CHAN_SET_STC = eCMD_C011_CMD_BASE + 0x113, eCMD_C011_DEC_CHAN_SET_PTS = eCMD_C011_CMD_BASE + 0x114, eCMD_C011_DEC_CHAN_CC_MODE = eCMD_C011_CMD_BASE + 0x115, eCMD_C011_DEC_CREATE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x116, eCMD_C011_DEC_COPY_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x117, eCMD_C011_DEC_DELETE_AUDIO_CONTEXT = eCMD_C011_CMD_BASE + 0x118, eCMD_C011_DEC_CHAN_SET_DECYPTION = eCMD_C011_CMD_BASE + 0x119, eCMD_C011_DEC_CHAN_START_VIDEO = eCMD_C011_CMD_BASE + 0x11A, eCMD_C011_DEC_CHAN_STOP_VIDEO = eCMD_C011_CMD_BASE + 0x11B, eCMD_C011_DEC_CHAN_PIC_CAPTURE = eCMD_C011_CMD_BASE + 0x11C, eCMD_C011_DEC_CHAN_PAUSE = eCMD_C011_CMD_BASE + 0x11D, eCMD_C011_DEC_CHAN_PAUSE_STATE = eCMD_C011_CMD_BASE + 0x11E, eCMD_C011_DEC_CHAN_SET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x11F, eCMD_C011_DEC_CHAN_GET_SLOWM_RATE = eCMD_C011_CMD_BASE + 0x120, eCMD_C011_DEC_CHAN_SET_FF_RATE = eCMD_C011_CMD_BASE + 0x121, eCMD_C011_DEC_CHAN_GET_FF_RATE = eCMD_C011_CMD_BASE + 0x122, eCMD_C011_DEC_CHAN_FRAME_ADVANCE = eCMD_C011_CMD_BASE + 0x123, eCMD_C011_DEC_CHAN_SET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x124, eCMD_C011_DEC_CHAN_GET_SKIP_PIC_MODE = eCMD_C011_CMD_BASE + 0x125, eCMD_C011_DEC_CHAN_FILL_PIC_BUF = eCMD_C011_CMD_BASE + 0x126, eCMD_C011_DEC_CHAN_SET_CONTINUITY_CHECK = eCMD_C011_CMD_BASE + 0x127, eCMD_C011_DEC_CHAN_GET_CONTINUITY_CHECK = eCMD_C011_CMD_BASE + 0x128, eCMD_C011_DEC_CHAN_SET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x129, eCMD_C011_DEC_CHAN_GET_BRCM_TRICK_MODE = eCMD_C011_CMD_BASE + 0x12A, eCMD_C011_DEC_CHAN_REVERSE_FIELD_STATUS = eCMD_C011_CMD_BASE + 0x12B, eCMD_C011_DEC_CHAN_I_PICTURE_FOUND = eCMD_C011_CMD_BASE + 0x12C, eCMD_C011_DEC_CHAN_SET_PARAMETER = eCMD_C011_CMD_BASE + 0x12D, eCMD_C011_DEC_CHAN_SET_USER_DATA_MODE = eCMD_C011_CMD_BASE + 0x12E, eCMD_C011_DEC_CHAN_SET_PAUSE_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x12F, eCMD_C011_DEC_CHAN_SET_SLOW_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x130, eCMD_C011_DEC_CHAN_SET_FF_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x131, eCMD_C011_DEC_CHAN_SET_DISPLAY_TIMING_MODE = eCMD_C011_CMD_BASE + 0x132, eCMD_C011_DEC_CHAN_SET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x133, eCMD_C011_DEC_CHAN_GET_DISPLAY_MODE = eCMD_C011_CMD_BASE + 0x134, eCMD_C011_DEC_CHAN_SET_REVERSE_FIELD = eCMD_C011_CMD_BASE + 0x135, eCMD_C011_DEC_CHAN_STREAM_OPEN = eCMD_C011_CMD_BASE + 0x136, eCMD_C011_DEC_CHAN_SET_PCR_PID = eCMD_C011_CMD_BASE + 0x137, eCMD_C011_DEC_CHAN_SET_VID_PID = eCMD_C011_CMD_BASE + 0x138, eCMD_C011_DEC_CHAN_SET_PAN_SCAN_MODE = eCMD_C011_CMD_BASE + 0x139, eCMD_C011_DEC_CHAN_START_DISPLAY_AT_PTS = eCMD_C011_CMD_BASE + 0x140, eCMD_C011_DEC_CHAN_STOP_DISPLAY_AT_PTS = eCMD_C011_CMD_BASE + 0x141, eCMD_C011_DEC_CHAN_SET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x142, eCMD_C011_DEC_CHAN_GET_DISPLAY_ORDER = eCMD_C011_CMD_BASE + 0x143, eCMD_C011_DEC_CHAN_SET_HOST_TRICK_MODE = eCMD_C011_CMD_BASE + 0x144, eCMD_C011_DEC_CHAN_SET_OPERATION_MODE = eCMD_C011_CMD_BASE + 0x145, eCMD_C011_DEC_CHAN_DISPLAY_PAUSE_UNTO_PTS = eCMD_C011_CMD_BASE + 0x146, eCMD_C011_DEC_CHAN_SET_PTS_STC_DIFF_THRESHOLD = eCMD_C011_CMD_BASE + 0x147, eCMD_C011_DEC_CHAN_SEND_COMPRESSED_BUF = eCMD_C011_CMD_BASE + 0x148, eCMD_C011_DEC_CHAN_SET_CLIPPING = eCMD_C011_CMD_BASE + 0x149, eCMD_C011_DEC_CHAN_SET_PARAMETERS_FOR_HARD_RESET_INTERRUPT_TO_HOST = eCMD_C011_CMD_BASE + 0x150, /* Decoder RevD commands */ eCMD_C011_DEC_CHAN_SET_CSC = eCMD_C011_CMD_BASE + 0x180, /* color space conversion */ eCMD_C011_DEC_CHAN_SET_RANGE_REMAP = eCMD_C011_CMD_BASE + 0x181, eCMD_C011_DEC_CHAN_SET_FGT = eCMD_C011_CMD_BASE + 0x182, /* Note: 0x183 not implemented yet in Rev D main */ eCMD_C011_DEC_CHAN_SET_LASTPICTURE_PADDING = eCMD_C011_CMD_BASE + 0x183, /* Decoder 7412 commands (7412-only) */ eCMD_C011_DEC_CHAN_SET_CONTENT_KEY = eCMD_C011_CMD_BASE + 0x190, eCMD_C011_DEC_CHAN_SET_SESSION_KEY = eCMD_C011_CMD_BASE + 0x191, eCMD_C011_DEC_CHAN_FMT_CHANGE_ACK = eCMD_C011_CMD_BASE + 0x192, eCMD_C011_DEC_CHAN_CUSTOM_VIDOUT = eCMD_C011_CMD_BASE + 0x1FF, /* Encoding commands */ eCMD_C011_ENC_CHAN_OPEN = eCMD_C011_CMD_BASE + 0x200, eCMD_C011_ENC_CHAN_CLOSE = eCMD_C011_CMD_BASE + 0x201, eCMD_C011_ENC_CHAN_ACTIVATE = eCMD_C011_CMD_BASE + 0x202, eCMD_C011_ENC_CHAN_CONTROL = eCMD_C011_CMD_BASE + 0x203, eCMD_C011_ENC_CHAN_STATISTICS = eCMD_C011_CMD_BASE + 0x204, eNOTIFY_C011_ENC_CHAN_EVENT = eCMD_C011_CMD_BASE + 0x210, }; #endif crystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_lnx.h0000644000175000017500000000470511610313111023214 0ustar andresandres/*************************************************************************** * Copyright (c) 2005-2009, Broadcom Corporation. * * Name: crystalhd_lnx . c * * Description: * BCM70012 Linux driver * * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ #ifndef _CRYSTALHD_LNX_H_ #define _CRYSTALHD_LNX_H_ #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include #include "crystalhd_cmds.h" #define CRYSTAL_HD_NAME "Broadcom Crystal HD Decoder Driver" /* OS specific PCI information structure and adapter information. */ struct crystalhd_adp { /* Hardware board/PCI specifics */ char name[32]; struct pci_dev *pdev; unsigned long pci_mem_start; uint32_t pci_mem_len; void *mem_addr; unsigned long pci_i2o_start; uint32_t pci_i2o_len; void *i2o_addr; unsigned int drv_data; unsigned int dmabits; /* 32 | 64 */ unsigned int registered; unsigned int present; unsigned int msi; spinlock_t lock; /* API Related */ int chd_dec_major; unsigned int cfg_users; crystalhd_ioctl_data *idata_free_head; /* ioctl data pool */ struct crystalhd_elem *elem_pool_head; /* Queue element pool */ struct crystalhd_cmd cmds; struct crystalhd_dio_req *ua_map_free_head; struct pci_pool *fill_byte_pool; }; struct crystalhd_adp *chd_get_adp(void); struct device *chddev(void); #endif crystalhd-0.0~git20110715.fdd2f19/driver/linux/configure.ac0000644000175000017500000000035411610313111022447 0ustar andresandresAC_INIT(configure.ac) AC_CHECK_TOOL(LD, ld, :) AC_ARG_WITH(kernel-path, [ --with-kernel-path Specify kernel path], KERN_DIR=$withval, KERN_DIR="/lib/modules/"$(uname -r)"/build") AC_SUBST(KERN_DIR) AC_OUTPUT([ ./Makefile ]) crystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_misc.h0000644000175000017500000001406711610313111023350 0ustar andresandres/*************************************************************************** * Copyright (c) 2005-2009, Broadcom Corporation. * * Name: crystalhd_misc . h * * Description: * BCM70012 Linux driver general purpose routines. * Includes reg/mem read and write routines. * * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ #ifndef _CRYSTALHD_MISC_H_ #define _CRYSTALHD_MISC_H_ #include #include #include #include #include #include #include #include #include "bc_dts_glob_lnx.h" #include "crystalhd_hw.h" /* forward declare */ struct crystalhd_hw; /* Global element pool for all Queue management. * TX: Active = BC_TX_LIST_CNT, Free = BC_TX_LIST_CNT. * RX: Free = BC_RX_LIST_CNT, Active = 2 * FW-CMD: 4 */ #define BC_LINK_ELEM_POOL_SZ ((BC_TX_LIST_CNT * 2) + BC_RX_LIST_CNT + 2 + 4) /* Driver's IODATA pool count */ #define CHD_IODATA_POOL_SZ (BC_IOCTL_DATA_POOL_SIZE * BC_LINK_MAX_OPENS) /* Scatter Gather memory pool size for Tx and Rx */ #define BC_LINK_SG_POOL_SZ (BC_TX_LIST_CNT + BC_RX_LIST_CNT) enum _crystalhd_dio_sig { crystalhd_dio_inv = 0, crystalhd_dio_locked, crystalhd_dio_sg_mapped, }; struct crystalhd_dio_user_info { void *xfr_buff; uint32_t xfr_len; uint32_t uv_offset; bool dir_tx; uint32_t uv_sg_ix; uint32_t uv_sg_off; int comp_sts; int ev_sts; uint32_t y_done_sz; uint32_t uv_done_sz; uint32_t comp_flags; bool b422mode; }; struct crystalhd_dio_req { uint32_t sig; uint32_t max_pages; struct page **pages; struct scatterlist *sg; int sg_cnt; int page_cnt; int direction; struct crystalhd_dio_user_info uinfo; void *fb_va; uint32_t fb_size; dma_addr_t fb_pa; void *pib_va; /* pointer to temporary buffer to extract metadata */ struct crystalhd_dio_req *next; }; #define BC_LINK_DIOQ_SIG (0x09223280) struct crystalhd_elem { struct crystalhd_elem *flink; struct crystalhd_elem *blink; void *data; uint32_t tag; }; typedef void (*crystalhd_data_free_cb)(void *context, void *data); struct crystalhd_dioq { uint32_t sig; struct crystalhd_adp *adp; struct crystalhd_elem *head; struct crystalhd_elem *tail; uint32_t count; spinlock_t lock; wait_queue_head_t event; crystalhd_data_free_cb data_rel_cb; void *cb_context; }; typedef void (*hw_comp_callback)(struct crystalhd_dio_req *, wait_queue_head_t *event, BC_STATUS sts); /*========== PCIe Config access routines.================*/ BC_STATUS crystalhd_pci_cfg_rd(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t *); BC_STATUS crystalhd_pci_cfg_wr(struct crystalhd_adp *, uint32_t, uint32_t, uint32_t); /*========= Linux Kernel Interface routines. ======================= */ void *bc_kern_dma_alloc(struct crystalhd_adp *, uint32_t, dma_addr_t *); void bc_kern_dma_free(struct crystalhd_adp *, uint32_t, void *, dma_addr_t); #define crystalhd_create_event(_ev) init_waitqueue_head(_ev) #define crystalhd_set_event(_ev) wake_up_interruptible(_ev) #define crystalhd_wait_on_event(ev, condition, timeout, ret, nosig) \ do { \ DECLARE_WAITQUEUE(entry, current); \ unsigned long end = jiffies + msecs_to_jiffies(timeout); \ ret = 0; \ add_wait_queue(ev, &entry); \ for (;;) { \ set_current_state(TASK_INTERRUPTIBLE); \ if (condition) { \ break; \ } \ if (time_after_eq(jiffies, end)) { \ ret = -EBUSY; \ break; \ } \ schedule_timeout((HZ / 100 > 1) ? HZ / 100 : 1); \ if (!nosig && signal_pending(current)) { \ ret = -EINTR; \ break; \ } \ } \ set_current_state(TASK_RUNNING); \ remove_wait_queue(ev, &entry); \ } while (0) /*================ Direct IO mapping routines ==================*/ extern int crystalhd_create_dio_pool(struct crystalhd_adp *, uint32_t); extern void crystalhd_destroy_dio_pool(struct crystalhd_adp *); extern BC_STATUS crystalhd_map_dio(struct crystalhd_adp *, void *, uint32_t, uint32_t, bool, bool, struct crystalhd_dio_req**); extern BC_STATUS crystalhd_unmap_dio(struct crystalhd_adp *, struct crystalhd_dio_req*); #define crystalhd_get_sgle_paddr(_dio, _ix) (cpu_to_le64(sg_dma_address(&_dio->sg[_ix]))) #define crystalhd_get_sgle_len(_dio, _ix) (cpu_to_le32(sg_dma_len(&_dio->sg[_ix]))) /*================ General Purpose Queues ==================*/ extern BC_STATUS crystalhd_create_dioq(struct crystalhd_adp *, struct crystalhd_dioq **, crystalhd_data_free_cb , void *); extern void crystalhd_delete_dioq(struct crystalhd_adp *, struct crystalhd_dioq *); extern BC_STATUS crystalhd_dioq_add(struct crystalhd_dioq *ioq, void *data, bool wake, uint32_t tag); extern void *crystalhd_dioq_fetch(struct crystalhd_dioq *ioq); extern void *crystalhd_dioq_find_and_fetch(struct crystalhd_dioq *ioq, uint32_t tag); extern void *crystalhd_dioq_fetch_wait(struct crystalhd_hw *hw, uint32_t to_secs, uint32_t *sig_pend); #define crystalhd_dioq_count(_ioq) ((_ioq) ? _ioq->count : 0) extern int crystalhd_create_elem_pool(struct crystalhd_adp *, uint32_t); extern void crystalhd_delete_elem_pool(struct crystalhd_adp *); /*================ Debug routines/macros .. ================================*/ extern void crystalhd_show_buffer(uint32_t off, uint8_t *buff, uint32_t dwcount); #endif crystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_flea_ddr.c0000644000175000017500000006512111610313111024145 0ustar andresandres/*************************************************************************** * Copyright (c) 2005-2010, Broadcom Corporation. * * Name: crystalhd_flea_ddr . c * * Description: * BCM70015 generic DDR routines * * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ #include "crystalhd_hw.h" #include "crystalhd_flea_ddr.h" /*#include "bchp_ddr23_ctl_regs_0.h" */ /*#include "bchp_ddr23_phy_byte_lane_0.h" */ /*#include "bchp_ddr23_phy_byte_lane_1.h" */ /*#include "bchp_ddr23_phy_control_regs.h" */ /*#include "bchp_pri_arb_control_regs.h" */ /*#include "bchp_pri_client_regs.h" */ /* RTS Programming Values for all Clients */ /* column legend */ /* [0]: 1=Program, 0=Default; */ /* [1]: Blockout Count; */ /* [2]: Critical Period; */ /* [3]: Priority; */ /* [4]: Access Mode */ /* Default mode for clients is best effort */ uint32_t rts_prog_vals[21][5] = { {1, 130, 130, 6, 1}, /* Deblock ( 0) */ {1, 1469, 1469, 9, 1}, /* Cabac ( 1) */ {1, 251, 251, 4, 1}, /* Iloop ( 2) */ {1, 842, 842, 5, 1}, /* Oloop ( 3) */ {1, 1512, 1512, 10, 1}, /* Symb_Int ( 4) */ {1, 43, 43, 14, 1}, /* Mcomp ( 5) */ {1, 1318, 1318, 11, 1}, /* XPT_0 ( 6) */ {1, 4320, 4320, 16, 1}, /* XPT_1 ( 7) */ {1, 5400, 5400, 17, 0}, /* XPT_2 ( 8) */ {1, 1080, 1080, 18, 1}, /* ARM ( 9) */ {1, 691, 691, 7, 0}, /* MEM_DMA (10) */ {1, 1382, 1382, 15, 0}, /* SHARF (11) */ {1, 346, 346, 2, 0}, /* BVN (12) */ {1, 1728, 1728, 13, 1}, /* RxDMA3 (13) */ {1, 864, 864, 8, 1}, /* TxDMA (14) */ {1, 173, 173, 3, 1}, /* MetaDMA (15) */ {1, 2160, 2160, 19, 1}, /* DirectDMA (16) */ {1, 10800, 10800, 20, 1}, /* MSA (17) */ {1, 216, 216, 1, 1}, /* TRACE (18) */ {1, 1598, 1598, 12, 0}, /* refresh1 (19) */ { 0, 0, 0, 0, 0}, /*(20) */ }; void crystalhd_flea_ddr_pll_config(struct crystalhd_hw* hw, int32_t *speed_grade, int32_t num_plls, uint32_t tmode) { uint32_t PLL_NDIV_INT[2]; uint32_t PLL_M1DIV[2]; int32_t i; uint32_t tmp; uint32_t config; uint32_t timeout; uint32_t skip_init[2]; /* completely skip initialization */ /*uint32_t offset[2]; */ uint32_t skip_pll_setup; uint32_t poll_cnt; skip_init[0] = 0; skip_init[1] = 0; /* If the test mode is not 0 then skip the PLL setups too. */ if (tmode != 0){ skip_pll_setup = 1; } else { skip_pll_setup = 0; } /* Use this scratch register in DDR0 - which should reset to 0 - as a simple symaphore for the test */ /* to monitor if and when the Initialization of the DDR is complete */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_SCRATCH, 0); if (!skip_pll_setup) { for(i=0;ipfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, (0 << 0) | /*PWRDWN */ (0 << 1) | /*REFCOMP_PWRDWN */ (1 << 2) | /*ARESET */ (1 << 3) | /*DRESET */ (0 << 4) | /*ENB_CLKOUT */ (0 << 5) | /*BYPEN ??? */ (0 << 6) | /*PWRDWN_CH1 */ (0 << 8) | /*DLY_CH1 */ (0 << 10)| /*VCO_RNG */ (1 << 31) /*DIV2 CLK RESET */ ); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_PRE_DIVIDER, (1 << 0) | /*P1DIV */ (1 << 4) | /*P2DIV */ (PLL_NDIV_INT[i] << 8) | /*NDIV_INT */ (1 << 24) /*BYPASS_SDMOD */ ); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_DIVIDER, (PLL_M1DIV[i] << 24) /*M1DIV */ ); config = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); config &= 0xfffffffb; /*clear ARESET */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, config); } /*poll for lock */ for(i=0;ipfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS); while((timeout>0) && ((tmp & 0x1) == 0)){ msleep_interruptible(1); tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_STATUS); timeout--; } if (timeout<=0) printk("Timed out waiting for DDR Controller PLL %d to lock\n",i); } /*deassert PLL digital reset */ for(i=0;ipfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); config &= 0xfffffff7; /*clear DRESET */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, config); } /*deassert reset of logic */ for(i=0;ipfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); config &= 0x7fffffff; /*clear logic reset */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, config); } } /* end (skip_pll_setup) */ /*run VDL calibration for all byte lanes */ for(i=0;ipfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE,tmp); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE,tmp); tmp = ( (1 << 0) | /*calib_fast */ (1 << 1) /*calib_once */ ); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE,tmp); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE,tmp); if (!skip_pll_setup){ /*VDLs might not lock if clocks are bypassed */ timeout=100; tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS); while((timeout>0) && ((tmp & 0x3) == 0x0)){ msleep_interruptible(1); timeout--; tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS); } if ((tmp & 0x3) != 0x3) printk("VDL calibration did not finish or did not lock!\n"); timeout=100; tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS); while((timeout>0) && ((tmp & 0x3) == 0x0)){ msleep_interruptible(1); timeout--; tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_STATUS); } if ((tmp & 0x3) != 0x3) printk("VDL calibration did not finish or did not lock!\n"); if(timeout<=0){ printk("DDR PHY %d VDL Calibration failed\n",i); } } else { msleep_interruptible(1); } /*clear VDL calib settings */ tmp = 0; hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_CALIBRATE,tmp); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_CALIBRATE,tmp); /*override the ADDR/CTRL VDLs with results from Bytelane #0 */ /*if tmode other than zero then set the VDL compensations to max values of 0x1ff. */ tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_STATUS); tmp = (tmp >> 4) & 0x3ff; /* If in other than tmode 0 then set the VDL override settings to max. */ if (tmode) { tmp = 0x3ff; hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_0, 0x1003f); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_1, 0x1003f); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_2, 0x1003f); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_VDL_OVERRIDE_3, 0x1003f); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_0, 0x1003f); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_1, 0x1003f); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_2, 0x1003f); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_VDL_OVERRIDE_3, 0x1003f); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_UPDATE_VDL, BCHP_DDR23_CTL_REGS_0_UPDATE_VDL_refresh_MASK); } hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_STATIC_VDL_OVERRIDE, (((tmp & 0x3f0) >> 4) << 0) | /* step override value */ (1 << 16) | /* override enable */ (1 << 20) /* override force ; no update vdl required */ ); /* NAREN added support for ZQ Calibration */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL, 0); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_en_MASK); tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL); poll_cnt = 0; while(1) { if(!(tmp & BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL_sample_done_MASK)) tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL); else break; if(poll_cnt++ > 100) break; } if(tmode) { /* Set fields addr_ovr_en and dq_pvr_en to '1'. Set all *_override_val fields to 0xf - ZQ_PVT_COMP_CTL */ tmp = ( ( 1 << 25) | /* addr_ovr_en */ ( 1 << 24) | /* dq_ovr_en */ (0xf << 12) | /* addr_pd_override_val */ (0xf << 8) | /* addr_nd_override_val */ (0xf << 4) | /* dq_pd_override_val */ (0xf << 0) ); /* dq_nd_override_val */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_ZQ_PVT_COMP_CTL, tmp); /* Drive_PAD_CTL register. Set field selrxdrv and slew to 0; */ tmp = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL); tmp &= (0xfffffffe); /*clear bits 0 and 1. */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL,tmp); } }/*for(i=0.. */ } void crystalhd_flea_ddr_ctrl_init(struct crystalhd_hw *hw, int32_t port, int32_t ddr3, int32_t speed_grade, int32_t col, int32_t bank, int32_t row, uint32_t tmode) { /*uint32_t offset; */ /*uint32_t arb_refresh_addr; */ uint32_t port_int; uint32_t data; /*DDR2 Parameters */ uint8_t tRCD = 0; uint8_t tRP = 0; uint8_t tRRD = 0; uint8_t tWR = 0; uint8_t tWTR = 0; uint8_t tCAS = 0; uint8_t tWL = 0; uint8_t tRTP = 0; uint8_t tRAS = 0; uint8_t tFAW = 0; uint8_t tRFC = 0; uint8_t INTLV_BYTES = 0; uint8_t INTLV_DISABLE = 0; uint8_t CTRL_BITS = 0; uint8_t ALLOW_PICTMEM_RD = 0; uint8_t DIS_DQS_ODT = 0; uint8_t CS0_ONLY = 0; uint8_t EN_ODT_EARLY = 0; uint8_t EN_ODT_LATE = 0; uint8_t USE_CHR_HGT = 0; uint8_t DIS_ODT = 0; uint8_t EN_2T_TIMING = 0; uint8_t CWL = 0; uint8_t DQ_WIDTH = 0; uint8_t DM_IDLE_MODE = 0; uint8_t CTL_IDLE_MODE = 0; uint8_t DQ_IDLE_MODE = 0; uint8_t DIS_LATENCY_CTRL = 0; uint8_t PSPLIT = 0; uint8_t DSPLIT = 0; /* For each controller port, 0 and 1. */ for (port_int=0; port_int < 1; ++port_int) { #if 0 printk("******************************************************\n"); printk("* Configuring DDR23 at addr=0x%x, speed grade [%s]\n",0, ((speed_grade == DDR2_667MHZ) && (tmode == 0)) ? "667MHZ": ((speed_grade == DDR2_533MHZ) && (tmode == 0)) ? "533MHZ": ((speed_grade == DDR2_400MHZ) && (tmode == 0)) ? "400MHZ": ((speed_grade == DDR2_333MHZ) && (tmode == 0)) ? "333MHZ": ((speed_grade == DDR2_266MHZ) && (tmode == 0)) ? "266MHZ": "400MHZ" ); #endif /* Written in this manner to prevent table lookup in Memory for embedded MIPS code. */ /* Cannot use memory until it is inited! Case statements with greater than 5 cases use memory tables */ /* when optimized. Tony O 9/18/07 */ /* Note if not in test mode 0, choose the slowest clock speed. */ if (speed_grade == DDR2_200MHZ) { tRCD = 3; tRP = 3; tRRD = 2; tWR = 3; tWTR = 2; tCAS = 4; tWL = 3; tRTP = 2; tRAS = 8; tFAW = 10; if (bank == BANK_SIZE_4) tRFC = 21; else /*BANK_SIZE_8 */ tRFC = 26; } else if (speed_grade == DDR2_266MHZ ) { tRCD = 4; tRP = 4; tRRD = 3; tWR = 4; tWTR = 2; tCAS = 4; tWL = 3; tRTP = 2; tRAS = 11; tFAW = 14; if (bank == BANK_SIZE_4) tRFC = 28; else /*BANK_SIZE_8 */ tRFC = 34; } else if (speed_grade == DDR2_333MHZ) { tRCD = 4; tRP = 4; tRRD = 4; tWR = 5; tWTR = 3; tCAS = 4; tWL = 3; tRTP = 3; tRAS = 14; tFAW = 17; if (bank == BANK_SIZE_4) tRFC = 35; else /*BANK_SIZE_8 */ tRFC = 43; } else if ((speed_grade == DDR2_400MHZ) || (tmode != 0)) { /* -25E timing */ tRCD = 6; tRP = 6; tRRD = 4; tWR = 6; tWTR = 4; tCAS = ddr3 ? 6 : 5; tWL = ddr3 ? 5 : 4; tRTP = 3; tRAS = 18; tFAW = 20; if (bank == BANK_SIZE_4) tRFC = 42; else /*BANK_SIZE_8 */ tRFC = 52; CWL = tWL - 5; } else if (speed_grade == DDR2_533MHZ) { /* -187E timing */ tRCD = 7; tRP = 7; tRRD = 6; tWR = 8; tWTR = 4; tCAS = 7; tWL = tCAS - 1; tRTP = 4; tRAS = 22; tFAW = 24; tRFC = 68; CWL = tWL - 5; } else if (speed_grade == DDR2_667MHZ) { /* -15E timing */ tRCD = 9; tRP = 9; tRRD = 5;/* 4/5 */ tWR = 10; tWTR = 5; tCAS = 9; tWL = 7; tRTP = 5; tRAS = 24; tFAW = 30; /* 20/30 */ tRFC = 74; CWL = tWL - 5; } else printk("init: CANNOT HAPPEN - Memory DDR23 Ctrl_init failure. Incorrect speed grade type [%d]\n", speed_grade); CTRL_BITS = 0; /* Control Bit for CKE signal */ EN_2T_TIMING = 0; INTLV_DISABLE = ddr3 ? 1:0; /* disable for DDR3, enable for DDR2 */ INTLV_BYTES = 0; ALLOW_PICTMEM_RD = 0; DIS_DQS_ODT = 0; CS0_ONLY = 0; EN_ODT_EARLY = 0; EN_ODT_LATE = 0; USE_CHR_HGT = 0; DIS_ODT = 0; /*Power Saving Controls */ DM_IDLE_MODE = 0; CTL_IDLE_MODE = 0; DQ_IDLE_MODE = 0; /*Latency Control Setting */ DIS_LATENCY_CTRL = 0; /* ****** Start of Grain/Flea specific fixed settings ***** */ CS0_ONLY = 1 ; /* 16-bit mode only */ INTLV_DISABLE = 1 ; /* Interleave is always disabled */ DQ_WIDTH = 16 ; /* ****** End of Grain specific fixed settings ***** */ #if 0 printk("* DDR23 Config: CAS: %d, tRFC: %d, INTLV: %d, WIDTH: %d\n", tCAS,tRFC,INTLV_BYTES,DQ_WIDTH); printk("******************************************************\n"); #endif /*Disable refresh */ data = ((0x68 << 0) | /*Refresh period */ (0x0 << 12) /*disable refresh */ ); hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0, data); /* DecSd_Ddr2Param1 */ data = 0; SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, trcd, tRCD); /* trcd */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, trp, tRP); /* trp */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, trrd, tRRD); /* trrd */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, twr, tWR); /* twr */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, twtr, tWTR); /* twtr */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, tcas, tCAS); /* tcas */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, twl, tWL); /* twl */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS1, trtp, tRTP); /* trtp */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS1, data ); /*DecSd_Ddr2Param3 - deassert reset only */ data = 0; /*DEBUG_PRINT(PARAMS3, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS3, data ); /* Reset must be deasserted 500us before CKE. This needs */ /* to be reflected in the CFE. (add delay here) */ /*DecSd_Ddr2Param2 */ data = 0; SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, tras, tRAS); /* tras */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, tfaw, tFAW); /* tfaw */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, trfc, tRFC); /* trfc */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, bank_bits, bank & 1); /* 0 = bank size of 4K == 2bits, 1 = bank size of 8k == 3 bits */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, allow_pictmem_rd, ALLOW_PICTMEM_RD); SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, cs0_only, CS0_ONLY); SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, dis_itlv, INTLV_DISABLE); /* #disable interleave */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, il_sel, INTLV_BYTES); /* #bytes per interleave */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, sd_col_bits, col & 3); /* column bits, 0 = 9, 1= 10, 2 or 3 = 11 bits */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, clke, CTRL_BITS); /* Control Bit for CKE signal */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, use_chr_hgt, USE_CHR_HGT); SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS2, row_bits, row & 1); /* row size 1 is 16K for 2GB device, otherwise 0 and 8k sized */ /*DEBUG_PRINT(PARAMS2, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2, data ); /*DecSd_Ddr2Param3. */ data = 0; SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, wr_odt_en, DIS_ODT ? 0 : 1); SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, wr_odt_le_adj, EN_ODT_EARLY ? 1 : 0); SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, wr_odt_te_adj, EN_ODT_LATE ? 1 : 0); SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, cmd_2t, EN_2T_TIMING ? 1: 0); /* 2T timing is disabled */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, ddr_bl, ddr3 ? 1: 0); /* 0 for DDR2, 1 for DDR3 */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, wr_odt_mode, ddr3 ? 1:0); /* ddr3 preamble */ SET_FIELD(data, BCHP_DDR23_CTL_REGS_0, PARAMS3, ddr3_reset, ddr3 ? 0:1); /* ddr3 reset */ /*DEBUG_PRINT(PARAMS3, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS3, data ); } /* for( port_int......) */ data = 0; SET_FIELD(data, BCHP_DDR23_PHY_CONTROL_REGS, DRIVE_PAD_CTL, slew, 1); SET_FIELD(data, BCHP_DDR23_PHY_CONTROL_REGS, DRIVE_PAD_CTL, seltxdrv_ci, 1); SET_FIELD(data, BCHP_DDR23_PHY_CONTROL_REGS, DRIVE_PAD_CTL, sel_sstl18, ddr3 ? 0 : 1); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_DRIVE_PAD_CTL, data ); data = 0; SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, slew, 0); SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, selrxdrv, 0); SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, seltxdrv_ci, 0); SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, sel_sstl18, ddr3 ? 0 : 1); SET_FIELD(data, BCHP_DDR23_PHY_BYTE_LANE_0, DRIVE_PAD_CTL, rt60b, 0); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL, data ); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL, data ); data = 0; if (speed_grade == DDR2_667MHZ) { data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK) | ((2 << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK)); } else { data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK) | ((1 << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_data_dly_MASK)); } data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_MASK) | ((((DIS_DQS_ODT || DIS_ODT) ? 0:1) << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_MASK)); data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_MASK) | (((EN_ODT_EARLY ? 1 : 0) << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_adj_MASK)); data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_MASK) | (((DIS_ODT ? 0:1) << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_enable_MASK)); data = ((data & ~BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_MASK) | (((EN_ODT_EARLY ? 1 : 0) << BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_SHIFT) & BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_rd_enb_odt_adj_MASK)); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL, data); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL, data); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_WR_PREAMBLE_MODE, ddr3 ? 1 : 0); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_WR_PREAMBLE_MODE, ddr3 ? 1 : 0); /* Disable unused clocks */ for (port_int=0; port_int<1; ++port_int) { /* For Grain */ /* Changes for Grain/Flea */ /*offset = 0; */ /*arb_refresh_addr = BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0; */ /*offset += GLOBAL_REG_RBUS_START; */ /* Changes for Grain - till here */ if (ddr3) { data = (CWL & 0x07) << 3; /*DEBUG_PRINT(LOAD_EMODE2_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD, data ); data = 0; /*DEBUG_PRINT(LOAD_EMODE3_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD, data ); data = 6; /* was 4; */ /*DEBUG_PRINT(LOAD_EMODE_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, data ); data = 0x1100; /* Reset DLL */ data += ((tWR-4) << 9); data += ((tCAS-4) << 4); /*DEBUG_PRINT(LOAD_MODE_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD, data ); data = 0x0400; /* long calibration */ /*DEBUG_PRINT(ZQ_CALIBRATE, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_ZQ_CALIBRATE, data ); msleep_interruptible(1); } else { /*DecSd_RegSdPrechCmd // Precharge */ data = 0; /*DEBUG_PRINT(PRECHARGE_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD, data ); /*DEBUG_PRINT(PRECHARGE_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD, data ); /*DecSd_RegSdLdModeCmd //Clear EMODE 2,3 */ data = 0; /*DEBUG_PRINT(LOAD_EMODE2_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE2_CMD, data ); /*DEBUG_PRINT(LOAD_EMODE3_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE3_CMD, data ); /*DecSd_RegSdLdEmodeCmd // Enable DLL ; Rtt ; enable OCD */ data = 0x3C0; /*DEBUG_PRINT(LOAD_EMODE_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, data ); /*DecSd_RegSdLdModeCmd */ data = 0x102; /* Reset DLL */ data += ((tWR-1) << 9); data += (tCAS << 4); /*DEBUG_PRINT(LOAD_MODE_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD, data ); /*DecSd_RegSdPrechCmd // Precharge */ data = 0; /*DEBUG_PRINT(PRECHARGE_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD, data ); /*DEBUG_PRINT(PRECHARGE_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PRECHARGE_CMD, data ); /*DecSd_RegSdRefCmd // Refresh */ data = 0x69; /*DEBUG_PRINT(REFRESH_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, data ); /*DEBUG_PRINT(REFRESH_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, data ); /*DecSd_RegSdLdModeCmd */ data = 0x002; /* Un-Reset DLL */ data += ((tWR-1) << 9); data += (tCAS << 4); /*DEBUG_PRINT(LOAD_MODE_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_MODE_CMD, data ); /*DecSd_RegSdLdEmodeCmd // Enable DLL ; Rtt ; enable OCD */ data = 0x3C0; /*DEBUG_PRINT(LOAD_EMODE_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, data ); /*DecSd_RegSdLdEmodeCmd // Enable DLL ; Rtt ; disable OCD */ data = 0x40; /*DEBUG_PRINT(LOAD_EMODE_CMD, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, data ); } /*Enable refresh */ data = ((0x68 << 0) | /*Refresh period */ (0x1 << 12) /*enable refresh */ ); if (tmode == 0) { /*MemSysRegWr(arb_refresh_addr + GLOBAL_REG_RBUS_START,data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0,data); } /*offset = 0; */ /*offset += GLOBAL_REG_RBUS_START; */ /* Use this scratch register in DDR0 as a simple symaphore for the test */ /* to monitor if and when the Initialization of the DDR is complete. Seeing a non zero value */ /* indicates DDR init complete. This code is ONLY for the MIPS. It has no affect in init.c */ /* The MIPS executes this code and we wait until DDR 1 is inited before setting the semaphore. */ if ( port_int == 1) hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_SCRATCH, 0xff); /*Setup the Arbiter Data and Pict Buffer split if specified */ if (port_int==0) { /*only need to do this once */ /*where is the pict buff split (2 bits) */ /*0 = always mem_a, 1 = (<128 is mem_a), 2 = (<64 is mem_a), 3 = always mem_b */ PSPLIT = 0; /*0 = 32MB, 1 = 64MB, 2 = 128 MB, 3 = 256MB, 4=512MB */ DSPLIT = 4; data = 0; data += DSPLIT; data += PSPLIT<< 4; /* MemSysRegWr (PRI_ARB_CONTROL_REGS_CONC_CTL + offset, data ); */ } if (DIS_LATENCY_CTRL == 1){ /*set the work limit to the maximum */ /*DEBUG_PRINT(LATENCY, data); */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LATENCY, 0x3ff ); } } /* for (port_int=0...... ) */ return; } void crystalhd_flea_ddr_arb_rts_init(struct crystalhd_hw *hw) { uint32_t addr_cnt; uint32_t addr_ctrl; uint32_t i; addr_cnt = BCHP_PRI_CLIENT_REGS_CLIENT_00_COUNT; addr_ctrl = BCHP_PRI_CLIENT_REGS_CLIENT_00_CONTROL; /*Go through the various clients and program them */ for(i=0;i<21;i++){ if (rts_prog_vals[i][0] > 0) { hw->pfnWriteDevRegister(hw->adp, addr_cnt, (rts_prog_vals[i][1]) | /*Blockout Count */ (rts_prog_vals[i][2] << 16) /*Critical Period */ ); hw->pfnWriteDevRegister(hw->adp, addr_ctrl, (rts_prog_vals[i][3]) | /*Priority Level */ (rts_prog_vals[i][4] << 8) /*Access Mode */ ); } addr_cnt+=8; addr_ctrl+=8; } } crystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_lnx.c0000644000175000017500000004704011610313111023206 0ustar andresandres/*************************************************************************** BCM70010 Linux driver Copyright (c) 2005-2009, Broadcom Corporation. This driver is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation, version 2 of the License. This driver is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this driver. If not, see . ***************************************************************************/ #include #include "crystalhd_lnx.h" static struct class *crystalhd_class; static struct crystalhd_adp *g_adp_info; extern int bc_get_userhandle_count(struct crystalhd_cmd *ctx); struct device *chddev(void) { return &g_adp_info->pdev->dev; } #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35) loff_t noop_llseek(struct file *file, loff_t offset, int origin) { return file->f_pos; } #endif #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 18) static irqreturn_t chd_dec_isr(int irq, void *arg) #else static irqreturn_t chd_dec_isr(int irq, void *arg, struct pt_regs *r) #endif { struct crystalhd_adp *adp = (struct crystalhd_adp *) arg; int rc = 0; if (adp) rc = crystalhd_cmd_interrupt(&adp->cmds); return IRQ_RETVAL(rc); } static int chd_dec_enable_int(struct crystalhd_adp *adp) { int rc = 0; if (!adp || !adp->pdev) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return -EINVAL; } rc = pci_enable_msi(adp->pdev); if(rc != 0) dev_err(&adp->pdev->dev, "MSI request failed..\n"); else adp->msi = 1; rc = request_irq(adp->pdev->irq, chd_dec_isr, IRQF_SHARED, adp->name, (void *)adp); if (rc != 0) { dev_err(&adp->pdev->dev, "Interrupt request failed..\n"); if(adp->msi) { pci_disable_msi(adp->pdev); adp->msi = 0; } } return rc; } static int chd_dec_disable_int(struct crystalhd_adp *adp) { if (!adp || !adp->pdev) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return -EINVAL; } free_irq(adp->pdev->irq, adp); if (adp->msi) { pci_disable_msi(adp->pdev); adp->msi = 0; } return 0; } crystalhd_ioctl_data *chd_dec_alloc_iodata(struct crystalhd_adp *adp, bool isr) { unsigned long flags = 0; crystalhd_ioctl_data *temp; if (!adp) return NULL; spin_lock_irqsave(&adp->lock, flags); temp = adp->idata_free_head; if (temp) { adp->idata_free_head = adp->idata_free_head->next; memset(temp, 0, sizeof(*temp)); } spin_unlock_irqrestore(&adp->lock, flags); return temp; } void chd_dec_free_iodata(struct crystalhd_adp *adp, crystalhd_ioctl_data *iodata, bool isr) { unsigned long flags = 0; if (!adp || !iodata) return; spin_lock_irqsave(&adp->lock, flags); iodata->next = adp->idata_free_head; adp->idata_free_head = iodata; spin_unlock_irqrestore(&adp->lock, flags); } static inline int crystalhd_user_data(unsigned long ud, void *dr, int size, int set) { int rc; if (!ud || !dr) { dev_err(chddev(), "%s: Invalid arg\n", __func__); return -EINVAL; } if (set) rc = copy_to_user((void *)ud, dr, size); else rc = copy_from_user(dr, (void *)ud, size); if (rc) { dev_err(chddev(), "Invalid args for command\n"); rc = -EFAULT; } return rc; } static int chd_dec_fetch_cdata(struct crystalhd_adp *adp, crystalhd_ioctl_data *io, uint32_t m_sz, unsigned long ua) { unsigned long ua_off; int rc = 0; if (!adp || !io || !ua || !m_sz) { dev_err(chddev(), "Invalid Arg!!\n"); return -EINVAL; } io->add_cdata = vmalloc(m_sz); if (!io->add_cdata) { dev_err(chddev(), "kalloc fail for sz:%x\n", m_sz); return -ENOMEM; } io->add_cdata_sz = m_sz; ua_off = ua + sizeof(io->udata); rc = crystalhd_user_data(ua_off, io->add_cdata, io->add_cdata_sz, 0); if (rc) { dev_err(chddev(), "failed to pull add_cdata sz:%x " "ua_off:%x\n", io->add_cdata_sz, (unsigned int)ua_off); kfree(io->add_cdata); io->add_cdata = NULL; return -ENODATA; } return rc; } static int chd_dec_release_cdata(struct crystalhd_adp *adp, crystalhd_ioctl_data *io, unsigned long ua) { unsigned long ua_off; int rc; if (!adp || !io || !ua) { dev_err(chddev(), "Invalid Arg!!\n"); return -EINVAL; } if (io->cmd != BCM_IOC_FW_DOWNLOAD) { ua_off = ua + sizeof(io->udata); rc = crystalhd_user_data(ua_off, io->add_cdata, io->add_cdata_sz, 1); if (rc) { dev_err(chddev(), "failed to push add_cdata sz:%x " "ua_off:%x\n", io->add_cdata_sz, (unsigned int)ua_off); return -ENODATA; } } if (io->add_cdata) { vfree(io->add_cdata); io->add_cdata = NULL; } return 0; } static int chd_dec_proc_user_data(struct crystalhd_adp *adp, crystalhd_ioctl_data *io, unsigned long ua, int set) { int rc; uint32_t m_sz = 0; if (!adp || !io || !ua) { dev_err(chddev(), "Invalid Arg!!\n"); return -EINVAL; } rc = crystalhd_user_data(ua, &io->udata, sizeof(io->udata), set); if (rc) { dev_err(chddev(), "failed to %s iodata\n", (set ? "set" : "get")); return rc; } switch (io->cmd) { case BCM_IOC_MEM_RD: case BCM_IOC_MEM_WR: case BCM_IOC_FW_DOWNLOAD: m_sz = io->udata.u.devMem.NumDwords * 4; if (set) rc = chd_dec_release_cdata(adp, io, ua); else rc = chd_dec_fetch_cdata(adp, io, m_sz, ua); break; default: break; } return rc; } static int chd_dec_api_cmd(struct crystalhd_adp *adp, unsigned long ua, uint32_t uid, uint32_t cmd, crystalhd_cmd_proc func) { int rc; crystalhd_ioctl_data *temp; BC_STATUS sts = BC_STS_SUCCESS; temp = chd_dec_alloc_iodata(adp, 0); if (!temp) { dev_err(chddev(), "Failed to get iodata..\n"); return -EINVAL; } temp->u_id = uid; temp->cmd = cmd; rc = chd_dec_proc_user_data(adp, temp, ua, 0); if (!rc) { if(func == NULL) sts = BC_STS_PWR_MGMT; /* Can only happen when we are in suspend state */ else sts = func(&adp->cmds, temp); if (sts == BC_STS_PENDING) sts = BC_STS_NOT_IMPL; temp->udata.RetSts = sts; rc = chd_dec_proc_user_data(adp, temp, ua, 1); } if (temp) { chd_dec_free_iodata(adp, temp, 0); temp = NULL; } return rc; } /* API interfaces */ #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35) static int chd_dec_ioctl(struct inode *in, struct file *fd, unsigned int cmd, unsigned long ua) #else static long chd_dec_ioctl(struct file *fd, unsigned int cmd, unsigned long ua) #endif { struct crystalhd_adp *adp = chd_get_adp(); struct device *dev = &adp->pdev->dev; crystalhd_cmd_proc cproc; struct crystalhd_user *uc; dev_dbg(dev, "Entering %s\n", __func__); if (!adp || !fd) { dev_err(chddev(), "Invalid adp\n"); return -EINVAL; } uc = fd->private_data; if (!uc) { dev_err(chddev(), "Failed to get uc\n"); return -ENODATA; } cproc = crystalhd_get_cmd_proc(&adp->cmds, cmd, uc); if (!cproc && !(adp->cmds.state & BC_LINK_SUSPEND)) { dev_err(chddev(), "Unhandled command: %d\n", cmd); return -EINVAL; } return chd_dec_api_cmd(adp, ua, uc->uid, cmd, cproc); } static int chd_dec_open(struct inode *in, struct file *fd) { struct crystalhd_adp *adp = chd_get_adp(); struct device *dev = &adp->pdev->dev; int rc = 0; BC_STATUS sts = BC_STS_SUCCESS; struct crystalhd_user *uc = NULL; dev_dbg(dev, "Entering %s\n", __func__); if (!adp) { dev_err(dev, "Invalid adp\n"); return -EINVAL; } if (adp->cfg_users >= BC_LINK_MAX_OPENS) { dev_info(dev, "Already in use.%d\n", adp->cfg_users); return -EBUSY; } sts = crystalhd_user_open(&adp->cmds, &uc); if (sts != BC_STS_SUCCESS) { dev_err(dev, "cmd_user_open - %d\n", sts); rc = -EBUSY; } else { adp->cfg_users++; fd->private_data = uc; } return rc; } static int chd_dec_close(struct inode *in, struct file *fd) { struct crystalhd_adp *adp = chd_get_adp(); struct device *dev = &adp->pdev->dev; struct crystalhd_cmd *ctx = &adp->cmds; struct crystalhd_user *uc; uint32_t mode; dev_dbg(dev, "Entering %s\n", __func__); if (!adp) { dev_err(dev, "Invalid adp\n"); return -EINVAL; } uc = fd->private_data; if (!uc) { dev_err(dev, "Failed to get uc\n"); return -ENODATA; } /* Check and close only if we have not flush/closed before */ /* This is needed because release is not guarenteed to be called immediately on close, * if duplicate file handles exist due to fork etc. This causes problems with close and re-open of the device immediately */ if(uc->in_use) { mode = uc->mode; ctx->user[uc->uid].mode = DTS_MODE_INV; ctx->user[uc->uid].in_use = 0; dev_info(chddev(), "Closing user[%x] handle with mode %x\n", uc->uid, mode); if (((mode & 0xFF) == DTS_DIAG_MODE) || ((mode & 0xFF) == DTS_PLAYBACK_MODE) || ((bc_get_userhandle_count(ctx) == 0) && (ctx->hw_ctx != NULL))) { ctx->cin_wait_exit = 1; ctx->pwr_state_change = BC_HW_RUNNING; /* Stop the HW Capture just in case flush did not get called before stop */ /* And only if we had actually started it */ if(ctx->hw_ctx->rx_freeq != NULL) { crystalhd_hw_stop_capture(ctx->hw_ctx, true); crystalhd_hw_free_dma_rings(ctx->hw_ctx); } if(ctx->adp->fill_byte_pool) crystalhd_destroy_dio_pool(ctx->adp); if(ctx->adp->elem_pool_head) crystalhd_delete_elem_pool(ctx->adp); ctx->state = BC_LINK_INVALID; crystalhd_hw_close(ctx->hw_ctx, ctx->adp); kfree(ctx->hw_ctx); ctx->hw_ctx = NULL; } uc->in_use = 0; if(adp->cfg_users > 0) adp->cfg_users--; } return 0; } static const struct file_operations chd_dec_fops = { .owner = THIS_MODULE, #if LINUX_VERSION_CODE < KERNEL_VERSION(2, 6, 35) .ioctl = chd_dec_ioctl, #else .unlocked_ioctl = chd_dec_ioctl, #endif .open = chd_dec_open, .release = chd_dec_close, .llseek = noop_llseek, }; static int __devinit chd_dec_init_chdev(struct crystalhd_adp *adp) { struct device *xdev = &adp->pdev->dev; struct device *dev; crystalhd_ioctl_data *temp; int rc = -ENODEV, i = 0; if (!adp) goto fail; adp->chd_dec_major = register_chrdev(0, CRYSTALHD_API_NAME, &chd_dec_fops); if (adp->chd_dec_major < 0) { dev_err(xdev, "Failed to create config dev\n"); rc = adp->chd_dec_major; goto fail; } /* register crystalhd class */ crystalhd_class = class_create(THIS_MODULE, "crystalhd"); if (IS_ERR(crystalhd_class)) { dev_err(xdev, "failed to create class\n"); goto fail; } #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 25) dev = device_create(crystalhd_class, NULL, MKDEV(adp->chd_dec_major, 0), NULL, "crystalhd"); #else dev = device_create(crystalhd_class, NULL, MKDEV(adp->chd_dec_major, 0), "crystalhd"); #endif if (IS_ERR(dev)) { dev_err(xdev, "failed to create device\n"); goto device_create_fail; } /* rc = crystalhd_create_elem_pool(adp, BC_LINK_ELEM_POOL_SZ); */ /* if (rc) { */ /* dev_err(xdev, "failed to create device\n"); */ /* goto elem_pool_fail; */ /* } */ /* Allocate general purpose ioctl pool. */ for (i = 0; i < CHD_IODATA_POOL_SZ; i++) { temp = kzalloc(sizeof(crystalhd_ioctl_data), GFP_KERNEL); if (!temp) { dev_err(xdev, "ioctl data pool kzalloc failed\n"); rc = -ENOMEM; goto kzalloc_fail; } /* Add to global pool.. */ chd_dec_free_iodata(adp, temp, 0); } return 0; kzalloc_fail: /*crystalhd_delete_elem_pool(adp); */ /*elem_pool_fail: */ device_destroy(crystalhd_class, MKDEV(adp->chd_dec_major, 0)); device_create_fail: class_destroy(crystalhd_class); fail: return rc; } static void __devexit chd_dec_release_chdev(struct crystalhd_adp *adp) { crystalhd_ioctl_data *temp = NULL; if (!adp) return; if (adp->chd_dec_major > 0) { /* unregister crystalhd class */ device_destroy(crystalhd_class, MKDEV(adp->chd_dec_major, 0)); unregister_chrdev(adp->chd_dec_major, CRYSTALHD_API_NAME); dev_info(chddev(), "released api device - %d\n", adp->chd_dec_major); class_destroy(crystalhd_class); } adp->chd_dec_major = 0; /* Clear iodata pool.. */ do { temp = chd_dec_alloc_iodata(adp, 0); kfree(temp); } while (temp); /*crystalhd_delete_elem_pool(adp); */ } static int __devinit chd_pci_reserve_mem(struct crystalhd_adp *pinfo) { struct device *dev = &pinfo->pdev->dev; int rc; uint32_t bar0 = pci_resource_start(pinfo->pdev, 0); uint32_t i2o_len = pci_resource_len(pinfo->pdev, 0); uint32_t bar2 = pci_resource_start(pinfo->pdev, 2); uint32_t mem_len = pci_resource_len(pinfo->pdev, 2); dev_dbg(dev, "bar0:0x%x-0x%08x bar2:0x%x-0x%08x\n", bar0, i2o_len, bar2, mem_len); /* bar-0 */ rc = check_mem_region(bar0, i2o_len); if (rc) { printk(KERN_ERR "No valid mem region...\n"); return -ENOMEM; } pinfo->i2o_addr = ioremap_nocache(bar0, i2o_len); if (!pinfo->i2o_addr) { printk(KERN_ERR "Failed to remap i2o region...\n"); return -ENOMEM; } pinfo->pci_i2o_start = bar0; pinfo->pci_i2o_len = i2o_len; /* bar-2 */ rc = check_mem_region(bar2, mem_len); if (rc) { printk(KERN_ERR "No valid mem region...\n"); return -ENOMEM; } pinfo->mem_addr = ioremap_nocache(bar2, mem_len); if (!pinfo->mem_addr) { printk(KERN_ERR "Failed to remap mem region...\n"); return -ENOMEM; } pinfo->pci_mem_start = bar2; pinfo->pci_mem_len = mem_len; /* pdev */ rc = pci_request_regions(pinfo->pdev, pinfo->name); if (rc < 0) { printk(KERN_ERR "Region request failed: %d\n", rc); return rc; } dev_dbg(dev, "i2o_addr:0x%08lx Mapped addr:0x%08lx \n", (unsigned long)pinfo->i2o_addr, (unsigned long)pinfo->mem_addr); return 0; } static void __devexit chd_pci_release_mem(struct crystalhd_adp *pinfo) { if (!pinfo) return; if (pinfo->mem_addr) iounmap(pinfo->mem_addr); if (pinfo->i2o_addr) iounmap(pinfo->i2o_addr); pci_release_regions(pinfo->pdev); } static void __devexit chd_dec_pci_remove(struct pci_dev *pdev) { struct crystalhd_adp *pinfo; BC_STATUS sts = BC_STS_SUCCESS; dev_dbg(chddev(), "Entering %s\n", __func__); pinfo = (struct crystalhd_adp *) pci_get_drvdata(pdev); if (!pinfo) { dev_err(chddev(), "could not get adp\n"); return; } sts = crystalhd_delete_cmd_context(&pinfo->cmds); if (sts != BC_STS_SUCCESS) dev_err(chddev(), "cmd delete :%d\n", sts); chd_dec_release_chdev(pinfo); chd_dec_disable_int(pinfo); chd_pci_release_mem(pinfo); pci_disable_device(pinfo->pdev); kfree(pinfo); g_adp_info = NULL; } static int __devinit chd_dec_pci_probe(struct pci_dev *pdev, const struct pci_device_id *entry) { struct device *dev = &pdev->dev; struct crystalhd_adp *pinfo; int rc; BC_STATUS sts = BC_STS_SUCCESS; dev_info(dev, "Starting Device:0x%04x\n", pdev->device); pinfo = kzalloc(sizeof(struct crystalhd_adp), GFP_KERNEL); if (!pinfo) { dev_err(dev, "%s: Failed to allocate memory\n", __func__); rc = -ENOMEM; goto out; } pinfo->pdev = pdev; rc = pci_enable_device(pdev); if (rc) { dev_err(dev, "%s: Failed to enable PCI device\n", __func__); goto free_priv; } snprintf(pinfo->name, sizeof(pinfo->name), "crystalhd_pci_e:%d:%d:%d", pdev->bus->number, PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn)); rc = chd_pci_reserve_mem(pinfo); if (rc) { dev_err(dev, "%s: Failed to set up memory regions.\n", __func__); goto disable_device; } pinfo->present = 1; pinfo->drv_data = entry->driver_data; /* Setup adapter level lock.. */ spin_lock_init(&pinfo->lock); /* setup api stuff.. */ rc = chd_dec_init_chdev(pinfo); if (rc) goto release_mem; rc = chd_dec_enable_int(pinfo); if (rc) { dev_err(dev, "%s: _enable_int err:%d\n", __func__, rc); goto cleanup_chdev; } /* Set dma mask... */ if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) { pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64)); pinfo->dmabits = 64; } else if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) { pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)); pinfo->dmabits = 32; } else { dev_err(dev, "%s: Unabled to setup DMA %d\n", __func__, rc); rc = -ENODEV; goto cleanup_int; } sts = crystalhd_setup_cmd_context(&pinfo->cmds, pinfo); if (sts != BC_STS_SUCCESS) { dev_err(dev, "%s: cmd setup :%d\n", __func__, sts); rc = -ENODEV; goto cleanup_int; } pci_set_master(pdev); pci_set_drvdata(pdev, pinfo); g_adp_info = pinfo; out: return rc; cleanup_int: chd_dec_disable_int(pinfo); cleanup_chdev: chd_dec_release_chdev(pinfo); release_mem: chd_pci_release_mem(pinfo); disable_device: pci_disable_device(pdev); free_priv: kfree(pdev); goto out; } int chd_dec_pci_suspend(struct pci_dev *pdev, pm_message_t state) { struct crystalhd_adp *adp; struct device *dev = &pdev->dev; crystalhd_ioctl_data *temp; BC_STATUS sts = BC_STS_SUCCESS; adp = (struct crystalhd_adp *)pci_get_drvdata(pdev); if (!adp) { dev_err(dev, "%s: could not get adp\n", __func__); return -ENODEV; } temp = chd_dec_alloc_iodata(adp, false); if (!temp) { dev_err(dev, "could not get ioctl data\n"); return -ENODEV; } sts = crystalhd_suspend(&adp->cmds, temp); if (sts != BC_STS_SUCCESS) { dev_err(dev, "Crystal HD Suspend %d\n", sts); chd_dec_free_iodata(adp, temp, false); return -ENODEV; } chd_dec_free_iodata(adp, temp, false); chd_dec_disable_int(adp); pci_save_state(pdev); /* Disable IO/bus master/irq router */ pci_disable_device(pdev); pci_set_power_state(pdev, pci_choose_state(pdev, state)); return 0; } int chd_dec_pci_resume(struct pci_dev *pdev) { struct crystalhd_adp *adp; struct device *dev = &pdev->dev; BC_STATUS sts = BC_STS_SUCCESS; int rc; adp = (struct crystalhd_adp *)pci_get_drvdata(pdev); if (!adp) { dev_err(dev, "%s: could not get adp\n", __func__); return -ENODEV; } pci_set_power_state(pdev, PCI_D0); pci_restore_state(pdev); /* device's irq possibly is changed, driver should take care */ if (pci_enable_device(pdev)) { dev_err(dev, "Failed to enable PCI device\n"); return 1; } pci_set_master(pdev); rc = chd_dec_enable_int(adp); if (rc) { dev_err(dev, "_enable_int err:%d\n", rc); pci_disable_device(pdev); return -ENODEV; } sts = crystalhd_resume(&adp->cmds); if (sts != BC_STS_SUCCESS) { dev_err(dev, "Crystal HD Resume %d\n", sts); pci_disable_device(pdev); return -ENODEV; } return 0; } #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 24) static DEFINE_PCI_DEVICE_TABLE(chd_dec_pci_id_table) = { { PCI_VDEVICE(BROADCOM, 0x1612), 8 }, { PCI_VDEVICE(BROADCOM, 0x1615), 8 }, { 0, }, }; #else static struct pci_device_id chd_dec_pci_id_table[] = { /* vendor, device, subvendor, subdevice, class, classmask, driver_data */ { 0x14e4, 0x1612, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 }, { 0x14e4, 0x1615, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 8 }, { 0, }, }; #endif MODULE_DEVICE_TABLE(pci, chd_dec_pci_id_table); static struct pci_driver bc_chd_driver = { .name = "crystalhd", .probe = chd_dec_pci_probe, .remove = __devexit_p(chd_dec_pci_remove), .id_table = chd_dec_pci_id_table, .suspend = chd_dec_pci_suspend, .resume = chd_dec_pci_resume }; struct crystalhd_adp *chd_get_adp(void) { return g_adp_info; } static int __init chd_dec_module_init(void) { int rc; printk(KERN_DEBUG "Loading crystalhd v%d.%d.%d\n", crystalhd_kmod_major, crystalhd_kmod_minor, crystalhd_kmod_rev); rc = pci_register_driver(&bc_chd_driver); if (rc < 0) printk(KERN_ERR "%s: Could not find any devices. err:%d\n", __func__, rc); return rc; } module_init(chd_dec_module_init); static void __exit chd_dec_module_cleanup(void) { printk(KERN_DEBUG "Unloading crystalhd %d.%d.%d\n", crystalhd_kmod_major, crystalhd_kmod_minor, crystalhd_kmod_rev); pci_unregister_driver(&bc_chd_driver); } module_exit(chd_dec_module_cleanup); MODULE_AUTHOR("Naren Sankar "); MODULE_AUTHOR("Prasad Bolisetty "); MODULE_DESCRIPTION(CRYSTAL_HD_NAME); MODULE_LICENSE("GPL"); MODULE_ALIAS("crystalhd"); crystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_cmds.c0000644000175000017500000010031011610313111023321 0ustar andresandres/*************************************************************************** * Copyright (c) 2005-2009, Broadcom Corporation. * * Name: crystalhd_cmds . c * * Description: * BCM70012/BCM70015 Linux driver user command interfaces. * * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ #include "crystalhd_lnx.h" #include "crystalhd_hw.h" static struct crystalhd_user *bc_cproc_get_uid(struct crystalhd_cmd *ctx) { struct crystalhd_user *user = NULL; int i; for (i = 0; i < BC_LINK_MAX_OPENS; i++) { if (!ctx->user[i].in_use) { user = &ctx->user[i]; break; } } return user; } int bc_get_userhandle_count(struct crystalhd_cmd *ctx) { int i, count = 0; for (i = 0; i < BC_LINK_MAX_OPENS; i++) { if (ctx->user[i].in_use) count++; } return count; } static void bc_cproc_mark_pwr_state(struct crystalhd_cmd *ctx, uint32_t state) { int i; for (i = 0; i < BC_LINK_MAX_OPENS; i++) { if (!ctx->user[i].in_use) continue; if ((ctx->user[i].mode & 0xFF) == DTS_DIAG_MODE || (ctx->user[i].mode & 0xFF) == DTS_PLAYBACK_MODE) { ctx->pwr_state_change = state; break; } } } static BC_STATUS bc_cproc_notify_mode(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { struct device *dev = chddev(); int rc = 0, i = 0; if (!ctx || !idata) { dev_err(dev, "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } if (ctx->user[idata->u_id].mode != DTS_MODE_INV) { dev_err(dev, "Close the handle first..\n"); return BC_STS_ERR_USAGE; } if ((idata->udata.u.NotifyMode.Mode && 0xFF) == DTS_MONITOR_MODE) { ctx->user[idata->u_id].mode = idata->udata.u.NotifyMode.Mode; return BC_STS_SUCCESS; } if (ctx->state != BC_LINK_INVALID) { dev_err(dev, "Link invalid state notify mode %x \n", ctx->state); return BC_STS_ERR_USAGE; } /* Check for duplicate playback sessions..*/ for (i = 0; i < BC_LINK_MAX_OPENS; i++) { if ((ctx->user[i].mode & 0xFF) == DTS_DIAG_MODE || (ctx->user[i].mode & 0xFF) == DTS_PLAYBACK_MODE) { dev_err(dev, "multiple playback sessions are not " "supported..\n"); return BC_STS_ERR_USAGE; } } ctx->cin_wait_exit = 0; ctx->user[idata->u_id].mode = idata->udata.u.NotifyMode.Mode; /* Create list pools */ rc = crystalhd_create_elem_pool(ctx->adp, BC_LINK_ELEM_POOL_SZ); if (rc) return BC_STS_ERROR; /* Setup mmap pool for uaddr sgl mapping..*/ rc = crystalhd_create_dio_pool(ctx->adp, BC_LINK_MAX_SGLS); if (rc) return BC_STS_ERROR; /* Setup Hardware DMA rings */ return crystalhd_hw_setup_dma_rings(ctx->hw_ctx); } static BC_STATUS bc_cproc_get_version(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { if (!ctx || !idata) { dev_err(chddev(), "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } idata->udata.u.VerInfo.DriverMajor = crystalhd_kmod_major; idata->udata.u.VerInfo.DriverMinor = crystalhd_kmod_minor; idata->udata.u.VerInfo.DriverRevision = crystalhd_kmod_rev; return BC_STS_SUCCESS; } static BC_STATUS bc_cproc_get_hwtype(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { if (!ctx || !idata) { dev_err(chddev(), "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } crystalhd_pci_cfg_rd(ctx->adp, 0, 2, (uint32_t *)&idata->udata.u.hwType.PciVenId); crystalhd_pci_cfg_rd(ctx->adp, 2, 2, (uint32_t *)&idata->udata.u.hwType.PciDevId); crystalhd_pci_cfg_rd(ctx->adp, 8, 1, (uint32_t *)&idata->udata.u.hwType.HwRev); return BC_STS_SUCCESS; } static BC_STATUS bc_cproc_reg_rd(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { if (!ctx || !idata) return BC_STS_INV_ARG; idata->udata.u.regAcc.Value = ctx->hw_ctx->pfnReadDevRegister(ctx->adp, idata->udata.u.regAcc.Offset); return BC_STS_SUCCESS; } static BC_STATUS bc_cproc_reg_wr(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { if (!ctx || !idata) return BC_STS_INV_ARG; ctx->hw_ctx->pfnWriteDevRegister(ctx->adp, idata->udata.u.regAcc.Offset, idata->udata.u.regAcc.Value); return BC_STS_SUCCESS; } static BC_STATUS bc_cproc_link_reg_rd(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { if (!ctx || !idata) return BC_STS_INV_ARG; idata->udata.u.regAcc.Value = ctx->hw_ctx->pfnReadFPGARegister(ctx->adp, idata->udata.u.regAcc.Offset); return BC_STS_SUCCESS; } static BC_STATUS bc_cproc_link_reg_wr(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { if (!ctx || !idata) return BC_STS_INV_ARG; ctx->hw_ctx->pfnWriteFPGARegister(ctx->adp, idata->udata.u.regAcc.Offset, idata->udata.u.regAcc.Value); return BC_STS_SUCCESS; } static BC_STATUS bc_cproc_mem_rd(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { BC_STATUS sts = BC_STS_SUCCESS; if (!ctx || !idata || !idata->add_cdata) return BC_STS_INV_ARG; if (idata->udata.u.devMem.NumDwords > (idata->add_cdata_sz / 4)) { dev_err(chddev(), "insufficient buffer\n"); return BC_STS_INV_ARG; } sts = ctx->hw_ctx->pfnDevDRAMRead(ctx->hw_ctx, idata->udata.u.devMem.StartOff, idata->udata.u.devMem.NumDwords, (uint32_t *)idata->add_cdata); return sts; } static BC_STATUS bc_cproc_mem_wr(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { BC_STATUS sts = BC_STS_SUCCESS; if (!ctx || !idata || !idata->add_cdata) return BC_STS_INV_ARG; if (idata->udata.u.devMem.NumDwords > (idata->add_cdata_sz / 4)) { dev_err(chddev(), "insufficient buffer\n"); return BC_STS_INV_ARG; } sts = ctx->hw_ctx->pfnDevDRAMWrite(ctx->hw_ctx, idata->udata.u.devMem.StartOff, idata->udata.u.devMem.NumDwords, (uint32_t *)idata->add_cdata); return sts; } static BC_STATUS bc_cproc_cfg_rd(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { uint32_t ix, cnt, off, len; BC_STATUS sts = BC_STS_SUCCESS; uint32_t *temp; if (!ctx || !idata) return BC_STS_INV_ARG; temp = (uint32_t *) idata->udata.u.pciCfg.pci_cfg_space; off = idata->udata.u.pciCfg.Offset; len = idata->udata.u.pciCfg.Size; if (len <= 4) { sts = crystalhd_pci_cfg_rd(ctx->adp, off, len, temp); return sts; } /* Truncate to dword alignment..*/ len = 4; cnt = idata->udata.u.pciCfg.Size / len; for (ix = 0; ix < cnt; ix++) { sts = crystalhd_pci_cfg_rd(ctx->adp, off, len, &temp[ix]); if (sts != BC_STS_SUCCESS) { dev_err(chddev(), "config read : %d\n", sts); return sts; } off += len; } return sts; } static BC_STATUS bc_cproc_cfg_wr(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { uint32_t ix, cnt, off, len; BC_STATUS sts = BC_STS_SUCCESS; uint32_t *temp; if (!ctx || !idata) return BC_STS_INV_ARG; temp = (uint32_t *) idata->udata.u.pciCfg.pci_cfg_space; off = idata->udata.u.pciCfg.Offset; len = idata->udata.u.pciCfg.Size; if (len <= 4) return crystalhd_pci_cfg_wr(ctx->adp, off, len, temp[0]); /* Truncate to dword alignment..*/ len = 4; cnt = idata->udata.u.pciCfg.Size / len; for (ix = 0; ix < cnt; ix++) { sts = crystalhd_pci_cfg_wr(ctx->adp, off, len, temp[ix]); if (sts != BC_STS_SUCCESS) { dev_err(chddev(), "config write : %d\n", sts); return sts; } off += len; } return sts; } static BC_STATUS bc_cproc_download_fw(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { BC_STATUS sts = BC_STS_SUCCESS; dev_dbg(chddev(), "Downloading FW\n"); if (!ctx || !idata || !idata->add_cdata || !idata->add_cdata_sz) { dev_err(chddev(), "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } if ((ctx->state != BC_LINK_INVALID) && (ctx->state != BC_LINK_RESUME)) { dev_dbg(chddev(), "Link invalid state download fw %x \n", ctx->state); return BC_STS_ERR_USAGE; } sts = ctx->hw_ctx->pfnFWDwnld(ctx->hw_ctx, (uint8_t *)idata->add_cdata, idata->add_cdata_sz); if (sts != BC_STS_SUCCESS) { dev_info(chddev(), "Firmware Download Failure!! - %d\n", sts); } else ctx->state |= BC_LINK_INIT; ctx->pwr_state_change = BC_HW_RUNNING; ctx->hw_ctx->FwCmdCnt = 0; return sts; } /* * We use the FW_CMD interface to sync up playback state with application * and firmware. This function will perform the required pre and post * processing of the Firmware commands. * * Pause - * Disable capture after decoder pause. * Resume - * First enable capture and issue decoder resume command. * Flush - * Abort pending input transfers and issue decoder flush command. * */ static BC_STATUS bc_cproc_do_fw_cmd(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { struct device *dev = chddev(); BC_STATUS sts; uint32_t *cmd; if (!(ctx->state & BC_LINK_INIT)) { dev_dbg(dev, "Link invalid state do fw cmd %x \n", ctx->state); return BC_STS_ERR_USAGE; } cmd = idata->udata.u.fwCmd.cmd; /* Pre-Process */ if (cmd[0] == eCMD_C011_DEC_CHAN_PAUSE) { if (!cmd[3]) { ctx->state &= ~BC_LINK_PAUSED; ctx->hw_ctx->pfnIssuePause(ctx->hw_ctx, false); } } else if (cmd[0] == eCMD_C011_DEC_CHAN_FLUSH) { dev_dbg(dev, "Flush issued\n"); if (cmd[3]) ctx->cin_wait_exit = 1; } sts = ctx->hw_ctx->pfnDoFirmwareCmd(ctx->hw_ctx, &idata->udata.u.fwCmd); if (sts != BC_STS_SUCCESS) { dev_dbg(dev, "fw cmd %x failed\n", cmd[0]); return sts; } /* Post-Process */ if (cmd[0] == eCMD_C011_DEC_CHAN_PAUSE) { if (cmd[3]) { ctx->state |= BC_LINK_PAUSED; ctx->hw_ctx->pfnIssuePause(ctx->hw_ctx, true); } } return sts; } static void bc_proc_in_completion(struct crystalhd_dio_req *dio_hnd, wait_queue_head_t *event, BC_STATUS sts) { if (!dio_hnd || !event) { dev_err(chddev(), "%s: Invalid Arg\n", __func__); return; } if (sts == BC_STS_IO_USER_ABORT || sts == BC_STS_PWR_MGMT) return; dio_hnd->uinfo.comp_sts = sts; dio_hnd->uinfo.ev_sts = 1; crystalhd_set_event(event); } static BC_STATUS bc_cproc_codein_sleep(struct crystalhd_cmd *ctx) { wait_queue_head_t sleep_ev; int rc = 0; if (ctx->state & BC_LINK_SUSPEND) return BC_STS_PWR_MGMT; if (ctx->cin_wait_exit) { ctx->cin_wait_exit = 0; return BC_STS_CMD_CANCELLED; } crystalhd_create_event(&sleep_ev); crystalhd_wait_on_event(&sleep_ev, 0, 100, rc, false); if (rc == -EINTR) return BC_STS_IO_USER_ABORT; return BC_STS_SUCCESS; } static BC_STATUS bc_cproc_hw_txdma(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata, struct crystalhd_dio_req *dio) { struct device *dev = chddev(); uint32_t tx_listid = 0; BC_STATUS sts = BC_STS_SUCCESS; wait_queue_head_t event; int rc = 0; if (!ctx || !idata || !dio) { dev_err(dev, "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } crystalhd_create_event(&event); ctx->tx_list_id = 0; /* msleep_interruptible(2000); */ sts = crystalhd_hw_post_tx(ctx->hw_ctx, dio, bc_proc_in_completion, &event, &tx_listid, idata->udata.u.ProcInput.Encrypted); while (sts == BC_STS_BUSY) { sts = bc_cproc_codein_sleep(ctx); if (sts != BC_STS_SUCCESS) break; sts = crystalhd_hw_post_tx(ctx->hw_ctx, dio, bc_proc_in_completion, &event, &tx_listid, idata->udata.u.ProcInput.Encrypted); } if (sts != BC_STS_SUCCESS) { dev_dbg(dev, "_hw_txdma returning sts:%d\n", sts); return sts; } if (ctx->cin_wait_exit) ctx->cin_wait_exit = 0; ctx->tx_list_id = tx_listid; dev_dbg(dev, "Sending TX\n"); /* _post() succeeded.. wait for the completion. */ crystalhd_wait_on_event(&event, (dio->uinfo.ev_sts), 3000, rc, false); ctx->tx_list_id = 0; if (!rc) { return dio->uinfo.comp_sts; } else if (rc == -EBUSY) { dev_dbg(dev, "_tx_post() T/O \n"); sts = BC_STS_TIMEOUT; } else if (rc == -EINTR) { dev_dbg(dev, "Tx Wait Signal int.\n"); sts = BC_STS_IO_USER_ABORT; } else { sts = BC_STS_IO_ERROR; } /* We are cancelling the IO from the same context as the _post(). * so no need to wait on the event again.. the return itself * ensures the release of our resources. */ crystalhd_hw_cancel_tx(ctx->hw_ctx, tx_listid); return sts; } /* Helper function to check on user buffers */ static BC_STATUS bc_cproc_check_inbuffs(bool pin, void *ubuff, uint32_t ub_sz, uint32_t uv_off, bool en_422) { struct device *dev = chddev(); if (!ubuff || !ub_sz) { dev_err(dev, "%s->Invalid Arg %p %x\n", ((pin) ? "TX" : "RX"), ubuff, ub_sz); return BC_STS_INV_ARG; } /* Check for alignment */ if (((uintptr_t)ubuff) & 0x03) { dev_err(dev, "%s-->Un-aligned address not implemented yet.. %p \n", ((pin) ? "TX" : "RX"), ubuff); return BC_STS_NOT_IMPL; } if (pin) return BC_STS_SUCCESS; if (!en_422 && !uv_off) { dev_err(dev, "Need UV offset for 420 mode.\n"); return BC_STS_INV_ARG; } if (en_422 && uv_off) { dev_err(dev, "UV offset in 422 mode ??\n"); return BC_STS_INV_ARG; } return BC_STS_SUCCESS; } static BC_STATUS bc_cproc_proc_input(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { struct device *dev = chddev(); void *ubuff; uint32_t ub_sz; struct crystalhd_dio_req *dio_hnd = NULL; BC_STATUS sts = BC_STS_SUCCESS; if (!ctx || !idata) { dev_err(dev, "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } if (ctx->state & BC_LINK_SUSPEND) { dev_err(dev, "proc_input: Link Suspended\n"); return BC_STS_PWR_MGMT; } ubuff = idata->udata.u.ProcInput.pDmaBuff; ub_sz = idata->udata.u.ProcInput.BuffSz; sts = bc_cproc_check_inbuffs(1, ubuff, ub_sz, 0, 0); if (sts != BC_STS_SUCCESS) return sts; sts = crystalhd_map_dio(ctx->adp, ubuff, ub_sz, 0, 0, 1, &dio_hnd); if (sts != BC_STS_SUCCESS) { dev_err(dev, "dio map - %d \n", sts); return sts; } if (!dio_hnd) return BC_STS_ERROR; sts = bc_cproc_hw_txdma(ctx, idata, dio_hnd); crystalhd_unmap_dio(ctx->adp, dio_hnd); return sts; } static BC_STATUS bc_cproc_add_cap_buff(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { struct device *dev = chddev(); void *ubuff; uint32_t ub_sz, uv_off; bool en_422; struct crystalhd_dio_req *dio_hnd = NULL; BC_STATUS sts = BC_STS_SUCCESS; if (!ctx || !idata) { dev_err(dev, "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } ubuff = idata->udata.u.RxBuffs.YuvBuff; ub_sz = idata->udata.u.RxBuffs.YuvBuffSz; uv_off = idata->udata.u.RxBuffs.UVbuffOffset; en_422 = idata->udata.u.RxBuffs.b422Mode; sts = bc_cproc_check_inbuffs(0, ubuff, ub_sz, uv_off, en_422); if (sts != BC_STS_SUCCESS) return sts; sts = crystalhd_map_dio(ctx->adp, ubuff, ub_sz, uv_off, en_422, 0, &dio_hnd); if (sts != BC_STS_SUCCESS) { dev_err(dev, "dio map - %d \n", sts); return sts; } if (!dio_hnd) return BC_STS_ERROR; sts = crystalhd_hw_add_cap_buffer(ctx->hw_ctx, dio_hnd, (ctx->state == BC_LINK_READY)); if ((sts != BC_STS_SUCCESS) && (sts != BC_STS_BUSY)) { crystalhd_unmap_dio(ctx->adp, dio_hnd); return sts; } return BC_STS_SUCCESS; } static BC_STATUS bc_cproc_fmt_change(struct crystalhd_cmd *ctx, struct crystalhd_dio_req *dio) { BC_STATUS sts = BC_STS_SUCCESS; sts = crystalhd_hw_add_cap_buffer(ctx->hw_ctx, dio, 0); if (sts != BC_STS_SUCCESS) return sts; ctx->state |= BC_LINK_FMT_CHG; if (ctx->state == BC_LINK_READY) sts = crystalhd_hw_start_capture(ctx->hw_ctx); return sts; } static BC_STATUS bc_cproc_fetch_frame(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { struct device *dev = chddev(); struct crystalhd_dio_req *dio = NULL; BC_STATUS sts = BC_STS_SUCCESS; BC_DEC_OUT_BUFF *frame; if (!ctx || !idata) { dev_err(dev, "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } if (ctx->state & BC_LINK_SUSPEND) return BC_STS_PWR_MGMT; if (!(ctx->state & BC_LINK_CAP_EN)) { dev_dbg(dev, "Capture not enabled..%x\n", ctx->state); return BC_STS_ERR_USAGE; } frame = &idata->udata.u.DecOutData; sts = crystalhd_hw_get_cap_buffer(ctx->hw_ctx, &frame->PibInfo, &dio); if (sts != BC_STS_SUCCESS) return (ctx->state & BC_LINK_SUSPEND) ? BC_STS_PWR_MGMT : sts; dev_dbg(dev, "Got Picture\n"); frame->Flags = dio->uinfo.comp_flags; if (frame->Flags & COMP_FLAG_FMT_CHANGE) return bc_cproc_fmt_change(ctx, dio); frame->OutPutBuffs.YuvBuff = dio->uinfo.xfr_buff; frame->OutPutBuffs.YuvBuffSz = dio->uinfo.xfr_len; frame->OutPutBuffs.UVbuffOffset = dio->uinfo.uv_offset; frame->OutPutBuffs.b422Mode = dio->uinfo.b422mode; frame->OutPutBuffs.YBuffDoneSz = dio->uinfo.y_done_sz; frame->OutPutBuffs.UVBuffDoneSz = dio->uinfo.uv_done_sz; crystalhd_unmap_dio(ctx->adp, dio); return BC_STS_SUCCESS; } static BC_STATUS bc_cproc_start_capture(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { ctx->state |= BC_LINK_CAP_EN; if( idata->udata.u.RxCap.PauseThsh ) ctx->hw_ctx->PauseThreshold = idata->udata.u.RxCap.PauseThsh; else ctx->hw_ctx->PauseThreshold = HW_PAUSE_THRESHOLD; if( idata->udata.u.RxCap.ResumeThsh ) ctx->hw_ctx->ResumeThreshold = idata->udata.u.RxCap.ResumeThsh; else ctx->hw_ctx->ResumeThreshold = HW_RESUME_THRESHOLD; printk(KERN_DEBUG "start_capture: pause_th:%d, resume_th:%d\n", ctx->hw_ctx->PauseThreshold, ctx->hw_ctx->ResumeThreshold); ctx->hw_ctx->DrvTotalFrmCaptured = 0; ctx->hw_ctx->DefaultPauseThreshold = ctx->hw_ctx->PauseThreshold; /* used to restore on FMTCH */ ctx->hw_ctx->pfnNotifyHardware(ctx->hw_ctx, BC_EVENT_START_CAPTURE); if (ctx->state == BC_LINK_READY) return crystalhd_hw_start_capture(ctx->hw_ctx); return BC_STS_SUCCESS; } static BC_STATUS bc_cproc_flush_cap_buffs(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { struct device *dev = chddev(); struct crystalhd_rx_dma_pkt *rpkt; if (!ctx || !idata) { dev_err(dev, "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } if (!(ctx->state & BC_LINK_CAP_EN)) return BC_STS_ERR_USAGE; /* We should ack flush even when we are in paused/suspend state */ /* if (!(ctx->state & BC_LINK_READY)) */ /* return crystalhd_hw_stop_capture(&ctx->hw_ctx); */ dev_dbg(dev, "number of rx success %u and failure %u\n", ctx->hw_ctx->stats.rx_success, ctx->hw_ctx->stats.rx_errors); if(idata->udata.u.FlushRxCap.bDiscardOnly) { /* just flush without unmapping and then resume */ crystalhd_hw_stop_capture(ctx->hw_ctx, false); while((rpkt = crystalhd_dioq_fetch(ctx->hw_ctx->rx_actq)) != NULL) crystalhd_dioq_add(ctx->hw_ctx->rx_freeq, rpkt, false, rpkt->pkt_tag); while((rpkt = crystalhd_dioq_fetch(ctx->hw_ctx->rx_rdyq)) != NULL) crystalhd_dioq_add(ctx->hw_ctx->rx_freeq, rpkt, false, rpkt->pkt_tag); crystalhd_hw_start_capture(ctx->hw_ctx); } else { ctx->state &= ~(BC_LINK_CAP_EN|BC_LINK_FMT_CHG); crystalhd_hw_stop_capture(ctx->hw_ctx, true); } return BC_STS_SUCCESS; } static BC_STATUS bc_cproc_get_stats(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { BC_DTS_STATS *stats; struct crystalhd_hw_stats hw_stats; uint32_t pic_width; uint8_t flags = 0; bool readTxOnly = false; unsigned long irqflags; if (!ctx || !idata) { dev_err(chddev(), "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } crystalhd_hw_stats(ctx->hw_ctx, &hw_stats); stats = &idata->udata.u.drvStat; stats->drvRLL = hw_stats.rdyq_count; stats->drvFLL = hw_stats.freeq_count; stats->DrvTotalFrmDropped = hw_stats.rx_errors; stats->DrvTotalHWErrs = hw_stats.rx_errors + hw_stats.tx_errors; stats->intCount = hw_stats.num_interrupts; stats->DrvIgnIntrCnt = hw_stats.num_interrupts - hw_stats.dev_interrupts; stats->TxFifoBsyCnt = hw_stats.cin_busy; stats->pauseCount = hw_stats.pause_cnt; /* Indicate that we are checking stats on the input buffer for a single threaded application */ /* this will prevent the HW from going to low power because we assume that once we have told the application */ /* that we have space in the HW, the app is going to try to DMA. And if we block that DMA, a single threaded application */ /* will deadlock */ if(stats->DrvNextMDataPLD & BC_BIT(31)) { flags |= 0x08; /* Also for single threaded applications, check to see if we have reduced the power down */ /* pause threshold to too low and increase it if the RLL is close to the threshold */ /* if(pDrvStat->drvRLL >= pDevExt->pHwExten->PauseThreshold) pDevExt->pHwExten->PauseThreshold++; PeekNextTS = TRUE;*/ } /* also indicate that we are just checking stats and not posting */ /* This allows multi-threaded applications to be placed into low power state */ /* because eveentually the RX thread will wake up the HW when needed */ flags |= 0x04; stats->pwr_state_change = ctx->pwr_state_change; if (ctx->state & BC_LINK_PAUSED) stats->DrvPauseTime = 1; /* use bit 29 of the input status to indicate that we are trying to read VC1 status */ /* This is important for the BCM70012 which uses a different input queue for VC1 */ if(stats->DrvcpbEmptySize & BC_BIT(29)) flags = 0x2; /* Bit 30 is used to indicate that we are reading only the TX stats and to not touch the Ready list */ if(stats->DrvcpbEmptySize & BC_BIT(30)) readTxOnly = true; spin_lock_irqsave(&ctx->hw_ctx->lock, irqflags); ctx->hw_ctx->pfnCheckInputFIFO(ctx->hw_ctx, 0, &stats->DrvcpbEmptySize, false, &flags); spin_unlock_irqrestore(&ctx->hw_ctx->lock, irqflags); /* status peek ahead to retreive the next decoded frame timestamp */ /* if (!readTxOnly && stats->drvRLL && (stats->DrvNextMDataPLD & BC_BIT(31))) { */ if (!readTxOnly && stats->drvRLL) { dev_dbg(chddev(), "Have Pictures %d\n", stats->drvRLL); pic_width = stats->DrvNextMDataPLD & 0xffff; stats->DrvNextMDataPLD = 0; if (pic_width <= 1920) { /* get fetch lock to make sure that fetch is not in progress as wel peek */ if(down_interruptible(&ctx->hw_ctx->fetch_sem)) goto get_out; if(ctx->hw_ctx->pfnPeekNextDeodedFr(ctx->hw_ctx,&stats->DrvNextMDataPLD, &stats->picNumFlags, pic_width)) { /* Check in case we dropped a picture here */ crystalhd_hw_stats(ctx->hw_ctx, &hw_stats); stats->drvRLL = hw_stats.rdyq_count; stats->drvFLL = hw_stats.freeq_count; } up(&ctx->hw_ctx->fetch_sem); dev_dbg(chddev(), "peeking done\n"); } } get_out: return BC_STS_SUCCESS; } static BC_STATUS bc_cproc_reset_stats(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { crystalhd_hw_stats(ctx->hw_ctx, NULL); return BC_STS_SUCCESS; } /** * * bc_cproc_release_user - Close Application Handle * * Used to be crystalhd_user_close * * @ctx: Command layer contextx. * @uc: User ID context. * * Return: * status * * Closer aplication handle and release app specific * resources. * * Move to IOCTL based implementation called from the RELEASE IOCTL */ BC_STATUS bc_cproc_release_user(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { struct device *dev = chddev(); uint32_t mode; if (!ctx || !idata) { dev_err(dev, "%s: Invalid Arg\n", __func__); return BC_STS_INV_ARG; } if (ctx->user[idata->u_id].mode == DTS_MODE_INV) { dev_err(dev, "Handle is already closed\n"); return BC_STS_ERR_USAGE; } mode = ctx->user[idata->u_id].mode; ctx->user[idata->u_id].mode = DTS_MODE_INV; ctx->user[idata->u_id].in_use = 0; dev_info(chddev(), "Closing user[%x] handle via ioctl with mode %x\n", idata->u_id, mode); if (((mode & 0xFF) == DTS_DIAG_MODE) || ((mode & 0xFF) == DTS_PLAYBACK_MODE) || ((bc_get_userhandle_count(ctx) == 0) && (ctx->hw_ctx != NULL))) { ctx->cin_wait_exit = 1; /* Stop the HW Capture just in case flush did not get called before stop */ ctx->pwr_state_change = BC_HW_RUNNING; crystalhd_hw_stop_capture(ctx->hw_ctx, true); crystalhd_hw_free_dma_rings(ctx->hw_ctx); crystalhd_destroy_dio_pool(ctx->adp); crystalhd_delete_elem_pool(ctx->adp); ctx->state = BC_LINK_INVALID; crystalhd_hw_close(ctx->hw_ctx, ctx->adp); kfree(ctx->hw_ctx); ctx->hw_ctx = NULL; } if(ctx->adp->cfg_users > 0) ctx->adp->cfg_users--; return BC_STS_SUCCESS; } /*=============== Cmd Proc Table.. ======================================*/ static const struct crystalhd_cmd_tbl g_crystalhd_cproc_tbl[] = { { BCM_IOC_GET_VERSION, bc_cproc_get_version, 0}, { BCM_IOC_GET_HWTYPE, bc_cproc_get_hwtype, 0}, { BCM_IOC_REG_RD, bc_cproc_reg_rd, 0}, { BCM_IOC_REG_WR, bc_cproc_reg_wr, 0}, { BCM_IOC_FPGA_RD, bc_cproc_link_reg_rd, 0}, { BCM_IOC_FPGA_WR, bc_cproc_link_reg_wr, 0}, { BCM_IOC_MEM_RD, bc_cproc_mem_rd, 0}, { BCM_IOC_MEM_WR, bc_cproc_mem_wr, 0}, { BCM_IOC_RD_PCI_CFG, bc_cproc_cfg_rd, 0}, { BCM_IOC_WR_PCI_CFG, bc_cproc_cfg_wr, 1}, { BCM_IOC_FW_DOWNLOAD, bc_cproc_download_fw, 1}, { BCM_IOC_FW_CMD, bc_cproc_do_fw_cmd, 1}, { BCM_IOC_PROC_INPUT, bc_cproc_proc_input, 1}, { BCM_IOC_ADD_RXBUFFS, bc_cproc_add_cap_buff, 1}, { BCM_IOC_FETCH_RXBUFF, bc_cproc_fetch_frame, 1}, { BCM_IOC_START_RX_CAP, bc_cproc_start_capture, 1}, { BCM_IOC_FLUSH_RX_CAP, bc_cproc_flush_cap_buffs, 1}, { BCM_IOC_GET_DRV_STAT, bc_cproc_get_stats, 0}, { BCM_IOC_RST_DRV_STAT, bc_cproc_reset_stats, 0}, { BCM_IOC_NOTIFY_MODE, bc_cproc_notify_mode, 0}, { BCM_IOC_RELEASE, bc_cproc_release_user, 0}, { BCM_IOC_END, NULL}, }; /*=============== Cmd Proc Functions.. ===================================*/ /** * crystalhd_suspend - Power management suspend request. * @ctx: Command layer context. * @idata: Iodata - required for internal use. * * Return: * status * * 1. Set the state to Suspend. * 2. Flush the Rx Buffers it will unmap all the buffers and * stop the RxDMA engine. * 3. Cancel The TX Io and Stop Dma Engine. * 4. Put the DDR in to deep sleep. * 5. Stop the hardware putting it in to Reset State. * * Current gstreamer frame work does not provide any power management * related notification to user mode decoder plug-in. As a work-around * we pass on the power mangement notification to our plug-in by completing * all outstanding requests with BC_STS_IO_USER_ABORT return code. */ BC_STATUS crystalhd_suspend(struct crystalhd_cmd *ctx, crystalhd_ioctl_data *idata) { struct device *dev = chddev(); BC_STATUS sts = BC_STS_SUCCESS; struct crystalhd_rx_dma_pkt *rpkt = NULL; if (!ctx || !idata) { dev_err(dev, "Invalid Parameters\n"); return BC_STS_ERROR; } if (ctx->state & BC_LINK_SUSPEND) return BC_STS_SUCCESS; if (ctx->state == BC_LINK_INVALID) { dev_dbg(dev, "Nothing To Do Suspend Success\n"); return BC_STS_SUCCESS; } dev_dbg(dev, "State before suspend is %x\n", ctx->state); bc_cproc_mark_pwr_state(ctx, BC_HW_SUSPEND); /* going to suspend */ if (ctx->state & BC_LINK_CAP_EN) { // Clean any pending RX crystalhd_hw_stop_capture(ctx->hw_ctx, false); while((rpkt = crystalhd_dioq_fetch(ctx->hw_ctx->rx_actq)) != NULL) crystalhd_dioq_add(ctx->hw_ctx->rx_freeq, rpkt, false, rpkt->pkt_tag); while((rpkt = crystalhd_dioq_fetch(ctx->hw_ctx->rx_rdyq)) != NULL) crystalhd_dioq_add(ctx->hw_ctx->rx_freeq, rpkt, false, rpkt->pkt_tag); } if (ctx->tx_list_id) { sts = crystalhd_hw_cancel_tx(ctx->hw_ctx, ctx->tx_list_id); if (sts != BC_STS_SUCCESS) return sts; } else { // Even if there is no active TX DMA need to stop and reset TX DMA pointers ctx->hw_ctx->pfnStopTxDMA(ctx->hw_ctx); } ctx->state = BC_LINK_SUSPEND; sts = crystalhd_hw_suspend(ctx->hw_ctx); if (sts != BC_STS_SUCCESS) return sts; dev_dbg(dev, "Crystal HD suspend success\n"); return BC_STS_SUCCESS; } /** * crystalhd_resume - Resume frame capture. * @ctx: Command layer contextx. * * Return: * status * * * Resume frame capture. * * PM_Resume can't resume the playback state back to pre-suspend state * because we don't keep video clip related information within driver. * To get back to the pre-suspend state App will re-open the device and * start a new playback session from the pre-suspend clip position. * */ BC_STATUS crystalhd_resume(struct crystalhd_cmd *ctx) { BC_STATUS sts = BC_STS_SUCCESS; sts = crystalhd_hw_resume(ctx->hw_ctx); if (sts != BC_STS_SUCCESS) return sts; bc_cproc_mark_pwr_state(ctx, BC_HW_RESUME); /* Starting resume */ ctx->state = BC_LINK_RESUME; dev_dbg(chddev(), "crystalhd_resume Success %x\n", ctx->state); return BC_STS_SUCCESS; } /** * crystalhd_user_open - Create application handle. * @ctx: Command layer contextx. * @user_ctx: User ID context. * * Return: * status * * Creates an application specific UID and allocates * application specific resources. HW layer initialization * is done for the first open request. */ BC_STATUS crystalhd_user_open(struct crystalhd_cmd *ctx, struct crystalhd_user **user_ctx) { struct device *dev = chddev(); struct crystalhd_user *uc; if (!ctx || !user_ctx) { dev_err(dev, "Invalid arg..\n"); return BC_STS_INV_ARG; } uc = bc_cproc_get_uid(ctx); if (!uc) { dev_info(dev, "No free user context...\n"); return BC_STS_BUSY; } dev_info(dev, "Opening new user[%x] handle\n", uc->uid); uc->mode = DTS_MODE_INV; uc->in_use = 0; if(ctx->hw_ctx == NULL) { ctx->hw_ctx = (struct crystalhd_hw*)kmalloc(sizeof(struct crystalhd_hw), GFP_KERNEL); if(ctx->hw_ctx != NULL) memset(ctx->hw_ctx, 0, sizeof(struct crystalhd_hw)); else return BC_STS_ERROR; crystalhd_hw_open(ctx->hw_ctx, ctx->adp); } uc->in_use = 1; *user_ctx = uc; ctx->pwr_state_change = BC_HW_RUNNING; return BC_STS_SUCCESS; } /** * crystalhd_setup_cmd_context - Setup Command layer resources. * @ctx: Command layer contextx. * @adp: Adapter context * * Return: * status * * Called at the time of driver load. */ BC_STATUS __devinit crystalhd_setup_cmd_context(struct crystalhd_cmd *ctx, struct crystalhd_adp *adp) { struct device *dev = &adp->pdev->dev; int i = 0; if (!ctx || !adp) { dev_err(dev, "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } if (ctx->adp) dev_dbg(dev, "Resetting Cmd context delete missing..\n"); ctx->adp = adp; for (i = 0; i < BC_LINK_MAX_OPENS; i++) { ctx->user[i].uid = i; ctx->user[i].in_use = 0; ctx->user[i].mode = DTS_MODE_INV; } ctx->hw_ctx = (struct crystalhd_hw*)kmalloc(sizeof(struct crystalhd_hw), GFP_KERNEL); memset(ctx->hw_ctx, 0, sizeof(struct crystalhd_hw)); /*Open and Close the Hardware to put it in to sleep state*/ crystalhd_hw_open(ctx->hw_ctx, ctx->adp); crystalhd_hw_close(ctx->hw_ctx, ctx->adp); kfree(ctx->hw_ctx); ctx->hw_ctx = NULL; return BC_STS_SUCCESS; } /** * crystalhd_delete_cmd_context - Release Command layer resources. * @ctx: Command layer contextx. * * Return: * status * * Called at the time of driver un-load. */ BC_STATUS __devexit crystalhd_delete_cmd_context(struct crystalhd_cmd *ctx) { dev_dbg(chddev(), "Deleting Command context..\n"); ctx->adp = NULL; return BC_STS_SUCCESS; } /** * crystalhd_get_cmd_proc - Cproc table lookup. * @ctx: Command layer contextx. * @cmd: IOCTL command code. * @uc: User ID context. * * Return: * command proc function pointer * * This function checks the process context, application's * mode of operation and returns the function pointer * from the cproc table. */ crystalhd_cmd_proc crystalhd_get_cmd_proc(struct crystalhd_cmd *ctx, uint32_t cmd, struct crystalhd_user *uc) { struct device *dev = chddev(); crystalhd_cmd_proc cproc = NULL; unsigned int i, tbl_sz; if (!ctx) { dev_err(dev, "Invalid arg.. Cmd[%d]\n", cmd); return NULL; } if ((cmd != BCM_IOC_GET_DRV_STAT) && (ctx->state & BC_LINK_SUSPEND)) { dev_err(dev, "Invalid State [suspend Set].. Cmd[%x]\n", cmd); return NULL; } tbl_sz = sizeof(g_crystalhd_cproc_tbl) / sizeof(struct crystalhd_cmd_tbl); for (i = 0; i < tbl_sz; i++) { if (g_crystalhd_cproc_tbl[i].cmd_id == cmd) { if ((uc->mode == DTS_MONITOR_MODE) && (g_crystalhd_cproc_tbl[i].block_mon)) { dev_dbg(dev, "Blocking cmd %d \n", cmd); break; } cproc = g_crystalhd_cproc_tbl[i].cmd_proc; break; } } return cproc; } /** * crystalhd_cmd_interrupt - ISR entry point * @ctx: Command layer contextx. * * Return: * TRUE: If interrupt from CrystalHD device. * * * ISR entry point from OS layer. */ bool crystalhd_cmd_interrupt(struct crystalhd_cmd *ctx) { if (!ctx) { printk(KERN_ERR "%s: Invalid arg..\n", __func__); return false; } /* If HW has not been initialized then all interrupts are spurious */ if ((ctx->hw_ctx == NULL) || (ctx->hw_ctx->pfnFindAndClearIntr == NULL)) return false; return ctx->hw_ctx->pfnFindAndClearIntr(ctx->adp, ctx->hw_ctx); } crystalhd-0.0~git20110715.fdd2f19/driver/linux/configure0000755000175000017500000024636311610313113022106 0ustar andresandres#! /bin/sh # Guess values for system-dependent variables and create Makefiles. # Generated by GNU Autoconf 2.68. # # # Copyright (C) 1992, 1993, 1994, 1995, 1996, 1998, 1999, 2000, 2001, # 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010 Free Software # Foundation, Inc. # # # This configure script is free software; the Free Software Foundation # gives unlimited permission to copy, distribute and modify it. ## -------------------- ## ## M4sh Initialization. ## ## -------------------- ## # Be more Bourne compatible DUALCASE=1; export DUALCASE # for MKS sh if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : emulate sh NULLCMD=: # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which # is contrary to our usage. Disable this feature. alias -g '${1+"$@"}'='"$@"' setopt NO_GLOB_SUBST else case `(set -o) 2>/dev/null` in #( *posix*) : set -o posix ;; #( *) : ;; esac fi as_nl=' ' export as_nl # Printing a long string crashes Solaris 7 /usr/bin/printf. as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo # Prefer a ksh shell builtin over an external printf program on Solaris, # but without wasting forks for bash or zsh. if test -z "$BASH_VERSION$ZSH_VERSION" \ && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then as_echo='print -r --' as_echo_n='print -rn --' elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then as_echo='printf %s\n' as_echo_n='printf %s' else if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' as_echo_n='/usr/ucb/echo -n' else as_echo_body='eval expr "X$1" : "X\\(.*\\)"' as_echo_n_body='eval arg=$1; case $arg in #( *"$as_nl"*) expr "X$arg" : "X\\(.*\\)$as_nl"; arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; esac; expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" ' export as_echo_n_body as_echo_n='sh -c $as_echo_n_body as_echo' fi export as_echo_body as_echo='sh -c $as_echo_body as_echo' fi # The user is always right. if test "${PATH_SEPARATOR+set}" != set; then PATH_SEPARATOR=: (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || PATH_SEPARATOR=';' } fi # IFS # We need space, tab and new line, in precisely that order. Quoting is # there to prevent editors from complaining about space-tab. # (If _AS_PATH_WALK were called with IFS unset, it would disable word # splitting by setting IFS to empty value.) IFS=" "" $as_nl" # Find who we are. Look in the path if we contain no directory separator. as_myself= case $0 in #(( *[\\/]* ) as_myself=$0 ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break done IFS=$as_save_IFS ;; esac # We did not find ourselves, most probably we were run as `sh COMMAND' # in which case we are not to be found in the path. if test "x$as_myself" = x; then as_myself=$0 fi if test ! -f "$as_myself"; then $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 exit 1 fi # Unset variables that we do not need and which cause bugs (e.g. in # pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" # suppresses any "Segmentation fault" message there. '((' could # trigger a bug in pdksh 5.2.14. for as_var in BASH_ENV ENV MAIL MAILPATH do eval test x\${$as_var+set} = xset \ && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : done PS1='$ ' PS2='> ' PS4='+ ' # NLS nuisances. LC_ALL=C export LC_ALL LANGUAGE=C export LANGUAGE # CDPATH. (unset CDPATH) >/dev/null 2>&1 && unset CDPATH if test "x$CONFIG_SHELL" = x; then as_bourne_compatible="if test -n \"\${ZSH_VERSION+set}\" && (emulate sh) >/dev/null 2>&1; then : emulate sh NULLCMD=: # Pre-4.2 versions of Zsh do word splitting on \${1+\"\$@\"}, which # is contrary to our usage. Disable this feature. alias -g '\${1+\"\$@\"}'='\"\$@\"' setopt NO_GLOB_SUBST else case \`(set -o) 2>/dev/null\` in #( *posix*) : set -o posix ;; #( *) : ;; esac fi " as_required="as_fn_return () { (exit \$1); } as_fn_success () { as_fn_return 0; } as_fn_failure () { as_fn_return 1; } as_fn_ret_success () { return 0; } as_fn_ret_failure () { return 1; } exitcode=0 as_fn_success || { exitcode=1; echo as_fn_success failed.; } as_fn_failure && { exitcode=1; echo as_fn_failure succeeded.; } as_fn_ret_success || { exitcode=1; echo as_fn_ret_success failed.; } as_fn_ret_failure && { exitcode=1; echo as_fn_ret_failure succeeded.; } if ( set x; as_fn_ret_success y && test x = \"\$1\" ); then : else exitcode=1; echo positional parameters were not saved. fi test x\$exitcode = x0 || exit 1" as_suggested=" as_lineno_1=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_1a=\$LINENO as_lineno_2=";as_suggested=$as_suggested$LINENO;as_suggested=$as_suggested" as_lineno_2a=\$LINENO eval 'test \"x\$as_lineno_1'\$as_run'\" != \"x\$as_lineno_2'\$as_run'\" && test \"x\`expr \$as_lineno_1'\$as_run' + 1\`\" = \"x\$as_lineno_2'\$as_run'\"' || exit 1" if (eval "$as_required") 2>/dev/null; then : as_have_required=yes else as_have_required=no fi if test x$as_have_required = xyes && (eval "$as_suggested") 2>/dev/null; then : else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR as_found=false for as_dir in /bin$PATH_SEPARATOR/usr/bin$PATH_SEPARATOR$PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. as_found=: case $as_dir in #( /*) for as_base in sh bash ksh sh5; do # Try only shells that exist, to save several forks. as_shell=$as_dir/$as_base if { test -f "$as_shell" || test -f "$as_shell.exe"; } && { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$as_shell"; } 2>/dev/null; then : CONFIG_SHELL=$as_shell as_have_required=yes if { $as_echo "$as_bourne_compatible""$as_suggested" | as_run=a "$as_shell"; } 2>/dev/null; then : break 2 fi fi done;; esac as_found=false done $as_found || { if { test -f "$SHELL" || test -f "$SHELL.exe"; } && { $as_echo "$as_bourne_compatible""$as_required" | as_run=a "$SHELL"; } 2>/dev/null; then : CONFIG_SHELL=$SHELL as_have_required=yes fi; } IFS=$as_save_IFS if test "x$CONFIG_SHELL" != x; then : # We cannot yet assume a decent shell, so we have to provide a # neutralization value for shells without unset; and this also # works around shells that cannot unset nonexistent variables. # Preserve -v and -x to the replacement shell. BASH_ENV=/dev/null ENV=/dev/null (unset BASH_ENV) >/dev/null 2>&1 && unset BASH_ENV ENV export CONFIG_SHELL case $- in # (((( *v*x* | *x*v* ) as_opts=-vx ;; *v* ) as_opts=-v ;; *x* ) as_opts=-x ;; * ) as_opts= ;; esac exec "$CONFIG_SHELL" $as_opts "$as_myself" ${1+"$@"} fi if test x$as_have_required = xno; then : $as_echo "$0: This script requires a shell more modern than all" $as_echo "$0: the shells that I found on your system." if test x${ZSH_VERSION+set} = xset ; then $as_echo "$0: In particular, zsh $ZSH_VERSION has bugs and should" $as_echo "$0: be upgraded to zsh 4.3.4 or later." else $as_echo "$0: Please tell bug-autoconf@gnu.org about your system, $0: including any error possibly output before this $0: message. Then install a modern shell, or manually run $0: the script under such a shell if you do have one." fi exit 1 fi fi fi SHELL=${CONFIG_SHELL-/bin/sh} export SHELL # Unset more variables known to interfere with behavior of common tools. CLICOLOR_FORCE= GREP_OPTIONS= unset CLICOLOR_FORCE GREP_OPTIONS ## --------------------- ## ## M4sh Shell Functions. ## ## --------------------- ## # as_fn_unset VAR # --------------- # Portably unset VAR. as_fn_unset () { { eval $1=; unset $1;} } as_unset=as_fn_unset # as_fn_set_status STATUS # ----------------------- # Set $? to STATUS, without forking. as_fn_set_status () { return $1 } # as_fn_set_status # as_fn_exit STATUS # ----------------- # Exit the shell with STATUS, even in a "trap 0" or "set -e" context. as_fn_exit () { set +e as_fn_set_status $1 exit $1 } # as_fn_exit # as_fn_mkdir_p # ------------- # Create "$as_dir" as a directory, including parents if necessary. as_fn_mkdir_p () { case $as_dir in #( -*) as_dir=./$as_dir;; esac test -d "$as_dir" || eval $as_mkdir_p || { as_dirs= while :; do case $as_dir in #( *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( *) as_qdir=$as_dir;; esac as_dirs="'$as_qdir' $as_dirs" as_dir=`$as_dirname -- "$as_dir" || $as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ X"$as_dir" : 'X\(//\)[^/]' \| \ X"$as_dir" : 'X\(//\)$' \| \ X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || $as_echo X"$as_dir" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/ q } /^X\(\/\/\)[^/].*/{ s//\1/ q } /^X\(\/\/\)$/{ s//\1/ q } /^X\(\/\).*/{ s//\1/ q } s/.*/./; q'` test -d "$as_dir" && break done test -z "$as_dirs" || eval "mkdir $as_dirs" } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir" } # as_fn_mkdir_p # as_fn_append VAR VALUE # ---------------------- # Append the text in VALUE to the end of the definition contained in VAR. Take # advantage of any shell optimizations that allow amortized linear growth over # repeated appends, instead of the typical quadratic growth present in naive # implementations. if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : eval 'as_fn_append () { eval $1+=\$2 }' else as_fn_append () { eval $1=\$$1\$2 } fi # as_fn_append # as_fn_arith ARG... # ------------------ # Perform arithmetic evaluation on the ARGs, and store the result in the # global $as_val. Take advantage of shells that can avoid forks. The arguments # must be portable across $(()) and expr. if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : eval 'as_fn_arith () { as_val=$(( $* )) }' else as_fn_arith () { as_val=`expr "$@" || test $? -eq 1` } fi # as_fn_arith # as_fn_error STATUS ERROR [LINENO LOG_FD] # ---------------------------------------- # Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are # provided, also output the error to LOG_FD, referencing LINENO. Then exit the # script with STATUS, using 1 if that was 0. as_fn_error () { as_status=$1; test $as_status -eq 0 && as_status=1 if test "$4"; then as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 fi $as_echo "$as_me: error: $2" >&2 as_fn_exit $as_status } # as_fn_error if expr a : '\(a\)' >/dev/null 2>&1 && test "X`expr 00001 : '.*\(...\)'`" = X001; then as_expr=expr else as_expr=false fi if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then as_basename=basename else as_basename=false fi if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then as_dirname=dirname else as_dirname=false fi as_me=`$as_basename -- "$0" || $as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ X"$0" : 'X\(//\)$' \| \ X"$0" : 'X\(/\)' \| . 2>/dev/null || $as_echo X/"$0" | sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/ q } /^X\/\(\/\/\)$/{ s//\1/ q } /^X\/\(\/\).*/{ s//\1/ q } s/.*/./; q'` # Avoid depending upon Character Ranges. as_cr_letters='abcdefghijklmnopqrstuvwxyz' as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' as_cr_Letters=$as_cr_letters$as_cr_LETTERS as_cr_digits='0123456789' as_cr_alnum=$as_cr_Letters$as_cr_digits as_lineno_1=$LINENO as_lineno_1a=$LINENO as_lineno_2=$LINENO as_lineno_2a=$LINENO eval 'test "x$as_lineno_1'$as_run'" != "x$as_lineno_2'$as_run'" && test "x`expr $as_lineno_1'$as_run' + 1`" = "x$as_lineno_2'$as_run'"' || { # Blame Lee E. McMahon (1931-1989) for sed's syntax. :-) sed -n ' p /[$]LINENO/= ' <$as_myself | sed ' s/[$]LINENO.*/&-/ t lineno b :lineno N :loop s/[$]LINENO\([^'$as_cr_alnum'_].*\n\)\(.*\)/\2\1\2/ t loop s/-\n.*// ' >$as_me.lineno && chmod +x "$as_me.lineno" || { $as_echo "$as_me: error: cannot create $as_me.lineno; rerun with a POSIX shell" >&2; as_fn_exit 1; } # Don't try to exec as it changes $[0], causing all sort of problems # (the dirname of $[0] is not the place where we might find the # original and so on. Autoconf is especially sensitive to this). . "./$as_me.lineno" # Exit status is that of the last command. exit } ECHO_C= ECHO_N= ECHO_T= case `echo -n x` in #((((( -n*) case `echo 'xy\c'` in *c*) ECHO_T=' ';; # ECHO_T is single tab character. xy) ECHO_C='\c';; *) echo `echo ksh88 bug on AIX 6.1` > /dev/null ECHO_T=' ';; esac;; *) ECHO_N='-n';; esac rm -f conf$$ conf$$.exe conf$$.file if test -d conf$$.dir; then rm -f conf$$.dir/conf$$.file else rm -f conf$$.dir mkdir conf$$.dir 2>/dev/null fi if (echo >conf$$.file) 2>/dev/null; then if ln -s conf$$.file conf$$ 2>/dev/null; then as_ln_s='ln -s' # ... but there are two gotchas: # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. # In both cases, we have to default to `cp -p'. ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || as_ln_s='cp -p' elif ln conf$$.file conf$$ 2>/dev/null; then as_ln_s=ln else as_ln_s='cp -p' fi else as_ln_s='cp -p' fi rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file rmdir conf$$.dir 2>/dev/null if mkdir -p . 2>/dev/null; then as_mkdir_p='mkdir -p "$as_dir"' else test -d ./-p && rmdir ./-p as_mkdir_p=false fi if test -x / >/dev/null 2>&1; then as_test_x='test -x' else if ls -dL / >/dev/null 2>&1; then as_ls_L_option=L else as_ls_L_option= fi as_test_x=' eval sh -c '\'' if test -d "$1"; then test -d "$1/."; else case $1 in #( -*)set "./$1";; esac; case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( ???[sx]*):;;*)false;;esac;fi '\'' sh ' fi as_executable_p=$as_test_x # Sed expression to map a string onto a valid CPP name. as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" # Sed expression to map a string onto a valid variable name. as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" test -n "$DJDIR" || exec 7<&0 &1 # Name of the host. # hostname on some systems (SVR3.2, old GNU/Linux) returns a bogus exit status, # so uname gets run too. ac_hostname=`(hostname || uname -n) 2>/dev/null | sed 1q` # # Initializations. # ac_default_prefix=/usr/local ac_clean_files= ac_config_libobj_dir=. LIBOBJS= cross_compiling=no subdirs= MFLAGS= MAKEFLAGS= # Identity of this package. PACKAGE_NAME= PACKAGE_TARNAME= PACKAGE_VERSION= PACKAGE_STRING= PACKAGE_BUGREPORT= PACKAGE_URL= ac_unique_file="configure.ac" ac_subst_vars='LTLIBOBJS LIBOBJS KERN_DIR LD target_alias host_alias build_alias LIBS ECHO_T ECHO_N ECHO_C DEFS mandir localedir libdir psdir pdfdir dvidir htmldir infodir docdir oldincludedir includedir localstatedir sharedstatedir sysconfdir datadir datarootdir libexecdir sbindir bindir program_transform_name prefix exec_prefix PACKAGE_URL PACKAGE_BUGREPORT PACKAGE_STRING PACKAGE_VERSION PACKAGE_TARNAME PACKAGE_NAME PATH_SEPARATOR SHELL' ac_subst_files='' ac_user_opts=' enable_option_checking with_kernel_path ' ac_precious_vars='build_alias host_alias target_alias' # Initialize some variables set by options. ac_init_help= ac_init_version=false ac_unrecognized_opts= ac_unrecognized_sep= # The variables have the same names as the options, with # dashes changed to underlines. cache_file=/dev/null exec_prefix=NONE no_create= no_recursion= prefix=NONE program_prefix=NONE program_suffix=NONE program_transform_name=s,x,x, silent= site= srcdir= verbose= x_includes=NONE x_libraries=NONE # Installation directory options. # These are left unexpanded so users can "make install exec_prefix=/foo" # and all the variables that are supposed to be based on exec_prefix # by default will actually change. # Use braces instead of parens because sh, perl, etc. also accept them. # (The list follows the same order as the GNU Coding Standards.) bindir='${exec_prefix}/bin' sbindir='${exec_prefix}/sbin' libexecdir='${exec_prefix}/libexec' datarootdir='${prefix}/share' datadir='${datarootdir}' sysconfdir='${prefix}/etc' sharedstatedir='${prefix}/com' localstatedir='${prefix}/var' includedir='${prefix}/include' oldincludedir='/usr/include' docdir='${datarootdir}/doc/${PACKAGE}' infodir='${datarootdir}/info' htmldir='${docdir}' dvidir='${docdir}' pdfdir='${docdir}' psdir='${docdir}' libdir='${exec_prefix}/lib' localedir='${datarootdir}/locale' mandir='${datarootdir}/man' ac_prev= ac_dashdash= for ac_option do # If the previous option needs an argument, assign it. if test -n "$ac_prev"; then eval $ac_prev=\$ac_option ac_prev= continue fi case $ac_option in *=?*) ac_optarg=`expr "X$ac_option" : '[^=]*=\(.*\)'` ;; *=) ac_optarg= ;; *) ac_optarg=yes ;; esac # Accept the important Cygnus configure options, so we can diagnose typos. case $ac_dashdash$ac_option in --) ac_dashdash=yes ;; -bindir | --bindir | --bindi | --bind | --bin | --bi) ac_prev=bindir ;; -bindir=* | --bindir=* | --bindi=* | --bind=* | --bin=* | --bi=*) bindir=$ac_optarg ;; -build | --build | --buil | --bui | --bu) ac_prev=build_alias ;; -build=* | --build=* | --buil=* | --bui=* | --bu=*) build_alias=$ac_optarg ;; -cache-file | --cache-file | --cache-fil | --cache-fi \ | --cache-f | --cache- | --cache | --cach | --cac | --ca | --c) ac_prev=cache_file ;; -cache-file=* | --cache-file=* | --cache-fil=* | --cache-fi=* \ | --cache-f=* | --cache-=* | --cache=* | --cach=* | --cac=* | --ca=* | --c=*) cache_file=$ac_optarg ;; --config-cache | -C) cache_file=config.cache ;; -datadir | --datadir | --datadi | --datad) ac_prev=datadir ;; -datadir=* | --datadir=* | --datadi=* | --datad=*) datadir=$ac_optarg ;; -datarootdir | --datarootdir | --datarootdi | --datarootd | --dataroot \ | --dataroo | --dataro | --datar) ac_prev=datarootdir ;; -datarootdir=* | --datarootdir=* | --datarootdi=* | --datarootd=* \ | --dataroot=* | --dataroo=* | --dataro=* | --datar=*) datarootdir=$ac_optarg ;; -disable-* | --disable-*) ac_useropt=`expr "x$ac_option" : 'x-*disable-\(.*\)'` # Reject names that are not valid shell variable names. expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && as_fn_error $? "invalid feature name: $ac_useropt" ac_useropt_orig=$ac_useropt ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` case $ac_user_opts in *" "enable_$ac_useropt" "*) ;; *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--disable-$ac_useropt_orig" ac_unrecognized_sep=', ';; esac eval enable_$ac_useropt=no ;; -docdir | --docdir | --docdi | --doc | --do) ac_prev=docdir ;; -docdir=* | --docdir=* | --docdi=* | --doc=* | --do=*) docdir=$ac_optarg ;; -dvidir | --dvidir | --dvidi | --dvid | --dvi | --dv) ac_prev=dvidir ;; -dvidir=* | --dvidir=* | --dvidi=* | --dvid=* | --dvi=* | --dv=*) dvidir=$ac_optarg ;; -enable-* | --enable-*) ac_useropt=`expr "x$ac_option" : 'x-*enable-\([^=]*\)'` # Reject names that are not valid shell variable names. expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && as_fn_error $? "invalid feature name: $ac_useropt" ac_useropt_orig=$ac_useropt ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` case $ac_user_opts in *" "enable_$ac_useropt" "*) ;; *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--enable-$ac_useropt_orig" ac_unrecognized_sep=', ';; esac eval enable_$ac_useropt=\$ac_optarg ;; -exec-prefix | --exec_prefix | --exec-prefix | --exec-prefi \ | --exec-pref | --exec-pre | --exec-pr | --exec-p | --exec- \ | --exec | --exe | --ex) ac_prev=exec_prefix ;; -exec-prefix=* | --exec_prefix=* | --exec-prefix=* | --exec-prefi=* \ | --exec-pref=* | --exec-pre=* | --exec-pr=* | --exec-p=* | --exec-=* \ | --exec=* | --exe=* | --ex=*) exec_prefix=$ac_optarg ;; -gas | --gas | --ga | --g) # Obsolete; use --with-gas. with_gas=yes ;; -help | --help | --hel | --he | -h) ac_init_help=long ;; -help=r* | --help=r* | --hel=r* | --he=r* | -hr*) ac_init_help=recursive ;; -help=s* | --help=s* | --hel=s* | --he=s* | -hs*) ac_init_help=short ;; -host | --host | --hos | --ho) ac_prev=host_alias ;; -host=* | --host=* | --hos=* | --ho=*) host_alias=$ac_optarg ;; -htmldir | --htmldir | --htmldi | --htmld | --html | --htm | --ht) ac_prev=htmldir ;; -htmldir=* | --htmldir=* | --htmldi=* | --htmld=* | --html=* | --htm=* \ | --ht=*) htmldir=$ac_optarg ;; -includedir | --includedir | --includedi | --included | --include \ | --includ | --inclu | --incl | --inc) ac_prev=includedir ;; -includedir=* | --includedir=* | --includedi=* | --included=* | --include=* \ | --includ=* | --inclu=* | --incl=* | --inc=*) includedir=$ac_optarg ;; -infodir | --infodir | --infodi | --infod | --info | --inf) ac_prev=infodir ;; -infodir=* | --infodir=* | --infodi=* | --infod=* | --info=* | --inf=*) infodir=$ac_optarg ;; -libdir | --libdir | --libdi | --libd) ac_prev=libdir ;; -libdir=* | --libdir=* | --libdi=* | --libd=*) libdir=$ac_optarg ;; -libexecdir | --libexecdir | --libexecdi | --libexecd | --libexec \ | --libexe | --libex | --libe) ac_prev=libexecdir ;; -libexecdir=* | --libexecdir=* | --libexecdi=* | --libexecd=* | --libexec=* \ | --libexe=* | --libex=* | --libe=*) libexecdir=$ac_optarg ;; -localedir | --localedir | --localedi | --localed | --locale) ac_prev=localedir ;; -localedir=* | --localedir=* | --localedi=* | --localed=* | --locale=*) localedir=$ac_optarg ;; -localstatedir | --localstatedir | --localstatedi | --localstated \ | --localstate | --localstat | --localsta | --localst | --locals) ac_prev=localstatedir ;; -localstatedir=* | --localstatedir=* | --localstatedi=* | --localstated=* \ | --localstate=* | --localstat=* | --localsta=* | --localst=* | --locals=*) localstatedir=$ac_optarg ;; -mandir | --mandir | --mandi | --mand | --man | --ma | --m) ac_prev=mandir ;; -mandir=* | --mandir=* | --mandi=* | --mand=* | --man=* | --ma=* | --m=*) mandir=$ac_optarg ;; -nfp | --nfp | --nf) # Obsolete; use --without-fp. with_fp=no ;; -no-create | --no-create | --no-creat | --no-crea | --no-cre \ | --no-cr | --no-c | -n) no_create=yes ;; -no-recursion | --no-recursion | --no-recursio | --no-recursi \ | --no-recurs | --no-recur | --no-recu | --no-rec | --no-re | --no-r) no_recursion=yes ;; -oldincludedir | --oldincludedir | --oldincludedi | --oldincluded \ | --oldinclude | --oldinclud | --oldinclu | --oldincl | --oldinc \ | --oldin | --oldi | --old | --ol | --o) ac_prev=oldincludedir ;; -oldincludedir=* | --oldincludedir=* | --oldincludedi=* | --oldincluded=* \ | --oldinclude=* | --oldinclud=* | --oldinclu=* | --oldincl=* | --oldinc=* \ | --oldin=* | --oldi=* | --old=* | --ol=* | --o=*) oldincludedir=$ac_optarg ;; -prefix | --prefix | --prefi | --pref | --pre | --pr | --p) ac_prev=prefix ;; -prefix=* | --prefix=* | --prefi=* | --pref=* | --pre=* | --pr=* | --p=*) prefix=$ac_optarg ;; -program-prefix | --program-prefix | --program-prefi | --program-pref \ | --program-pre | --program-pr | --program-p) ac_prev=program_prefix ;; -program-prefix=* | --program-prefix=* | --program-prefi=* \ | --program-pref=* | --program-pre=* | --program-pr=* | --program-p=*) program_prefix=$ac_optarg ;; -program-suffix | --program-suffix | --program-suffi | --program-suff \ | --program-suf | --program-su | --program-s) ac_prev=program_suffix ;; -program-suffix=* | --program-suffix=* | --program-suffi=* \ | --program-suff=* | --program-suf=* | --program-su=* | --program-s=*) program_suffix=$ac_optarg ;; -program-transform-name | --program-transform-name \ | --program-transform-nam | --program-transform-na \ | --program-transform-n | --program-transform- \ | --program-transform | --program-transfor \ | --program-transfo | --program-transf \ | --program-trans | --program-tran \ | --progr-tra | --program-tr | --program-t) ac_prev=program_transform_name ;; -program-transform-name=* | --program-transform-name=* \ | --program-transform-nam=* | --program-transform-na=* \ | --program-transform-n=* | --program-transform-=* \ | --program-transform=* | --program-transfor=* \ | --program-transfo=* | --program-transf=* \ | --program-trans=* | --program-tran=* \ | --progr-tra=* | --program-tr=* | --program-t=*) program_transform_name=$ac_optarg ;; -pdfdir | --pdfdir | --pdfdi | --pdfd | --pdf | --pd) ac_prev=pdfdir ;; -pdfdir=* | --pdfdir=* | --pdfdi=* | --pdfd=* | --pdf=* | --pd=*) pdfdir=$ac_optarg ;; -psdir | --psdir | --psdi | --psd | --ps) ac_prev=psdir ;; -psdir=* | --psdir=* | --psdi=* | --psd=* | --ps=*) psdir=$ac_optarg ;; -q | -quiet | --quiet | --quie | --qui | --qu | --q \ | -silent | --silent | --silen | --sile | --sil) silent=yes ;; -sbindir | --sbindir | --sbindi | --sbind | --sbin | --sbi | --sb) ac_prev=sbindir ;; -sbindir=* | --sbindir=* | --sbindi=* | --sbind=* | --sbin=* \ | --sbi=* | --sb=*) sbindir=$ac_optarg ;; -sharedstatedir | --sharedstatedir | --sharedstatedi \ | --sharedstated | --sharedstate | --sharedstat | --sharedsta \ | --sharedst | --shareds | --shared | --share | --shar \ | --sha | --sh) ac_prev=sharedstatedir ;; -sharedstatedir=* | --sharedstatedir=* | --sharedstatedi=* \ | --sharedstated=* | --sharedstate=* | --sharedstat=* | --sharedsta=* \ | --sharedst=* | --shareds=* | --shared=* | --share=* | --shar=* \ | --sha=* | --sh=*) sharedstatedir=$ac_optarg ;; -site | --site | --sit) ac_prev=site ;; -site=* | --site=* | --sit=*) site=$ac_optarg ;; -srcdir | --srcdir | --srcdi | --srcd | --src | --sr) ac_prev=srcdir ;; -srcdir=* | --srcdir=* | --srcdi=* | --srcd=* | --src=* | --sr=*) srcdir=$ac_optarg ;; -sysconfdir | --sysconfdir | --sysconfdi | --sysconfd | --sysconf \ | --syscon | --sysco | --sysc | --sys | --sy) ac_prev=sysconfdir ;; -sysconfdir=* | --sysconfdir=* | --sysconfdi=* | --sysconfd=* | --sysconf=* \ | --syscon=* | --sysco=* | --sysc=* | --sys=* | --sy=*) sysconfdir=$ac_optarg ;; -target | --target | --targe | --targ | --tar | --ta | --t) ac_prev=target_alias ;; -target=* | --target=* | --targe=* | --targ=* | --tar=* | --ta=* | --t=*) target_alias=$ac_optarg ;; -v | -verbose | --verbose | --verbos | --verbo | --verb) verbose=yes ;; -version | --version | --versio | --versi | --vers | -V) ac_init_version=: ;; -with-* | --with-*) ac_useropt=`expr "x$ac_option" : 'x-*with-\([^=]*\)'` # Reject names that are not valid shell variable names. expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && as_fn_error $? "invalid package name: $ac_useropt" ac_useropt_orig=$ac_useropt ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` case $ac_user_opts in *" "with_$ac_useropt" "*) ;; *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--with-$ac_useropt_orig" ac_unrecognized_sep=', ';; esac eval with_$ac_useropt=\$ac_optarg ;; -without-* | --without-*) ac_useropt=`expr "x$ac_option" : 'x-*without-\(.*\)'` # Reject names that are not valid shell variable names. expr "x$ac_useropt" : ".*[^-+._$as_cr_alnum]" >/dev/null && as_fn_error $? "invalid package name: $ac_useropt" ac_useropt_orig=$ac_useropt ac_useropt=`$as_echo "$ac_useropt" | sed 's/[-+.]/_/g'` case $ac_user_opts in *" "with_$ac_useropt" "*) ;; *) ac_unrecognized_opts="$ac_unrecognized_opts$ac_unrecognized_sep--without-$ac_useropt_orig" ac_unrecognized_sep=', ';; esac eval with_$ac_useropt=no ;; --x) # Obsolete; use --with-x. with_x=yes ;; -x-includes | --x-includes | --x-include | --x-includ | --x-inclu \ | --x-incl | --x-inc | --x-in | --x-i) ac_prev=x_includes ;; -x-includes=* | --x-includes=* | --x-include=* | --x-includ=* | --x-inclu=* \ | --x-incl=* | --x-inc=* | --x-in=* | --x-i=*) x_includes=$ac_optarg ;; -x-libraries | --x-libraries | --x-librarie | --x-librari \ | --x-librar | --x-libra | --x-libr | --x-lib | --x-li | --x-l) ac_prev=x_libraries ;; -x-libraries=* | --x-libraries=* | --x-librarie=* | --x-librari=* \ | --x-librar=* | --x-libra=* | --x-libr=* | --x-lib=* | --x-li=* | --x-l=*) x_libraries=$ac_optarg ;; -*) as_fn_error $? "unrecognized option: \`$ac_option' Try \`$0 --help' for more information" ;; *=*) ac_envvar=`expr "x$ac_option" : 'x\([^=]*\)='` # Reject names that are not valid shell variable names. case $ac_envvar in #( '' | [0-9]* | *[!_$as_cr_alnum]* ) as_fn_error $? "invalid variable name: \`$ac_envvar'" ;; esac eval $ac_envvar=\$ac_optarg export $ac_envvar ;; *) # FIXME: should be removed in autoconf 3.0. $as_echo "$as_me: WARNING: you should use --build, --host, --target" >&2 expr "x$ac_option" : ".*[^-._$as_cr_alnum]" >/dev/null && $as_echo "$as_me: WARNING: invalid host type: $ac_option" >&2 : "${build_alias=$ac_option} ${host_alias=$ac_option} ${target_alias=$ac_option}" ;; esac done if test -n "$ac_prev"; then ac_option=--`echo $ac_prev | sed 's/_/-/g'` as_fn_error $? "missing argument to $ac_option" fi if test -n "$ac_unrecognized_opts"; then case $enable_option_checking in no) ;; fatal) as_fn_error $? "unrecognized options: $ac_unrecognized_opts" ;; *) $as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2 ;; esac fi # Check all directory arguments for consistency. for ac_var in exec_prefix prefix bindir sbindir libexecdir datarootdir \ datadir sysconfdir sharedstatedir localstatedir includedir \ oldincludedir docdir infodir htmldir dvidir pdfdir psdir \ libdir localedir mandir do eval ac_val=\$$ac_var # Remove trailing slashes. case $ac_val in */ ) ac_val=`expr "X$ac_val" : 'X\(.*[^/]\)' \| "X$ac_val" : 'X\(.*\)'` eval $ac_var=\$ac_val;; esac # Be sure to have absolute directory names. case $ac_val in [\\/$]* | ?:[\\/]* ) continue;; NONE | '' ) case $ac_var in *prefix ) continue;; esac;; esac as_fn_error $? "expected an absolute directory name for --$ac_var: $ac_val" done # There might be people who depend on the old broken behavior: `$host' # used to hold the argument of --host etc. # FIXME: To remove some day. build=$build_alias host=$host_alias target=$target_alias # FIXME: To remove some day. if test "x$host_alias" != x; then if test "x$build_alias" = x; then cross_compiling=maybe $as_echo "$as_me: WARNING: if you wanted to set the --build type, don't use --host. If a cross compiler is detected then cross compile mode will be used" >&2 elif test "x$build_alias" != "x$host_alias"; then cross_compiling=yes fi fi ac_tool_prefix= test -n "$host_alias" && ac_tool_prefix=$host_alias- test "$silent" = yes && exec 6>/dev/null ac_pwd=`pwd` && test -n "$ac_pwd" && ac_ls_di=`ls -di .` && ac_pwd_ls_di=`cd "$ac_pwd" && ls -di .` || as_fn_error $? "working directory cannot be determined" test "X$ac_ls_di" = "X$ac_pwd_ls_di" || as_fn_error $? "pwd does not report name of working directory" # Find the source files, if location was not specified. if test -z "$srcdir"; then ac_srcdir_defaulted=yes # Try the directory containing this script, then the parent directory. ac_confdir=`$as_dirname -- "$as_myself" || $as_expr X"$as_myself" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ X"$as_myself" : 'X\(//\)[^/]' \| \ X"$as_myself" : 'X\(//\)$' \| \ X"$as_myself" : 'X\(/\)' \| . 2>/dev/null || $as_echo X"$as_myself" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/ q } /^X\(\/\/\)[^/].*/{ s//\1/ q } /^X\(\/\/\)$/{ s//\1/ q } /^X\(\/\).*/{ s//\1/ q } s/.*/./; q'` srcdir=$ac_confdir if test ! -r "$srcdir/$ac_unique_file"; then srcdir=.. fi else ac_srcdir_defaulted=no fi if test ! -r "$srcdir/$ac_unique_file"; then test "$ac_srcdir_defaulted" = yes && srcdir="$ac_confdir or .." as_fn_error $? "cannot find sources ($ac_unique_file) in $srcdir" fi ac_msg="sources are in $srcdir, but \`cd $srcdir' does not work" ac_abs_confdir=`( cd "$srcdir" && test -r "./$ac_unique_file" || as_fn_error $? "$ac_msg" pwd)` # When building in place, set srcdir=. if test "$ac_abs_confdir" = "$ac_pwd"; then srcdir=. fi # Remove unnecessary trailing slashes from srcdir. # Double slashes in file names in object file debugging info # mess up M-x gdb in Emacs. case $srcdir in */) srcdir=`expr "X$srcdir" : 'X\(.*[^/]\)' \| "X$srcdir" : 'X\(.*\)'`;; esac for ac_var in $ac_precious_vars; do eval ac_env_${ac_var}_set=\${${ac_var}+set} eval ac_env_${ac_var}_value=\$${ac_var} eval ac_cv_env_${ac_var}_set=\${${ac_var}+set} eval ac_cv_env_${ac_var}_value=\$${ac_var} done # # Report the --help message. # if test "$ac_init_help" = "long"; then # Omit some internal or obsolete options to make the list less imposing. # This message is too long to be a string in the A/UX 3.1 sh. cat <<_ACEOF \`configure' configures this package to adapt to many kinds of systems. Usage: $0 [OPTION]... [VAR=VALUE]... To assign environment variables (e.g., CC, CFLAGS...), specify them as VAR=VALUE. See below for descriptions of some of the useful variables. Defaults for the options are specified in brackets. Configuration: -h, --help display this help and exit --help=short display options specific to this package --help=recursive display the short help of all the included packages -V, --version display version information and exit -q, --quiet, --silent do not print \`checking ...' messages --cache-file=FILE cache test results in FILE [disabled] -C, --config-cache alias for \`--cache-file=config.cache' -n, --no-create do not create output files --srcdir=DIR find the sources in DIR [configure dir or \`..'] Installation directories: --prefix=PREFIX install architecture-independent files in PREFIX [$ac_default_prefix] --exec-prefix=EPREFIX install architecture-dependent files in EPREFIX [PREFIX] By default, \`make install' will install all the files in \`$ac_default_prefix/bin', \`$ac_default_prefix/lib' etc. You can specify an installation prefix other than \`$ac_default_prefix' using \`--prefix', for instance \`--prefix=\$HOME'. For better control, use the options below. Fine tuning of the installation directories: --bindir=DIR user executables [EPREFIX/bin] --sbindir=DIR system admin executables [EPREFIX/sbin] --libexecdir=DIR program executables [EPREFIX/libexec] --sysconfdir=DIR read-only single-machine data [PREFIX/etc] --sharedstatedir=DIR modifiable architecture-independent data [PREFIX/com] --localstatedir=DIR modifiable single-machine data [PREFIX/var] --libdir=DIR object code libraries [EPREFIX/lib] --includedir=DIR C header files [PREFIX/include] --oldincludedir=DIR C header files for non-gcc [/usr/include] --datarootdir=DIR read-only arch.-independent data root [PREFIX/share] --datadir=DIR read-only architecture-independent data [DATAROOTDIR] --infodir=DIR info documentation [DATAROOTDIR/info] --localedir=DIR locale-dependent data [DATAROOTDIR/locale] --mandir=DIR man documentation [DATAROOTDIR/man] --docdir=DIR documentation root [DATAROOTDIR/doc/PACKAGE] --htmldir=DIR html documentation [DOCDIR] --dvidir=DIR dvi documentation [DOCDIR] --pdfdir=DIR pdf documentation [DOCDIR] --psdir=DIR ps documentation [DOCDIR] _ACEOF cat <<\_ACEOF _ACEOF fi if test -n "$ac_init_help"; then cat <<\_ACEOF Optional Packages: --with-PACKAGE[=ARG] use PACKAGE [ARG=yes] --without-PACKAGE do not use PACKAGE (same as --with-PACKAGE=no) --with-kernel-path Specify kernel path Report bugs to the package provider. _ACEOF ac_status=$? fi if test "$ac_init_help" = "recursive"; then # If there are subdirs, report their specific --help. for ac_dir in : $ac_subdirs_all; do test "x$ac_dir" = x: && continue test -d "$ac_dir" || { cd "$srcdir" && ac_pwd=`pwd` && srcdir=. && test -d "$ac_dir"; } || continue ac_builddir=. case "$ac_dir" in .) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;; *) ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'` # A ".." for each directory in $ac_dir_suffix. ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'` case $ac_top_builddir_sub in "") ac_top_builddir_sub=. ac_top_build_prefix= ;; *) ac_top_build_prefix=$ac_top_builddir_sub/ ;; esac ;; esac ac_abs_top_builddir=$ac_pwd ac_abs_builddir=$ac_pwd$ac_dir_suffix # for backward compatibility: ac_top_builddir=$ac_top_build_prefix case $srcdir in .) # We are building in place. ac_srcdir=. ac_top_srcdir=$ac_top_builddir_sub ac_abs_top_srcdir=$ac_pwd ;; [\\/]* | ?:[\\/]* ) # Absolute name. ac_srcdir=$srcdir$ac_dir_suffix; ac_top_srcdir=$srcdir ac_abs_top_srcdir=$srcdir ;; *) # Relative name. ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix ac_top_srcdir=$ac_top_build_prefix$srcdir ac_abs_top_srcdir=$ac_pwd/$srcdir ;; esac ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix cd "$ac_dir" || { ac_status=$?; continue; } # Check for guested configure. if test -f "$ac_srcdir/configure.gnu"; then echo && $SHELL "$ac_srcdir/configure.gnu" --help=recursive elif test -f "$ac_srcdir/configure"; then echo && $SHELL "$ac_srcdir/configure" --help=recursive else $as_echo "$as_me: WARNING: no configuration information is in $ac_dir" >&2 fi || ac_status=$? cd "$ac_pwd" || { ac_status=$?; break; } done fi test -n "$ac_init_help" && exit $ac_status if $ac_init_version; then cat <<\_ACEOF configure generated by GNU Autoconf 2.68 Copyright (C) 2010 Free Software Foundation, Inc. This configure script is free software; the Free Software Foundation gives unlimited permission to copy, distribute and modify it. _ACEOF exit fi ## ------------------------ ## ## Autoconf initialization. ## ## ------------------------ ## cat >config.log <<_ACEOF This file contains any messages produced by compilers while running configure, to aid debugging if configure makes a mistake. It was created by $as_me, which was generated by GNU Autoconf 2.68. Invocation command line was $ $0 $@ _ACEOF exec 5>>config.log { cat <<_ASUNAME ## --------- ## ## Platform. ## ## --------- ## hostname = `(hostname || uname -n) 2>/dev/null | sed 1q` uname -m = `(uname -m) 2>/dev/null || echo unknown` uname -r = `(uname -r) 2>/dev/null || echo unknown` uname -s = `(uname -s) 2>/dev/null || echo unknown` uname -v = `(uname -v) 2>/dev/null || echo unknown` /usr/bin/uname -p = `(/usr/bin/uname -p) 2>/dev/null || echo unknown` /bin/uname -X = `(/bin/uname -X) 2>/dev/null || echo unknown` /bin/arch = `(/bin/arch) 2>/dev/null || echo unknown` /usr/bin/arch -k = `(/usr/bin/arch -k) 2>/dev/null || echo unknown` /usr/convex/getsysinfo = `(/usr/convex/getsysinfo) 2>/dev/null || echo unknown` /usr/bin/hostinfo = `(/usr/bin/hostinfo) 2>/dev/null || echo unknown` /bin/machine = `(/bin/machine) 2>/dev/null || echo unknown` /usr/bin/oslevel = `(/usr/bin/oslevel) 2>/dev/null || echo unknown` /bin/universe = `(/bin/universe) 2>/dev/null || echo unknown` _ASUNAME as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. $as_echo "PATH: $as_dir" done IFS=$as_save_IFS } >&5 cat >&5 <<_ACEOF ## ----------- ## ## Core tests. ## ## ----------- ## _ACEOF # Keep a trace of the command line. # Strip out --no-create and --no-recursion so they do not pile up. # Strip out --silent because we don't want to record it for future runs. # Also quote any args containing shell meta-characters. # Make two passes to allow for proper duplicate-argument suppression. ac_configure_args= ac_configure_args0= ac_configure_args1= ac_must_keep_next=false for ac_pass in 1 2 do for ac_arg do case $ac_arg in -no-create | --no-c* | -n | -no-recursion | --no-r*) continue ;; -q | -quiet | --quiet | --quie | --qui | --qu | --q \ | -silent | --silent | --silen | --sile | --sil) continue ;; *\'*) ac_arg=`$as_echo "$ac_arg" | sed "s/'/'\\\\\\\\''/g"` ;; esac case $ac_pass in 1) as_fn_append ac_configure_args0 " '$ac_arg'" ;; 2) as_fn_append ac_configure_args1 " '$ac_arg'" if test $ac_must_keep_next = true; then ac_must_keep_next=false # Got value, back to normal. else case $ac_arg in *=* | --config-cache | -C | -disable-* | --disable-* \ | -enable-* | --enable-* | -gas | --g* | -nfp | --nf* \ | -q | -quiet | --q* | -silent | --sil* | -v | -verb* \ | -with-* | --with-* | -without-* | --without-* | --x) case "$ac_configure_args0 " in "$ac_configure_args1"*" '$ac_arg' "* ) continue ;; esac ;; -* ) ac_must_keep_next=true ;; esac fi as_fn_append ac_configure_args " '$ac_arg'" ;; esac done done { ac_configure_args0=; unset ac_configure_args0;} { ac_configure_args1=; unset ac_configure_args1;} # When interrupted or exit'd, cleanup temporary files, and complete # config.log. We remove comments because anyway the quotes in there # would cause problems or look ugly. # WARNING: Use '\'' to represent an apostrophe within the trap. # WARNING: Do not start the trap code with a newline, due to a FreeBSD 4.0 bug. trap 'exit_status=$? # Save into config.log some information that might help in debugging. { echo $as_echo "## ---------------- ## ## Cache variables. ## ## ---------------- ##" echo # The following way of writing the cache mishandles newlines in values, ( for ac_var in `(set) 2>&1 | sed -n '\''s/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'\''`; do eval ac_val=\$$ac_var case $ac_val in #( *${as_nl}*) case $ac_var in #( *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 $as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; esac case $ac_var in #( _ | IFS | as_nl) ;; #( BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( *) { eval $ac_var=; unset $ac_var;} ;; esac ;; esac done (set) 2>&1 | case $as_nl`(ac_space='\'' '\''; set) 2>&1` in #( *${as_nl}ac_space=\ *) sed -n \ "s/'\''/'\''\\\\'\'''\''/g; s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\''\\2'\''/p" ;; #( *) sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" ;; esac | sort ) echo $as_echo "## ----------------- ## ## Output variables. ## ## ----------------- ##" echo for ac_var in $ac_subst_vars do eval ac_val=\$$ac_var case $ac_val in *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;; esac $as_echo "$ac_var='\''$ac_val'\''" done | sort echo if test -n "$ac_subst_files"; then $as_echo "## ------------------- ## ## File substitutions. ## ## ------------------- ##" echo for ac_var in $ac_subst_files do eval ac_val=\$$ac_var case $ac_val in *\'\''*) ac_val=`$as_echo "$ac_val" | sed "s/'\''/'\''\\\\\\\\'\'''\''/g"`;; esac $as_echo "$ac_var='\''$ac_val'\''" done | sort echo fi if test -s confdefs.h; then $as_echo "## ----------- ## ## confdefs.h. ## ## ----------- ##" echo cat confdefs.h echo fi test "$ac_signal" != 0 && $as_echo "$as_me: caught signal $ac_signal" $as_echo "$as_me: exit $exit_status" } >&5 rm -f core *.core core.conftest.* && rm -f -r conftest* confdefs* conf$$* $ac_clean_files && exit $exit_status ' 0 for ac_signal in 1 2 13 15; do trap 'ac_signal='$ac_signal'; as_fn_exit 1' $ac_signal done ac_signal=0 # confdefs.h avoids OS command line length limits that DEFS can exceed. rm -f -r conftest* confdefs.h $as_echo "/* confdefs.h */" > confdefs.h # Predefined preprocessor variables. cat >>confdefs.h <<_ACEOF #define PACKAGE_NAME "$PACKAGE_NAME" _ACEOF cat >>confdefs.h <<_ACEOF #define PACKAGE_TARNAME "$PACKAGE_TARNAME" _ACEOF cat >>confdefs.h <<_ACEOF #define PACKAGE_VERSION "$PACKAGE_VERSION" _ACEOF cat >>confdefs.h <<_ACEOF #define PACKAGE_STRING "$PACKAGE_STRING" _ACEOF cat >>confdefs.h <<_ACEOF #define PACKAGE_BUGREPORT "$PACKAGE_BUGREPORT" _ACEOF cat >>confdefs.h <<_ACEOF #define PACKAGE_URL "$PACKAGE_URL" _ACEOF # Let the site file select an alternate cache file if it wants to. # Prefer an explicitly selected file to automatically selected ones. ac_site_file1=NONE ac_site_file2=NONE if test -n "$CONFIG_SITE"; then # We do not want a PATH search for config.site. case $CONFIG_SITE in #(( -*) ac_site_file1=./$CONFIG_SITE;; */*) ac_site_file1=$CONFIG_SITE;; *) ac_site_file1=./$CONFIG_SITE;; esac elif test "x$prefix" != xNONE; then ac_site_file1=$prefix/share/config.site ac_site_file2=$prefix/etc/config.site else ac_site_file1=$ac_default_prefix/share/config.site ac_site_file2=$ac_default_prefix/etc/config.site fi for ac_site_file in "$ac_site_file1" "$ac_site_file2" do test "x$ac_site_file" = xNONE && continue if test /dev/null != "$ac_site_file" && test -r "$ac_site_file"; then { $as_echo "$as_me:${as_lineno-$LINENO}: loading site script $ac_site_file" >&5 $as_echo "$as_me: loading site script $ac_site_file" >&6;} sed 's/^/| /' "$ac_site_file" >&5 . "$ac_site_file" \ || { { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} as_fn_error $? "failed to load site script $ac_site_file See \`config.log' for more details" "$LINENO" 5; } fi done if test -r "$cache_file"; then # Some versions of bash will fail to source /dev/null (special files # actually), so we avoid doing that. DJGPP emulates it as a regular file. if test /dev/null != "$cache_file" && test -f "$cache_file"; then { $as_echo "$as_me:${as_lineno-$LINENO}: loading cache $cache_file" >&5 $as_echo "$as_me: loading cache $cache_file" >&6;} case $cache_file in [\\/]* | ?:[\\/]* ) . "$cache_file";; *) . "./$cache_file";; esac fi else { $as_echo "$as_me:${as_lineno-$LINENO}: creating cache $cache_file" >&5 $as_echo "$as_me: creating cache $cache_file" >&6;} >$cache_file fi # Check that the precious variables saved in the cache have kept the same # value. ac_cache_corrupted=false for ac_var in $ac_precious_vars; do eval ac_old_set=\$ac_cv_env_${ac_var}_set eval ac_new_set=\$ac_env_${ac_var}_set eval ac_old_val=\$ac_cv_env_${ac_var}_value eval ac_new_val=\$ac_env_${ac_var}_value case $ac_old_set,$ac_new_set in set,) { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&5 $as_echo "$as_me: error: \`$ac_var' was set to \`$ac_old_val' in the previous run" >&2;} ac_cache_corrupted=: ;; ,set) { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' was not set in the previous run" >&5 $as_echo "$as_me: error: \`$ac_var' was not set in the previous run" >&2;} ac_cache_corrupted=: ;; ,);; *) if test "x$ac_old_val" != "x$ac_new_val"; then # differences in whitespace do not lead to failure. ac_old_val_w=`echo x $ac_old_val` ac_new_val_w=`echo x $ac_new_val` if test "$ac_old_val_w" != "$ac_new_val_w"; then { $as_echo "$as_me:${as_lineno-$LINENO}: error: \`$ac_var' has changed since the previous run:" >&5 $as_echo "$as_me: error: \`$ac_var' has changed since the previous run:" >&2;} ac_cache_corrupted=: else { $as_echo "$as_me:${as_lineno-$LINENO}: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&5 $as_echo "$as_me: warning: ignoring whitespace changes in \`$ac_var' since the previous run:" >&2;} eval $ac_var=\$ac_old_val fi { $as_echo "$as_me:${as_lineno-$LINENO}: former value: \`$ac_old_val'" >&5 $as_echo "$as_me: former value: \`$ac_old_val'" >&2;} { $as_echo "$as_me:${as_lineno-$LINENO}: current value: \`$ac_new_val'" >&5 $as_echo "$as_me: current value: \`$ac_new_val'" >&2;} fi;; esac # Pass precious variables to config.status. if test "$ac_new_set" = set; then case $ac_new_val in *\'*) ac_arg=$ac_var=`$as_echo "$ac_new_val" | sed "s/'/'\\\\\\\\''/g"` ;; *) ac_arg=$ac_var=$ac_new_val ;; esac case " $ac_configure_args " in *" '$ac_arg' "*) ;; # Avoid dups. Use of quotes ensures accuracy. *) as_fn_append ac_configure_args " '$ac_arg'" ;; esac fi done if $ac_cache_corrupted; then { $as_echo "$as_me:${as_lineno-$LINENO}: error: in \`$ac_pwd':" >&5 $as_echo "$as_me: error: in \`$ac_pwd':" >&2;} { $as_echo "$as_me:${as_lineno-$LINENO}: error: changes in the environment can compromise the build" >&5 $as_echo "$as_me: error: changes in the environment can compromise the build" >&2;} as_fn_error $? "run \`make distclean' and/or \`rm $cache_file' and start over" "$LINENO" 5 fi ## -------------------- ## ## Main body of script. ## ## -------------------- ## ac_ext=c ac_cpp='$CPP $CPPFLAGS' ac_compile='$CC -c $CFLAGS $CPPFLAGS conftest.$ac_ext >&5' ac_link='$CC -o conftest$ac_exeext $CFLAGS $CPPFLAGS $LDFLAGS conftest.$ac_ext $LIBS >&5' ac_compiler_gnu=$ac_cv_c_compiler_gnu if test -n "$ac_tool_prefix"; then # Extract the first word of "${ac_tool_prefix}ld", so it can be a program name with args. set dummy ${ac_tool_prefix}ld; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_LD+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$LD"; then ac_cv_prog_LD="$LD" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_LD="${ac_tool_prefix}ld" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi LD=$ac_cv_prog_LD if test -n "$LD"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $LD" >&5 $as_echo "$LD" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi fi if test -z "$ac_cv_prog_LD"; then ac_ct_LD=$LD # Extract the first word of "ld", so it can be a program name with args. set dummy ld; ac_word=$2 { $as_echo "$as_me:${as_lineno-$LINENO}: checking for $ac_word" >&5 $as_echo_n "checking for $ac_word... " >&6; } if ${ac_cv_prog_ac_ct_LD+:} false; then : $as_echo_n "(cached) " >&6 else if test -n "$ac_ct_LD"; then ac_cv_prog_ac_ct_LD="$ac_ct_LD" # Let the user override the test. else as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. for ac_exec_ext in '' $ac_executable_extensions; do if { test -f "$as_dir/$ac_word$ac_exec_ext" && $as_test_x "$as_dir/$ac_word$ac_exec_ext"; }; then ac_cv_prog_ac_ct_LD="ld" $as_echo "$as_me:${as_lineno-$LINENO}: found $as_dir/$ac_word$ac_exec_ext" >&5 break 2 fi done done IFS=$as_save_IFS fi fi ac_ct_LD=$ac_cv_prog_ac_ct_LD if test -n "$ac_ct_LD"; then { $as_echo "$as_me:${as_lineno-$LINENO}: result: $ac_ct_LD" >&5 $as_echo "$ac_ct_LD" >&6; } else { $as_echo "$as_me:${as_lineno-$LINENO}: result: no" >&5 $as_echo "no" >&6; } fi if test "x$ac_ct_LD" = x; then LD=":" else case $cross_compiling:$ac_tool_warned in yes:) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: using cross tools not prefixed with host triplet" >&5 $as_echo "$as_me: WARNING: using cross tools not prefixed with host triplet" >&2;} ac_tool_warned=yes ;; esac LD=$ac_ct_LD fi else LD="$ac_cv_prog_LD" fi # Check whether --with-kernel-path was given. if test "${with_kernel_path+set}" = set; then : withval=$with_kernel_path; KERN_DIR=$withval else KERN_DIR="/lib/modules/"$(uname -r)"/build" fi ac_config_files="$ac_config_files ./Makefile" cat >confcache <<\_ACEOF # This file is a shell script that caches the results of configure # tests run on this system so they can be shared between configure # scripts and configure runs, see configure's option --config-cache. # It is not useful on other systems. If it contains results you don't # want to keep, you may remove or edit it. # # config.status only pays attention to the cache file if you give it # the --recheck option to rerun configure. # # `ac_cv_env_foo' variables (set or unset) will be overridden when # loading this file, other *unset* `ac_cv_foo' will be assigned the # following values. _ACEOF # The following way of writing the cache mishandles newlines in values, # but we know of no workaround that is simple, portable, and efficient. # So, we kill variables containing newlines. # Ultrix sh set writes to stderr and can't be redirected directly, # and sets the high bit in the cache file unless we assign to the vars. ( for ac_var in `(set) 2>&1 | sed -n 's/^\([a-zA-Z_][a-zA-Z0-9_]*\)=.*/\1/p'`; do eval ac_val=\$$ac_var case $ac_val in #( *${as_nl}*) case $ac_var in #( *_cv_*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: cache variable $ac_var contains a newline" >&5 $as_echo "$as_me: WARNING: cache variable $ac_var contains a newline" >&2;} ;; esac case $ac_var in #( _ | IFS | as_nl) ;; #( BASH_ARGV | BASH_SOURCE) eval $ac_var= ;; #( *) { eval $ac_var=; unset $ac_var;} ;; esac ;; esac done (set) 2>&1 | case $as_nl`(ac_space=' '; set) 2>&1` in #( *${as_nl}ac_space=\ *) # `set' does not quote correctly, so add quotes: double-quote # substitution turns \\\\ into \\, and sed turns \\ into \. sed -n \ "s/'/'\\\\''/g; s/^\\([_$as_cr_alnum]*_cv_[_$as_cr_alnum]*\\)=\\(.*\\)/\\1='\\2'/p" ;; #( *) # `set' quotes correctly as required by POSIX, so do not add quotes. sed -n "/^[_$as_cr_alnum]*_cv_[_$as_cr_alnum]*=/p" ;; esac | sort ) | sed ' /^ac_cv_env_/b end t clear :clear s/^\([^=]*\)=\(.*[{}].*\)$/test "${\1+set}" = set || &/ t end s/^\([^=]*\)=\(.*\)$/\1=${\1=\2}/ :end' >>confcache if diff "$cache_file" confcache >/dev/null 2>&1; then :; else if test -w "$cache_file"; then if test "x$cache_file" != "x/dev/null"; then { $as_echo "$as_me:${as_lineno-$LINENO}: updating cache $cache_file" >&5 $as_echo "$as_me: updating cache $cache_file" >&6;} if test ! -f "$cache_file" || test -h "$cache_file"; then cat confcache >"$cache_file" else case $cache_file in #( */* | ?:*) mv -f confcache "$cache_file"$$ && mv -f "$cache_file"$$ "$cache_file" ;; #( *) mv -f confcache "$cache_file" ;; esac fi fi else { $as_echo "$as_me:${as_lineno-$LINENO}: not updating unwritable cache $cache_file" >&5 $as_echo "$as_me: not updating unwritable cache $cache_file" >&6;} fi fi rm -f confcache test "x$prefix" = xNONE && prefix=$ac_default_prefix # Let make expand exec_prefix. test "x$exec_prefix" = xNONE && exec_prefix='${prefix}' # Transform confdefs.h into DEFS. # Protect against shell expansion while executing Makefile rules. # Protect against Makefile macro expansion. # # If the first sed substitution is executed (which looks for macros that # take arguments), then branch to the quote section. Otherwise, # look for a macro that doesn't take arguments. ac_script=' :mline /\\$/{ N s,\\\n,, b mline } t clear :clear s/^[ ]*#[ ]*define[ ][ ]*\([^ (][^ (]*([^)]*)\)[ ]*\(.*\)/-D\1=\2/g t quote s/^[ ]*#[ ]*define[ ][ ]*\([^ ][^ ]*\)[ ]*\(.*\)/-D\1=\2/g t quote b any :quote s/[ `~#$^&*(){}\\|;'\''"<>?]/\\&/g s/\[/\\&/g s/\]/\\&/g s/\$/$$/g H :any ${ g s/^\n// s/\n/ /g p } ' DEFS=`sed -n "$ac_script" confdefs.h` ac_libobjs= ac_ltlibobjs= U= for ac_i in : $LIBOBJS; do test "x$ac_i" = x: && continue # 1. Remove the extension, and $U if already installed. ac_script='s/\$U\././;s/\.o$//;s/\.obj$//' ac_i=`$as_echo "$ac_i" | sed "$ac_script"` # 2. Prepend LIBOBJDIR. When used with automake>=1.10 LIBOBJDIR # will be set to the directory where LIBOBJS objects are built. as_fn_append ac_libobjs " \${LIBOBJDIR}$ac_i\$U.$ac_objext" as_fn_append ac_ltlibobjs " \${LIBOBJDIR}$ac_i"'$U.lo' done LIBOBJS=$ac_libobjs LTLIBOBJS=$ac_ltlibobjs : "${CONFIG_STATUS=./config.status}" ac_write_fail=0 ac_clean_files_save=$ac_clean_files ac_clean_files="$ac_clean_files $CONFIG_STATUS" { $as_echo "$as_me:${as_lineno-$LINENO}: creating $CONFIG_STATUS" >&5 $as_echo "$as_me: creating $CONFIG_STATUS" >&6;} as_write_fail=0 cat >$CONFIG_STATUS <<_ASEOF || as_write_fail=1 #! $SHELL # Generated by $as_me. # Run this file to recreate the current configuration. # Compiler output produced by configure, useful for debugging # configure, is in config.log if it exists. debug=false ac_cs_recheck=false ac_cs_silent=false SHELL=\${CONFIG_SHELL-$SHELL} export SHELL _ASEOF cat >>$CONFIG_STATUS <<\_ASEOF || as_write_fail=1 ## -------------------- ## ## M4sh Initialization. ## ## -------------------- ## # Be more Bourne compatible DUALCASE=1; export DUALCASE # for MKS sh if test -n "${ZSH_VERSION+set}" && (emulate sh) >/dev/null 2>&1; then : emulate sh NULLCMD=: # Pre-4.2 versions of Zsh do word splitting on ${1+"$@"}, which # is contrary to our usage. Disable this feature. alias -g '${1+"$@"}'='"$@"' setopt NO_GLOB_SUBST else case `(set -o) 2>/dev/null` in #( *posix*) : set -o posix ;; #( *) : ;; esac fi as_nl=' ' export as_nl # Printing a long string crashes Solaris 7 /usr/bin/printf. as_echo='\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\\' as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo as_echo=$as_echo$as_echo$as_echo$as_echo$as_echo$as_echo # Prefer a ksh shell builtin over an external printf program on Solaris, # but without wasting forks for bash or zsh. if test -z "$BASH_VERSION$ZSH_VERSION" \ && (test "X`print -r -- $as_echo`" = "X$as_echo") 2>/dev/null; then as_echo='print -r --' as_echo_n='print -rn --' elif (test "X`printf %s $as_echo`" = "X$as_echo") 2>/dev/null; then as_echo='printf %s\n' as_echo_n='printf %s' else if test "X`(/usr/ucb/echo -n -n $as_echo) 2>/dev/null`" = "X-n $as_echo"; then as_echo_body='eval /usr/ucb/echo -n "$1$as_nl"' as_echo_n='/usr/ucb/echo -n' else as_echo_body='eval expr "X$1" : "X\\(.*\\)"' as_echo_n_body='eval arg=$1; case $arg in #( *"$as_nl"*) expr "X$arg" : "X\\(.*\\)$as_nl"; arg=`expr "X$arg" : ".*$as_nl\\(.*\\)"`;; esac; expr "X$arg" : "X\\(.*\\)" | tr -d "$as_nl" ' export as_echo_n_body as_echo_n='sh -c $as_echo_n_body as_echo' fi export as_echo_body as_echo='sh -c $as_echo_body as_echo' fi # The user is always right. if test "${PATH_SEPARATOR+set}" != set; then PATH_SEPARATOR=: (PATH='/bin;/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 && { (PATH='/bin:/bin'; FPATH=$PATH; sh -c :) >/dev/null 2>&1 || PATH_SEPARATOR=';' } fi # IFS # We need space, tab and new line, in precisely that order. Quoting is # there to prevent editors from complaining about space-tab. # (If _AS_PATH_WALK were called with IFS unset, it would disable word # splitting by setting IFS to empty value.) IFS=" "" $as_nl" # Find who we are. Look in the path if we contain no directory separator. as_myself= case $0 in #(( *[\\/]* ) as_myself=$0 ;; *) as_save_IFS=$IFS; IFS=$PATH_SEPARATOR for as_dir in $PATH do IFS=$as_save_IFS test -z "$as_dir" && as_dir=. test -r "$as_dir/$0" && as_myself=$as_dir/$0 && break done IFS=$as_save_IFS ;; esac # We did not find ourselves, most probably we were run as `sh COMMAND' # in which case we are not to be found in the path. if test "x$as_myself" = x; then as_myself=$0 fi if test ! -f "$as_myself"; then $as_echo "$as_myself: error: cannot find myself; rerun with an absolute file name" >&2 exit 1 fi # Unset variables that we do not need and which cause bugs (e.g. in # pre-3.0 UWIN ksh). But do not cause bugs in bash 2.01; the "|| exit 1" # suppresses any "Segmentation fault" message there. '((' could # trigger a bug in pdksh 5.2.14. for as_var in BASH_ENV ENV MAIL MAILPATH do eval test x\${$as_var+set} = xset \ && ( (unset $as_var) || exit 1) >/dev/null 2>&1 && unset $as_var || : done PS1='$ ' PS2='> ' PS4='+ ' # NLS nuisances. LC_ALL=C export LC_ALL LANGUAGE=C export LANGUAGE # CDPATH. (unset CDPATH) >/dev/null 2>&1 && unset CDPATH # as_fn_error STATUS ERROR [LINENO LOG_FD] # ---------------------------------------- # Output "`basename $0`: error: ERROR" to stderr. If LINENO and LOG_FD are # provided, also output the error to LOG_FD, referencing LINENO. Then exit the # script with STATUS, using 1 if that was 0. as_fn_error () { as_status=$1; test $as_status -eq 0 && as_status=1 if test "$4"; then as_lineno=${as_lineno-"$3"} as_lineno_stack=as_lineno_stack=$as_lineno_stack $as_echo "$as_me:${as_lineno-$LINENO}: error: $2" >&$4 fi $as_echo "$as_me: error: $2" >&2 as_fn_exit $as_status } # as_fn_error # as_fn_set_status STATUS # ----------------------- # Set $? to STATUS, without forking. as_fn_set_status () { return $1 } # as_fn_set_status # as_fn_exit STATUS # ----------------- # Exit the shell with STATUS, even in a "trap 0" or "set -e" context. as_fn_exit () { set +e as_fn_set_status $1 exit $1 } # as_fn_exit # as_fn_unset VAR # --------------- # Portably unset VAR. as_fn_unset () { { eval $1=; unset $1;} } as_unset=as_fn_unset # as_fn_append VAR VALUE # ---------------------- # Append the text in VALUE to the end of the definition contained in VAR. Take # advantage of any shell optimizations that allow amortized linear growth over # repeated appends, instead of the typical quadratic growth present in naive # implementations. if (eval "as_var=1; as_var+=2; test x\$as_var = x12") 2>/dev/null; then : eval 'as_fn_append () { eval $1+=\$2 }' else as_fn_append () { eval $1=\$$1\$2 } fi # as_fn_append # as_fn_arith ARG... # ------------------ # Perform arithmetic evaluation on the ARGs, and store the result in the # global $as_val. Take advantage of shells that can avoid forks. The arguments # must be portable across $(()) and expr. if (eval "test \$(( 1 + 1 )) = 2") 2>/dev/null; then : eval 'as_fn_arith () { as_val=$(( $* )) }' else as_fn_arith () { as_val=`expr "$@" || test $? -eq 1` } fi # as_fn_arith if expr a : '\(a\)' >/dev/null 2>&1 && test "X`expr 00001 : '.*\(...\)'`" = X001; then as_expr=expr else as_expr=false fi if (basename -- /) >/dev/null 2>&1 && test "X`basename -- / 2>&1`" = "X/"; then as_basename=basename else as_basename=false fi if (as_dir=`dirname -- /` && test "X$as_dir" = X/) >/dev/null 2>&1; then as_dirname=dirname else as_dirname=false fi as_me=`$as_basename -- "$0" || $as_expr X/"$0" : '.*/\([^/][^/]*\)/*$' \| \ X"$0" : 'X\(//\)$' \| \ X"$0" : 'X\(/\)' \| . 2>/dev/null || $as_echo X/"$0" | sed '/^.*\/\([^/][^/]*\)\/*$/{ s//\1/ q } /^X\/\(\/\/\)$/{ s//\1/ q } /^X\/\(\/\).*/{ s//\1/ q } s/.*/./; q'` # Avoid depending upon Character Ranges. as_cr_letters='abcdefghijklmnopqrstuvwxyz' as_cr_LETTERS='ABCDEFGHIJKLMNOPQRSTUVWXYZ' as_cr_Letters=$as_cr_letters$as_cr_LETTERS as_cr_digits='0123456789' as_cr_alnum=$as_cr_Letters$as_cr_digits ECHO_C= ECHO_N= ECHO_T= case `echo -n x` in #((((( -n*) case `echo 'xy\c'` in *c*) ECHO_T=' ';; # ECHO_T is single tab character. xy) ECHO_C='\c';; *) echo `echo ksh88 bug on AIX 6.1` > /dev/null ECHO_T=' ';; esac;; *) ECHO_N='-n';; esac rm -f conf$$ conf$$.exe conf$$.file if test -d conf$$.dir; then rm -f conf$$.dir/conf$$.file else rm -f conf$$.dir mkdir conf$$.dir 2>/dev/null fi if (echo >conf$$.file) 2>/dev/null; then if ln -s conf$$.file conf$$ 2>/dev/null; then as_ln_s='ln -s' # ... but there are two gotchas: # 1) On MSYS, both `ln -s file dir' and `ln file dir' fail. # 2) DJGPP < 2.04 has no symlinks; `ln -s' creates a wrapper executable. # In both cases, we have to default to `cp -p'. ln -s conf$$.file conf$$.dir 2>/dev/null && test ! -f conf$$.exe || as_ln_s='cp -p' elif ln conf$$.file conf$$ 2>/dev/null; then as_ln_s=ln else as_ln_s='cp -p' fi else as_ln_s='cp -p' fi rm -f conf$$ conf$$.exe conf$$.dir/conf$$.file conf$$.file rmdir conf$$.dir 2>/dev/null # as_fn_mkdir_p # ------------- # Create "$as_dir" as a directory, including parents if necessary. as_fn_mkdir_p () { case $as_dir in #( -*) as_dir=./$as_dir;; esac test -d "$as_dir" || eval $as_mkdir_p || { as_dirs= while :; do case $as_dir in #( *\'*) as_qdir=`$as_echo "$as_dir" | sed "s/'/'\\\\\\\\''/g"`;; #'( *) as_qdir=$as_dir;; esac as_dirs="'$as_qdir' $as_dirs" as_dir=`$as_dirname -- "$as_dir" || $as_expr X"$as_dir" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ X"$as_dir" : 'X\(//\)[^/]' \| \ X"$as_dir" : 'X\(//\)$' \| \ X"$as_dir" : 'X\(/\)' \| . 2>/dev/null || $as_echo X"$as_dir" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/ q } /^X\(\/\/\)[^/].*/{ s//\1/ q } /^X\(\/\/\)$/{ s//\1/ q } /^X\(\/\).*/{ s//\1/ q } s/.*/./; q'` test -d "$as_dir" && break done test -z "$as_dirs" || eval "mkdir $as_dirs" } || test -d "$as_dir" || as_fn_error $? "cannot create directory $as_dir" } # as_fn_mkdir_p if mkdir -p . 2>/dev/null; then as_mkdir_p='mkdir -p "$as_dir"' else test -d ./-p && rmdir ./-p as_mkdir_p=false fi if test -x / >/dev/null 2>&1; then as_test_x='test -x' else if ls -dL / >/dev/null 2>&1; then as_ls_L_option=L else as_ls_L_option= fi as_test_x=' eval sh -c '\'' if test -d "$1"; then test -d "$1/."; else case $1 in #( -*)set "./$1";; esac; case `ls -ld'$as_ls_L_option' "$1" 2>/dev/null` in #(( ???[sx]*):;;*)false;;esac;fi '\'' sh ' fi as_executable_p=$as_test_x # Sed expression to map a string onto a valid CPP name. as_tr_cpp="eval sed 'y%*$as_cr_letters%P$as_cr_LETTERS%;s%[^_$as_cr_alnum]%_%g'" # Sed expression to map a string onto a valid variable name. as_tr_sh="eval sed 'y%*+%pp%;s%[^_$as_cr_alnum]%_%g'" exec 6>&1 ## ----------------------------------- ## ## Main body of $CONFIG_STATUS script. ## ## ----------------------------------- ## _ASEOF test $as_write_fail = 0 && chmod +x $CONFIG_STATUS || ac_write_fail=1 cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 # Save the log message, to keep $0 and so on meaningful, and to # report actual input values of CONFIG_FILES etc. instead of their # values after options handling. ac_log=" This file was extended by $as_me, which was generated by GNU Autoconf 2.68. Invocation command line was CONFIG_FILES = $CONFIG_FILES CONFIG_HEADERS = $CONFIG_HEADERS CONFIG_LINKS = $CONFIG_LINKS CONFIG_COMMANDS = $CONFIG_COMMANDS $ $0 $@ on `(hostname || uname -n) 2>/dev/null | sed 1q` " _ACEOF case $ac_config_files in *" "*) set x $ac_config_files; shift; ac_config_files=$*;; esac cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 # Files that config.status was made for. config_files="$ac_config_files" _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 ac_cs_usage="\ \`$as_me' instantiates files and other configuration actions from templates according to the current configuration. Unless the files and actions are specified as TAGs, all are instantiated by default. Usage: $0 [OPTION]... [TAG]... -h, --help print this help, then exit -V, --version print version number and configuration settings, then exit --config print configuration, then exit -q, --quiet, --silent do not print progress messages -d, --debug don't remove temporary files --recheck update $as_me by reconfiguring in the same conditions --file=FILE[:TEMPLATE] instantiate the configuration file FILE Configuration files: $config_files Report bugs to the package provider." _ACEOF cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 ac_cs_config="`$as_echo "$ac_configure_args" | sed 's/^ //; s/[\\""\`\$]/\\\\&/g'`" ac_cs_version="\\ config.status configured by $0, generated by GNU Autoconf 2.68, with options \\"\$ac_cs_config\\" Copyright (C) 2010 Free Software Foundation, Inc. This config.status script is free software; the Free Software Foundation gives unlimited permission to copy, distribute and modify it." ac_pwd='$ac_pwd' srcdir='$srcdir' test -n "\$AWK" || AWK=awk _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 # The default lists apply if the user does not specify any file. ac_need_defaults=: while test $# != 0 do case $1 in --*=?*) ac_option=`expr "X$1" : 'X\([^=]*\)='` ac_optarg=`expr "X$1" : 'X[^=]*=\(.*\)'` ac_shift=: ;; --*=) ac_option=`expr "X$1" : 'X\([^=]*\)='` ac_optarg= ac_shift=: ;; *) ac_option=$1 ac_optarg=$2 ac_shift=shift ;; esac case $ac_option in # Handling of the options. -recheck | --recheck | --rechec | --reche | --rech | --rec | --re | --r) ac_cs_recheck=: ;; --version | --versio | --versi | --vers | --ver | --ve | --v | -V ) $as_echo "$ac_cs_version"; exit ;; --config | --confi | --conf | --con | --co | --c ) $as_echo "$ac_cs_config"; exit ;; --debug | --debu | --deb | --de | --d | -d ) debug=: ;; --file | --fil | --fi | --f ) $ac_shift case $ac_optarg in *\'*) ac_optarg=`$as_echo "$ac_optarg" | sed "s/'/'\\\\\\\\''/g"` ;; '') as_fn_error $? "missing file argument" ;; esac as_fn_append CONFIG_FILES " '$ac_optarg'" ac_need_defaults=false;; --he | --h | --help | --hel | -h ) $as_echo "$ac_cs_usage"; exit ;; -q | -quiet | --quiet | --quie | --qui | --qu | --q \ | -silent | --silent | --silen | --sile | --sil | --si | --s) ac_cs_silent=: ;; # This is an error. -*) as_fn_error $? "unrecognized option: \`$1' Try \`$0 --help' for more information." ;; *) as_fn_append ac_config_targets " $1" ac_need_defaults=false ;; esac shift done ac_configure_extra_args= if $ac_cs_silent; then exec 6>/dev/null ac_configure_extra_args="$ac_configure_extra_args --silent" fi _ACEOF cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 if \$ac_cs_recheck; then set X '$SHELL' '$0' $ac_configure_args \$ac_configure_extra_args --no-create --no-recursion shift \$as_echo "running CONFIG_SHELL=$SHELL \$*" >&6 CONFIG_SHELL='$SHELL' export CONFIG_SHELL exec "\$@" fi _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 exec 5>>config.log { echo sed 'h;s/./-/g;s/^.../## /;s/...$/ ##/;p;x;p;x' <<_ASBOX ## Running $as_me. ## _ASBOX $as_echo "$ac_log" } >&5 _ACEOF cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 # Handling of arguments. for ac_config_target in $ac_config_targets do case $ac_config_target in "./Makefile") CONFIG_FILES="$CONFIG_FILES ./Makefile" ;; *) as_fn_error $? "invalid argument: \`$ac_config_target'" "$LINENO" 5;; esac done # If the user did not use the arguments to specify the items to instantiate, # then the envvar interface is used. Set only those that are not. # We use the long form for the default assignment because of an extremely # bizarre bug on SunOS 4.1.3. if $ac_need_defaults; then test "${CONFIG_FILES+set}" = set || CONFIG_FILES=$config_files fi # Have a temporary directory for convenience. Make it in the build tree # simply because there is no reason against having it here, and in addition, # creating and moving files from /tmp can sometimes cause problems. # Hook for its removal unless debugging. # Note that there is a small window in which the directory will not be cleaned: # after its creation but before its name has been assigned to `$tmp'. $debug || { tmp= ac_tmp= trap 'exit_status=$? : "${ac_tmp:=$tmp}" { test ! -d "$ac_tmp" || rm -fr "$ac_tmp"; } && exit $exit_status ' 0 trap 'as_fn_exit 1' 1 2 13 15 } # Create a (secure) tmp directory for tmp files. { tmp=`(umask 077 && mktemp -d "./confXXXXXX") 2>/dev/null` && test -d "$tmp" } || { tmp=./conf$$-$RANDOM (umask 077 && mkdir "$tmp") } || as_fn_error $? "cannot create a temporary directory in ." "$LINENO" 5 ac_tmp=$tmp # Set up the scripts for CONFIG_FILES section. # No need to generate them if there are no CONFIG_FILES. # This happens for instance with `./config.status config.h'. if test -n "$CONFIG_FILES"; then ac_cr=`echo X | tr X '\015'` # On cygwin, bash can eat \r inside `` if the user requested igncr. # But we know of no other shell where ac_cr would be empty at this # point, so we can use a bashism as a fallback. if test "x$ac_cr" = x; then eval ac_cr=\$\'\\r\' fi ac_cs_awk_cr=`$AWK 'BEGIN { print "a\rb" }' /dev/null` if test "$ac_cs_awk_cr" = "a${ac_cr}b"; then ac_cs_awk_cr='\\r' else ac_cs_awk_cr=$ac_cr fi echo 'BEGIN {' >"$ac_tmp/subs1.awk" && _ACEOF { echo "cat >conf$$subs.awk <<_ACEOF" && echo "$ac_subst_vars" | sed 's/.*/&!$&$ac_delim/' && echo "_ACEOF" } >conf$$subs.sh || as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 ac_delim_num=`echo "$ac_subst_vars" | grep -c '^'` ac_delim='%!_!# ' for ac_last_try in false false false false false :; do . ./conf$$subs.sh || as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 ac_delim_n=`sed -n "s/.*$ac_delim\$/X/p" conf$$subs.awk | grep -c X` if test $ac_delim_n = $ac_delim_num; then break elif $ac_last_try; then as_fn_error $? "could not make $CONFIG_STATUS" "$LINENO" 5 else ac_delim="$ac_delim!$ac_delim _$ac_delim!! " fi done rm -f conf$$subs.sh cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 cat >>"\$ac_tmp/subs1.awk" <<\\_ACAWK && _ACEOF sed -n ' h s/^/S["/; s/!.*/"]=/ p g s/^[^!]*!// :repl t repl s/'"$ac_delim"'$// t delim :nl h s/\(.\{148\}\)..*/\1/ t more1 s/["\\]/\\&/g; s/^/"/; s/$/\\n"\\/ p n b repl :more1 s/["\\]/\\&/g; s/^/"/; s/$/"\\/ p g s/.\{148\}// t nl :delim h s/\(.\{148\}\)..*/\1/ t more2 s/["\\]/\\&/g; s/^/"/; s/$/"/ p b :more2 s/["\\]/\\&/g; s/^/"/; s/$/"\\/ p g s/.\{148\}// t delim ' >$CONFIG_STATUS || ac_write_fail=1 rm -f conf$$subs.awk cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 _ACAWK cat >>"\$ac_tmp/subs1.awk" <<_ACAWK && for (key in S) S_is_set[key] = 1 FS = "" } { line = $ 0 nfields = split(line, field, "@") substed = 0 len = length(field[1]) for (i = 2; i < nfields; i++) { key = field[i] keylen = length(key) if (S_is_set[key]) { value = S[key] line = substr(line, 1, len) "" value "" substr(line, len + keylen + 3) len += length(value) + length(field[++i]) substed = 1 } else len += 1 + keylen } print line } _ACAWK _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 if sed "s/$ac_cr//" < /dev/null > /dev/null 2>&1; then sed "s/$ac_cr\$//; s/$ac_cr/$ac_cs_awk_cr/g" else cat fi < "$ac_tmp/subs1.awk" > "$ac_tmp/subs.awk" \ || as_fn_error $? "could not setup config files machinery" "$LINENO" 5 _ACEOF # VPATH may cause trouble with some makes, so we remove sole $(srcdir), # ${srcdir} and @srcdir@ entries from VPATH if srcdir is ".", strip leading and # trailing colons and then remove the whole line if VPATH becomes empty # (actually we leave an empty line to preserve line numbers). if test "x$srcdir" = x.; then ac_vpsub='/^[ ]*VPATH[ ]*=[ ]*/{ h s/// s/^/:/ s/[ ]*$/:/ s/:\$(srcdir):/:/g s/:\${srcdir}:/:/g s/:@srcdir@:/:/g s/^:*// s/:*$// x s/\(=[ ]*\).*/\1/ G s/\n// s/^[^=]*=[ ]*$// }' fi cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 fi # test -n "$CONFIG_FILES" eval set X " :F $CONFIG_FILES " shift for ac_tag do case $ac_tag in :[FHLC]) ac_mode=$ac_tag; continue;; esac case $ac_mode$ac_tag in :[FHL]*:*);; :L* | :C*:*) as_fn_error $? "invalid tag \`$ac_tag'" "$LINENO" 5;; :[FH]-) ac_tag=-:-;; :[FH]*) ac_tag=$ac_tag:$ac_tag.in;; esac ac_save_IFS=$IFS IFS=: set x $ac_tag IFS=$ac_save_IFS shift ac_file=$1 shift case $ac_mode in :L) ac_source=$1;; :[FH]) ac_file_inputs= for ac_f do case $ac_f in -) ac_f="$ac_tmp/stdin";; *) # Look for the file first in the build tree, then in the source tree # (if the path is not absolute). The absolute path cannot be DOS-style, # because $ac_f cannot contain `:'. test -f "$ac_f" || case $ac_f in [\\/$]*) false;; *) test -f "$srcdir/$ac_f" && ac_f="$srcdir/$ac_f";; esac || as_fn_error 1 "cannot find input file: \`$ac_f'" "$LINENO" 5;; esac case $ac_f in *\'*) ac_f=`$as_echo "$ac_f" | sed "s/'/'\\\\\\\\''/g"`;; esac as_fn_append ac_file_inputs " '$ac_f'" done # Let's still pretend it is `configure' which instantiates (i.e., don't # use $as_me), people would be surprised to read: # /* config.h. Generated by config.status. */ configure_input='Generated from '` $as_echo "$*" | sed 's|^[^:]*/||;s|:[^:]*/|, |g' `' by configure.' if test x"$ac_file" != x-; then configure_input="$ac_file. $configure_input" { $as_echo "$as_me:${as_lineno-$LINENO}: creating $ac_file" >&5 $as_echo "$as_me: creating $ac_file" >&6;} fi # Neutralize special characters interpreted by sed in replacement strings. case $configure_input in #( *\&* | *\|* | *\\* ) ac_sed_conf_input=`$as_echo "$configure_input" | sed 's/[\\\\&|]/\\\\&/g'`;; #( *) ac_sed_conf_input=$configure_input;; esac case $ac_tag in *:-:* | *:-) cat >"$ac_tmp/stdin" \ || as_fn_error $? "could not create $ac_file" "$LINENO" 5 ;; esac ;; esac ac_dir=`$as_dirname -- "$ac_file" || $as_expr X"$ac_file" : 'X\(.*[^/]\)//*[^/][^/]*/*$' \| \ X"$ac_file" : 'X\(//\)[^/]' \| \ X"$ac_file" : 'X\(//\)$' \| \ X"$ac_file" : 'X\(/\)' \| . 2>/dev/null || $as_echo X"$ac_file" | sed '/^X\(.*[^/]\)\/\/*[^/][^/]*\/*$/{ s//\1/ q } /^X\(\/\/\)[^/].*/{ s//\1/ q } /^X\(\/\/\)$/{ s//\1/ q } /^X\(\/\).*/{ s//\1/ q } s/.*/./; q'` as_dir="$ac_dir"; as_fn_mkdir_p ac_builddir=. case "$ac_dir" in .) ac_dir_suffix= ac_top_builddir_sub=. ac_top_build_prefix= ;; *) ac_dir_suffix=/`$as_echo "$ac_dir" | sed 's|^\.[\\/]||'` # A ".." for each directory in $ac_dir_suffix. ac_top_builddir_sub=`$as_echo "$ac_dir_suffix" | sed 's|/[^\\/]*|/..|g;s|/||'` case $ac_top_builddir_sub in "") ac_top_builddir_sub=. ac_top_build_prefix= ;; *) ac_top_build_prefix=$ac_top_builddir_sub/ ;; esac ;; esac ac_abs_top_builddir=$ac_pwd ac_abs_builddir=$ac_pwd$ac_dir_suffix # for backward compatibility: ac_top_builddir=$ac_top_build_prefix case $srcdir in .) # We are building in place. ac_srcdir=. ac_top_srcdir=$ac_top_builddir_sub ac_abs_top_srcdir=$ac_pwd ;; [\\/]* | ?:[\\/]* ) # Absolute name. ac_srcdir=$srcdir$ac_dir_suffix; ac_top_srcdir=$srcdir ac_abs_top_srcdir=$srcdir ;; *) # Relative name. ac_srcdir=$ac_top_build_prefix$srcdir$ac_dir_suffix ac_top_srcdir=$ac_top_build_prefix$srcdir ac_abs_top_srcdir=$ac_pwd/$srcdir ;; esac ac_abs_srcdir=$ac_abs_top_srcdir$ac_dir_suffix case $ac_mode in :F) # # CONFIG_FILE # _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 # If the template does not know about datarootdir, expand it. # FIXME: This hack should be removed a few years after 2.60. ac_datarootdir_hack=; ac_datarootdir_seen= ac_sed_dataroot=' /datarootdir/ { p q } /@datadir@/p /@docdir@/p /@infodir@/p /@localedir@/p /@mandir@/p' case `eval "sed -n \"\$ac_sed_dataroot\" $ac_file_inputs"` in *datarootdir*) ac_datarootdir_seen=yes;; *@datadir@*|*@docdir@*|*@infodir@*|*@localedir@*|*@mandir@*) { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&5 $as_echo "$as_me: WARNING: $ac_file_inputs seems to ignore the --datarootdir setting" >&2;} _ACEOF cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 ac_datarootdir_hack=' s&@datadir@&$datadir&g s&@docdir@&$docdir&g s&@infodir@&$infodir&g s&@localedir@&$localedir&g s&@mandir@&$mandir&g s&\\\${datarootdir}&$datarootdir&g' ;; esac _ACEOF # Neutralize VPATH when `$srcdir' = `.'. # Shell code in configure.ac might set extrasub. # FIXME: do we really want to maintain this feature? cat >>$CONFIG_STATUS <<_ACEOF || ac_write_fail=1 ac_sed_extra="$ac_vpsub $extrasub _ACEOF cat >>$CONFIG_STATUS <<\_ACEOF || ac_write_fail=1 :t /@[a-zA-Z_][a-zA-Z_0-9]*@/!b s|@configure_input@|$ac_sed_conf_input|;t t s&@top_builddir@&$ac_top_builddir_sub&;t t s&@top_build_prefix@&$ac_top_build_prefix&;t t s&@srcdir@&$ac_srcdir&;t t s&@abs_srcdir@&$ac_abs_srcdir&;t t s&@top_srcdir@&$ac_top_srcdir&;t t s&@abs_top_srcdir@&$ac_abs_top_srcdir&;t t s&@builddir@&$ac_builddir&;t t s&@abs_builddir@&$ac_abs_builddir&;t t s&@abs_top_builddir@&$ac_abs_top_builddir&;t t $ac_datarootdir_hack " eval sed \"\$ac_sed_extra\" "$ac_file_inputs" | $AWK -f "$ac_tmp/subs.awk" \ >$ac_tmp/out || as_fn_error $? "could not create $ac_file" "$LINENO" 5 test -z "$ac_datarootdir_hack$ac_datarootdir_seen" && { ac_out=`sed -n '/\${datarootdir}/p' "$ac_tmp/out"`; test -n "$ac_out"; } && { ac_out=`sed -n '/^[ ]*datarootdir[ ]*:*=/p' \ "$ac_tmp/out"`; test -z "$ac_out"; } && { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: $ac_file contains a reference to the variable \`datarootdir' which seems to be undefined. Please make sure it is defined" >&5 $as_echo "$as_me: WARNING: $ac_file contains a reference to the variable \`datarootdir' which seems to be undefined. Please make sure it is defined" >&2;} rm -f "$ac_tmp/stdin" case $ac_file in -) cat "$ac_tmp/out" && rm -f "$ac_tmp/out";; *) rm -f "$ac_file" && mv "$ac_tmp/out" "$ac_file";; esac \ || as_fn_error $? "could not create $ac_file" "$LINENO" 5 ;; esac done # for ac_tag as_fn_exit 0 _ACEOF ac_clean_files=$ac_clean_files_save test $ac_write_fail = 0 || as_fn_error $? "write failure creating $CONFIG_STATUS" "$LINENO" 5 # configure is writing to config.log, and then calls config.status. # config.status does its own redirection, appending to config.log. # Unfortunately, on DOS this fails, as config.log is still kept open # by configure, so config.status won't be able to write to it; its # output is simply discarded. So we exec the FD to /dev/null, # effectively closing config.log, so it can be properly (re)opened and # appended to by config.status. When coming back to configure, we # need to make the FD available again. if test "$no_create" != yes; then ac_cs_success=: ac_config_status_args= test "$silent" = yes && ac_config_status_args="$ac_config_status_args --quiet" exec 5>/dev/null $SHELL $CONFIG_STATUS $ac_config_status_args || ac_cs_success=false exec 5>>config.log # Use ||, not &&, to avoid exiting from the if with $? = 1, which # would make configure fail if this is the last instruction. $ac_cs_success || as_fn_exit 1 fi if test -n "$ac_unrecognized_opts" && test "$enable_option_checking" != no; then { $as_echo "$as_me:${as_lineno-$LINENO}: WARNING: unrecognized options: $ac_unrecognized_opts" >&5 $as_echo "$as_me: WARNING: unrecognized options: $ac_unrecognized_opts" >&2;} fi crystalhd-0.0~git20110715.fdd2f19/driver/linux/bcm_70012_run.sh0000644000175000017500000000207411610313111022674 0ustar andresandres#!/bin/bash # # Author: Prasad Bolisetty # # Script to load broadcom 70012 module and create device node. # # bcm_dev_bin="crystalhd" bcm_dev_bin_ko="crystalhd.ko" bcm_dev_name="crystalhd" bcm_node="/dev/crystalhd" if ! whoami | grep root > /dev/null ; then echo " Login as root and try.." exit 1; fi if /sbin/lsmod | grep $bcm_dev_bin > /dev/null ; then echo "Stopping Broadcom Crystal HD (BCM70012) Module" /sbin/rmmod $bcm_dev_bin >& /dev/null if [ $? -ne 0 ]; then echo "Failed to stop: Close applications and try again. " exit 1; fi fi bcm_major=`cat /proc/devices | grep "$bcm_dev_name" | cut -c1-3` if [ -z "$bcm_major" ]; then /sbin/insmod $bcm_dev_bin_ko >& /dev/null bcm_major=`cat /proc/devices | grep "$bcm_dev_name" | cut -c1-3` if [ $? -ne 0 -o -z "$bcm_major" ]; then echo "Error($bcm_major): Loading Broadcom Crystal HD (BCM70012) Module" rmmod $bcm_dev_bin >& /dev/null exit 1; fi fi if [ -c $bcm_node ]; then rm -f $bcm_node >& /dev/null fi mknod -m 666 $bcm_node c $bcm_major 0 echo "Broadcom Crystal HD (BCM70012) Module loaded" crystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_hw.h0000644000175000017500000005323211610313111023030 0ustar andresandres/*************************************************************************** * Copyright (c) 2005-2009, Broadcom Corporation. * * Name: crystalhd_hw . h * * Description: * BCM70012 Linux driver hardware layer. * * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ #ifndef _CRYSTALHD_HW_H_ #define _CRYSTALHD_HW_H_ #define DEBUG 1 #include #include #if LINUX_VERSION_CODE > KERNEL_VERSION(2, 6, 24) #include #else #include #endif #include "crystalhd_fw_if.h" #include "crystalhd_misc.h" #include "DriverFwShare.h" #include "FleaDefs.h" /* HW constants..*/ #define DMA_ENGINE_CNT 2 #define MAX_PIB_Q_DEPTH 64 #define MIN_PIB_Q_DEPTH 2 #define WR_POINTER_OFF 4 #define MAX_VALID_POLL_CNT 1000 #define TX_WRAP_THRESHOLD 128 * 1024 #define NUMBER_OF_TRANSFERS_TX_SIDE 1 #define NUMBER_OF_TRANSFERS_RX_SIDE 2 struct BC_DRV_PIC_INFO { struct C011_PIB DecoPIB; struct BC_DRV_PIC_INFO *Flink; }; union desc_low_addr_reg { struct { #ifdef __LITTLE_ENDIAN_BITFIELD uint32_t list_valid:1; uint32_t reserved:4; uint32_t low_addr:27; #else uint32_t low_addr:27; uint32_t reserved:4; uint32_t list_valid:1; #endif }; uint32_t whole_reg; }; struct dma_descriptor { /* 8 32-bit values */ #ifdef __LITTLE_ENDIAN_BITFIELD /* 0th u32 */ uint32_t sdram_buff_addr:28; /* bits 0-27: SDRAM Address */ uint32_t res0:4; /* bits 28-31: Reserved */ /* 1st u32 */ uint32_t buff_addr_low; /* 1 buffer address low */ uint32_t buff_addr_high; /* 2 buffer address high */ /* 3rd u32 */ uint32_t res2:2; /* 0-1 - Reserved */ uint32_t xfer_size:23; /* 2-24 = Xfer size in words */ uint32_t res3:6; /* 25-30 reserved */ uint32_t intr_enable:1; /* 31 - Interrupt After this desc */ /* 4th u32 */ uint32_t endian_xlat_align:2; /* 0-1 Endian Translation */ uint32_t next_desc_cont:1; /* 2 - Next desc is in contig memory */ uint32_t res4:25; /* 3 - 27 Reserved bits */ uint32_t fill_bytes:2; /* 28-29 Bits Fill Bytes */ uint32_t dma_dir:1; /* 30 bit DMA Direction */ uint32_t last_rec_indicator:1; /* 31 bit Last Record Indicator */ /* 5th u32 */ uint32_t next_desc_addr_low; /* 32-bits Next Desc Addr lower */ /* 6th u32 */ uint32_t next_desc_addr_high; /* 32-bits Next Desc Addr Higher */ /* 7th u32 */ uint32_t res8; /* Last 32bits reserved */ #else /* 0th u32 */ uint32_t res0:4; /* bits 28-31: Reserved */ uint32_t sdram_buff_addr:28; /* bits 0-27: SDRAM Address */ /* 1st u32 */ uint32_t buff_addr_low; /* 1 buffer address low */ uint32_t buff_addr_high; /* 2 buffer address high */ /* 3rd u32 */ uint32_t intr_enable:1; /* 31 - Interrupt After this desc */ uint32_t res3:6; /* 25-30 reserved */ uint32_t xfer_size:23; /* 2-24 = Xfer size in words */ uint32_t res2:2; /* 0-1 - Reserved */ /* 4th u32 */ uint32_t last_rec_indicator:1; /* 31 bit Last Record Indicator */ uint32_t dma_dir:1; /* 30 bit DMA Direction */ uint32_t fill_bytes:2; /* 28-29 Bits Fill Bytes */ uint32_t res4:25; /* 3 - 27 Reserved bits */ uint32_t next_desc_cont:1; /* 2 - Next desc is in contig memory */ uint32_t endian_xlat_align:2; /* 0-1 Endian Translation */ /* 5th u32 */ uint32_t next_desc_addr_low; /* 32-bits Next Desc Addr lower */ /* 6th u32 */ uint32_t next_desc_addr_high; /* 32-bits Next Desc Addr Higher */ /* 7th u32 */ uint32_t res8; /* Last 32bits reserved */ #endif }; /* * We will allocate the memory in 4K pages * the linked list will be a list of 32 byte descriptors. * The virtual address will determine what should be freed. */ struct dma_desc_mem { struct dma_descriptor *pdma_desc_start; /* 32-bytes for dma descriptor. should be first element */ dma_addr_t phy_addr; /* physical address of each DMA desc */ uint32_t sz; struct dma_desc_mem *Next; /* points to Next Descriptor in chain */ }; enum list_sts { sts_free = 0, /* RX-Y Bits 0:7 */ rx_waiting_y_intr = 0x00000001, rx_y_error = 0x00000004, /* RX-UV Bits 8:16 */ rx_waiting_uv_intr = 0x0000100, rx_uv_error = 0x0000400, rx_sts_waiting = (rx_waiting_y_intr|rx_waiting_uv_intr), rx_sts_error = (rx_y_error|rx_uv_error), rx_y_mask = 0x000000FF, rx_uv_mask = 0x0000FF00, }; enum INTERRUPT_STATUS { NO_INTERRUPT = 0x0000, FPGA_RX_L0_DMA_DONE = 0x0001, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ FPGA_RX_L1_DMA_DONE = 0x0002, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ FPGA_TX_L0_DMA_DONE = 0x0004, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ FPGA_TX_L1_DMA_DONE = 0x0008, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ DECO_PIB_INTR = 0x0010, /*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ DECO_FMT_CHANGE = 0x0020, DECO_MBOX_RESP = 0x0040, DECO_RESUME_FRM_INTER_PAUSE = 0x0080, /*Not Handled in DPC Need to Fire Rx cmds on resume from Pause*/ }; enum ERROR_STATUS { NO_ERROR =0, RX_Y_DMA_ERR_L0 =0x0001,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ RX_UV_DMA_ERR_L0 =0x0002,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ RX_Y_DMA_ERR_L1 =0x0004,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ RX_UV_DMA_ERR_L1 =0x0008,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ TX_DMA_ERR_L0 =0x0010,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ TX_DMA_ERR_L1 =0x0020,/*DONT CHANGE VALUES...SOME BITWIZE OPERATIONS WILL FAIL*/ FW_CMD_ERROR =0x0040, DROP_REPEATED =0x0080, DROP_FLEA_FMTCH =0x0100,/*We do not want to deliver the flea dummy frame*/ DROP_DATA_ERROR =0x0200,/*We were not able to get the PIB correctly so drop the frame. */ DROP_SIZE_ERROR =0x0400,/*We were not able to get the size properly from hardware. */ FORCE_CANCEL =0x8000 }; enum LIST_STATUS { ListStsFree=0, /* Initial state and state the buffer is moved to Ready Buffer list. */ RxListWaitingForYIntr=1, /* When the Y Descriptor is posted. */ RxListWaitingForUVIntr=2, /* When the UV descriptor is posted. */ TxListWaitingForIntr =4, }; struct RX_DMA_LIST { enum LIST_STATUS ListSts; /*LIST_ENTRY ActiveList; */ uint32_t ActiveListLen; uint32_t ListLockInd; /* To Be Filled up During Init */ uint32_t ulDiscCount; /* Discontinuity On this list */ uint32_t RxYFirstDescLADDRReg; /* First Desc Low Addr Y */ uint32_t RxYFirstDescUADDRReg; /* First Desc UPPER Addr Y */ uint32_t RxYCurDescLADDRReg; /* Current Desc Low Addr Y */ uint32_t RxYCurDescUADDRReg; /* First Desc Low Addr Y */ uint32_t RxYCurByteCntRemReg; /* Cur Byte Cnt Rem Y */ uint32_t RxUVFirstDescLADDRReg; /* First Desc Low Addr UV */ uint32_t RxUVFirstDescUADDRReg; /* First Desc UPPER Addr UV */ uint32_t RxUVCurDescLADDRReg; /* Current Desc Low Addr UV */ uint32_t RxUVCurDescUADDRReg; /* Current Desc UPPER Addr UV */ uint32_t RxUVCurByteCntRemReg; /* Cur Byte Cnt Rem UV */ }; struct tx_dma_pkt { struct dma_desc_mem desc_mem; hw_comp_callback call_back; struct crystalhd_dio_req *dio_req; wait_queue_head_t *cb_event; uint32_t list_tag; }; struct crystalhd_rx_dma_pkt { struct dma_desc_mem desc_mem; struct crystalhd_dio_req *dio_req; uint32_t pkt_tag; uint32_t flags; BC_PIC_INFO_BLOCK pib; dma_addr_t uv_phy_addr; struct crystalhd_rx_dma_pkt *next; }; struct crystalhd_hw_stats{ uint32_t rx_errors; uint32_t tx_errors; uint32_t freeq_count; uint32_t rdyq_count; uint32_t num_interrupts; uint32_t dev_interrupts; uint32_t cin_busy; uint32_t pause_cnt; uint32_t rx_success; }; enum DECO_STATE { DECO_OPERATIONAL = 0, /* We start with this state.ST_FW_DWNLD,ST_CAPTURE,STOP_CAPTURE */ DECO_INTER_PAUSED = 1, /* Driver Issued Pause To Decoder */ DECO_INTER_PAUSE_IN_PROGRESS = 2, /* Pause CMD is pending with F/W */ DECO_INTER_RESUME_IN_PROGRESS = 3, /* Resume CMD is pending with F/W */ DECO_STOPPED_BY_APP = 4 /* After STOP Video I do not want to Throttle Decoder.So Special State */ }; /* */ /* These events can be used to notify the hardware layer */ /* to set up it adapter in proper state...or for anyother */ /* purpose for that matter. */ /* We will use this for intermediae events as defined below */ enum BRCM_EVENT { BC_EVENT_ADAPTER_INIT_FAILED =0, BC_EVENT_ADAPTER_INIT_SUCCESS =1, BC_EVENT_FW_DNLD_STARTED =2, BC_EVENT_FW_DNLD_ERR =3, BC_EVENT_FW_DNLD_DONE =4, BC_EVENT_SYS_SHUT_DOWN =5, BC_EVENT_START_CAPTURE =6, BC_EVENT_START_CAPTURE_IMMI =7, BC_EVENT_STOP_CAPTURE =8, /* Stop Capturing the Rx buffers Stop the DMA engines UnMapBuffers Discard Free and Ready list */ BC_EVENT_DO_CLEANUP =9, /* Total Cleanup Rx And Tx side */ BC_DISCARD_RX_BUFFERS =10 /* Move all the Ready buffers to free list. Stop RX DMA. Post Rx Side buffers. */ }; struct crystalhd_hw; /* forward declaration for the types */ /*typedef void* (*HW_VERIFY_DEVICE)(struct crystalhd_adp*); */ /*typedef bool (*HW_INIT_DEVICE_RESOURCES)(struct crystalhd_adp*); */ /*typedef bool (*HW_CLEAN_DEVICE_RESOURCES)(struct crystalhd_adp*); */ typedef bool (*HW_START_DEVICE)(struct crystalhd_hw*); typedef bool (*HW_STOP_DEVICE)(struct crystalhd_hw*); /* typedef bool (*HW_XLAT_AND_FIRE_SGL)(struct crystalhd_adp*,PVOID,PSCATTER_GATHER_LIST,uint32_t); */ /* typedef bool (*HW_RX_XLAT_SGL)(struct crystalhd_adp*,crystalhd_dio_req *ioreq); */ typedef bool (*HW_FIND_AND_CLEAR_INTR)(struct crystalhd_adp*,struct crystalhd_hw*); typedef uint32_t (*HW_READ_DEVICE_REG)(struct crystalhd_adp*,uint32_t); typedef void (*HW_WRITE_DEVICE_REG)(struct crystalhd_adp*,uint32_t,uint32_t); typedef uint32_t (*HW_READ_FPGA_REG)(struct crystalhd_adp*,uint32_t); typedef void (*HW_WRITE_FPGA_REG)(struct crystalhd_adp*,uint32_t,uint32_t); typedef BC_STATUS (*HW_READ_DEV_MEM)(struct crystalhd_hw*,uint32_t,uint32_t,uint32_t*); typedef BC_STATUS (*HW_WRITE_DEV_MEM)(struct crystalhd_hw*,uint32_t,uint32_t,uint32_t*); /* typedef bool (*HW_INIT_DRAM)(struct crystalhd_adp*); */ /* typedef bool (*HW_DISABLE_INTR)(struct crystalhd_adp*); */ /* typedef bool (*HW_ENABLE_INTR)(struct crystalhd_adp*); */ typedef BC_STATUS (*HW_POST_RX_SIDE_BUFF)(struct crystalhd_hw*,struct crystalhd_rx_dma_pkt*); typedef bool (*HW_CHECK_INPUT_FIFO)(struct crystalhd_hw*, uint32_t, uint32_t*,bool,uint8_t*); typedef void (*HW_START_TX_DMA)(struct crystalhd_hw*, uint8_t, addr_64); typedef BC_STATUS (*HW_STOP_TX_DMA)(struct crystalhd_hw*); /* typedef bool (*HW_EVENT_NOTIFICATION)(struct crystalhd_adp*,BRCM_EVENT); */ /* typedef bool (*HW_RX_POST_INTR_PROCESSING)(struct crystalhd_adp*,uint32_t,uint32_t); */ typedef void (*HW_GET_DONE_SIZE)(struct crystalhd_hw *hw, uint32_t, uint32_t*, uint32_t*); /* typedef bool (*HW_ADD_DRP_TO_FREE_LIST)(struct crystalhd_adp*,crystalhd_dio_req *ioreq); */ typedef struct crystalhd_dio_req* (*HW_FETCH_DONE_BUFFERS)(struct crystalhd_adp*,bool); /* typedef bool (*HW_ADD_ROLLBACK_RXBUF)(struct crystalhd_adp*,crystalhd_dio_req *ioreq); */ typedef bool (*HW_PEEK_NEXT_DECODED_RXBUF)(struct crystalhd_hw*,uint64_t*,uint32_t*,uint32_t); typedef BC_STATUS (*HW_FW_PASSTHRU_CMD)(struct crystalhd_hw*,PBC_FW_CMD); /* typedef bool (*HW_CANCEL_FW_CMDS)(struct crystalhd_adp*,OS_CANCEL_CALLBACK); */ /* typedef void* (*HW_GET_FW_DONE_OS_CMD)(struct crystalhd_adp*); */ /* typedef PBC_DRV_PIC_INFO (*SEARCH_FOR_PIB)(struct crystalhd_adp*,bool,uint32_t); */ /* typedef bool (*HW_DO_DRAM_PWR_MGMT)(struct crystalhd_adp*); */ typedef BC_STATUS (*HW_FW_DOWNLOAD)(struct crystalhd_hw*,uint8_t*,uint32_t); typedef BC_STATUS (*HW_ISSUE_DECO_PAUSE)(struct crystalhd_hw*, bool); typedef void (*HW_STOP_DMA_ENGINES)(struct crystalhd_hw*); /* typedef BOOLEAN (*FIRE_RX_REQ_TO_HW) (PHW_EXTENSION,PRX_DMA_LIST); typedef BOOLEAN (*PIC_POST_PROC) (PHW_EXTENSION,PRX_DMA_LIST,PULONG); typedef BOOLEAN (*HW_ISSUE_DECO_PAUSE) (PHW_EXTENSION,BOOLEAN,BOOLEAN); typedef BOOLEAN (*FIRE_TX_CMD_TO_HW) (PCONTEXT_FOR_POST_TX); */ typedef void (*NOTIFY_FLL_CHANGE)(struct crystalhd_hw*,bool); typedef bool (*HW_EVENT_NOTIFICATION)(struct crystalhd_hw*, enum BRCM_EVENT); struct crystalhd_hw { struct tx_dma_pkt tx_pkt_pool[DMA_ENGINE_CNT]; spinlock_t lock; uint32_t tx_ioq_tag_seed; uint32_t tx_list_post_index; struct crystalhd_rx_dma_pkt *rx_pkt_pool_head; uint32_t rx_pkt_tag_seed; bool dev_started; struct crystalhd_adp *adp; wait_queue_head_t *pfw_cmd_event; int fwcmd_evt_sts; uint32_t pib_del_Q_addr; uint32_t pib_rel_Q_addr; uint32_t channelNum; struct crystalhd_dioq *tx_freeq; struct crystalhd_dioq *tx_actq; /* Rx DMA Engine Specific Locks */ spinlock_t rx_lock; uint32_t rx_list_post_index; enum list_sts rx_list_sts[DMA_ENGINE_CNT]; struct crystalhd_dioq *rx_rdyq; struct crystalhd_dioq *rx_freeq; struct crystalhd_dioq *rx_actq; uint32_t stop_pending; uint32_t hw_pause_issued; uint32_t fwcmdPostAddr; uint32_t fwcmdPostMbox; uint32_t fwcmdRespMbox; /* HW counters.. */ struct crystalhd_hw_stats stats; /* Picture Information Block Management Variables */ uint32_t PICWidth; /* Pic Width Recieved On Format Change for link/With WidthField On Flea*/ uint32_t PICHeight; /* Pic Height Recieved on format change[Link and Flea]/Not Used in Flea*/ uint32_t LastPicNo; /* For Repeated Frame Detection */ uint32_t LastTwoPicNo; /* For Repeated Frame Detection on Interlace clip*/ uint32_t LastSessNum; /* For Session Change Detection */ struct semaphore fetch_sem; /* semaphore between fetch and probe of the next picture information, since both will be in process context */ uint32_t RxCaptureState; /* 0 if capture is not enabled, 1 if capture is enabled, 2 if stop rxdma is pending */ /* BCM70015 mods */ uint32_t PicQSts; /* This is the bitmap given by PiCQSts Interrupt*/ uint32_t TxBuffInfoAddr; /* Address of the TX Fifo in DRAM*/ uint32_t FleaRxPicDelAddr; /* Memory address where the pictures are fired*/ uint32_t FleaFLLUpdateAddr; /* Memory Address where FLL is updated*/ uint32_t FleaBmpIntrCnt; uint32_t RxSeqNum; uint32_t DrvEosDetected; uint32_t DrvCancelEosFlag; uint32_t SkipDropBadFrames; uint32_t TemperatureRegVal; TX_INPUT_BUFFER_INFO TxFwInputBuffInfo; enum DECO_STATE DecoderSt; /* Weather the decoder is paused or not*/ uint32_t PauseThreshold; uint32_t ResumeThreshold; uint32_t RxListPointer; /* Treat the Rx List As Circular List */ enum LIST_STATUS TxList0Sts; enum LIST_STATUS TxList1Sts; uint32_t FleaEnablePWM; uint32_t FleaWaitFirstPlaybackNotify; enum FLEA_POWER_STATES FleaPowerState; uint32_t EmptyCnt; bool SingleThreadAppFIFOEmpty; bool PwrDwnTxIntr; /* Got an TX FIFO status interrupt when in power down state */ bool PwrDwnPiQIntr; /* Got a Picture Q interrupt when in power down state */ uint32_t OLWatchDogTimer; uint32_t ILWatchDogTimer; uint32_t FwCmdCnt; bool WakeUpDecodeDone; /* Used to indicate that the HW is awake to RX is running so we can actively manage power */ uint64_t TickCntDecodePU; /* Time when we first powered up to decode */ uint64_t TickSpentInPD; /* Total amount of time spent in PD */ uint64_t TickStartInPD; /* Tick count when we start in PD */ uint32_t PDRatio; /* % of time spent in power down. Goal is to keep this close to 50 */ uint32_t DefaultPauseThreshold; /* default threshold to set when we start power management */ /* uint32_t FreeListLen; */ /* uint32_t ReadyListLen; */ /* */ /* Counters needed for monitoring purposes. */ /* These counters are per session and will be reset to zero in */ /* start capture. */ /* */ uint32_t DrvPauseCnt; /* Number of Times the driver has issued pause.*/ #if 0 uint32_t DrvServiceIntrCnt; /* Number of interrutps the driver serviced. */ uint32_t DrvIgnIntrCnt; /* Number of Interrupts Driver Ignored.NOT OUR INTR. */ uint32_t DrvTotalFrmDropped; /* Number of frames dropped by the driver.*/ #endif uint32_t DrvTotalFrmCaptured; /* Numner of Good Frames Captured*/ #if 0 uint32_t DrvTotalHWErrs; /* Total HW Errors.*/ uint32_t DrvTotalPIBFlushCnt; /* Number of Times the driver flushed PIB Queues.*/ uint32_t DrvMissedPIBCnt; /* Number of Frames for which the PIB was not found.*/ uint64_t TickCntOnPause; */ uint32_t TotalTimeInPause; /* In Milliseconds */ uint32_t RepeatedFramesCnt; */ #endif /* HW_VERIFY_DEVICE pfnVerifyDevice; */ /* HW_INIT_DEVICE_RESOURCES pfnInitDevResources; */ /* HW_CLEAN_DEVICE_RESOURCES pfnCleanDevResources; */ HW_START_DEVICE pfnStartDevice; HW_STOP_DEVICE pfnStopDevice; /* HW_XLAT_AND_FIRE_SGL pfnTxXlatAndFireSGL; */ /* HW_RX_XLAT_SGL pfnRxXlatSgl; */ HW_FIND_AND_CLEAR_INTR pfnFindAndClearIntr; HW_READ_DEVICE_REG pfnReadDevRegister; HW_WRITE_DEVICE_REG pfnWriteDevRegister; HW_READ_FPGA_REG pfnReadFPGARegister; HW_WRITE_FPGA_REG pfnWriteFPGARegister; HW_READ_DEV_MEM pfnDevDRAMRead; HW_WRITE_DEV_MEM pfnDevDRAMWrite; /* HW_INIT_DRAM pfnInitDRAM; */ /* HW_DISABLE_INTR pfnDisableIntr; */ /* HW_ENABLE_INTR pfnEnableIntr; */ HW_POST_RX_SIDE_BUFF pfnPostRxSideBuff; HW_CHECK_INPUT_FIFO pfnCheckInputFIFO; HW_START_TX_DMA pfnStartTxDMA; HW_STOP_TX_DMA pfnStopTxDMA; HW_GET_DONE_SIZE pfnHWGetDoneSize; /* HW_EVENT_NOTIFICATION pfnNotifyHardware; */ /* HW_ADD_DRP_TO_FREE_LIST pfnAddRxDRPToFreeList; */ /* HW_FETCH_DONE_BUFFERS pfnFetchReadyRxDRP; */ /* HW_ADD_ROLLBACK_RXBUF pfnRollBackRxBuf; */ HW_PEEK_NEXT_DECODED_RXBUF pfnPeekNextDeodedFr; HW_FW_PASSTHRU_CMD pfnDoFirmwareCmd; /* HW_GET_FW_DONE_OS_CMD pfnGetFWDoneCmdOsCntxt; */ /* HW_CANCEL_FW_CMDS pfnCancelFWCmds; */ /* SEARCH_FOR_PIB pfnSearchPIB; */ /* HW_DO_DRAM_PWR_MGMT pfnDRAMPwrMgmt; */ HW_FW_DOWNLOAD pfnFWDwnld; HW_ISSUE_DECO_PAUSE pfnIssuePause; HW_STOP_DMA_ENGINES pfnStopRXDMAEngines; /* FIRE_RX_REQ_TO_HW pfnFireRx; */ /* PIC_POST_PROC pfnPostProcessPicture; */ /* FIRE_TX_CMD_TO_HW pfnFireTx; */ NOTIFY_FLL_CHANGE pfnNotifyFLLChange; HW_EVENT_NOTIFICATION pfnNotifyHardware; }; struct crystalhd_rx_dma_pkt *crystalhd_hw_alloc_rx_pkt(struct crystalhd_hw *hw); void crystalhd_hw_free_rx_pkt(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *pkt); void crystalhd_tx_desc_rel_call_back(void *context, void *data); void crystalhd_rx_pkt_rel_call_back(void *context, void *data); void crystalhd_hw_delete_ioqs(struct crystalhd_hw *hw); BC_STATUS crystalhd_hw_create_ioqs(struct crystalhd_hw *hw); BC_STATUS crystalhd_hw_open(struct crystalhd_hw *hw, struct crystalhd_adp *adp); BC_STATUS crystalhd_hw_close(struct crystalhd_hw *hw, struct crystalhd_adp *adp); BC_STATUS crystalhd_hw_setup_dma_rings(struct crystalhd_hw *hw); BC_STATUS crystalhd_hw_free_dma_rings(struct crystalhd_hw *hw); BC_STATUS crystalhd_hw_tx_req_complete(struct crystalhd_hw *hw, uint32_t list_id, BC_STATUS cs); BC_STATUS crystalhd_hw_fill_desc(struct crystalhd_dio_req *ioreq, struct dma_descriptor *desc, dma_addr_t desc_paddr_base, uint32_t sg_cnt, uint32_t sg_st_ix, uint32_t sg_st_off, uint32_t xfr_sz, struct device *dev, uint32_t destDRAMaddr); BC_STATUS crystalhd_xlat_sgl_to_dma_desc(struct crystalhd_dio_req *ioreq, struct dma_desc_mem * pdesc_mem, uint32_t *uv_desc_index, struct device *dev, uint32_t destDRAMaddr); BC_STATUS crystalhd_rx_pkt_done(struct crystalhd_hw *hw, uint32_t list_index, BC_STATUS comp_sts); BC_STATUS crystalhd_hw_post_tx(struct crystalhd_hw *hw, struct crystalhd_dio_req *ioreq, hw_comp_callback call_back, wait_queue_head_t *cb_event, uint32_t *list_id, uint8_t data_flags); BC_STATUS crystalhd_hw_cancel_tx(struct crystalhd_hw *hw, uint32_t list_id); BC_STATUS crystalhd_hw_add_cap_buffer(struct crystalhd_hw *hw,struct crystalhd_dio_req *ioreq, bool en_post); BC_STATUS crystalhd_hw_get_cap_buffer(struct crystalhd_hw *hw,struct C011_PIB *pib,struct crystalhd_dio_req **ioreq); BC_STATUS crystalhd_hw_start_capture(struct crystalhd_hw *hw); BC_STATUS crystalhd_hw_stop_capture(struct crystalhd_hw *hw, bool unmap); BC_STATUS crystalhd_hw_suspend(struct crystalhd_hw *hw); BC_STATUS crystalhd_hw_resume(struct crystalhd_hw *hw); void crystalhd_hw_stats(struct crystalhd_hw *hw, struct crystalhd_hw_stats *stats); #define GET_Y0_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ MISC1_Y_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) #define GET_UV0_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L0_OVERRUN_ERROR_MASK | \ MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK | \ MISC1_UV_RX_ERROR_STATUS_RX_L0_DESC_TX_ABORT_ERRORS_MASK | \ MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) #define GET_Y1_ERR_MSK (MISC1_Y_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ MISC1_Y_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) #define GET_UV1_ERR_MSK (MISC1_UV_RX_ERROR_STATUS_RX_L1_OVERRUN_ERROR_MASK | \ MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK | \ MISC1_UV_RX_ERROR_STATUS_RX_L1_DESC_TX_ABORT_ERRORS_MASK | \ MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) #endif crystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_linkfuncs.h0000644000175000017500000002357311610313111024413 0ustar andresandres/*************************************************************************** * Copyright (c) 2005-2009, Broadcom Corporation. * * Name: crystalhd_linkfuncs . h * * Description: * BCM70012 Linux driver hardware layer. * * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ #ifndef _CRYSTALHD_LINKFUNCS_H_ #define _CRYSTALHD_LINKFUNCS_H_ #define ASPM_L1_ENABLE (BC_BIT(27)) /************************************************* 7412 Decoder Registers. **************************************************/ #define FW_CMD_BUFF_SZ 64 #define TS_Host2CpuSnd 0x00000100 #define HW_PauseMbx 0x00000300 #define Hst2CpuMbx1 0x00100F00 #define Cpu2HstMbx1 0x00100F04 #define MbxStat1 0x00100F08 #define Stream2Host_Intr_Sts 0x00100F24 #define C011_RET_SUCCESS 0x0 /* Reutrn status of firmware command. */ /* TS input status register */ #define TS_StreamAFIFOStatus 0x0010044C #define TS_StreamBFIFOStatus 0x0010084C /*UART Selection definitions*/ #define UartSelectA 0x00100300 #define UartSelectB 0x00100304 #define BSVS_UART_DEC_NONE 0x00 #define BSVS_UART_DEC_OUTER 0x01 #define BSVS_UART_DEC_INNER 0x02 #define BSVS_UART_STREAM 0x03 /* Code-In fifo */ #define REG_DecCA_RegCinCTL 0xa00 #define REG_DecCA_RegCinBase 0xa0c #define REG_DecCA_RegCinEnd 0xa10 #define REG_DecCA_RegCinWrPtr 0xa04 #define REG_DecCA_RegCinRdPtr 0xa08 #define REG_Dec_TsUser0Base 0x100864 #define REG_Dec_TsUser0Rdptr 0x100868 #define REG_Dec_TsUser0Wrptr 0x10086C #define REG_Dec_TsUser0End 0x100874 /* ASF Case ...*/ #define REG_Dec_TsAudCDB2Base 0x10036c #define REG_Dec_TsAudCDB2Rdptr 0x100378 #define REG_Dec_TsAudCDB2Wrptr 0x100374 #define REG_Dec_TsAudCDB2End 0x100370 /* DRAM bringup Registers */ #define SDRAM_PARAM 0x00040804 #define SDRAM_PRECHARGE 0x000408B0 #define SDRAM_EXT_MODE 0x000408A4 #define SDRAM_MODE 0x000408A0 #define SDRAM_REFRESH 0x00040890 #define SDRAM_REF_PARAM 0x00040808 #define DecHt_PllACtl 0x34000C #define DecHt_PllBCtl 0x340010 #define DecHt_PllCCtl 0x340014 #define DecHt_PllDCtl 0x340034 #define DecHt_PllECtl 0x340038 #define AUD_DSP_MISC_SOFT_RESET 0x00240104 #define AIO_MISC_PLL_RESET 0x0026000C #define PCIE_CLK_REQ_REG 0xDC #define PCI_CLK_REQ_ENABLE (BC_BIT(8)) /************************************************* F/W Copy engine definitions.. **************************************************/ #define BC_FWIMG_ST_ADDR 0x00000000 #define DecHt_HostSwReset 0x340000 #define BC_DRAM_FW_CFG_ADDR 0x001c2000 union intr_mask_reg { struct { uint32_t mask_tx_done:1; uint32_t mask_tx_err:1; uint32_t mask_rx_done:1; uint32_t mask_rx_err:1; uint32_t mask_pcie_err:1; uint32_t mask_pcie_rbusmast_err:1; uint32_t mask_pcie_rgr_bridge:1; uint32_t reserved:25; }; uint32_t whole_reg; }; union link_misc_perst_deco_ctrl { struct { uint32_t bcm7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/ uint32_t reserved0:3; /* Reserved.No Effect*/ uint32_t stop_bcm_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/ uint32_t reserved1:27; /* Reseved. No Effect*/ }; uint32_t whole_reg; }; union link_misc_perst_clk_ctrl { struct { uint32_t sel_alt_clk:1; /* When set, selects a 6.75MHz clock as the source of core_clk */ uint32_t stop_core_clk:1; /* When set, stops the branch of core_clk that is not needed for low power operation */ uint32_t pll_pwr_dn:1; /* When set, powers down the main PLL. The alternate clock bit should be set to select an alternate clock before setting this bit.*/ uint32_t reserved0:5; /* Reserved */ uint32_t pll_mult:8; /* This setting controls the multiplier for the PLL. */ uint32_t pll_div:4; /* This setting controls the divider for the PLL. */ uint32_t reserved1:12; /* Reserved */ }; uint32_t whole_reg; }; union link_misc_perst_decoder_ctrl { struct { uint32_t bcm_7412_rst:1; /* 1 -> BCM7412 is held in reset. Reset value 1.*/ uint32_t res0:3; /* Reserved.No Effect*/ uint32_t stop_7412_clk:1; /* 1 ->Stops branch of 27MHz clk used to clk BCM7412*/ uint32_t res1:27; /* Reseved. No Effect */ }; uint32_t whole_reg; }; /* DMA engine register BIT mask wrappers.. */ #define DMA_START_BIT MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK #define GET_RX_INTR_MASK (INTR_INTR_STATUS_L1_UV_RX_DMA_ERR_INTR_MASK | \ INTR_INTR_STATUS_L1_UV_RX_DMA_DONE_INTR_MASK | \ INTR_INTR_STATUS_L1_Y_RX_DMA_ERR_INTR_MASK | \ INTR_INTR_STATUS_L1_Y_RX_DMA_DONE_INTR_MASK | \ INTR_INTR_STATUS_L0_UV_RX_DMA_ERR_INTR_MASK | \ INTR_INTR_STATUS_L0_UV_RX_DMA_DONE_INTR_MASK | \ INTR_INTR_STATUS_L0_Y_RX_DMA_ERR_INTR_MASK | \ INTR_INTR_STATUS_L0_Y_RX_DMA_DONE_INTR_MASK) uint32_t link_dec_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off); void link_dec_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val); uint32_t crystalhd_link_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off); void crystalhd_link_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val); uint32_t crystalhd_link_dram_rd(struct crystalhd_hw *hw, uint32_t mem_off); void crystalhd_link_dram_wr(struct crystalhd_hw *hw, uint32_t mem_off, uint32_t val); BC_STATUS crystalhd_link_mem_rd(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *rd_buff); BC_STATUS crystalhd_link_mem_wr(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *wr_buff); void crystalhd_link_enable_uarts(struct crystalhd_hw *hw); void crystalhd_link_start_dram(struct crystalhd_hw *hw); bool crystalhd_link_bring_out_of_rst(struct crystalhd_hw *hw); bool crystalhd_link_put_in_reset(struct crystalhd_hw *hw); void crystalhd_link_disable_interrupts(struct crystalhd_hw *hw); void crystalhd_link_enable_interrupts(struct crystalhd_hw *hw); void crystalhd_link_clear_errors(struct crystalhd_hw *hw); void crystalhd_link_clear_interrupts(struct crystalhd_hw *hw); void crystalhd_link_soft_rst(struct crystalhd_hw *hw); bool crystalhd_link_load_firmware_config(struct crystalhd_hw *hw); bool crystalhd_link_start_device(struct crystalhd_hw *hw); bool crystalhd_link_stop_device(struct crystalhd_hw *hw); uint32_t link_GetPicInfoLineNum(struct crystalhd_dio_req *dio, uint8_t *base); uint32_t link_GetMode422Data(struct crystalhd_dio_req *dio, PBC_PIC_INFO_BLOCK pPicInfoLine, int type); uint32_t link_GetMetaDataFromPib(struct crystalhd_dio_req *dio, PBC_PIC_INFO_BLOCK pPicInfoLine); uint32_t link_GetHeightFromPib(struct crystalhd_dio_req *dio, PBC_PIC_INFO_BLOCK pPicInfoLine); bool link_GetPictureInfo(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, struct crystalhd_dio_req *dio, uint32_t *PicNumber, uint64_t *PicMetaData); uint32_t link_GetRptDropParam(struct crystalhd_hw *hw, uint32_t picHeight, uint32_t picWidth, void *pRxDMAReq); bool crystalhd_link_peek_next_decoded_frame(struct crystalhd_hw *hw, uint64_t *meta_payload, uint32_t *picNumFlags, uint32_t PicWidth); bool crystalhd_link_check_input_full(struct crystalhd_hw *hw, uint32_t needed_sz, uint32_t *empty_sz, bool b_188_byte_pkts, uint8_t *flags); bool crystalhd_link_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts); bool crystalhd_link_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts); void crystalhd_link_tx_isr(struct crystalhd_hw *hw, uint32_t int_sts); void crystalhd_link_start_tx_dma_engine(struct crystalhd_hw *hw, uint8_t list_id, addr_64 desc_addr); BC_STATUS crystalhd_link_stop_tx_dma_engine(struct crystalhd_hw *hw); uint32_t crystalhd_link_get_pib_avail_cnt(struct crystalhd_hw *hw); uint32_t crystalhd_link_get_addr_from_pib_Q(struct crystalhd_hw *hw); bool crystalhd_link_rel_addr_to_pib_Q(struct crystalhd_hw *hw, uint32_t addr_to_rel); void link_cpy_pib_to_app(struct C011_PIB *src_pib, BC_PIC_INFO_BLOCK *dst_pib); void crystalhd_link_proc_pib(struct crystalhd_hw *hw); void crystalhd_link_start_rx_dma_engine(struct crystalhd_hw *hw); void crystalhd_link_stop_rx_dma_engine(struct crystalhd_hw *hw); BC_STATUS crystalhd_link_hw_prog_rxdma(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *rx_pkt); BC_STATUS crystalhd_link_hw_post_cap_buff(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *rx_pkt); void crystalhd_link_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index, uint32_t *y_dw_dnsz, uint32_t *uv_dw_dnsz); void crystalhd_link_hw_finalize_pause(struct crystalhd_hw *hw); bool crystalhd_link_rx_list0_handler(struct crystalhd_hw *hw,uint32_t int_sts,uint32_t y_err_sts,uint32_t uv_err_sts); bool crystalhd_link_rx_list1_handler(struct crystalhd_hw *hw,uint32_t int_sts,uint32_t y_err_sts,uint32_t uv_err_sts); void crystalhd_link_rx_isr(struct crystalhd_hw *hw, uint32_t intr_sts); BC_STATUS crystalhd_link_hw_pause(struct crystalhd_hw *hw, bool state); BC_STATUS crystalhd_link_fw_cmd_post_proc(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd); BC_STATUS crystalhd_link_put_ddr2sleep(struct crystalhd_hw *hw); BC_STATUS crystalhd_link_download_fw(struct crystalhd_hw* hw, uint8_t* buffer, uint32_t sz); BC_STATUS crystalhd_link_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd); bool crystalhd_link_hw_interrupt_handle(struct crystalhd_adp *adp, struct crystalhd_hw *hw); void crystalhd_link_notify_fll_change(struct crystalhd_hw *hw, bool bCleanupContext); bool crystalhd_link_notify_event(struct crystalhd_hw *hw, enum BRCM_EVENT EventCode); #endif crystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_fleafuncs.c0000644000175000017500000025704311610313111024361 0ustar andresandres/*************************************************************************** * Copyright (c) 2005-2009, Broadcom Corporation. * * Name: crystalhd_fleafuncs.c * * Description: * BCM70015 Linux driver HW layer. * * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ #include #include #include #include #include #include "crystalhd_hw.h" #include "crystalhd_fleafuncs.h" #include "crystalhd_lnx.h" #include "FleaDefs.h" #include "crystalhd_flea_ddr.h" #define OFFSETOF(_s_, _m_) ((size_t)(unsigned long)&(((_s_ *)0)->_m_)) void crystalhd_flea_core_reset(struct crystalhd_hw *hw) { unsigned int pollCnt=0,regVal=0; dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_core_reset]: Starting core reset\n"); hw->pfnWriteDevRegister(hw->adp, BCHP_MISC3_RESET_CTRL, 0x01); pollCnt=0; while (1) { pollCnt++; regVal=0; msleep_interruptible(1); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC3_RESET_CTRL); if(!(regVal & 0x01)) { /* -- Bit is 0, Reset is completed. Which means that -- wait for sometime and then allow other accesses. */ msleep_interruptible(1); break; } if(pollCnt > MAX_VALID_POLL_CNT) { printk("!!FATAL ERROR!! Core Reset Failure\n"); break; } } msleep_interruptible(5); return; } void crystalhd_flea_disable_interrupts(struct crystalhd_hw *hw) { union FLEA_INTR_BITS_COMMON IntrMaskReg; /* -- Mask everything except the reserved bits. */ IntrMaskReg.WholeReg =0xffffffff; IntrMaskReg.Reserved1=0; IntrMaskReg.Reserved2=0; IntrMaskReg.Reserved3=0; IntrMaskReg.Reserved4=0; hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_MSK_SET_REG, IntrMaskReg.WholeReg); return; } void crystalhd_flea_enable_interrupts(struct crystalhd_hw *hw) { union FLEA_INTR_BITS_COMMON IntrMaskReg; /* -- Clear The Mask for everything except the reserved bits. */ IntrMaskReg.WholeReg =0xffffffff; IntrMaskReg.Reserved1=0; IntrMaskReg.Reserved2=0; IntrMaskReg.Reserved3=0; IntrMaskReg.Reserved4=0; hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_MSK_CLR_REG, IntrMaskReg.WholeReg); return; } void crystalhd_flea_clear_interrupts(struct crystalhd_hw *hw) { union FLEA_INTR_BITS_COMMON IntrStsValue; IntrStsValue.WholeReg = hw->pfnReadDevRegister(hw->adp, BCHP_INTR_INTR_STATUS); if(IntrStsValue.WholeReg) { hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_CLR_REG, IntrStsValue.WholeReg); hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_EOI_CTRL, 1); } return; } bool crystalhd_flea_detect_ddr3(struct crystalhd_hw *hw) { uint32_t regVal = 0; /*Set the Multiplexer to select the GPIO-6*/ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0); /*Make sure that the bits-24:27 are reset*/ if(regVal & 0x0f000000) { regVal = regVal & 0xf0ffffff; /*Clear bit 24-27 for selecting GPIO_06*/ hw->pfnWriteDevRegister(hw->adp, BCHP_SUN_TOP_CTRL_PIN_MUX_CTRL_0, regVal); } regVal=0; /*Set the Direction of GPIO-6*/ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_GIO_IODIR_LO); if(!(regVal & BC_BIT(6))) { /*Set the Bit number 6 to make the GPIO6 as input*/ regVal |= BC_BIT(6); hw->pfnWriteDevRegister(hw->adp, BCHP_GIO_IODIR_LO, regVal); } regVal=0; regVal = hw->pfnReadDevRegister(hw->adp, BCHP_GIO_DATA_LO); /*If this bit is clear then have DDR-3 else we have DDR-2*/ if(!(regVal & BC_BIT(6))) { dev_dbg(&hw->adp->pdev->dev,"DDR-3 Detected\n"); return true; } dev_dbg(&hw->adp->pdev->dev,"DDR-2 Detected\n"); return false; } void crystalhd_flea_init_dram(struct crystalhd_hw *hw) { int32_t ddr2_speed_grade[2]; uint32_t sd_0_col_size, sd_0_bank_size, sd_0_row_size; uint32_t sd_1_col_size, sd_1_bank_size, sd_1_row_size; uint32_t ddr3_mode[2]; uint32_t regVal; bool bDDR3Detected=false; /*Should be filled in using the detection logic. Default to DDR2 */ /* On all designs we are using DDR2 or DDR3 x16 and running at a max of 400Mhz */ /* Only one bank of DDR supported. The other is a dummy */ ddr2_speed_grade[0] = DDR2_400MHZ; ddr2_speed_grade[1] = DDR2_400MHZ; sd_0_col_size = COL_BITS_10; sd_0_bank_size = BANK_SIZE_8; sd_0_row_size = ROW_SIZE_8K; /* DDR2 */ /* sd_0_row_size = ROW_SIZE_16K; // DDR3 */ sd_1_col_size = COL_BITS_10; sd_1_bank_size = BANK_SIZE_8; sd_1_row_size = ROW_SIZE_8K; ddr3_mode[0] = 0; ddr3_mode[1] = 0; bDDR3Detected = crystalhd_flea_detect_ddr3(hw); if(bDDR3Detected) { ddr3_mode[0] = 1; sd_0_row_size = ROW_SIZE_16K; /* DDR3 */ sd_1_row_size = ROW_SIZE_16K; /* DDR3 */ } /* Step 1. PLL Init */ crystalhd_flea_ddr_pll_config(hw, ddr2_speed_grade, 1, 0); /* only need to configure PLLs in TM0 */ /* Step 2. DDR CTRL Init */ crystalhd_flea_ddr_ctrl_init(hw, 0, ddr3_mode[0], ddr2_speed_grade[0], sd_0_col_size, sd_0_bank_size, sd_0_row_size, 0); /* Step 3 RTS Init - Real time scheduling memory arbiter */ crystalhd_flea_ddr_arb_rts_init(hw); /* NAREN turn off ODT. The REF1 and SV1 and most customer designs allow this. */ /* IF SOMEONE COMPLAINS ABOUT MEMORY OR DATA CORRUPTION LOOK HERE FIRST */ /*hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_LOAD_EMODE_CMD, 0x02, false); */ /*regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS3); regVal &= ~(BCHP_DDR23_CTL_REGS_0_PARAMS3_wr_odt_en_MASK); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS3, regVal);*/ /*regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL); regVal |= BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL_seltxdrv_ci_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_DRIVE_PAD_CTL, regVal); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL); regVal |= BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL_seltxdrv_ci_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_DRIVE_PAD_CTL, regVal);*/ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE); regVal |= BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE_clk_pad_dis_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_PAD_DISABLE, regVal); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL); regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL_dq_odt_enable_MASK); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_READ_CONTROL, regVal); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL); regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL_dq_odt_enable_MASK); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_READ_CONTROL, regVal); return; } uint32_t crystalhd_flea_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off) { uint32_t baseAddr = reg_off >> 16; void *regAddr; if (!adp) { printk(KERN_ERR "%s: Invalid args\n", __func__); return 0; } if(baseAddr == 0 || baseAddr == FLEA_GISB_DIRECT_BASE) /* Direct Mapped Region */ { regAddr = adp->i2o_addr + (reg_off & 0x0000FFFF); if(regAddr > (adp->i2o_addr + adp->pci_i2o_len)) { dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", __func__, reg_off); return 0; } return readl(regAddr); } else /* non directly mapped region */ { if(adp->pci_i2o_len < 0xFFFF) { printk("Un-expected mapped region size\n"); return 0; } regAddr = adp->i2o_addr + FLEA_GISB_INDIRECT_ADDRESS; writel(reg_off | 0x10000000, regAddr); regAddr = adp->i2o_addr + FLEA_GISB_INDIRECT_DATA; return readl(regAddr); } } void crystalhd_flea_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val) { uint32_t baseAddr = reg_off >> 16; void *regAddr; if (!adp) { printk(KERN_ERR "%s: Invalid args\n", __func__); return; } if(baseAddr == 0 || baseAddr == FLEA_GISB_DIRECT_BASE) /* Direct Mapped Region */ { regAddr = adp->i2o_addr + (reg_off & 0x0000FFFF); if(regAddr > (adp->i2o_addr + adp->pci_i2o_len)) { dev_err(&adp->pdev->dev, "%s: reg_off out of range: 0x%08x\n", __func__, reg_off); return ; } writel(val, regAddr); } else /* non directly mapped region */ { if(adp->pci_i2o_len < 0xFFFF) { printk("Un-expected mapped region size\n"); return; } regAddr = adp->i2o_addr + FLEA_GISB_INDIRECT_ADDRESS; writel(reg_off | 0x10000000, regAddr); regAddr = adp->i2o_addr + FLEA_GISB_INDIRECT_DATA; writel(val, regAddr); } } /** * crystalhd_flea_mem_rd - Read data from DRAM area. * @adp: Adapter instance * @start_off: Start offset. * @dw_cnt: Count in dwords. * @rd_buff: Buffer to copy the data from dram. * * Return: * Status. * * Dram read routine. */ BC_STATUS crystalhd_flea_mem_rd(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *rd_buff) { uint32_t ix = 0; uint32_t addr = start_off, base; if (!hw || !rd_buff) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } if( hw->FleaPowerState == FLEA_PS_LP_COMPLETE ) { /*printk(KERN_ERR "%s: Flea power down, cann't read memory.\n", __func__); */ return BC_STS_BUSY; } if((start_off + dw_cnt * 4) > FLEA_TOTAL_DRAM_SIZE) { printk(KERN_ERR "Access beyond DRAM limit at Addr 0x%x and size 0x%x words\n", start_off, dw_cnt); return BC_STS_ERROR; } /* Set the base addr for the 512kb window */ hw->pfnWriteDevRegister(hw->adp, BCHP_MISC2_DIRECT_WINDOW_CONTROL, (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK) | BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK); for (ix = 0; ix < dw_cnt; ix++) { rd_buff[ix] = readl(hw->adp->mem_addr + (addr & ~BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK)); base = addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK; addr += 4; /* DWORD access at all times */ if (base != (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK)) { /* Set the base addr for next 512kb window */ hw->pfnWriteDevRegister(hw->adp, BCHP_MISC2_DIRECT_WINDOW_CONTROL, (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK) | BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK); } } return BC_STS_SUCCESS; } /** * crystalhd_flea_mem_wr - Write data to DRAM area. * @adp: Adapter instance * @start_off: Start offset. * @dw_cnt: Count in dwords. * @wr_buff: Data Buffer to be written. * * Return: * Status. * * Dram write routine. */ BC_STATUS crystalhd_flea_mem_wr(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *wr_buff) { uint32_t ix = 0; uint32_t addr = start_off, base; uint32_t temp; if (!hw || !wr_buff) { printk(KERN_ERR "%s: Invalid arg\n", __func__); return BC_STS_INV_ARG; } if( hw->FleaPowerState == FLEA_PS_LP_COMPLETE ) { /*printk(KERN_ERR "%s: Flea power down, cann't write memory.\n", __func__); */ return BC_STS_BUSY; } if((start_off + dw_cnt * 4) > FLEA_TOTAL_DRAM_SIZE) { printk("Access beyond DRAM limit at Addr 0x%x and size 0x%x words\n", start_off, dw_cnt); return BC_STS_ERROR; } /* Set the base addr for the 512kb window */ hw->pfnWriteDevRegister(hw->adp, BCHP_MISC2_DIRECT_WINDOW_CONTROL, (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK) | BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK); for (ix = 0; ix < dw_cnt; ix++) { writel(wr_buff[ix], hw->adp->mem_addr + (addr & ~BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK)); base = addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK; addr += 4; /* DWORD access at all times */ if (base != (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK)) { /* Set the base addr for next 512kb window */ hw->pfnWriteDevRegister(hw->adp, BCHP_MISC2_DIRECT_WINDOW_CONTROL, (addr & BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_BASE_ADDR_MASK) | BCHP_MISC2_DIRECT_WINDOW_CONTROL_DIRECT_WINDOW_ENABLE_MASK); } } /*Dummy Read To Flush Memory Arbitrator*/ crystalhd_flea_mem_rd(hw, start_off, 1, &temp); return BC_STS_SUCCESS; } static void crystalhd_flea_runtime_power_up(struct crystalhd_hw *hw) { uint32_t regVal; uint64_t currTick; uint32_t totalTick_Hi; uint32_t TickSpentInPD_Hi; uint64_t temp_64; long totalTick_Hi_f; long TickSpentInPD_Hi_f; /*printk("RT PU \n"); */ /* NAREN This function restores clocks and power to the DRAM and to the core to bring the decoder back up to full operation */ /* Start the DRAM controller clocks first */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); regVal &= ~(BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_MASK); hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); /* Delay to allow the DRAM clock to stabilize */ udelay(25); /* Power Up PHY and start clocks on DRAM device */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL); regVal &= ~(BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_MASK); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL, regVal); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); regVal &= ~(BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, regVal); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL, ~(BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK)); /* Delay to allow the PLL to lock */ udelay(25); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL); regVal &= ~(BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_MASK ); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, regVal); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL); regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_MASK); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL, regVal); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL); regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_MASK); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL, regVal); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_MASK ); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, regVal); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); regVal &= ~(BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_MASK ); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, regVal); /* Start Refresh Cycles from controller */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0); regVal |= BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_enable_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0, regVal); /* turn off self-refresh */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2); regVal &= ~(BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_MASK); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2, regVal); udelay(5); /* Issue refresh cycle */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, 0x60); /* Enable the ARM AVD and BLINK clocks */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); regVal &= ~(BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK); hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, 0x03000000); /* Start arbiter */ hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL, BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Enable); #ifdef _POWER_HANDLE_AVD_WATCHDOG_ /* Restore Watchdog timers */ /* Make sure the timeouts do not happen */ /*Outer Loop Watchdog timer */ hw->pfnWriteDevRegister(hw->adp, BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR, hw->OLWatchDogTimer); /*//Inner Loop Watchdog timer */ hw->pfnWriteDevRegister(hw->adp, BCHP_DECODE_CPUREGS2_0_REG_WATCHDOG_TMR, hw->ILWatchDogTimer); #endif /*printk("RT Power Up Flea Complete\n"); */ rdtscll(currTick); hw->TickSpentInPD += (currTick - hw->TickStartInPD); temp_64 = (hw->TickSpentInPD)>>24; TickSpentInPD_Hi = (uint32_t)(temp_64); TickSpentInPD_Hi_f = (long)TickSpentInPD_Hi; temp_64 = (currTick - hw->TickCntDecodePU)>>24; totalTick_Hi = (uint32_t)(temp_64); totalTick_Hi_f = (long)totalTick_Hi; if( totalTick_Hi_f <= 0 ) { temp_64 = (hw->TickSpentInPD); TickSpentInPD_Hi = (uint32_t)(temp_64); TickSpentInPD_Hi_f = (long)TickSpentInPD_Hi; temp_64 = (currTick - hw->TickCntDecodePU); totalTick_Hi = (uint32_t)(temp_64); totalTick_Hi_f = (long)totalTick_Hi; } if( totalTick_Hi_f <= 0 ) { printk("totalTick_Hi_f <= 0, set hw->PDRatio = 60\n"); hw->PDRatio = 60; } else hw->PDRatio = (TickSpentInPD_Hi_f * 100) / totalTick_Hi_f; /*printk("Ticks currently spent in PD: 0x%llx Total: 0x%llx Ratio %d,\n", */ /* hw->TickSpentInPD, (currTick - hw->TickCntDecodePU), hw->PDRatio); */ /* NAREN check if the PD ratio is greater than 75. If so, try to increase the PauseThreshold to improve the ratio */ /* never go higher than the default threshold */ if((hw->PDRatio > 75) && (hw->PauseThreshold < hw->DefaultPauseThreshold)) { /*printk("Current PDRatio:%u, PauseThreshold:%u, DefaultPauseThreshold:%u, incress PauseThreshold.\n", */ /* hw->PDRatio, hw->PauseThreshold, hw->DefaultPauseThreshold); */ hw->PauseThreshold++; } else { /*printk("Current PDRatio:%u, PauseThreshold:%u, DefaultPauseThreshold:%u, don't incress PauseThreshold.\n", */ /* hw->PDRatio, hw->PauseThreshold, hw->DefaultPauseThreshold); */ } return; } static void crystalhd_flea_runtime_power_dn(struct crystalhd_hw *hw) { uint32_t regVal; uint32_t pollCnt; /*printk("RT PD \n"); */ hw->DrvPauseCnt++; /* NAREN This function stops the decoder clocks including the AVD, ARM and DRAM */ /* It powers down the DRAM device and places the DRAM into self-refresh */ #ifdef _POWER_HANDLE_AVD_WATCHDOG_ /* Make sure the timeouts do not happen */ /* Because the AVD drops to a debug prompt and stops decoding if it hits any watchdogs */ /*Outer Loop Watchdog timer */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR); hw->OLWatchDogTimer = regVal; hw->pfnWriteDevRegister(hw->adp, BCHP_DECODE_CPUREGS_0_REG_WATCHDOG_TMR, 0xffffffff); /*Inner Loop Watchdog timer */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DECODE_CPUREGS2_0_REG_WATCHDOG_TMR); hw->ILWatchDogTimer = regVal; hw->pfnWriteDevRegister(hw->adp, BCHP_DECODE_CPUREGS2_0_REG_WATCHDOG_TMR, 0xffffffff); #endif /* Stop memory arbiter first to freese memory access */ hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL, BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Disable); /* delay at least 15us for memory transactions to complete */ /* udelay(15); */ /* Wait for MEMC to become idle. Continue even if we are no since worst case this would just mean higher power consumption */ pollCnt=0; while (pollCnt++ <= 400) /*200 */ { regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_CTL_STATUS); if(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_MASK) { /* udelay(10); */ break; } udelay(10); } /*If we failed Start the arbiter and return*/ if(!(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_MASK)) { printk("RT PD : failed Start the arbiter and return.\n"); hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL, BCHP_PRI_ARB_CONTROL_REGS_MASTER_CTL_arb_disable_Enable); return; } /* Disable the AVD, ARM and BLINK clocks*/ /*regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); regVal |= BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regValE);*/ /* turn on self-refresh */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2); regVal |= BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2, regVal); /* Issue refresh cycle */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, 0x60); /* Stop Refresh Cycles from controller */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0); regVal &= ~(BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0_enable_MASK); hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0, regVal); /* Check if we are in self-refresh. Continue even if we are no since worst case this would just mean higher power consumption */ pollCnt=0; while(pollCnt++ < 100) { regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_CTL_STATUS); if(!(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_MASK)) break; } regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); regVal |= BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); /* Power down PHY and stop clocks on DRAM */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL); regVal |= BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_MASK | BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_iddq_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, regVal); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL); regVal |= BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_MASK | BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_iddq_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, regVal); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL); regVal |= BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL, regVal); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL); regVal |= BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL, regVal); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL); regVal |= BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_MASK | BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_MASK | BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_rxenb_MASK | BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_cke_reb_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, regVal); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL, BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); regVal |= BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, regVal); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL); regVal |= BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL, regVal); /* Finally clock off the DRAM controller */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); regVal |= BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); /* udelay(20); */ /*printk("RT Power Down Flea Complete\n"); */ /* Measure how much time we spend in idle */ rdtscll(hw->TickStartInPD); return; } bool crystalhd_flea_detect_fw_alive(struct crystalhd_hw *hw) { uint32_t pollCnt = 0; uint32_t hbCnt = 0; uint32_t heartBeatReg1 = 0; uint32_t heartBeatReg2 = 0; bool bRetVal = false; heartBeatReg1 = hw->pfnReadDevRegister(hw->adp, HEART_BEAT_REGISTER); while(1) { heartBeatReg2 = hw->pfnReadDevRegister(hw->adp, HEART_BEAT_REGISTER); if(heartBeatReg1 != heartBeatReg2) { hbCnt++; heartBeatReg1 = heartBeatReg2; } if(hbCnt >= HEART_BEAT_POLL_CNT) { bRetVal = true; break; } pollCnt++; if(pollCnt >= FLEA_MAX_POLL_CNT) { bRetVal = false; break; } msleep_interruptible(1); } return bRetVal; } void crystalhd_flea_handle_PicQSts_intr(struct crystalhd_hw *hw) { uint32_t newChBitmap=0; newChBitmap = hw->pfnReadDevRegister(hw->adp, RX_DMA_PIC_QSTS_MBOX); hw->PicQSts = newChBitmap; /* -- For link we were enabling the capture on format change -- For Flea, we will get a PicQSts interrupt where we will -- enable the capture. */ if(hw->RxCaptureState != 1) { hw->RxCaptureState = 1; } } void crystalhd_flea_update_tx_buff_info(struct crystalhd_hw *hw) { TX_INPUT_BUFFER_INFO TxBuffInfo; uint32_t ReadSzInDWords=0; ReadSzInDWords = (sizeof(TxBuffInfo) - sizeof(TxBuffInfo.Reserved))/4; hw->pfnDevDRAMRead(hw, hw->TxBuffInfoAddr, ReadSzInDWords, (uint32_t*)&TxBuffInfo); if(TxBuffInfo.DramBuffAdd % 4) { printk("Tx Err:: DWORD UNAligned Tx Addr. Not Updating\n"); return; } hw->TxFwInputBuffInfo.DramBuffAdd = TxBuffInfo.DramBuffAdd; hw->TxFwInputBuffInfo.DramBuffSzInBytes = TxBuffInfo.DramBuffSzInBytes; hw->TxFwInputBuffInfo.Flags = TxBuffInfo.Flags; hw->TxFwInputBuffInfo.HostXferSzInBytes = TxBuffInfo.HostXferSzInBytes; hw->TxFwInputBuffInfo.SeqNum = TxBuffInfo.SeqNum; return; } /* was HWFleaNotifyFllChange */ void crystalhd_flea_notify_fll_change(struct crystalhd_hw *hw, bool bCleanupContext) { unsigned long flags = 0; uint32_t freeListLen = 0; /* * When we are doing the cleanup we should update DRAM only if the * firmware is running. So Detect the heart beat. */ if(bCleanupContext && (!crystalhd_flea_detect_fw_alive(hw))) return; spin_lock_irqsave(&hw->lock, flags); freeListLen = crystalhd_dioq_count(hw->rx_freeq); hw->pfnDevDRAMWrite(hw, hw->FleaFLLUpdateAddr, 1, &freeListLen); spin_unlock_irqrestore(&hw->lock, flags); return; } static void crystalhd_flea_init_power_state(struct crystalhd_hw *hw) { hw->FleaEnablePWM = false; /* enable by default */ hw->FleaPowerState = FLEA_PS_NONE; } static bool crystalhd_flea_set_power_state(struct crystalhd_hw *hw, enum FLEA_POWER_STATES NewState) { bool StChangeSuccess=false; uint32_t tempFLL = 0; uint32_t freeListLen = 0; BC_STATUS sts; struct crystalhd_rx_dma_pkt *rx_pkt = NULL; freeListLen = crystalhd_dioq_count(hw->rx_freeq); switch(NewState) { case FLEA_PS_ACTIVE: { /*Transition to Active State*/ if(hw->FleaPowerState == FLEA_PS_LP_PENDING) { StChangeSuccess = true; hw->FleaPowerState = FLEA_PS_ACTIVE; /* Write the correct FLL to FW */ hw->pfnDevDRAMWrite(hw, hw->FleaFLLUpdateAddr, 1, &freeListLen); /* We need to check to post here because we may never get a context to post otherwise */ if(hw->PicQSts != 0) { rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); if (rx_pkt) sts = hw->pfnPostRxSideBuff(hw, rx_pkt); } /*printk(" Success\n"); */ }else if(hw->FleaPowerState == FLEA_PS_LP_COMPLETE){ crystalhd_flea_runtime_power_up(hw); StChangeSuccess = true; hw->FleaPowerState = FLEA_PS_ACTIVE; /* Write the correct FLL to FW */ hw->pfnDevDRAMWrite(hw, hw->FleaFLLUpdateAddr, 1, &freeListLen); /* Now check if we missed processing PiQ and TXFIFO interrupts when we were in power down */ if (hw->PwrDwnPiQIntr) { crystalhd_flea_handle_PicQSts_intr(hw); hw->PwrDwnPiQIntr = false; } /* We need to check to post here because we may never get a context to post otherwise */ if(hw->PicQSts != 0) { rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); if (rx_pkt) sts = hw->pfnPostRxSideBuff(hw, rx_pkt); } if (hw->PwrDwnTxIntr) { crystalhd_flea_update_tx_buff_info(hw); hw->PwrDwnTxIntr = false; } } break; } case FLEA_PS_LP_PENDING: { if(hw->FleaPowerState != FLEA_PS_ACTIVE) { break; } /*printk(" Success\n"); */ StChangeSuccess = true; /* Write 0 FLL to FW to prevent it from sending PQ*/ hw->pfnDevDRAMWrite(hw, hw->FleaFLLUpdateAddr, 1, &tempFLL); hw->FleaPowerState = FLEA_PS_LP_PENDING; break; } case FLEA_PS_LP_COMPLETE: { if( (hw->FleaPowerState == FLEA_PS_ACTIVE) || (hw->FleaPowerState == FLEA_PS_LP_PENDING)) { /* Write 0 FLL to FW to prevent it from sending PQ*/ hw->pfnDevDRAMWrite(hw, hw->FleaFLLUpdateAddr, 1, &tempFLL); crystalhd_flea_runtime_power_dn(hw); StChangeSuccess = true; hw->FleaPowerState = FLEA_PS_LP_COMPLETE; } break; } default: break; } return StChangeSuccess; } /* * Look At Different States and List Status and decide on * Next Logical State To Be In. */ static void crystalhd_flea_set_next_power_state(struct crystalhd_hw *hw, enum FLEA_STATE_CH_EVENT PowerEvt) { enum FLEA_POWER_STATES NextPS; NextPS = hw->FleaPowerState; if( hw->FleaEnablePWM == false ) { hw->FleaPowerState = FLEA_PS_ACTIVE; return; } /* printk("Trying Power State Transition from %x Because Of Event:%d \n", */ /* hw->FleaPowerState, */ /* PowerEvt); */ if(PowerEvt == FLEA_EVT_STOP_DEVICE) { hw->FleaPowerState = FLEA_PS_STOPPED; return; } if(PowerEvt == FLEA_EVT_START_DEVICE) { hw->FleaPowerState = FLEA_PS_ACTIVE; return; } switch(hw->FleaPowerState) { case FLEA_PS_ACTIVE: { if(PowerEvt == FLEA_EVT_FLL_CHANGE) { /*Ready List Was Decremented. */ /*printk("1:TxL0Sts:%x TxL1Sts:%x EmptyCnt:%x RxL0Sts:%x RxL1Sts:%x FwCmdCnt:%x\n", */ /* hw->TxList0Sts, */ /* hw->TxList1Sts, */ /* hw->EmptyCnt, */ /* hw->rx_list_sts[0], */ /* hw->rx_list_sts[1], */ /* hw->FwCmdCnt); */ if( (hw->TxList0Sts == ListStsFree) && (hw->TxList1Sts == ListStsFree) && (!hw->EmptyCnt) && /*We have Not Indicated Any Empty Fifo to Application*/ (!hw->SingleThreadAppFIFOEmpty) && /*for single threaded apps*/ (!(hw->rx_list_sts[0] && rx_waiting_y_intr)) && (!(hw->rx_list_sts[1] && rx_waiting_y_intr)) && (!hw->FwCmdCnt)) { NextPS = FLEA_PS_LP_COMPLETE; }else{ NextPS = FLEA_PS_LP_PENDING; } } break; } case FLEA_PS_LP_PENDING: { if( (PowerEvt == FLEA_EVT_FW_CMD_POST) || (PowerEvt == FLEA_EVT_FLL_CHANGE)) { NextPS = FLEA_PS_ACTIVE; }else if(PowerEvt == FLEA_EVT_CMD_COMP){ /*printk("2:TxL0Sts:%x TxL1Sts:%x EmptyCnt:%x STAppFIFOEmpty:%x RxL0Sts:%x RxL1Sts:%x FwCmdCnt:%x\n", */ /* hw->TxList0Sts, */ /* hw->TxList1Sts, */ /* hw->EmptyCnt, */ /* hw->SingleThreadAppFIFOEmpty, */ /* hw->rx_list_sts[0], */ /* hw->rx_list_sts[1], */ /* hw->FwCmdCnt); */ if( (hw->TxList0Sts == ListStsFree) && (hw->TxList1Sts == ListStsFree) && (!hw->EmptyCnt) && /*We have Not Indicated Any Empty Fifo to Application*/ (!hw->SingleThreadAppFIFOEmpty) && /*for single threaded apps*/ (!(hw->rx_list_sts[0] && rx_waiting_y_intr)) && (!(hw->rx_list_sts[1] && rx_waiting_y_intr)) && (!hw->FwCmdCnt)) { NextPS = FLEA_PS_LP_COMPLETE; } } break; } case FLEA_PS_LP_COMPLETE: { if( (PowerEvt == FLEA_EVT_FLL_CHANGE) || (PowerEvt == FLEA_EVT_FW_CMD_POST)) { NextPS = FLEA_PS_ACTIVE; } break; } default: { printk("Invalid Flea Power State %x\n", hw->FleaPowerState); break; } } if(hw->FleaPowerState != NextPS) { printk("%s:State Transition [FromSt:%x ToSt:%x] Because Of Event:%d \n", __FUNCTION__, hw->FleaPowerState, NextPS, PowerEvt); crystalhd_flea_set_power_state(hw,NextPS); } return; } /* was FleaSetRxPicFireAddr */ #if 0 static void crystalhd_flea_set_rx_pic_fire_addr(struct crystalhd_hw *hw, uint32_t BorshContents) { hw->FleaRxPicDelAddr = BorshContents + 1 + HOST_TO_FW_PIC_DEL_INFO_ADDR; hw->FleaFLLUpdateAddr = BorshContents + 1 + HOST_TO_FW_FLL_ADDR; return; } #endif void crystalhd_flea_init_temperature_measure (struct crystalhd_hw *hw, bool bTurnOn) { hw->TemperatureRegVal=0; if(bTurnOn) { hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_TEMP_MON_CTRL, 0x3); hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_TEMP_MON_CTRL, 0x203); } else { hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_TEMP_MON_CTRL, 0x103); } return; } /* was HwFleaUpdateTempInfo */ void crystalhd_flea_update_temperature(struct crystalhd_hw *hw) { uint32_t regVal = 0; regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_TEMP_MON_STATUS); hw->TemperatureRegVal = regVal; return; } /** * crystalhd_flea_download_fw - Write data to DRAM area. * @adp: Adapter instance * @pBuffer: Buffer pointer for the FW data. * @buffSz: data size in bytes. * * Return: * Status. * * Flea firmware download routine. */ BC_STATUS crystalhd_flea_download_fw(struct crystalhd_hw *hw, uint8_t *pBuffer, uint32_t buffSz) { uint32_t pollCnt=0,regVal=0; uint32_t borchStachAddr=0; uint32_t *pCmacSig=NULL,cmacOffset=0,i=0; /*uint32_t BuffSz = (BuffSzInDWords * 4); */ /*uint32_t HBCnt=0; */ bool bRetVal = true; bool bSecure = true; // Default production cards. Can be false only for internal Broadcom dev cards dev_dbg(&hw->adp->pdev->dev, "[%s]: Sz:%d\n", __func__, buffSz); /* *-- Step 1. Enable the SRCUBBING and DRAM SCRAMBLING *-- Step 2. Poll for SCRAM_KEY_DONE_INT. *-- Step 3. Write the BORCH and STARCH addresses. *-- Step 4. Write the firmware to DRAM. *-- Step 5. Write the CMAC to SCRUB->CMAC registers. *-- Step 6. Write the ARM run bit to 1. *-- Step 7. Poll for BOOT verification done interrupt. */ /* First validate that we got data in the FW buffer */ if (buffSz == 0) return BC_STS_ERROR; /*-- Step 1. Enable the SRCUBBING and DRAM SCRAMBLING. */ /* Can we set both the bits at the same time?? Security Arch Doc describes the steps */ /* and the first step is to enable scrubbing and then scrambling. */ if(bSecure) { dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 1. Enable scrubbing\n"); /* Enable Scrubbing */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_SCRUB_CTRL_SCRUB_ENABLE); regVal |= SCRUB_ENABLE_BIT; hw->pfnWriteDevRegister(hw->adp, BCHP_SCRUB_CTRL_SCRUB_ENABLE, regVal); /* Enable Scrambling */ regVal |= DRAM_SCRAM_ENABLE_BIT; hw->pfnWriteDevRegister(hw->adp, BCHP_SCRUB_CTRL_SCRUB_ENABLE, regVal); //-- Step 2. Poll for SCRAM_KEY_DONE_INT. dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 2. Poll for SCRAM_KEY_DONE_INT\n"); pollCnt=0; while(pollCnt < FLEA_MAX_POLL_CNT) { regVal = hw->pfnReadDevRegister(hw->adp, BCHP_WRAP_MISC_INTR2_PCI_STATUS); if(regVal & SCRAM_KEY_DONE_INT_BIT) break; pollCnt++; msleep_interruptible(1); /*1 Milli Sec delay*/ } /* -- Will Assert when we do not see SCRAM_KEY_DONE_INTERRUPT */ if(!(regVal & SCRAM_KEY_DONE_INT_BIT)) { dev_err(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 2. Did not get scram key done interrupt.\n"); return BC_STS_ERROR; } } /*Clear the interrupts by writing the register value back*/ regVal &= 0x00FFFFFF; /*Mask off the reserved bits.[24-31] */ hw->pfnWriteDevRegister(hw->adp, BCHP_WRAP_MISC_INTR2_PCI_CLEAR, regVal); /*-- Step 3. Write the BORCH and STARCH addresses. */ borchStachAddr = GetScrubEndAddr(buffSz); if(!bSecure) borchStachAddr = (buffSz - 1) & BCHP_SCRUB_CTRL_BORCH_END_ADDRESS_BORCH_END_ADDR_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_SCRUB_CTRL_BORCH_END_ADDRESS, borchStachAddr); hw->pfnWriteDevRegister(hw->adp, BCHP_SCRUB_CTRL_STARCH_END_ADDRESS, borchStachAddr); /* * Now the command address is * relative to firmware file size. */ /*FWIFSetFleaCmdAddr(pHWExt->pFwExt, */ /* borchStachAddr+1+DDRADDR_4_FWCMDS); */ hw->fwcmdPostAddr = borchStachAddr+1+DDRADDR_4_FWCMDS; hw->fwcmdPostMbox = FW_CMD_POST_MBOX; hw->fwcmdRespMbox = FW_CMD_RES_MBOX; /*FleaSetRxPicFireAddr(pHWExt,borchStachAddr); */ hw->FleaRxPicDelAddr = borchStachAddr + 1 + HOST_TO_FW_PIC_DEL_INFO_ADDR; hw->FleaFLLUpdateAddr = borchStachAddr + 1 + HOST_TO_FW_FLL_ADDR; dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 3. Write the BORCH and STARCH addresses. %x:%x, %x:%x\n", BCHP_SCRUB_CTRL_BORCH_END_ADDRESS, borchStachAddr, BCHP_SCRUB_CTRL_STARCH_END_ADDRESS, borchStachAddr ); /*-- Step 4. Write the firmware to DRAM. [Without the Signature, 32-bit access to DRAM] */ dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 4. Write the firmware to DRAM. Sz:%d Bytes\n", buffSz - FLEA_FW_SIG_LEN_IN_BYTES - LENGTH_FIELD_SIZE); if(bSecure) hw->pfnDevDRAMWrite(hw, FW_DOWNLOAD_START_ADDR, (buffSz - FLEA_FW_SIG_LEN_IN_BYTES - LENGTH_FIELD_SIZE)/4, (uint32_t *)pBuffer); else hw->pfnDevDRAMWrite(hw, FW_DOWNLOAD_START_ADDR, buffSz/4, (uint32_t*)pBuffer); /* -- Step 5. Write the signature to CMAC register. */ /* -- This is what we need to write to CMAC registers. ================================================================================== Register Offset Boot Image CMAC Value ================================================================================== BCHP_SCRUB_CTRL_BI_CMAC_31_0 0x000f600c CMAC Bits[31:0] BCHP_SCRUB_CTRL_BI_CMAC_63_32 0x000f6010 CMAC Bits[63:32] BCHP_SCRUB_CTRL_BI_CMAC_95_64 0x000f6014 CMAC Bits[95:64] BCHP_SCRUB_CTRL_BI_CMAC_127_96 0x000f6018 CMAC Bits[127:96] ================================================================================== */ if(bSecure) { dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 5. Write the signature to CMAC register.\n"); cmacOffset = buffSz - FLEA_FW_SIG_LEN_IN_BYTES; pCmacSig = (uint32_t *) &pBuffer[cmacOffset]; for(i=0;i < FLEA_FW_SIG_LEN_IN_DWORD;i++) { uint32_t offSet = (BCHP_SCRUB_CTRL_BI_CMAC_127_96 - (i * 4)); hw->pfnWriteDevRegister(hw->adp, offSet, cpu_to_be32(*pCmacSig)); pCmacSig++; } } /*-- Step 6. Write the ARM run bit to 1. */ /* We need a write back because we do not want to change other bits */ dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 6. Write the ARM run bit to 1.\n"); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL); regVal |= ARM_RUN_REQ_BIT; hw->pfnWriteDevRegister(hw->adp, BCHP_ARMCR4_BRIDGE_REG_BRIDGE_CTL, regVal); if(bSecure) { /* -- Step 7. Poll for Boot Verification done/failure interrupt.*/ dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Poll for Boot Verification done/failure interrupt.\n"); pollCnt=0; while(1) { regVal = hw->pfnReadDevRegister(hw->adp, BCHP_WRAP_MISC_INTR2_PCI_STATUS); if(regVal & BOOT_VER_FAIL_BIT ) { dev_err(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Error bit occured. RetVal:%x\n", regVal); bRetVal = false; break; } if(regVal & BOOT_VER_DONE_BIT) { dev_dbg(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Done RetVal:%x\n", regVal); bRetVal = true; /*This is the only place we return TRUE from*/ break; } pollCnt++; if( pollCnt >= FLEA_MAX_POLL_CNT ) { dev_err(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Both done and failure bits are not set.\n"); bRetVal = false; break; } msleep_interruptible(5); /*5 Milli Sec delay*/ } if( !bRetVal ) { dev_info(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 7. Firmware image signature failure.\n"); return BC_STS_ERROR; } /*Clear the interrupts by writing the register value back*/ regVal &= 0x00FFFFFF; //Mask off the reserved bits.[24-31] hw->pfnWriteDevRegister(hw->adp, BCHP_WRAP_MISC_INTR2_PCI_CLEAR, regVal); msleep_interruptible(10); /*10 Milli Sec delay*/ } else bRetVal = true; /* -- It was seen on Dell390 systems that the firmware command was fired before the -- firmware was actually ready to accept the firmware commands. The driver did -- not recieve a response for the firmware commands and this was causing the DIL to timeout -- ,reclaim the resources and crash. The following code looks for the heartbeat and -- to make sure that we return from this function only when we get the heart beat making sure -- that the firmware is running. */ bRetVal = crystalhd_flea_detect_fw_alive(hw); if( !bRetVal ) { dev_info(&hw->adp->pdev->dev,"[crystalhd_flea_download_fw]: step 8. Detect firmware heart beat failed.\n"); return BC_STS_ERROR; } dev_dbg(&hw->adp->pdev->dev, "[%s]: Complete.\n", __func__); return BC_STS_SUCCESS; } bool crystalhd_flea_start_device(struct crystalhd_hw *hw) { uint32_t regVal = 0; bool bRetVal = false; /* -- Issue Core reset to bring in the default values in place */ crystalhd_flea_core_reset(hw); /* -- If the gisb arbitar register is not set to some other value -- and the firmware crashes, we see a NMI since the hardware did -- not respond to a register read at all. The PCI-E trace confirms the problem. -- Right now we are setting the register values to 0x7e00 and will check later -- what should be the correct value to program. */ hw->pfnWriteDevRegister(hw->adp, BCHP_SUN_GISB_ARB_TIMER, 0xd80); /* -- Disable all interrupts */ crystalhd_flea_clear_interrupts(hw); crystalhd_flea_disable_interrupts(hw); /* -- Enable the option for getting the done count in -- Rx DMA engine. */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_DMA_DEBUG_OPTIONS_REG); regVal |= 0x10; hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_DMA_DEBUG_OPTIONS_REG, regVal); /* -- Enable the TX DMA Engine once on startup. -- This is a new bit added. */ hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_TX_DMA_CTRL, 0x01); /* -- Enable the RX3 DMA Engine once on startup. -- This is a new bit added. */ hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_DMA_CTRL, 0x01); /* -- Set the Run bit for RX-Y and RX-UV DMA engines. */ hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, 0x01); /* -- Make sure Early L1 is disabled - NAREN - This will not prevent the device from entering L1 under active mode */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC_PERST_CLOCK_CTRL); regVal &= ~BCHP_MISC_PERST_CLOCK_CTRL_EARLY_L1_EXIT_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_MISC_PERST_CLOCK_CTRL, regVal); crystalhd_flea_init_dram(hw); msleep_interruptible(5); /* Enable the Single Shot Transaction on PCI by disabling the */ /* bit 29 of transaction configuration register */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_PCIE_TL_TRANSACTION_CONFIGURATION); regVal &= (~(BC_BIT(29))); hw->pfnWriteDevRegister(hw->adp, BCHP_PCIE_TL_TRANSACTION_CONFIGURATION, regVal); crystalhd_flea_init_temperature_measure(hw,true); crystalhd_flea_init_power_state(hw); crystalhd_flea_set_next_power_state(hw, FLEA_EVT_START_DEVICE); /* -- Enable all interrupts */ crystalhd_flea_clear_interrupts(hw); crystalhd_flea_enable_interrupts(hw); /* -- This is the only time we set this pointer for Flea. -- Since there is no stop the pointer is not reset anytime.... -- except for fatal errors. */ hw->rx_list_post_index = 0; hw->RxCaptureState = 0; msleep_interruptible(1); return bRetVal; } bool crystalhd_flea_stop_device(struct crystalhd_hw *hw) { uint32_t regVal=0, pollCnt=0; /* -- Issue the core reset so that we -- make sure there is nothing running. */ crystalhd_flea_core_reset(hw); crystalhd_flea_init_temperature_measure(hw, false); /* -- If the gisb arbitrater register is not set to some other value -- and the firmware crashes, we see a NMI since the hardware did -- not respond to a register read at all. The PCI-E trace confirms the problem. -- Right now we are setting the register values to 0x7e00 and will check later -- what should be the correct value to program. */ hw->pfnWriteDevRegister(hw->adp, BCHP_SUN_GISB_ARB_TIMER, 0xd80); /* -- Disable the TX DMA Engine once on shutdown. -- This is a new bit added. */ hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_TX_DMA_CTRL, 0x0); /* -- Disable the RX3 DMA Engine once on Stop. -- This is a new bit added. */ hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_DMA_CTRL, 0x0); /* -- Clear the RunStop Bit For RX DMA Control */ hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_SW_DESC_LIST_CTRL_STS, 0x0); hw->pfnWriteDevRegister(hw->adp, BCHP_PRI_ARB_CONTROL_REGS_REFRESH_CTL_0, 0x0); /* * Wait for MEMC to become idle */ pollCnt=0; while (1) { regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_CTL_STATUS); if(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_idle_MASK) break; pollCnt++; if(pollCnt >= 100) break; msleep_interruptible(1); } /*First Disable the AVD and ARM before disabling the DRAM*/ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); regVal = BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); /* -- Disable the interrupt after disabling the ARM and AVD. -- We should be able to access the registers because we still -- have not disabled the clock for blink block. We disable the -- blick 108 abd 216 clock at the end of this function. */ crystalhd_flea_clear_interrupts(hw); crystalhd_flea_disable_interrupts(hw); /*Now try disabling the DRAM.*/ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2); regVal |= BCHP_DDR23_CTL_REGS_0_PARAMS2_clke_MASK; /* * disable CKE */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_PARAMS2, regVal); /* * issue refresh command */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_REFRESH_CMD, 0x60); pollCnt=0; while(1) { regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_CTL_REGS_0_CTL_STATUS); if(!(regVal & BCHP_DDR23_CTL_REGS_0_CTL_STATUS_clke_MASK)) break; pollCnt++; if(pollCnt >= 100) break; msleep_interruptible(1); } /* * Enable DDR clock, DM and READ_ENABLE pads power down and force into the power down */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL, BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_idle_MASK | BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dm_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dq_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_read_enb_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_dqs_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_0_IDLE_PAD_CONTROL_clk_iddq_MASK); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL, BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_idle_MASK | BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dm_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dq_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_read_enb_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_dqs_iddq_MASK | BCHP_DDR23_PHY_BYTE_LANE_1_IDLE_PAD_CONTROL_clk_iddq_MASK); /* * Power down BL LDO cells */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL, BCHP_DDR23_PHY_BYTE_LANE_0_CLOCK_REG_CONTROL_pwrdn_MASK); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL, BCHP_DDR23_PHY_BYTE_LANE_1_CLOCK_REG_CONTROL_pwrdn_MASK); /* * Enable DDR control signal pad power down and force into the power down */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL, BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_idle_MASK | BCHP_DDR23_PHY_CONTROL_REGS_IDLE_PAD_CONTROL_ctl_iddq_MASK); /* * Disable ddr phy clock */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL, BCHP_DDR23_PHY_CONTROL_REGS_CLK_PM_CTRL_DIS_DDR_CLK_MASK); /* * Disable PLL output */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, regVal & ~BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_ENB_CLKOUT_MASK); /* * Power down addr_ctl LDO cells */ hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL, BCHP_DDR23_PHY_CONTROL_REGS_CLOCK_REG_CONTROL_pwrdn_MASK); /* * Power down the PLL */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG); hw->pfnWriteDevRegister(hw->adp, BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG, regVal | BCHP_DDR23_PHY_CONTROL_REGS_PLL_CONFIG_PWRDN_MASK); /* shut down the PLL1 */ regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PLL1_CTRL); hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PLL1_CTRL, regVal | BCHP_CLK_PLL1_CTRL_POWERDOWN_MASK); hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PLL0_ARM_DIV, 0xff); regVal = hw->pfnReadDevRegister(hw->adp, BCHP_CLK_PM_CTRL); regVal |= BCHP_CLK_PM_CTRL_DIS_SUN_27_LOW_PWR_MASK | BCHP_CLK_PM_CTRL_DIS_SUN_108_LOW_PWR_MASK | BCHP_CLK_PM_CTRL_DIS_MISC_OTP_9_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_ARM_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_BLINK_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_MISC_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_BLINK_216_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_DDR_108_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_DDR_216_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_AVD_216_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_MISC_216_CLK_MASK | BCHP_CLK_PM_CTRL_DIS_SUN_216_CLK_MASK; hw->pfnWriteDevRegister(hw->adp, BCHP_CLK_PM_CTRL, regVal); crystalhd_flea_set_next_power_state(hw, FLEA_EVT_STOP_DEVICE); return true; } bool crystalhd_flea_wake_up_hw(struct crystalhd_hw *hw) { if(hw->FleaPowerState != FLEA_PS_ACTIVE) { crystalhd_flea_set_next_power_state(hw, FLEA_EVT_FLL_CHANGE); } /* Now notify HW of the number of entries in the Free List */ /* This starts up the channel bitmap delivery */ crystalhd_flea_notify_fll_change(hw, false); hw->WakeUpDecodeDone = true; return true; } bool crystalhd_flea_check_input_full(struct crystalhd_hw *hw, uint32_t needed_sz, uint32_t *empty_sz, bool b_188_byte_pkts, uint8_t *flags) { uint32_t regVal=0; TX_INPUT_BUFFER_INFO *pTxBuffInfo; uint32_t FlagsAddr=0; *empty_sz = 0; /* *DramAddrOut=0; */ /* Add condition here to wake up the HW in case some application is trying to do TX before starting RX - like FP */ /* To prevent deadlocks. We are called here from Synchronized context so we can safely call this directly */ if(hw->WakeUpDecodeDone != true) { /* Only wake up the HW if we are either being called from a single threaded app - like FP */ /* or if we are not checking for the input buffer size as just a test */ if(*flags == 0) crystalhd_flea_wake_up_hw(hw); else { *empty_sz = 2 * 1024 * 1024; /* FW Buffer size */ /**DramAddrOut=0; */ *flags=0; return false; } } /* if we have told the app that we have buffer empty then we cannot go to low power */ if((hw->FleaPowerState != FLEA_PS_ACTIVE) && !hw->SingleThreadAppFIFOEmpty) { /**TxBuffSzOut=0; */ /**DramAddrOut=0; */ *empty_sz = 0; *flags=0; /*printk("PD can't Tx\n"); */ return true; /*Indicate FULL*/ } if(hw->TxFwInputBuffInfo.Flags & DFW_FLAGS_TX_ABORT) { *empty_sz=0; /**DramAddrOut=0; */ *flags |= DFW_FLAGS_TX_ABORT; return true; } if( (hw->TxFwInputBuffInfo.DramBuffSzInBytes < needed_sz) ||(!hw->TxFwInputBuffInfo.DramBuffAdd)) { *empty_sz=0; /**DramAddrOut=0; */ *flags=0; return true; /*Indicate FULL*/ } if(hw->TxFwInputBuffInfo.DramBuffAdd % 4) { /* -- Indicate Full if we get a non-dowrd aligned address. -- This will avoid us posting the command to firmware and -- The TX will timeout and we will close the application properly. -- This avoids a illegal operation as far as the TX is concerned. */ printk("TxSDRAM-Destination Address Not DWORD Aligned:%x\n",hw->TxFwInputBuffInfo.DramBuffAdd); return true; } /* -- We got everything correctly from the firmware and hence we should be -- able to do the DMA. Indicate what app wants to hear. -- Firmware SAYS: I AM HUNGRY, GIVE ME FOOD. :) */ *empty_sz=hw->TxFwInputBuffInfo.DramBuffSzInBytes; /**dramAddrOut=pHWExt->TxFwInputBuffInfo.DramBuffAdd; */ /* printk("empty size is %d\n", *empty_sz); */ /* If we are just checking stats and are not actually going to DMA, don't increment */ /* But we have to account for single threaded apps */ if((*flags & 0x08) == 0x08) { /* This is a synchronized function */ /* NAREN - In single threaded mode, if we have less than a defined size of buffer */ /* ask the firmware to wrap around. To prevent deadlocks. */ if(hw->TxFwInputBuffInfo.DramBuffSzInBytes < TX_WRAP_THRESHOLD) { pTxBuffInfo = (TX_INPUT_BUFFER_INFO *) (0); FlagsAddr = hw->TxBuffInfoAddr + ((uintptr_t) (&pTxBuffInfo->Flags)); /* Read Modify the Flags to ask the FW to WRAP */ hw->pfnDevDRAMRead(hw,FlagsAddr,1,®Val); regVal |= DFW_FLAGS_WRAP; hw->pfnDevDRAMWrite(hw,FlagsAddr,1,®Val); /* Indicate Busy to the application because we have to get new buffers from FW */ *empty_sz=0; /* *DramAddrOut=0; */ *flags=0; /* Wait for the next interrupt from the HW */ hw->TxFwInputBuffInfo.DramBuffSzInBytes = 0; hw->TxFwInputBuffInfo.DramBuffAdd = 0; return true; } else hw->SingleThreadAppFIFOEmpty = true; } else if((*flags & 0x04) != 0x04) hw->EmptyCnt++; /*OS_INTERLOCK_INCREMENT(&pHWExt->EmptyCnt); */ /* Different from our Windows implementation */ /* set bit 7 of the flags field to indicate that we have to use the destination address for TX */ *flags |= BC_BIT(7); return false; /*Indicate Empty*/ } BC_STATUS crystalhd_flea_fw_cmd_post_proc(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd) { BC_STATUS sts = BC_STS_SUCCESS; struct DecRspChannelStartVideo *st_rsp = NULL; struct C011_TS_CMD *pGenRsp = NULL; struct DecRspChannelChannelOpen *pRsp = NULL; pGenRsp = (struct C011_TS_CMD *) fw_cmd->rsp; switch (fw_cmd->cmd[0]) { case eCMD_C011_DEC_CHAN_STREAM_OPEN: hw->channelNum = pGenRsp->ulParams[2]; dev_dbg(&hw->adp->pdev->dev, "Snooped Stream Open Cmd For ChNo:%x\n", hw->channelNum); break; case eCMD_C011_DEC_CHAN_OPEN: pRsp = (struct DecRspChannelChannelOpen *)pGenRsp; hw->channelNum = pRsp->ChannelID; /* used in Flea to update the Tx Buffer stats */ hw->TxBuffInfoAddr = pRsp->transportStreamCaptureAddr; hw->TxFwInputBuffInfo.DramBuffAdd=0; hw->TxFwInputBuffInfo.DramBuffSzInBytes=0; hw->TxFwInputBuffInfo.Flags=0; hw->TxFwInputBuffInfo.HostXferSzInBytes=0; hw->TxFwInputBuffInfo.SeqNum=0; /* NAREN Init power management states here when we start the channel */ hw->PwrDwnTxIntr = false; hw->PwrDwnPiQIntr = false; hw->EmptyCnt = 0; hw->SingleThreadAppFIFOEmpty = false; dev_dbg(&hw->adp->pdev->dev, "Snooped ChOpen Cmd For ChNo:%x TxBuffAddr:%x\n", hw->channelNum, hw->TxBuffInfoAddr); break; case eCMD_C011_DEC_CHAN_START_VIDEO: st_rsp = (struct DecRspChannelStartVideo *)fw_cmd->rsp; hw->pib_del_Q_addr = st_rsp->picInfoDeliveryQ; hw->pib_rel_Q_addr = st_rsp->picInfoReleaseQ; dev_dbg(&hw->adp->pdev->dev, "Snooping CHAN_START_VIDEO command to get the Addr of Del/Rel Queue\n"); dev_dbg(&hw->adp->pdev->dev, "DelQAddr:%x RelQAddr:%x\n", hw->pib_del_Q_addr, hw->pib_rel_Q_addr); break; default: break; } return sts; } BC_STATUS crystalhd_flea_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd) { struct device *dev; uint32_t cnt = 0, cmd_res_addr; uint32_t *cmd_buff, *res_buff; wait_queue_head_t fw_cmd_event; int rc = 0; BC_STATUS sts; unsigned long flags; crystalhd_create_event(&fw_cmd_event); if (!hw || !fw_cmd) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } dev = &hw->adp->pdev->dev; dev_dbg(dev, "%s entered\n", __func__); cmd_buff = fw_cmd->cmd; res_buff = fw_cmd->rsp; if (!cmd_buff || !res_buff) { dev_err(dev, "Invalid Parameters for F/W Command\n"); return BC_STS_INV_ARG; } hw->fwcmd_evt_sts = 0; hw->pfw_cmd_event = &fw_cmd_event; hw->FwCmdCnt++; if(hw->FleaPowerState != FLEA_PS_ACTIVE) { crystalhd_flea_set_next_power_state(hw, FLEA_EVT_FW_CMD_POST); } spin_lock_irqsave(&hw->lock, flags); /*Write the command to the memory*/ hw->pfnDevDRAMWrite(hw, hw->fwcmdPostAddr, FW_CMD_BUFF_SZ, cmd_buff); /*Memory Read for memory arbitrator flush*/ hw->pfnDevDRAMRead(hw, hw->fwcmdPostAddr, 1, &cnt); /* Write the command address to mailbox */ hw->pfnWriteDevRegister(hw->adp, hw->fwcmdPostMbox, hw->fwcmdPostAddr); spin_unlock_irqrestore(&hw->lock, flags); msleep_interruptible(50); /* FW commands should complete even if we got a signal from the upper layer */ crystalhd_wait_on_event(&fw_cmd_event, hw->fwcmd_evt_sts, 20000, rc, true); if (!rc) { sts = BC_STS_SUCCESS; } else if (rc == -EBUSY) { dev_err(dev, "Firmware command T/O\n"); sts = BC_STS_TIMEOUT; } else if (rc == -EINTR) { dev_info(dev, "FwCmd Wait Signal - Can Never Happen\n"); sts = BC_STS_IO_USER_ABORT; } else { dev_err(dev, "FwCmd IO Error.\n"); sts = BC_STS_IO_ERROR; } if (sts != BC_STS_SUCCESS) { dev_err(dev, "FwCmd Failed.\n"); return sts; } spin_lock_irqsave(&hw->lock, flags); /*Get the Responce Address*/ cmd_res_addr = hw->pfnReadDevRegister(hw->adp, hw->fwcmdRespMbox); /*Read the Response*/ hw->pfnDevDRAMRead(hw, cmd_res_addr, FW_CMD_BUFF_SZ, res_buff); spin_unlock_irqrestore(&hw->lock, flags); if (res_buff[2] != 0) { dev_err(dev, "res_buff[2] != C011_RET_SUCCESS\n"); return BC_STS_FW_CMD_ERR; } sts = crystalhd_flea_fw_cmd_post_proc(hw, fw_cmd); if (sts != BC_STS_SUCCESS) dev_err(dev, "crystalhd_fw_cmd_post_proc Failed.\n"); return sts; } void crystalhd_flea_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index, uint32_t *y_dw_dnsz, uint32_t *uv_dw_dnsz) { uint32_t y_dn_sz_reg, uv_dn_sz_reg; if (!list_index) { y_dn_sz_reg = BCHP_MISC1_Y_RX_LIST0_CUR_BYTE_CNT; uv_dn_sz_reg = BCHP_MISC1_HIF_RX_LIST0_CUR_BYTE_CNT; } else { y_dn_sz_reg = BCHP_MISC1_Y_RX_LIST1_CUR_BYTE_CNT; uv_dn_sz_reg = BCHP_MISC1_HIF_RX_LIST1_CUR_BYTE_CNT; } *y_dw_dnsz = hw->pfnReadFPGARegister(hw->adp, y_dn_sz_reg); *uv_dw_dnsz = hw->pfnReadFPGARegister(hw->adp, uv_dn_sz_reg); return ; } BC_STATUS crystalhd_flea_hw_pause(struct crystalhd_hw *hw, bool state) { /*printk("%s: Set flea to power down.\n", __func__); */ crystalhd_flea_set_next_power_state(hw, FLEA_EVT_FLL_CHANGE); return BC_STS_SUCCESS; } bool crystalhd_flea_peek_next_decoded_frame(struct crystalhd_hw *hw, uint64_t *meta_payload, uint32_t *picNumFlags, uint32_t PicWidth) { unsigned long flags = 0; struct crystalhd_dioq *ioq; struct crystalhd_elem *tmp; struct crystalhd_rx_dma_pkt *rpkt; *meta_payload = 0; ioq = hw->rx_rdyq; spin_lock_irqsave(&ioq->lock, flags); if ((ioq->count > 0) && (ioq->head != (struct crystalhd_elem *)&ioq->head)) { tmp = ioq->head; spin_unlock_irqrestore(&ioq->lock, flags); rpkt = (struct crystalhd_rx_dma_pkt *)tmp->data; if (rpkt) { flea_GetPictureInfo(hw, rpkt, picNumFlags, meta_payload); /*printk("%s: flea_GetPictureInfo Pic#:%d\n", __func__, PicNumber); */ } return true; } spin_unlock_irqrestore(&ioq->lock, flags); return false; } void crystalhd_flea_clear_rx_errs_intrs(struct crystalhd_hw *hw) /* -- Clears all the errors and interrupt on RX DMA engine. */ { uint32_t ulRegVal; union FLEA_INTR_BITS_COMMON IntrToClear,IntrSts; IntrToClear.WholeReg = 0; IntrSts.WholeReg = 0; IntrSts.WholeReg = hw->pfnReadDevRegister(hw->adp, BCHP_INTR_INTR_STATUS); if(IntrSts.WholeReg) { ulRegVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS); hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS, ulRegVal); ulRegVal = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS); hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS, ulRegVal); IntrToClear.L0UVRxDMADone = IntrSts.L0UVRxDMADone; IntrToClear.L0UVRxDMAErr = IntrSts.L0UVRxDMAErr; IntrToClear.L0YRxDMADone = IntrSts.L0YRxDMADone; IntrToClear.L0YRxDMAErr = IntrSts.L0YRxDMAErr; IntrToClear.L1UVRxDMADone = IntrSts.L1UVRxDMADone; IntrToClear.L1UVRxDMAErr = IntrSts.L1UVRxDMAErr; IntrToClear.L1YRxDMADone = IntrSts.L1YRxDMADone; IntrToClear.L1YRxDMAErr = IntrSts.L1YRxDMAErr; hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_CLR_REG, IntrToClear.WholeReg); hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_EOI_CTRL, 1); } return; } void crystalhd_flea_stop_rx_dma_engine(struct crystalhd_hw *hw) { union FLEA_INTR_BITS_COMMON IntrStsValue; bool failedL0 = true, failedL1 = true; uint32_t pollCnt = 0; hw->RxCaptureState = 2; if((hw->rx_list_sts[0] == sts_free) && (hw->rx_list_sts[1] == sts_free)) { hw->RxCaptureState = 0; hw->RxSeqNum = 0; return; /* Nothing to be done */ } if(hw->rx_list_sts[0] == sts_free) failedL0 = false; if(hw->rx_list_sts[1] == sts_free) failedL1 = false; while(1) { IntrStsValue.WholeReg = hw->pfnReadDevRegister(hw->adp, BCHP_INTR_INTR_STATUS); if(hw->rx_list_sts[0] != sts_free) { if( (IntrStsValue.L0YRxDMADone) || (IntrStsValue.L0YRxDMAErr) || (IntrStsValue.L0UVRxDMADone) || (IntrStsValue.L0UVRxDMAErr) ) { failedL0 = false; } } else failedL0 = false; if(hw->rx_list_sts[1] != sts_free) { if( (IntrStsValue.L1YRxDMADone) || (IntrStsValue.L1YRxDMAErr) || (IntrStsValue.L1UVRxDMADone) || (IntrStsValue.L1UVRxDMAErr) ) { failedL1 = false; } } else failedL1 = false; msleep_interruptible(10); if(pollCnt >= MAX_VALID_POLL_CNT) break; if((failedL0 == false) && (failedL1 == false)) break; pollCnt++; } if(failedL0 || failedL1) printk("Failed to stop RX DMA\n"); hw->RxCaptureState = 0; hw->RxSeqNum = 0; crystalhd_flea_clear_rx_errs_intrs(hw); } BC_STATUS crystalhd_flea_hw_fire_rxdma(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *rx_pkt) { struct device *dev; addr_64 desc_addr; unsigned long flags; PIC_DELIVERY_HOST_INFO PicDeliInfo; uint32_t BuffSzInDwords; if (!hw || !rx_pkt) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return BC_STS_INV_ARG; } dev = &hw->adp->pdev->dev; if (hw->rx_list_post_index >= DMA_ENGINE_CNT) { dev_err(dev, "List Out Of bounds %x\n", hw->rx_list_post_index); return BC_STS_INV_ARG; } if(hw->RxCaptureState != 1) { dev_err(dev, "Capture not enabled\n"); return BC_STS_BUSY; } spin_lock_irqsave(&hw->rx_lock, flags); if (hw->rx_list_sts[hw->rx_list_post_index]) { dev_dbg(dev, "HW list is busy\n"); spin_unlock_irqrestore(&hw->rx_lock, flags); return BC_STS_BUSY; } if (!TEST_BIT(hw->PicQSts, hw->channelNum)) { /* NO pictures available for this channel */ dev_dbg(dev, "No Picture Available for DMA\n"); spin_unlock_irqrestore(&hw->rx_lock, flags); return BC_STS_BUSY; } CLEAR_BIT(hw->PicQSts, hw->channelNum); desc_addr.full_addr = rx_pkt->desc_mem.phy_addr; PicDeliInfo.ListIndex = hw->rx_list_post_index; PicDeliInfo.RxSeqNumber = hw->RxSeqNum; PicDeliInfo.HostDescMemLowAddr_Y = desc_addr.low_part; PicDeliInfo.HostDescMemHighAddr_Y = desc_addr.high_part; if (rx_pkt->uv_phy_addr) { /* Program the UV descriptor */ desc_addr.full_addr = rx_pkt->uv_phy_addr; PicDeliInfo.HostDescMemLowAddr_UV = desc_addr.low_part; PicDeliInfo.HostDescMemHighAddr_UV = desc_addr.high_part; } rx_pkt->pkt_tag = hw->rx_pkt_tag_seed + hw->rx_list_post_index; hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_y_intr; if (rx_pkt->uv_phy_addr) hw->rx_list_sts[hw->rx_list_post_index] |= rx_waiting_uv_intr; hw->rx_list_post_index = (hw->rx_list_post_index + 1) % DMA_ENGINE_CNT; spin_unlock_irqrestore(&hw->rx_lock, flags); crystalhd_dioq_add(hw->rx_actq, (void *)rx_pkt, false, rx_pkt->pkt_tag); BuffSzInDwords = (sizeof (PicDeliInfo) - sizeof(PicDeliInfo.Reserved))/4; /* -- Write the parameters in DRAM. */ spin_lock_irqsave(&hw->lock, flags); hw->pfnDevDRAMWrite(hw, hw->FleaRxPicDelAddr, BuffSzInDwords, (uint32_t*)&PicDeliInfo); hw->pfnWriteDevRegister(hw->adp, RX_POST_MAILBOX, hw->channelNum); spin_unlock_irqrestore(&hw->lock, flags); hw->RxSeqNum++; return BC_STS_SUCCESS; } BC_STATUS crystalhd_flea_hw_post_cap_buff(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *rx_pkt) { BC_STATUS sts = crystalhd_flea_hw_fire_rxdma(hw, rx_pkt); if (sts != BC_STS_SUCCESS) crystalhd_dioq_add(hw->rx_freeq, (void *)rx_pkt, false, rx_pkt->pkt_tag); hw->pfnNotifyFLLChange(hw, false); return sts; } void crystalhd_flea_start_tx_dma_engine(struct crystalhd_hw *hw, uint8_t list_id, addr_64 desc_addr) { uint32_t dma_cntrl; uint32_t first_desc_u_addr, first_desc_l_addr; TX_INPUT_BUFFER_INFO TxBuffInfo; uint32_t WrAddr=0, WrSzInDWords=0; hw->EmptyCnt--; hw->SingleThreadAppFIFOEmpty = false; /* For FLEA, first update the HW with the DMA parameters */ WrSzInDWords = (sizeof(TxBuffInfo.DramBuffAdd) + sizeof(TxBuffInfo.DramBuffSzInBytes) + sizeof(TxBuffInfo.HostXferSzInBytes))/4; /*Make the DramBuffSz as Zero skip first ULONG*/ WrAddr = hw->TxBuffInfoAddr; hw->TxFwInputBuffInfo.DramBuffAdd = TxBuffInfo.DramBuffAdd = 0; hw->TxFwInputBuffInfo.DramBuffSzInBytes = TxBuffInfo.DramBuffSzInBytes = 0; TxBuffInfo.HostXferSzInBytes = hw->TxFwInputBuffInfo.HostXferSzInBytes; hw->pfnDevDRAMWrite(hw, WrAddr, WrSzInDWords, (uint32_t *)&TxBuffInfo); if (list_id == 0) { first_desc_u_addr = BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST0; first_desc_l_addr = BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0; } else { first_desc_u_addr = BCHP_MISC1_TX_FIRST_DESC_U_ADDR_LIST1; first_desc_l_addr = BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1; } dma_cntrl = hw->pfnReadFPGARegister(hw->adp, BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS); if (!(dma_cntrl & BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK)) { dma_cntrl |= BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK; hw->pfnWriteFPGARegister(hw->adp, BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS, dma_cntrl); } hw->pfnWriteFPGARegister(hw->adp, first_desc_u_addr, desc_addr.high_part); hw->pfnWriteFPGARegister(hw->adp, first_desc_l_addr, desc_addr.low_part | 0x01); /* Be sure we set the valid bit ^^^^ */ return; } BC_STATUS crystalhd_flea_stop_tx_dma_engine(struct crystalhd_hw *hw) { struct device *dev; uint32_t dma_cntrl, cnt = 30; uint32_t l1 = 1, l2 = 1; dma_cntrl = hw->pfnReadFPGARegister(hw->adp, BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS); dev = &hw->adp->pdev->dev; dev_dbg(dev, "Stopping TX DMA Engine..\n"); if (!(dma_cntrl & BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK)) { hw->TxList0Sts = ListStsFree; hw->TxList1Sts = ListStsFree; hw->tx_list_post_index = 0; dev_dbg(dev, "Already Stopped\n"); return BC_STS_SUCCESS; } crystalhd_flea_disable_interrupts(hw); /* Issue stop to HW */ dma_cntrl &= ~BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK; hw->pfnWriteFPGARegister(hw->adp, BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS, dma_cntrl); dev_dbg(dev, "Cleared the DMA Start bit\n"); /* Poll for 3seconds (30 * 100ms) on both the lists..*/ while ((l1 || l2) && cnt) { if (l1) { l1 = hw->pfnReadFPGARegister(hw->adp, BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST0); l1 &= BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK; } if (l2) { l2 = hw->pfnReadFPGARegister(hw->adp, BCHP_MISC1_TX_FIRST_DESC_L_ADDR_LIST1); l2 &= BCHP_MISC1_TX_SW_DESC_LIST_CTRL_STS_TX_DMA_RUN_STOP_MASK; } msleep_interruptible(100); cnt--; } if (!cnt) { dev_err(dev, "Failed to stop TX DMA.. l1 %d, l2 %d\n", l1, l2); crystalhd_flea_enable_interrupts(hw); return BC_STS_ERROR; } hw->TxList0Sts = ListStsFree; hw->TxList1Sts = ListStsFree; hw->tx_list_post_index = 0; dev_dbg(dev, "stopped TX DMA..\n"); crystalhd_flea_enable_interrupts(hw); return BC_STS_SUCCESS; } static void crystalhd_flea_update_tx_done_to_fw(struct crystalhd_hw *hw) { struct device *dev; uint32_t regVal = 0; uint32_t seqNumAddr = 0; uint32_t seqVal = 0; TX_INPUT_BUFFER_INFO *pTxBuffInfo; dev = &hw->adp->pdev->dev; /* -- first update the sequence number and then update the -- scratch. */ pTxBuffInfo = (TX_INPUT_BUFFER_INFO *) (0); seqNumAddr = hw->TxBuffInfoAddr + ((uintptr_t) (&pTxBuffInfo->SeqNum)); /*Read the seqnece number */ hw->pfnDevDRAMRead(hw, seqNumAddr, 1, ®Val); seqVal = regVal; regVal++; /*Increment and Write back to same memory location. */ hw->pfnDevDRAMWrite(hw, seqNumAddr, 1, ®Val); regVal = hw->pfnReadDevRegister(hw->adp, INDICATE_TX_DONE_REG); regVal++; hw->pfnWriteDevRegister(hw->adp, INDICATE_TX_DONE_REG, regVal); dev_dbg(dev, "TxUpdate[SeqNum DRAM Addr:%x] SeqNum:%x ScratchValue:%x\n", seqNumAddr, seqVal, regVal); return; } bool crystalhd_flea_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts) { uint32_t err_mask, tmp; err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L0_DESC_TX_ABORT_ERRORS_MASK | MISC1_TX_DMA_ERROR_STATUS_TX_L0_DMA_DATA_TX_ABORT_ERRORS_MASK | MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; if (!(err_sts & err_mask)) return false; dev_err(&hw->adp->pdev->dev, "Error on Tx-L0 %x\n", err_sts); tmp = err_mask; if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK) tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L0_FIFO_FULL_ERRORS_MASK; if (tmp) { /* reset list index.*/ hw->tx_list_post_index = 0; } tmp = err_sts & err_mask; hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_TX_DMA_ERROR_STATUS, tmp); return true; } bool crystalhd_flea_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts) { uint32_t err_mask, tmp; err_mask = MISC1_TX_DMA_ERROR_STATUS_TX_L1_DESC_TX_ABORT_ERRORS_MASK | MISC1_TX_DMA_ERROR_STATUS_TX_L1_DMA_DATA_TX_ABORT_ERRORS_MASK | MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; if (!(err_sts & err_mask)) return false; dev_err(&hw->adp->pdev->dev, "Error on Tx-L1 %x\n", err_sts); tmp = err_mask; if (err_sts & MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK) tmp &= ~MISC1_TX_DMA_ERROR_STATUS_TX_L1_FIFO_FULL_ERRORS_MASK; if (tmp) { /* reset list index.*/ hw->tx_list_post_index = 0; } tmp = err_sts & err_mask; hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_TX_DMA_ERROR_STATUS, tmp); return true; } void crystalhd_flea_tx_isr(struct crystalhd_hw *hw, union FLEA_INTR_BITS_COMMON int_sts) { uint32_t err_sts; if (int_sts.L0TxDMADone) { hw->TxList0Sts &= ~TxListWaitingForIntr; crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, BC_STS_SUCCESS); } if (int_sts.L1TxDMADone) { hw->TxList1Sts &= ~TxListWaitingForIntr; crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, BC_STS_SUCCESS); } if (!(int_sts.L0TxDMAErr || int_sts.L1TxDMAErr)) /* No error mask set.. */ return; /* Handle Tx errors. */ err_sts = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_TX_DMA_ERROR_STATUS); if (crystalhd_flea_tx_list0_handler(hw, err_sts)) crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 0, BC_STS_ERROR); if (crystalhd_flea_tx_list1_handler(hw, err_sts)) crystalhd_hw_tx_req_complete(hw, hw->tx_ioq_tag_seed + 1, BC_STS_ERROR); hw->stats.tx_errors++; } bool crystalhd_flea_rx_list0_handler(struct crystalhd_hw *hw, union FLEA_INTR_BITS_COMMON int_sts, uint32_t y_err_sts, uint32_t uv_err_sts) { uint32_t tmp; enum list_sts tmp_lsts; if (!(y_err_sts & GET_Y0_ERR_MSK) && !(uv_err_sts & GET_UV0_ERR_MSK)) return false; tmp_lsts = hw->rx_list_sts[0]; /* Y0 - DMA */ tmp = y_err_sts & GET_Y0_ERR_MSK; if (int_sts.L0YRxDMADone) hw->rx_list_sts[0] &= ~rx_waiting_y_intr; if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { hw->rx_list_sts[0] &= ~rx_waiting_y_intr; tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; } if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { /* Can never happen for Flea */ printk("FLEA fifo full - impossible\n"); hw->rx_list_sts[0] &= ~rx_y_mask; hw->rx_list_sts[0] |= rx_y_error; tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; } if (tmp) { hw->rx_list_sts[0] &= ~rx_y_mask; hw->rx_list_sts[0] |= rx_y_error; hw->rx_list_post_index = 0; } /* UV0 - DMA */ tmp = uv_err_sts & GET_UV0_ERR_MSK; if (int_sts.L0UVRxDMADone) hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK) { hw->rx_list_sts[0] &= ~rx_waiting_uv_intr; tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_UNDERRUN_ERROR_MASK; } if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK) { /* Can never happen for Flea */ printk("FLEA fifo full - impossible\n"); hw->rx_list_sts[0] &= ~rx_uv_mask; hw->rx_list_sts[0] |= rx_uv_error; tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L0_FIFO_FULL_ERRORS_MASK; } if (tmp) { hw->rx_list_sts[0] &= ~rx_uv_mask; hw->rx_list_sts[0] |= rx_uv_error; hw->rx_list_post_index = 0; } if (y_err_sts & GET_Y0_ERR_MSK) { tmp = y_err_sts & GET_Y0_ERR_MSK; hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS, tmp); } if (uv_err_sts & GET_UV0_ERR_MSK) { tmp = uv_err_sts & GET_UV0_ERR_MSK; hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS, tmp); } return (tmp_lsts != hw->rx_list_sts[0]); } bool crystalhd_flea_rx_list1_handler(struct crystalhd_hw *hw, union FLEA_INTR_BITS_COMMON int_sts, uint32_t y_err_sts, uint32_t uv_err_sts) { uint32_t tmp; enum list_sts tmp_lsts; if (!(y_err_sts & GET_Y1_ERR_MSK) && !(uv_err_sts & GET_UV1_ERR_MSK)) return false; tmp_lsts = hw->rx_list_sts[1]; /* Y1 - DMA */ tmp = y_err_sts & GET_Y1_ERR_MSK; if (int_sts.L1YRxDMADone) hw->rx_list_sts[1] &= ~rx_waiting_y_intr; if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { hw->rx_list_sts[1] &= ~rx_waiting_y_intr; tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; } if (y_err_sts & MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { /* Can never happen for Flea */ printk("FLEA fifo full - impossible\n"); hw->rx_list_sts[1] &= ~rx_y_mask; hw->rx_list_sts[1] |= rx_y_error; tmp &= ~MISC1_Y_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; } if (tmp) { hw->rx_list_sts[1] &= ~rx_y_mask; hw->rx_list_sts[1] |= rx_y_error; hw->rx_list_post_index = 0; } /* UV1 - DMA */ tmp = uv_err_sts & GET_UV1_ERR_MSK; if (int_sts.L1UVRxDMADone) hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK) { hw->rx_list_sts[1] &= ~rx_waiting_uv_intr; tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_UNDERRUN_ERROR_MASK; } if (uv_err_sts & MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK) { /* Can never happen for Flea */ printk("FLEA fifo full - impossible\n"); hw->rx_list_sts[1] &= ~rx_uv_mask; hw->rx_list_sts[1] |= rx_uv_error; tmp &= ~MISC1_UV_RX_ERROR_STATUS_RX_L1_FIFO_FULL_ERRORS_MASK; } if (tmp) { hw->rx_list_sts[1] &= ~rx_uv_mask; hw->rx_list_sts[1] |= rx_uv_error; hw->rx_list_post_index = 0; } if (y_err_sts & GET_Y1_ERR_MSK) { tmp = y_err_sts & GET_Y1_ERR_MSK; hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS, tmp); } if (uv_err_sts & GET_UV1_ERR_MSK) { tmp = uv_err_sts & GET_UV1_ERR_MSK; hw->pfnWriteDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS, tmp); } return (tmp_lsts != hw->rx_list_sts[1]); } void crystalhd_flea_rx_isr(struct crystalhd_hw *hw, union FLEA_INTR_BITS_COMMON intr_sts) { unsigned long flags; uint32_t i, list_avail = 0; BC_STATUS comp_sts = BC_STS_NO_DATA; uint32_t y_err_sts, uv_err_sts, y_dn_sz = 0, uv_dn_sz = 0; bool ret = 0; if (!hw) { printk(KERN_ERR "%s: Invalid Arguments\n", __func__); return; } if (!(intr_sts.L0YRxDMADone || intr_sts.L1YRxDMADone || intr_sts.L0UVRxDMADone || intr_sts.L1UVRxDMADone || intr_sts.L0YRxDMAErr || intr_sts.L1YRxDMAErr || intr_sts.L0UVRxDMAErr || intr_sts.L1UVRxDMAErr)) return; spin_lock_irqsave(&hw->rx_lock, flags); y_err_sts = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_Y_RX_ERROR_STATUS); uv_err_sts = hw->pfnReadDevRegister(hw->adp, BCHP_MISC1_HIF_RX_ERROR_STATUS); for (i = 0; i < DMA_ENGINE_CNT; i++) { /* Update States..*/ if (i == 0) ret = crystalhd_flea_rx_list0_handler(hw, intr_sts, y_err_sts, uv_err_sts); else ret = crystalhd_flea_rx_list1_handler(hw, intr_sts, y_err_sts, uv_err_sts); if (ret) { switch (hw->rx_list_sts[i]) { case sts_free: comp_sts = BC_STS_SUCCESS; list_avail = 1; hw->stats.rx_success++; break; case rx_y_error: case rx_uv_error: case rx_sts_error: /* We got error on both or Y or uv. */ hw->stats.rx_errors++; hw->pfnHWGetDoneSize(hw, i, &y_dn_sz, &uv_dn_sz); dev_info(&hw->adp->pdev->dev, "list_index:%x " "rx[%d] rxtot[%d] Y:%x UV:%x Int:%x YDnSz:%x " "UVDnSz:%x\n", i, hw->stats.rx_errors, hw->stats.rx_errors + hw->stats.rx_success, y_err_sts, uv_err_sts, intr_sts.WholeReg, y_dn_sz, uv_dn_sz); hw->rx_list_sts[i] = sts_free; comp_sts = BC_STS_ERROR; break; default: /* Wait for completion..*/ comp_sts = BC_STS_NO_DATA; break; } } /* handle completion...*/ if (comp_sts != BC_STS_NO_DATA) { crystalhd_rx_pkt_done(hw, i, comp_sts); comp_sts = BC_STS_NO_DATA; } } spin_unlock_irqrestore(&hw->rx_lock, flags); if (list_avail) crystalhd_hw_start_capture(hw); } bool crystalhd_flea_hw_interrupt_handle(struct crystalhd_adp *adp, struct crystalhd_hw *hw) { union FLEA_INTR_BITS_COMMON IntrStsValue; bool bIntFound = false; bool bPostRxBuff = false; bool bSomeCmdDone = false; struct crystalhd_rx_dma_pkt *rx_pkt; bool rc = false; if (!adp || !hw->dev_started) return rc; IntrStsValue.WholeReg=0; IntrStsValue.WholeReg = hw->pfnReadDevRegister(hw->adp, BCHP_INTR_INTR_STATUS); if(!IntrStsValue.WholeReg) return rc; /*Not Our interrupt*/ /*If any of the bit is set we have a problem*/ if(IntrStsValue.HaltIntr || IntrStsValue.PcieTgtCaAttn || IntrStsValue.PcieTgtUrAttn) { printk("Bad HW Error in CrystalHD Driver\n"); return rc; } /* Our interrupt */ hw->stats.num_interrupts++; rc = true; /* NAREN When In Power Down state, only interrupts possible are TXFIFO and PiQ */ /* Save the state of these interrupts to process them when we resume from power down */ if(hw->FleaPowerState == FLEA_PS_LP_COMPLETE) { if(IntrStsValue.ArmMbox1Int) { hw->PwrDwnPiQIntr = true; bIntFound = true; } if(IntrStsValue.ArmMbox2Int) { hw->PwrDwnTxIntr = true; bIntFound = true; } /*Write End Of Interrupt for PCIE*/ if(bIntFound) { hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_CLR_REG, IntrStsValue.WholeReg); hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_EOI_CTRL, 1); } return (bIntFound); } /* -- Arm Mail box Zero interrupt is -- BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM1 */ if(IntrStsValue.ArmMbox0Int) { /*HWFWCmdComplete(pHWExt,IntrBmp); */ /*Set the Event and the status flag*/ if (hw->pfw_cmd_event) { hw->fwcmd_evt_sts = 1; crystalhd_set_event(hw->pfw_cmd_event); } bIntFound = true; bSomeCmdDone = true; hw->FwCmdCnt--; } /* Rx interrupts */ crystalhd_flea_rx_isr(hw, IntrStsValue); if( IntrStsValue.L0YRxDMADone || IntrStsValue.L1YRxDMADone || IntrStsValue.L0UVRxDMADone || IntrStsValue.L1UVRxDMADone || IntrStsValue.L0YRxDMAErr || IntrStsValue.L1YRxDMAErr ) { bSomeCmdDone = true; } /* Tx interrupts*/ crystalhd_flea_tx_isr(hw, IntrStsValue); /* -- Indicate the TX Done to Flea Firmware. */ if(IntrStsValue.L0TxDMADone || IntrStsValue.L1TxDMADone || IntrStsValue.L0TxDMAErr || IntrStsValue.L1TxDMAErr) { crystalhd_flea_update_tx_done_to_fw(hw); bSomeCmdDone = true; } /* -- We are doing this here because we processed the interrupts. -- We might want to change the PicQSts bitmap in any of the interrupts. -- This should be done before trying to post the next RX buffer. -- NOTE: ArmMbox1Int is BCHP_ARMCR4_BRIDGE_REG_MBOX_ARM2 */ if(IntrStsValue.ArmMbox1Int) { /*pHWExt->FleaBmpIntrCnt++; */ crystalhd_flea_update_temperature(hw); crystalhd_flea_handle_PicQSts_intr(hw); bPostRxBuff = true; bIntFound = true; } if(IntrStsValue.ArmMbox2Int) { crystalhd_flea_update_temperature(hw); crystalhd_flea_update_tx_buff_info(hw); bIntFound = true; } /*Write End Of Interrupt for PCIE*/ if(rc) { hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_INTR_CLR_REG, IntrStsValue.WholeReg); hw->pfnWriteDevRegister(hw->adp, BCHP_INTR_EOI_CTRL, 1); } /* Try to post RX Capture buffer from ISR context */ if(bPostRxBuff) { rx_pkt = crystalhd_dioq_fetch(hw->rx_freeq); if (rx_pkt) hw->pfnPostRxSideBuff(hw, rx_pkt); } if( (hw->FleaPowerState == FLEA_PS_LP_PENDING) && (bSomeCmdDone)) { /*printk("interrupt_handle: current PS:%d, bSomeCmdDone%d\n", hw->FleaPowerState,bSomeCmdDone); */ crystalhd_flea_set_next_power_state(hw, FLEA_EVT_CMD_COMP); } /* NAREN place the device in low power mode if we have not started playing video */ /*if((hw->FleaPowerState == FLEA_PS_ACTIVE) && (hw->WakeUpDecodeDone != true)) */ /*{ */ /* if((hw->ReadyListLen == 0) && (hw->FreeListLen == 0)) */ /* { */ /* crystalhd_flea_set_next_power_state(hw, FLEA_EVT_FLL_CHANGE); */ /* printk("ISR Idle\n"); */ /* } */ /*} */ return rc; } /* This function cannot be called from ISR context since it uses APIs that can sleep */ bool flea_GetPictureInfo(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt * rx_pkt, uint32_t *PicNumber, uint64_t *PicMetaData) { struct device *dev = &hw->adp->pdev->dev; uint32_t PicInfoLineNum = 0, offset = 0, size = 0; PBC_PIC_INFO_BLOCK pPicInfoLine = NULL; uint32_t tmpYBuffData; unsigned long res = 0; uint32_t widthField = 0; bool rtVal = true; void *tmpPicInfo = NULL; struct crystalhd_dio_req *dio = rx_pkt->dio_req; *PicNumber = 0; *PicMetaData = 0; if (!dio) goto getpictureinfo_err_nosem; /* if(down_interruptible(&hw->fetch_sem)) */ /* goto getpictureinfo_err_nosem; */ tmpPicInfo = kmalloc(2 * sizeof(BC_PIC_INFO_BLOCK) + 16, GFP_KERNEL); /* since copy_from_user can sleep anyway */ if(tmpPicInfo == NULL) goto getpictureinfo_err; dio->pib_va = kmalloc(32, GFP_KERNEL); /* temp buffer of 32 bytes for the rest; */ if(dio->pib_va == NULL) goto getpictureinfo_err; offset = (rx_pkt->dio_req->uinfo.y_done_sz * 4) - PIC_PIB_DATA_OFFSET_FROM_END; res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff + offset), 4); if (res != 0) goto getpictureinfo_err; PicInfoLineNum = *(uint32_t*)(dio->pib_va); if (PicInfoLineNum > 1092) { dev_err(dev, "Invalid Line Number[%x], DoneSz:0x%x Bytes\n", (int)PicInfoLineNum, rx_pkt->dio_req->uinfo.y_done_sz * 4); goto getpictureinfo_err; } offset = (rx_pkt->dio_req->uinfo.y_done_sz * 4) - PIC_WIDTH_OFFSET_FROM_END; res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff + offset), 4); if (res != 0) goto getpictureinfo_err; widthField = *(uint32_t*)(dio->pib_va); hw->PICWidth = widthField & 0x3FFFFFFF; /* bit 31 is FMT Change, bit 30 is EOS */ if (hw->PICWidth > 2048) { dev_err(dev, "Invalid width [%d]\n", hw->PICWidth); goto getpictureinfo_err; } /* calc pic info line offset */ if (dio->uinfo.b422mode) { size = 2 * sizeof(BC_PIC_INFO_BLOCK); offset = (PicInfoLineNum * hw->PICWidth * 2) + 4; } else { size = sizeof(BC_PIC_INFO_BLOCK); offset = (PicInfoLineNum * hw->PICWidth) + 4; } res = copy_from_user(tmpPicInfo, (void *)(dio->uinfo.xfr_buff+offset), size); if (res != 0) goto getpictureinfo_err; pPicInfoLine = (PBC_PIC_INFO_BLOCK)(tmpPicInfo); *PicMetaData = pPicInfoLine->timeStamp; if(widthField & PIB_EOS_DETECTED_BIT) { dev_dbg(dev, "Got EOS flag.\n"); hw->DrvEosDetected = 1; *(uint32_t *)(dio->pib_va) = 0xFFFFFFFF; res = copy_to_user((void *)(dio->uinfo.xfr_buff), dio->pib_va, 4); if (res != 0) goto getpictureinfo_err; } else { if( hw->DrvEosDetected == 1 ) hw->DrvCancelEosFlag = 1; hw->DrvEosDetected = 0; res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff), 4); if (res != 0) goto getpictureinfo_err; tmpYBuffData = *(uint32_t *)(dio->pib_va); pPicInfoLine->ycom = tmpYBuffData; res = copy_to_user((void *)(dio->uinfo.xfr_buff+offset), tmpPicInfo, size); if (res != 0) goto getpictureinfo_err; *(uint32_t *)(dio->pib_va) = PicInfoLineNum; res = copy_to_user((void *)(dio->uinfo.xfr_buff), dio->pib_va, 4); if (res != 0) goto getpictureinfo_err; } if(widthField & PIB_FORMAT_CHANGE_BIT) { rx_pkt->flags = 0; rx_pkt->flags |= COMP_FLAG_PIB_VALID | COMP_FLAG_FMT_CHANGE; rx_pkt->pib.picture_number = pPicInfoLine->picture_number; rx_pkt->pib.width = pPicInfoLine->width; rx_pkt->pib.height = pPicInfoLine->height; rx_pkt->pib.chroma_format = pPicInfoLine->chroma_format; rx_pkt->pib.pulldown = pPicInfoLine->pulldown; rx_pkt->pib.flags = pPicInfoLine->flags; rx_pkt->pib.sess_num = pPicInfoLine->sess_num; rx_pkt->pib.aspect_ratio = pPicInfoLine->aspect_ratio; rx_pkt->pib.colour_primaries = pPicInfoLine->colour_primaries; rx_pkt->pib.picture_meta_payload = pPicInfoLine->picture_meta_payload; rx_pkt->pib.frame_rate = pPicInfoLine->frame_rate; rx_pkt->pib.custom_aspect_ratio_width_height = pPicInfoLine->custom_aspect_ratio_width_height; rx_pkt->pib.n_drop = pPicInfoLine->n_drop; rx_pkt->pib.ycom = pPicInfoLine->ycom; hw->PICHeight = rx_pkt->pib.height; hw->PICWidth = rx_pkt->pib.width; hw->LastPicNo=0; hw->LastTwoPicNo=0; hw->PDRatio = 0; /* NAREN - reset PD ratio to start measuring for new clip */ hw->PauseThreshold = hw->DefaultPauseThreshold; hw->TickSpentInPD = 0; rdtscll(hw->TickCntDecodePU); dev_dbg(dev, "[FMT CH] DoneSz:0x%x, PIB:%x %x %x %x %x %x %x %x %x %x\n", rx_pkt->dio_req->uinfo.y_done_sz * 4, rx_pkt->pib.picture_number, rx_pkt->pib.aspect_ratio, rx_pkt->pib.chroma_format, rx_pkt->pib.colour_primaries, rx_pkt->pib.frame_rate, rx_pkt->pib.height, rx_pkt->pib.width, rx_pkt->pib.n_drop, rx_pkt->pib.pulldown, rx_pkt->pib.ycom); rtVal = false; } if(pPicInfoLine->flags & FLEA_DECODE_ERROR_FLAG) { *PicNumber = 0; } else { /* get pic number and flags */ if (dio->uinfo.b422mode) offset = (PicInfoLineNum * hw->PICWidth * 2); else offset = (PicInfoLineNum * hw->PICWidth); res = copy_from_user(dio->pib_va, (void *)(dio->uinfo.xfr_buff+offset), 4); if (res != 0) goto getpictureinfo_err; *PicNumber = *(uint32_t *)(dio->pib_va); } if(dio->pib_va) kfree(dio->pib_va); if(tmpPicInfo) kfree(tmpPicInfo); /* up(&hw->fetch_sem); */ return rtVal; getpictureinfo_err: /* up(&hw->fetch_sem); */ getpictureinfo_err_nosem: if(dio->pib_va) kfree(dio->pib_va); if(tmpPicInfo) kfree(tmpPicInfo); *PicNumber = 0; *PicMetaData = 0; return false; } uint32_t flea_GetRptDropParam(struct crystalhd_hw *hw, void* pRxDMAReq) { uint32_t PicNumber = 0,result = 0; uint64_t PicMetaData = 0; if(flea_GetPictureInfo(hw, (struct crystalhd_rx_dma_pkt *)pRxDMAReq, &PicNumber, &PicMetaData)) result = PicNumber; return result; } bool crystalhd_flea_notify_event(struct crystalhd_hw *hw, enum BRCM_EVENT EventCode) { switch(EventCode) { case BC_EVENT_START_CAPTURE: { crystalhd_flea_wake_up_hw(hw); break; } default: break; } return true; } crystalhd-0.0~git20110715.fdd2f19/driver/linux/Makefile.in0000644000175000017500000000263111610313111022226 0ustar andresandres# # Broadcom Crystal HD (BCM970012) controller Makefile. # # KDIR = @KERN_DIR@ INCLUDES = -I$(KDIR)/include INCLUDES += -I$(src)/../../include INCLUDES += -I$(src)/../../include/link INCLUDES += -I$(src)/../../include/flea EXTRA_CFLAGS = -D__KERNEL__ -DMODULE $(INCLUDES) $(INC) EXTRA_CFLAGS += -Wall -Wstrict-prototypes -Wno-trigraphs -Werror -O2 OBJ := crystalhd_lnx.o \ crystalhd_misc.o \ crystalhd_cmds.o \ crystalhd_hw.o \ crystalhd_linkfuncs.o \ crystalhd_fleafuncs.o \ crystalhd_flea_ddr.o PWD = $(shell pwd) obj-m := crystalhd.o crystalhd-objs := $(OBJ) all: $(MAKE) -C $(KDIR) SUBDIRS=$(PWD) modules install: if [ -e "/lib/udev/rules.d" ] ; then cp -f 20-crystalhd.rules /lib/udev/rules.d/ ; fi if [ -e "/etc/udev/rules.d" ] ; then cp -f 20-crystalhd.rules /etc/udev/rules.d/ ; fi if [ -d "/lib/modules/$(shell uname -r)/kernel/drivers/staging/crystalhd" ] ; \ then install -m 0644 crystalhd.ko /lib/modules/$(shell uname -r)/kernel/drivers/staging/crystalhd/ ; \ else \ install -d /lib/modules/$(shell uname -r)/kernel/drivers/video/broadcom ; \ install -m 0644 crystalhd.ko /lib/modules/$(shell uname -r)/kernel/drivers/video/broadcom ; \ fi /sbin/depmod -a clean: rm -f *.map *.list *.o *.ko crystalhd.mod.c $(OBJ) distclean: rm -f *.map *.list *.o *.ko crystalhd.mod.c $(OBJ) rm -f configure config.status config.log *~* rm -rf autom4te.cache rm -f Makefile rm -f Module.symvers crystalhd-0.0~git20110715.fdd2f19/driver/linux/crystalhd_fleafuncs.h0000644000175000017500000000724111610313111024357 0ustar andresandres/*************************************************************************** * Copyright (c) 2005-2009, Broadcom Corporation. * * Name: crystalhd_fleafuncs . h * * Description: * BCM70015 Linux driver hardware layer. * * HISTORY: * ********************************************************************** * This file is part of the crystalhd device driver. * * This driver is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by * the Free Software Foundation, version 2 of the License. * * This driver is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this driver. If not, see . **********************************************************************/ #ifndef _CRYSTALHD_FLEAFUNCS_H_ #define _CRYSTALHD_FLEAFUNCS_H_ #include "FleaDefs.h" #define FW_CMD_BUFF_SZ 64 bool crystalhd_flea_start_device(struct crystalhd_hw *hw); bool crystalhd_flea_stop_device(struct crystalhd_hw *hw); bool crystalhd_flea_hw_interrupt_handle(struct crystalhd_adp *adp, struct crystalhd_hw *hw); uint32_t crystalhd_flea_reg_rd(struct crystalhd_adp *adp, uint32_t reg_off); /* Done */ void crystalhd_flea_reg_wr(struct crystalhd_adp *adp, uint32_t reg_off, uint32_t val); /* Done */ bool crystalhd_flea_check_input_full(struct crystalhd_hw *hw, uint32_t needed_sz, uint32_t *empty_sz, bool b_188_byte_pkts, uint8_t *flags); BC_STATUS crystalhd_flea_mem_rd(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *rd_buff); /* Done */ BC_STATUS crystalhd_flea_mem_wr(struct crystalhd_hw *hw, uint32_t start_off, uint32_t dw_cnt, uint32_t *wr_buff); /* Done */ BC_STATUS crystalhd_flea_do_fw_cmd(struct crystalhd_hw *hw, BC_FW_CMD *fw_cmd); BC_STATUS crystalhd_flea_download_fw(struct crystalhd_hw* hw, uint8_t* buffer, uint32_t sz); void crystalhd_flea_get_dnsz(struct crystalhd_hw *hw, uint32_t list_index, uint32_t *y_dw_dnsz, uint32_t *uv_dw_dnsz); BC_STATUS crystalhd_flea_hw_pause(struct crystalhd_hw *hw, bool state); bool crystalhd_flea_peek_next_decoded_frame(struct crystalhd_hw *hw, uint64_t *meta_payload, uint32_t *picNumFlags, uint32_t PicWidth); BC_STATUS crystalhd_flea_hw_post_cap_buff(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt *rx_pkt); void crystalhd_flea_start_tx_dma_engine(struct crystalhd_hw *hw, uint8_t list_id, addr_64 desc_addr); void crystalhd_flea_stop_rx_dma_engine(struct crystalhd_hw *hw); BC_STATUS crystalhd_flea_stop_tx_dma_engine(struct crystalhd_hw *hw); bool crystalhd_flea_tx_list0_handler(struct crystalhd_hw *hw, uint32_t err_sts); bool crystalhd_flea_tx_list1_handler(struct crystalhd_hw *hw, uint32_t err_sts); void crystalhd_flea_tx_isr(struct crystalhd_hw *hw, union FLEA_INTR_BITS_COMMON int_sts); bool crystalhd_flea_rx_list0_handler(struct crystalhd_hw *hw,union FLEA_INTR_BITS_COMMON int_sts,uint32_t y_err_sts,uint32_t uv_err_sts); bool crystalhd_flea_rx_list1_handler(struct crystalhd_hw *hw,union FLEA_INTR_BITS_COMMON int_sts,uint32_t y_err_sts,uint32_t uv_err_sts); void crystalhd_flea_rx_isr(struct crystalhd_hw *hw, union FLEA_INTR_BITS_COMMON intr_sts); void crystalhd_flea_notify_fll_change(struct crystalhd_hw *hw, bool bCleanupContext); bool crystalhd_flea_notify_event(struct crystalhd_hw *hw, enum BRCM_EVENT EventCode); bool flea_GetPictureInfo(struct crystalhd_hw *hw, struct crystalhd_rx_dma_pkt * rx_pkt, uint32_t *PicNumber, uint64_t *PicMetaData); #endif